A3982SLBTR-T - Allegro Microsystems

Translator

OUT2A

SENSE2

VBB2

OUT2B

ENABLE

PGND

CP1

CP2

VCP

VREG

MS1

Charge

Pump

Reg

OSC

& Control Logic

OUT1A

SENSE1

VBB1

OUT1B

DIR

RESET

PGND

REF

STEP

VDD

ROSC

26184.28C

Description

The A3982 is a complete stepper motor driver with built-

in translator for easy operation. It is designed to operate

bipolar stepper motors in full- and half-step modes, with an

output drive capacity of up to 35 V and ±2 A. The A3982

includes a fixed off-time current regulator which has the

ability to operate in Slow or Mixed decay modes.

The translator is the key to the easy implementation of the

A3982. Simply inputting one pulse on the STEP input drives

the motor one step. There are no phase sequence tables, high

frequency control lines, or complex interfaces to program.

The A3982 interface is an ideal fit for applications where a

complex microprocessor is unavailable or is overburdened.

The chopping control in the A3982 automatically selects

the current decay mode (Slow or Mixed). When a signal

occurs at the STEP input pin, the A3982 determines if

that step results in a higher or lower current in each of the

motor phases. If the change is to a higher current, then the

decay mode is set to Slow decay. If the change is to a lower

current, then the current decay is set to Mixed (set initially

to a fast decay for a period amounting to 31.25% of the

Features and Benefits

▪ Low RDS(on) outputs

▪ Automatic current decay mode detection/selection

▪ Mixed and Slow current decay modes

▪ Synchronous rectification for low power dissipation

▪ Internal UVLO and thermal shutdown circuitry

▪ Crossover-current protection

DMOS Stepper Motor Driver with Translator

Continued on the next page…

Package: 24 pin SOICW with internally

fused leads (suffix LB)

Pin-out Diagram

Not to scale

A3982

DMOS Stepper Motor Driver with Translator

A3982

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

fixed off-time, then to a slow decay for the remainder of the

off-time). This current decay control scheme results in reduced

audible motor noise, increased step accuracy, and reduced power

dissipation.

Internal synchronous rectification control circuitry is provided to

improve power dissipation during PWM operation.

Internal circuit protection includes: thermal shutdown with

hysteresis, undervoltage lockout (UVLO), and crossover-current

protection. Special power-on sequencing is not required.

The A3982 is supplied in a 24-pin wide-body SOIC

(package LB) with internally-fused power ground leads for

enhanced thermal dissipation. It is lead (Pb) free, with 100%

matte tin plated leadframe.

Description (continued)

Absolute Maximum Ratings

Characteristic Symbol Notes Rating Units

Load Supply Voltage VBB 35 V

Logic Input Voltage VIN –0.3 to 7 V

Sense Voltage VSENSE 0.5 V

Reference Voltage VREF 4V

Output Current IOUT

Output current rating may be limited by duty cycle,

ambient temperature, and heat sinking. Under

any set of conditions, do not exceed the specified

current rating or a junction temperature of 150°C.

±2 A

Operating Ambient Temperature TARange S –20 to 85 ºC

Maximum Junction Temperature TJ(max) 150 ºC

Storage Temperature Tstg –55 to 150 ºC

Selection Guide

Part Number Packing* Package

A3982SLB-T 31 pieces per tube 24-pin Wide SOIC with pins 6 and 7, and 18

and 19, fused internally

A3982SLBTR-T 1000 pieces per reel

*Contact Allegro for additional packing options

DMOS Stepper Motor Driver with Translator

A3982

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Functional Block Diagram

SENSE1

SENSE2

VREG

VCP

CP2

Control

Logic

DAC

VDD

PWM Latch

Blanking

Mixed Decay

DAC

STEP

DIR

RESET

MS1

PWM Latch

Blanking

Mixed Decay

Current

Regulator

CP1

Charge

Pump

RS2

RS1

VBB1

OUT1A

OUT1B

VBB2

OUT2A

OUT2B

0.1 μF

VREF

Translator

Gate

Drive DMOS Full Bridge

DMOS Full Bridge

0.1 μF

0.22 μF

OSC

ROSC

REF

ENABLE

DMOS Stepper Motor Driver with Translator

A3982

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

ELECTRICAL CHARACTERISTICS1 at TA = 25°C, VBB = 35 V (unless otherwise noted)

1Negative current is defined as coming out of (sourcing from) the specified device pin.

2Typical data are for initial design estimations only, and assume optimum manufacturing and application conditions. Performance may vary for

individual units, within the specified maximum and minimum limits.

3errI = (ITrip – IProg

) ⁄ IProg

, where IProg = %ITripMAX× I TripMAX.

Characteristics Symbol Test Conditions Min. Typ.2Max. Units

Output Drivers

Load Supply Voltage Range VBB Operating 8 – 35 V

Logic Supply Voltage Range VDD Operating 3.0 – 5.5 V

Output On Resistance RDSON

Source Driver, IOUT = –1.5 A – 0.370 0.460 

Sink Driver, IOUT = 1.5 A – 0.330 0.380 

Body Diode Forward Voltage VF

Source Diode, IF = –1.5 A – – 1.2 V

Sink Diode, IF = 1.5 A – – 1.2 V

Motor Supply Current IBB

fPWM < 50 kHz – – 4 mA

Operating, outputs disabled – – 2 mA

Logic Supply Current IDD

fPWM < 50 kHz – – 8 mA

Outputs off – – 5 mA

Control Logic

Logic Input Voltage VIN(1) VDD×0.7 ––V

VIN(0) ––

VDD×0.3 V

Logic Input Current IIN(1) VIN = VDD×0.7 –20 <1.0 20 A

IIN(0) VIN = VDD×0.3 –20 <1.0 20 A

Input Hysteresis VHYS(IN) 150 300 500 mV

Blank Time tBLANK 0.7 1 1.3 s

Fixed Off-Time tOFF

OSC > 3 V 20 30 40 s

ROSC = 25 k23 30 37 s

Reference Input Voltage Range VREF 0–4V

Reference Input Current IREF –3 0 3 A

Current Trip-Level Error3errI

VREF = 2 V, %ITripMAX = 70.71% – – ±5 %

VREF = 2 V, %ITripMAX = 100.00% – – ±5 %

Crossover Dead Time tDT 100 475 800 ns

Protection

Thermal Shutdown Temperature TJ– 165 – °C

Thermal Shutdown Hysteresis TJHYS –15–°C

UVLO Enable Threshold UVLO VDD rising 2.35 2.7 3 V

UVLO Hysteresis UVHYS 0.05 0.10 – V

DMOS Stepper Motor Driver with Translator

A3982

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

THERMAL CHARACTERISTICS

Characteristic Symbol Test Conditions* Value Units

Package Thermal Resistance RθJA

One-layer PCB, one-sided with copper limited to solder pads 77 ºC/W

One-layer PCB, two-sided with copper limited to solder pads and

3.57 in.2 of copper area on each side, connected to PGND pins 45 ºC/W

Four-layer PCB, based on JEDEC standard 35 ºC/W

*Additional thermal information available on Allegro Web site.

Temperature, T

(°C)

Power Dissipation, P

(W)

0.50

1.50

2.00

2.50

3.00

3.50

4.00

1.00

20 40 60 80 100 120 140 160

Power Dissipation versus Ambient Temperature

RθJA =35ºC/W

RθJA = 45 ºC/W

RθJA =77ºC

DMOS Stepper Motor Driver with Translator

A3982

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Figure 1. Logic Interface Timing Diagram

STEP

MS1,

RESET, or DIR

Table 1. Stepping Resolution Truth Table

MS1 Step Resolution Excitation Mode

L Full Step 2 Phase

H Half Step 1-2 Phase

Time Duration Symbol Typ. Unit

STEP minimum, HIGH pulse width tA1s

STEP minimum, LOW pulse width tB1s

Setup time, input change to STEP tC200 ns

Hold time, input change to STEP tD200 ns

DMOS Stepper Motor Driver with Translator

A3982

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Functional Description

Device Operation. The A3982 is a complete stepper

motor driver with a built-in translator for easy operation

with minimal control lines. It is designed to operate bipolar

stepper motors in full- and half-step modes. The currents in

each of the two output full-bridges and all of the N-channel

DMOS FETs are regulated with fixed off-time PMW (pulse

width modulated) control circuitry. At each step, the current

for each full-bridge is set by the value of its external current-

sense resistor (RS1 or RS2), a reference voltage (VREF), and

the output voltage of its DAC (which in turn is controlled by

the output of the translator).

At power-on or reset, the translator sets the DACs and the

phase current polarity to the initial Home state (shown in

figures 2 and 3), and the current regulator to Mixed Decay

Mode for both phases. When a step command signal occurs

on the STEP input, the translator automatically sequences

the DACs to the next level and current polarity. (See table 2

for the current-level sequence.) The step resolution is set by

input MS1, as shown in table 1.

When stepping, if the new output levels of the DACs are

lower than their previous output levels, then the decay mode

for the active full-bridge is set to Mixed. If the new output

levels of the DACs are higher than or equal to their previous

levels, then the decay mode for the active full-bridge is set to

Slow. This automatic current decay selection improves step-

ping performance by reducing the distortion of the current

waveform that results from the back EMF of the motor.

RESET Input (RESET). The RESET input sets the

translator to a predefined Home state (shown in figures 2

and 3), and turns off all of the DMOS outputs. All STEP

inputs are ignored until the RESET input is set to high.

Step Input (STEP). A low-to-high transition on the STEP

input sequences the translator and advances the motor one

increment. The translator controls the input to the DACs and

the direction of current flow in each winding. The size of the

increment is determined by input MS1, as shown in table 1.

Direction Input (DIR). This determines the direction of

rotation of the motor. When low, the direction will be clock-

wise and when high, counterclockwise. Changes to this input

do not take effect until the next STEP rising edge.

Internal PWM Current Control. Each full-bridge is

controlled by a fixed off-time PWM current control circuit

that limits the load current to a desired value, ITRIP

. Ini-

tially, a diagonal pair of source and sink DMOS outputs are

enabled and current flows through the motor winding and

the current sense resistor, RSx. When the voltage across RSx

equals the DAC output voltage, the current sense compara-

tor resets the PWM latch. The latch then turns off either the

source DMOS FET (when in Slow Decay Mode) or the sink

and source DMOS FETs (when in Mixed Decay Mode).

The maximum value of current limiting is set by the selec-

tion of RSx and the voltage at the VREF pin. The transcon-

ductance function is approximated by the maximum value of

current limiting, ITripMAX (A), which is set by

ITripMAX = VREF / ( 8 × R S)

where RS is the resistance of the sense resistor (Ω) and VREF

is the input voltage on the REF pin (V).

The DAC output reduces the VREF output to the current

sense comparator in precise steps, such that

Itrip = (%ITripMAX / 100) × ITripMAX

(See table 2 for %ITripMAX at each step.)

It is critical that the maximum rating (0.5 V) on the SENSE1

and SENSE2 pins is not exceeded.

Fixed Off-Time. The internal PWM current control cir-

cuitry uses a one-shot circuit to control the duration of time

that the DMOS FETs remain off. The one shot off-time, tOFF,

Functional Description

DMOS Stepper Motor Driver with Translator

A3982

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

is determined by the selection of an external resistor con-

nected from the ROSC timing pin to ground. If the ROSC

pin is tied to an external voltage > 3 V, then tOFF defaults to

30 μs. The ROSC pin can be safely connected to the VDD

pin for this purpose. The value of tOFF (μs) is approximately

tOFF ≈ ROSC ⁄ 825

Blanking. This function blanks the output of the current

sense comparators when the outputs are switched by the

internal current control circuitry. The comparator outputs

are blanked to prevent false overcurrent detection due to

reverse recovery currents of the clamp diodes, and switching

transients related to the capacitance of the load. The blank

time, tBLANK (μs), is approximately

tBLANK ≈ 1 μs

Charge Pump (CP1 and CP2). The charge pump is

used to generate a gate supply greater than that of VBB

for driving the source-side DMOS gates. A 0.1 μF ceramic

capacitor, should be connected between CP1 and CP2. In

addition, a 0.1 μF ceramic capacitor is required between

VCP and VBB, to act as a reservoir for operating the

high-side DMOS gates.

VREG (VREG). This internally-generated voltage is

used to operate the sink-side DMOS outputs. The VREG

pin must be decoupled with a 0.22 μF ceramic capacitor to

ground. VREG is internally monitored. In the case of a fault

condition, the DMOS outputs of the A3982 are disabled.

Enable Input (ENABLE). This input turns on or off all

of the DMOS outputs. When set to a logic high, the outputs

are disabled. When set to a logic low, the internal control

enables the outputs as required. The translator inputs STEP,

DIR, and MS1, as well as the internal sequencing logic, all

remain active, independent of the ENABLE input state.

Shutdown. In the event of a fault, overtemperature

(excess TJ) or an undervoltage (on VCP), the DMOS out-

puts of the A3982 are disabled until the fault condition is

removed. At power-on, the UVLO (undervoltage lockout)

circuit disables the DMOS outputs and resets the translator

to the Home state.

Mixed Decay Operation. The bridge can operate in

Mixed Decay Mode, depending on the step sequence, as

shown in figures 3 thru 5. As the trip point is reached, the

A3982 initially goes into a fast decay mode for 31.25%

of the off-time, tOFF. After that, it switches to Slow Decay

Mode for the remainder of tOFF.

Synchronous Rectification. When a PWM-off cycle

is triggered by an internal fixed–off-time cycle, load current

recirculates according to the decay mode selected by the

control logic. This synchronous rectification feature turns on

the appropriate FETs during current decay, and effectively

shorts out the body diodes with the low DMOS RDSON. This

reduces power dissipation significantly, and can eliminate

the need for external Schottky diodes in many applications.

Turning off synchronous rectification prevents the reversal of

the load current when a zero-current level is detected.

DMOS Stepper Motor Driver with Translator

A3982

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Home Microstep Position

100.00

70.71

–70.71

0.00

–100.00

100.00

70.71

–70.71

0.00

–100.00

Phase 2

OUT2A

Direction = H

(%)

Phase 1

OUT1A

Direction = H

(%)

STEP

Slow

Mixed

Slow

Mixed

Slow

Mixed

Slow

Mixed

Slow

Mixed

Slow

Phase 2

OUT2A

Direction = H

(%)

Phase 1

OUT1A

Direction = H

(%)

STEP

Home Microstep Position

100.00

70.71

–70.71

0.00

–100.00

100.00

70.71

–70.71

0.00

–100.00

Slow

Figure 3. Decay Modes for Half-Step IncrementsFigure 2. Decay Mode for Full-Step Increments

Table 2. Step Sequencing Settings

Home step position at Step Angle 45º; DIR = H

Full

Step

Half

Step

Phase 1

Current

[% ItripMax]

(%)

Phase 2

Current

[% ItripMax]

(%)

Step

Angle

(º)

1 100.00 0.00 0.0

1 2 70.71 70.71 45.0

3 0.00 100.00 90.0

2 4 –70.71 70.71 135.0

5 –100.00 0.00 180.0

3 6 –70.71 –70.71 225.0

7 0.00 –100.00 270.0

4 8 70.71 –70.71 315.0

DMOS Stepper Motor Driver with Translator

A3982

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Pin List Table

Name Description Number

OUT2A DMOS Full Bridge 2 Output A 1

SENSE2 Sense resistor for Bridge 2 2

VBB2 Load supply 3

OUT2B DMOS Full Bridge 2 Output B 4

ENABLE Logic input 5

PGND Power ground 6

PGND Power ground 7

CP1 Charge pump capacitor 1 8

CP2 Charge pump capacitor 2 9

VCP Reservoir capacitor 10

VREG Regulator decoupling 11

MS1 Logic input 12

RESET Logic input 13

ROSC Timing set 14

VDD Logic supply 15

STEP Logic input 16

REF Current trip reference voltage input 17

PGND Power ground 18

PGND Power ground 19

DIR Logic input 20

1OUT1B DMOS Full Bridge 1 Output B 21

VBB1 Load supply 22

SENSE1 Sense resistor for Bridge 1 23

OUT1A DMOS Full Bridge 1 Output A 24

DMOS Stepper Motor Driver with Translator

A3982

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

LB Package, 24-Pin Wide Body SOIC

The products described here are manufactured under one or more U.S. patents or U.S. patents pending.

Allegro MicroSystems, Inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per-

mit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the

information being relied upon is current.

Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the

failure of that life support device or system, or to affect the safety or effectiveness of that device or system.

The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, Allegro MicroSystems, Inc. assumes no re spon si bil i ty for its use;

nor for any in fringe ment of patents or other rights of third parties which may result from its use.

For the latest version of this document, visit our website:

www.allegromicro.com

1.27

0.25

BReference pad layout (reference IPC SOIC127P1030X265-24M)

All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary

to meet application process requirements and PCB layout tolerances

0.20 ±0.10

0.41 ±0.10

2.20

0.65

9.60

1.27

15.40±0.20

2.65 MAX

10.30±0.33

7.50±0.10

SEATING

PLANE

C0.10

24X

For reference only

Pins 6 and 7, and 18 and 19 internally fused

Dimensions in millimeters

(Reference JEDEC MS-013 AD)

Dimensions exclusive of mold flash, gate burrs, and dambar protrusions

Exact case and lead configuration at supplier discretion within limits shown

ATerminal #1 mark area

GAUGE PLANE

SEATING PLANE PCB Layout Reference View

4° ±4

0.27 +0.07

–0.06

0.84 +0.44

–0.43