1
FEATURES APPLICATIONS
DESCRIPTION
TYPICAL APPLICATION CIRCUIT
1
2
3
4
10
9
8
7
VBST
DRVH
SW
V5IN
PGOOD
TRIP
EN
VFB
TPS51218
5 6DRVLRF
GND
VIN
VOUT
VOUT_GND
EN
V5IN
UDG-09064
TPS51218
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............................................................................................................................................................... SLUS935A – MAY 2009 – REVISED JUNE 2009
HIGH PERFORMANCE, SINGLE SYNCHRONOUS STEP-DOWNCONTROLLER FOR NOTEBOOK POWER SUPPLY
•Notebook Computers2
•Wide Input Voltage Range: 3 V to 28 V
•I/O Supplies•Output Voltage Range: 0.7 V to 2.6 V
•System Power Supplies•Wide Output Load Range: 0 to 20A+•Built-in 0.5% 0.7 V Reference•D-CAP™ Mode with 100-ns Load Step
The TPS51218 is a small-sized single buck controllerResponse
with adaptive on-time D-CAP™ mode. The device is•Adaptive On Time Control Architecture With 4
suitable for low output voltage, high current, PCSelectable Frequency Setting
system power rail and similar point-of-load (POL)•4700 ppm/ ° C R
DS(on)
Current Sensing
power supply in digital consumer products. A smallpackage with minimal pin-count saves space on the•Internal 1-ms Voltage Servo Softstart
PCB, while a dedicated EN pin and pre-set frequency•Pre-Charged Start-up Capability
selections minimize design effort required for new•Built in Output Discharge
designs. The skip-mode at light load condition, stronggate drivers and low-side FET R
DS(on)
current sensing•Power Good Output
supports low-loss and high efficiency, over a broad•Integrated Boost Switch
load range. The conversion input voltage which is the•Built-in OVP/UVP/OCP
high-side FET drain voltage ranges from 3 V to 28 Vand the output voltage ranges from 0.7 V to 2.6 V.•Thermal Shutdown (Non-latch)
The device requires an external 5-V supply. The•SON-10 (DSC) Package
TPS51218 is available in a 10-pin SON packagespecified from – 40 ° C to 85 ° C.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2D-CAP is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2009, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
ABSOLUTE MAXIMUM RATINGS
(1)
DISSIPATION RATINGS
TPS51218
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
ORDERING DEVICE OUTPUT MINIMUMT
A
PACKAGE PINSNUMBER SUPPLY QUANTITY
TPS51218DSCR 10 Tape and reel 3000– 40 ° C to 85 ° C Plastic SON PowerPAD
TPS51218DSCT 10 Mini reel 250
over operating free-air temperature range (unless otherwise noted)
VALUE UNIT
VBST – 0.3 to 37VBST
(3)
– 0.3 to 7Input voltage range
(2)
VSW – 5 to 30V5IN, EN, TRIP, VFB, RF – 0.3 to 7DRVH – 5 to 37DRVH
(3)
– 0.3 to 7Output voltage range
(2)
VDRVL – 0.5 to 7PGOOD – 0.3 to 7T
J
Junction temperature range 150 ° CT
STG
Storage temperature range – 55 to 150 ° C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratingsonly and functional operation of the device at these or any other conditions beyond those indicated under recommended operatingconditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) All voltage values are with respect to the network ground terminal unless otherwise noted.(3) Voltage values are with respect to the SW terminal.
2-oz. trace and copper pad with solder.
PACKAGE T
A
< 25 ° C DERATING FACTOR T
A
= 85 ° CPOWER RATING ABOVE T
A
= 25 ° C POWER RATING
10-pin DSC
(1)
1.54 W 15 mW/ ° C 0.62 W
(1) Enhanced thermal conductance by thermal vias is used beneath thermal pad as shown in Land Pattern information.
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RECOMMENDED OPERATING CONDITIONS
TPS51218
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............................................................................................................................................................... SLUS935A – MAY 2009 – REVISED JUNE 2009
over operating free-air temperature range (unless otherwise noted)
MIN TYP MAX UNIT
Supply voltage V5IN 4.5 6.5 VVBST – 0.1 34.5SW – 1 28Input voltage range SW
(1)
– 4 28 VVBST
(2)
– 0.1 6.5EN, TRIP, VFB, RF – 0.1 6.5DRVH – 1 34.5DRVH
(1)
– 4 34.5Output voltage range DRVH
(2)
– 0.1 6.5 VDRVL – 0.3 6.5PGOOD – 0.1 6.5T
A
Operating free-air temperature – 40 85 ° C
(1) This voltage should be applied for less than 30% of the repetitive period.(2) Voltage values are with respect to the SW terminal.
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ELECTRICAL CHARACTERISTICS
TPS51218
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over recommended free-air temperature range, V5IN=5V. (Unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
V5IN current, T
A
= 25 ° C, No Load,I
V5IN
V5IN supply current 320 500 µAV
EN
= 5 V, V
VFB
= 0.735 VI
V5INSDN
V5IN shutdown current V5IN current, T
A
= 25 ° C, No Load, V
EN
= 0 V 1 µA
INTERNAL REFERENCE VOLTAGE
VFB voltage, CCM condition
(1)
0.7000 VT
A
= 25 ° C, skip mode 0.7005 0.7040 0.7075V
VFB
VFB regulation voltage
T
A
= 0 ° C to 85 ° C, skip mode 0.6984 0.7040 0.7096 VT
A
= – 40 ° C to 85 ° C, skip mode 0.6970 0.7040 0.7110I
VFB
VFB input current V
VFB
= 0.735 V, T
A
= 25 ° C, skip mode 0.01 0.2 µA
OUTPUT DISCHARGE
Output discharge current fromI
Dischg
V
EN
= 0 V, V
SW
= 0.5 V 5 13 mASW pin
OUTPUT DRIVERS
Source, I
DRVH
= – 50 mA 1.5 3R
DRVH
DRVH resistance
Sink, I
DRVH
= 50 mA 0.7 1.8
ΩSource, I
DRVL
= – 50 mA 1.0 2.2R
DRVL
DRVL resistance
Sink, I
DRVL
= 50 mA 0.5 1.2DRVH-off to DRVL-on 7 17 30t
D
Dead time nsDRVL-off to DRVH-on 10 22 35
BOOT STRAP SWITCH
V
FBST
Forward voltage V
V5IN-VBST
, I
F
= 10 mA, T
A
= 25 ° C 0.1 0.2 VI
VBSTLK
VBST leakage current V
VBST
= 34.5 V, V
SW
= 28 V, T
A
= 25 ° C 0.01 1.5 µA
DUTY AND FREQUENCY CONTROL
t
OFF(min)
Minimum off-time T
A
= 25 ° C 150 260 400
nsV
IN
= 28 V, V
OUT
= 0.7 V, R
RF
= 39k Ω,t
ON(min)
Minimum on-time 79T
A
= 25 ° C
(1)
SOFTSTART
t
ss
Internal SS time From V
EN
= high to V
OUT
= 95% 1 ms
POWERGOOD
PG in from lower 92.5% 95% 97.5%V
THPG
PG threshold PG in from higher 107.5% 110% 112.5%PG hysteresis 2.5% 5% 7.5%I
PGMAX
PG sink current V
PGOOD
= 0.5 V 3 6 mAt
PGDEL
PG delay Delay for PG in 0.8 1 1.2 ms
LOGIC THRESHOLD AND SETTING CONDITIONS
Enable 1.8V
EN
EN voltage threshold VDisable 0.5I
EN
EN input current V
EN
= 5V 1.0 µAR
RF
= 470 k Ω, T
A
= 25 ° C
(2)
266 290 314R
RF
= 200 k Ω, T
A
= 25 ° C
(2)
312 340 368f
SW
Switching frequency kHzR
RF
= 100 k Ω, T
A
= 25 ° C
(2)
349 380 411R
RF
= 39 k Ω, T
A
= 25 ° C
(2)
395 430 465CCM 1.8V
RF
CCM setting voltage VAuto-skip 0.5
(1) Ensured by design. Not production tested.(2) Not production tested. Test condition is V
IN
= 8 V, V
OUT
= 1.1 V, I
OUT
= 10 A using application circuit shown in Figure 21 .
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............................................................................................................................................................... SLUS935A – MAY 2009 – REVISED JUNE 2009
ELECTRICAL CHARACTERISTICS (continued)over recommended free-air temperature range, V5IN=5V. (Unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
PROTECTION: CURRENT SENSE
I
TRIP
TRIP source current V
TRIP
= 1V, T
A
= 25 ° C 9 10 11 µATRIP current temperatureTC
ITRIP
On the basis of 25 ° C 4700 ppm/ ° Ccoeffficient
Current limit threshold settingV
TRIP
V
TRIP-GND
Voltage 0.2 3 Vrange
V
TRIP
= 3.0 V 355 375 395V
OCL
Current limit threshold V
TRIP
= 1.6 V 185 200 215 mVV
TRIP
= 0.2 V 17 25 33V
TRIP
= 3.0 V – 395 – 375 – 355V
OCLN
Negative current limit threshold V
TRIP
= 1.6 V – 215 – 200 – 185 mVV
TRIP
= 0.2 V – 33 – 25 – 17Positive 3 15Auto zero cross adjustableV
AZCADJ
mVrange
Negative – 15 – 3
PROTECTION: UVP AND OVP
V
OVP
OVP trip threshold OVP detect 115% 120% 125%t
OVPDEL
OVP propagation delay time 50-mV overdrive 1 µsV
UVP
Output UVP trip threshold UVP detect 65% 70% 75%Output UVP propagation delayt
UVPDEL
0.8 1 1.2 mstimet
UVPEN
Output UVP enable delay time From Enable to UVP workable 1.0 1.2 1.4 ms
UVLO
Wake up 4.20 4.38 4.50V
UVV5IN
V5IN UVLO threshold VShutdown 3.7 3.93 4.1
THERMAL SHUTDOWN
Shutdown temperature
(3)
145T
SDN
Thermal shutdown threshold ° CHysteresis
(3)
10
(3) Ensured by design. Not production tested.
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DEVICE INFORMATION
1
2
3
4
5
10
9
8
7
6
PGOOD
TRIP
EN
VFB
RF
VBST
DRVH
SW
V5IN
DRVL
TPS51218DSC
GND
DSC PACKAGE
(TOP VIEW)
TRIP
OCL
V
V8
=
TPS51218
SLUS935A – MAY 2009 – REVISED JUNE 2009 ...............................................................................................................................................................
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Thermal pad is used as an active terminal of GND.
PIN FUNCTIONS
PIN
I/O DESCRIPTIONNAME NO.
High-side MOSFET driver output. The SW node referenced floating driver. The gate drive voltage isDRVH 9 O
defined by the voltage across VBST to SW node bootstrap flying capacitorSynchronous MOSFET driver output. The GND referenced driver. The gate drive voltage is defined byDRVL 6 O
V5IN voltage.EN 3 I SMPS enable pin. Short to GND to disable the device.ThermalGND I GroundPad
Power Good window comparator open drain output. Pull up with resistor to 5 V or appropriate signalPGOOD 1 O voltage. Continuous current capability is 1 mA. PGOOD goes high 1 ms after VFB becomes withinspecified limits. Power bad, or the terminal goes low, after a 2- µs delay.Switching frequency selection. Connect a resistance to select switching frequency as shown in Table 1 .
The switching frequency is detected and stored into internal registers during startup. This pin also controlsRF 5 I Auto-skip or forced CCM selection.Pull down to GND with resistor : Auto-SkipConnect to PGOOD with resistor: forced CCM after PGOOD becomes high.Switch node. A high-side MOSFET gate drive return. Also used for on time generation and outputSW 8 I
discharge.
OCL detection threshold setting pin. 10 µA at room temperature, 4700 ppm/ ° C current is sourced and setthe OCL trip voltage as follows.
TRIP 2 I
(0.2 V ≤V
TRIP
≤3 V)
V5IN 7 I 5 V +30%/ – 10% power supply input.Supply input for high-side MOSFET driver (bootstrap terminal). Connect a flying capacitor from this pin toVBST 10 I
the SW pin. Internally connected to V5IN via bootstrap MOSFET switch.VFB 4 I SMPS feedback input. Connect the feedback resistor divider.
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GND
SW
TPS51218
OCP
ZC
XCON
RF
FCCM
VBST
V5IN
PWM
VFB
TRIP
Auto-skip/FCCM
+
+
Delay
0.7 V +10/15%
0.7 V –5/10%
PGOOD
Control Logic
UDG-09065
10 mA
+
+
0.7 V –30%
0.7 V +20%
+
+
EN
Ramp Comp
Enable/SS Control
+
+
+
+
0.7 V
x(-1/8)
x(1/8)
Frequency
Setting
Detector
DRVH
DRVL
tON
One-
Shot
Auto-skip
UV
OV
TPS51218
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FUNCTIONAL BLOCK DIAGRAM
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TYPICAL CHARACTERISTICS
–50
200
0
050 100 150
600
400
1000
800
VV5IN = 5 V
VEN = 5 V
VVFB = 0.735 V
No Load
TJ– Junction Temperature – °C
IV5IN – V5IN Supply Current – mA
–50
0
0 50 100 150
TJ– Junction Temperature – °C
4
12
8
20
16
IV5INSDN – V5IN Shutdown Current – mA
10
6
18
14
2
VV5IN = 5 V
VEN = 0 V
No Load
–50
0
0 50 100 150
TJ– Junction Temperature – °C
150
VOVP /VUVP – OVP/UVP Trip Threshold – %
50
100
OVP
VV5IN = 5 V
UVP
–50 0 50 100 150
TJ– Junction Temperature – °C
VV5IN = 5 V
VTRIP = 1 V
0
4
12
8
20
16
ITRIP – Current Sense Current – mA
10
6
18
14
2
TPS51218
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V5IN SUPPLY CURRENT V5IN SHUTDOWN CURRENTvs vsJUNCTION TEMPERATURE JUNCTION TEMPERATURE
Figure 1. Figure 2.
OVP/UVP THRESHOLD CURRENT SENSE CURRENT (I
TRIP
)vs vsJUNCTION TEMPERATURE JUNCTION TEMPERATURE
Figure 3. Figure 4.
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6
200
10 14 18 22
VIN – Input Voltage – V
250
500
fSW – Switching Frequency – kHz
350
300
450
400
IO= 10 A
Auto-Skip
8 12 16 20
RRF = 100 kW
RRF = 39 kW
RRF = 200 kW
RRF = 470 kW
0.001
0.1
0.01 100
IOUT – Output Current – A
1
1000
fSW – Switching Frequency – kHz
10
100
VIN = 12 V
RRF = 470 kW
0.1 1 10
FCCM
Auto-Skip
0.001
0.1
0.01 100
1
1000
fSW – Switching Frequency – kHz
10
100
VIN = 12 V
RRF = 200 kW
0.1 1 10
FCCM
Auto-Skip
IOUT – Output Current – A
0.001
0.1
0.01 100
1
1000
fSW – Switching Frequency – kHz
10
100
VIN = 12 V
RRF = 100 kW
0.1 1 10
FCCM
Auto-Skip
IOUT – Output Current – A
TPS51218
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............................................................................................................................................................... SLUS935A – MAY 2009 – REVISED JUNE 2009
TYPICAL CHARACTERISTICS (continued)
SWITCHING FREQUENCY SWITCHING FREQUENCYvs vsINPUT VOLTAGE OUTPUT CURRENT
Figure 5. Figure 6.
SWITCHING FREQUENCY SWITCHING FREQUENCYvs vsOUTPUT CURRENT OUTPUT CURRENT
Figure 7. Figure 8.
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0.001
0.1
0.01 100
1
1000
fSW – Switching Frequency – kHz
10
100
VIN = 12 V
RRF = 39 kW
0.1 1 10
FCCM
Auto-Skip
IOUT – Output Current – A
0.001 0.01 100
VIN = 12 V
RRF = 470 kW
0.1 1 10
IOUT – Output Current – A
MODE
Auto-Skip
FCCM
1.08
1.09
1.12
VOUT – Output Voltage – V
1.10
1.11
h– Efficiency – %
0.001 0.01 1000.1 1 10
IOUT – Output Current – A
0
100
50
80
70
60
RRF = 470 kW
VOUT = 1.1 V
90
Auto-Skip
FCCM
20
30
10
40
VIN (V)
8
12
20
1.08
1.09
1.12
VOUT – Output Voltage – V
1.10
1.11
Auto-Skip
RRF = 470 kW
6 8 16 18 22
VIN – Input Voltage – V
201410 12
IOUT = 20 A
IOUT = 0 A
TPS51218
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TYPICAL CHARACTERISTICS (continued)
SWITCHING FREQUENCY OUTPUT VOLTAGEvs vsOUTPUT CURRENT OUTPUT CURRENT
Figure 9. Figure 10.
OUTPUT VOLTAGE 1.1-V EFFICIENCYvs vsINPUT VOLTAGE OUTPUT CURRENT
Figure 11. Figure 12.
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............................................................................................................................................................... SLUS935A – MAY 2009 – REVISED JUNE 2009
TYPICAL CHARACTERISTICS (continued)
Figure 13. 1.1-V Start-Up Waveform Figure 14. Pre-Biased Start-Up WaveformX X
X X
X X
Figure 15. 1.1-V Soft-Stop Waveform Figure 16. 1.1-V Load Transient ResponseX X
X X
X X
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APPLICATION INFORMATION
GENERAL DESCRIPTION
ENABLE AND SOFT START
ADAPTIVE ON-TIME D-CAP™ CONTROL
TPS51218
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The TPS51218 is a high-efficiency, single channel, synchronous buck regulator controller suitable for low outputvoltage point-of-load applications in notebook computers and similar digital consumer applications. The devicefeatures proprietary D-CAP™ mode control combined with adaptive on-time architecture. This combination isideal for building modern low duty ratio, ultra-fast load step response DC-DC converters. The output voltageranges from 0.7 V to 2.6 V. The conversion input voltage range is from 3 V to 28 V. The D-CAP™ mode uses theESR of the output capacitor(s) to sense current information. An advantage of this control scheme is that it doesnot require an external phase compensation network, helping the designer with ease-of-use and realizing lowexternal component count configuration. The switching frequency is selectable from four preset values using aresistor connected from the RF pin to ground. Adaptive on-time control tracks the preset switching frequencyover a wide range of input and output voltages, while it increases the switching frequency at step-up of load.
The RF pin also serves in selecting between auto-skip mode and forced continuous conduction mode for lightload conditions. The strong gate drivers of the TPS51218 allow low R
DS(on)
FETs for high current applications.
When the EN pin voltage rises above the enable threshold, (typically 1.2 V) the controller enters its start-upsequence. The first 250 µs calibrates the switching frequency setting resistance attached at RF to GND andstores the switching frequency code in internal registers. A voltage of 0.1 V is applied to RF for measurement.Switching is inhibited during this phase. In the second phase, internal DAC starts ramping up the referencevoltage from 0 V to 0.7 V. This ramping time is 750 µs. Smooth and constant ramp up of the output voltage ismaintained during start up regardless of load current. Connect a 1-k Ωresistor in series with the EN pin to provideprotection.
TPS51218 does not have a dedicated oscillator that determines switching frequency. However, the device runswith pseudo-constant frequency by feed-forwarding the input and output voltages into its on-time one-shot timer.The adaptive on-time control adjusts the on-time to be inversely proportional to the input voltage and proportionalto the output voltage (t
ON
∝V
OUT
/ V
IN
). This makes the switching frequency fairly constant in steady stateconditions over wide input voltage range. The switching frequency is selectable from four preset values by aresistor connected to RF as shown in Table 1 . (Leaving the resistance open sets the switching frequency to thelowest value, 290 kHz. However, it is recommended to apply one of the resistances on the table in anyapplication designs.)
Table 1. Resistor and Switching Frequency
SWITCHINGRESISTANCE (R
RF
)
FREQUENCY (f
SW
)(k Ω)
(kHz)
470 290200 340100 38039 430
The off-time is modulated by a PWM comparator. The VFB node voltage (the mid point of resistor divider) iscompared to the internal 0.7-V reference voltage added with a ramp signal. When both signals match, the PWMcomparator asserts the set signal to terminate the off-time (turn off the low-side MOSFET and turn on high-sideMOSFET). The set signal becomes valid if the inductor current level is below OCP threshold, otherwise theoff-time is extended until the current level to become below the threshold.
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SMALL SIGNAL MODEL
R1
R2
Voltage Divider
+
VFB
+
0.7 V
PWM Control
Logic
and
Driver
VIN
L
ESR
CO
VC
RL
IIND IOUT
UDG-09063
IC
Switching Modulator
Output
Capacitor
DRVH
DRVL
VOUT
O
1
H(s) s ESR C
=´ ´
(1)
fSW
0
O
1
f2 ESR C 4
= £
p´ ´
(2)
RAMP SIGNAL
TPS51218
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............................................................................................................................................................... SLUS935A – MAY 2009 – REVISED JUNE 2009
From small-signal loop analysis, a buck converter using D-CAP™ mode can be simplified as shown in Figure 17 .
Figure 17. Simplified Modulator Model
The output voltage is compared with internal reference voltage (ramp signal is ignored here for simplicity). ThePWM comparator determines the timing to turn on the high-side MOSFET. The gain and speed of thecomparator can be assumed high enough to keep the voltage at the beginning of each on cycle substantiallyconstant.
For loop stability, the 0-dB frequency, ƒ
0
, defined in Equation 2 need to be lower than 1/4 of the switchingfrequency.
According to Equation 2 , the loop stability of D-CAP™ mode modulator is mainly determined by the capacitor'schemistry. For example, specialty polymer capacitors (SP-CAP) have C
O
on the order of several 100 µF andESR in range of 10 m Ω. These makes f
0
on the order of 100 kHz or less and the loop is stable. However,ceramic capacitors have an ƒ
0
of more than 700 kHz, which is not suitable for this modulator.
The TPS51218 adds a ramp signal to the 0.7-V reference in order to improve its jitter performance. As describedin the previous section, the feedback voltage is compared with the reference information to keep the outputvoltage in regulation. By adding a small ramp signal to the reference, the S/N ratio at the onset of a newswitching cycle is improved. Therefore the operation becomes less jittery and more stable. The ramp signal iscontrolled to start with – 7 mV at the beginning of ON-cycle and becomes 0 mV at the end of OFF-cycle incontinuous conduction steady state.
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LIGHT LOAD CONDITION IN AUTO-SKIP OPERATION
( ) f
IN OUT OUT
O LL SW IN
(V V ) V
1
I2 L V
- ´
= ´
´ ´
(3)
ADAPTIVE ZERO CROSSING
FORCED CONTINUOUS CONDUCTION MODE
OUTPUT DISCHARGE CONTROL
LOW-SIDE DRIVER
HIGH-SIDE DRIVER
TPS51218
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With RF pin pulled down to low via R
RF
, the TPS51218 automatically reduces switching frequency at light loadconditions to maintain high efficiency. As the output current decreases from heavy load condition, the inductorcurrent is also reduced and eventually comes to the point that its rippled valley touches zero level, which is theboundary between continuous conduction and discontinuous conduction modes. The rectifying MOSFET isturned off when this zero inductor current is detected. As the load current further decreases, the converter runs into discontinuous conduction mode. The on-time is kept almost the same as it was in the continuous conductionmode so that it takes longer time to discharge the output capacitor with smaller load current to the level of thereference voltage. The transition point to the light load operation I
O(LL)
(i.e., the threshold between continuous anddiscontinuous conduction mode) can be calculated in Equation 3 .
where
•f
SW
is the PWM switching frequency
Switching frequency versus output current in the light load condition is a function of L, V
IN
and V
OUT
, but itdecreases almost proportional to the output current from the I
O(LL)
given in Equation 3 . For example, it is 58 kHzat I
O(LL)
/5 if the frequency setting is 290 kHz.
The TPS51218 has an adaptive zero crossing circuit which performs optimization of the zero inductor currentdetection at skip mode operation. This function pursues ideal low-side MOSFET turning off timing andcompensates inherent offset voltage of the ZC comparator and delay time of the ZC detection circuit. It preventsSW-node swing-up caused by too late detection and minimizes diode conduction period caused by too earlydetection. As a result, better light load efficiency is delivered.
When the RF pin is tied high, the controller keeps continuous conduction mode (CCM) in light load condition. Inthis mode, switching frequency is kept almost constant over the entire load range which is suitable forapplications need tight control of the switching frequency at a cost of lower efficiency. To set the switchingfrequency to be the same as Auto-skip mode, it is recommended to connect R
RF
to PGOOD. In this way, RF istied low prior to soft-start operation to set frequency and tied high after powergood indicates high.
When EN is low, the TPS51218 discharges the output capacitor using internal MOSFET connected between SWand GND while high-side and low-side MOSFETs are kept off. The current capability of this MOSFET is limited todischarge slowly.
The low-side driver is designed to drive high current low R
DS(on)
N-channel MOSFET(s). The drive capability isrepresented by its internal resistance, which are 1.0 Ωfor V5IN to DRVL and 0.5 Ωfor DRVL to GND. A dead timeto prevent shoot through is internally generated between high-side MOSFET off to low-side MOSFET on, andlow-side MOSFET off to high-side MOSFET on. 5-V bias voltage is delivered from V5IN supply. Theinstantaneous drive current is supplied by an input capacitor connected between V5IN and GND. The averagedrive current is equal to the gate charge at Vgs=5V times switching frequency. This gate drive current as well asthe high-side gate drive current times 5V makes the driving power which need to be dissipated from TPS51218package.
The high-side driver is designed to drive high current, low R
DS(on)
N-channel MOSFET(s). When configured as afloating driver, 5 V of bias voltage is delivered from V5IN supply. The average drive current is also equal to thegate charge at V
GS
=5V times switching frequency. The instantaneous drive current is supplied by the flyingcapacitor between VBST and SW pins. The drive capability is represented by its internal resistance, which are1.5 Ωfor VBST to DRVH and 0.7 Ωfor DRVH to SW.
14 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): TPS51218
POWER-GOOD
CURRENT SENSE AND OVER CURRENT PROTECTION
TRIP TRIP TRIP
V (mV) R (k ) I ( A)= W ´ m
(4)
( )
f
IND ripple IN OUT OUT
TRIP TRIP
OCP
DS(on) DS(on) SW IN
I(V V ) V
V V 1
I8 R 2 8 R 2 L V
æ ö - ´
ç ÷
= + = + ´
ç ÷
´ ´ ´ ´
è ø
(5)
OVER/UNDER VOLTAGE PROTECTION
UVLO PROTECTION
THERMAL SHUTDOWN
TPS51218
www.ti.com
............................................................................................................................................................... SLUS935A – MAY 2009 – REVISED JUNE 2009
The TPS51218 has powergood output that indicates high when switcher output is within the target. Thepowergood function is activated after soft-start has finished. If the output voltage becomes within +10%/ – 5% ofthe target value, internal comparators detect power-good state and the power-good signal becomes high after a1-ms internal delay. If the output voltage goes outside of +15%/ – 10% of the target value, the powergood signalbecomes low after a 2- µs internal delay. The powergood output is an open-drain output and must be pulled upexternally.
TPS51218 has cycle-by-cycle overcurrent limiting control. The inductor current is monitored during the OFF stateand the controller keeps the OFF state during the inductor current is larger than the overcurrent trip level. Toprovide both good accuracy and cost effective solution, the TPS51218 supports temperature compensatedMOSFET R
DS(on)
sensing. The TRIP pin should be connected to GND through the trip voltage setting resistor,R
TRIP
. The TRIP terminal sources I
TRIP
current, which is 10 µA typically at room temperature, and the trip level isset to the OCL trip voltage V
TRIP
as shown in Equation 4 . Note that V
TRIP
is limited up to approximately 3 Vinternally.
The inductor current is monitored by the voltage between GND pad and SW pin so that the SW pin should beconnected to the drain terminal of the low-side MOSFET properly. I
TRIP
has 4700ppm/ ° C temperature slope tocompensate the temperature dependency of the R
DS(on)
. GND is used as the positive current sensing node sothat GND should be connected to the proper current sensing device, i.e. the source terminal of the low-sideMOSFET.
As the comparison is done during the OFF state, V
TRIP
sets valley level of the inductor current. Thus, the loadcurrent at overcurrent threshold, I
OCP
, can be calculated in Equation 5
In an overcurrent condition, the current to the load exceeds the current to the output capacitor thus the outputvoltage tends to fall down. Eventually, it crosses the undervoltage protection threshold and shuts down thecontroller.
When the device is operating in the forced continuous conduction mode, the negative current limit (NCL) protectsthe external FET from carrying too much current. The NCL detect threshold is set as the same absolute value aspositive OCL but negative polarity. Please be noted the threshold still represents the valley value of the inductorcurrent.
TPS51218 monitors a resistor divided feedback voltage to detect over and undervoltage. When the feedbackvoltage becomes higher than 120% of the target voltage, the OVP comparator output goes high and the circuitlatches as the high-side MOSFET driver OFF and the low-side MOSFET driver ON.
When the feedback voltage becomes lower than 70% of the target voltage, the UVP comparator output goeshigh and an internal UVP delay counter begins counting. After a 1-ms delay, TPS51218 latches OFF bothhigh-side and low-side MOSFETs drivers. This function is enabled after 1.2 ms following EN has become high.
TPS51218 has V5IN undervoltage lockout protection (UVLO). When the V5IN voltage is lower than UVLOthreshold voltage, the switch mode power supply shuts off. This is non-latch protection.
TPS51218 monitors the die temperature. If the temperature exceeds the threshold value (typically 145C), theTPS51218 is shut off. This is non-latch protection.
Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Link(s): TPS51218
EXTERNAL COMPONENTS SELECTION
( )
()
( ) ( )
( )
()
( )
f f
OUT OUT OUT OUT
IN max IN max
IND(ripple) SW SW
IN max OUT max IN max
V V V V V V
1 3
LI V I V
- ´ - ´
= ´ = ´
´ ´
(6)
( )
()
( )
f
OUT OUT
IN max
TRIP
IND(peak )
DS(on) SW IN max
V V V
V1
I8 R L V
- ´
= + ´
´ ´
(7)
( ) ff
OUT SW SW
IND(ripple)
V 10 mV 1 D 10 mV L L
ESR 0.7 V I 0.7 V 70
´ ´ - ´ ´
é ù é ù ´
ë û ë û
= = = W
é ù
ë û
´
é ù é ù
ë û ë û
(8)
tSW
t – Time
0
VVFB – Feedback Voltage – mV
10
tSW x (1-D)
VRIPPLE(FB)
TPS51218
SLUS935A – MAY 2009 – REVISED JUNE 2009 ...............................................................................................................................................................
www.ti.com
Selecting external components is simple in D-CAP™ mode.
1. Choose the inductor.
The inductance value should be determined to give the ripple current of approximately 1/4 to 1/2 of maximumoutput current. Larger ripple current increases output ripple voltage and improves S/N ratio and helps stableoperation.
The inductor also needs to have low DCR to achieve good efficiency, as well as enough room above peakinductor current before saturation. The peak inductor current can be estimated in Equation 7 .
2. Choose the output capacitor(s).
Organic semiconductor capacitor(s) or specialty polymer capacitor(s) are recommended. For loop stability,capacitance and ESR should satisfy Equation 2 . For jitter performance, Equation 8 is a good starting point todetermine ESR.
where
•D is the duty ratio•the output ripple down slope rate is 10 mV/t
SW
in terms of VFB terminal voltage as shown in Figure 18•t
SW
is the switching period
Figure 18. Ripple Voltage Down Slope
16 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): TPS51218
IND(ripple)
OUT
I ESR
V 0.7
2
R1 R2
0.7
´
æ ö
- -
ç ÷
ç ÷
è ø
= ´
(9)
LAYOUT CONSIDERATIONS
UDG-09066
TPS51218
DRVL
4
VIN
1mF
VFB
V5IN
VOUT
2
TRIP
5
RF
# 2
# 1
# 3
5
6
Thermal Pad
GND
TPS51218
www.ti.com
............................................................................................................................................................... SLUS935A – MAY 2009 – REVISED JUNE 2009
3. Determine the value of R1 and R2.
The output voltage is programmed by the voltage-divider resistor, R1 and R2, shown in Figure 17 . R1 isconnected between the VFB pin and the output, and R2 is connected between the VFB pin and GND. Typicaldesigns begin with the selection of an R2 value between 10 k Ωand 20 k Ω. Determine R1 using Equation 9 .
Figure 19. Ground System of DC/DC Converter Using the TPS51218
Certain points must be considered before starting a layout work using the TPS51218.•Inductor, V
IN
capacitor(s), V
OUT
capacitor(s) and MOSFETs are the power components and should be placedon one side of the PCB (solder side). Other small signal components should be placed on another side(component side). At least one inner plane should be inserted, connected to ground, in order to shield andisolate the small signal traces from noisy power lines.•All sensitive analog traces and components such as VFB, PGOOD, TRIP and RF should be placed awayfrom high-voltage switching nodes such as SW, DRVL, DRVH or VBST to avoid coupling. Use internallayer(s) as ground plane(s) and shield feedback trace from power traces and components.•The DC/DC converter has several high-current loops. The area of these loops should be minimized in order tosuppress generating switching noise.– The most important loop to minimize the area of is the path from the V
IN
capacitor(s) through the high andlow-side MOSFETs, and back to the capacitor(s) through ground. Connect the negative node of the V
INcapacitor(s) and the source of the low-side MOSFET at ground as close as possible. (Refer to loop #1 ofFigure 19 )– The second important loop is the path from the low-side MOSFET through inductor and V
OUT
capacitor(s),and back to source of the low-side MOSFET through ground. Connect source of the low-side MOSFETand negative node of V
OUT
capacitor(s) at ground as close as possible. (Refer to loop #2 of Figure 19 )– The third important loop is of gate driving system for the low-side MOSFET. To turn on the low-sideMOSFET, high current flows from V5IN capacitor through gate driver and the low-side MOSFET, and back
Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Link(s): TPS51218
LAYOUT CONSIDERATIONS TO REMOTE SENSING
UDG-09067
TPS51218
Thermal Pad
DRVL
4 5
VIN
1mF
VFB
V5IN
6
VOUT
2
TRIP
5
RF
0.1 mF
100 W
VTT_SENSE
VSS_SENSE
GND
TPS51218
SLUS935A – MAY 2009 – REVISED JUNE 2009 ...............................................................................................................................................................
www.ti.com
to negative node of the capacitor through ground. To turn off the low-side MOSFET, high current flowsfrom gate of the low-side MOSFET through the gate driver and GND pad of the device, and back tosource of the low-side MOSFET through ground. Connect negative node of V5IN capacitor, source of thelow-side MOSFET and GND pad of the device at ground as close as possible. (Refer to loop #3 ofFigure 19 )•Since the TPS51218 controls output voltage referring to voltage across V
OUT
capacitor, the top-side resistor ofthe voltage divider should be connected to the positive node of V
OUT
capacitor. In a same manner bothbottom side resistor and GND pad of the device should be connected to the negative node of V
OUT
capacitor.The trace from these resistors to the VFB pin should be short and thin. Place on the component side andavoid via(s) between these resistors and the device.•Connect the overcurrent setting resistors from TRIP pin to ground and make the connections as close aspossible to the device. The trace from TRIP pin to resistor and from resistor to ground should avoid couplingto a high-voltage switching node.•Connect the frequency setting resistor from RF pin to ground, or to the PGOOD pin, and make theconnections as close as possible to the device. The trace from the RF pin to the resistor and from the resistorto ground should avoid coupling to a high-voltage switching node.•Connections from gate drivers to the respective gate of the high-side or the low-side MOSFET should be asshort as possible to reduce stray inductance. Use 0.65 mm (25 mils) or wider trace and via(s) of at least0.5 mm (20 mils) diameter along this trace.•The PCB trace defined as switch node, which connects to source of high-side MOSFET, drain of low-sideMOSFET and high-voltage side of the inductor, should be as short and wide as possible.
Figure 20. Remote Sensing of Output Voltage Using the TPS51218
•Make a Kelvin connection to the load device.•Run the feedback signals as a differential pair to the device. The distance of these parallel pair should be asshort as possible.•Run the lines in a quiet layer. Isolate them from noisy signals by a voltage or ground plane.
18 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): TPS51218
TPS51218 APPLICATION CIRCUITS
1
2
3
4
10
9
8
7
VBST
DRVH
SW
V5IN
PGOOD
TRIP
EN
VFB
U1
TPS51218
5 6DRVLRF GND C2
1mF
C1
0.1 mF
C4
330 mF x 4
C3
10 mF x 4
L1
0.45 mH
R6
100 kW
R3
1 kW
R1
5.6 kW
VIN
8 V
to
20 V
VOUT
1.1 V
18 A
VOUT_GND
EN
V5IN
4.5 V
to
6.5 V
R5
30 kW
R2
10 kW
UDG-09068
R4(A)
470 kW
Q2
FDMS8670AS
Q1
FDMS8680
Q3
FDMS8670AS
R7
3.3 W
1
2
3
4
10
9
8
7
VBST
DRVH
SW
V5IN
PGOOD
TRIP
EN
VFB
U1
TPS51218
5 6DRVLRF GND C2
1mF
C1
0.1 mF
C4
330 mF x 4
C3
10 mF x 4
L1
0.45 mH
R6
100 kW
R3
1 kW
R1
5.6 kW
VIN
8 V
to
20 V
VOUT
1.1 V
18 A
VOUT_GND
EN
V5IN
4.5 V
to
6.5 V
R5
30 kW
R2
10 kW
UDG-09069
Q2
FDMS8670AS
Q1
FDMS8680
Q3
FDMS8670AS
R4(A)
470 kW
R7
3.3 W
TPS51218
www.ti.com
............................................................................................................................................................... SLUS935A – MAY 2009 – REVISED JUNE 2009
Figure 21. 1.1-V/18-A Auto-Skip Mode
A. See Table 1 for resistor/frequency values.
Figure 22. 1.1-V/18-A Forced Continuous Conduction Mode
Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Link(s): TPS51218
TPS51218
SLUS935A – MAY 2009 – REVISED JUNE 2009 ...............................................................................................................................................................
www.ti.com
Table 2. 1.1-V, 18-A, 290-kHz Application List of Materials
REFERENCE
QTY SPECIFICATION MANUFACTURER PART NUMBERDESIGNATOR
C3 1 4 × 10 µF, 25 V Taiyo Yuden TMK325BJ106MMC4 1 4 × 330 µF, 2 V, 12 m ΩPanasonic EEFCX0D331XRL1 1 0.45 µH, 25 A, 1.1 m ΩPanasonic ETQP4LR45XFCQ1 1 30 V, 35 A, 8.5 m ΩFairchild FDMS8680Q2, Q3 2 30 V, 42 A, 3.5 m ΩFairchild FDMS8670AS
20 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): TPS51218
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS51218DSCR SON DSC 10 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS51218DSCR SON DSC 10 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS51218DSCT SON DSC 10 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS51218DSCT SON DSC 10 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 19-Aug-2011
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS51218DSCR SON DSC 10 3000 346.0 346.0 29.0
TPS51218DSCR SON DSC 10 3000 346.0 346.0 29.0
TPS51218DSCT SON DSC 10 250 210.0 185.0 35.0
TPS51218DSCT SON DSC 10 250 190.5 212.7 31.8
PACKAGE MATERIALS INFORMATION
www.ti.com 19-Aug-2011
Pack Materials-Page 2
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