www.latticesemi.com 1DS1020_23.5
ispMACH
4000V/B/C/Z Family
3.3 V/2.5 V/1.8 V In-System Programmable
SuperFAST
High Density PLDs
April 2016 Data Sheet DS1020
®
TM
© 2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
Features
High Performance
•f
MAX = 400 MHz maximum operating frequency
•t
PD = 2.5 ns propagation delay
• Up to four global clock pins with programmable
clock polarity control
• Up to 80 PTs per output
Ease of Design
• Enhanced macrocells with individual clock,
reset, preset and clock enable controls
• Up to four global OE controls
• Individual local OE control per I/O pin
• Excellent First-Time-FitTM and refit
• Fast path, SpeedLockingTM Path, and wide-PT
path
• Wide input gating (36 input logic blocks) for fast
counters, state machines and address decoders
Zero Power (ispMACH 4000Z) and Low
Power (ispMACH 4000V/B/C)
• Typical static current 10 µA (4032Z)
• Typical static current 1.3 mA (4000C)
• 1.8 V core low dynamic power
• ispMACH 4000Z operational down to 1.6 V VCC
Broad Device Offering
• Multiple temperature range support
– Commercial: 0 to 90 °C junction (Tj)
– Industrial: –40 to 105 °C junction (Tj)
– Extended: –40 to 130 °C junction (Tj)
• For AEC-Q100 compliant devices, refer to
LA-ispMACH 4000V/Z Automotive Data Sheet
Easy System Integration
• Superior solution for power sensitive consumer
applications
• Operation with 3.3 V, 2.5 V or 1.8 V LVCMOS I/O
• Operation with 3.3 V (4000V), 2.5 V (4000B) or
1.8 V (4000C/Z) supplies
• 5 V tolerant I/O for LVCMOS 3.3, LVTTL, and
PCI interfaces
• Hot-socketing
• Open-drain capability
• Input pull-up, pull-down or bus-keeper
• Programmable output slew rate
• 3.3 V PCI compatible
• IEEE 1149.1 boundary scan testable
• 3.3 V/2.5 V/1.8 V In-System Programmable
(ISP™) using IEEE 1532 compliant interface
• I/O pins with fast setup path
• Lead-free package options
Table 1. ispMACH 4000V/B/C Family Selection Guide
ispMACH
4032V/B/C
ispMACH
4064V/B/C
ispMACH
4128V/B/C
ispMACH
4256V/B/C
ispMACH
4384V/B/C
ispMACH
4512V/B/C
Macrocells 32 64 128 256 384 512
I/O + Dedicated Inputs 30+2/32+4 30+2/32+4/
64+10
64+10/92+4/
96+4
64+10/96+14/
128+4/160+4
128+4/192+4 128+4/208+4
tPD (ns) 2.5 2.5 2.7 3.0 3.5 3.5
tS (ns) 1.8 1.8 1.8 2.0 2.0 2.0
tCO (ns) 2.2 2.2 2.7 2.7 2.7 2.7
fMAX (MHz) 400 400 333 322 322 322
Supply Voltages (V) 3.3/2.5/1.8V 3.3/2.5/1.8V 3.3/2.5/1.8V 3.3/2.5/1.8V 3.3/2.5/1.8V 3.3/2.5/1.8V
Pins/Package 44 TQFP4
48 TQFP444 TQFP4
48 TQFP4
100 TQFP 100 TQFP
128 TQFP
144 TQFP1
100 TQFP
144 TQFP1
176 TQFP
256 ftBGA2/
fpBGA2, 3
176 TQFP
256 ftBGA/
fpBGA3
176 TQFP
256 ftBGA/
fpBGA3
1. 3.3 V (4000V) only.
2. 128-I/O and 160-I/O configurations.
3. Use 256 ftBGA package for all new designs. Refer to PCN#14A-07 for 256 fpBGA package discontinuance.
4. 1.0 mm thickness.
ispMACH 4000V/B/C/Z Family Data Sheet
2
Table 2. ispMACH 4000Z Family Selection Guide
ispMACH 4000 Introduction
The high performance ispMACH 4000 family from Lattice offers a SuperFAST CPLD solution. The family is a blend
of Lattice’s two most popular architectures: the ispLSI® 2000 and ispMACH 4A. Retaining the best of both families,
the ispMACH 4000 architecture focuses on significant innovations to combine the highest performance with low
power in a flexible CPLD family.
The ispMACH 4000 combines high speed and low power with the flexibility needed for ease of design. With its
robust Global Routing Pool and Output Routing Pool, this family delivers excellent First-Time-Fit, timing predictabil-
ity, routing, pin-out retention and density migration.
The ispMACH 4000 family offers densities ranging from 32 to 512 macrocells. There are multiple density-I/O com-
binations in Thin Quad Flat Pack (TQFP), Chip Scale BGA (csBGA) and Fine Pitch Thin BGA (ftBGA) packages
ranging from 44 to 256 pins/balls. Table 1 shows the macrocell, package and I/O options, along with other key
parameters.
The ispMACH 4000 family has enhanced system integration capabilities. It supports 3.3 V (4000V), 2.5 V (4000B)
and 1.8 V (4000C/Z) supply voltages and 3.3 V, 2.5 V and 1.8 V interface voltages. Additionally, inputs can be
safely driven up to 5.5 V when an I/O bank is configured for 3.3 V operation, making this family 5 V tolerant. The
ispMACH 4000 also offers enhanced I/O features such as slew rate control, PCI compatibility, bus-keeper latches,
pull-up resistors, pull-down resistors, open drain outputs and hot socketing. The ispMACH 4000 family members
are 3.3 V/2.5 V/1.8 V in-system programmable through the IEEE Standard 1532 interface. IEEE Standard 1149.1
boundary scan testing capability also allows product testing on automated test equipment. The 1532 interface sig-
nals TCK, TMS, TDI and TDO are referenced to VCC (logic core).
Overview
The ispMACH 4000 devices consist of multiple 36-input, 16-macrocell Generic Logic Blocks (GLBs) interconnected
by a Global Routing Pool (GRP). Output Routing Pools (ORPs) connect the GLBs to the I/O Blocks (IOBs), which
contain multiple I/O cells. This architecture is shown in Figure 1.
ispMACH 4032ZC ispMACH 4064ZC ispMACH 4128ZC ispMACH 4256ZC
Macrocells 32 64 128 256
I/O + Dedicated Inputs 32+4/32+4 32+4/32+12/
64+10/64+10
64+10/96+4 64+10/96+6/
128+4
tPD (ns) 3.5 3.7 4.2 4.5
tS (ns) 2.2 2.5 2.7 2.9
tCO (ns) 3.0 3.2 3.5 3.8
fMAX (MHz) 267 250 220 200
Supply Voltage (V) 1.8 1.8 1.8 1.8
Max. Standby Icc (µA) 20 25 35 55
Pins/Package 48 TQFP
56 csBGA
48 TQFP
56 csBGA
100 TQFP
132 csBGA
100 TQFP
132csBGA
100 TQFP
132 csBGA
176 TQFP
