General Description
The MAX6974/MAX6975 precision current-sinking,
24-output PWM LED drivers drive red, green, and blue
LEDs for full-color graphic message boards and video
displays. Each output has an individual 12-bit (MAX6974)
or 14-bit (MAX6975) PWM-intensity (hue) control and
7-bit (MAX6974) or 5-bit (MAX6975) global PWM intensity
(luminance) control. The MAX6974/MAX6975 feature a
high-speed, fully buffered cascadable serial interface,
open-circuit LED fault detection circuitry, as well as a
watchdog timer.
The driver has three banks of eight outputs, with each
bank intended to drive a different color in RGB applica-
tions. The full-scale current for each bank of eight out-
puts is adjustable from 6mA to 30mA in 256 steps
(0.3125% per step) to calibrate each color.
The MAX6974/MAX6975 can optionally multiplex by
using outputs MUX0 and MUX1, which each drive an
external pnp transistor. Multiplexing doubles the
MAX6974/MAX6975 drive capability to 48 LEDs.
The MAX6974/MAX6975 operate from a 3.0V to 3.6V
power supply. The LED power supply can range from
3V to 7V. The LED drivers require only 0.8V headroom
above the LEDs’ forward-voltage drop. Using a sepa-
rate LED supply voltage for each LED minimizes power
consumption.
The serial interface uses differential signaling for the
high-speed clock and data signals to reduce EMI and
improve signal integrity. The MAX6974/MAX6975 buffer
all interface signals to simplify cascading devices in
modules that use a large number of drivers.
An internal watchdog timer, when enabled, automatically
clears the pixel-data registers and blanks the display if
any of the signal inputs fail to toggle within 40ms.
The MAX6974/MAX6975 are available in 40-pin TQFN
packages and operate over the -40°C to +125°C
temperature range.
Refer to the MAX6972/MAX6973 data sheet for a
16-output, 11mA to 55mA software-compatible device.
Applications
LED Video Display Panels
LED Message Boards
Variable Message Signs (VMS)
Signs
Graphic Panels
Features
♦24 LED Current Sink Outputs (Three Banks of
Eight Outputs)
♦48 LED Drive Option When Multiplexing
♦33MHz Clock Supports Up to 63 Frames per
Second of Video
♦Constant Output Current Calibration from 6mA to
30mA in 256 Steps
♦EZCascade™ Interface Simplifies Multiple Driver
Cascading Without External Buffers
♦12-Bit or 14-Bit Individual PWM LED Intensity
Controls
♦7-Bit or 5-Bit Panel PWM-Intensity Control
♦+3V to +7V LED Power Supply
♦+3.0V to +3.6V Logic Supply
♦Open-Circuit LED Fault Detection
♦Optional Watchdog Timer Blanks Display if
Interface Fails
♦Standard -40°C to +125°C Operating Temperature
Range
MAX6974/MAX6975
24-Output PWM LED Drivers
for Message Boards
________________________________________________________________
Maxim Integrated Products
1
19-0555; Rev 2; 10/07
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
EVALUATION KIT
AVAILABLE
Typical Operating Circuit appears at the end of data sheet.
*
EP = Exposed paddle.
+
Denotes a lead-free package.
MAX6974ATL/
MAX6975ATL
TQFN-EP
TOP VIEW
35
36
34
33
12
11
13
14
12
+
B5
4567
2728
EP*
*EP = EXPOSED PADDLE.
2930 26 24 23 22
B4
B3
G2
G1
G0
R7
3
25
37
B2 R6
38
39
40
B1
B0
VDD
R5
R4
R3
B6
32
15
G3
B7
31
16
17
18
19
20 G4
8910
21
AGND
R2
R1
R0
I.C.
LOADI
DIN-
DIN+
CLKI-
CLKI+
MUX0
CLKO+
CLK0-
DOUT+
DOUT-
LOADO
VDD
G7
G6
G5
MUX1
Pin Configuration
Ordering Information
PART
TEMP RANGE
PIN-
PACKAGE
PKG
CODE
MAX6974ATL+ -40°C to +125°C 40 TQFN-EP*
T4066-3
MAX6975ATL+ -40°C to +125°C 40 TQFN-EP*
T4066-3
EZCascade is a trademark of Maxim Integrated Products, Inc.
MAX6974/MAX6975
24-Output PWM LED Drivers
for Message Boards
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
(All voltages with respect to GND.)
VDD ........................................................................-0.3V to +4.0V
R0–R7, G0–G7, B0–B7, MUX0, and MUX1 ...........-0.3V to +8.0V
All Other Pins..............................................-0.3V to (VDD + 0.3V)
Continuous Power Dissipation (TA= +70°C)
40-Pin TQFN (derate 37mW/°C over +70°C) .............2963mW
Operating Temperature Range .........................-40°C to +125°C
Junction Temperature......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Operating Supply Voltage VDD 3.0 3.6 V
LEDs Anode Voltage
(R0–R7, G0–G7, B0–B7, MUX0,
and MUX1)
VO7V
fCLKI = 0Hz; CLKO_, DOUT_ loaded 200Ω;
calibration DACs set to 0x01 28 52
fCLKI = 0Hz; CLKO_, DOUT_ loaded 200Ω;
calibration DACs set to 0xFF 51 72
Supply Current IDD
fCLKI = 32MHz; CLKO_, DOUT_ loaded 200Ω;
calibration DACs set to 0xFF 54 77
mA
Input High Voltage LOADI VIHC 0.7
x VDD V
Input Low Voltage LOADI VILC 0.3
x VDD V
Differential Input Voltage Range
CLKI_, DIN_ VID ±0.15 ±1.20 V
Common-Mode Input Voltage
CLKI_, DIN_ VCM | V
I D / 2| 2.4 V
Differential Input High Threshold VDIFFTH 8 100 mV
Differential Input Low Threshold VDIFFTL -100 -8 mV
Differential Output Voltage
CLKO_, DOUT_ VOD Termination 200Ω at receiver _+ and _- inputs ±190 ±550 mV
Differential Output Offset
CLKO_, DOUT_ VOS Termination 200Ω at receiver _+ and _- inputs 1.125 1.25 1.375 V
Input Leakage Current
CLKI_, DIN_, LOADI IIH, IIL -1 +1 µA
Input Capacitance
CLKI_, DIN_, LOADI 10 pF
Output Low Voltage LOADO VOLC ISINK = 5mA 0.05 0.25 V
Output High Voltage LOADO VOHC ISOURCE = 5mA VDD
- 0.5
VDD
- 0.2 V
ELECTRICAL CHARACTERISTICS
(VDD = 3.0V to 3.6V, TA= TMIN to TMAX, unless otherwise noted. Typical values are at VDD = 3.3V, TA= +85°C.) (Note 1)
MAX6974/MAX6975
24-Output PWM LED Drivers
for Message Boards
_______________________________________________________________________________________ 3
Note 1: All parameters tested at TA= +85°C. Specifications over temperature are guaranteed by design.
Note 2: Specification limits apply to devices at the same TAfor TA= TMIN to TMAX.
Note 3: Guaranteed by design.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output Slew Time LOADO 20% to 80%, 80% to 20%, load = 10pF 3 ns
Output Low Voltage MUX_ VOLM ISINK = 40mA 0.4 V
Open-Circuit Detection VOCD 200 mV
Output Voltage Slew Time
R0–R7, G0–G7, B0–B7
80% to 20%, load = 50pF,
calibration DACs set to 0xFF 100 ns
TA = +85°C 29.4 30 30.6
TA = +125°C 29.10 30.90
Full-Scale Port Output Current
R0–R7, G0–G7, B0–B7 ISINKFS VDD = 3.3V, VO = 1.2V,
calibration DACs set to 0xFF TA = TMIN to TMAX 28.2 31.8
mA
TA = +125°C
(Note 3) 0.5 1.7
TA = +85°C 0.3 1
Port-to-Port Current Matching
R0–R7, G0–G7, B0–B7 ΔISINK
VDD = 3.3V, VO = 1.2V,
calibration DACs set to 0xFF
ISINK = 30mA (Note 2) TA = -40°C
(Note 3) ±0.9 3.0
%
TA = +85°C 0.3 1.15
Output Load Regulation ΔIOLR
V
D D
= 3.3V , V
O = 1.2V to 3.0V ,
calibration DACs set to 0x80,
ISINK = 18mA TA = TMIN to TMAX 1.5
mA/V
TA = +85°C 0.6 1.7
Output Power-Supply Rejection ΔIOPSR
V
D D
= 3.0V to 3.6V , V
O = 1.2V ,
calibration DACs set to 0x80,
ISINK = 18mA TA = TMIN to TMAX 2.0
mA/V
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3.0V to 3.6V, TA= TMIN to TMAX, unless otherwise noted. Typical values are at VDD = 3.3V, TA= +85°C.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
CLKI_ Input Frequency fCLKI 33 MHz
CLKI_ Duty Cycle 40 60 %
CLKO_ Output Delay tPD-CLKO 19 ns
DIN_ Setup Time tSU-DIN 0.5 ns
DIN_ Hold Time tHD-DIN 5ns
DOUT_ Output Delay tPD-DOUT 18 ns
LOADO Output Delay tPD-LOADO 21 ns
LOADI Hold Time tHD-LOADI 11 ns
Watchdog Period When enabled 40 125 300 ms
TIMING CHARACTERISTICS
(VDD = 3.0V to 3.6V, TA= TMIN to TMAX, unless otherwise noted. Typical values are at 3.3V, TA= +85°C.) (Note 1)
MAX6974/MAX6975
24-Output PWM LED Drivers
for Message Boards
4 _______________________________________________________________________________________
Typical Operating Characteristics
(VDD = 3.3V, TA= +25°C, unless otherwise noted.)
OPERATING CURRENT CONSUMPTION
vs. SUPPLY VOLTAGE VDD
MAX6974 toc01
SUPPLY VOLTAGE VDD (V)
IDD (mA)
3.43.33.23.1
53
49
51
55
45
47
3.0 3.5 3.6
TA = -40°CTA = +25°C
TA = +125°C
TA = +85°C
fCLKI = 32MHz
CALDAC = 0xFF
OPERATING CURRENT CONSUMPTION
vs. SUPPLY VOLTAGE VDD
MAX6974 toc02
SUPPLY VOLTAGE VDD (V)
IDD (mA)
3.53.43.33.23.1
24
26
28
30
20
22
3.0 3.6
TA = -40°CTA = +25°C
TA = +85°C
TA = +125°C
fCLKI = 0MHz
CALDAC = 0x00
LED OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
MAX6974 toc03
OUTPUT VOLTAGE (V)
ISINK (mA)
564321
5
15
10
25
20
30
35
0
07
TA = -40°C
TA = +125°C
TA = +25°C
TA = +85°C
LED OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
MAX6974 toc04
OUTPUT VOLTAGE (V)
ISINK (mA)
564321
5
15
10
25
20
30
35
0
07
VDD = +3.0V
VDD = +3.3V VDD = +3.6V
MAX6974/MAX6975
24-Output PWM LED Drivers
for Message Boards
_______________________________________________________________________________________ 5
Pin Description
PIN NAME FUNCTION
1MUX0 Multiplex 0 Active-Low, Open-Drain Output. Use MUX0 to drive a pnp transistor.
2 CLKI+ PWM and Serial-Interface Noninverting Clock LVDS Input
3 CLKI- PWM and Serial-Interface Inverting Clock LVDS Input
4 DIN+ Serial-Interface Noninverting Data LVDS Input
5 DIN- Serial-Interface Inverting Data LVDS Input
6 LOADI Serial-Interface Load CMOS Input
7 I.C. Internally Connected. Connect to GND.
8–15 R0–R7 Red LED Drive Outputs. R0 to R7 are open-drain, constant-current sinks.
16–23 G0–G7 Green LED Drive Outputs. G0–G7 are open-drain, constant-current sinks.
24, 40 VDD Positive Supply Voltage. Bypass VDD to GND with a 0.1µF ceramic capacitor.
25 LOADO Serial-Interface Load CMOS Output
26 DOUT- Serial-Interface Inverting Data LVDS Output
27 DOUT+ Serial-Interface Noninverting Data LVDS Output
28 CLKO- PWM and Serial-Interface Inverting Clock LVDS Output
29 CLKO+ PWM and Serial-Interface Noninverting Clock LVDS Output
30 MUX1 Multiplex 1 Active-Low, Open-Drain Output. Use MUX1 to drive a pnp transistor.
31 AGND Analog Ground. Connect to GND.
32–39 B7–B0 Blue LED Drive Outputs. B0 to B7 are open-drain, constant-current sinks.
EP GND Power Ground. Exposed pad on package underside must be connected to GND.
MAX6974/MAX6975
24-Output PWM LED Drivers
for Message Boards
6 _______________________________________________________________________________________
MAX6974 Block Diagram
R LED DRIVERS
R7–R0
ISET
R7
ISET
8-BIT
G CALDAC
MUX1
OUTPUTS
7-BIT GLOBAL-INTENSITY PDM MODULATOR
12-BIT INDIVIDUAL PWM MODULATOR
88
288
CALIBRATION
DATA LATCH
GLOBAL-
INTENSITY
DATA LATCH
8 8
MUX0 PIXEL PWM NEW DATA LATCH MUX1 PIXEL PWM NEW DATA LATCH
288 288
EXT. PNP EXT. PNP
7
7
EN EN
PWM
COUNTERS
SYNC
288-BIT DATA SHIFT REGISTER
CLKI
LOADI
D
CLKO
DOUT
DIN
288
288
288
CONTROL
MUX0 PIXEL PWM OLD DATA LATCH
LOAD
288 288
MUX1 PIXEL PWM OLD DATA LATCH
OE
LOAD
Q1
24
7
MUX0
OUTPUT
24-BIT NEW HEADER
SHIFT REGISTER
SYNC DETECT
R6 R5 R4 R3 R2 R1 R0
8-BIT
R CALDAC
R LED OUTPUTS
G LED DRIVERS
G7–G0
G7 G6 G5 G4 G3 G2 G1 G0
G LED OUTPUTS
LOADO
ISET
8-BIT
B CALDAC
8
B LED DRIVERS
B7–B0
B7 B6 B5 B4 B3 B2 B1 B0
B LED OUTPUTS
8
0/1
OE
MAX6974
MAX6974/MAX6975
24-Output PWM LED Drivers
for Message Boards
_______________________________________________________________________________________ 7
MAX6975 Block Diagram
R LED DRIVERS
R7–R0
ISET
R7
ISET
8-BIT
G CALDAC
MUX1
OUTPUTS
5-BIT GLOBAL-INTENSITY PDM MODULATOR
14-BIT INDIVIDUAL PWM MODULATOR
88
336
CALIBRATION
DATA LATCH
GLOBAL-
INTENSITY
DATA LATCH
8 8
MUX0 PIXEL PWM NEW DATA LATCH MUX1 PIXEL PWM NEW DATA LATCH
336 336
EXT. PNP EXT. PNP
5
5
EN EN
PWM
COUNTERS
SYNC
336-BIT DATA SHIFT REGISTER
CLKI
LOADI
D
CLKO
DOUT
DIN
336
336
336
CONTROL
MUX0 PIXEL PWM OLD DATA LATCH
LOAD
336 336
MUX1 PIXEL PWM OLD DATA LATCH
OE
LOAD
Q1
24
5
MUX0
OUTPUT
24-BIT NEW HEADER
SHIFT REGISTER
SYNC DETECT
R6 R5 R4 R3 R2 R1 R0
8-BIT
R CALDAC
R LED OUTPUTS
G LED DRIVERS
G7–G0
G7 G6 G5 G4 G3 G2 G1 G0
G LED OUTPUTS
LOADO
ISET
8-BIT
B CALDAC
8
B LED DRIVERS
B7–B0
B7 B6 B5 B4 B3 B2 B1 B0
B LED OUTPUTS
8
0/1
OE
MAX6975
MAX6974/MAX6975
Detailed Description
The MAX6974/MAX6975 drive 24 nonmultiplexed LEDs
or 48 multiplexed LEDs for various indoor and outdoor
display applications. The EZCascade serial interface
enables large multidriver display panels to be con-
structed with interconnected MAX6974/MAX6975
devices (see Figure 1).
The drivers provide 12-bit (MAX6974) or 14-bit
(MAX6975) individual PWM steps for each LED output.
Four to seven global-intensity bits provide additional
pulse-density modulation (PDM) intensity control (see
Table 1). The MAX6974/MAX6975 provide 19 bits of
total current/intensity control range per color per pixel,
or 18 bits if multiplexing. The total PWM dynamic range
encompasses gamma correction and, if desired, indi-
vidual LED calibration.
LED outputs are grouped in ports (R, G, and B) with
eight LED outputs per port. Each port features its own
current calibration control DAC (CALDAC) with 0.31%
resolution to set the current. The MAX6974/
MAX6975 current calibration feature allows unmatched
LEDS from different lots and manufacturers to be
color matched.
Power-Up
On power-up, the MAX6974/MAX6975 set the calibration
current to the minimum current for all LED outputs and
clear the global-intensity PDM data, individual-intensity
PWM data, and the timing counters. The display
remains blank after CLKI starts running. The watchdog
function is inactive after power-up.
24-Output PWM LED Drivers
for Message Boards
8 _______________________________________________________________________________________
HOST
CLKO
DOUT
LOADO
CLKI
DIN
LOADI
MAX6974/
MAX6975
1
MAX6974/
MAX6975
2
MAX6974/
MAX6975
3
MAX6974/
MAX6975
N
CLKI
DIN
LOADI
CLKO
DOUT
LOADO
CLKI
DIN
LOADI
CLKO
DOUT
LOADO
CLKI
DIN
LOADI
CLKO
DOUT
LOADO
CLKI
DIN
LOADI
CLKO
DOUT
LOADO
OPTIONAL FEEDBACK
Figure 1. Generic Cascaded Connection Scheme
GLOBAL PDM
PART LED DRIVE
OUTPUTS
LED DRIVE
CURRENT
CALIBRATION
DAC RANGE DIRECT MULTIPLEXED
INDIVIDUAL
PWM
MAX6974 7 bits 6 bits 12 bits
5 bits 4 bits
MAX6975
24
(7V rated) 30mA 6mA to 30mA
3 bits 2 bits 14 bits
Table 1. Comparison of MAX6974/MAX6975
LED-Intensity Control
The MAX6974/MAX6975 provide three levels of output
current control for LED drive: calibration DACs
(CALDACs), global-intensity control, and individual-
intensity control. The CALDACs set the port output cur-
rent levels, while the global-intensity and individual-
intensity controls modulate the output current on/off
times, providing a fine-resolution control of average
output currents (see Figure 2). The individual-intensity
control operates on each output independently to set
each individual LED intensity level. The global-intensity
controls modulate MAX6974/MAX6975 outputs simulta-
neously for a uniform brightness control without affect-
ing color. Using a fixed output current level that is
modulated only by on/off control leaves the LED color
unaffected while precisely controlling intensity. Finally,
all outputs can be turned on and off simultaneously by
setting or clearing configuration bit D3 (PWM-ON).
Calibration DACs
The 8-bit R, G, and B CALDACs set the output current
level for all eight outputs in the R, G, and B ports,
respectively (see the
MAX6974 Block Diagram
and
MAX6975 Block Diagram
). The R CALDAC, G
CALDAC, and B CALDAC range from a low of 6mA
(0x00) to a maximum of 30mA (0xFF), providing
94µA/step of current trimming. The CALDACs are
loaded by the serial interface using command 01 (see
Table 4). The B CALDAC data is loaded first, followed
by the G CALDAC data, and then the R CALDAC data
(see the
Serial Interface
section). The loaded data takes
effect immediately.
Global-Intensity Control
The MAX6974/MAX6975 adjust global and individual
intensities over a time period called a frame. One frame
requires 219 (524,288) periods of CLKI and corre-
sponds to one video-frame time. Video frames generally
contain consecutive images displayed rapidly to yield
a motion picture display. Running the MAX6974/
MAX6975 at fCLKI = 31.5MHz allows a video-frame
update rate of 60fps for full-motion video (see the
MAX6974 Video-Frame Timing
and
MAX6975 Video-
Frame Timing
sections).
The MAX6974/MAX6975 further divide frames into sub-
frames to allow a unique combination of global- and
individual-intensity controls. The number of subframes
is equal to the number of global-intensity control steps.
The MAX6974 uses 128 subframes per frame in
nonmultiplexed mode (corresponding to 7-bit global-
intensity PDM control) and 64 subframes in multiplexed
mode (corresponding to 6-bit global-intensity PDM
control). The MAX6975 features 5-, 4-, 3-, and 2-bit
global-intensity control to yield 32, 16, 8, and 4 sub-
frames per frame, respectively.
The MAX6974/MAX6975 control global intensity by
driving subframes on and off. When a subframe is on, it
allows the individual PWM intensity control to be driven
on the outputs. Subframes that are off do not have any
PWM modulation on the outputs.
Individual PWM Control
The MAX6974/MAX6975 further modulate the time that
each subframe is ON by a pulse-width modulation
MAX6974/MAX6975
24-Output PWM LED Drivers
for Message Boards
_______________________________________________________________________________________ 9
5
10
15
25
30
(mA) CALDAC
CURRENT
20
30mA MAX
6mA MIN
1270 GLOBAL
= 96
GLOBAL-INTENSITY
PDM
INDIVIDUAL-INTENSITY
PWM
40950 Rn, Gn, OR Bn PWM
= 2560
Rn, Gn, OR Bn IAVE = 10.22mA
CALDAC
= 169
2550
21.8mA
100%
0%
50%
100%
0%
50%
100%
0%
50%
Figure 2. Relationship Among the CALDACs, Global-Intensity, and Individual-Intensity PWM Controls
MAX6974/MAX6975
(PWM) value. Each output current driver in the R, G,
and B ports has a unique 12-bit (MAX6974) or 14-bit
(MAX6975) PWM control value providing fine resolution
adjustment of average current output. Each bit time of
the PWM corresponds to one period of CLKI (TCLKI).
The PWM setting determines the amount of time, out of
the total period, that the output is on. The subframes
have PWM off-zones at the start (tSPWM) and end
(tEPWM) of the PWM period (see Figure 3). The sub-
frame period and PWM off zones are shown in Table 2
for each device.
The MAX6974 subdivides each subframe by 4096
(12-bit) PWM steps and has 16 cycle off zones, leaving
an active PWM region of 4064 PWM steps ranging from
16 to 4079. The MAX6975 subdivides each subframe
by 16,384 (14-bit) PWM steps and has 32 cycle off
zones, leaving an active PWM region of 16,320 PWM
steps ranging from 32 to 16,351. The PWM phase for
outputs R0, R2, R4, R6, G0, G2, G4, G6, B0, B2, B4,
and B6 use phasing with the outputs on first and off
second. Inverse phasing is used for outputs R1, R3,
R5, R7, G1, G3, G5, G7, B1, B3, B5, and B7 as shown
in Figure 3 to balance the timing of loads on the LED
anode power supply.
In multiplexed operation, the subframes are shared
between MUX0 and MUX1 active times, effectively
reducing the number of subframes by 2.
LED-Intensity Control Example
The three levels of intensity control are shown in Figure 2
for one LED output driver in a MAX6974 in nonmulti-
plexed mode. As an example, the CALDAC is set to
169DEC, setting the port output current level to 21.8mA.
The global-intensity PDM value is set to 96DEC, producing
an even distribution of ON subframes out of the 128
24-Output PWM LED Drivers
for Message Boards
10 ______________________________________________________________________________________
R0, R2, R4, R6
G0, G2, G4, G6
B0, B2, B4, B6
R1, R3, R5, R7
G1, G3, G5, G7
B1, B3, B5, B7
R0, R2, R4, R6
G0, G2, G4, G6
B0, B2, B4, B6
R1, R3, R5, R7
G1, G3, G5, G7
B1, B3, B5, B7
SUBFRAME (n) SUBFRAME (n + 1)
tSPWM
tEMUX
tEMUX
MUX0
SUBFRAME (n), MUX0 SUBFRAME (n), MUX1
MUX1
tSPWM
tSPWM tEPWM
MULTIPLEXED
NONMULTIPLEXED
tSPWM tEPWM
ON/OFF PHASING
OFF/ON PHASING
ON/OFF PHASING
OFF/ON PHASING
50% 75%
100%25%
75%75%
75% 75%
Figure 3. Multiplexed and Nonmultiplexed Output Driver Phasing and Example PWM Values
PART SUBFRAME
(TCLKI)
tSPWM
(TCLKI)
tEPWM
(TCLKI)
tEMUX
(TCLKI)
MAX6974 4096 16 16 16
MAX6975 16,384 32 32 32
Table 2. Subframe and PWM Timing
possible (shown in Figure 4 as subframes 1, 3, 4, 5, etc).
Each subframe can be ON for a PWM duration set by the
individual PWM value. The PWM value setting of
2560DEC out of 4096 (12-bit) results in a further reduction
of current ON time (shown in bold trace).
The internal PDM logic spreads the on subframes as
evenly as possible among the off subframes to keep
the effective scanning frequency high.
For applications with a slower clock speed, the
MAX6975 can increase the display refresh rate by a
factor of four to eliminate visible flicker. Setting configu-
ration bit D4 (GLB4) to 1 activates the increased
refresh rate (see Table 6). The increased refresh rate
reduces the number of global-intensity settings by a
factor of four (see Table 3).
MAX6974 Video-Frame Timing
The MAX6974 supports up to 60 video frames per
second (fps). The following equation shows the
required clock frequency to support 60 video fps:
60 (video fps) x 4096 (clocks per 12-bit PWM period) x
128 (global-intensity subframes) = 31.5MHz.
The MAX6974 supports up to a 33MHz clock signal
(~63fps).
Each 12-bit PWM period contains 4096 clock cycles;
multiply that number by 128 (number of global-intensity
subframes) to obtain the required number of clock cycles
(524,288) per video frame. The MAX6974 requires 36
bits (12 bits per color multiplied by three colors) to drive
an RGB pixel. The maximum pixel data that the
MAX6974 can send per video frame is 524,288 / 36 or
14,563 pixels, corresponding to 1820 cascaded
MAX6974s.
MAX6975 Video-Frame Timing
The MAX6975 also supports up to 60 video frames per
second (fps). The following equation shows the
required clock frequency to support 60 video fps:
60 (video fps) x 16,384 (clocks per 14-bit PWM period)
x 32 (global-intensity subframes) = 31.5MHz.
The MAX6975 supports up to a 33MHz clock signal
(~63fps).
Each 14-bit PWM period contains 16,384 clock cycles;
multiply 16,384 by 32 (global-intensity subframes) to
obtain the required number of clock cycles (524,288)
per video frame. The MAX6975 requires 42 bits (14 bits
per color multiplied by three colors) to drive an RGB
pixel. The maximum pixel data that the MAX6975 can
send per video frame is 524,288 / 42 or 12,483 pixels,
corresponding to 1560 cascaded MAX6975s.
Multiplexed vs. Nonmultiplexed Operation
The MAX6974/MAX6975 can double the number of
LEDs driven from 24 to 48 through multiplexing. When
multiplexing, the two outputs, MUX0 and MUX1, drive
MAX6974/MAX6975
24-Output PWM LED Drivers
for Message Boards
______________________________________________________________________________________ 11
169d = 20
SUBFRAME NUMBER
5
10
15
25
30mA MAX
6mA MIN
(mA)
01234567891011
CALDAC CURRENT
OUTPUT LED CURRENT
PWM = 2560/4096
ONE FRAME IS 219 (524,288) CLKI CYCLES LONG
GLOBAL PDM = 96/128 SUBFRAMES
ON ON ON ON ON ON ON ON
Figure 4. The three levels of LED current control (CALDAC, global-intensity PDM, and individual PWM) modulate the average output
current.
MAX6974/MAX6975
two external pnp transistors, such as FMMTL717, used
as common-anode power switches (see Figure 5).
Setting configuration bit D0 to 1 enables multiplex
operation. MUX0 and MUX1 alternate the LED anode
drive voltage between two sets of LEDs. The R, G, and
B ports provide individual PWM control during alternate
24-Output PWM LED Drivers
for Message Boards
12 ______________________________________________________________________________________
R0
R1
R2
R3
R4
R5
R6
R7
(REDS)
(REDS) (GREENS) (GREENS) (BLUES) (BLUES)
Q1
FMMTL717
R1
560Ω
R2
180Ω
C1
120pF
+5.55V
Q2
FMMTL717
R1
560Ω
R2
180Ω
C1
120pF
G1
G2
G3
G4
G5
G6
G7
G0
B1
B2
B3
B4
B5
B6
B7
B0
MUX0
MUX1
SUBFRAME 15
MUX1
16,384 CLKs
SUBFRAME 0
MUX0
16,384 CLKs
SUBFRAME 0
MUX1
16,384 CLKs
SUBFRAME 1
MUX0
16,384 CLKs
SUBFRAME 1
MUX1
16,384 CLKs
SUBFRAME 14
MUX0
16,384 CLKs
SUBFRAME 14
MUX1
16,384 CLKs
SUBFRAME 15
MUX0
16,384 CLKs
SUBFRAME 15
MUX1
16,384 CLKs
SUBFRAME 0
MUX0
16,384 CLKs
ONE COMPLETE 524,288 CLOCK CYCLE MULTIPLEXED VIDEO FRAME
Figure 5. MAX6975 Multiplexing Two Sets of Eight RGB Pixels with a Single LED Supply and Subframe Timing
MUX cycles as shown in Figure 3. The alternating MUX
cycles reduce the global-intensity resolution (the num-
ber of subframes) by half, which reduces the average
LED current by half.
Watchdog
A selectable watchdog timer monitors serial-interface
inputs CLKI, DIN, and LOADI. Enabling the watchdog
timer requires that CLKI, DIN, and LOADI toggle at
least once every 40ms. If any of these transitions fails to
occur, then the individual-intensity PWM data latches
clear. This condition effectively blanks the LEDs.
Update the individual-intensity PWM data registers to
turn the LEDs back on. The watchdog timeout does not
affect the calibration or global-intensity data, the clock
synchronization, or multiplexed/nonmultiplexed setting.
Use the watchdog functionality in safety-critical appli-
cations where a blanked display is safer than an incor-
rect display.
LED Open-Circuit and
Overtemperature Detection
The MAX6974/MAX6975 feature two fault detection func-
tions: open-circuit LED outputs and overtemperature. An
LED open circuit is detected on driver outputs by moni-
toring for output voltages below 200mV. When an open
circuit is detected, the MAX6974/MAX6975 increments
a fault counter included in the serial-interface protocol
that can be routed back to the host transmitter for diag-
nostics. Any number of open-circuit LEDS, multiplexed
or nonmultiplexed, can be detected, however, only one
counter increment occurs per device.
The MAX6974/MAX6975 detect die temperatures
above TDIE = +165°C and disable all output drivers by
setting all PWM data to zero. The fault counter in the
serial-interface protocol is incremented by one count
for each cascaded device with an overtemperature
condition. The output drivers are turned back on when
the die temperature falls below TDIE = +150°C. The
fault counter value is distinguished between LED open-
circuit and overtemperature conditions by the serial-
interface command used at the time of detection (see
the
Serial Interface
section for more details).
Commands
The MAX6974/MAX6975 have four commands used to
load all operating mode and LED output current data.
MAX6974/MAX6975
24-Output PWM LED Drivers
for Message Boards
______________________________________________________________________________________ 13
PART MUX
BIT OPERATION PWM
RES.
TOTAL CLOCKS PER
PWM SUBFRAME
USEABLE CLOCKS PER
PWM SUBFRAME
MAXIMUM PWM
DUTY CYCLE
0 Nonmultiplex
MAX6974 1 Multiplex 12 bits 4096 4064 4064 / 4096 = 99.22%
0 Nonmultiplex
MAX6975 1 Multiplex 14 bits 16,384 16,320 16,320 / 16,384 = 99.61%
Table 3. MAX6974/MAX6975 Timing Comparison
PART GLB4
BIT
MUX
BIT OPERATION
GLOBAL
PDM
RES.
SUBFRAMES
PER FRAME
CLOCKS
PER
FRAME
CLOCK
FREQUENCY (MHz)
FOR 50fps
CLOCK
FREQUENCY (MHz)
FOR 60fps
X 0 Nonmultiplex 7 bits 128
MAX6974 X 1 Multiplex 6 bits 64 524,288 26.2144 31.45728
0 Nonmultiplex 5 bits 32
01 Multiplex 4 bits 16 524,288 26.2144 31.45728
0 Nonmultiplex 3 bits 8
MAX6975
11 Multiplex 2 bits 4 131,072 6.5536 7.8643
MAX6974/MAX6975
Each command is uniquely identified by two bits, C1
and C0, embedded in the serial-interface protocol
structure. The commands Load CALDAC, Load Global-
Intensity PDM, and Load Configuration each require 24
bits of data (3 bytes) for every cascaded device. The
number of bits required for the command load individual
PWM varies by device and multiplex mode of operation.
Each cascaded device can receive unique data for
CALDACs, global intensity, configuration, and individual
PWM output drivers. Generally, all cascaded devices
are operated in the same configuration mode. The data
bytes are transmitted MSB first for all commands. The
commands are communicated to all cascaded devices
by the host using the synchronous serial-interface and
protocol structure (see the
Serial Interface
section for
details). The four commands and the data lengths for
each command are shown in Table 4.
The MAX6974, operating in nonmultiplexed mode,
requires twenty-four 12-bit individual PWM data (288
bits total) and requires forty-eight 12-bit data (576 bits
total) in multiplexed operation mode. Similarly, the
MAX6975, operating in nonmultiplexed mode, requires
twenty-four 14-bit individual-intensity PWM data (336
bits total) and requires forty-eight 14-bit (672 bits total)
data in multiplexed mode. The individual PWM data are
loaded into an intermediate latch and transferred to the
actual PWM latches at subframe 0 and PWM clock 0.
The R, G, and B calibration DACs are loaded with 8-bit
data each in nonmultiplexed and multiplexed modes.
Data is updated immediately into the CALDAC latches
(see Table 8)
.
The MAX6974/MAX6975 require one data byte to set the
global-intensity PDM for all output drivers. The global-
intensity PDM data has a variable number of active bits
depending on the multiplex operating mode and, for
the MAX6975, the global-quarter setting. The number of
bits used for global-intensity control is always justified
to the LSB of the data byte, as shown in Table 5. One
byte of data is sent three times with the global-intensity
PDM data bits justified to the LSB. Data is updated into
the PWM latches at subframe 0 and PWM clock 0 (see
Table 9)
.
When using the MAX6975 5-bit global-intensity setting,
the settings range from 0 to 63 to set the global intensity
from 1 to 64 subframes ON to 64 out of 64 subframes ON.
When using the MAX6974 7-bit global-intensity setting,
the settings range from 0 to 127 to set the global inten-
sity from 1 out of 128 subframes ON to 128 out of 128
subframes ON.
24-Output PWM LED Drivers
for Message Boards
14 ______________________________________________________________________________________
CMD[1:0]
C1 C0 COMMAND DATA LENGTH PER CASCADED DEVICE
288 bits (MAX6974 nonmultiplexed)
576 bits (MAX6974 multiplexed)
336 bits (MAX6975 nonmultiplexed)
0 0 Load individual PWM
672 bits (MAX6975 multiplexed)
0 1 Load CALDAC 24 bits
1 0 Load global-intensity PDM 24 bits
1 1 Load configuration 24 bits
Table 4. Commands and Data Length
PART GLB4 MUX TOTAL BITS MSB D7 D6 D5 D4 D3 D2 D1 LSB D0
X 0 7 0 Bit[6] Bit[5] Bit[4] Bit[3] Bit[2] Bit[1] Bit[0]
MAX6974 X 1 6 0 0 Bit[5] Bit[4] Bit[3] Bit[2] Bit[1] Bit[0]
0 0 5 0 0 0 Bit[4] Bit[3] Bit[2] Bit[1] Bit[0]
0 1 4 0 0 0 0 Bit[3] Bit[2] Bit[1] Bit[0]
1 0 3 0 0 0 0 0 Bit[2] Bit[1] Bit[0]
MAX6975
1 1 2 0 0 0 0 0 0 Bit[1] Bit[0]
Table 5. Global-Intensity Data Bit Justification
The global-intensity data is received in an intermediate
register and is applied to the outputs at subframe 0 and
PWM clock 0.
The MAX6974/MAX6975 have one byte of configuration
data with 5 active bit settings as shown in Table 6. One
byte of data containing configuration bit settings is sent
three times. Data is updated immediately into the CAL-
DAC latches. See Table 10
.
The loaded configuration
settings take effect immediately.
Serial Interface
The MAX6974/MAX6975 feature a fully synchronous
and fully buffered serial interface that allows cascading
of multiple devices. The serial interface consists of
inputs (CLKI, DIN, and LOADI) and outputs (CLKO,
DOUT, and LOADO). The MAX6974/MAX6975 can
pass different data to each cascaded device without
any additional inputs to identify the position of the
devices in the cascaded chain.
MAX6974/MAX6975
24-Output PWM LED Drivers
for Message Boards
______________________________________________________________________________________ 15
CONFIGURATION BIT ACRONYM FUNCTION DESCRIPTION
MSB D7 — 0 Not used
D6 — 0 Not used
D5 — 0 Not used
D4 GLB4 Global quarter
Enables the reduced global-intensity setting in the MAX6975 when set to
1. When set, the MAX6975 uses eight (or four, if multiplexing) PWM
subframes. GLB4 is set to 0 as power-on default. Setting bit D4 has no
effect in the MAX6974.
D3 PWM-ON
Enable
individual
PWMs
Turns all individual PWM outputs on when set to 1. Power-on default is
PWM-ON set to 0 to disable all current output drivers. PWM-ON can be
used to turn all LEDs on or off without affecting the global-intensity or
individual PWM settings.
D2 CRST
Reset frame
and PWM
counters
Setting CRST to 1 synchronously resets internal counters to 0. This action
sets the MAX6974/MAX6975 to subframe 0 of the global-intensity
subframe counter and clock 0 of all individual PWM counters. The CRST
bit is a nonlatching control function that resets to 0 after the counters are
set to 0.
D1 WDOG Watchdog
enable
Setting WDOG to 1 enables the watchdog timer operation. Power-on
default is 0.
LSB D0 MUX Multiplex
enable Setting MUX to 1 turns multiplex mode on. Power-on default is 0.
Table 6. Load Configuration Bit Definitions
MAX6974/MAX6975
The serial interface uses the continuously running
clock, CLKI, to synchronously transfer and latch data
(33MHz max). The MAX6974/MAX6975 sample inputs
DIN and LOADI on the rising edge of CLKI and update
outputs DOUT and LOADO on the rising edge of CLKI.
The MAX6974/MAX6975 specifications guarantee that
cascaded devices observe setup and hold timing from
device to device, making external buffers and clock
trees unnecessary, even in very large systems.
The high-speed CLKI, CLKO, DIN, and DOUT signals
use low-voltage differential signaling (LVDS), and the
less frequently changing control signals, LOADI and
LOADO, use standard CMOS. The differential signals
are generally referred to in unipolar shorthand; for
example, the statement “CLKI rising edge” means that
CLKI+ is rising, and CLKI- is falling.
The MAX6974/MAX6975 use LVDS drivers with differential
signaling (300mV nominal logic swing around a +1.2V
bias) and cascaded CMOS control signals to minimize
signal-path EMI and simplify interface timing and print-
ed-circuit board (PCB) layout. Note the differential
inputs for the first driver can be driven from +3.3V
CMOS using LVDS level translators, such as the
MAX9112 terminated with 110Ω(see Figure 12).
A 25MHz to 33MHz clock frequency is recommended
to keep the display refresh rate high. When using the
MAX6975 in reduced global-intensity mode (GLB4 = 1
in configuration register), the recommended clock
frequency range is 6MHz to 33MHz.
Serial-Interface Protocol Structure
The MAX6974/MAX6975 serial interface transfers all
data and control functions using a protocol structure
consisting of header, data, and optional tail segments
transmitted in this sequence. The header and tail
24-Output PWM LED Drivers
for Message Boards
16 ______________________________________________________________________________________
tHD-DIN
tHD-LOADI
CLKI+
CLKI-
CLKO+
CLKO-
DIN+
DIN-
DOUT+
DOUT-
LOADI
LOADO
tPD-CLKO
tSU-DIN
tPD-DOUT
tPD-LOADO
tSU-LOADI
Figure 6. Serial-Interface Timing
segments transfer to all cascaded devices, while the
data section reduces in bit length as data transfers
through the cascaded devices. When LOADI is low, the
MAX6974/MAX6975 continuously monitor DIN for
reception of the SYNC pattern (see the
Header
Segment
section).
Header Segment
The 24-bit header segment consists of an 8-bit fixed
synchronization pattern (SYNC), a 6-bit command pat-
tern (CMD), and a 10-bit counter (CNTR) segment (see
Table 7). LOADI must change from low to high within
plus or minus one clock cycle of the first command bit.
When the SYNC bit pattern 0xE8 is recognized, LOADI
is monitored for the rising edge, allowing the device to
internally synchronize LOADI to CLKI. The six command
bits, CMD[5:0], consist of bits C1 and C0 repeated
three times. The four commands used by the MAX6974/
MAX6975 are defined by the two bits, C1 and C0.
The counter segment is incremented by one for each
cascaded device with an internal fault detected. Use the
counter segment to collect fault data across the cas-
caded chain.
HDR[23:0]
Complete 24-bit header segment.
SYNC[7:0]
Synchronization bit pattern 0xE8 is recognized by the
MAX6974/MAX6975 during intervals when LOADI is low.
The SYNC bit pattern, followed by the rising edge of
LOADI, internally synchronizes the timing relationship
between CLKI and DIN with the LOADI signal. The
synchronization pattern must be 0xE8.
CMD[5:0]
Send command bits C1 and C0 three times in succes-
sion. The command bits define how many data bits are
received and where the data is loaded. The four com-
mands are:
CNTR[9:0]
This is the counter for open LED or overtemperature fault
conditions. The host sends the header segment with the
counter value set to zero. The counter value is incre-
mented one count by each device that detects a fault
condition in the cascaded chain. The accumulated count
value returns to the host from the last device in the cas-
cade chain. The command determines which fault type
is incremented to the counter (see
LED Open-Circuit and
Overtemperature Detection Counter
section):
CMD[1:0] = X0 Overtemperature faults counted
CMD[1:0] = X1 Open LED faults counted
MAX6974/MAX6975
24-Output PWM LED Drivers
for Message Boards
______________________________________________________________________________________ 17
HDR
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYNC CMD CNTR
765432101010109876543210
1 1 1 0 1 0 0 0 C1C0C1C0C1C0b9b8b7b6b5b4b3b2b1b0
Table 7. Serial-Interface Header
C1:C0 COMMAND CMD[5:0]
00 Load individual PWM 000000
01 Load CALDAC 010101
10 Load global-intensity PDM 101010
11 Load configuration 111111
HEADER
COUNTER
CLKI
COMMAND
11101000
SYNC
LOADI
12345678910 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
DIN
1
0
(CONTINUOUS)
C1 C0 C1 C0 C1 C0 b9 b8 b7 b6 b5 b4 b3 b2
DATA
b1 b0
Figure 7. Header-Segment Timing
MAX6974/MAX6975
Data Segment
The bit length of the data segment received by the
MAX6974/MAX6975 is dependent on the command
specified in the header.
The load CALDAC command has three unique data
bytes, while load global-intensity PDM and load
configuration each have one byte of data repeated
three times. The CALDAC data within the command
load CALDAC is sent with B CALDAC data first, fol-
lowed by G CALDAC data, and then R CALDAC data,
as shown in Table 8.
The data segment of the load individual PWM command
has a variable length depending on specific device and
configuration settings. The data is always organized
as B driver data first in the order of B7 first to B0 last
(MSB first), followed by the G driver data in the same
order of G7 to G0 (MSB first), and then the R driver data
in the order of R7 to R0 (MSB first).
Tail Segment
The MAX6974/MAX6975 allow for an optional string of
data bits to be transmitted following all device data
bits, which is referred to as the tail segment. The data
bits of the tail segment are clocked back to the host,
following the header, from the last device in a cascaded
chain. The number of bits in the tail segment is optional.
The tail carries no device-specific data on DIN, but
provides feedback confirmation to the host that all data
bits were extracted by all devices in the cascade chain.
24-Output PWM LED Drivers
for Message Boards
18 ______________________________________________________________________________________
HEADER DATA 1 DATA 2 DATA 3 … DATA N
HDR[23:0] B[7:0] G[7:0] R[7:0] B[7:0] G[7:0] R[7:0] B[7:0] G[7:0] R[7:0] … B[7:0] G[7:0] R[7:0]
Table 8. Serial Format for Load CALDAC
HEADER DATA 1 DATA 2 DATA 3 … DATA N
HDR[23:0] D[7:0] D[7:0] D[7:0] D[7:0] D[7:0] D[7:0] D[7:0] D[7:0] D[7:0] … D[7:0] D[7:0] D[7:0]
Table 9. Serial Format for Load Global-Intensity PDM
HEADER DATA 1 DATA 2 DATA 3 … DATA N
HDR[23:0] D[7:0] D[7:0] D[7:0] D[7:0] D[7:0] D[7:0] D[7:0] D[7:0] D[7:0] … D[7:0] D[7:0] D[7:0]
Table 10. Serial Format for Load Configuration
HEADER DATA 1 DATA 2 DATA 3 … DATA N
HDR[23:0] B7, B6, …R0 B7, B6, …R0 B7, B6, …R0 … B7…R0
Table 11. Serial Format for Load Individual PWM (Nonmultiplexed)
HEADER DATA 1 DATA 2 DATA 3 … DATA N
HDR[23:0] B7, B7', B6, B6', …R0' B7, B7', B6, B6', …R0' B7, B7', B6, B6', …R0' … B7, B7', B6, B6', …R0'
Table 12. Serial Format for Load Individual PWM (Multiplexed)
B[7:0] 8-bit data loaded into port B CALDAC
G[7:0] 8-bit data loaded into port G CALDAC
R[7:0] 8-bit data loaded into port R CALDAC
N Number of cascaded devices
D[7:0] Send the 8-bit data for the global-intensity PDM three times (24 total bits)
D[7:0] Send the 8-bit configuration data three times (24 total bits)
B_…G_…R_ 12-bit (MAX6974) or 14-bit (MAX6975) data each
B_ 12-bit (MAX6974) or 14-bit (MAX6975) PWM data for each output B_ during multiplex phase MUX0, MSB first
B_' 12-bit (MAX6974) or 14-bit (MAX6975) PWM data for each output B_ during multiplex phase MUX1, MSB first
G_ 12-bit (MAX6974) or 14-bit (MAX6975) PWM data for each output G_ during multiplex phase MUX0, MSB first
G_' 12-bit (MAX6974) or 14-bit (MAX6975) PWM data for each output G_ during multiplex phase MUX1, MSB first
R_ 12-bit (MAX6974) or 14-bit (MAX6975) PWM data for each output R_ during multiplex phase MUX0, MSB first
R_' 12-bit (MAX6974) or 14-bit (MAX6975) PWM data for each output R_ during multiplex phase MUX1, MSB first
Serial-Interface Cascade Timing
The MAX6974/MAX6975 serial-interface protocol timing
is simplified by the guaranteed setup and hold charac-
teristics of the outputs from one device driving the
inputs of another. An example of a cascade of three
MAX6974/MAX6975 devices is shown in Figure 8.
Example of Serial-Interface
Cascade Timing
The basic timing of a MAX6974/MAX6975 cascaded
chain of three devices demonstrates the principle that
applies to any number of cascaded devices. The first
device connected to the host transmitter is referenced
as 1, and the remaining devices are referenced as 2
and 3. Device 3 outputs connect to the host for commu-
nicating diagnostic and fault counter data.
The first MAX6974/MAX6975, device 1, receives the
header and captures the first set of data bits. The
number of captured bits is determined by the command
given in the header. A timing example of the data trans-
fer for the Load CALDAC command is shown in Figure
9. Device 1 does not send the captured data out on
DOUT. Instead, device 1 sends out a new header 25
clock cycles after the reception of the first header bit on
DIN. The data flow on each interconnect node is shown
in Figure 10.
After capturing the first data set, device 1 transmits all
following data segments and the optional tail segment
on DOUT, delayed by one CLKI cycle. Device 2
receives the new header from device 1, followed by
data that now begins with device 2’s data set. Device 2
repeats the same process as described above; captur-
ing the first data set received, appending a new head-
er, and passing all subsequent data out DOUT to the
next device 3. Device 3 captures the last data set and
transmits a header followed by the tail segment. The
last header and tail segments are clocked back into the
host receiver. The header received by the host contains
the updated fault counter data. The tail data bit pattern
can be compared to the tail data originally transmitted
by the host for data integrity check.
MAX6974/MAX6975
24-Output PWM LED Drivers
for Message Boards
______________________________________________________________________________________ 19
HOST
CLKO
DOUT
LOADO
CLKI
DIN
LOADI
CLK0
D0
LOAD0
CLK1
D1
LOAD1
CLK2
D2
LOAD2
CLK3
D3
LOAD3
MAX6974/MAX6975
1
MAX6974/MAX6975
2
MAX6974/MAX6975
3
CLKI
DIN
LOADI
CLKO
DOUT
LOADO
CLKI
DIN
LOADI
CLKO
DOUT
LOADO
CLKI
DIN
LOADI
CLKO
DOUT
LOADO
Figure 8. Example Showing Three-Device Cascade Connection Scheme with the Interconnecting Nodes Labeled for Clarity
DATA: CALDAC DATA 1
(CONTINUOUS)
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
CLKI
LOADI
DIN
0
1
B CALDAC G CALDAC G CALDAC B CALDAC G CALDAC R CALDAC
DATA: CALDAC DATA 2
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
Figure 9. Timing Example Showing CALDAC Data Set for the First Two Cascaded Devices
IDLE
IDLE
IDLE
IDLE
CLK0
3 BYTES 1 3 BYTES 2 3 BYTES 3HEADER 1 T
3 BYTES 2 3 BYTES 3HEADER 2 T
3 BYTES 3HEADER 3 T
HEADER 4 T
25 CLOCKS
25 CLOCKS
25 CLOCKS
D0
D1
D2
D3
Figure 10. Data Cascading Example for 24-Bit Data Words
MAX6974/MAX6975
When the MAX6974/MAX6975 send individual-intensity
PWM data, the data segment bit length is large due to
the 12-bit or 14-bit PWM data for each of the 24 outputs
(see Figure 11). The various data segment bit lengths
for each of the four commands and different operating
modes is shown in Table 4. Data capturing is the same
as described above with the header segment outputs
and data being delayed by the full length of the data bit
stream being captured plus one clock cycle.
LED Open-Circuit and
Overtemperature Detection Counter
The MAX6974/MAX6975 feature LED open-circuit
detection and overtemperature detection that use the
counter section of the header segment to record
detected faults. Using commands 01 or 11 force the
counter to record LED open-circuit detection faults.
Using commands 00 or 10 force the counter to record
overtemperature faults.
The MAX6974/MAX6975 detect an open circuit on a driver
output by monitoring for output voltages below 200mV.
When an open circuit is detected, the MAX6974/
MAX6975 increment the counter segment data,
CNTR[9:0], received on DIN by 1 before transmitting a
header and new counter value out DOUT. Regardless
of the number of open-circuit outputs on a device, the
counter increment is 1.
The MAX6974/MAX6975 detect die temperatures above
TDIE = +165°C and disable all output drivers by setting
all PWM data to zero. During an overtemperature event,
the MAX6974/MAX6975 increment the counter segment
data, CNTR[9:0], received on DIN by 1 before transmitting
a header and new counter value out DOUT. The output
drivers are allowed to be on when the die temperature
falls below TDIE = +150°C.
When there is no fault detected, the counter data is
passed directly to DOUT unaltered.
Applications Information
Terminations and PCB Layout
The MAX6974/MAX6975’s layout simplifies cascading
multiple devices, as the interface signals flow through
from each device. The synchronous and buffered
nature of the interface simplifies the board design, but
pay attention to signal routing and termination, as with
other high-speed logic circuits.
Terminate the differential input pairs, CLKI+ and CLKI-,
as well as DIN+ and DIN-, with a termination resistor as
close as possible to the package. When using the
MAX6974/MAX6975 as the signal source, use a 200Ω
termination resistor. When using a level translator or clock
retimer as the signal source, use a 110Ωtermination
resistor. Route each differential input pair as close
parallel tracks with spacing or a GND trace between
the track pair and the next signal track to minimize
cross-coupling. Track lengths up to a few inches do not
require termination-matched tracks (transmission lines).
24-Output PWM LED Drivers
for Message Boards
20 ______________________________________________________________________________________
DATA 1 PWM 288 BITSH1
289 CLOCKS
289 CLOCKS
289 CLOCKS
D0
D1
D2
D3
DATA 2 PWM 288 BITS DATA 3 PWM 288 BITS T
DATA 2 PWM 288 BITS DATA 3 PWM 288 BITS T
H2
DATA 3 PWM 288 BITS T
H3
T
H4
Figure 11. Long (288 Bits) PWM Data Cascading Shown for
MAX6974 in Nonmultiplexed Mode
CLKI- CLKO-
CLKO+
CLKI+
200Ω
DIN- DOUT-
DOUT+
DIN+
LOADO
LOADI
n-2
200Ω
MAX6974
CLKI- CLKO-
CLKO+
CLKI+
110Ω
DIN- DOUT-
DOUT+
DIN+
LOADO
LOADI
n-1
110Ω
MAX6974
DO2-
DO2+
DIN2 DO1-
DO1+
DIN1
MAX9112
CLK
DIN
LOAD
HOST
n MORE DEVICES WITH
200Ω TERMINATION
Figure 12. Typical Cascaded Serial-Interface Termination Circuit
MAX6974/MAX6975
24-Output PWM LED Drivers
for Message Boards
______________________________________________________________________________________ 21
Use the same length interface signal paths, whether
differential or CMOS, to ensure a uniform propagation
delay for each signal.
Power-Supply Considerations
The MAX6974/MAX6975 operate with a power-supply
voltage of 3.0V to 3.6V. Bypass the VDD power supply
to GND with a 0.1µF ceramic capacitor as close as
possible to the device pins. If the LED supply is shared
with the VDD supply, adequately decouple the VDD
supply with bulk capacitance to ensure that the fast-
rising, high-current LED drive currents do not cause
transient dips in VDD.
Driving LEDs from a Supply Higher than 7V
An external npn transistor in a cascode configuration
extends the output drive voltage above 7V. The external
pass transistor’s emitter clamps to a VBE below its
base, which is connected to the MAX6974/MAX6975’s
supply voltage. An optional emitter resistor reduces the
voltage drop across the MAX6974/MAX6975’s output
transistor and effectively takes the dissipation off the
device into the resistor. The external transistor’s collector
current is equal to its emitter current (less a small base
current), and the MAX6974/MAX6975 accurately
control the emitter current with a constant current sink
driver structure.
Example of using an external npn transistor:
VDD = 3.3V ±5%, IOUT = 30mA, external pass transistor
VBE = 0.7V to 1V at 30mA emitter current.
For best output current accuracy, design VOto be at
least 1.2V:
R1(MAX) = (3.15 - 1 - 1.2) / 0.030 = 31.7Ω, so choose
R1 = 30Ω.
MAX6974
MAX6975
VDD
R1
Q1
30mA
+3.3V +3.3V +24V
R1
R2
R3
R4
R5
R6
R7
R0
GND
Figure 13. External Cascode npn Transistor
MAX6974 MAX6974
SYSTEM
CLK
DATA
LOAD
CLKO
DINO
LOADO
CLKI
DINI
LOADI
R0/G0/B0
8 RGB LEDs
R1/G1/B1
R2/G2/B2
R3/G3/B3
R4/G4/B4
R5/G5/B5
R6/G6/B6
R7/G7/B7
R0/G0/B0
R1/G1/B1
R2/G2/B2
R3/G3/B3
R4/G4/B4
R5/G5/B5
R6/G6/B6
R7/G7/B7
CLKO
DINO
LOADO
CLKI
DINI
LOADI
Typical Operating Circuit
Chip Information
PROCESS: BiCMOS
MAX6974/MAX6975
24-Output PWM LED Drivers
for Message Boards
22 ______________________________________________________________________________________
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
QFN THIN.EPS
MAX6974/MAX6975
24-Output PWM LED Drivers
for Message Boards
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________
23
© 2007 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
Revision History
Pages changed at Rev 1: 1, 3, 23
Pages changed at Rev 2: 3, 16, 20, 23
