MMA040AA Datasheet
DC–28 GHz GaAs MMIC Distributed Amplifier
DC–28 GHz GaAs MMIC Distributed Amplifier
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DC–28 GHz GaAs MMIC Distributed Amplifier
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Revision History
The revision history describes the changes that were implemented in the document. The changes
are listed by revision, starting with the most current publication.
1.1 Revision 2.0
Revision 2.0 was the first publication of this document.
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Contents
Revision History .............................................................................................................................. 3
1.1 Revision 2.0 ................................................................................................................................................ 3
2 Product Overview .................................................................................................................... 7
2.1 Functional Block Diagram .......................................................................................................................... 7
2.2 Applications ............................................................................................................................................... 7
2.3 Key Features ............................................................................................................................................... 7
3 Electrical Specifications ............................................................................................................ 8
3.1 Absolute Maximum Ratings ....................................................................................................................... 8
3.2 Typical Electrical Performance ................................................................................................................... 9
3.3 Typical Performance Curves ..................................................................................................................... 10
4 Chip Outline Drawing, Die Packaging, Bond Pad, and Assembly Information ....................... 18
4.1 Chip Outline Drawing ............................................................................................................................... 18
4.2 Die Packaging Information ....................................................................................................................... 18
4.3 Bond Pad Information .............................................................................................................................. 19
4.4 Assembly Drawing.................................................................................................................................... 20
5 Handling and Die Attachment Recommendations ................................................................. 21
6 Ordering Information ............................................................................................................. 22
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List of Figures
Figure 1 Functional Block Diagram .............................................................................................................................. 7
Figure 2 Broadband Gain(VDD = 8 V, IDD = 60mA, T = 25 C .......................................................................................... 10
Figure 3 Broadband Gain vs Temperature (VDD = 8 V, IDD = 60mA) ............................................................................ 10
Figure 4 Gain vs. VDD (IDD = 60 mA, T = 25 °C) ......................................................................................................... 11
Figure 5 Gain vs. IDD (VDD = 8 V, T = 25 °C)............................................................................................................... 11
Figure 6 Input Return Loss (VDD = 8 V, IDD = 60 mA, T = 25 °C) ................................................................................ 12
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List of Tables
Table 1 Absolute Maximum Ratings ............................................................................................................................ 8
Table 2 Typical Electrical Performance .......................................................................................................................... 9
Table 3 Die Packaging Information .............................................................................................................................. 18
Table 4 Bond Pad Information ..................................................................................................................................... 19
Table 5 Bias Sequence ................................................................................................................................................. 20
Table 6 Ordering Information ...................................................................................................................................... 22
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2 Product Overview
MMA040AA is a gallium arsenide (GaAs) monolithic microwave integrated circuit (MMIC)
pseudomorphic high-electron mobility transistor (pHEMT) low-noise distributed amplifier die that
operates between DC and 28 GHz. The amplifier provides flat gain of 16.5 dB, 2.5 dB noise figure,
and 27 dBm OIP3, while requiring only 60 mA from a 8 V supply. The MMA040AA amplifier features
compact die size and I/Os that are internally matched to 50 Ω, facilitating easy integration into
multi-chip modules (MCMs).
2.1 Functional Block Diagram
The following illustration shows the primary functional blocks of the MMA040AA device.
Figure 1 Functional Block Diagram
2.2 Applications
The MMA040AA device is designed for the following applications:
• Test instrumentation
• Telecom infrastructure
• Microwave radio and VSAT
• Microwave communications
2.3 Key Features
The following are key features of the MMA040AA device:
• Frequency range: DC to 28 GHz
• Flat gain: 16.5 dB
• High IP3: 27 dBm
• Low noise: 2.5 dB at 10 GHz
• Supply voltage: 7 V at 60 mA
• 50 Ω matched I/O
• Compact die size: 3 mm × 1.32 mm × 0.1 mm
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3 Electrical Specifications
3.1 Absolute Maximum Ratings
The following table shows the absolute maximum ratings at 25 °C unless otherwise specified.
Table 1 Absolute Maximum Ratings
Parameter
Rating
Storage temperature
–65 to 150 °C
Operating temperature
–55 to 85 °C
Drain bias voltage, (VD)
9 V
Gate bias voltages, (VG1 and VG2)
–2 to 0.5 V
VD current (IDD)
300 mA
RF input power
22 dBm
DC power dissipation (T = 85 °C)
1.1 W
Channel temperature
150 °C
Thermal impedance
60 °C/W
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3.2 Typical Electrical Performance
The following table shows the typical electrical characteristics of the MMA040AA device at 25 °C,
where VDD is 8 V and IDD is 60 mA. All measurements are derived from the RF probed die according
to the assembly diagram shown in section 4.4, unless otherwise noted.
Table 2 Typical Electrical Performance
Parameter
Frequency Range
Min
Typ
Max
Units
Operational frequency range
DC
28
GHz
Gain
DC-6 GHz
15.5
16.5
dB
6 GHz-12 GHz
15.5
16.5
dB
12 GHz-20 GHz
15
16
dB
Gain flatness
DC-6 GHz
±0.2
dB
6 GHz-12 GHz
±0.2
dB
12 GHz-20 GHz
±0.2
dB
Gain variation over temperature
DC-6 GHz
0.007
dB/°C
6 GHz-12 GHz
0.007
dB/°C
12 GHz-20 GHz
0.007
dB/°C
Noise figure
DC-6 GHz
2.5
3
dB
6 GHz-12 GHz
2
2.5
dB
12 GHz-20 GHz
3
3.5
dB
Input return loss
DC-6 GHz
15
dB
6 GHz-12 GHz
15
dB
12 GHz-20 GHz
12
dB
Output return loss
DC-6 GHz
12
dB
6 GHz-12 GHz
15
dB
12 GHz-20 GHz
18
dB
P1dB
DC-6 GHz
15
16
dBm
6 GHz-12 GHz
15.5
16
dBm
12 GHz-20 GHz
14
15
dBm
Psat
DC-6 GHz
17
dBm
6 GHz-12 GHz
18
dBm
12 GHz-20 GHz
17
dBm
OIP3
DC-6 GHz
27
dBm
6 GHz-12 GHz
27
dBm
12 GHz-20 GHz
27.5
dBm
VDD (drain voltage supply)
8
V
IDD (drain current)
60
mA
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3.3 Typical Performance Curves
The following graphs show the typical performance curves of the MMA040AA device at 25 °C, unless
otherwise indicated.
Figure 2 Broadband Gain(VDD = 8 V, IDD = 60mA, T = 25 C
Figure 3 Broadband Gain vs Temperature (VDD = 8 V, IDD = 60mA)
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Figure 4 Gain vs. VDD (IDD = 60 mA, T = 25 °C)
Figure 5 Gain vs. IDD (VDD = 8 V, T = 25 °C)
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Figure 6 Input Return Loss (VDD = 8 V, IDD = 60 mA, T = 25 °C)
Figure 7 Input Return Loss vs. Temperature (VDD = 8 V, IDD = 60 mA)
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Figure 9 Return Loss vs. Temperature (VDD = 8 V, IDD = 60 mA)
Figure 10 Noise Figure vs. Temperature (VDD = 8 V, IDD = 60 mA, T = 25 °C)
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Figure 11 Noise Figure vs. VDD (IDD = 60 mA, T = 25 °C)
Figure 12 Noise Figure vs. IDD (VDD = 6 V, T = 25 °C)
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Figure 13 P1dB Output Power vs. Temperature (VDD = 8 V, IDD = 60 mA, T = 25 °C)
Figure 14 P1dB Output Power vs. VDD (IDD = 60 mA, T = 25 °C)
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Figure 15 P1dB Output Power vs. IDD (VDD = 8 V, T = 25 °C)
Figure 16 Output IP3 vs. Temperature (VDD = 8 V, IDD = 60 mA)
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Figure 17 Output IP3 vs. VDD (IDD = 60 mA, T = 25 °C)
Figure 18 Output IP3 vs. IDD (VDD = 8 V, T = 25 °C)
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4 Chip Outline Drawing, Die Packaging, Bond Pad, and Assembly
Information
4.1 Chip Outline Drawing
The following illustration shows the chip outline of the MMA040AA device. Dimensions are in μm
and are relative to the zero datum locations shown in the drawing. The minimum bond pad size is
100 μm × 100 μm. Both the bond pad surface and the backside metal are 3 μm gold. The die
thickness is 100 μm. The backside is the DC/RF ground. The airbridge keep out region is in
crosshatch, and the unlabeled pads should not be bonded.
Figure 19 Outline Drawing
4.2 Die Packaging Information
The following table shows the chip outline of the MMA040AA device. For additional packaging
information, contact your Microsemi sales representative.
Table 3 Die Packaging Information
Standard Format
Option Format
Waffle Pack
Gel Pack
50-100 pieces per pack
50 pieces per pack
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4.3 Bond Pad Information
The following table shows the bond pad information of the MMA040AA device.
Table 4 Bond Pad Information
Bond Pad Number
Bond Pad Name
Description
2
RFIN
This pad is DC-coupled and matched to 50 Ω.
9
RFOUT + VDD (optional)
This pin is matched to 50 Ω and can be used to bias VDD.
14
VG1
Gate control for amplifier. Adjust to achieve IDD = 60
mA.
4, 5, 6
VD1, VD1A, VD1B
Low-frequency termination. Connect bypass capacitors
per application circuit below. (no bias necessary)
11, 12
VG1A, VG1B
Low-frequency termination. Connect bypass capacitors
per application circuit below. (no bias necessary)
1, 3, 7, 8, 10, 13
GND
Die bottom must be connected to RF/DC ground.
Backside Paddle
RF/DC GND
RF/DC ground.
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4.4 Assembly Drawing
The following figure shows the assembly diagram of the MMA040AA device. In the die test assembly
shown, both RFIN and RFOUT ports should utilize bias tees or DC blocks to isolate external circuits
from the IC. VDD to the MMA040AA die is supplied through DC bypass caps of >10 nF (the actual
value depends on the low-frequency bandwidth requirements of the application).
Figure 20 Assembly Diagram
Table 5 Bias Sequence
Bias Sequence
1) Set the gate voltage VG1 to -1V
2) Set drain voltage VDD to 8V
3) Adjust the gate voltage until the drain current is 60mA
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5 Handling and Die Attachment Recommendations
Gallium arsenide integrated circuits are sensitive to electrostatic discharge (ESD) and can be
damaged by static electricity. It is recommended to follow all procedures and guidelines outlined in
the Microsemi application note AN01 GaAs MMIC Handling and Die Attach Recommendations.
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6 Ordering Information
The following table shows the ordering information for the MMA040AA device.
Table 6 Ordering Information
Part Number
Package
MMA040AA
Die
