LM20124MHENOPB - NATIONAL SEMICONDUCTOR

LM1973

LM1973 µPot3-Channel 76dB Audio Attenuator with Mute

Literature Number: SNAS093A

LM1973

µPot™3-Channel 76dB Audio Attenuator with Mute

General Description

The LM1973 is a digitally controlled 3-channel 76dB audio

attenuator fabricated on a CMOS process. Each channel

has attenuation steps of 0.5dB from 0dB–15.5dB, 1.0dB

steps from 16dB–47dB, and 2.0dB steps from 48dB– 76dB,

with a mute function attenuating 104dB. Its logarithmic at-

tenuation curve can be customized through software to fit

the desired application.

The performance of a µPot™is demonstrated through its

excellent Signal-to-Noise Ratio, extremely low (THD+N),

and high channel separation. Each µPot contains a mute

function that disconnects the input signal from the output,

providing a minimum attenuation of 96dB. Transitions be-

tween any attenuation settings are pop free.

The LM1973’s 3-wire serial digital interface is TTL and

CMOS compatible; receiving data that selects a channel and

the desired attenuation level. The Data-Out pin of the

LM1973 allows multiple µPots to be daisy-chained together,

reducing the number of enable and data lines to be routed

for a given application.

Key Specifications

nTotal Harmonic Distortion + Noise: 0.003% (max)

nFrequency response: 100 kHz (−3dB) (min)

nAttenuation range (excluding mute): 76dB (typ)

nDifferential attenuation: ±0.25dB (max)

nSignal-to-noise ratio (ref. 4 Vrms): 110dB (min)

nChannel separation: 110dB (typ)

Features

n3-wire serial interface

nDaisy-chain capability

n104dB mute attenuation

nPop and click free attenuation changes

Applications

nAutomated studio mixing consoles

nMusic reproduction systems

nSound reinforcement systems

nElectronic music (MIDI)

nPersonal computer audio control

Typical Application Connection Diagram

Dual-In-Line Plastic or

Surface Mount Package

01195802

Top View

Order Number LM1973M or LM1973N

See NS Package Number M20B or N20A

µPot™and Overture™are trademarks of National Semiconductor Corporation.

01195801

FIGURE 1. Typical Audio Attenuator

Application Circuit

December 1994

LM1973 µPot 3-Channel 76dB Audio Attenuator with Mute

Absolute Maximum Ratings (Notes 1,

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

Supply Voltage (V

–V

) 15V

Voltage at Any Pin V

− 0.2V to V

+ 0.2V

Power Dissipation (Note 3) 150 mW

ESD Susceptability (Note 4) 1800V

Junction Temperature 150˚C

Soldering Information

N Package (10 sec.) +260˚C

Storage Temperature −65˚C to +150˚C

Operating Ratings (Notes 1, 2)

MIN

MAX

Temperature Range

MIN

≤T

MAX

0˚C ≤T

≤+70˚C

Supply Voltage (V

−V

) 4.5V to 12V

Electrical Characteristics (Notes 1, 2)

The following specifications apply for all channels with V

= +6V, V

= −6V, V

= 5.5 Vpk, andf=1kHz, unless otherwise

specified. Limits apply for T

= 25˚C. Digital inputs are TTL and CMOS compatible.

Symbol Parameter Conditions LM1973 Units

(Limits)

Typical Limit

(Note 5) (Note 6)

Supply Current Inputs are AC Grounded 3 5 mA (max)

THD+N Total Harmonic Distortion

plus Noise

= 0.5 Vpk @0dB Attenuation 0.0008 0.003 % (max)

XTalk Crosstalk (Channel Separation) 0dB Attenuation for V

110 dB

(Note 7) V

measured @−76dB

SNR Signal-to-Noise Ratio Inputs are AC Grounded

@−12dB Attenuation 120 110 dB (min)

A-Weighted

Mute Attenuation 104 96 dB (min)

Attenuation Step Size Error 0dB to −16dB ±0.05 dB (max)

−17dB to −48dB ±0.1 dB (max)

−49dB to −76dB ±0.25 dB (max)

Absolute Attenuation Error Attenuation @0dB 0.01 0.5 dB (min)

Attenuation @−20dB 19.8 19.0 dB (min)

Attenuation @−40dB 39.5 38.5 dB (min)

Attenuation @−60dB 59.3 58.0 dB (min)

Attenuation @−76dB 74.5 73.0 dB (min)

Channel-to-Channel Attenuation Attenuation @0dB, −20dB, −40dB, −60dB ±0.5 dB (max)

Tracking Error Attenuation @−76dB ±0.75 dB (max)

LEAK

Analog Input Leakage Current Inputs are AC Grounded 10.0 100 nA (max)

AC Input Impedance Pins 2, 4, 18, V

=1.0Vpk,f=1kHz 40 20 kΩ(min)

60 kΩ(max)

Input Current @Pins 9, 10, 11 @0V <V

<5V 1.0 ±100 nA (max)

CLK

Clock Frequency 3 2 MHz (max)

High-Level Input Voltage @Pins 9, 10, 11 2.0 V (min)

Low-Level Input Voltage @Pins 9, 10, 11 0.8 V (max)

Data-Out Levels (Pin 12) V

=6V, V

=0V 0.1 V (max)

5.9 V (min)

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is

functional, but do not guarantee specific performance limits. Electrical Characteristics state DC and AC electrical specifications under particular test conditions which

guarantee specific performance limits. This assumes that the device is within the Operating Ratings. Specifications are not guaranteed for parameters where no limit

is given, however, the typical value is a good indication of device performance.

Note 2: All voltages are measured with respect to GND (pins 1, 3, 5, 14, 17), unless otherwise specified.

Note 3: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX,θJA, and the ambient temperature TA. The maximum

allowable power dissipation is PD = (TJMAX −T

A)/θJA or the number given in the Absolute Maximum Ratings, whichever is lower. For the LM1973N, TJMAX = +150˚C,

and the typical junction-to-ambient thermal resistance, when board mounted, is 65˚C/W.

Note 4: Human body model, 100 pF discharged through a 1.5 kΩresistor.

Note 5: Typicals are measured at 25˚C and represent the parametric norm.

LM1973

www.national.com 2

Electrical Characteristics (Notes 1, 2) (Continued)

Note 6: Limits are guaranteed to National’s AOQL (Average Output Quality Level).

Note 7: At the present time the Crosstalk measurement is specified as a typical only, which is due to a hardware limitation of the automated test equipment.

Timing Diagram

Pin Descriptions

Signal Ground (1, 5, 17): Each input has its own indepen-

dent ground, GND1, GND2, and GND3.

Signal Input (2, 4, 18): There are 3 independent signal

inputs, IN1, IN2, and IN3.

Signal Output (6, 16, 20): There are 3 independent signal

outputs, OUT1, OUT2, and OUT3.

Voltage Supply (13, 15): Positive voltage supply pins, V

DD1

and V

DD2

Voltage Supply (7, 19): Negative voltage supply pins, V

SS1

and V

SS2

. To be tied to ground in a single supply configura-

tion.

AC Ground (3, 14): These two pins are not physically con-

nected to the die in any way (i.e., No bondwires). These pins

must be AC grounded to prevent signal coupling between

any of the pins nearby. Pin 14 should be connected to pins

13 and 15 for ease of wiring and the best isolation.

Logic Ground (8): Digital signal ground for the interface

lines; CLOCK, LOAD/SHIFT, DATA-IN and DATA-OUT.

Clock (9): The clock input accepts a TTL or CMOS level

signal. The clock input is used to load data into the internal

shift register on the rising edge of the input clock waveform.

Load/Shift (10): The load/shift input accepts a TTL or

CMOS level signal. This is the enable pin of the device,

allowing data to be clocked in while this input is low (0V).

Data-In (11): The data-in input accepts a TTL or CMOS level

signal. This pin is used to accept serial data from a micro-

controller that will be latched and decoded to change a

channel’s attenuation level.

Data-Out (12): This pin is used in daisy-chain mode where

more than one µPot is controlled via the same data line. As

the data is clocked into the chain from the µC, the preceding

data in the shift register is shifted out the DATA-OUT pin to

the next µPot in the chain or to ground if it is the last µPot in

the chain. The LOAD/SHIFT line goes high once all of the

new data has been shifted into each of its respective regis-

ters.

Connection Diagram

01195802

01195803

FIGURE 2. Timing Diagram

LM1973

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Typical Performance Characteristics

Supply Current vs

Supply Voltage

Supply Current vs

Temperature

01195816 01195817

Noise Floor Spectrum by FFT

Amplitude vs Frequency

THD vs Freq by FFT

−V

= 12V

01195818 01195819

THD vs V

OUT

1 kHz by FFT

−V

= 12V Crosstalk Test

01195820 01195821

LM1973

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Typical Performance Characteristics (Continued)

THD+Nvs

Frequency and Amplitude FFT of 1 kHz THD

01195822 01195823

FFT of 20 kHz THD

THD+NvsAmplitude

f=20Hz,V

=±6V

into CH1 @0dB

01195824 01195825

THD+NvsAmplitude

f = 1 kHz, V

=±6V

into CH1 @0dB

THD+NvsAmplitude

f = 20 kHz, V

=±6V

into CH1 @0dB

01195826 01195827

LM1973

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Application Information

ATTENUATION STEP SCHEME

The fundamental attenuation step scheme for the LM1973

µPot is shown in Figure 3. This attenuation step scheme,

however, can be changed through programming techniques

to fit different application requirements. One such example

would be a constant logarithmic attenuation scheme of 2dB

steps for a panning function as shown in Figure 5. The only

restriction to the customization of attenuation schemes are

the given attenuation levels and their corresponding data

bits shown in Table 1. The device will change attenuation

levels only when a channel address is recognized. When

recognized, the attenuation level will be changed corre-

sponding to the data bits shown in Table 1. As shown in

Figure 6, an LM1973 can be configured with a mono audio

signal level control and with a panning control which sepa-

rates the mono signal into left and right channels. This circuit

may utilize the fundamental attenuation scheme of the

LM1973 for the level control, but also possess a constant

2dB panning control for the left and right channels as stated

earlier.

LM1973 Channel Attenuation

vs Digital Step Value

01195807

FIGURE 3. LM1973 Attenuation Step Scheme

LM1973 Channel Attenuation

vs Digital Step Value

(Programmed 1.0dB Steps)

01195814

FIGURE 4. LM1973 1.0dB and 2.0dB

Attenuation Step Scheme

LM1973 Channel Attenuation

vs Digital Step Value

(Programmed 2.0dB Steps)

01195815

FIGURE 5. LM1973 2.0dB Attenuation Step Scheme

LM1973

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Application Information (Continued)

INPUT IMPEDANCE

The input impedance of a µPot is constant at a nominal

40 kΩ. To eliminate any unwanted DC components from

propagating through the device it is common to use 1 µF

input coupling caps. This is not necessary, however, if the dc

offset from the previous stage is negligible. For higher per-

formance systems, input coupling caps are preferred.

OUTPUT IMPEDANCE

The output of a µPot varies typically between 25 kΩand

35 kΩand changes nonlinearly with step changes. Since a

µPot is made up of a resistor ladder network with a logarith-

mic attenuation, the output impedance is nonlinear. Due to

this configuration, a µPot cannot be considered as a linear

potentiometer, but can be considered only as a logarithmic

attenuator.

It should be noted that the linearity of a µPot cannot be

measured directly without a buffer because the input imped-

ance of most measurement systems is not high enough to

provide the required accuracy. Due to the low impedance of

the measurement system, the output of the µPot would be

loaded down and an incorrect reading will result. To prevent

loading from occurring, a JFET input op amp should be used

as the buffer/amplifier. The performance of a µPot is limited

only by the performance of the external buffer/amplifier.

MUTE FUNCTION

One major feature of a µPot is its ability to mute the input

signal to an attenuation level of 104dB as shown in Figure 3.

This is accomplished internally by physically isolating the

output from the input while also grounding the output pin

through approximately 2 kΩ.

The mute function is obtained during power-up of the device

or by sending any binary data of 01001111 and above (to

11111111) serially to the device. The device may be placed

into mute from a previous attenuation setting by sending any

of the above data. This allows the designer to place a mute

button onto his system which could cause a microcontroller

to send the appropriate data to a µPot and thus mute any or

all channels. Since this function is achieved through soft-

ware, the designer has a great amount of flexibility in con-

figuring the system.

DC INPUTS

Although the µPot was designed to be used as an attenuator

for signals within the audio spectrum, the device is capable

of tracking an input DC voltage. The device will track DC

voltages to a diode drop above each supply rail.

One point to remember about DC tracking is that with a

buffer at the output of the µPot, the resolution of DC tracking

will depend upon the gain configuration of that output buffer

and its supply voltage. It should also be remembered that the

output buffer’s supply voltage does not have to be the same

as the µPot’s supply voltage. This could allow for more

resolution when DC tracking.

SERIAL DATA FORMAT

The LM1973 uses a 3-wire serial communication format that

is easily controlled by a microcontroller. The timing for the

3-wire set, comprised of DATA-IN, CLOCK, and LOAD/

SHIFT is shown in Figure 2.Figure 9 exhibits in block

diagram form how the digital interface controls the tap

switches which select the appropriate attenuation level. As

depicted in Figure 2, the LOAD/SHIFT line is to go low at

least 150 ns before the rising edge of the first clock pulse

and is to remain low throughout the transmission of each set

of 16 data bits. The serial data is comprised of 8 bits for

channel selection and 8 bits for attenuation setting. For both

address data and attenuation setting data, the MSB is sent

first and the 8 bits of address data are to be sent before the

8 bits of attenuation data. Please refer to Figure 7 to confirm

the serial data format transfer process.

01195808

FIGURE 6. Mono Level Control with Panning Circuit

01195809

FIGURE 7. Serial Data Format Transfer Process

LM1973

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Application Information (Continued)

TABLE 1. LM1973 Micropot Attenuator

MSB: LSB

Address Register (Byte 0)

0000 0000 Channel 1

0000 0001 Channel 2

0000 0010 Channel 3

Data Register (Byte 1)

Contents Attenuation Level dB

0000 0000 0.0

0000 0001 0.5

0000 0010 1.0

0000 0011 1.5

::::: ::

0001 1110 15.0

0001 1111 15.5

0010 0000 16.0

0010 0001 17.0

0010 0010 18.0

::::: ::

0011 1110 46.0

0011 1111 47.0

0100 0000 48.0

0100 0001 50.0

0100 0010 52.0

::::: ::

0100 1100 72.0

0100 1101 74.0

0100 1110 76.0

0100 1111 100.0 (Mute)

0101 0000 100.0 (Mute)

::::: ::

1111 1110 100.0 (Mute)

1111 1111 100.0 (Mute)

µPot SYSTEM ARCHITECTURE

The µPot’s digital interface is essentially a shift register,

where serial data is shifted in, latched, and then decoded. As

new data is shifted into the DATA-IN pin, the previously

latched data is shifted out the DATA-OUT pin. Once the data

is shifted in, the LOAD/SHIFT line goes high, latching in the

new data. The data is then decoded and the appropriate

switch is activated to set the desired attenuation level for the

selected channel. This process is continued each and every

time an attenuation change is made. Each channel is up-

dated, only, when that channel is selected for an attenuator

change or the system is powered down and then back up

again. When the µPot is powered up, each channel is placed

into the muted mode.

µPot LADDER ARCHITECTURE

Each channel of a µPot has its own independent resistor

ladder network. As shown in Figure 8, the ladder consists of

multiple R1/R2 elements which make up the attenuation

scheme. Within each element there are tap switches that

select the appropriate attenuation level corresponding to the

data bits in Table 1. It can be seen in Figure 8 that the input

impedance for the channel is a constant value regardless of

which tap switch is selected, while the output impedance

varies according to the tap switch selected.

DIGITAL LINE COMPATIBILITY

The µPot’s digital interface section is compatible with either

TTL or CMOS logic due to the shift register inputs acting

upon a threshold voltage of 2 diode drops or approximately

1.4V.

DIGITAL DATA-OUT PIN

The DATA-OUT pin is available for daisy-chain system con-

figurations where multiple µPots will be used. The use of the

daisy-chain configuration allows the system designer to use

only one DATA and one LOAD/SHIFT line per chain, thus

simplifying PCB trace layouts.

In order to provide the highest level of channel separation

and isolate any of the signal lines from digital noise, the

DATA-OUT pin should be terminated througha2kΩresistor

if not used. The pin may be left floating, however, any signal

noise on that line may couple to adjacent lines creating

higher noise specs.

01195811

FIGURE 8. µPot Ladder Architecture

LM1973

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Application Information (Continued)

DAISY-CHAIN CAPABILITY

Since the µPot’s digital interface is essentially a shift register,

multiple µPots can be programmed utilizing the same data

and load/shift lines. As shown in Figure 11, for an n-µPot

daisy-chain, there are 16n bits to be shifted and loaded for

the chain. The data loading sequence is the same for

n-µPots as it is for one µPot. First the LOAD/SHIFT line goes

low, then the data is clocked in sequentially while the pre-

ceding data in each µPot is shifted out the DATA-OUT pin to

the next µPot in the chain or to ground if it is the last µPot in

the chain. Then the LOAD/SHIFT line goes high; latching the

data into each of their corresponding µPots. The data is then

decoded according to the address (channel selection) and

the appropriate tap switch controlling the attenuation level is

selected.

CROSSTALK MEASUREMENTS

The crosstalk of a µPot as shown in the Typical Perfor-

mance Characteristics section was obtained by placing a

signal on one channel and measuring the level at the output

of another channel of the same frequency. It is important to

be sure that the signal level being measured is of the same

frequency such that a true indication of crosstalk may be

obtained. Also, to ensure an accurate measurement, the

measured channel’s input should be AC grounded through a

1 µF capacitor.

CLICKS AND POPS

So, why is that output buffer needed anyway? There are

three answers to this question, all of which are important

from a system point of view.

The first reason to utilize a buffer/amplifier at the output of a

µPot is to ensure that there are no audible clicks or pops due

to attenuation step changes in the device. If an on-board

bipolar op amp had been used for the output stage, its

requirement of a finite amount of DC bias current for opera-

tion would cause a DC voltage “pop” when the output imped-

ance of the µPot changes. Again, this phenomenon is due to

the fact that the output impedance of the µPot is changing

with step changes and a bipolar amplifier requires a finite

amount of DC bias current for its operation. As the imped-

ance changes, so does the DC bias current and thus there is

a DC voltage “pop”.

Secondly, the µPot has no drive capability, so any desired

gain needs to be accomplished through a buffer/non-

inverting amplifer.

Third, the output of a µPot needs to see a high impedance to

prevent loading and subsequent linearity errors from ocur-

ring. A JFET input buffer provides a high input impedance to

the output of the µPot so that this does not occur.

Clicks and pops can be avoided by using a JFET input

buffer/amplifier such as an LF412ACN. The LF412 has a

high input impedance and exhibits both a low noise floor and

low THD+N throughout the audio spectrum which maintains

signal integrity and linearity for the system. The performance

of the system solution is entirely dependent upon the quality

and performance of the JFET input buffer/amplifier.

LOGARITHMIC GAIN AMPLIFIER

The µPot is capable of being used in the feedback loop of an

amplifier, however, as stated previously, the output of the

µPot needs to see a high impedance in order to maintain its

high performance and linearity. Again, loading the output will

change the values of attenuation for the device. As shown in

Figure 10, a µPot used in the feedback loop creates a

logarithmic gain amplifier. In this configuration the attenua-

tion levels from Table 1, now become gain levels with the

largest possible gain value being 76dB. For most applica-

tions 76dB of gain will cause signal clipping to occur, how-

ever, because of the µPot’s versatility the gain can be con-

trolled through programming such that the clipping level of

the system is never obtained. An important point to remem-

ber is that when in mute mode the input is disconnected from

the output. In this configuration this will place the amplifier in

its open loop gain state, thus resulting in severe comparator

action. Care should be taken with the programming and

design of this type of circuit. To provide the best perfor-

mance, a JFET input amplifier should be used.

01195810

FIGURE 9. µPot System Architecture

LM1973

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Application Information (Continued)

01195813

FIGURE 10. Digitally-Controlled Logarithmic Gain Amplifier Circuit

01195812

FIGURE 11. n-µPot Daisy-Chained Circuit

LM1973

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Physical Dimensions inches (millimeters) unless otherwise noted

Surface Mount Package

Order Number LM1973M

NS Package Number M20B

Dual-In-Line Plastic Package

Order Number LM1973N

NS Package Number N20A

LM1973

www.national.com11

Notes

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves

the right at any time without notice to change said circuitry and specifications.

For the most current product information visit us at www.national.com.

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NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS

WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR

CORPORATION. As used herein:

1. Life support devices or systems are devices or systems

which, (a) are intended for surgical implant into the body, or

(b) support or sustain life, and whose failure to perform when

properly used in accordance with instructions for use

provided in the labeling, can be reasonably expected to result

in a significant injury to the user.

2. A critical component is any component of a life support

device or system whose failure to perform can be reasonably

expected to cause the failure of the life support device or

system, or to affect its safety or effectiveness.

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National Semiconductor certifies that the products and packing materials meet the provisions of the Customer Products Stewardship

Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification (CSP-9-111S2) and contain no ‘‘Banned

Substances’’ as defined in CSP-9-111S2.

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www.national.com

LM1973 µPot 3-Channel 76dB Audio Attenuator with Mute

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