345-6 [ 24S He (MA) MOTOROLA DUAL DECADE COUNTER; DUAL 4-STAGE BINARY COUNTER The SN54/74LS390 and SN54/74LS$393 each containapair: high-speed 4-stage ripple counters. Each half of the LS390 is parti: ned into a divide-by-two section and a divide-by five section, with a separ > clock input for each section. The two sections can be connected to count 1 the 8.4.2.1 BCD code or they can countin a biquinary sequence to provide: ;quare wave (50% duty cycle) at the final output. Each half of the LS393 operates as a Modulo-16 binary divide with the last three stages triggered in a ripple fashion. In both the LS390 ar j the LS393, the flip-flops are triggered by a HIGH-to-LOW transition of th + CP inputs. Each half of each circuit type has a Master Reset input which :sponds toa HIGH signal by forcing all four outputs to the LOW state. Dual Versions of LS290 and LS293 S390 has Separate Clocks Allowing +2, +2.5, +5 Individual Asynchronous Clear for Each Counter Typical Max Count Frequency of 50 MHz * Input Clamp Diodes Minimize High Speed Termination Effe ts CONNECTION DIAGRAM DIP (TOP VIEW) SN54/74LS390 Vcc CPp MR Qo CP} GQ; G2 Qy fis] Lis] Ge] fis] fe] fi) fro] Fo) ) NOTE: The Fiatp: version has the sae pinouts __SN54/74LS393 (Connectic Diagram) as Voc CP MR Qp QQ; Q2 Q3 the Dual Ir .ine Package. (a) fa] fre] fi] fro] fo] fe] ) Loy t2] Let Led Let Led iJ cP MR Qo Q; Qs Qq GND SN54/74LS390 SN54/74LS393 DUAL DECADE COUNTER; DUAL 4-STAGE BINARY COUNTER LOW POWER SCHOTTKY Ne J SUFFIX i CERAMIC CASE 620-09 1 5 N SUFFIX PLASTIC 16 CASE 648-08 D SUFFIX SOIC CASE 7518-03 LE 1 - J SUFFIX IK CERAMIC 4 CASE 632-08 4 1 N SUFFIX PLASTIC CASE 646-06 = CASE 751A-02 P D SUFFIX ; LS SOIC 1 ORDERING INFORMATION SNS54LSXXXJ_ ss Ceramic SN74LSXXXN_ Plastic SN74LSXXXD = SOIC FAST Af DLS TTL DATA 5-340 SN54/74LS390 SN 34/74LS393 PIN NAMES Clock (Active LOW going edge) Input to +16 (LS393) LOADING (Note a) HIGH LOW 0.5 ULL. 1OUL. OSUL. 1.0ULL, 0.5 ULL. 15ULL, O.5 UL. 0.25 UL. WOUL. | 5 (2.5) UL. CP9 Clock (Active LOW going edge) Input to +2 (LS390) CP, Clock (Active LOW going edge) Input to ~5 (LS390) MR Master Reset (Active HIGH) input Qg-O3 Flip-Flop outputs (Note 6) NOTES. a) 1 TTL Unit Load (U.L.) = 40 LA HIGH/1.6 mA LOW. b) The Output LOW drive factor ts 2.5 U L. for Military ( Temperature Ranges. FUNCTIONAL DESCRIPTION Each half of the SN54/74LS393 operates in the Modulo 16 binary sequence, as indicated in the + 16 Truth Table. The first flip-flop is triggered by HIGH-to-LOW transitions of the CP input signal. Each of the other flip-flops is triggered by a HIGH-to-LOW transition of the Q output of the preceding flip-flop. Thus state changes of the Q outputs do not occur simultaneously. This means that logic signals derived from combinations of these outputs will be subject to decoding spikes and, therefore, should not be used as clocks for other counters, registers or flip-flops. A HIGH signal on MR forces all outputs to the LOW state and prevents counting. Each half of the LS390 contains a +5 section that is independent except for the common MR function. The +5 s Th cy fur Sit Q int co By th. de te Le SN54/74LS390 LOGIC DIAG: CP )and 5 UL. for Commercial (74) ion operates in 4.2.1 binary sequence, as shown inthe +5 h Table, with the third stage output exhibiting a 20% duty e when the input frequency is constant. To obtain a +10 tion having a 50% duty cycle output, connect the input lal to CP and connect the Q3 output to the CP9 input; the output provides the desired 50% duty cycle output. if the it frequency is connected to CPg and the Qo output is nected to CP, a decade divider operating in the 8.4.2.1 ) code is obtained, as shown in the BCD Truth Table. Since flip-flops change state asynchronously, logic signals ved from combinations of LS390 outputs are also subject ecoding spikes. A HIGH signal on MR forces all outputs N and prevents counting. AM (one half shown) K CP J K cP J K cP J K CP y Cp Q Cp Q Cp 4 Cp vA be i_. Qq Qy Qe Q3 $N54/74LS393 LOGIC DIAGRH .M (one half shown) CP K cP J K CP J K CP J K CP J Cc Cc c C 0 Q D Q D 0 D Q MR De ~~ Qo Qy Qs Q3 FAST AND LST L DATA 5-341 SN54/74LS390 3N54/74LS393 SN54/74LS390 BCD SN54/74L 390-5 SN54/74L5393 TRUTH TABLE _ TRUTH * \BLE TRUTH TABLE (Input on CPg; Qg CP1} (Input or CPt) OUTPUTS ( ITPUTS OUTPUTS COUNT COUNT - COUNT Q3 | G2 | Qy | Qo Q: Qg{ Qy Q3} Qa} Q;1 | Qo 0 byeere Ye 0 Lo ob PL 0 Li bLyYL|L i 1 Lyk L H 1 {. L H 1 L L L H 2 Li} beEP_H EL 2 Lp aH P_eL 2 LJYtLIJHEL 3 L HJ] H 3 L L H H 3 Ly] ue ]H]H 4 el ede 4 LT} HEE EL 4 LyVHEL EL 5 L H L H 5 L H L H > Topep ele eS] cpRye ys yoy ty yaa SN54/74LS390 10 (50% @ Qo) 8 Hi UTE EL : 8 H} LIL IL TRUTH ABLE 9 Hit itt |H 9 H{ LCL] LH (Inputon CF Q3 to CPo} {0 Hi CLHIEL UTPUTS uN HJ} bP] H COUNT Q. alala 12 HIT H]JLYIL 3, 2, 3 |H|HI LIA 0 boo L L 14 H H H L { booby HT et 1 [HHT AHH 2 L HILAL 3 L HHI L 4 H L L L H = HIGH Voltage Level 5 L i L 4 L = LOW Voltage Level L bLyH{H 7 L HyLIH 8 L HYJHIH 9 H L L H GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit Voc Supply Voltage 54 4.5 5.0 5.5 v 74 4.75 5.0 .25 TA Operating Ambient Temperature Range 54 55 25 125 C 74 0 25 70 lOH Output Current High 54, 74 -0.4 mA lot Output Current Low 54 4.0 mA 74 8.0 FAST AN )LS TTL DATA 3-342 SN54/74LS390 SNE 1/74LS393 OC CHARACTERISTICS OVER OPERATING TEMPERATURE RANC : (unless otherwise specified) Limits Symbol Parameter Min Typ Ma Unit Test Conditions d Input HIGH Voit f Vi input HIGH Voltage 2.0 V Al inputs | nput HIGH Voltage for Vv input LOW Voltage 34 0. Vv Guaranteed Input LOW Voltage for IL Pp g 74 0. Alf Inputs ViK Input Clamp Diode Voltage -0.65 { ~!: Vv Voc = MIN, tq =-18 mA 54 2.5 3.5 Vv Voc = MIN, lon = MAX, Vin = cc 1OH = > IN = IH VOH Output HIGH Voltage 74 7 35 V or Vi. per Truth Table 54, 74 0.25 C Vv jou = 4.0 mA Voc = Vcc MIN, Vou Output LOW Voltage Vin = ViL or Vi 74 0.35 0 Vv lou = 8.0 mA per Truth Table pA Voc = MAX, Vin = 2.7 V hH input HIGH Current - 0 mA Vcc = MAX, Vin = 7.0 V MR =( 4 mA hie Input LOW Current CP CPo - 6 mA | Voc = MAX, Vin =0.4V CPy - 4 mA los Short Circuit Current (Note 1) ~-20 - 0 mA Voc = MAX lec Power Supply Current i mA | Voc = MAX Note 1. Not mare than one qutput should be shorted at a time, nor far mare than 1 seconci AC CHARACTERISTICS (Ta = 25C, Voc = 5.0 V) Limits Symboi Parameter Min Typ hx Unit Test Conditions Maximum Clock Frequency MAX CP to Ag 25 35 MHz Maximum Clock Frequency fMAX CP} to, 20 MHz tPLH Propagation Delay, 12 ) ns tPHL CP to Qq LS393 13 ) tPLH = 12 J tPHL CPq to Qg LS390 13 5 ns 'PLH = 40 J CP toQ LS393 ns {PHL 3 40 0 CL = 15 pF tPLH = 37 0 (PHL CPg to Qe LS390 39 0 ns tPLH aS 13 1 tPHL CP; to Qy LS390 14 4 ns tPLH aS 24 9 (PHL CPy to Qo LS390 26 9 ns tPLH = 13 i tPHL MR to Any Output LS390/393 24 19 ns FAST AND LS T ~ DATA 5-343 . SN54/74LS39) ) SN54/74LS393 AC SETUP REQUIREMENTS (Ta = 25C, Voc = 50 V) Limits Symbol Parameter Min Typ i Test Conditions tw Clock Puise Width LS393 20 tw CPg Pulse Width LS390 20 tw CP Pulse Width LS390 40 tw MR Pulse Width LS390/393 20 trac Recovery Time LS390/393 25 AC 'AVEFORMS cP 13V . , 13V 7 fe ty PHL r 'PLH e 13V 13V Figure t MA & MS Ee Noe Q ke 1.9V / Figure 2 The number af Clock Pulses required between tpyy, an: pi} Measurements can be determined from the appropnate Truth Table. FAST AND LS TTL DATA 5-344