DAC8532 SBAS246A - DECEMBER 2001 - MAY 2003 Dual Channel, Low Power, 16-Bit, Serial Input DIGITAL-TO-ANALOG CONVERTER FEATURES DESCRIPTION microPOWER OPERATION: 500A at 5V POWER-ON RESET TO ZERO-SCALE POWER SUPPLY: +2.7V to +5.5V 16-BIT MONOTONIC OVER TEMPERATURE SETTLING TIME: 10s to 0.003% FSR ULTRA-LOW AC CROSSTALK: -100dB typ LOW-POWER SERIAL INTERFACE WITH SCHMITT-TRIGGERED INPUTS ON-CHIP OUTPUT BUFFER AMPLIFIER WITH RAIL-TO-RAIL OPERATION DOUBLE BUFFERED INPUT ARCHITECTURE SIMULTANEOUS OR SEQUENTIAL OUTPUT UPDATE AND POWERDOWN TINY MSOP-8 PACKAGE The DAC8532 is a dual channel, 16-bit Digital-to-Analog Converter (DAC) offering low power operation and a flexible serial host interface. Each on-chip precision output amplifier allows rail-to-rail output swing to be achieved over the supply range of 2.7V to 5.5V. The device supports a standard 3-wire serial interface capable of operating with input data clock frequencies up to 30MHz for VDD = 5V. The DAC8532 requires an external reference voltage to set the output range of each DAC channel. Also incorporated into the device is a power-on reset circuit which ensures that the DAC outputs power up at zero-scale and remain there until a valid write takes place. The DAC8532 provides a flexible power-down feature, accessed over the serial interface, that reduces the current consumption of the device to 200nA at 5V. The low-power consumption of this device in normal operation makes it ideally suited to portable battery-operated equipment and other low-power applications. The power consumption is 2.5mW at 5V, reducing to 1W in powerdown mode. APPLICATIONS PORTABLE INSTRUMENTATION CLOSED-LOOP SERVO-CONTROL PROCESS CONTROL DATA ACQUISITION SYSTEMS PROGRAMMABLE ATTENUATION PC PERIPHERALS The DAC8532 is available in a MSOP-8 package with a specified operating temperature range of -40C to +105C. VDD VREF Data Buffer A DAC Register A DAC A VOUTA Data Buffer B DAC Register B DAC B VOUTB Channel Select Load Control 16 SYNC SCLK DIN 24-Bit Serial-toParallel Shift Register 8 Control Logic Power-Down Control Logic 2 Resistor Network GND Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright (c) 2001-2003, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. www.ti.com ELECTROSTATIC DISCHARGE SENSITIVITY ABSOLUTE MAXIMUM RATINGS(1) VDD to GND ........................................................................... -0.3V to +6V Digital Input Voltage to GND ................................. -0.3V to +VDD + 0.3V VOUTA or VOUTB to GND .......................................... -0.3V to +VDD + 0.3V Operating Temperature Range ...................................... -40C to +105C Storage Temperature Range ......................................... -65C to +150C Junction Temperature Range (TJ max) ........................................ +150C Power Dissipation ........................................................ (TJ max -- TA)/JA JA Thermal Impedance ......................................................... 206C/W JC Thermal Impedance .......................................................... 44C/W Lead Temperature, Soldering: Vapor Phase (60s) ............................................................... +215C Infrared (15s) ........................................................................ +220C This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. NOTE: (1) Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. PACKAGE/ORDERING INFORMATION PRODUCT PACKAGE-LEAD PACKAGE DESIGNATOR(1) SPECIFICATION TEMPERATURE RANGE PACKAGE MARKING ORDERING NUMBER TRANSPORT MEDIA, QUANTITY MSOP-8 DGK -40C to +105C D32E " " " " DAC8532IDGK DAC8532IDGKR Tube, 80 Tape and Reel, 2500 DAC8532 NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com. ELECTRICAL CHARACTERISTICS VDD = +2.7V to +5.5V. -40C to +105C, unless otherwise specified. DAC8532 PARAMETER CONDITIONS MIN TYP MAX UNITS PERFORMANCE (1) STATIC Resolution Relative Accuracy Differential Nonlinearity Zero-Scale Error Full-Scale Error Gain Error Zero-Scale Error Drift Gain Temperature Coefficient Channel-to-Channel Matching PSRR OUTPUT CHARACTERISTICS (2) Output Voltage Range Output Voltage Settling Time Slew Rate Capacitive Load Stability Code Change Glitch Impulse Digital Feedthrough DC Crosstalk AC Crosstalk DC Output Impedance Short-Circuit Current Power-Up Time AC PERFORMANCE 16 16-Bit Monotonic +5 -0.15 20 5 15 0.75 RL = 2k, CL = 200pF 0 To 0.003% FSR 0200H to FD00H RL = 2k; 0pF < CL < 200pF RL = 2k; CL = 500pF RL = RL = 2k 1LSB Change Around Major Carry VDD = +5V VDD = +3V Coming Out of Power-Down Mode VDD = +5V Coming Out of Power-Down Mode VDD = +3V 8 12 1 470 1000 20 0.5 0.25 -100 1 50 20 0.0987 1 +25 -1.0 1.0 Bits % of FSR LSB mV % of FSR % of FSR V/C ppm of FSR/C mV mV/V VREF V 10 s -96 s V/s pF pF nV-s nV-s LSB dB mA mA 2.5 s 5 s 94 67 69 65 dB dB dB dB BW = 20kHz, VDD = 5V FOUT = 1kHz, 1st 19 Harmonics Removed SNR THD SFDR SINAD DAC8532 2 www.ti.com SBAS246A ELECTRICAL CHARACTERISTICS (Cont.) VDD = +2.7V to +5.5V. -40C to +105C, unless otherwise specified. DAC8532 PARAMETER CONDITIONS REFERENCE INPUT Reference Current MIN VREF = VDD = +5V VREF = VDD = +3V Reference Input Range Reference Input Impedance TYP MAX UNITS 67 40 90 54 VDD A A V k 1 0.8 0.6 3 A V V V V pF 5.5 V 0 75 LOGIC INPUTS (2) Input Current VINL, Input LOW Voltage VINL, Input LOW Voltage VINH, Input HIGH Voltage VINH, Input HIGH Voltage Pin Capacitance VDD VDD VDD VDD POWER REQUIREMENTS VDD IDD (normal mode) VDD = +3.6V to +5.5V VDD = +2.7V to +3.6V IDD (all power-down modes) VDD = +3.6V to +5.5V VDD = +2.7V to +3.6V = = = = +5V +3V +5V +3V 2.4 2.1 2.7 DAC Active and Excluding Load Current VIH = VDD and VIL = GND VIH = VDD and VIL = GND 500 450 800 750 A A VIH = VDD and VIL = GND VIH = VDD and VIL = GND 0.2 0.05 1 1 A A ILOAD = 2mA, VDD = +5V 89 POWER EFFICIENCY IOUT/IDD TEMPERATURE RANGE Specified Performance -40 % +105 C NOTES: (1) Linearity calculated using a reduced code range of 485 to 64714; output unloaded. (2) Ensured by design and characterization, not production tested. PIN CONFIGURATION PIN DESCRIPTIONS Top View MSOP-8 VDD 1 VREF 2 VOUTB VOUTA 8 GND 7 DIN 3 6 SCLK 4 5 SYNC DAC8532 PIN DAC8532 SBAS246A NAME DESCRIPTION Power supply input, +2.7V to +5.5V. 1 VDD 2 VREF 3 VOUTB 4 VOUTA Analog output voltage from DAC A. 5 SYNC Level triggered SYNC input (active LOW). This is the frame synchronization signal for the input data. When SYNC goes LOW, it enables the input shift register and data is transferred on the falling edge of SCLK. The action specified by the 8-bit control byte and 16-bit data word is executed following the 24th falling SCLK clock edge (unless SYNC is taken HIGH before this edge in which case the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the DAC8532). 6 SCLK Serial Clock Input. Data can be transferred at rates up to 30 MHz at 5V. 7 DIN Serial Data Input. Data is clocked into the 24-bit input shift register on each falling edge of the serial clock input. 8 GND Ground reference point for all circuitry on the part. Reference voltage input. Analog output voltage from DAC B. 3 www.ti.com TIMING CHARACTERISTICS(1, 2) VDD = +2.7V to +5.5V; all specifications -40C to +105C unless otherwise noted. DAC8532 PARAMETER t1 (3) t2 t3 t4 t5 t6 t7 t8 t9 DESCRIPTION CONDITIONS MIN TYP MAX UNITS VDD = 2.7V to 3.6V VDD = 3.6V to 5.5V 50 33 ns ns VDD = 2.7V to 3.6V VDD = 3.6V to 5.5V 13 13 ns ns VDD = 2.7V to 3.6V VDD = 3.6V to 5.5V 22.5 13 ns ns VDD = 2.7V to 3.6V VDD = 3.6V to 5.5V 0 0 ns ns VDD = 2.7V to 3.6V VDD = 3.6V to 5.5V 5 5 ns ns VDD = 2.7V to 3.6V VDD = 3.6V to 5.5V 4.5 4.5 ns ns VDD = 2.7V to 3.6V VDD = 3.6V to 5.5V 0 0 ns ns VDD = 2.7V to 3.6V VDD = 3.6V to 5.5V 50 33 ns ns VDD = 2.7V to 5.5V 100 ns SCLK Cycle Time SCLK HIGH Time SCLK LOW Time SYNC to SCLK Rising Edge Setup Time Data Setup Time Data Hold Time 24th SCLK Falling Edge to SYNC Rising Edge Minimum SYNC HIGH Time 24th SCLK Falling Edge to SYNC Falling Edge NOTES: (1) All input signals are specified with tR = tF = 5ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. (2) See Serial Write Operation timing diagram, below. (3) Maximum SCLK frequency is 30MHz at VDD = +3.6V to +5.5V and 20MHz at VDD = +2.7V to +3.6V. SERIAL WRITE OPERATION t1 SCLK t9 1 24 t8 t3 t4 t2 t7 SYNC t6 t5 DIN DB23 DB0 DB23 DAC8532 4 www.ti.com SBAS246A TYPICAL CHARACTERISTICS At TA = +25C, unless otherwise noted. LE (LSB) VDD = VREF = 5V, TA = 25C, Channel A Output 2.0 1.5 1.0 0.5 0.0 -0.5 -1.0 -1.5 -2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH 64 48 32 16 0 -16 -32 -48 -64 VDD = VREF = 5V, TA = 25C, Channel B Output 2.0 1.5 1.0 0.5 0.0 -0.5 -1.0 -1.5 -2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code Digital Input Code LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE VDD = VREF = 2.7V, TA = 25C, Channel A Output LE (LSB) 64 48 32 16 0 -16 -32 -48 -64 DLE (LSB) 64 48 32 16 0 -16 -32 -48 -64 LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE 2.0 1.5 1.0 0.5 0.0 -0.5 -1.0 -1.5 -2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH DLE (LSB) DLE (LSB) LE (LSB) DLE (LSB) LE (LSB) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE 64 48 32 16 0 -16 -32 -48 -64 VDD = VREF = 2.7V, TA = 25C, Channel B Output 2.0 1.5 1.0 0.5 0.0 -0.5 -1.0 -1.5 -2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code Digital Input Code ZERO-SCALE ERROR vs TEMPERATURE FULL-SCALE ERROR vs TEMPERATURE 25 15 VDD = VREF VDD = 5V, CH B 10 VDD = 5V, CH A Output Error (mV) Output Error (mV) 20 15 10 VDD = 2.7V, CH B 5 (To avoid clipping of the output signal during the test, VREF = VDD - 10mV) 5 VDD = 2.7V, CH B -5 VDD = 2.7V, CH A -10 VDD = 2.7V, CH A 0 -40 -10 20 50 80 -15 -40 105 Temperature (C) VDD = 5V, CH A -10 20 50 80 105 Temperature (C) DAC8532 SBAS246A VDD = 5V, CH B 0 5 www.ti.com TYPICAL CHARACTERISTICS (Cont.) ABSOLUTE ERROR 30 VDD = VREF = 5V, TA = 25C 25 20 15 Channel B Output 10 5 0 -5 -10 Channel A Output -15 -20 -25 -30 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Output Error (mV) Output Error (mV) At TA = +25C, unless otherwise noted. ABSOLUTE ERROR 30 VDD = VREF = 2.7V, TA = 25C 25 20 15 10 Channel B Output 5 0 -5 -10 Channel A Output -15 -20 -25 -30 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code Digital Input Code HISTOGRAM OF CURRENT CONSUMPTION OUTPUT VOLTAGE DRIFT 2500 VDD = VREF = 5V, Reference Current Included VDD = VREF = 5V, TA = 25C (1C), Digital Code = 7FFFH Frequency VOUT (25V/div) 2000 1500 1000 500 0 400 440 Time (1min/div) 480 520 560 600 640 680 720 760 800 IDD (A) HISTOGRAM OF CURRENT CONSUMPTION SINK CURRENT CAPABILITY 2500 0.15 VDD = VREF = 2.7V, Reference Current Included VREF = VDD - 10mV DAC Loaded with 0000H 0.125 2000 VOUT (V) Frequency 0.1 1500 1000 0.075 VDD = 2.7V 0.05 VDD = 5V 500 0.025 0 0 280 320 360 400 440 480 520 560 600 640 680 0 1 2 3 4 5 ISINK (mA) IDD (A) DAC8532 6 www.ti.com SBAS246A TYPICAL CHARACTERISTICS (Cont.) At TA = +25C, unless otherwise noted. SOURCE CURRENT CAPABILITY 2.7 4.95 2.65 VOUT (V) VOUT (V) SOURCE CURRENT CAPABILITY 5 4.9 4.85 2.6 2.55 VREF = VDD - 10mV DAC Loaded with FFFFH VDD = 5V 4.8 0 1 VREF = VDD - 10mV DAC Loaded with FFFFH VDD = 2.7V 2.5 2 3 4 0 5 1 2 ISOURCE (mA) 700 500 500 IDD (A) IDD (A) 600 400 VDD = VREF = 2.7V 300 400 VDD = VREF = 2.7V 300 200 200 100 100 Reference Current Included, CH A and CH B Active, No Load 0 0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH -40 -10 20 50 80 105 Temperature (C) Digital Input Code SUPPLY CURRENT vs SUPPLY VOLTAGE POWER-DOWN CURRENT vs SUPPLY VOLTAGE 800 50 VREF = VDD, Both DACs Active, Reference Current Included, No Load Reference Current Excluded 45 40 700 35 650 IDD (nA) IDD (A) 5 VDD = VREF = 5V VDD = VREF = 5V 600 600 550 TA = +105C TA = -40C 30 25 20 TA = +25C 15 500 10 450 400 4 SUPPLY CURRENT vs TEMPERATURE SUPPLY CURRENT vs DIGITAL INPUT CODE 700 750 3 ISOURCE (mA) 5 0 2.7 3.05 3.4 3.75 4.1 4.45 4.8 5.15 5.5 2.7 VDD (V) 4.1 4.8 5.5 VDD (V) DAC8532 SBAS246A 3.4 7 www.ti.com TYPICAL CHARACTERISTICS (Cont.) At TA = +25C, unless otherwise noted. FULL-SCALE SETTLING TIME (Large Signal) SUPPLY CURRENT vs LOGIC INPUT VOLTAGE 1150 TA = 25C, SYNC Input (All Other Inputs = GND) Reference Current Included, CHA and CHB Active, No Load 1050 950 5 4 VDD = VREF = 5V, Output Loaded with 2k and 200pF to GND 850 VOUT (V) IDD (A) VDD = VREF = 5V 750 3 2 650 1 550 VDD = VREF = 2.7V 0 450 0 1 2 3 4 5 Time (2s/div) VLOGIC (V) HALF-SCALE SETTLING TIME (Large Signal) 3 2.5 FULL-SCALE SETTLING TIME (Large Signal) 3.5 VDD = VREF = 5V, Output Loaded with 2k and 200pF to GND. 3 2.5 VOUT (V) VOUT (V) 2 1.5 1 VDD = VREF = 2.7V, Output Loaded with 2k and 200pF to GND. 2 1.5 1 0.5 0.5 0 0 Time (2s/div) Time (2s/div) HALF-SCALE SETTLING TIME (Large Signal) VOUT (V) 1.5 POWER-ON RESET TO ZERO-SCALE VDD = VREF = 2.7V, Output Loaded with 2k and 200pF to GND. Loaded with 2k to GND VDD (2V/div) VOUT (1V/div) 1 0.5 0 Time (2s/div) Time (100s/div) DAC8532 8 www.ti.com SBAS246A TYPICAL CHARACTERISTICS (Cont.) At TA = +25C, unless otherwise noted. OUTPUT GLITCH (Worst Case) 5.5 5 4.5 4 3.5 3 2.5 2 1.5 1 0.5 0 -0.5 4.72 VDD = VREF = 5V Power Up to Code FFFFH 4.7 4.68 VOUT (V, 20mV/div) VOUT (V) EXITING POWER-DOWN MODE 4.66 4.64 4.62 4.6 4.58 VDD = VREF = 5V Code F000H to EFFFH to F000H (Glitch Occurs Every N * 4096 Code Boundary) 4.56 4.54 4.52 Time (1s/div) Time (1s/div) SIGNAL-TO-NOISE RATIO vs OUTPUT FREQUENCY 2.54 96 2.52 94 2.5 92 VDD = 5V SNR (dB) VOUT (V, 20mV/div) OUTPUT GLITCH (Mid-Scale) 2.48 2.46 2.44 VDD = 2.7V 90 88 VDD = VREF = 5V Code 8000H to 7FFFH to 8000H (Glitch Occurs Every N * 4096 Code Boundary) VDD = VREF -1dB FSR Digital Input, FS = 52ksps Measurement Bandwidth = 20kHz 86 2.42 84 0 Time (1s/div) 500 1000 1500 2000 2500 3000 3500 4000 Output Frequency (Hz) TOTAL HARMONIC DISTORTION vs OUTPUT FREQUENCY 0 VDD = VREF = 5V -1dB FSR Digital Input, FS = 52ksps Measurement Bandwidth = 20kHz -20 THD (dB) -40 THD -60 -80 2nd Harmonic 3rd Harmonic -100 -120 0 500 1000 1500 2000 2500 3000 3500 4000 Output Frequency (Hz) DAC8532 SBAS246A 9 www.ti.com THEORY OF OPERATION VREF DAC SECTION RDIVIDER The architecture of each channel of the DAC8532 consists of a resistor string DAC followed by an output buffer amplifier. Figure 1 shows a simplified block diagram of the DAC architecture. VREF 2 R VREF R DAC Register REF (+) Resistor String REF(-) To Output Amplifier (2x Gain) VOUTX Output Amplifier GND FIGURE 1. DAC8532 Architecture. R The input coding for each device is unipolar straight binary, so the ideal output voltage is given by: VOUT X = VREF * R D 65536 where D = decimal equivalent of the binary code that is loaded to the DAC register; it can range from 0 to 65535. VOUTX refers to channel A or B. RESISTOR STRING The resistor string section is shown in Figure 2. It is simply a divide-by-2 resistor followed by a string of resistors, each of value R. The code loaded into the DAC register determines at which node on the string the voltage is tapped off. This voltage is then applied to the output amplifier by closing one of the switches connecting the string to the amplifier. OUTPUT AMPLIFIER Each output buffer amplifier is capable of generating rail-torail voltages on its output which approaches an output range of 0V to VDD (gain and offset errors must be taken into account). Each buffer is capable of driving a load of 2k in parallel with 1000pF to GND. The source and sink capabilities of the output amplifier can be seen in the typical characteristics. FIGURE 2. Resistor String. The write sequence begins by bringing the SYNC line LOW. Data from the DIN line is clocked into the 24-bit shift register on each falling edge of SCLK. The serial clock frequency can be as high as 30MHz, making the DAC8532 compatible with high speed DSPs. On the 24th falling edge of the serial clock, the last data bit is clocked into the shift register and the programmed function is executed (i.e., a change in Data Buffer contents, DAC Register contents, and/or a change in the power-down mode of a specified channel or channels). At this point, the SYNC line may be kept LOW or brought HIGH. In either case, the minimum delay time from the 24th falling SCLK edge to the next falling SYNC edge must be met in order to properly begin the next cycle. To assure the lowest power consumption of the device, care should be taken that the digital input levels are as close to each rail as possible. (Please refer to the "Typical Characteristics" section for the "Supply Current vs Logic Input Voltage" transfer characteristic curve). SERIAL INTERFACE The DAC8532 uses a 3-wire serial interface (SYNC, SCLK, and DIN), which is compatible with SPITM, QSPITM, and MicrowireTM interface standards, as well as most DSPs. See the Serial Write Operation timing diagram for an example of a typical write sequence. SPI and QSP are registered trademarks of Motorola. Microwire is a registered trademark of National Semiconductor. DAC8532 10 www.ti.com SBAS246A INPUT SHIFT REGISTER The input shift register of the DAC8532 is 24 bits wide (see Figure 5) and is made up of 8 control bits (DB16-DB23) and 16 data bits (DB0-DB15). The first two control bits (DB22 and DB23) are reserved and must be "0" for proper operation. LD A (DB20) and LD B (DB21) control the updating of each analog output with the specified 16-bit data value or power-down command. Bit DB19 is a "Don't Care" bit which does not affect the operation of the DAC8532 and can be 1 or 0. The following control bit, Buffer Select (DB18), controls the destination of the data (or power-down command) between DAC A and DAC B. The final two control bits, PD0 (DB16) and PD1 (DB17), select the power-down mode of one or both of the DAC channels. The four modes are normal mode or any one of three power-down modes. A more complete description of the operational modes of the DAC8532 can be found in the Power-Down Modes section. The remaining sixteen bits of the 24-bit input word make up the data bits. These are transferred to the specified Data Buffer or DAC Register, depending on the command issued by the control byte, on the 24th falling edge of SCLK. Please refer to Tables II and III for more information. are set to zero-scale; they remain there until a valid write sequence and load command is made to the respective DAC channel. This is useful in applications where it is important to know the state of the output of each DAC output while the device is in the process of powering up. No device pin should be brought high before power is applied to the device. POWER-DOWN MODES The DAC8532 utilizes four modes of operation. These modes are accessed by setting two bits (PD1 and PD0) in the control register and performing a "Load" action to one or both DACs. Table I shows how the state of the bits correspond to the mode of operation of each channel of the device. (Each DAC channel can be powered down simultaneously or independently of each other. Power-down occurs after proper data is written into PD0 and PD1 and a "Load" command occurs.) Please refer to the "Operation Examples" section for additional information. PD1 (DB17) Resistor String DAC Amplifier Power-down Circuitry VOUTX OPERATING MODE 0 0 Normal Operation -- -- Power-Down Modes 0 1 Output Typically 1k to GND 1 0 Output Typically 100k to GND 1 1 High Impedance TABLE I. Modes of Operation for the DAC8532. Resistor Network FIGURE 3. Output Stage During Power-Down (High-Impedance) SYNC INTERRUPT In a normal write sequence, the SYNC line is kept LOW for at least 24 falling edges of SCLK and the addressed DAC register is updated on the 24th falling edge. However, if SYNC is brought HIGH before the 24th falling edge, it acts as an interrupt to the write sequence; the shift register is reset and the write sequence is discarded. Neither an update of the data buffer contents, DAC register contents or a change in the operating mode occurs (see Figure 4). POWER-ON RESET The DAC8532 contains a power-on reset circuit that controls the output voltage during power-up. On power-up, the DAC registers are filled with zeros and the output voltages When both bits are set to 0, the device works normally with a typical power consumption of 500A at 5V. For the three power-down modes, however, the supply current falls to 200nA at 5V (50nA at 3V). Not only does the supply current fall but the output stage is also internally switched from the output of the amplifier to a resistor network of known values. This has the advantage that the output impedance of the device is known while it is in power-down mode. There are three different options for power-down: The output is connected internally to GND through a 1k resistor, a 100k resistor, or it is left open-circuited (High-Impedance). The output stage is illustrated in Figure 3. All analog circuitry is shut down when the power-down mode is activated. Each DAC will exit power-down when PD0 and PD1 are set to 0, new data is written to the Data Buffer, and the DAC channel receives a "Load" command. The time to exit power-down is typically 2.5s for VDD = 5V and 5s for VDD = 3V (See the Typical Characteristics). DAC8532 SBAS246A PD0 (DB16) 11 www.ti.com 24th Falling Edge 1 SCLK 2 24th Falling Edge 1 2 SYNC Invalid Write-Sync Interrupt: SYNC HIGH before 24th Falling Edge DIN DB23 DB22 Valid Write -Buffer/DAC Update: SYNC HIGH after 24th Falling Edge DB0 DB23 DB22 DB1 DB0 FIGURE 4. Interrupt and Valid SYNC Timing. DB23 DB12 0 0 LDB LDA X Buffer Select PD1 PD0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DB11 DB0 FIGURE 5. DAC8532 Data Input Register Format. D17 D16 D15 D14 D13-D0 Reserved Reserved Load B Load A Don't Care Buffer Select PD1 PD0 MSB MSB-1 MSB-2...LSB D23 D22 D21 D20 D19 D18 (Always Write 0) 0 = A, 1 = B 0 0 0 0 X # 0 0 0 0 X # 0 0 0 1 X # 0 0 DESCRIPTION 0 1 X 0 0 Data (see Table III) 0 0 Data 0 (see Table III) (see Table III) 0 0 0 1 X 1 0 0 1 0 X # 0 0 1 0 X 0 (see Table III) 0 0 1 0 X 1 (see Table III) 0 0 1 1 X # 0 0 X 0 X X WR Buffer B w/Power-Down Command and LOAD DAC A 0 1 1 X 0 (see Table III) 0 0 1 1 X 1 (see Table III) WR Buffer # w/Data and Load DAC B X WR Buffer A w/Power-Down Command and LOAD DAC B X WR Buffer B w/ Power-Down Command and LOAD DAC B (DAC B Powered Down) Data 0 WR Buffer # w/Data and Load DAC A WR Buffer A w/Power-Down Command and LOAD DAC A (DAC A Powered Down) Data 0 WR Buffer # w/Data WR Buffer # w/Power-Down Command WR Buffer # w/Data and Load DACs A and B X WR Buffer A w/Power-Down Command and Load DACs A and B (DAC A Powered Down) X WR Buffer B w/Power-Down Command and Load DACs A and B (DAC B Powered Down) TABLE II. Control Matrix. D17 D16 PD1 PD0 0 1 1k 1 0 100k 1 1 High Impedance OUTPUT IMPEDANCE POWERDOWN COMMANDS TABLE III. Power-Down Commands. DAC8532 12 www.ti.com SBAS246A OPERATION EXAMPLES Example 1: Write to Data Buffer A; Write to Data Buffer B; Load DACA and DACB Simultaneously * 1st--Write to Data Buffer A: Reserved Reserved LDB LDA DC Buffer Select PD1 PD0 DB15 ...... DB1 DB0 0 0 0 0 X 0 0 0 D15 ..... D1 D0 * 2nd--Write to Data Buffer B and Load DAC A and DAC B simultaneously: Reserved Reserved LDB LDA DC Buffer Select PD1 PD0 DB15 ...... DB1 DB0 0 0 1 1 X 1 0 0 D15 ..... D1 D0 The DACA and DACB analog outputs simultaneously settle to the specified values upon completion of the 2nd write sequence. (The "Load" command moves the digital data from the data buffer to the DAC register at which time the conversion takes place and the analog output is updated. "Completion" occurs on the 24th falling SCLK edge after SYNC LOW.) Example 2: Load New Data to DACA and DACB Sequentially * 1st--Write to Data Buffer A and Load DAC A: DACA output settles to specified value on completion: Reserved Reserved LDB LDA DC Buffer Select PD1 PD0 DB15 ...... DB1 DB0 0 0 0 1 X 0 0 0 D15 ..... D1 D0 * 2nd--Write to Data Buffer B and Load DAC B: DACB output settles to specified value on completion: Reserved Reserved LDB LDA DC Buffer Select PD1 PD0 DB15 ...... DB1 DB0 0 0 1 0 X 1 0 0 D15 ..... D1 D0 After completion of the 1st write cycle, the DACA analog output settles to the voltage specified; upon completion of write cycle 2, the DACB analog output settles. Example 3: Power-Down DACA to 1k and Power-Down DACB to 100k Simultaneously * 1st--Write power-down command to Data Buffer A: Reserved Reserved LDB LDA DC Buffer Select PD1 PD0 0 0 0 0 X 0 0 1 DB15 ...... DB1 DB0 Don't Care * 2nd--Write power-down command to Data Buffer B and Load DACA and DACB simultaneously: Reserved Reserved LDB LDA DC Buffer Select PD1 PD0 0 0 1 1 X 1 1 0 DB15 ...... DB1 DB0 Don't Care The DACA and DACB analog outputs simultaneously power-down to each respective specified mode upon completion of the 2nd write sequence. Example 4: Power-Down DACA and DACB to High Impedance Sequentially: * 1st--Write power-down command to Data Buffer A and Load DAC A: DAC A output = High-Z: Reserved Reserved LDB LDA DC Buffer Select PD1 PD0 0 0 0 1 X 0 1 1 DB15 ...... DB1 DB0 Don't Care * 2nd--Write power-down command to Data Buffer B and Load DAC B: DAC B output = High-Z: Reserved Reserved LDB LDA DC Buffer Select PD1 PD0 0 0 1 0 X 1 1 1 DB15 ...... DB1 DB0 Don't Care The DACA and DACB analog outputs sequentially power-down to high impedance upon completion of the 1st and 2nd write sequences, respectively. DAC8532 SBAS246A 13 www.ti.com MICROPROCESSOR INTERFACING DAC8532(1) 68HC11(1) DAC8532 to 8051 INTERFACE PC7 SYNC Figure 6 shows a serial interface between the DAC8532 and a typical 8051-type microcontroller. The setup for the interface is as follows: TXD of the 8051 drives SCLK of the DAC8532, while RXD drives the serial data line of the device. The SYNC signal is derived from a bit-programmable pin on the port of the 8051. In this case, port line P3.3 is used. When data is to be transmitted to the DAC8532, P3.3 is taken LOW. The 8051 transmits data in 8-bit bytes; thus only eight falling clock edges occur in the transmit cycle. To load data to the DAC, P3.3 is left LOW after the first eight bits are transmitted, then a second and third write cycle is initiated to transmit the remaining data. P3.3 is taken HIGH following the completion of the third write cycle. The 8051 outputs the serial data in a format which presents the LSB first, while the DAC8532 requires its data with the MSB as the first bit received. The 8051 transmit routine must therefore take this into account, and "mirror" the data as needed. SCK SCLK 80C51/80L51(1) MOSI DIN NOTE: (1) Additional pins omitted for clarity. FIGURE 8. DAC8532 to 68HC11 Interface. The 68HC11 should be configured so that its CPOL bit is 0 and its CPHA bit is 1. This configuration causes data appearing on the MOSI output to be valid on the falling edge of SCK. When data is being transmitted to the DAC, the SYNC line is held LOW (PC7). Serial data from the 68HC11 is transmitted in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. (Data is transmitted MSB first.) In order to load data to the DAC8532, PC7 is left LOW after the first eight bits are transferred, then a second and third serial write operation is performed to the DAC. PC7 is taken HIGH at the end of this procedure. DAC8532(1) P3.3 SYNC TXD SCLK RXD DIN DAC8532 to TMS320 DSP INTERFACE Figure 9 shows the connections between the DAC8532 and a TMS320 digital signal processor. By decoding the FSX signal, multiple DAC8532s can be connected to a single serial port of the DSP. NOTE: (1) Additional pins omitted for clarity. FIGURE 6. DAC8532 to 80C51/80L51 Interface. DAC8532 DAC8532 to Microwire INTERFACE Positive Supply VDD Figure 7 shows an interface between the DAC8532 and any Microwire compatible device. Serial data is shifted out on the falling edge of the serial clock and is clocked into the DAC8532 on the rising edge of the SK signal. 0.1F 10F TMS320 DSP FSX DX CLKX SYNC DIN VOUTA Output A VOUTB Output B SCLK VREF 0.1F MicrowireTM DAC8532(1) CS SYNC SK SCLK SO DIN 1F to 10F Reference Input GND FIGURE 9. DAC8532 to TMS320 DSP. APPLICATIONS NOTE: (1) Additional pins omitted for clarity. Microwire is a registered trademark of National Semiconductor. CURRENT CONSUMPTION FIGURE 7. DAC8532 to Microwire Interface. DAC8532 to 68HC11 INTERFACE Figure 8 shows a serial interface between the DAC8532 and the 68HC11 microcontroller. SCK of the 68HC11 drives the SCLK of the DAC8532, while the MOSI output drives the serial data line of the DAC. The SYNC signal is derived from a port line (PC7), similar to the 8051 diagram. The DAC8532 typically consumes 250uA at VDD = 5V and 225uA at VDD = 3V for each active channel, including reference current consumption. Additional current consumption can occur at the digital inputs if VIH<<VDD. For most efficient power operation, CMOS logic levels are recommended at the digital inputs to the DAC. In power-down mode, typical current consumption is 200nA. A delay time of 10 to 20ms after a power-down command is issued to the DAC is typically sufficient for the power-down current to drop below 10A. DAC8532 14 www.ti.com SBAS246A DRIVING RESISTIVE AND CAPACITIVE LOADS The DAC8532 output stage is capable of driving loads of up to 1000pF while remaining stable. Within the offset and gain error margins, the DAC8532 can operate rail-to-rail when driving a capacitive load. Resistive loads of 2k can be driven by the DAC8532 while achieving a typical load regulation of 1%. As the load resistance drops below 2k, the load regulation error increases. When the outputs of the DAC are driven to the positive rail under resistive loading, the PMOS transistor of each Class-AB output stage can enter into the linear region. When this occurs, the added IR voltage drop deteriorates the linearity performance of the DAC. This only occurs within approximately the top 20mV of the DAC's digital input-to-voltage output transfer characteristic. The reference voltage applied to the DAC8532 may be reduced below the supply voltage applied to VDD in order to eliminate this condition if good linearity is a requirement at full scale (under resistive loading conditions). CROSSTALK AND AC PERFORMANCE The DAC8532 architecture uses separate resistor strings for each DAC channel in order to achieve ultra-low crosstalk performance. DC crosstalk seen at one channel during a fullscale change on the neighboring channel is typically less than 0.5LSBs. The AC crosstalk measured (for a full-scale, 1kHz sine wave output generated at one channel, and measured at the remaining output channel) is typically under -100dB. In addition, the DAC8532 can achieve typical AC performance of 96dB SNR (Signal-to-Noise Ratio) and 65db THD (Total Harmonic Distortion), making the DAC8532 a solid choice for applications requiring low SNR at output frequencies at or below 4kHz. For full-scale output swings, the output stage of each DAC8532 channel typically exhibits less than 100mV of overshoot and undershoot when driving a 200pF capacitive load. Code-to-code change glitches are extremely low (~10uV) given that the code-to-code transition does not cross an Nx4096 code boundary. Due to internal segmentation of the DAC8532, code-to-code glitches occur at each crossing of an Nx4096 code boundary. These glitches can approach 100mVs for N = 15, but settle out within ~2s. USING REF02 AS A POWER SUPPLY FOR DAC8532 Due to the extremely low supply current required by the DAC8532, a possible configuration is to use a REF02 +5V precision voltage reference to supply the required voltage to the DAC8532's supply input as well as the reference input, as shown in Figure 10. This is especially useful if the power supply is quite noisy or if the system supply voltages are at some value other than 5V. The REF02 will output a steady supply voltage for the DAC8532. If the REF02 is used, the current it needs to supply to the DAC8532 is 567A typical and 890A max for VDD = 5V. When a DAC output is loaded, the REF02 also needs to supply the current to the load. The total typical current required (with a 5k load on a given DAC output) is: 567A + (5V/ 5k) = 1.567mA +15 +5V REF02 1.567mA OUTPUT VOLTAGE STABILITY The DAC8532 exhibits excellent temperature stability of 5ppm/C typical output voltage drift over the specified temperature range of the device. This enables the output voltage of each channel to stay within a 25V window for a 1C ambient temperature change. Good Power-Supply Rejection Ratio (PSRR) performance reduces supply noise present on VDD from appearing at the outputs to well below 10V-s. Combined with good DC noise performance and true 16-bit differential linearity, the DAC8532 becomes a perfect choice for closed-loop control applications. SETTLING TIME AND OUTPUT GLITCH PERFORMANCE Settling time to within the 16-bit accurate range of the DAC8532 is achievable within 10s for a full-scale code change at the input. Worst case settling times between consecutive code changes is typically less than 2s, enabling update rates up to 500ksps for digital input signals changing code-to-code. The high-speed serial interface of the DAC8532 is designed in order to support these high update rates. 3-Wire Serial Interface VDD, VREF SCLK DAC8532 VOUT = 0V to 5V DIN FIGURE 10. REF02 as a Power Supply to the DAC8532. The load regulation of the REF02 is typically 0.005%/mA, which results in an error of 392V for the 1.5mA current drawn from it. This corresponds to a 5.13LSB error for a 0V to 5V output range. BIPOLAR OPERATION USING THE DAC8532 The DAC8532 has been designed for single-supply operation but a bipolar output range is also possible using the circuit in Figure 11. The circuit shown will give an output voltage range of VREF. Rail-to-rail operation at the amplifier output is achievable using an amplifier such as the OPA703, see Figure 11. DAC8532 SBAS246A SYNC 15 www.ti.com R2 10k +5V +5V R1 10k OPA703 VOUTX VDD, VREF 10F 5V DAC8532 0.1F -5V (Other pins omitted for clarity.) FIGURE 11. Bipolar Operation with the DAC8532. The output voltage for any input code can be calculated as follows: D R1 + R 2 VOUT X = VREF * - VREF * 65536 R1 R * 2 R1 where D represents the input code in decimal (0-65535). With VREF = 5V, R1 = R2 = 10k: 10 * D VOUT X = - 5V 65536 This is an output voltage range of 5V with 0000H corresponding to a -5V output and FFFFH corresponding to a +5V output. Similarly, using VREF = 2.5V, a 2.5V output voltage range can be achieved. LAYOUT A precision analog component requires careful layout, adequate bypassing, and clean, well-regulated power supplies. The DAC8532 offers single-supply operation, and it will often be used in close proximity with digital logic, microcontrollers, microprocessors, and digital signal processors. The more digital logic present in the design and the higher the switching speed, the more difficult it will be to keep digital noise from appearing at the output. Due to the single ground pin of the DAC8532, all return currents, including digital and analog return currents for the DAC, must flow through a single point. Ideally, GND would be connected directly to an analog ground plane. This plane would be separate from the ground connection for the digital components until they were connected at the power entry point of the system. The power applied to VDD should be well regulated and low noise. Switching power supplies and DC/DC converters will often have high-frequency glitches or spikes riding on the output voltage. In addition, digital components can create similar high-frequency spikes as their internal logic switches states. This noise can easily couple into the DAC output voltage through various paths between the power connections and analog output. As with the GND connection, VDD should be connected to a positive power-supply plane or trace that is separate from the connection for digital logic until they are connected at the power entry point. In addition, a 1F to 10F capacitor in parallel with a 0.1F bypass capacitor is strongly recommended. In some situations, additional bypassing may be required, such as a 100F electrolytic capacitor or even a "Pi" filter made up of inductors and capacitors--all designed to essentially low-pass filter the supply, removing the highfrequency noise. DAC8532 16 www.ti.com SBAS246A PACKAGE OPTION ADDENDUM www.ti.com 16-Aug-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) DAC8532IDGK ACTIVE VSSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-2-260C-1 YEAR DAC8532IDGKG4 ACTIVE VSSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-2-260C-1 YEAR DAC8532IDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-2-260C-1 YEAR DAC8532IDGKRG4 ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-2-260C-1 YEAR Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 16-Aug-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device DAC8532IDGKR Package Package Pins Type Drawing VSSOP DGK 8 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 12.4 Pack Materials-Page 1 5.3 B0 (mm) K0 (mm) P1 (mm) 3.4 1.4 8.0 W Pin1 (mm) Quadrant 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 16-Aug-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DAC8532IDGKR VSSOP DGK 8 2500 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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