DAC8532IDGKRG4 - Texas Instruments

Dual Channel, Low Power, 16-Bit, Serial Input

DIGITAL-TO-ANALOG CONVERTER

APPLICATIONS

● PORTABLE INSTRUMENTATION

● CLOSED-LOOP SERVO-CONTROL

● PROCESS CONTROL

● DATA ACQUISITION SYSTEMS

●PROGRAMMABLE ATTENUATION

● PC PERIPHERALS

DESCRIPTION

The DAC8532 is a dual channel, 16-bit Digital-to-Analog

Converter (DAC) offering low power operation and a flexible

serial host interface. Each on-chip precision output amplifier

allows rail-to-rail output swing to be achieved over the supply

range of 2.7V to 5.5V. The device supports a standard 3-wire

serial interface capable of operating with input data clock

frequencies up to 30MHz for VDD = 5V.

The DAC8532 requires an external reference voltage to set

the output range of each DAC channel. Also incorporated

into the device is a power-on reset circuit which ensures that

the DAC outputs power up at zero-scale and remain there

until a valid write takes place. The DAC8532 provides a

flexible power-down feature, accessed over the serial inter-

face, that reduces the current consumption of the device to

200nA at 5V.

The low-power consumption of this device in normal opera-

tion makes it ideally suited to portable battery-operated

equipment and other low-power applications. The power

consumption is 2.5mW at 5V, reducing to 1µW in power-

down mode.

The DAC8532 is available in a MSOP-8 package with a

specified operating temperature range of –40°C to +105°C.

FEATURES

●

micro

POWER OPERATION:

500

A at 5V

●

POWER-ON RESET TO ZERO-SCALE

● POWER SUPPLY: +2.7V to +5.5V

● 16-BIT MONOTONIC OVER TEMPERATURE

● SETTLING TIME: 10µs to ±0.003% FSR

● ULTRA-LOW AC CROSSTALK: –100dB typ

● LOW-POWER SERIAL INTERFACE WITH

SCHMITT-TRIGGERED INPUTS

● ON-CHIP OUTPUT BUFFER AMPLIFIER WITH

RAIL-TO-RAIL OPERATION

● DOUBLE BUFFERED INPUT ARCHITECTURE

● SIMULTANEOUS OR SEQUENTIAL OUTPUT

UPDATE AND POWERDOWN

● TINY MSOP-8 PACKAGE

DAC8532

SBAS246A – DECEMBER 2001 – MAY 2003

www.ti.com

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Control Logic

Channel

Select Load

Control

Data

Buffer B DAC

DAC B

Power-Down

Control Logic

24-Bit

Serial-to-

Parallel

Shift

Network

GND

OUT

Data

Buffer A DAC

REF

SYNC

SCLK

DAC8532

2SBAS246A

www.ti.com

SPECIFICATION

PACKAGE TEMPERATURE PACKAGE ORDERING TRANSPORT

PRODUCT PACKAGE-LEAD DESIGNATOR(1) RANGE MARKING NUMBER MEDIA, QUANTITY

DAC8532 MSOP-8 DGK –40°C to +105°C D32E DAC8532IDGK Tube, 80

"" ""DAC8532IDGKR Tape and Reel,

2500

NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com.

PARAMETER CONDITIONS MIN TYP MAX UNITS

STATIC PERFORMANCE(1)

Resolution 16 Bits

Relative Accuracy ±0.0987 % of FSR

Differential Nonlinearity 16-Bit Monotonic ±1LSB

Zero-Scale Error +5 +25 mV

Full-Scale Error –0.15 –1.0 % of FSR

Gain Error ±1.0 % of FSR

Zero-Scale Error Drift ±20 µV/°C

Gain Temperature Coefficient ±5 ppm of FSR/°C

Channel-to-Channel Matching RL = 2kΩ, CL = 200pF 15 mV

PSRR 0.75 mV/V

OUTPUT CHARACTERISTICS(2)

Output Voltage Range 0V

REF V

Output Voltage Settling Time To ±0.003% FSR

0200H to FD00H810 µs

RL = 2kΩ; 0pF < CL < 200pF

RL = 2kΩ; CL = 500pF 12 µs

Slew Rate 1V/µs

Capacitive Load Stability RL = ∞470 pF

RL = 2kΩ1000 pF

Code Change Glitch Impulse 1LSB Change Around Major Carry 20 nV-s

Digital Feedthrough 0.5 nV-s

DC Crosstalk 0.25 LSB

AC Crosstalk –100 –96 dB

DC Output Impedance 1Ω

Short-Circuit Current VDD = +5V 50 mA

VDD = +3V 20 mA

Power-Up Time Coming Out of Power-Down Mode

VDD = +5V 2.5 µs

Coming Out of Power-Down Mode

VDD = +3V 5 µs

AC PERFORMANCE BW = 20kHz, VDD = 5V

FOUT = 1kHz, 1st 19 Harmonics Removed

SNR 94 dB

THD 67 dB

SFDR 69 dB

SINAD 65 dB

VDD to GND...........................................................................–0.3V to +6V

Digital Input Voltage to GND ................................. –0.3V to +VDD + 0.3V

VOUTA or VOUTB to GND.......................................... –0.3V to +VDD + 0.3V

Operating Temperature Range ......................................–40°C to +105°C

Storage Temperature Range .........................................–65°C to +150°C

Junction Temperature Range (TJ max) ........................................ +150°C

Power Dissipation ........................................................ (TJ max — TA)/

JA Thermal Impedance......................................................... 206°C/W

JC Thermal Impedance .......................................................... 44°C/W

Lead Temperature, Soldering:

Vapor Phase (60s) ............................................................... +215°C

Infrared (15s)........................................................................ +220°C

NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings”

may cause permanent damage to the device. Exposure to absolute maximum

conditions for extended periods may affect device reliability.

ELECTROSTATIC

DISCHARGE SENSITIVITY

This integrated circuit can be damaged by ESD. Texas Instru-

ments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling

and installation procedures can cause damage.

ESD damage can range from subtle performance degradation

to complete device failure. Precision integrated circuits may be

more susceptible to damage because very small parametric

changes could cause the device not to meet its published

specifications.

ABSOLUTE MAXIMUM RATINGS(1)

PACKAGE/ORDERING INFORMATION

ELECTRICAL CHARACTERISTICS

VDD = +2.7V to +5.5V. –40°C to +105°C, unless otherwise specified.

DAC8532

SBAS246A www.ti.com

REFERENCE INPUT

Reference Current VREF = VDD = +5V 67 90 µA

VREF = VDD = +3V 40 54 µA

Reference Input Range 0 VDD V

Reference Input Impedance 75 kΩ

LOGIC INPUTS(2)

Input Current ±1µA

VINL, Input LOW Voltage VDD = +5V 0.8 V

VINL, Input LOW Voltage VDD = +3V 0.6 V

VINH, Input HIGH Voltage VDD = +5V 2.4 V

VINH, Input HIGH Voltage VDD = +3V 2.1 V

Pin Capacitance 3pF

POWER REQUIREMENTS

VDD 2.7 5.5 V

IDD (normal mode)

DAC Active and Excluding Load Current

VDD = +3.6V to +5.5V VIH = VDD and VIL = GND 500 800 µA

VDD = +2.7V to +3.6V VIH = VDD and VIL = GND 450 750 µA

IDD (all power-down modes)

VDD = +3.6V to +5.5V VIH = VDD and VIL = GND 0.2 1 µA

VDD = +2.7V to +3.6V VIH = VDD and VIL = GND 0.05 1 µA

POWER EFFICIENCY

IOUT/IDD ILOAD = 2mA, VDD = +5V 89 %

TEMPERATURE RANGE

Specified Performance –40 +105 °C

PARAMETER CONDITIONS MIN TYP MAX UNITS

ELECTRICAL CHARACTERISTICS (Cont.)

VDD = +2.7V to +5.5V. –40°C to +105°C, unless otherwise specified.

DAC8532

NOTES: (1) Linearity calculated using a reduced code range of 485 to 64714; output unloaded. (2) Ensured by design and characterization, not production tested.

PIN NAME DESCRIPTION

DD Power supply input, +2.7V to +5.5V.

REF Reference voltage input.

OUTB Analog output voltage from DAC B.

OUTA Analog output voltage from DAC A.

5 SYNC Level triggered SYNC input (active LOW). This is the

frame synchronization signal for the input data.

When SYNC goes LOW, it enables the input shift

SCLK. The action specified by the 8-bit control byte

and 16-bit data word is executed following the 24th

falling SCLK clock edge (unless SYNC is taken

HIGH before this edge in which case the rising edge

of SYNC acts as an interrupt and the write sequence

is ignored by the DAC8532).

6 SCLK Serial Clock Input. Data can be transferred at rates

up to 30 MHz at 5V.

IN Serial Data Input. Data is clocked into the 24-bit

input shift register on each falling edge of the serial

clock input.

8 GND Ground reference point for all circuitry on the part.

PIN DESCRIPTIONS

PIN CONFIGURATION

Top View MSOP-8

REF

OUT

GND

SCLK

SYNC

DAC8532

4SBAS246A

www.ti.com

SERIAL WRITE OPERATION

SCLK 1 24

SYNC

DB23 DB0 DB23

PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNITS

t1(3) SCLK Cycle Time VDD = 2.7V to 3.6V 50 ns

VDD = 3.6V to 5.5V 33 ns

t2SCLK HIGH Time VDD = 2.7V to 3.6V 13 ns

VDD = 3.6V to 5.5V 13 ns

t3SCLK LOW Time VDD = 2.7V to 3.6V 22.5 ns

VDD = 3.6V to 5.5V 13 ns

t4SYNC to SCLK Rising

Edge Setup Time VDD = 2.7V to 3.6V 0 ns

VDD = 3.6V to 5.5V 0 ns

t5Data Setup Time VDD = 2.7V to 3.6V 5 ns

VDD = 3.6V to 5.5V 5 ns

t6Data Hold Time VDD = 2.7V to 3.6V 4.5 ns

VDD = 3.6V to 5.5V 4.5 ns

t724th SCLK Falling Edge to

SYNC Rising Edge VDD = 2.7V to 3.6V 0 ns

VDD = 3.6V to 5.5V 0 ns

t8Minimum SYNC HIGH Time VDD = 2.7V to 3.6V 50 ns

VDD = 3.6V to 5.5V 33 ns

t924th SCLK Falling Edge to

SYNC Falling Edge VDD = 2.7V to 5.5V 100 ns

NOTES: (1) All input signals are specified with tR = tF = 5ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. (2) See Serial Write Operation timing

diagram, below. (3) Maximum SCLK frequency is 30MHz at VDD = +3.6V to +5.5V and 20MHz at VDD = +2.7V to +3.6V.

TIMING CHARACTERISTICS(1, 2)

VDD = +2.7V to +5.5V; all specifications –40°C to +105°C unless otherwise noted.

DAC8532

SBAS246A www.ti.com

TYPICAL CHARACTERISTICS

At TA = +25°C, unless otherwise noted.

–16

–32

–48

–64

LE (LSB)

LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR vs CODE

0000H2000H4000H6000H8000H

Digital Input Code

A000HC000HE000HFFFFH

2.0

1.5

1.0

0.5

0.0

–0.5

–1.0

–1.5

–2.0

DLE (LSB)

VDD = VREF = 5V, TA = 25°C,

Channel A Output

–16

–32

–48

–64

LE (LSB)

LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR vs CODE

0000H2000H4000H6000H8000H

Digital Input Code

A000HC000HE000HFFFFH

2.0

1.5

1.0

0.5

0.0

–0.5

–1.0

–1.5

–2.0

DLE (LSB)

VDD = VREF = 5V, TA = 25°C,

Channel B Output

–16

–32

–48

–64

LE (LSB)

LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR vs CODE

0000H2000H4000H6000H8000H

Digital Input Code

A000HC000HE000HFFFFH

2.0

1.5

1.0

0.5

0.0

–0.5

–1.0

–1.5

–2.0

DLE (LSB)

VDD = VREF = 2.7V, TA = 25°C,

Channel A Output

–16

–32

–48

–64

LE (LSB)

LINEARITY ERROR AND

DIFFERENTIAL LINEARITY ERROR vs CODE

0000

2000

4000

6000

8000

Digital Input Code

A000

C000

E000

FFFF

2.0

1.5

1.0

0.5

0.0

–0.5

–1.0

–1.5

–2.0

DLE (LSB)

= V

REF

= 2.7V, T

= 25°C,

Channel B Output

ZERO-SCALE ERROR vs TEMPERATURE

–40

Output Error (mV)

Temperature (°C)

–10 20 50 80 105

VDD = VREF VDD = 5V, CH B

VDD = 5V, CH A

VDD = 2.7V, CH A

VDD = 2.7V, CH B

FULL-SCALE ERROR vs TEMPERATURE

–40

Output Error (mV)

Temperature (°C)

–10 20 50 80 105

–5

–10

–15

(To avoid clipping of the output signal

during the test, V

REF

= V

– 10mV)

= 5V, CH A

= 2.7V, CH A

= 2.7V, CH B V

= 5V, CH B

DAC8532

6SBAS246A

www.ti.com

TYPICAL CHARACTERISTICS (Cont.)

At TA = +25°C, unless otherwise noted.

ABSOLUTE ERROR

0000H2000H4000H6000H8000H

Digital Input Code

A000HC000HE000HFFFFH

–5

–10

–15

–20

–25

–30

Output Error (mV)

VDD = VREF = 5V, TA = 25°C

Channel A Output

Channel B Output

ABSOLUTE ERROR

0000H2000H4000H6000H8000H

Digital Input Code

A000HC000HE000HFFFFH

–5

–10

–15

–20

–25

–30

Output Error (mV)

VDD = VREF = 2.7V, TA = 25°C

Channel A Output

Channel B Output

HISTOGRAM OF CURRENT CONSUMPTION

Frequency

IDD (µA)

2500

2000

1500

1000

500

0400 440 480 520 560 600 640 680 720 760 800

VDD = VREF = 5V,

Reference Current Included

HISTOGRAM OF CURRENT CONSUMPTION

Frequency

IDD (µA)

2500

2000

1500

1000

500

0280 320 360 400 440 480 520 560 600 640 680

VDD = VREF = 2.7V,

Reference Current Included

SINK CURRENT CAPABILITY

VOUT (V)

ISINK (mA)

12345

0.15

0.125

0.1

0.075

0.05

0.025

VREF = VDD – 10mV

DAC Loaded with 0000H

VDD = 2.7V

VDD = 5V

OUTPUT VOLTAGE DRIFT

Time (1min/div)

OUT

(25µV/div)

= V

REF

= 5V, T

= 25°C (±1°C),

Digital Code = 7FFF

DAC8532

SBAS246A www.ti.com

TYPICAL CHARACTERISTICS (Cont.)

At TA = +25°C, unless otherwise noted.

SOURCE CURRENT CAPABILITY

VOUT (V)

ISOURCE (mA)

12345

4.95

4.9

4.85

4.8

VREF = VDD – 10mV

DAC Loaded with FFFFH

VDD = 5V

SOURCE CURRENT CAPABILITY

OUT

(V)

SOURCE

(mA)

12345

2.7

2.65

2.6

2.55

2.5

REF

= V

– 10mV

DAC Loaded with FFFF

= 2.7V

SUPPLY CURRENT vs TEMPERATURE

700

600

500

400

300

200

100

IDD (µA)

–40 Temperature (°C)

–10 20 50 80 105

VDD = VREF = 5V

VDD = VREF = 2.7V

Reference Current Included,

CH A and CH B Active, No Load

SUPPLY CURRENT vs DIGITAL INPUT CODE

0000

2000

4000

6000

8000

Digital Input Code

A000

C000

E000

FFFF

700

600

500

400

300

200

100

IDD (µA)

VDD = VREF = 5V

VDD = VREF = 2.7V

POWER-DOWN CURRENT vs SUPPLY VOLTAGE

IDD (nA)

2.7 VDD (V)

3.4 4.1 4.8 5.5

Reference Current Excluded

TA = +105°CTA = –40°C

TA = +25°C

SUPPLY CURRENT vs SUPPLY VOLTAGE

800

750

700

650

600

550

500

450

400

(µA)

2.7 V

(V)

3.05 3.753.4 4.454.1 5.154.8 5.5

REF

= V

, Both DACs Active,

Reference Current Included, No Load

DAC8532

8SBAS246A

www.ti.com

TYPICAL CHARACTERISTICS (Cont.)

At TA = +25°C, unless otherwise noted.

SUPPLY CURRENT vs LOGIC INPUT VOLTAGE

IDD (µA)

VLOGIC (V)

12345

1150

1050

950

850

750

650

550

450

VDD = VREF = 5V

VDD = VREF = 2.7V

TA = 25°C, SYNC Input (All Other Inputs = GND)

Reference Current Included,

CHA and CHB Active,

No Load

FULL-SCALE SETTLING TIME

(Large Signal)

Time (2µs/div)

VOUT (V)

= V

REF

= 5V,

Output Loaded with

2kΩ and 200pF to

GND

HALF-SCALE SETTLING TIME

(Large Signal)

Time (2µs/div)

2.5

1.5

0.5

OUT

(V)

VDD = VREF = 5V,

Output Loaded with

2kΩ and 200pF

to GND.

FULL-SCALE SETTLING TIME

(Large Signal)

Time (2µs/div)

3.5

2.5

1.5

0.5

OUT

(V)

= V

REF

= 2.7V,

Output Loaded with

2kΩ and 200pF

to GND.

HALF-SCALE SETTLING TIME

(Large Signal)

Time (2µs/div)

1.5

0.5

OUT

(V)

= V

REF

= 2.7V,

Output Loaded with

2kΩ and 200pF

to GND.

POWER-ON RESET TO ZERO-SCALE

Time (100µs/div)

Loaded with 2kΩ to GND

(2V/div)

OUT

(1V/div)

DAC8532

SBAS246A www.ti.com

TYPICAL CHARACTERISTICS (Cont.)

At TA = +25°C, unless otherwise noted.

EXITING POWER-DOWN MODE

Time (1µs/div)

5.5

4.5

3.5

2.5

1.5

0.5

–0.5

VOUT (V)

VDD = VREF = 5V

Power Up to Code FFFFH

OUTPUT GLITCH

(Mid-Scale)

Time (1µs/div)

2.54

2.52

2.5

2.48

2.46

2.44

2.42

VOUT (V, 20mV/div)

VDD = VREF = 5V

Code 8000H to 7FFFH to 8000H

(Glitch Occurs Every N • 4096 Code Boundary)

SIGNAL-TO-NOISE RATIO vs OUTPUT FREQUENCY

SNR (dB)

0Output Frequency (Hz)

500 15001000 25002000 35003000 4000

= V

REF

–1dB FSR Digital Input, F

= 52ksps

Measurement Bandwidth = 20kHz

= 5V

= 2.7V

TOTAL HARMONIC DISTORTION

vs OUTPUT FREQUENCY

–20

–40

–60

–80

–100

–120

THD (dB)

0Output Frequency (Hz)

500 15001000 25002000 35003000 4000

VDD = VREF = 5V

–1dB FSR Digital Input, FS = 52ksps

Measurement Bandwidth = 20kHz

2nd Harmonic

THD

3rd Harmonic

OUTPUT GLITCH

(Worst Case)

Time (1µs/div)

4.72

4.7

4.68

4.66

4.64

4.62

4.6

4.58

4.56

4.54

4.52

VOUT (V, 20mV/div)

= V

REF

= 5V

Code F000

to EFFF

to F000

(Glitch Occurs Every N • 4096 Code Boundary)

DAC8532

10 SBAS246A

www.ti.com

THEORY OF OPERATION

DAC SECTION

The architecture of each channel of the DAC8532 consists of

a resistor string DAC followed by an output buffer amplifier.

Figure 1 shows a simplified block diagram of the DAC

architecture.

The input coding for each device is unipolar straight binary,

so the ideal output voltage is given by:

VXV D

OUT REF

=•

65536

where D = decimal equivalent of the binary code that is

loaded to the DAC register; it can range from 0 to 65535.

VOUTX refers to channel A or B.

RESISTOR STRING

The resistor string section is shown in Figure 2. It is simply

a divide-by-2 resistor followed by a string of resistors, each

of value R. The code loaded into the DAC register deter-

mines at which node on the string the voltage is tapped off.

This voltage is then applied to the output amplifier by closing

one of the switches connecting the string to the amplifier.

OUTPUT AMPLIFIER

Each output buffer amplifier is capable of generating rail-to-

rail voltages on its output which approaches an output range

of 0V to VDD (gain and offset errors must be taken into

account). Each buffer is capable of driving a load of 2kΩ in

parallel with 1000pF to GND. The source and sink capabili-

ties of the output amplifier can be seen in the typical charac-

teristics.

SERIAL INTERFACE

The DAC8532 uses a 3-wire serial interface (SYNC, SCLK,

and DIN), which is compatible with SPI™, QSPI™, and

Microwire™ interface standards, as well as most DSPs. See

the Serial Write Operation timing diagram for an example of

a typical write sequence.

SPI and QSP are registered trademarks of Motorola.

Microwire is a registered trademark of National Semiconductor.

DAC Register REF (+)

Resistor String

REF(–)

Output

Amplifier

GND

REF

OUT

FIGURE 1. DAC8532 Architecture.

To Output

Amplifier

(2x Gain)

REF

DIVIDER

FIGURE 2. Resistor String.

The write sequence begins by bringing the SYNC line LOW.

Data from the DIN line is clocked into the 24-bit shift register

on each falling edge of SCLK. The serial clock frequency can

be as high as 30MHz, making the DAC8532 compatible with

high speed DSPs. On the 24th falling edge of the serial clock,

the last data bit is clocked into the shift register and the

programmed function is executed (i.e., a change in Data

Buffer contents, DAC Register contents, and/or a change in

the power-down mode of a specified channel or channels).

At this point, the SYNC line may be kept LOW or brought

HIGH. In either case, the minimum delay time from the 24th

falling SCLK edge to the next falling SYNC edge must be met

in order to properly begin the next cycle. To assure the

lowest power consumption of the device, care should be

taken that the digital input levels are as close to each rail as

possible. (Please refer to the “Typical Characteristics” sec-

tion for the “Supply Current vs Logic Input Voltage” transfer

characteristic curve).

DAC8532

SBAS246A www.ti.com

INPUT SHIFT REGISTER

The input shift register of the DAC8532 is 24 bits wide (see

Figure 5) and is made up of 8 control bits (DB16-DB23) and 16

data bits (DB0-DB15). The first two control bits (DB22 and

DB23) are reserved and must be “0” for proper operation. LD

A (DB20) and LD B (DB21) control the updating of each analog

output with the specified 16-bit data value or power-down

command. Bit DB19 is a “Don't Care” bit which does not affect

the operation of the DAC8532 and can be 1 or 0. The following

control bit, Buffer Select (DB18), controls the destination of the

data (or power-down command) between DAC A and DAC B.

The final two control bits, PD0 (DB16) and PD1 (DB17), select

the power-down mode of one or both of the DAC channels. The

four modes are normal mode or any one of three power-down

modes. A more complete description of the operational modes

of the DAC8532 can be found in the Power-Down Modes

section. The remaining sixteen bits of the 24-bit input word

make up the data bits. These are transferred to the specified

Data Buffer or DAC Register, depending on the command

issued by the control byte, on the 24th falling edge of SCLK.

Please refer to Tables II and III for more information.

are set to zero-scale; they remain there until a valid write

sequence and load command is made to the respective

DAC channel. This is useful in applications where it is

important to know the state of the output of each DAC

output while the device is in the process of powering up.

No device pin should be brought high before power is

applied to the device.

POWER-DOWN MODES

The DAC8532 utilizes four modes of operation. These modes

are accessed by setting two bits (PD1 and PD0) in the control

Table I shows how the state of the bits correspond to the

mode of operation of each channel of the device. (Each DAC

channel can be powered down simultaneously or indepen-

dently of each other. Power-down occurs after proper data is

written into PD0 and PD1 and a “Load” command occurs.)

Please refer to the "Operation Examples" section for addi-

tional information.

Resistor

String DAC Amplifier

Power-down

Circuitry Resistor

Network

OUT

FIGURE 3. Output Stage During Power-Down (High-Impedance)

SYNC INTERRUPT

In a normal write sequence, the SYNC line is kept LOW for

at least 24 falling edges of SCLK and the addressed DAC

SYNC is brought HIGH before the 24th falling edge, it acts as

an interrupt to the write sequence; the shift register is reset

and the write sequence is discarded. Neither an update of

the data buffer contents, DAC register contents or a change

in the operating mode occurs (see Figure 4).

POWER-ON RESET

The DAC8532 contains a power-on reset circuit that con-

trols the output voltage during power-up. On power-up, the

DAC registers are filled with zeros and the output voltages

PD1 (DB17) PD0 (DB16) OPERATING MODE

0 0 Normal Operation

——Power-Down Modes

0 1 Output Typically 1kΩ to GND

1 0 Output Typically 100kΩ to GND

1 1 High Impedance

TABLE I. Modes of Operation for the DAC8532.

When both bits are set to 0, the device works normally with

a typical power consumption of 500µA at 5V. For the three

power-down modes, however, the supply current falls to

200nA at 5V (50nA at 3V). Not only does the supply current

fall but the output stage is also internally switched from the

output of the amplifier to a resistor network of known values.

This has the advantage that the output impedance of the

device is known while it is in power-down mode. There are

three different options for power-down: The output is con-

nected internally to GND through a 1kΩ resistor, a 100kΩ

resistor, or it is left open-circuited (High-Impedance). The

output stage is illustrated in Figure 3.

All analog circuitry is shut down when the power-down mode

is activated. Each DAC will exit power-down when PD0 and

PD1 are set to 0, new data is written to the Data Buffer, and

the DAC channel receives a “Load” command. The time to

exit power-down is typically 2.5µs for VDD = 5V and 5µs for

VDD = 3V (See the Typical Characteristics).

DAC8532

12 SBAS246A

www.ti.com

D17 D16

PD1 PD0

01 1kΩ

1 0 100kΩ

1 1 High Impedance

TABLE III. Power-Down Commands.

OUTPUT IMPEDANCE POWERDOWN COMMANDS

00LDBLDAX

Buffer Selec

t PD1 PD0 D15 D14 D13 D12

D11D10D9D8D7D6D5D4D3D2D1D0

DB11 DB0

FIGURE 5. DAC8532 Data Input Register Format.

DB23 DB12

D23 D22 D21 D20 D19 D18 D17 D16

Reserved Reserved Load B Load A Don’t Care Buffer Select PD1 PD0

0 = A, 1 = B

0 0 0 0 X # 0 0 Data WR Buffer # w/Data

0 0 0 0 X # X WR Buffer # w/Power-Down Command

0 0 0 1 X # 0 0 Data WR Buffer # w/Data and Load DAC A

0001X 0 X WR Buffer A w/Power-Down Command and LOAD DAC A

(DAC A Powered Down)

0 0 0 1 X 1 X WR Buffer B w/Power-Down Command and LOAD DAC A

0 0 1 0 X # 0 0 Data WR Buffer # w/Data and Load DAC B

0 0 1 0 X 0 X WR Buffer A w/Power-Down Command and LOAD DAC B

0010X 1 X WR Buffer B w/ Power-Down Command and LOAD DAC B

(DAC B Powered Down)

0 0 1 1 X # 0 0 Data WR Buffer # w/Data and Load DACs A and B

0011X 0 X WR Buffer A w/Power-Down Command and Load DACs A

and B (DAC A Powered Down)

0011X 1 X WR Buffer B w/Power-Down Command and Load DACs A

and B (DAC B Powered Down)

D15 D14 D13-D0

MSB MSB-1 MSB-2...LSB

(see Table III)

(Always Write 0)

TABLE II. Control Matrix.

DESCRIPTION

(see Table III)

SCLK

SYNC

DIN

Invalid Write-Sync Interrupt:

SYNC HIGH before 24th Falling Edge Valid Write -Buffer/DAC Update:

SYNC HIGH after 24th Falling Edge

DB23 DB22

12 12

DB0 DB23 DB22 DB1 DB0

24th Falling

Edge 24th Falling

Edge

FIGURE 4. Interrupt and Valid SYNC Timing.

DAC8532

SBAS246A www.ti.com

OPERATION EXAMPLES

Example 1: Write to Data Buffer A; Write to Data Buffer B; Load DACA and DACB Simultaneously

•1st—Write to Data Buffer A:

•2nd—Write to Data Buffer B and Load DAC A and DAC B simultaneously:

Reserved Reserved LDB LDA DC

Buffer Select

PD1 PD0 DB15 ...... DB1 DB0

0000X000D15..... D1 D0

The DACA and DACB analog outputs simultaneously settle to the specified values upon completion of the 2nd write sequence.

(The “Load” command moves the digital data from the data buffer to the DAC register at which time the conversion takes place

and the analog output is updated. “Completion” occurs on the 24th falling SCLK edge after SYNC LOW.)

Example 2: Load New Data to DACA and DACB Sequentially

•1st—Write to Data Buffer A and Load DAC A: DACA output settles to specified value on completion:

Reserved Reserved LDB LDA DC

Buffer Select

PD1 PD0 DB15 ...... DB1 DB0

0011X100D15..... D1 D0

•2nd—Write to Data Buffer B and Load DAC B: DACB output settles to specified value on completion:

Reserved Reserved LDB LDA DC

Buffer Select

PD1 PD0 DB15 ...... DB1 DB0

0001X000D15..... D1 D0

After completion of the 1

write cycle, the DACA analog output settles to the voltage specified; upon completion of write cycle 2,

the DACB analog output settles.

Example 3: Power-Down DACA to 1kΩ and Power-Down DACB to 100kΩ Simultaneously

•1st—Write power-down command to Data Buffer A:

Reserved Reserved LDB LDA DC

Buffer Select

PD1 PD0 DB15 ...... DB1 DB0

0010X100D15..... D1 D0

•2nd—Write power-down command to Data Buffer B and Load DACA and DACB simultaneously:

Reserved Reserved LDB LDA DC

Buffer Select

PD1 PD0 DB15 ...... DB1 DB0

0000X001 Don’t Care

Reserved Reserved LDB LDA DC

Buffer Select

PD1 PD0 DB15 ...... DB1 DB0

0011X110 Don’t Care

The DACA and DACB analog outputs simultaneously power-down to each respective specified mode upon completion of the

2nd write sequence.

Example 4: Power-Down DACA and DACB to High Impedance Sequentially:

•1st—Write power-down command to Data Buffer A and Load DAC A: DAC A output = High-Z:

Reserved Reserved LDB LDA DC

Buffer Select

PD1 PD0 DB15 ...... DB1 DB0

0001X011 Don’t Care

Reserved Reserved LDB LDA DC

Buffer Select

PD1 PD0 DB15 ...... DB1 DB0

0010X111 Don’t Care

•2nd—Write power-down command to Data Buffer B and Load DAC B: DAC B output = High-Z:

The DACA and DACB analog outputs sequentially power-down to high impedance upon completion of the 1st and 2nd write

sequences, respectively.

DAC8532

14 SBAS246A

www.ti.com

DAC8532 to Microwire INTERFACE

Figure 7 shows an interface between the DAC8532 and any

Microwire compatible device. Serial data is shifted out on the

falling edge of the serial clock and is clocked into the

DAC8532 on the rising edge of the SK signal.

MICROPROCESSOR

INTERFACING

DAC8532 to 8051 INTERFACE

Figure 6 shows a serial interface between the DAC8532 and

a typical 8051-type microcontroller. The setup for the inter-

face is as follows: TXD of the 8051 drives SCLK of the

DAC8532, while RXD drives the serial data line of the device.

The SYNC signal is derived from a bit-programmable pin on

the port of the 8051. In this case, port line P3.3 is used. When

data is to be transmitted to the DAC8532, P3.3 is taken LOW.

The 8051 transmits data in 8-bit bytes; thus only eight falling

clock edges occur in the transmit cycle. To load data to the

DAC, P3.3 is left LOW after the first eight bits are transmitted,

then a second and third write cycle is initiated to transmit the

remaining data. P3.3 is taken HIGH following the completion

of the third write cycle. The 8051 outputs the serial data in a

format which presents the LSB first, while the DAC8532

requires its data with the MSB as the first bit received. The

8051 transmit routine must therefore take this into account,

and “mirror” the data as needed.

The 68HC11 should be configured so that its CPOL bit is 0

and its CPHA bit is 1. This configuration causes data appear-

ing on the MOSI output to be valid on the falling edge of SCK.

When data is being transmitted to the DAC, the SYNC line is

held LOW (PC7). Serial data from the 68HC11 is transmitted

in 8-bit bytes with only eight falling clock edges occurring in

the transmit cycle. (Data is transmitted MSB first.) In order to

load data to the DAC8532, PC7 is left LOW after the first

eight bits are transferred, then a second and third serial write

operation is performed to the DAC. PC7 is taken HIGH at the

end of this procedure.

DAC8532 to TMS320 DSP INTERFACE

Figure 9 shows the connections between the DAC8532 and

a TMS320 digital signal processor. By decoding the FSX

signal, multiple DAC8532s can be connected to a single

serial port of the DSP.

FIGURE 6. DAC8532 to 80C51/80L51 Interface.

FIGURE 7. DAC8532 to Microwire Interface.

FIGURE 8. DAC8532 to 68HC11 Interface.

DAC8532 to 68HC11 INTERFACE

Figure 8 shows a serial interface between the DAC8532 and

the 68HC11 microcontroller. SCK of the 68HC11 drives the

SCLK of the DAC8532, while the MOSI output drives the

serial data line of the DAC. The SYNC signal is derived from

a port line (PC7), similar to the 8051 diagram.

FIGURE 9. DAC8532 to TMS320 DSP.

DAC8532

TMS320 DSP

SYNC

DIN

SCLK

FSX

CLKX

VDD

VOUTA

VOUTB

Output A

Output B

Reference

Input

VREF

GND

0.1µF1µF to 10µF

Positive Supply

0.1µF10µF

APPLICATIONS

CURRENT CONSUMPTION

The DAC8532 typically consumes 250uA at VDD = 5V and

225uA at VDD = 3V for each active channel, including refer-

ence current consumption. Additional current consumption

can occur at the digital inputs if VIH<<VDD. For most efficient

power operation, CMOS logic levels are recommended at the

digital inputs to the DAC.

In power-down mode, typical current consumption is 200nA.

A delay time of 10 to 20ms after a power-down command is

issued to the DAC is typically sufficient for the power-down

current to drop below 10µA.

80C51/80L51

(1)

P3.3

TXD

RXD

DAC8532

(1)

SYNC

SCLK

NOTE: (1) Additional pins omitted for clarity.

SYNC

SCLK

DIN

MicrowireTM

DAC8532(1)

NOTE: (1) Additional pins omitted for clarity.

Microwire is a registered trademark of National Semiconductor.

68HC11

(1)

PC7

SCK

MOSI

SYNC

SCLK

DAC8532

(1)

NOTE: (1) Additional pins omitted for clarity.

DAC8532

SBAS246A www.ti.com

DRIVING RESISTIVE AND CAPACITIVE LOADS

The DAC8532 output stage is capable of driving loads of up

to 1000pF while remaining stable. Within the offset and gain

error margins, the DAC8532 can operate rail-to-rail when

driving a capacitive load. Resistive loads of 2kΩ can be

driven by the DAC8532 while achieving a typical load regu-

lation of 1%. As the load resistance drops below 2kΩ, the

load regulation error increases. When the outputs of the DAC

are driven to the positive rail under resistive loading, the

PMOS transistor of each Class-AB output stage can enter

into the linear region. When this occurs, the added IR voltage

drop deteriorates the linearity performance of the DAC. This

only occurs within approximately the top 20mV of the DAC’s

digital input-to-voltage output transfer characteristic. The

reference voltage applied to the DAC8532 may be reduced

below the supply voltage applied to VDD in order to eliminate

this condition if good linearity is a requirement at full scale

(under resistive loading conditions).

CROSSTALK AND AC PERFORMANCE

The DAC8532 architecture uses separate resistor strings for

each DAC channel in order to achieve ultra-low crosstalk

performance. DC crosstalk seen at one channel during a full-

scale change on the neighboring channel is typically less than

0.5LSBs. The AC crosstalk measured (for a full-scale, 1kHz

sine wave output generated at one channel, and measured at

the remaining output channel) is typically under –100dB.

In addition, the DAC8532 can achieve typical AC perfor-

mance of 96dB SNR (Signal-to-Noise Ratio) and 65db THD

(Total Harmonic Distortion), making the DAC8532 a solid

choice for applications requiring low SNR at output frequen-

cies at or below 4kHz.

OUTPUT VOLTAGE STABILITY

The DAC8532 exhibits excellent temperature stability of

5ppm/°C typical output voltage drift over the specified tem-

perature range of the device. This enables the output voltage

of each channel to stay within a ±25µV window for a ±1°C

ambient temperature change.

Good Power-Supply Rejection Ratio (PSRR) performance

reduces supply noise present on VDD from appearing at the

outputs to well below 10µV-s. Combined with good DC noise

performance and true 16-bit differential linearity, the DAC8532

becomes a perfect choice for closed-loop control applica-

tions.

SETTLING TIME AND OUTPUT

GLITCH PERFORMANCE

Settling time to within the 16-bit accurate range of the

DAC8532 is achievable within 10µs for a full-scale code

change at the input. Worst case settling times between

consecutive code changes is typically less than 2µs, en-

abling update rates up to 500ksps for digital input signals

changing code-to-code. The high-speed serial interface of

the DAC8532 is designed in order to support these high

update rates.

For full-scale output swings, the output stage of each

DAC8532 channel typically exhibits less than 100mV of

overshoot and undershoot when driving a 200pF capacitive

load. Code-to-code change glitches are extremely low

(~10uV) given that the code-to-code transition does not

cross an Nx4096 code boundary. Due to internal segmen-

tation of the DAC8532, code-to-code glitches occur at each

crossing of an Nx4096 code boundary. These glitches can

approach 100mVs for N = 15, but settle out within ~2µs.

USING REF02 AS A POWER SUPPLY FOR DAC8532

Due to the extremely low supply current required by the

DAC8532, a possible configuration is to use a REF02 +5V

precision voltage reference to supply the required voltage to

the DAC8532's supply input as well as the reference input, as

shown in Figure 10. This is especially useful if the power

supply is quite noisy or if the system supply voltages are at

some value other than 5V. The REF02 will output a steady

supply voltage for the DAC8532. If the REF02 is used, the

current it needs to supply to the DAC8532 is 567µA typical

and 890µA max for VDD = 5V. When a DAC output is loaded,

the REF02 also needs to supply the current to the load. The

total typical current required (with a 5kΩ load on a given DAC

output) is:

567µA + (5V/5kΩ) = 1.567mA

FIGURE 10. REF02 as a Power Supply to the DAC8532.

REF02

DAC8532

3-Wire

Serial

Interface

+5V

1.567mA

VDD, VREF

VOUT = 0V to 5V

SYNC

SCLK

DIN

+15

The load regulation of the REF02 is typically 0.005%/mA,

which results in an error of 392µV for the 1.5mA current

drawn from it. This corresponds to a 5.13LSB error for a 0V

to 5V output range.

BIPOLAR OPERATION USING THE DAC8532

The DAC8532 has been designed for single-supply opera-

tion but a bipolar output range is also possible using the

circuit in Figure 11. The circuit shown will give an output

voltage range of ±VREF. Rail-to-rail operation at the amplifier

output is achievable using an amplifier such as the OPA703,

see Figure 11.

DAC8532

16 SBAS246A

www.ti.com

The output voltage for any input code can be calculated as

follows:

VXV DRR

RVR

OUT REF REF

=•









•+









•





















65536

–

where D represents the input code in decimal (0–65535).

With VREF = 5V, R1 = R2 = 10kΩ:

VX DV

OUT =•











65536 5–

This is an output voltage range of ±5V with 0000H corre-

sponding to a –5V output and FFFFH corresponding to a +5V

output. Similarly, using VREF = 2.5V, a ±2.5V output voltage

range can be achieved.

LAYOUT

A precision analog component requires careful layout, ad-

equate bypassing, and clean, well-regulated power supplies.

The DAC8532 offers single-supply operation, and it will often

be used in close proximity with digital logic, microcontrollers,

microprocessors, and digital signal processors. The more

digital logic present in the design and the higher the switch-

ing speed, the more difficult it will be to keep digital noise

from appearing at the output.

FIGURE 11. Bipolar Operation with the DAC8532.

DAC8532

(Other pins omitted for clarity.)

, V

REF

OUT

10kΩ

+5V

10µF0.1µF–5V

±5V

+5V

OPA703

Due to the single ground pin of the DAC8532, all return

currents, including digital and analog return currents for the

DAC, must flow through a single point. Ideally, GND would

be connected directly to an analog ground plane. This plane

would be separate from the ground connection for the digital

components until they were connected at the power entry

point of the system.

The power applied to VDD should be well regulated and low

noise. Switching power supplies and DC/DC converters will

often have high-frequency glitches or spikes riding on the

output voltage. In addition, digital components can create

similar high-frequency spikes as their internal logic switches

states. This noise can easily couple into the DAC output

voltage through various paths between the power connec-

tions and analog output.

As with the GND connection, VDD should be connected to a

positive power-supply plane or trace that is separate from the

connection for digital logic until they are connected at the

power entry point. In addition, a 1µF to 10µF capacitor in

parallel with a 0.1µF bypass capacitor is strongly recom-

mended. In some situations, additional bypassing may be

required, such as a 100µF electrolytic capacitor or even a

“Pi” filter made up of inductors and capacitors—all designed

to essentially low-pass filter the supply, removing the high-

frequency noise.

PACKAGE OPTION ADDENDUM

www.ti.com 16-Aug-2012

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status (1) Package Type Package

Drawing Pins Package Qty Eco Plan (2) Lead/

Ball Finish MSL Peak Temp (3) Samples

(Requires Login)

DAC8532IDGK ACTIVE VSSOP DGK 8 80 Green (RoHS

& no Sb/Br) CU NIPDAUAGLevel-2-260C-1 YEAR

DAC8532IDGKG4 ACTIVE VSSOP DGK 8 80 Green (RoHS

& no Sb/Br) CU NIPDAUAGLevel-2-260C-1 YEAR

DAC8532IDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS

& no Sb/Br) CU NIPDAUAGLevel-2-260C-1 YEAR

DAC8532IDGKRG4 ACTIVE VSSOP DGK 8 2500 Green (RoHS

& no Sb/Br) CU NIPDAUAGLevel-2-260C-1 YEAR

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

DAC8532IDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 16-Aug-2012

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

DAC8532IDGKR VSSOP DGK 8 2500 367.0 367.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 16-Aug-2012

Pack Materials-Page 2

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other

changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should

obtain the latest relevant information before placing orders and should verify that such information is current and complete. All

semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time

of order acknowledgment.

TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms

and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary

to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily

performed.

TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and

applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide

adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or

other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information

published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or

endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the

third party, or a license from TI under the patents or other intellectual property of TI.

Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration

and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered

documentation. Information of third parties may be subject to additional restrictions.

Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service

voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.

TI is not responsible or liable for any such statements.

Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements

concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support

that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which

anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause

harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use

of any TI components in safety-critical applications.

In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to

help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and

requirements. Nonetheless, such components are subject to these terms.

No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties

have executed a special agreement specifically governing such use.

Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in

military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components

which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and

regulatory requirements in connection with such use.

TI has specifically designated certain components which meet ISO/TS16949 requirements, mainly for automotive use. Components which

have not been so designated are neither designed nor intended for automotive use; and TI will not be responsible for any failure of such

components to meet such requirements.

Products Applications

Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive

Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications

Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers

DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps

DSP dsp.ti.com Energy and Lighting www.ti.com/energy

Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial

Interface interface.ti.com Medical www.ti.com/medical

Logic logic.ti.com Security www.ti.com/security

Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense

Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video

RFID www.ti-rfid.com

OMAP Mobile Processors www.ti.com/omap TI E2E Community e2e.ti.com

Wireless Connectivity www.ti.com/wirelessconnectivity

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265