1. General description
The 74LVC595A is an 8-bit serial-in/serial or parallel-out shift register with a storage
register and 3-state outputs. Both the shift and storage register have separate clocks.
The input can be driven from either 3.3 Vor 5 V devices. This feature allows the use of
this device in a mixed 3.3 Vand 5 V environment.
This device is fully specified for partial Power-down applications using IOFF.
The IOFF circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
Data is shifted on the positive-going transitions of the SHCP input. The data in the shift
register is transferred to the storage register on a positive-going transition of the STCP
input. If both clocks are connected together, the shift register will always be one clock
pulse ahead of the storage register.
The shift register has a serial input (DS) and a serial output (Q7S) for cascading
purposes. It is also provided with asynchronous reset input MR (active LOW) for all 8 shift
register stages. The storage register has 8 parallel 3-state bus driver outputs. Data in the
storage register appears at the output whenever the output enable input (OE) is LOW.
2. Features
■5 V tolerant inputs/outputs for interfacing with 5 V logic
■Wide supply voltage range from 1.2 V to 3.6 V
■CMOS low-power consumption
■Direct interface with TTL levels
■Balanced propagation delays
■All inputs have Schmitt-trigger action
■Complies with JEDEC standard JESD8-B/JESD36
■ESD protection:
◆HBM JESD22-A114-D exceeds 2000 V
◆CDM JESD22-C101-C exceeds 1000 V
■Specified from −40 °C to +85 °C and −40 °C to +125 °C.
3. Applications
■Serial-to-parallel data conversion
■Remote control holding register
74LVC595A
8-bit serial-in/serial-out or parallel-out shift register; 3-state
Rev. 01 — 29 May 2007 Product data sheet
74LVC595A_1 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 01 — 29 May 2007 2 of 19
NXP Semiconductors 74LVC595A
8-bit serial-in/serial-out or parallel-out shift register; 3-state
4. Ordering information
5. Functional diagram
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
74LVC595AD −40 °C to +125 °C SO16 plastic small outline package; 16 leads;
body width 3.9 mm SOT109-1
74LVC595APW −40 °C to +125 °C TSSOP16 plastic thin shrink small outline package; 16 leads;
body width 4.4 mm SOT403-1
74LVC595ABQ −40 °C to +125 °C DHVQFN16 plastic dual in-line compatible thermal enhanced
very thin quad flat package; no leads; 16
terminals; body 2.5 ×3.5 × 0.85 mm
SOT763-1
Fig 1. Logic symbol Fig 2. Functional diagram
OEMR
9
15
1
2
3
4
5
6
7
1310
14
11 12
mna552
Q1
Q0
Q2
Q3
Q4
Q5
Q6
Q7
Q7S
DS
STCP
SHCP
mna554
3-STATE OUTPUTS
8-BIT STORAGE REGISTER
8-STAGE SHIFT REGISTER
Q0Q1Q2Q3Q4Q5Q6Q7
Q7S
14
151234567
9
DS
SHCP
STCP
OE
11
10
12
13
MR
74LVC595A_1 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 01 — 29 May 2007 3 of 19
NXP Semiconductors 74LVC595A
8-bit serial-in/serial-out or parallel-out shift register; 3-state
Fig 3. Logic diagram
STAGE 0 STAGES 1 TO 6 STAGE 7
FF0
D
CP
Q
R
LATCH
D
CP
Q
FF7
D
CP
Q
R
LATCH
D
CP
Q
mna555
DQ
Q1Q2Q3Q4Q5Q6Q7
Q7S
Q0
DS
STCP
SHCP
OE
MR
Fig 4. Timing diagram
SHCP
DS
STCP
MR
OE
Q0
Q1
Q6
Q7
Q7S
Z-state
Z-state
Z-state
Z-state
mna556
74LVC595A_1 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 01 — 29 May 2007 4 of 19
NXP Semiconductors 74LVC595A
8-bit serial-in/serial-out or parallel-out shift register; 3-state
6. Pinning information
6.1 Pinning
6.2 Pin description
Fig 5. Pin configuration SO16 and TSSOP16 Fig 6. Pin configuration DHVQFN16
74LVC595A
Q1 VCC
Q2 Q0
Q3 DS
Q4 OE
Q5 STCP
Q6 SHCP
Q7 MR
GND Q7S
001aaf569
1
2
3
4
5
6
7
8
10
9
12
11
14
13
16
15
001aaf570
74LVC595A
Q7 MR
Q6 SHCP
Q5 STCP
Q4 OE
Q3 DS
Q2 Q0
GND
Q7S
Q1
VCC
Transparent top view
7 10
6 11
5 12
4 13
3 14
2 15
8
9
1
16
terminal 1
index area
Table 2. Pin description
Symbol Pin Description
Q[0:7] 15, 1, 2, 3, 4, 5, 6, 7 parallel data output
GND 8 ground (0 V)
Q7S 9 serial data output
MR 10 master reset (active LOW)
SHCP 11 shift register clock input
STCP 12 storage register clock input
OE 13 output enable input (active LOW)
DS 14 serial data input
VCC 16 supply voltage
74LVC595A_1 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 01 — 29 May 2007 5 of 19
NXP Semiconductors 74LVC595A
8-bit serial-in/serial-out or parallel-out shift register; 3-state
7. Functional description
[1] H = HIGH voltage state;
L = LOW voltage state;
↑= LOW-to-HIGH transition;
X = don’t care;
NC = no change;
Z = high-impedance OFF-state.
8. Limiting values
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For SO16 packages: above 70 °C the value of Ptot derates linearly with 8 mW/K.
For TSSOP16 packages: above 60 °C the value of Ptot derates linearly with 5.5 mW/K.
For DHVQFN16 packages: above 60 °C the value of Ptot derates linearly with 4.5 mW/K.
Table 3. Function table[1]
Input Output Function
SHCP STCP OE MR DS Q7S Qn
X X L L X L NC a LOW-state on MR only affects the shift register
X↑L L X L L empty shift register loaded into storage register
X X H L X L Z shift register clear; parallel outputs in high impedance OFF-state
↑X L H H Q6S NC logic HIGH-state shifted into shift register stage 0. Contents of all
shift register stages shifted through, e.g. previous state of stage 6
(internal Q6S) appears on the serial output (Q7S).
X↑L H X NC QnS contents of shift register stages (internal QnS) are transferred to
the storage register and parallel output stages
↑↑L H X Q6S QnS contents of shift register shifted through; previous contents of the
shift register is transferred to the storage register and the parallel
output stages
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage −0.5 +6.5 V
IIK input clamping current VI<0 V −50 - mA
VIinput voltage [1] −0.5 +6.5 V
IOK output clamping current VO>V
CC or VO<0 V - ±50 mA
VOoutput voltage 3-state [1] −0.5 6.5 V
output HIGH or LOW state [1] −0.5 VCC + 0.5 V
IOoutput current VO=0 VtoV
CC -±50 mA
ICC supply current - 100 mA
IGND ground current −100 - mA
Tstg storage temperature −65 +150 °C
Ptot total power dissipation Tamb =−40 °C to +125 °C[2] - 500 mW
74LVC595A_1 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 01 — 29 May 2007 6 of 19
NXP Semiconductors 74LVC595A
8-bit serial-in/serial-out or parallel-out shift register; 3-state
9. Recommended operating conditions
10. Static characteristics
Table 5. Recommended operating conditions
Symbol Parameter Conditions Min Typ Max Unit
VCC supply voltage 1.65 - 3.6 V
functional 1.2 - - V
VIinput voltage 0 - 5.5 V
VOoutput voltage 3-state 0 - 5.5 V
output HIGH or LOW state 0 - VCC V
Tamb ambient temperature −40 - +125 °C
∆t/∆V input transition rise and fall rate VCC = 1.65 V to 2.7 V 0 - 20 ns/V
VCC = 2.7 V to 3.6 V 0 - 10 ns/V
Table 6. Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions −40 °C to +85 °C−40 °C to +125 °C Unit
Min Typ[1] Max Min Max
VIH HIGH-level
input voltage VCC = 1.2 V 1.08 - - 1.08 - V
VCC = 1.65 V to 1.95 V 0.65 × VCC - - 0.65 × VCC -V
VCC = 2.3 V to 2.7 V 1.7 - - 1.7 - V
VCC = 2.7 V to 3.6 V 2.0 - - 2.0 - V
VIL LOW-level
input voltage VCC = 1.2 V - - 0.12 - 0.12 V
VCC = 1.65 V to 1.95 V - - 0.35 × VCC - 0.35 × VCC V
VCC = 2.3 V to 2.7 V - - 0.7 - 0.7 V
VCC = 2.7 V to 3.6 V - - 0.8 - 0.8 V
VOH HIGH-level
output
voltage
VI=V
IH or VIL
IO=−100 µA;
VCC = 1.65 V to 3.6 V VCC −0.2 - - VCC −0.3 - V
IO=−4 mA; VCC = 1.65 V 1.2 - - 1.05 - V
IO=−8 mA; VCC = 2.3 V 1.8 - - 1.65 - V
IO=−12 mA; VCC = 2.7 V 2.2 - - 2.05 - V
IO=−18 mA; VCC = 3.0 V 2.4 - - 2.25 - V
IO=−24 mA; VCC = 3.0 V 2.2 - - 2.0 - V
VOL LOW-level
output
voltage
VI=V
IH or VIL
IO= 100 µA;
VCC = 1.65 V to 3.6 V - - 0.2 - 0.3 V
IO= 4 mA; VCC = 1.65 V - - 0.45 - 0.65 V
IO= 8 mA; VCC = 2.3 V - - 0.6 - 0.8 V
IO= 12 mA; VCC = 2.7 V - - 0.4 - 0.6 V
IO= 24 mA; VCC = 3.0 V - - 0.55 - 0.8 V
IIinputleakage
current VCC = 3.6 V;
VI= 5.5 Vor GND -±0.1 ±5-±20 µA
74LVC595A_1 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 01 — 29 May 2007 7 of 19
NXP Semiconductors 74LVC595A
8-bit serial-in/serial-out or parallel-out shift register; 3-state
[1] All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb =25°C.
[2] For transceivers, the parameter IOZ includes the input leaking current.
11. Dynamic characteristics
IOZ OFF-state
output
current
VI=V
IH or VIL;
VO= 5.5 Vor GND;
VCC = 3.6 V
[2] - 0.1 ±10 - ±20 µA
IOFF power-off
leakage
current
VCC = 0 V; VIor VO= 5.5 V - 0.1 10 - 20 µA
ICC supply
current VCC = 3.6 V;
VI=V
CC or GND; IO=0A - 0.1 10 - 40 µA
∆ICC additional
supply
current
per input pin;
VCC = 1.65 V to 3.6 V;
VI=V
CC −0.6 V; IO=0A
- 5 500 - 5000 µA
CIinput
capacitance VCC = 0 V to 3.6 V;
VI= GND to VCC
- 5.0 - - - pF
Table 6. Static characteristics
…continued
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions −40 °C to +85 °C−40 °C to +125 °C Unit
Min Typ[1] Max Min Max
Table 7. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 13.
Symbol Parameter Conditions −40 °C to +85 °C−40 °C to +125 °C Unit
Min Typ[1] Max Min Max
tpd propagation delay SHCP to Q7S; see Figure 7 [2]
VCC = 1.2 V - 17.5 - - - ns
VCC = 1.65 V to 1.95 V 2.0 6.6 15.8 2.0 18.2 ns
VCC = 2.3 V to 2.7 V 1.5 4.2 8.1 1.5 9.3 ns
VCC = 2.7 V 1.5 4.7 7.6 1.5 8.7 ns
VCC = 3.0 V to 3.6 V 1.5 4.0 6.7 1.5 7.7 ns
STCP to Qn; see Figure 8 [2]
VCC = 1.2 V - 16.8 - - - ns
VCC = 1.65 V to 1.95 V 2.0 5.8 15.8 2.0 18.2 ns
VCC = 2.3 V to 2.7 V 1.5 3.7 8.1 1.5 9.3 ns
VCC = 2.7 V 1.5 4.0 7.6 1.5 8.7 ns
VCC = 3.0 V to 3.6 V 1.2 3.3 6.7 1.2 7.7 ns
tPHL HIGH to LOW
propagation delay MR to Q7S; see Figure 11
VCC = 1.2 V - 17.3 - - - ns
VCC = 1.65 V to 1.95 V 2.0 6.9 15.8 2.0 18.2 ns
VCC = 2.3 V to 2.7 V 1.5 4.3 8.1 1.5 9.3 ns
VCC = 2.7 V 1.5 4.5 7.6 1.5 8.7 ns
VCC = 3.0 V to 3.6 V 1.2 3.8 6.7 1.2 7.7 ns
74LVC595A_1 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 01 — 29 May 2007 8 of 19
NXP Semiconductors 74LVC595A
8-bit serial-in/serial-out or parallel-out shift register; 3-state
ten enable time OE to Qn; see Figure 12 [3]
VCC = 1.2 V - 17.9 - - - ns
VCC = 1.65 V to 1.95 V 2.0 6.4 14.1 2.0 16.2 ns
VCC = 2.3 V to 2.7 V 1.5 4.2 8.0 1.5 9.2 ns
VCC = 2.7 V 1.5 4.5 7.6 1.5 8.7 ns
VCC = 3.0 V to 3.6 V 1.2 3.8 6.7 1.2 7.7 ns
tdis disable time OE to Qn; see Figure 12 [4]
VCC = 1.2 V - 9.6 - - - ns
VCC = 1.65 V to 1.95 V 2.0 4.9 9.8 2.0 11.2 ns
VCC = 2.3 V to 2.7 V 1.2 2.8 5.8 1.2 6.6 ns
VCC = 2.7 V 1.5 3.7 6.2 1.5 7.1 ns
VCC = 3.0 V to 3.6 V 1.2 3.5 5.7 1.2 6.5 ns
tWpulse width SHCP, STCP HIGH or LOW;
see Figure 7 and Figure 8
VCC = 1.65 V to 1.95 V 6.0 2.5 - 7.0 - ns
VCC = 2.3 V to 2.7 V 5.0 2.0 - 5.5 - ns
VCC = 2.7 V 4.5 1.5 - 5.0 - ns
VCC = 3.0 V to 3.6 V 4.0 1.5 - 4.5 - ns
MR LOW; see Figure 11
VCC = 1.65 V to 1.95 V 5.0 2.0 - 5.5 - ns
VCC = 2.3 V to 2.7 V 4.0 1.5 - 4.5 - ns
VCC = 2.7 V 2.5 1.0 - 3.0 - ns
VCC = 3.0 V to 3.6 V 2.5 1.0 - 3.0 - ns
tsu set-up time DS to SHCP; see Figure 9
VCC = 1.65 V to 1.95 V 5.0 0.4 - 5.5 - ns
VCC = 2.3 V to 2.7 V 4.0 0.1 - 4.5 - ns
VCC = 2.7 V 2.0 0 - 2.5 - ns
VCC = 3.0 V to 3.6 V 2.0 −0.1 - 2.5 - ns
MR to STCP; see Figure 10
VCC = 1.65 V to 1.95 V 8.0 3.5 - 8.5 - ns
VCC = 2.3 V to 2.7 V 5.0 2.1 - 5.5 - ns
VCC = 2.7 V 4.0 1.8 - 4.5 - ns
VCC = 3.0 V to 3.6 V 4.0 1.7 - 4.5 - ns
SHCP to STCP; see Figure 8
VCC = 1.65 V to 1.95 V 8.0 3.5 - 8.5 - ns
VCC = 2.3 V to 2.7 V 5.0 2.1 - 5.5 - ns
VCC = 2.7 V 4.0 1.8 - 4.5 - ns
VCC = 3.0 V to 3.6 V 4.0 1.7 - 4.5 - ns
Table 7. Dynamic characteristics
…continued
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 13.
Symbol Parameter Conditions −40 °C to +85 °C−40 °C to +125 °C Unit
Min Typ[1] Max Min Max
74LVC595A_1 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 01 — 29 May 2007 9 of 19
NXP Semiconductors 74LVC595A
8-bit serial-in/serial-out or parallel-out shift register; 3-state
[1] Typical values are measured at Tamb =25°C and VCC = 1.8 V, 2.5 V, 2.7 V, and 3.3 V respectively.
[2] tpd is the same as tPLH and tPHL.
[3] ten is the same as tPZH and tPZL.
[4] tdis is the same as tPHZ and tPLZ.
[5] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
[6] CPD is used to determine the dynamic power dissipation (PDin µW).
PD=C
PD ×VCC2×fi×N+∑(CL×VCC2×fo) where:
fi= input frequency in MHz;
fo= output frequency in MHz;
CL= output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
∑(CL×VCC2×fo) = sum of outputs.
thhold time DS to SHCP; see Figure 9
VCC = 1.65 V to 1.95 V 1.5 0.2 - 2.0 - ns
VCC = 2.3 V to 2.7 V 1.5 0.1 - 2.0 - ns
VCC = 2.7 V 1.5 −0.1 - 2.0 - ns
VCC = 3.0 V to 3.6 V 1.0 −0.2 - 1.5 - ns
trec recovery time MR to SHCP; see Figure 11
VCC = 1.65 V to 1.95 V 5.0 −2.7 - 5.5 - ns
VCC = 2.3 V to 2.7 V 4.0 −1.5 - 4.5 - ns
VCC = 2.7 V 2.0 −1.0 - 2.5 - ns
VCC = 3.0 V to 3.6 V 2.0 −1.0 - 2.5 - ns
fmax maximum
frequency SHCP or STCP; see Figure 7
and Figure 8
VCC = 1.65 V to 1.95 V 80 130 - 70 - MHz
VCC = 2.3 V to 2.7 V 100 140 - 90 - MHz
VCC = 2.7 V 110 150 - 100 - MHz
VCC = 3.0 V to 3.6 V 130 180 - 115 - MHz
tsk(o) output skew time VCC = 3.0 V to 3.6 V [5] - - 1.0 - 1.5 ns
CPD power dissipation
capacitance VI = GND to VCC [6]
VCC = 1.65 V to 1.95 V - 50 - - - pF
VCC = 2.3 V to 2.7 V - 45 - - - pF
VCC = 3.0 V to 3.6 V - 44 - - - pF
Table 7. Dynamic characteristics
…continued
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 13.
Symbol Parameter Conditions −40 °C to +85 °C−40 °C to +125 °C Unit
Min Typ[1] Max Min Max
74LVC595A_1 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 01 — 29 May 2007 10 of 19
NXP Semiconductors 74LVC595A
8-bit serial-in/serial-out or parallel-out shift register; 3-state
12. Waveforms
Measurement points are given in Table 8.
VOL and VOH are typical output voltage drops that occur with the output load.
Fig 7. The shift clock (SHCP) to serial data output (Q7S) propagation delays, the shift clock pulse width and
maximum shift clock frequency
mna557
SHCP input
Q7S output
tPLH tPHL
tW
1/fmax
VM
VOH
VI
GND
VOL
VM
Measurement points are given in Table 8.
VOL and VOH are typical output voltage drops that occur with the output load.
Fig 8. The storage clock (STCP) to parallel data output (Qn) propagation delays, the storage clock pulse width
and the shift clock to storage clock set-up time
mna558
STCP input
Qn output
tPLH tPHL
tW
tsu 1/fmax
VM
VOH
VI
GND
VOL
VM
SHCP input
VI
GND
VM
74LVC595A_1 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 01 — 29 May 2007 11 of 19
NXP Semiconductors 74LVC595A
8-bit serial-in/serial-out or parallel-out shift register; 3-state
Measurement points are given in Table 8.
The shaded areas indicate when the input is permitted to change for predictable output performance.
VOL and VOH are typical output voltage drops that occur with the output load.
Fig 9. The data set-up and hold times for the serial data input (DS)
mna560
GND
GND
th
tsu th
tsu
VM
VM
VM
VI
VOH
VOL
VI
Q7S output
SHCP input
DS input
Measurement points are given in Table 8.
VOL and VOH are typical output voltage drops that occur with the output load.
Fig 10. The master reset (MR) to storage clock (STCP) set-up times
001aaf571
MR input
STCP input
Qn outputs
tsu
VM
VI
VI
GND
GND
VOH
VOL
VM
VM
74LVC595A_1 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 01 — 29 May 2007 12 of 19
NXP Semiconductors 74LVC595A
8-bit serial-in/serial-out or parallel-out shift register; 3-state
Measurement points are given in Table 8.
VOL and VOH are typical output voltage drops that occur with the output load.
Fig 11. The master reset (MR) pulse width, the master reset to serial data output (Q7S) propagation delays and the
master reset to shift clock (SHCP) recovery time
mna561
MR input
SHCP input
Q7S output
tPHL
tWtrec
VM
VOH
VOL
VI
GND
VI
GND
VM
VM
Measurement points are given in Table 8.
VOL and VOH are typical output voltage drops that occur with the output load.
Fig 12. 3-state enable and disable times
001aae821
tPLZ
tPHZ
outputs
disabled outputs
enabled
VY
VX
outputs
enabled
output
LOW-to-OFF
OFF-to-LOW
output
HIGH-to-OFF
OFF-to-HIGH
OE input
VI
VCC
VM
VOL
VOH
GND
GND
tPZL
tPZH
VM
VM
Table 8. Measurement points
Supply voltage Input Output
VCC VMVMVXVY
VCC < 2.7 V 0.5 × VCC 0.5 × VCC VOL +0.15 V VOH −0.15 V
VCC ≥2.7 V 1.5 V 1.5 V VOL +0.3 V VOH −0.3 V
74LVC595A_1 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 01 — 29 May 2007 13 of 19
NXP Semiconductors 74LVC595A
8-bit serial-in/serial-out or parallel-out shift register; 3-state
Test data is given in Table 9. Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 13. Load circuitry for switching times
VMVM
tW
tW
10 %
90 %
0 V
VI
VI
negative
pulse
positive
pulse
0 V
VMVM
90 %
10 %
tf
tr
tr
tf
001aae331
VEXT
VCC
VIVO
DUT
CL
RT
RL
RL
PULSE
GENERATOR
Table 9. Test data
Supply voltage Input Load VEXT
VItr, tfCLRLtPLH, tPHL tPLZ, tPZL tPHZ, tPZH
1.2 V VCC ≤ 2 ns 30 pF 1 kΩopen 2 × VCC GND
1.65 V to 1.95 V VCC ≤ 2 ns 30 pF 1 kΩopen 2 × VCC GND
2.3 V to 2.7 V VCC ≤ 2 ns 30 pF 500 Ωopen 2 × VCC GND
2.7 V 2.7 V ≤ 2.5 ns 50 pF 500 Ωopen 2 × VCC GND
3.0 V to 3.6 V 2.7 V ≤ 2.5 ns 50 pF 500 Ωopen 2 × VCC GND
74LVC595A_1 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 01 — 29 May 2007 14 of 19
NXP Semiconductors 74LVC595A
8-bit serial-in/serial-out or parallel-out shift register; 3-state
13. Package outline
Fig 14. Package outline SOT109-1 (SO16)
X
wM
θ
A
A1
A2
bp
D
HE
Lp
Q
detail X
E
Z
e
c
L
vMA
(A )
3
A
8
9
1
16
y
pin 1 index
UNIT A
max. A1A2A3bpcD
(1) E(1) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm
inches
1.75 0.25
0.10 1.45
1.25 0.25 0.49
0.36 0.25
0.19 10.0
9.8 4.0
3.8 1.27 6.2
5.8 0.7
0.6 0.7
0.3 8
0
o
o
0.25 0.1
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
1.0
0.4
SOT109-1 99-12-27
03-02-19
076E07 MS-012
0.069 0.010
0.004 0.057
0.049 0.01 0.019
0.014 0.0100
0.0075 0.39
0.38 0.16
0.15 0.05
1.05
0.041
0.244
0.228 0.028
0.020 0.028
0.012
0.01
0.25
0.01 0.004
0.039
0.016
0 2.5 5 mm
scale
SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
74LVC595A_1 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 01 — 29 May 2007 15 of 19
NXP Semiconductors 74LVC595A
8-bit serial-in/serial-out or parallel-out shift register; 3-state
Fig 15. Package outline SOT403-1 (TSSOP16)
UNIT A1A2A3bpcD
(1) E(2) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.15
0.05 0.95
0.80 0.30
0.19 0.2
0.1 5.1
4.9 4.5
4.3 0.65 6.6
6.2 0.4
0.3 0.40
0.06 8
0
o
o
0.13 0.10.21
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
0.75
0.50
SOT403-1 MO-153 99-12-27
03-02-18
wM
bp
D
Z
e
0.25
18
16 9
θ
A
A1
A2
Lp
Q
detail X
L
(A )
3
HE
E
c
vMA
X
A
y
0 2.5 5 mm
scale
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1
A
max.
1.1
pin 1 index
74LVC595A_1 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 01 — 29 May 2007 16 of 19
NXP Semiconductors 74LVC595A
8-bit serial-in/serial-out or parallel-out shift register; 3-state
Fig 16. Package outline SOT763-1 (DHVQFN16)
terminal 1
index area
0.51
A1Eh
b
UNIT ye
0.2
c
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 3.6
3.4
Dh
2.15
1.85
y1
2.6
2.4 1.15
0.85
e1
2.5
0.30
0.18
0.05
0.00 0.05 0.1
DIMENSIONS (mm are the original dimensions)
SOT763-1 MO-241 - - -- - -
0.5
0.3
L
0.1
v
0.05
w
0 2.5 5 mm
scale
SOT763-1
DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
16 terminals; body 2.5 x 3.5 x 0.85 mm
A(1)
max.
AA1c
detail X
y
y1C
e
L
Eh
Dh
e
e1
b
27
15 10
9
8
1
16
X
D
E
C
BA
terminal 1
index area
AC
CB
vM
wM
E(1)
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
D(1)
02-10-17
03-01-27
74LVC595A_1 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 01 — 29 May 2007 17 of 19
NXP Semiconductors 74LVC595A
8-bit serial-in/serial-out or parallel-out shift register; 3-state
14. Abbreviations
15. Revision history
Table 10. Abbreviations
Acronym Description
CDM Charged Device Model
CMOS Complementary Metal Oxide Semiconductor
DUT Device Under Test
ESD ElectroStatic Discharge
HBM Human Body Model
TTL Transistor-Transistor Logic
Table 11. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74LVC595A_1 20070529 Product data sheet - -
74LVC595A_1 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 01 — 29 May 2007 18 of 19
NXP Semiconductors 74LVC595A
8-bit serial-in/serial-out or parallel-out shift register; 3-state
16. Legal information
16.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
16.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of a NXP Semiconductors product can reasonably be expected to
result in personal injury, death or severe property or environmental damage.
NXP Semiconductors accepts no liability for inclusion and/or use of NXP
Semiconductors products in such equipment or applications and therefore
such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
17. Contact information
For additional information, please visit: http://www.nxp.com
For sales office addresses, send an email to: salesaddresses@nxp.com
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.
NXP Semiconductors 74LVC595A
8-bit serial-in/serial-out or parallel-out shift register; 3-state
© NXP B.V. 2007. All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 29 May 2007
Document identifier: 74LVC595A_1
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
18. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
4 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
7 Functional description . . . . . . . . . . . . . . . . . . . 5
8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
9 Recommended operating conditions. . . . . . . . 6
10 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
11 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7
12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14
14 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 17
15 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 17
16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 18
16.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 18
16.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
16.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 18
16.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 18
17 Contact information. . . . . . . . . . . . . . . . . . . . . 18
18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
