AM29F080-90SC - Advanced Micro Devices

PRELIMINARY

This document contains information on a product under development at Advanced Micro Devices. The information

is intended to help you e valuate this product. AMD reserves the right to change or discontinue work on this proposed

product without notice.

Publication# 19643 Rev: AAmendment/+1

Issue Date: April 1997

5.0 V-only Flash

Am29F080

8 Megabit (1,048,576 x 8-Bit) CMOS 5.0 Volt-only,

Sector Erase Flash Memory

DISTINCTIVE CHARACTERISTICS

■

5.0 V olt

10% for read and write operations

— Minimizes system level power requirements

■

Compatible with JEDEC-standards

— Pinout and software compatible with

single-power-supply Flash

— Superior inadvertent write protection

■

Package Options

— 40-pin TSOP

— 44-pin PSOP

■

Minimum 100,000 write/erase c ycles guaranteed

■

High performance

— 85 ns maximum access time

■

Sector erase architecture

— Uniform sectors of 64 Kbytes each

— Any combination of sectors can be erased.

Also supports full chip erase

■

Group sector protection

— Hardware method that disables any combination

of sector groups from write or erase operations

(a sector group consists of 2 adjacent sectors of

64 Kbytes each)

■

Embedded Erase™ Algorithms

— Automatically preprograms and erases the chip

or any sector

■

Embedded Program™ Algorithms

— Automatically programs and veriﬁes data at

speciﬁed address

■

Data P olling and T oggle Bit feature f or detection

of program or erase cycle completion

■

Ready/Busy output (RY/BY)

— Hardware method for detection of program or

erase cycle completion

■

Erase Suspend/Resume

— Supports

reading or programming

data to a

sector not being erased

■

Low power consumption

— 30 mA maximum active read current

— 60 mA maximum program/erase current

■

Enhanced power management for standby

mode

— <1

A typical standby current

— Standard access time from standby mode

■

Hardware RESET pin

— Resets internal state machine to the read mode

GENERAL DESCRIPTION

The Am29F080 is an 8 Mbit, 5.0 Volt-only Flash mem-

or y organized as 1 Megabyte of 8 bits. The 1 Mbyte of

data is divided into 16 sectors of 64 Kbytes for ﬂexible

erase capability. The 8 bits of data will appear on DQ0–

DQ7. The Am29F080 is offered in a 40-pin TSOP, or

44-pin PSOP package. This device is designed to be

programmed in-system with the standard system

5.0 volt V

supply. 12.0 volt V

is not required for

program or erase operations. The device can also be

reprogrammed in standard EPROM programmers.

The standard Am29F080 offers access times of 85 ns,

90 ns, 120 ns, and 150 ns allowing operation of high-

speed microprocessors without wait states. To

eliminate bus contention the device has separate chip

enable (CE), write enable (WE), and output enable

(OE) controls.

The Am29F080 is entirely command set compatible

with the JEDEC single-power-supply Flash standard.

Commands are written to the command register using

standard microprocessor write timings. Register

contents serve as input to an internal state-machine

which controls the erase and programming circuitry.

Write cycles also internally latch addresses and data

2 Am29F080

PRELIMINARY

needed for the programming and erase operations.

Reading data out of the device is similar to reading

from 12.0 volt Flash or conventional EPROM devices.

The Am29F080 is programmed by executing the

program command sequence. This will invoke the

Embedded Program Algorithm which is an internal al-

gorithm that automatically times the program pulse

widths and veriﬁes proper cell margin. Erase is accom-

plished by executing the erase command sequence.

This will invoke the Embedded Erase Algorithm which

is an internal algorithm that automatically preprograms

the arra y if it is not already prog rammed bef ore ex ecut-

ing the erase operation. During erase, the de vice auto-

matically times the erase pulse widths and veriﬁes

proper cell margin.

This device also features a sector erase architecture.

This allows for sectors of memory to be erased and re-

programmed without affecting the data contents of

other sectors. A sector is typically erased and veriﬁed

within one second. The Am29F080 is erased when

shipped from the factory.

The Am29F080 device also features hardware sector

group protection. This f eature will disable both prog ram

and erase operations in any combination of eight sector

groups of memory.

A sector group consists of two adja-

cent sectors grouped in the following pattern: sectors

0–1, 2–3, 4–5, 6–7, 8–9, 10–11, 12–13, and 14–15.

AMD has implemented an Erase Suspend feature that

enables the user to put erase on hold for any period of

time to read data from, or program data to , a sector that

was not being erased. Thus, true background erase

can be achieved.

The device features single 5.0 volt power supply oper-

ation for both read and write functions. Internally gen-

erated and regulated voltages are provided for the

program and erase operations. A low V

detector au-

tomatically inhibits write operations during power tran-

sitions. The end of program or er ase is detected by the

RY/BY pin, Data Polling of DQ7, or by the Toggle Bit I

(DQ6). Once the end of a program or erase cycle has

been completed, the de vice automatically resets to the

read mode.

The Am29F080 also has a hardware RESET pin. When

this pin is driven low, execution of any Embedded Pro-

gram Algorithm or Embedded Erase Algorithm will be

terminated. The internal state machine will then be

reset into the read mode. The RESET pin may be tied

to the system reset circuitry. Therefore, if a system

reset occurs during the Embedded Program Algorithm

or Embedded Erase Algorithm, the device will be auto-

matically reset to the read mode and will leave errone-

ous data stored in the address locations being

operated on. These locations will need re-writing after

the Reset. Resetting the device will enable the sys-

tem’s microprocessor to read the boot-up ﬁrmware

from the Flash memory.

AMD’s Flash technology combines years of Flash

memory manufacturing experience to produce the

highest levels of quality, reliability and cost effective-

ness. The Am29F080 memory electrically erases all

bits within a sector simultaneously via Fowler-Nord-

heim tunneling. The b ytes are prog rammed one b yte at

a time using the EPROM programming mechanism of

hot electron injection.

Flexible Sector-Erase Architecture

■

Sixteen 64 Kbyte sectors

■

Eight sector groups each of which consists of

2 adjacent sectors in the following pattern: sectors

0–1, 2–3, 4–5, 6–7, 8–9, 10–11, 12–13, and 14–15

■

Individual-sector or multiple-sector erase capability

■

Sector group protection is user-deﬁnable

0EFFFFh Sector

Group

SA15 64 Kbyte 0DFFFFh

SA14 64 Kbyte 0CFFFFh

SA13 64 Kbyte 0BFFFFh

SA12 64 Kbyte 0AFFFFh

16 Sectors Total

09FFFFh

08FFFFh

07FFFFh

06FFFFh

05FFFFh

04FFFFh

03FFFFh

SA3 64 Kbyte 02FFFFh

SA2 64 Kbyte 01FFFFh

SA1 64 Kbyte 00FFFFh Sector

Group

SA0 64 Kbyte 000000h

19643A-25

Am29F080 3

PRELIMINARY

5.0 V-only Flash

PRODUCT SELECTOR GUIDE

BLOCK DIAGRAM

Family Part No. Am29F080

Ordering Part

No: V

= 5.0 Volt

-85

= 5.0 Volt

10%

-90 -120 -150

Max Access Time (ns) 85 90 120 150

CE (E) Access (ns) 85 90 120 150

OE (G) Access (ns) 40 40 50 75

Erase Voltage

Generator

Y-Gating

Cell Matrix

X-Decoder

Y-Decoder

Address Latch

Chip Enable

Output Enable

Logic

PGM Voltage

Generator

Timer

VCC Detector

State

Control

Command

RY/BY

A0–A19

STB

DQ0–DQ7

VCC

VSS

19643A-1

Data Latch

Input/Output

Buffers

Sector Switches

RESET

4 Am29F080

PRELIMINARY

CONNECTION DIAGRAMS

8-Mbit Pinout

A19

A18

A17

A16

A15

A14

A13

A12

VCC

RESET

A11

A10

RY/BY

DQ7

DQ6

DQ5

DQ4

VCC

VSS

DQ3

DQ2

DQ1

DQ0

RY/BY

DQ7

DQ6

DQ5

DQ4

VCC

VSS

DQ3

DQ2

DQ1

DQ0

A19

A18

A17

A16

A15

A14

A13

A12

VCC

RESET

A11

A10

Standard TSOP

Reverse TSOP 19643A-2

Am29F080 5

PRELIMINARY

5.0 V-only Flash

CONNECTION DIAGRAMS

8-Mbit Pinout

PIN CONFIGURATION

A0–A19 = 20 Addresses

CE = Chip Enable

DQ0–DQ7 = 8 Data Inputs/Outputs

NC = Pin Not Connected Internally

OE = Output Enable

RESET = Hardware Reset Pin, Active Low

RY/BY = Ready/Busy Output

= +5.0 Volt Single-Power Supply

(

10% for -90, -120, -150) or

(

5% for -85)

= Device Ground

WE = Write Enable

LOGIC SYMBOL

RESET

A11

A10

DQ0

DQ1

DQ2

DQ3

VSS

VCC

A12

A13

A14

A15

A16

A17

A18

A19

RY/BY

DQ7

DQ6

DQ5

DQ4

VCC

PSOP 19643A-3

DQ0–DQ7

A0–A19

CE (E)

OE (G)

WE (W)

RESET RY/BY

19643A-4

6 Am29F080

PRELIMINARY

ORDERING INFORMATION

Standard Products

Valid Combinations

Valid Combinations list conﬁgurations planned to be sup-

ported in volume for this device. Consult the local AMD sales

ofﬁce to conﬁrm availability of speciﬁc v alid combinations and

to check on newly released combinations.

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is

formed by a combination of:

TEMPERATURE RANGE

C = Commercial (0°C to +70°C)

I = Industrial (–40°C to +85°C)

P ACKAGE TYPE

E = 40-Pin Thin Small Outline Package

(TSOP) Standard Pinout (TS 040)

F = 40-Pin Thin Small Outline Package

(TSOP) Reverse Pinout (TSR040)

S = 44-Pin Plastic Small Outline Package

(SO 044)

DEVICE NUMBER/DESCRIPTION

Am29F080

8 Megabit (1M x 8-Bit) CMOS Flash Memory

5.0 Volt-only Program and Erase

AM29F080 -85 E C

OPTIONAL PROCESSING

Blank = Standard Processing

B = Burn-In

SPEED OPTION

See Product Selector Guide and

Valid Combinations

AM29F080-85

EC, ECB, EI, EIB,

FC, FCB, FI, FIB,

SC, SCB, SI, SIB

AM29F080-90

AM29F080-120

AM29F080-150

Am29F080 7

PRELIMINARY

5.0 V-only Flash

Table 1. Am29F080 User Bus Operations

Legend:

L = logic 0, H = logic 1, X = Don’t Care. See DC Characteristics for voltage levels.

Notes:

1. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 5.

2. Refer to the section on Sector Group Protection.

Read Mode

The Am29F080 has two control functions which must

be satisﬁed in order to obtain data at the outputs. CE is

the power control and should be used for device selec-

tion. OE is the output control and should be used to

gate data to the output pins if the device is selected.

Address access time (t

ACC

) is equal to the delay

from stable addresses to valid output data. The chip

enable access time (t

) is the delay from stable ad-

dresses and stable CE to valid data at the output pins.

The output enable access time is the delay from the

falling edge of OE to valid data at the output pins (as-

suming the addresses have been stable for at least

ACC

–

time).

Standby Mode

There are two wa ys to implement the standb y mode on

the Am29F080 device, one using both the CE and

RESET pins; the other via the RESET pin only.

When using both pins, a CMOS standby mode is

achieved with CE and RESET inputs both held at V

0.3 V. Under this condition the current is typically

reduced to less than 1

A. A TTL standby mode is

achieved with CE and RESET pins held at V

. Under

this condition the current is typically reduced to 200

The device can be read with standard access time (t

)

from either of these standby modes.

When using the RESET pin only, a CMOS standby

mode is achie ved with RESET input held at V

0.3 V

(CE = don’t care). Under this condition the current is

typically reduced to less than 1

A. A TTL standby

mode is achieved with RESET pin held at V

(CE = don’t care). Under this condition the current is

typically reduced to less than 200

A. Once the RESET

pin is taken high, the de vice requires 500 ns of wak e up

time before outputs are valid for read access.

In the standby mode the outputs are in the high

impedance state, independent of the OE input.

Output Disable

With the OE input at a logic high le vel (V

), output from

the de vice is disabled. This will cause the output pins to

be in a high impedance state.

Operation CE OE WE A0 A1 A6 A9 DQ0–DQ7 RESET

A utoselect, AMD Manuf. Code (Note 1) L L H L L L V

Code H

Autoselect Device Code (Note 1) L L H H L L V

Code H

Read L L X A0 A1 A6 A9 D

OUT

Standby H XXXXXXHIGH Z H

Output Disable L H H XXXXHIGH Z H

Write L H L A0 A1 A6 A9 D

Verify Sector Group Protect (Note 2) L LHLHLV

Code H

Temporary Sector Group Unprotect XXXXXXX X V

Hardware Reset/Standby XXXXXXXHIGH Z L

8 Am29F080

PRELIMINARY

Autoselect

The autoselect mode allows the reading of a binary

code from the device and will identify its manufacturer

and type. This mode is intended for use by program-

ming equipment for the purpose of automatically

matching the device to be programmed with its corre-

sponding programming algorithm. This mode is func-

tional over the entire temperature range of the device.

To activate this mode, the programming equipment

must force VID (11.5 V to 12.5 V) on address pin A9.

Two identiﬁer bytes may then be sequenced from the

device outputs by toggling address A0 from VIL to VIH.

All addresses are don’t cares except A0, A1, and A6

(seeTable 2).

The manufacturer and device codes may also be read

via the command register, for instances when the

Am29F080 is erased or progr ammed in a system with-

out access to high voltage on the A9 pin. The command

sequence is illustrated in Table 5 (see Autoselect

Command Sequence).

Byte 0 (A0 = VIL) represents the manufacturer’s code

(AMD = 01H) and byte 1 (A0 = VIH) the device identiﬁer

code for Am29F080 = D5H. These two bytes are given

in the table below. All identiﬁers for manufacturer and

device will exhibit odd parity with DQ7 deﬁned as the

parity bit. In order to read the proper device codes

when executing the Autoselect, A1 must be VIL

(see Table 2).

The autoselect mode also facilitates the deter mination

of sector group protection in the system. By performing

a read operation at the address location XX02H with

the higher order address bits A17, A18, and A19 set to

the desired sector group address, the de vice will return

01H for a protected sector group and 00H for a non-

protected sector group.

Table 2. Am29F080 Sector Protection Verify Autoselect Codes

*Outputs 01H at protected sector addresses

Type A17 to A19 A6 A1 A0 Code

(HEX) DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0

Manufacturer Code—AMD X X X VIL VIL VIL 01H00000001

Am29F080 Device X X X VIL VIL VIH D5H11010101

Sector Group Protection Sector Group

Addr. VIL VIH VIL 01H* 00000001

Am29F080 9

PRELIMINARY

5.0 V-only Flash

Table 3. Sector Address Table

Table 4. Sector Group Addresses

A19 A18 A17 A16 Address Range

SA0 0000000000h–00FFFFh

SA1 0001010000h–01FFFFh

SA2 0010020000h–02FFFFh

SA3 0011030000h–03FFFFh

SA4 0100040000h–04FFFFh

SA5 0101050000h–05FFFFh

SA6 0110060000h–06FFFFh

SA7 0111070000h–07FFFFh

SA8 1000080000h–08FFFFh

SA9 1001090000h–09FFFFh

SA10 10100A0000h–0AFFFFh

SA11 10110B0000h–0BFFFFh

SA12 11000C0000h–0CFFFFh

SA13 11010D0000h–0DFFFFh

SA14 11100E0000h–0EFFFFh

SA15 11110F0000h–0FFFFFh

A19 A18 A17 Sectors

SGA0 0 0 0 SA0–SA1

SGA1 0 0 1 SA2–SA3

SGA2 0 1 0 SA4–SA5

SGA3 0 1 1 SA6–SA7

SGA4 1 0 0 SA8–SA9

SGA5 1 0 1 SA10–SA11

SGA6 1 1 0 SA12–SA13

SGA7 1 1 1 SA14–SA15

10 Am29F080

PRELIMINARY

Write

Device erasure and programming are accomplished

via the command register. The contents of the register

serve as inputs to the internal state machine. The state

machine outputs dictate the function of the device.

The command register itself does not occupy any ad-

dressable memory location. The register is a latch used

to store the commands, along with the address and

data inf ormation needed to execute the command. The

command register is written to by bringing WE to VIL,

while CE is at VIL and OE is at VIH. Addresses are

latched on the falling edge of WE or CE, whichever

happens later ; while data is latched on the rising edge

of WE or CE, whichever happens ﬁrst. Standard

microprocessor write timings are used.

Refer to AC Write Characteristics and the Erase/

Programming W aveforms for speciﬁc timing parameters.

Sector Group Protection

The Am29F080 features hardware sector group pro-

tection. This feature will disable both program and

erase operations in any combination of eight sector

groups of memory. Each sector group consists of two

adjacent sectors grouped in the following pattern: sec-

tors 0–1, 2–3, 4–5, 6–7, 8–9, 10–11, 12–13, 14–15

(see Table 4). The sector group protect feature is en-

abled using programming equipment at the user’s site.

The device is shipped with all sector groups unpro-

tected. Alternatively, AMD may program and protect

sector groups in the f actory prior to shipping the device

(AMD’s ExpressFlash™ Service).

It is possible to determine if a sector group is protected

in the system by writing an Autoselect command. Per-

forming a read operation at the address location

XX02H, where the higher order address bits A17, A18,

and A19 is the desired sector group address, will pro-

duce a logical “1” at DQ0 for a protected sector group.

See Table 2 for Autoselect codes.

Temporary Sector Group Unprotect

This feature allows temporary unprotection of previ-

ously protected sector groups of the Am29F080 de vice

in order to change data in-system. The Sector Group

Unprotect mode is activated by setting the RESET pin

to high voltage (12 V). During this mode, former ly pro-

tected sector groups can be programmed or er ased by

selecting the sector group addresses. Once the 12 V is

taken a w a y from the RESET pin, all the previously pro-

tected sector groups will be protected again. Refer to

Figures 15 and 16.

Command Deﬁnitions

Device operations are selected by writing speciﬁc ad-

dress and data sequences into the command register.

Writing incorrect address and data values or writ-

ing them in the improper sequence will reset the

device to the read mode. Table 5 deﬁnes the valid

Suspend (B0H) and Erase Resume (30H) commands

are valid only while the Sector Erase operation is in

progress. Moreover, both Reset/Read commands are

functionally equivalent, resetting the device to the

read mode.

Am29F080 11

PRELIMINARY

5.0 V-only Flash

Table 5. Am29F080 Command Deﬁnitions

Notes:

1. Bus operations are deﬁned in Table 1.

2. RA = Address of the memory location to be read.

PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the WE pulse.

SA = Address of the sector to be erased. The combination of A19, A18, A17, and A16 will uniquely select any sector.

3. RD = Data read from location RA during read operation.

PD = Data to be programmed at location PA. Data is latched on the rising edge of WE.

4. Read and Byte program functions to non-erasing sectors are allowed in the Erase Suspend mode.

5. Address bits A15, A14, A13, A12 and A11 = X, X = don’t care.

Read/Reset Command

The read or reset operation is initiated by writing the

read/reset command sequence into the command reg-

ister. Microprocessor read cycles retrieve array data

from the memory. The device remains enabled for

reads until the command register contents are altered.

The device will automatically power-up in the read/

reset state. In this case, a command sequence is not

required to read data. Standard microprocessor read

cycles will retrieve array data. This default value en-

sures that no spurious alteration of the memory content

occurs during the power transition. Refer to the AC

Read Characteristics and Waveforms for the speciﬁc

timing parameters.

Command

Sequence

Read/Reset

Bus

Write

Cycles

Req’d

First Bus

Write Cycle Second Bus

Write Cycle Third Bus

Write Cycle

Fourth Bus

Read/Write

Cycle Fifth Bus

Write Cycle Sixth Bus

Write Cycle

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Reset/Read 1 XXXXH F0H

Reset/Read 3 5555H AAH 2AAAH 55H 5555H F0H RA RD

Autoselect 3 5555H AAH 2AAAH 55H 5555H 90H 00H/

01H 01H/

D5H

Byte Program 4 5555H AAH 2AAAH 55H 5555H A0H PA PD

Chip Erase 6 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H

Sector Erase 6 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H SA 30H

Erase Suspend 1 XXXXH B0H

Erase Resume 1 XXXXH 30H

12 Am29F080

PRELIMINARY

Autoselect Command

Flash memories are intended for use in applications

where the local CPU can alter memory contents. As

such, manufacture and device codes must be accessi-

ble while the device resides in the target system.

PROM programmers typically access the signature

codes by raising A9 to a high voltage. However, multi-

plexing high voltage onto the address lines is not

generally a desirable system design practice.

The de vice contains an autoselect command operation

to supplement traditional PR OM programming method-

ology. The operation is initiated by writing the autose-

lect command sequence into the command register.

Following the command write, a read cycle from ad-

dress XX00H retrieves the manufacturer code of 01H.

A read cycle from address XX01H returns the device

code D5H (see Table 2).

All manufacturer and de vice codes will exhibit odd par-

ity with DQ7 deﬁned as the parity bit.

Furthermore, the write protect status of sectors can be

read in this mode. Scanning the sector group ad-

dresses (A17, A18, and A19) while (A6, A1, A0) =

(0, 1, 0) will produce a logical “1” at de vice output DQ0

for a protected sector group.

To ter minate the operation, it is necessar y to write the

read/reset command sequence into the register.

Byte Programming

The device is programmed on a byte-by-byte basis.

Programming is a four bus cycle operation. There are

two “unlock” write cycles. These are followed by the

program setup command and data write cycles. Ad-

dresses are latched on the falling edge of CE or WE,

whiche v er happens later and the data is latched on the

rising edge of CE or WE, whichever happens ﬁrst. The

rising edge of CE or WE (whichever happens ﬁrst) be-

gins programming using the Embedded Prog ram Algo-

rithm. Upon executing the algorithm, the system is

not

required to provide further controls or timings. The de-

vice will automatically provide adequate internally gen-

erated program pulses and verify the programmed cell

margin.

The automatic programming operation is completed

when the data on DQ7 (also used as Data Polling) is

equivalent to the data written to this bit at which time

the de vice returns to the read mode and addresses are

no longer latched (see Table 6, Write Operation Sta-

tus). Therefore , the device requires that a v alid address

to the de vice be supplied by the system at this particu-

lar instance of time for Data Polling operations. Data

Polling must be performed at the memory location

which is being programmed.

Any commands written to the chip during the Embed-

ded Program Algorithm will be ignored. If a hardware

reset occurs during the programming operation, the

data at that particular location will be corrupted.

Programming is allowed in any sequence and across

sector boundaries. Beware that a data “0” cannot be

programmed back to a “1”. Attempting to do so may

cause the device to exceed programming time limits

(DQ5 = 1) device or result in an apparent success, ac-

cording to the data polling algorithm, but a read from

reset/read mode will show that the data is still “0”. Only

erase operations can convert “0”s to “1”s.

Figure 1 illustrates the Embedded Programming Algo-

rithm using typical command strings and bus operations.

Chip Erase

Chip erase is a six bus cycle operation. There are two

“unlock” write cycles. These are followed by writing the

“setup” command. Two more “unlock” write cycles are

then followed by the chip erase command.

Chip erase does

not

require the user to program the

device prior to erase. Upon executing the Embedded

Erase Algorithm command sequence the device will

automatically program and v erify the entire memory f or

an all zero data pattern prior to electrical erase. The

erase is performed sequentially one sector at a time

(See table “Erase and Programming Performance” for

erase times). The system is not required to provide an y

controls or timings during these operations.

The automatic erase begins on the rising edge of the

last WE pulse in the command sequence and

terminates when the data on DQ7 is “1” (see Write Op-

eration Status section) at which time the de vice returns

to read mode.

Figure 2 illustrates the Embedded Erase Algorithm

using typical command strings and bus operations.

Sector Erase

Sector erase is a six b us cycle operation. There are two

“unlock” write cycles. These are followed by writing the

“setup” command. Two more “unlock” write cycles are

then f ollowed by the sector erase command. The sector

address (any address location within the desired

sector) is latched on the falling edge of WE, while the

command (30H) is latched on the rising edge of WE.

After a time-out of 50 µs from the rising edge of the last

sector erase command, the sector erase operation

will begin.

Multiple sectors may be erased sequentially by writ-

ing the six bus cycle oper ations as described abov e .

This sequence is followed with writes of the Sector

Erase command to addresses in other sectors de-

sired to be sequentially erased. The time between

writes must be less than 50 µs otherwise that com-

mand will not be accepted and erasure will start. It

is recommended that processor interrupts be dis-

abled during this time to guarantee this condition.

Am29F080 13

PRELIMINARY

5.0 V-only Flash

The interrupts can be re-enabled after the last Sec-

tor Erase command is written. A time-out of 50 µs

from the rising edge of the last WE will initiate the

execution of the Sector Erase command(s). If an-

other falling edge of the WE occurs within the 50 µs

time-out window the timer is reset. (Monitor DQ3 to

determine if the sector erase timer window is still

open, see section DQ3, Sector Erase Timer.) Any

command other than Sector Erase or Erase Sus-

pend during this period will reset the device to the

read mode, ignoring the previous command string.

In that case, restart the erase on those sectors and

allow them to complete.

(Refer to the Write Operation Status section for DQ3,

Sector Erase Timer, operation.) Loading the sector

erase buffer may be done in any sequence and with

any number of sectors (0 to 15).

Sector erase does

not

require the user to program the

device prior to erase. The device automatically pro-

grams all memory locations in the sector(s) to be

erased prior to electrical erase. When erasing a sector

or sectors the remaining unselected sectors are not af-

fected. The system is

not

required to provide any con-

trols or timings during these operations.

The automatic sector erase begins after the 50 µs time

out from the rising edge of the WE pulse for the last

sector erase command pulse and terminates when the

data on DQ7, Data Polling, is “1” (see Write Operation

Status section) at which time the device retur ns to the

read mode. Data Polling must be performed at an

address within any of the sectors being erased.

Figure 2 illustrates the Embedded Erase Algorithm

using typical command strings and bus operations.

Erase Suspend

The Erase Suspend command allows the user to inter-

rupt a Sector Erase operation and then perform data

reads or programs to a sector not being erased. This

command is applicable ONLY dur ing the Sector Erase

operation which includes the time-out period for sector

erase. The Erase Suspend command will be ignored if

written dur ing the Chip Erase operation or Embedded

Program Algorithm. Writing the Erase Suspend com-

mand during the Sector Erase time-out results in imme-

diate termination of the time-out period and suspension

of the erase operation.

Any other command written during the Erase Suspend

mode will be ignored except the Erase Resume com-

mand. Writing the Erase Resume command resumes

the erase operation. The addresses are “don’t-cares”

when writing the Erase Suspend or Erase Resume

command.

When the Erase Suspend command is written during

the Sector Erase operation, the device will take a

maximum of 20 µs to suspend the erase operation.

When the device has entered the erase-suspended

mode, the RY/BY output pin and the DQ7 bit will be at

logic “1”, and DQ6 will stop toggling. The user must use

the address of the erasing sector for reading DQ6 and

DQ7 to determine if the erase operation has been

suspended. Further writes of the Erase Suspend

command are ignored.

When the erase operation has been suspended, the

device defaults to the erase-suspend-read mode.

Reading data in this mode is the same as reading from

the standard read mode except that the data must be

read from sectors that have not been erase-sus-

pended. Successively reading from the erase-

suspended sector while the device is in the erase-

suspend-read mode will cause DQ2 to toggle. (See the

section on DQ2).

After entering the erase-suspend-read mode, the user

can program the de vice by writing the appropriate com-

mand sequence for Byte Program. This program mode

is known as the erase-suspend-program mode. Again,

programming in this mode is the same as prog ramming

in the regular Byte Program mode except that the data

must be progr ammed to sectors that are not erase-sus-

pended. Successively reading from the erase-sus-

pended sector while the device is in the erase-

suspend-program mode will cause DQ2 to toggle. The

end of the erase-suspended program operation is de-

tected by the RY/BY output pin, Data P olling of DQ7, or

by the Toggle Bit I (DQ6) which is the same as the reg-

ular Byte Program operation. Note that DQ7 must be

read from the byte prog r am address while DQ6 can be

read from any address.

To resume the operation of Sector Erase, the Resume

command (30H) should be written. Any further writes of

the Resume command at this point will be ignored. An-

other Erase Suspend command can be written after the

chip has resumed erasing.

14 Am29F080

PRELIMINARY

WRITE OPERATION STATUS Table 6. Write Operation Status

Notes:

1. Performing successive read operations from the erase-suspended sector will cause DQ2 to toggle.

2. Performing successive read operations from any address will cause DQ6 to toggle.

3. Reading the byte address being prog r ammed while in the er ase-suspend prog r am mode will indicate logic “1” at the DQ2 bit.

However, successive reads from the erase-suspended sector will cause DQ2 to toggle.

DQ7

Data Polling

The Am29F080 device features Data Polling as a

method to indicate to the host that the embedded algo-

rithms are in progress or completed. During the Em-

bedded Program Algorithm, an attempt to read the

device will produce the complement of the data last

written to DQ7. Upon completion of the Embedded Pro-

gram Algorithm, an attempt to read the device will pro-

duce the true data last written to DQ7. During the

Embedded Erase Algorithm, an attempt to read the de-

vice will produce a “0” at the DQ7 output. Upon comple-

tion of the Embedded Erase Algorithm an attempt to

read the device will produce a “1” at the DQ7 output.

The ﬂowchart for Data Polling (DQ7) is shown in

Figure 3.

Data P olling will also ﬂag the entry into Erase Suspend.

DQ7 will switch “0” to “1” at the star t of the Erase Sus-

pend mode. Please note that the address of an erasing

sector must be applied in order to observe DQ7 in the

Erase Suspend Mode.

During Program in Erase Suspend, Data Polling will

perform the same as in regular program execution

outside of the suspend mode.

For chip erase, the Data Polling is valid after the rising

edge of the sixth WE pulse in the six write pulse

sequence. For sector erase, the Data Polling is valid

after the last rising edge of the sector erase WE pulse.

Data Polling must be performed at sector addresses

within any of the sectors being erased and not a sector

that is within a protected sector group. Otherwise, the

status may not be valid.

Just prior to the completion of Embedded Algorithm op-

erations DQ7 may change asynchronously while the

output enable (OE) is asserted low . This means that the

device is driving status information on DQ7 at one in-

stant of time and then that byte’s valid data at the next

instant of time. Depending on when the system sam-

ples the DQ7 output, it may read the status or valid

data. Even if the device has completed the Embedded

Algorithm operations and DQ7 has a valid data, the

data outputs on DQ0–DQ6 may be still invalid. The

valid data on DQ0–DQ7 can be read on the successiv e

read attempts.

The Data Polling feature is only active during the Em-

bedded Programming Algorithm, Embedded Erase Al-

gorithm, Erase Suspend, erase-suspend-program

mode, or sector erase time-out (see Table 6).

See Figure 11 f or the Data Polling timing speciﬁcations

and diagrams.

Status DQ7 DQ6 DQ5 DQ3 DQ2

In Progress

Byte Program in Embedded Program Algorithm DQ7 Toggle 0 0 1

Embedded Erase Algorithm 0 Toggle 0 1 Toggle

Erase Suspended Mode

Erase Suspend Read

(Erase Suspended Sector) 1100

Toggle

(Note 1)

Erase Suspend Read

(Non-Erase Suspended Sector) Data Data Data Data Data

Erase Suspend Program

(Non-Erase Suspended Sector) DQ7 Toggle

(Note 2) 00 1

(Note 3)

Exceeded Time

Limits

Byte Program in Embedded Program Algorithm DQ7 Toggle 1 0 1

Program/Erase in Embedded Erase Algorithm 0 Toggle 1 1 N/A

Erase Suspended Mode Erase Suspend Program

(Non-Erase Suspended Sector) DQ7 Toggle 1 1 N/A

Am29F080 15

PRELIMINARY

5.0 V-only Flash

DQ6

Toggle Bit I

The Am29F080 also features the “Toggle Bit I” as a

method to indicate to the host system that the embed-

ded algorithms are in progress or completed.

During an Embedded Program or Erase Algorithm cy-

cle, successive attempts to read (OE toggling) data

from the device

at any address

will result in DQ6 tog-

gling between one and zero. Once the Embedded Pro-

gram or Erase Algorithm cycle is completed, DQ6 will

stop toggling and valid data will be read on

the next

successive attempt. During programming, the Toggle

Bit I is valid after the rising edge of the f ourth WE pulse

in the four write pulse sequence. For chip erase, the

Toggle Bit I is valid after the rising edge of the sixth WE

pulse in the six write pulse sequence. For Sector

Erase, the Toggle Bit I is valid after the last rising edge

of the sector erase WE pulse. The Toggle Bit I is active

during the sector erase time-out.

Either CE or OE toggling will cause DQ6 to toggle. In

addition, an Erase Suspend/Resume command will

cause DQ6 to toggle. See Figure 12 for the Toggle Bit I

timing speciﬁcations and diagrams.

DQ5

Exceeded Timing Limits

DQ5 will indicate if the program or erase time has ex-

ceeded the speciﬁed limits (internal pulse count).

Under these conditions DQ5 will produce a “1”. This is

a failure condition which indicates that the program or

erase cycle was not successfully completed. Data Poll-

ing is the only operating function of the device under

this condition. The CE circuit will partially power down

the device under these conditions (to approximately 2

mA). The OE and WE pins will control the output

disable functions as described in Table 1.

The DQ5 f ailure condition will also appear if a user tries

to program a 1 to a location that is previously pro-

grammed to 0. In this case the device locks out and

never completes the Embedded Program Algorithm.

Hence, the system ne ver reads a v alid data on DQ7 bit

and DQ6 ne ver stops toggling. Once the de vice has e x-

ceeded timing limits, the DQ5 bit will indicate a “1”.

Please note that this is not a device failure condition

since the device was incorrectly used. If this occurs,

reset the device.

DQ3

Sector Erase Timer

After the completion of the initial sector erase com-

mand sequence the sector erase time-out will begin.

DQ3 will remain low until the time-out is complete . Data

Polling and Toggle Bit I are valid after the initial sector

erase command sequence.

If Data Polling or the Toggle Bit I indicates the device

has been written with a valid erase command, DQ3

ma y be used to determine if the sector erase timer win-

dow is still open. If DQ3 is high (“1”) the internally con-

trolled erase cycle has begun; attempts to write

subsequent commands (other than Erase Suspend) to

the device will be ignored until the erase operation is

completed as indicated by Data Polling or Toggle Bit I.

If DQ3 is low (“0”), the de vice will accept additional sec-

tor erase commands. To insure the command has been

accepted, the system software should chec k the status

of DQ3 prior to and following each subsequent sector

erase command. If DQ3 were high on the second sta-

tus check, the command may not ha v e been accepted.

Refer to Table 6: Write Operation Status.

DQ2

Toggle Bit II

This toggle bit, along with DQ6, can be used to

determine whether the device is in the Embedded

Erase Algorithm or in Erase Suspend.

Successive reads from the erasing sector will cause

DQ2 to toggle during the Embedded Erase Algorithm.

If the device is in the erase-suspended-read mode,

successive reads from the erase-suspend sector will

cause DQ2 to toggle. When the device is in the erase-

suspended-program mode, successive reads from the

byte address of the non-erase suspended sector will

indicate a logic “1” at the DQ2 bit.

DQ6 is different from DQ2 in that DQ6 toggles only

when the standard Program or Erase, or Erase Sus-

pend Program oper ation is in progress. The behavior of

these two status bits, along with that of DQ7, is

summarized as follows:

Notes:

1. These status ﬂags apply when outputs are read from a

sector that has been erase-suspended.

2. These status ﬂags apply when outputs are read from the

byte address of the non-erase suspended sector.

Mode DQ7 DQ6 DQ2

Program DQ7 Toggles 1

Erase 0 Toggles Toggles

Erase Suspend Read

(Note 1) 1 1 Toggles

(Erase-Suspended

Sector)

Erase Suspend Program DQ7

(Note2) Toggles Toggles

16 Am29F080

PRELIMINARY

For example, DQ2 and DQ6 can be used together to

determine the erase-suspend-read mode (DQ2 toggles

while DQ6 does not). See also Table 6 and Figure 17.

Furthermore, DQ2 can also be used to determine

which sector is being erased. When the device is in the

erase mode, DQ2 toggles if this bit is read from the

erasing sector.

RY/BY

Ready/Busy

The Am29F080 provides a RY/BY open-drain output

pin as a wa y to indicate to the host system that the Em-

bedded Algorithms are either in progress or has been

completed. If the output is low, the device is busy with

either a program or erase operation. If the output is

high, the device is ready to accept any read/write or

erase operation. When the R Y/BY pin is lo w, the device

will not accept any additional program or erase com-

mands with the exception of the Erase Suspend com-

mand. If the Am29F080 is placed in an Erase Suspend

mode, the RY/BY output will be high.

During programming, the RY/BY pin is driven low after

the rising edge of the fourth WE pulse . During an erase

operation, the RY/BY pin is driven low after the rising

edge of the sixth WE pulse . The RY/BY pin will indicate

a busy condition during the RESET pulse. Ref er to Fig-

ure 13 for a detailed timing diagram. The RY/BY pin is

pulled high in standby mode.

Since this is an open-drain output, several RY/BY pins

can be tied together in parallel with a pull-up resistor

to VCC.

RESET

Hardware Reset

The Am29F080 device may be reset by driving the

RESET pin to VIL. The RESET pin must be kept low

(VIL) for at least 500 ns. Any operation in progress will

be terminated and the internal state machine will be

reset to the read mode 20 µs after the RESET pin is

driven low. If a hardw are reset occurs during a program

or erase operation, the data at that particular location

will be indeterminate.

When the RESET pin is low and the internal reset is

complete, the de vice goes to standby mode and cannot

be accessed. Also , note that all the data output pins are

tri-stated for the duration of the RESET pulse. Once the

RESET pin is taken high, the device requires 500 ns of

wake up time until outputs are valid for read access.

The RESET pin may be tied to the system reset input.

Therefore, if a system reset occurs during the Embed-

ded Program or Er ase Algorithm, the device will be au-

tomatically reset to read mode and this will enable the

system’s microprocessor to read the boot-up ﬁrmware

from the Flash memory.

Data Protection

The Am29F080 is designed to offer protection against

accidental erasure or programming caused by spurious

system le vel signals that ma y e xist during power transi-

tions. During power up the device automatically resets

the internal state machine in the Read mode. Also , with

its control register architecture, alteration of the mem-

ory contents only occurs after successful completion of

speciﬁc multi-bus cycle command sequences.

The device also incorporates several features to

prevent inadvertent write cycles resulting from VCC

power-up and po wer-do wn transitions or system noise .

Low VCC Write Inhibit

To avoid initiation of a write cycle during VCC po w er-up

and power-do wn, the Am29F080 loc ks out write cycles

for VCC < VLK O (see DC Char acteristics section for v olt-

ages). When VCC < VLKO, the command register is dis-

abled, all internal program/erase circuits are disabled,

and the device resets to the read mode. The

Am29F080 ignores all writes until VCC > VLKO. The user

must ensure that the control pins are in the correct logic

state when VCC > VLKO to prevent unintentional writes.

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE, CE, or

WE will not initiate a write cycle.

Logical Inhibit

Writing is inhibited by holding any one of OE = VIL,

CE = VIH, or WE = VIH. To initiate a write cycle CE and

WE must be a logical zero while OE is a logical one.

Power-Up Write Inhibit

Power-up of the device with WE = CE = VIL and

OE = VIH will not accept commands on the rising edge

of WE. The internal state machine is automatically

reset to the read mode on power-up.

Am29F080 17

PRELIMINARY

5.0 V-only Flash

EMBEDDED ALGORITHMS

Start

Programming Completed

Last Address

Write Program Command Sequence

(see below)

Data Poll Device

Increment Address

Yes

5555H/AAH

2AAAH/55H

5555H/A0H

Program Command Sequence (Address/Command):

19643A-5

Figure 1. Embedded Programming Algorithm

Program Address/Program Data

18 Am29F080

PRELIMINARY

EMBEDDED ALGORITHMS

Note:

To insure the command has been accepted, the system software should chec k the status of DQ3 prior to and follo wing each sub-

sequent sector erase command. If DQ3 were high on the second status check, the command may not have been accepted.

Figure 2. Embedded Erase Algorithm

Start

Erasure Completed

Write Erase Command Sequence

(see below)

Data Polling or Toggle Bit I

Successfully Completed

5555H/AAH

2AAAH/55H

5555H/80H

Chip Erase Command Sequence

(Address/Command):

5555H/AAH

2AAAH/55H

5555H/10H

5555H/AAH

2AAAH/55H

5555H/80H

Individual Sector/Multiple Sector

Erase Command Sequence

(Address/Command):

5555H/AAH

Sector Address/30H

2AAAH/55H

Additional sector

erase commands

are optional

19643A-6

Am29F080 19

PRELIMINARY

5.0 V-only Flash

Note:

DQ7 is rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5.

Figure 3. Data Polling Algorithm

Start

Fail

DQ7 = Data

Pass

Yes

DQ5 = 1

Yes

Read Byte

(DQ0–DQ7)

Addr = VA

Read Byte

(DQ0–DQ7)

Addr = VA

VA = Byte address for programming

= any of the sector addresses within the

sector being erased during sector erase

operation

= valid address equals any non-protected

sector group address during chip erase

19643A-7

DQ7 = Data

20 Am29F080

PRELIMINARY

Note:

DQ6 is rechecked even if DQ5 = “1” because DQ6 may stop toggling at the same time as DQ5 changing to “1”.

Figure 4. Toggle Bit I Algorithm

Start

Fail

DQ6 =Toggle

Pass

Yes

DQ6 = Toggle

DQ5 = 1

Yes

Read Byte

(DQ0-DQ7)

Addr = Don’t Care

Read Byte

(DQ0-DQ7)

Addr = Don’t Care

19643A-8

Am29F080 21

PRELIMINARY

5.0 V-only Flash

Figure 5. Maximum Negative Overshoot Waveform

Figure 6. Maximum Positive Overshoot Waveform

20 ns

+0.8 V

–0.5 V

20 ns

–2.0 V

19643A-9

20 ns

VCC + 0.5 V

2.0 V

20 ns 20 ns

VCC + 2.0 V

19643A-10

22 Am29F080

PRELIMINARY

ABSOLUTE MAXIMUM RATINGS

Storage Temperature

Plastic Packages. . . . . . . . . . . . . . . –65°C to +125°C

Ambient Temperature

with Power Applied . . . . . . . . . . . . . –55°C to +125°C

Voltage with Respect to Ground

All pins except A9 (Note 1) . . . . . . . . –2.0 V to +7.0 V

VCC (Note 1) . . . . . . . . . . . . . . . . . . . –2.0 V to +7.0 V

A9, OE, RESET (Note 2). . . . . . . . . –2.0 V to +13.5 V

Output Short Circuit Current (Note 3) . . . . . . .200 mA

Notes:

1. Minimum DC v oltage on input or I/O pins is

–

0.5 V. During

voltage transitions, inputs may overshoot V

–

2.0 V for

periods of up to 20 ns. Maximum DC v oltage on input and

I/O pins is V

+ 0.5 V. During voltage transitions, input

and I/O pins ma y overshoot to V

+ 2.0 V f or periods up

to 20ns.

2. Minimum DC input voltage on A9, OE, RESET pins is

–

0.5V. During voltage transitions , A9, OE, RESET pins

ma y ov ershoot V

–

2.0 V for periods of up to 20 ns.

Maximum DC input v oltage on A9 is +12.5 V which may

overshoot to 14.0 V for periods up to 20 ns.

3. No more than one output shorted to ground at a time. Du-

ration of the short circuit should not be greater than one

second.

Stresses above those listed under “Absolute Maximum Rat-

ings” may cause per manent damage to the device. This is a

stress rating only; functional operation of the device at these

or any other conditions above those indicated in the opera-

tional sections of this speciﬁcation is not implied. Exposure of

the device to absolute maximum rating conditions for

extended periods may affect device reliability.

OPERATING RANGES

Commercial (C) Devices

Ambient Temperature (TA) . . . . . . . . . . . 0°C to +70°C

Industrial (I) Devices

Ambient Temperature (TA) . . . . . . . . –40+C to +85+C

Extended (E) Devices

Ambient Temperature (TA) . . . . . . . . –55°C to +125°C

VCC Supply V oltages

VCC for Am29F080-85 . . . . . . . . . .+4.75 V to +5.25 V

VCC for Am29F080-90, 120, 150 . .+4.50 V to +5.50 V

Operating ranges deﬁne those limits between which the

functionality of the device is guaranteed.

Am29F080 23

PRELIMINARY

5.0 V-only Flash

DC CHARACTERISTICS

TTL/NMOS Compatible

Notes:

1. The I

current listed includes both the DC operating current and the frequency dependent component (at 6 MHz).

The frequency component typically is less than 1 mA/MHz, with OE at V

IH.

2. I

active while Embedded Program or Erase Algorithm is in progress.

3. Not 100% tested.

Parameter

Symbol Parameter Description Test Conditions Min Max Unit

ILI Input Load Current VIN = VSS to VCC, VCC = V CC Max ±1.0 µA

ILIT A9 Input Load Current VCC = VCC Max, A9 = 12.0 Volt 50 µA

ILO Output Leakage Current VOUT = VSS to VCC, VCC = VCC Max ±1.0 µA

ICC1 VCC Active Read Current (Note 1) CE = VIL, OE = VIH 30 mA

ICC2 VCC Active Program/Erase Current

(Notes 2, 3) CE = VIL, OE = VIH 60 mA

ICC3 VCC Standby Current VCC = VCC Max, CE = V IH, RESET = VIH 1.0 mA

ICC4 VCC Standby Current (Reset) VCC = VCC Max, RESET = VIL 1.0 mA

VIL Input Low Voltage –0.5 0.8 V

VIH Input High Voltage 2.0 VCC + 0.5 V

VID Voltage for Autoselect and

Temporary Sector Unprotect VCC = 5.0 volt 11.5 12.5 V

VOL Output Low Voltage IOL = 12 mA, VCC = VCC Min 0.45 V

VOH Output High Voltage IOH = –2.5 mA, VCC = VCC Min 2.4 V

VLKO Low V CC Lock-Out Voltage 3.2 4.2 V

24 Am29F080

PRELIMINARY

DC CHARACTERISTICS (continued)

CMOS Compatible

Note:

1. The I

current listed includes both the DC operating current and the frequency dependent component (at 6 MHz).

The frequency component typically is less than 1 mA/MHz, with OE at V

2. ICC active while Embedded Program or Erase Algorithm is in progress.

3. Not 100% tested.

Parameter

Symbol Parameter Description Test Description Min Typ Max Unit

ILI Input Load Current VIN = VSS to VCC, VCC = VCC Max ±1.0 µA

ILIT A9 Input Load Current VCC = VCC Max, A9 = 12.0 Volt 50 µA

ILO Output Leakage Current VOUT = VSS to VCC, VCC = V CC Max ±1.0 µA

ICC1 VCC Active Read Current 1 CE = VIL, OE = VIH 25 40 mA

ICC2 VCC Active Program/Erase Current

(Notes 2, 3) CE = VIL, OE = VIH 30 40 mA

ICC3 VCC Standby Current VCC = VCC Max, CE = VCC ± 0.3 V,

RESET = VCC ± 0.3 V 15µA

CC4 VCC Standby Current (Reset) VCC = VCC Max,

RESET = VSS ± 0.3 V 15µA

IL Input Low Voltage –0.5 0.8 V

VIH Input High V oltage 0.7x V CC VCC +0.3 V

VID Voltage for Autoselect and

Temporary Sector Unprotect VCC = 5.0 Volt 11.5 12.5 V

VOL Output Low Voltage IOL = 12 mA, VCC = VCC Min 0.45 V

VOH1 Output High Voltage IOH = –2.5 mA, VCC = VCC Min 0.85x

VCC V

VOH2 IOH = –100 µA, VCC = VCC Min VCC–0.4 V

VLKO Low V CC Lock-out Voltage 3.2 4.2 V

Am29F080 25

PRELIMINARY

5.0 V-only Flash

AC CHARACTERISTICS

Read-only Operations Characteristic

Notes:

1. Test Conditions:

Output Load: 1 TTL gate and 30 pF

Input rise and fall times: 5 ns

Input pulse levels: 0.0 V to 3.0 V

Timing measurement reference level Input: 1.5 V

Output: 1.5 V

2. Test Conditions:

Output Load: 1 TTL gate and 100 pF

Input rise and fall times: 20 ns

Input pulse levels: 0.45 V to 2.4 V

Timing measurement reference level Input: 0.8 and 2.0 V

Output: 0.8 and 2.0 V

3. Output driver disable time.

4. Not 100% tested.

Parameter

Symbols

Description Test Setup -85

(Note 1) -90

(Note 2) -120

(Note 2) -150

(Note 2) UnitJEDEC Standard

tAVAV tRC Read Cycle Time (Note 3) Min 85 90 120 150 ns

tAVQV tACC Address to Output Delay CE = VIL

OE = VIL Max 85 90 120 150 ns

tELQV tCE Chip Enable to Output Delay OE = VIL Max 85 90 120 150 ns

tGLQV tOE Output Enable to Output Delay Max 40 40 50 55 ns

tEHQZ tDF Chip Enable to Output High Z

(Notes 3 and 4) Max 20 20 30 35 ns

tGHQZ tDF Output Enable to Output High Z

(Notes 3 and 4) Max 20 20 30 35 ns

tAXQX tOH

Output Hold Time from

Addresses, CE or OE,

Whichever Occurs First Min0000ns

Ready RESET Pin Low to ReadMode

(Note 4) Max 20 20 20 20 µs

26 Am29F080

PRELIMINARY

Note:

For all others: C

= 100 pF including jig capacitance

For

85: C

= 30 pF

Figure 7. Test Conditions

2.7 kΩ

Diodes = IN3064

or Equivalent

CL6.2 kΩ

5.0 Volt

IN3064

or Equivalent

Device

Under

Test

19643A-11

Am29F080 27

PRELIMINARY

5.0 V-only Flash

AC CHARACTERISTICS

Write/Erase/Program Operations

Notes:

1. This does not include the preprogramming time.

2. Not 100% tested.

3. These timings are for Temporary Sector Group Unprotect operation.

Parameter

Symbols

Description -85 -90 -120 -150 UnitJEDEC Standard

tAVAV tWC Write Cycle Time (Note 2) Min 85 90 120 150 ns

tAVWL tAS Address Setup Time Min 0000ns

WLAX tAH Address Hold Time Min 40 45 50 50 ns

tDVWH tDS Data Setup Time Min 40 45 50 50 ns

tWHDX tDH Data Hold Time Min 0000ns

OEH Output Enable

Hold Time

Read (Note 2) Min 0000ns

Toggle Bit I and Data Polling

(Note 2) Min 10 10 10 10 ns

tGHWL tGHWL Read Recover Time Before Write

(OE high to WE low) Min0000ns

ELWL tCS CE setup Time Min 0000ns

WHEH tCH CE Hold Time Min 0000ns

WLWH tWP Write Pulse Width Min 40 45 50 50 ns

tWHWL tWPH Write Pulse Width High Min 20 20 20 20 ns

tWHWH1 tWHWH1 Byte Programming Operation Typ 7777µs

WHWH2 tWHWH2 Sector Erase Operation (Note 1) Typ 1111sec

Max8888sec

VCS VCC Setup Time (Note 2) Min 50 50 50 50 µs

tVIDR Rise Time to VID (Notes 2, 3) Min 500 500 500 500 ns

tOESP OE Setup Time to WE Active (Notes 2, 3) Min 4444µs

RP RESET Pulse Width Min 500 500 500 500 ns

tBUSY Program/Erase Valid to RY/BY Delay Min 40 40 50 60 ns

28 Am29F080

PRELIMINARY

KEY TO SWITCHING WA VEFORMS

Must be

Steady

May

Change

from H to L

May

Change

from L to H

Does Not

Apply

Don’t Care,

Any Change

Permitted

Will be

Steady

Will be

Changing

from H to L

Will be

Changing

from L to H

Changing,

State

Unknown

Center

Line is High-

Impedance

“Off” State

WAVEFORM INPUTS OUTPUTS

KS000010

Am29F080 29

PRELIMINARY

5.0 V-only Flash

SWITCHING W A VEFORMS

Addresses

Outputs

Addresses Stable

High Z High Z

(tDF)

(tCE)(tOH)

Output V alid

tACC

tOE

tRC

tOEH

19643A-12

Figure 8. AC Waveforms for Read Operations Timing Diagram

30 Am29F080

PRELIMINARY

SWITCHING W A VEFORMS

Notes:

1. PA is address of the memory location to be programmed.

2. PD is data to be programmed at byte address.

3. DQ7 is the output of the complement of the data written to the device.

4. D

OUT

is the output of the data written to the device.

5. Figure indicates last two bus cycles of four bus cycle sequence.

Figure 9. Program Operation Timings

Note:

SA is the sector address for Sector Erase. Addresses = don’t care for Chip Erase.

Figure 10. AC Waveforms Chip/Sector Erase Operations

DOUT

tAH

Data Polling

tDF

tOH

tOE

tDS

tCS tWPH

tDH

tWP

tGHWL

Addresses

Data

5.0 V

DQ7

5555H PA

A0H

19643A-13

tWC tRC

tAS

tWHWH1

tCE

3rd Bus Cycle

tWP

tCS tDH

5555H 2AAAH SA

Data

VCC

AAH 55H

Addresses 2AAAH

tDS

5555H

tWPH

tGHWL

tAH

AAH 55H80H 10H/30H

19643A-14

tAS

5555H

tVCS

Am29F080 31

PRELIMINARY

5.0 V-only Flash

SWITCHING W A VEFORMS

*DQ7 = Valid Data (The device has completed the Embedded operation.)

Figure 11. AC Waveforms for Data Polling During Embedded Algorithm Operations

*DQ6 stops toggling (The device has completed the Embedded operation.)

Figure 12. AC Waveforms for Toggle Bit I During Embedded Algorithm Operations

DQ0–DQ7

V alid Data

tOE

DQ7 =

Valid Data

High Z

DQ7

DQ0–DQ6 DQ0–DQ6 = Invalid

19643A-15

tOEH

tCE

tCH

tDF

tOH

tWHWH 1 or 2

DQ7

tOEH

tOE

DQ6 =

Stop Toggling DQ0–DQ7

Valid

DQ6 = Toggle

Data

(DQ0–DQ7)

19643A-16

32 Am29F080

PRELIMINARY

Figure 13. RY/BY Timing Diagram During Program/Erase Operations

Figure 14. RESET Timing Diagram

RY/BY tBUSY

Entire programming

or erase operations

The rising edge of the last WE signal

19643A-17

RESET

19643A-18

tReady

tRP

Am29F080 33

PRELIMINARY

5.0 V-only Flash

Notes:

1. All protected sector groups unprotected.

2. All previously protected sector groups are protected once again.

Figure 15. Temporary Sector Group Unprotect Algorithm

Figure 16. Temporary Sector Group Unprotect Timing Diagram

Start

Perform Erase or

Program Operations

RESET = VIH

Temporary Sector Group

Unprotect Completed

(Note 2)

RESET = VID

(Note 1)

19643A-21

RY/BY Program or Erase Command Sequence

19643A-22

RESET

0V or 5 V

0 or 5V tVIDR

12V

34 Am29F080

PRELIMINARY

Note:

DQ2 is read from the erase-suspended sector.

Figure 17. DQ2 vs. DQ6

DQ2

DQ6

Enter

Embedded

Erasing Enter Erase

Suspend Program

Erase

Suspend

Toggle

DQ2 and DQ6

with OE

19643A-23

Erase

Resume

Erase Erase Suspend

Read Erase Suspend

Read

Erase

Suspend

Program

Erase Erase

Complete

Am29F080 35

PRELIMINARY

5.0 V-only Flash

AC CHARACTERISTICS

Write/Erase/Program Operations

Alternate CE Controlled Writes

Notes:

1. This does not include the preprogramming time.

2. Not 100% tested.

Parameter

Symbols

Description -85 -90 -120 -150 UnitJEDEC Standard

tAVAV tWC Write Cycle Time (Note 2) Min 85 90 120 150 ns

tAVEL tAS Address setup Time Min 0000ns

ELAX tAH Address Hold Time Min 40 45 50 50 ns

tDVEH tDS Data Setup Time Min 40 45 50 50 ns

tEHDX tDH Data Hold Time Min 0000ns

OES Output Enable Setup Time (Note 2) Min 0000ns

OEH

Output Enable Read (Note 2) Min 0000ns

Hold Time Toggle Bit I and Data Polling

(Note 2) Min 10 10 10 10 ns

tGHEL tGHEL Read Recover Time Before Write Min 0000ns

WLEL tWS CE setup Time Min 0000ns

EHWH tWH CE Hold Time Min 0000ns

ELEH tCP Write Pulse Width Min 40 45 50 50 ns

tEHEL tCPH Write Pulse Width High Min 20 20 20 20 ns

tWHWH1 tWHWH1 Byte Programming Operation Typ 7777µs

WHWH2 tWHWH2 Sector Erase Operation (Note 1) Typ1111sec

Max8888sec

36 Am29F080

PRELIMINARY

Notes:

1. PA is address of the memory location to be programmed.

2. PD is data to be programmed at byte address.

3. DQ7 is the output of the complement of the data written to the device.

4. D

OUT

is the output of the data written to the device.

5. Figure indicates last two bus cycles of four bus cycle sequence.

Figure 18. Alternate CE Controlled Program Operation Timings

DOUT

tAH

Data Polling

tDS

tWS tCPH

tDH

tCP

tGHEL

Addresses

Data

5.0 V

DQ7

5555H PA

A0H

19643A-24

tWC tAS

tWHWH1

Am29F080 37

PRELIMINARY

5.0 V-only Flash

ERASE AND PROGRAMMING PERFORMANCE

Notes:

1. 25

C, 5 V V

, 100,000 cycles.

2. Although Embedded Algorithms allow for a longer chip program and erase time , the actual time will be considerably less since

bytes program or erase signiﬁcantly faster than the worst case byte.

3. Under worst case condition of 90

C , 4.5 V V

, 100,000 cycles.

4. System-level overhead is deﬁned as the time required to execute the four bus cycle command necessary to program each

byte. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00H before erasure.

5. The Embedded Algorithms allow f or 2.5 ms byte program time . DQ5 = “1” only after a byte tak es the theoretical maximum time

to program. A minimal number of bytes ma y require signiﬁcantly more progr amming pulses than the typical byte. The majority

of the bytes will program within one or two pulses. This is demonstrated by the Typical and Maximum Programming Times

listed above.

LATCHUP CHARACTERISTICS

Includes all pins except V

. Test conditions: V

= 5.0 Volt, one pin at a time.

TSOP PIN CAPACITANCE

Notes:

1. Sampled, not 100% tested.

2. Test conditions T

= 25

C, f = 1.0 MHz

Parameter

Limits

Comments

Typ

(Note 1) Max Unit

Sector Erase Time 1.0 8 sec Excludes 00H programming prior to erasure

Chip Erase Time 16 128 sec Excludes 00H programming prior to erasure

Byte Programming Time 7 300

(Note 3) µs Excludes system-level overhead (Note 4)

Chip Programming Time 7.2 21.6

(Notes 3,5) sec Excludes system-level overhead (Note 4)

Parameter Description Min Max

Input Voltage with respect to VSS on all I/O pins –1.0 V VCC + 1.0 V

VCC Current –100 mA +100 mA

Parameter

Symbol Parameter Description Test setup Typ Max Unit

CIN Input Capacitance VIN = 0 6 7.5 pF

COUT Output Capacitance VOUT = 0 8.5 12 pF

CIN2 Control Pin Capacitance VIN = 0 7.5 9 pF

38 Am29F080

PRELIMINARY

PSOP PIN CAPACITANCE

Notes:

1. Sampled, not 100% tested.

2. Test conditions T

= 25

C, f = 1.0 MHz

Parameter

Symbol Parameter Description Test setup Typ Max Unit

CIN Input Capacitance VIN = 0 6 7.5 pF

COUT Output Capacitance VOUT = 0 8.5 12 pF

CIN2 Control Pin Capacitance VIN = 0 8 10 pF

Am29F080 39

PRELIMINARY

5.0 V-only Flash

REVISION SUMMARY

Ordering Information, Standard Products:

Added the industrial temperature range to the -85 and

-90 speed options.

DC Characteristics, CMOS Compatible:

Improved speciﬁcations on ICC1, ICC2, and ICC3.

AC Characteristics:

Write/Erase/Program Operations:

Updated speciﬁca-

tions for byte programming and sector erase.

Figure 16, Temporary Sector Group Unprotect:

Corrected ﬁgure.

Erase and Programming Performance:

Updated all parameters.

Physical Dimensions:

TS040 40 Pin Thin Small Outline Package, TSR040 40-

Pin Reversed Thin Small Outline Package:

For standal-

one data sheet, modiﬁed drawing to indicate there are

f ewer pins shown on dr awing than on actual product. F or

data book, the package dr awings are new additions.