DS90LV018A
3V LVDS Single CMOS Differential Line Receiver
General Description
The DS90LV018A is a single CMOS differential line receiver
designed for applications requiring ultra low power dissipa-
tion, low noise and high data rates. The device is designed to
support data rates in excess of 400 Mbps (200 MHz) utilizing
Low Voltage Differential Signaling (LVDS) technology.
The DS90LV018A accepts low voltage (350 mV typical) dif-
ferential input signals and translates them to 3V CMOS out-
put levels. The receiver also supports open, shorted and ter-
minated (100Ω) input fail-safe. The receiver output will be
HIGH for all fail-safe conditions. The DS90LV018A has a
flow-through design for easy PCB layout.
The DS90LV018Aand companion LVDS line driver provide a
new alternative to high power PECL/ECL devices for high
speed point-to-point interface applications.
Features
n>400 Mbps (200 MHz) switching rates
n50 ps differential skew (typical)
n2.5 ns maximum propagation delay
n3.3V power supply design
nFlow-through pinout
nPower down high impedance on LVDS inputs
nLow Power design (18mW @3.3V static)
nInteroperable with existing 5V LVDS networks
nAccepts small swing (350 mV typical) differential signal
levels
nSupports open, short and terminated input fail-safe
nConforms to ANSI/TIA/EIA-644 Standard
nIndustrial temperature operating range
(−40˚C to +85˚C)
nAvailable in SOIC package
Connection Diagram Functional Diagram
Truth Table
INPUTS OUTPUT
[R
IN
+]−[R
IN
−] R
OUT
V
ID
≥0.1V H
V
ID
≤−0.1V L
Full Fail-safe
OPEN/SHORT H
or Terminated
Dual-in-Line
DS100078-1
Order Number DS90LV018ATM
See NS Package Number M08A
DS100078-2
June 1998
DS90LV018A 3V LVDS Single CMOS Differential Line Receiver
© 1998 National Semiconductor Corporation DS100078 www.national.com
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
CC
) −0.3V to +4V
Input Voltage (R
IN
+, R
IN
−) −0.3V to +3.9V
Output Voltage (R
OUT
) −0.3V to (V
CC
+ 0.3V)
Maximum Package Power Dissipation +25˚C
M Package 1025 mW
Derate M Package 8.2 mW/˚C above +25˚C
Storage Temperature Range −65˚C to +150˚C
Lead Temperature Range Soldering
(4 sec.) +260˚C
Maximum Junction Temperature +150˚C
ESD Rating (Note 4)
(HBM 1.5 kΩ, 100 pF) ≥7kV
(EIAJ 0Ω, 200 pF) ≥500 V
Recommended Operating
Conditions
Min Typ Max Units
Supply Voltage (V
CC
) +3.0 +3.3 +3.6 V
Receiver Input Voltage GND 3.0 V
Operating Free Air
Temperature (T
A
) −40 25 +85 ˚C
Electrical Characteristics
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified. (Notes 2, 3)
Symbol Parameter Conditions Pin Min Typ Max Units
V
TH
Differential Input High Threshold V
CM
= +1.2V, 0V, 3V (Note 11) R
IN
+, +100 mV
V
TL
Differential Input Low Threshold R
IN
− −100 mV
I
IN
Input Current V
IN
= +2.8V V
CC
= 3.6V or 0V −10 ±1 +10 µA
V
IN
= 0V −10 ±1 +10 µA
V
IN
= +3.6V V
CC
= 0V -20 +20 µA
V
OH
Output High Voltage I
OH
= −0.4 mA, V
ID
= +200 mV R
OUT
2.7 3.1 V
I
OH
= −0.4 mA, Inputs terminated 2.7 3.1 V
I
OH
= −0.4 mA, Inputs shorted 2.7 3.1 V
V
OL
Output Low Voltage I
OL
= 2 mA, V
ID
= −200 mV 0.3 0.5 V
I
OS
Output Short Circuit Current V
OUT
= 0V (Note 5) −15 −50 −100 mA
V
CL
Input Clamp Voltage I
CL
= −18 mA −1.5 −0.8 V
I
CC
No Load Supply Current Inputs Open V
CC
5.4 9 mA
Switching Characteristics
V
CC
= +3.3V ±10%,T
A
= −40˚C to +85˚C (Notes 6, 7)
Symbol Parameter Conditions Min Typ Max Units
t
PHLD
Differential Propagation Delay High to Low C
L
= 15 pF 1.0 1.6 2.5 ns
t
PLHD
Differential Propagation Delay Low to High V
ID
= 200 mV 1.0 1.7 2.5 ns
t
SKD1
Differential Pulse Skew |t
PHLD
−t
PLHD
| (Note 8) (
Figure 1
and
Figure 2
) 0 50 400 ps
t
SKD3
Differential Part to Part Skew (Note 9) 0 1.0 ns
t
SKD4
Differential Part to Part Skew (Note 10) 0 1.5 ns
t
TLH
Rise Time 325 800 ps
t
THL
Fall Time 225 800 ps
f
MAX
Maximum Operating Frequency (Note 12) 200 250 MHz
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.
Note 2: Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground unless otherwise speci-
fied (such as VID).
Note 3: All typicals are given for: VCC = +3.3V and TA= +25˚C.
Note 4: ESD Rating: HBM (1.5 kΩ, 100 pF) ≥7kV
EIAJ (0Ω, 200 pF) ≥500V
Note 5: Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only. Only one output should be shorted at a time, do not ex-
ceed maximum junction temperature specification.
Note 6: CLincludes probe and jig capacitance.
Note 7: Generator waveform for all tests unless otherwise specified:f=1MHz, ZO=50Ω,t
rand tf(0%to 100%)≤3 ns for RIN.
Note 8: tSKD1 is the magnitude difference in differential propagation delay time between the positive-going-edge and the negative-going-edge of the same channel.
Note 9: tSKD3, part to part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices at the same VCC
and within 5˚C of each other within the operating temperature range.
www.national.com 2
Switching Characteristics (Continued)
Note 10: tSKD4, part to part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices over the recom-
mended operating temperature and voltage ranges, and across process distribution. tSKD4 is defined as |Max − Min| differential propagation delay.
Note 11: VCC is always higher than RIN+ and RIN− voltage. RIN+ and RIN− are allowed to have voltage range −0.05V to +3.05V. VID is not allowed to be greater than
100 mV when VCM =0Vor3V.
Note 12: fMAX generator input conditions: tr=tf<1ns(0
%to 100%), 50%duty cycle, differential (1.05V to 1.35V peak to peak). Output criteria: 60%/40%duty cycle,
VOL (max 0.4V), VOH (min 2.7V), load =15 pF (stray plus probes).
Parameter Measurement Information
Typical Application
Applications Information
General application guidelines and hints for LVDS drivers
and receivers may be found in the following application
notes: LVDS Owner’s Manual (lit #550062-001), AN808,
AN1035, AN977, AN971, AN916, AN805, AN903.
LVDS drivers and receivers are intended to be primarily used
in an uncomplicated point-to-point configuration as is shown
in
Figure 3
. This configuration provides a clean signaling en-
vironment for the fast edge rates of the drivers. The receiver
is connected to the driver through a balanced media which
may be a standard twisted pair cable, a parallel pair cable, or
simply PCB traces. Typically the characteristic impedance of
the media is in the range of 100Ω. A termination resistor of
100Ωshould be selected to match the media, and is located
as close to the receiver input pins as possible. The termina-
tion resistor converts the driver output (current mode) into a
voltage that is detected by the receiver. Other configurations
are possible such as a multi-receiver configuration, but the
effects of a mid-stream connector(s), cable stub(s), and
other impedance discontinuities as well as ground shifting,
noise margin limits, and total termination loading must be
taken into account.
The DS90LV018A differential line receiver is capable of de-
tecting signals as low as 100 mV, over a ±1V common-mode
range centered around +1.2V.This is related to the driver off-
set voltage which is typically +1.2V. The driven signal is cen-
tered around this voltage and may shift ±1V around this cen-
ter point. The ±1V shifting may be the result of a ground
potential difference between the driver’s ground reference
and the receiver’s ground reference, the common-mode ef-
fects of coupled noise, or a combination of the two. The AC
parameters of both receiver input pins are optimized for a
recommended operating input voltage range of 0V to +2.4V
DS100078-3
FIGURE 1. Receiver Propagation Delay and Transition Time Test Circuit
DS100078-4
FIGURE 2. Receiver Propagation Delay and Transition Time Waveforms
Balanced System
DS100078-5
FIGURE 3. Point-to-Point Application
3 www.national.com
Applications Information (Continued)
(measured from each pin to ground). The device will still op-
erate for receivers input voltages up to V
CC
, but exceeding
V
CC
will turn on the ESD protection circuitry which will clamp
the bus voltages.
Power Decoupling Recommendations:
Bypass capacitors must be used on power pins. Use high
frequency ceramic (surface mount is recommended) 0.1µF
and 0.001µF capacitors in parallel at the power supply pin
with the smallest value capacitor closest to the device supply
pin. Additional scattered capacitors over the printed circuit
board will improve decoupling. Multiple vias should be used
to connect the decoupling capacitors to the power planes. A
10µF (35V) or greater solid tantalum capacitor should be
connected at the power entry point on the printed circuit
board between the supply and ground.
PC Board considerations:
Use at least 4 PCB board layers (top to bottom): LVDS sig-
nals, ground, power, TTL signals.
Isolate TTL signals from LVDS signals, otherwise the TTL
signals may couple onto the LVDS lines. It is best to put TTL
and LVDS signals on different layers which are isolated by a
power/ground plane(s).
Keep drivers and receivers as close to the (LVDS port side)
connectors as possible.
Differential Traces:
Use controlled impedance traces which match the differen-
tial impedance of your transmission medium (ie. cable) and
termination resistor. Run the differential pair trace lines as
close together as possible as soon as they leave the IC
(stubs should be <10mm long). This will help eliminate re-
flections and ensure noise is coupled as commo-mode. In
fact, we have seen that differential signals which are 1mm
apart radiate far less noise than traces 3mm apart since
magnetic field cancellation is much better with the closer
traces. In addition, noise induced on the differential lines is
much more likely to appear as common-mode which is re-
jected by the receiver.
Match electrical lengths between traces to reduce skew.
Skew between the signals of a pair means a phase differ-
ence between signals which destroys the magnetic field can-
cellation benefits of differential signals and EMI will result!
(Note that the velocity of propagation,v=c/E
r
where c (the
speed of light) = 0.2997mm/ps or 0.0118 in/ps). Do not rely
solely on the autoroute function for differential traces. Care-
fully review dimensions to match differential impedance and
provide isolation for the differential lines. Minimize the num-
ber of vias and other discontinuities on the line.
Avoid 90˚ turns (these cause impedance discontinuities).
Use arcs or 45˚ bevels.
Within a pair of traces, the distance between the two traces
should be minimized to maintain common-mode rejection of
the receivers. On the printed circuit board, this distance
should remain constant to avoid discontinuities in differential
impedance. Minor violations at connection points are allow-
able.
Termination:
Use a termination resistor which best matches the differen-
tial impedance or your transmission line. The resistor should
be between 90Ωand 130Ω. Remember that the current
mode outputs need the termination resistor to generate the
differential voltage. LVDS will not work without resistor termi-
nation. Typically, connecting a single resistor across the pair
at the receiver end will suffice.
Surface mount 1%-2
%resistors are the best. PCB stubs,
component lead, and the distance from the termination to the
receiver inputs should be minimized. The distance between
the termination resistor and the receiver should be <10mm
(12mm MAX).
Fail-Safe Feature:
The LVDS receiver is a high gain, high speed device that
amplifies a small differential signal (20mV) to CMOS logic
levels. Due to the high gain and tight threshold of the re-
ceiver, care should be taken to prevent noise from appearing
as a valid signal.
The receiver’s internal fail-safe circuitry is designed to
source/sink a small amount of current, providing fail-safe
protection (a stable known state of HIGH output voltage) for
floating, terminated or shorted receiver inputs.
1. Open Input Pins. The DS90LV018Ais a single receiver
device. Do not tie the receiver inputs to ground or any
other voltages. The input is biased by internal high value
pull up and pull down resistors to set the output to a
HIGH state. This internal circuitry will guarantee a HIGH,
stable output state for open inputs.
2. Terminated Input. If the driver is disconnected (cable
unplugged), or if the driver is in a power-off condition,
the receiver output will again be in a HIGH state, even
with the end of cable 100Ωtermination resistor across
the input pins. The unplugged cable can become a float-
ing antenna which can pick up noise. If the cable picks
up more than 10mV of differential noise, the receiver
may see the noise as a valid signal and switch. To insure
that any noise is seen as common-mode and not differ-
ential, a balanced interconnect should be used. Twisted
pair cable will offer better balance than flat ribbon cable.
3. Shorted Inputs. If a fault condition occurs that shorts
the receiver inputs together, thus resulting in a 0V differ-
ential input voltage, the receiver output will remain in a
HIGH state. Shorted input fail-safe is not supported
across the common-mode range of the device (GND to
2.4V). It is only supported with inputs shorted and no ex-
ternal common-mode voltage applied.
External lower value pull up and pull down resistors (for a
stronger bias) may be used to boost fail-safe in the presence
of higher noise levels. The pull up and pull down resistors
should be in the 5kΩto 15kΩrange to minimize loading and
waveform distortion to the driver. The common-mode bias
point should be set to approximately 1.2V (less than 1.75V)
to be compatible with the internal circuitry.
Probing LVDS Transmission Lines:
Always use high impedance (>100kΩ), low capacitance
(<2 pF) scope probes with a wide bandwidth (1 GHz)
scope. Improper probing will give deceiving results.
Cables and Connectors, General Comments:
When choosing cable and connectors for LVDS it is impor-
tant to remember:
Use controlled impedance media. The cables and connec-
tors you use should have a matched differential impedance
of about 100Ω. They should not introduce major impedance
discontinuities.
Balanced cables (e.g. twisted pair) are usually better than
unbalanced cables (ribbon cable, simple coax) for noise re-
duction and signal quality. Balanced cables tend to generate
www.national.com 4
Applications Information (Continued)
less EMI due to field canceling effects and also tend to pick
up electromagnetic radiation a common-mode (not differen-
tial mode) noise which is rejected by the receiver.
For cable distances <0.5M, most cables can be made to
work effectively. For distances 0.5M ≤d≤10M, CAT 3 (cat-
egory 3) twisted pair cable works well, is readily available
and relatively inexpensive.
Pin Descriptions
Pin No. Name Description
1R
IN
- Inverting receiver input pin
2R
IN
+ Non-inverting receiver input pin
7R
OUT
Receiver output pin
8V
CC
Power supply pin, +3.3V ±0.3V
5 GND Ground pin
3, 4, 6 NC No connection
Ordering Information
Operating Package Type/ Order Number
Temperature Number
−40˚C to +85˚C SOP/M08A DS90LV018ATM
Typical Performance Characteristics
Output High Voltage vs
Power Supply Voltage
DS100078-7
Output Low Voltage vs
Power Supply Voltage
DS100078-8
5 www.national.com
Typical Performance Characteristics (Continued)
Output Short Circuit Current vs
Power Supply Voltage
DS100078-9
Differential Transition Voltage vs
Power Supply Voltage
DS100078-10
Power Supply Current
vs Frequency
DS100078-11
Power Supply Current vs
Ambient Temperature
DS100078-12
Differential Propagation Delay vs
Power Supply Voltage
DS100078-13
Differential Propagation Delay vs
Ambient Temperature
DS100078-14
www.national.com 6
Typical Performance Characteristics (Continued)
Differential Skew vs
Power Supply Voltage
DS100078-15
Differential Skew vs
Ambient Temperature
DS100078-16
Differential Propagation Delay vs
Differential Input Voltage
DS100078-17
Differential Propagation Delay vs
Common-Mode Voltage
DS100078-18
Transition Time vs
Power Supply Voltage
DS100078-19
Transition Time vs
Ambient Temperature
DS100078-20
7 www.national.com
Typical Performance Characteristics (Continued)
Differential Propagation Delay
vs Load
DS100078-22
Transition Time
vs Load
DS100078-23
Differential Propagation Delay
vs Load
DS100078-21
Transition Time
vs Load
DS100078-24
www.national.com 8
9
Physical Dimensions inches (millimeters) unless otherwise noted
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8-Lead (0.150" Wide) Molded Small Outline Package, JEDEC
Order Number DS90LV018ATM
NS Package Number M08A
DS90LV018A 3V LVDS Single CMOS Differential Line Receiver
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
National P/N DS90LV018A - 3V LVDS Single CMOS Differential Line Receiver
See Microcontroller
Products
Products > Analog - Interface > LVDS Circuits > Line Drivers, Receivers and Transceivers > DS90LV018A
DS90LV018A Product Folder
3V LVDS Single CMOS Differential Line Receiver
Generic P/N 90LV018A
General
Description Features Datasheet Package
& Models Samples
& Pricing
Parametric Table Parametric Table
Supply Voltage 3.3V
Process CMOS
Number of Drivers 0
Number of Receivers 1
Data Rate (Mbps) 400
Skew (ns) .05
Datasheet
Title Size in
Kbytes Date View Online Download Receive via
Email
DS90LV018A 3V LVDS Single CMOS Differential Line
Receiver 241
Kbytes
13-
Jul-
98 View Online Download Receive via
Email
DS90LV018A 3V LVDS Single CMOS Differential Line
Receiver (JAPANESE)321
Kbytes
View Online
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Receive via
Email
If you have trouble printing or viewing PDF file(s), see Printing Problems.
Package Availability, Models, Samples & Pricing
Part Number Package Status Models Samples &
Electronic
Orders
Budgetary
Pricing Std
Pack
Size
Package
Marking
Type Pins MSL SPICE IBIS Qty $US
each
DS90LV018ATM SOIC
NARROW 8MSL Full
production N/A lv018atm.ibs
24 Hour
Samples
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90LV0
18ATM
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file:///H|/imaging/BITTING/cpl/20020808_1/08062002_10/NATL/08062002_HTML/DS90LV018A.html (1 of 2) [Aug-09-2002 10:10:01 AM]
National P/N DS90LV018A - 3V LVDS Single CMOS Differential Line Receiver
General Description
The is a single CMOS differential line receiver designed for applications requiring ultra low power dissipation,
low noise and high data rates. The device is designed to support data rates in excess of 400 Mbps (200 MHz)
utilizing Low Voltage Differential Signaling (LVDS) technology.
The accepts low voltage (350 mV typical) differential input signals and translates them to 3V CMOS output
levels. The receiver also supports open, shorted and terminated (100 Ohm) input fail-safe. The receiver
output will be HIGH for all fail-safe conditions. The has a flow-through design for easy PCB layout.
The and companion LVDS line driver provide a new alternative to high power PECL/ECL devices for high
speed point-to-point interface applications.
Features
● >400 Mbps (200 MHz) switching rates
● 50 ps differential skew (typical)
● 2.5 ns maximum propagation delay
● 3.3V power supply design
● Flow-through pinout
● Power down high impedance on LVDS inputs
● Low Power design (18mW @ 3.3V static)
● Interoperable with existing 5V LVDS networks
● Accepts small swing (350 mV typical) differential signal levels
● Supports open, short and terminated input fail-safe
● Conforms to ANSI/TIA/EIA-644 Standard
● Industrial temperature operating range (-40°C to +85°C)
● Available in SOIC package
[Information as of 5-Aug-2002]
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