UDG-12040
RF
TRIP
MODE
VDD
VREG
VIN
VIN
VIN
VIN
VIN
VIN
TPS53318/TPS53319
VFB
EN
PG OOD
VBST
ROVP
LL
LL
LL
1 2 3 4 5 6 7 8 9 10 11
22 21 20 19 18 17 16 15 14 13 12
VOUT
VREG
GND
LL
LL
LL
VVDD
VIN
PGOOD
EN
TPS53318, TPS53319
www.ti.com
SLUSAY8B –JUNE 2012–REVISED MAY 2013
High-Efficiency 8-A or 14-A Synchronous Buck Converter with Eco-mode™
Check for Samples: TPS53318,TPS53319
1FEATURES
2• Conversion Input Voltage Range: 1.5 V to 22 V • Open-Drain Power Good Indication
• VDD Input Voltage Range: 4.5 V to 25 V • Incorporates NexFET™ Power Block
Technology
• 91% Efficiency from 12 V to 1.5 V at 14 A • 22-pin QFN Package with PowerPAD™
• Output Voltage Range: 0.6 V to 5.5 V
• 5-V LDO Output APPLICATIONS
• Supports Single Rail Input • Server/Storage
• Integrated Power MOSFETs with 8-A • Workstations and Desktops
(TPS53318) or 14-A (TPS53319) of Continuous • Telecommunications Infrastructure
Output Current
• Auto-Skip Eco-mode™ for Light-Load DESCRIPTION
Efficiency The TPS53318 and TPS53319 are D-CAP™ mode,
• <110 μA Shut Down Current 8-A or 14-A synchronous switchers with integrated
• D-CAP™ Mode with Fast Transient Response MOSFETs. They are designed for ease of use, low
• Selectable Switching Frequency from 250 kHz external component count, and space-conscious
power systems.
to 1 MHz with External Resistor
• Selectable Auto-Skip or PWM-Only Operation These devices feature accurate 1%, 0.6-V reference,
and integrated boost switch. A sample of competitive
• Built-in 1% 0.6-V Reference. features include: 1.5-V to 22-V wide conversion input
• 0.7-ms, 1.4-ms, 2.8-ms and 5.6-ms Selectable voltage range, very low external component count, D-
Internal Voltage Servo Soft-Start CAP™ mode control for super fast transient, auto-
• Integrated Boost Switch skip mode operation, internal soft-start control,
selectable frequency, and no need for compensation.
• Pre-Charged Start-up Capability
• Adjustable Overcurrent Limit with Thermal The conversion input voltage ranges from 1.5 V to
22 V, the supply voltage range is from 4.5 V to 25 V,
Compensation and the output voltage range is from 0.6 V to 5.5 V.
• Overvoltage, Undervoltage, UVLO and Over-
Temperature Protection These devices are available in 5 mm x 6 mm, 22-pin
QFN package and is specified from –40°C to 85°C.
• Supports All Ceramic Output Capacitors
SIMPLIFIED APPLICATION
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2Eco-mode, NexFET, PowerPAD are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Copyright © 2012–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TPS53318, TPS53319
SLUSAY8B –JUNE 2012–REVISED MAY 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
ORDERING PART MINIMUM
TAPACKAGE PINS OUTPUT SUPPLY ECO PLAN
NUMBER QUANTITY
TPS53318DQPR Tape and reel 2500
TPS53318DQPT Mini reel 250
Plastic QFN Pb-Free (RoHS
–40°C to 85°C 22
(DQP) Exempt)
TPS53319DQPR Tape and reel 2500
TPS53319DQPT Mini reel 250
ABSOLUTE MAXIMUM RATINGS(1)
VALUE UNIT
MIN MAX
VIN (main supply) –0.3 30
VDD –0.3 28
Input voltage range VBST –0.3 32 V
VBST(with respect to LL) –0.3 7
EN, TRIP, VFB, RF, MODE, ROVP –0.3 7
DC –2 30
LL Pulse < 20ns, E=5 μJ –7 32
Output voltage range V
PGOOD, VREG –0.3 7
GND –0.3 0.3
Source/Sink current VBST 50 mA
Operating free-air temperature, TA–40 85
Storage temperature range, Tstg –55 150 ˚C
Junction temperature range, TJ–40 150
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 300
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
THERMAL INFORMATION TPS53319
THERMAL METRIC(1) UNITS
DQP (22 PINS)
θJA Junction-to-ambient thermal resistance 27.2
θJCtop Junction-to-case (top) thermal resistance 17.1
θJB Junction-to-board thermal resistance 5.9 °C/W
ψJT Junction-to-top characterization parameter 0.8
ψJB Junction-to-board characterization parameter 5.8
θJCbot Junction-to-case (bottom) thermal resistance 1.2
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
2Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: TPS53318 TPS53319
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SLUSAY8B –JUNE 2012–REVISED MAY 2013
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted) VALUE UNIT
MIN MAX
VIN (main supply) 1.5 22
VDD 4.5 25
Input voltage range VBST 4.5 28 V
VBST(with respect to LL) 4.5 6.5
EN, TRIP, VFB, RF, MODE, ROVP –0.1 6.5
Output voltage range LL –1 27 V
PGOOD, VREG –0.1 6.5
Junction temperature range, TJ–40 125 °C
ELECTRICAL CHARACTERISTICS
Over recommended free-air temperature range, VVDD=12 V (unless otherwise noted)
PARAMETER CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
VIN pin power conversion input
VVIN 1.5 22 V
voltage
VVDD Supply input voltage 4.5 25.0 V
IVIN(leak) VIN pin leakage current VEN = 0 V 1 µA
IVDD VDD supply current TA= 25°C, No load, VEN = 5 V, VVFB = 0.630 V 420 590 µA
IVDDSDN VDD shutdown current TA= 25°C, No load, VEN = 0 V 110 µA
INTERNAL REFERENCE VOLTAGE
VVFB VFB regulation voltage CCM condition(1) 0.600 V
TA= 25°C 0.597 0.600 0.603
VVFB VFB regulation voltage 0°C ≤TA≤85°C 0.5952 0.600 0.6048 V
–40°C ≤TA≤85°C 0.594 0.600 0.606
IVFB VFB input current VVFB = 0.630 V, TA= 25°C 0.01 0.20 µA
LDO OUTPUT
VVREG LDO output voltage 0 mA ≤IVREG ≤30 mA 4.77 5.00 5.36 V
IVREG LDO output current(1) Maximum current allowed from LDO 30 mA
VDO Low drop out voltage VVDD = 4.5 V, IVREG = 30 mA 250 mV
BOOT STRAP SWITCH
VFBST Forward voltage VVREG-VBST, IF= 10 mA, TA= 25°C 0.1 0.2 V
IVBSTLK VBST leakage current VVBST = 23 V, VSW = 17 V, TA= 25°C 0.01 1.50 µA
DUTY AND FREQUENCY CONTROL
tOFF(min) Minimum off-time TA= 25°C 150 260 400 ns
VIN = 17 V, VOUT = 0.6 V, fSW = 1 MHz,
tON(min) Minimum on-time 35 ns
TA= 25 °C(1)
SOFT START
RMODE = 39 kΩ0.7
RMODE = 100 kΩ1.4
Internal soft-start time from
tSS ms
VOUT = 0 V to 95% of VOUT RMODE = 200 kΩ2.8
RMODE = 470 kΩ5.6
OUTPUT VOLTAGE DISCHARGE
IDSCHG Output voltage discharge current VEN= 0 V, VSW= 0.5 V 5.0 6.6 9.0 mA
(1) Ensured by design. Not production tested.
Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Links: TPS53318 TPS53319
TPS53318, TPS53319
SLUSAY8B –JUNE 2012–REVISED MAY 2013
www.ti.com
ELECTRICAL CHARACTERISTICS
Over recommended free-air temperature range, VVDD=12 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWERGOOD
PG in from lower 92.5% 95.0% 98.5%
VTHPG PG threshold PG in from higher 107.5% 110.0% 112.5%
PG hysteresis 2.5% 5.0% 7.5%
RPG PG transistor on-resistance 15 30 60 Ω
tPGDEL PG delay Delay for PG in 0.8 1 1.2 ms
LOGIC THRESHOLD AND SETTING CONDITIONS
Enable 1.0 1.3 1.6
VEN EN Voltage V
Disable 0.8 1.0 1.2
IEN EN Input current VEN = 5 V 1.0 µA
RRF = 0 Ωto GND, TA= 25°C(1) 200 250 300
RRF = 187 kΩto GND, TA= 25°C(1) 250 300 350
RRF = 619 kΩ, to GND, TA= 25°C(1) 350 400 450
RRF = Open, TA= 25°C(1) 450 500 550
fSW Switching frequency kHz
RRF = 866 kΩto VREG, TA= 25°C(1) 540 600 660
RRF = 309 kΩto VREG, TA= 25°C(1) 670 750 820
RRF = 124 kΩto VREG, TA= 25°C(1) 770 850 930
RRF = 0 Ωto VREG, TA= 25°C(1) 880 970 1070
PROTECTION: CURRENT SENSE
ITRIP TRIP source current VTRIP = 1 V, TA= 25°C 10 µA
TCITRIP TRIP current temperature coeffficient On the basis of 25°C(2) 3000 ppm/°C
TPS53318 0.4 1.5
Current limit threshold setting
VTRIP VTRIP-GND V
range TPS53319 0.4 2.4
VTRIP = 1.2 V 37.5
VOCL Current limit threshold mV
VTRIP = 0.4 12.5
VTRIP = 1.2 V –37.5
VOCLN Negative current limit threshold mV
VTRIP = 0.4 V –12.5
RTRIP = 66.5 kΩ, 0°C ≤TA≤125°C 4.6 5.4 6.3
IOCP Valley current limit threshold A
RTRIP = 66.5 kΩ, –40°C ≤TA≤125°C 4.4 5.4 6.3
Positive 3 15
VAZCADJ Auto zero cross adjustable range mV
Negative –15 –3
PROTECTION: UVP and OVP
VOVP OVP trip threshold OVP detect 115% 120% 125%
tOVPDEL OVP proprogation delay VFB delay with 50-mV overdrive 1 µs
VUVP Output UVP trip threshold UVP detect 65% 70% 75%
tUVPDEL Output UVP proprogation delay 0.8 1.0 1.2 ms
tUVPEN Output UVP enable delay From enable to UVP workable 1.5 2.3 3.0 ms
UVLO
Wake up 4.00 4.20 4.33
VUVVREG VREG UVLO threshold V
Hysteresis 0.25
THERMAL SHUTDOWN
Shutdown temperature(2) 145
TSDN Thermal shutdown threshold °C
Hysteresis(2) 10
(1) Not production tested. Test condition is VIN= 12 V, VOUT= 1.2 V, IOUT = 5 A using application circuit shown in Figure 1.
(2) Ensured by design. Not production tested.
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Product Folder Links: TPS53318 TPS53319
VFB
EN
PGOOD
1
2
3
4
5
6
7
8
9
10
11 12
13
14
15
16
17
GND
PowerPadTM
18
19
20
21
22
VBST
TRIP
MODE
ROVP
LL
LL
LL
LL
LL
LL
RF
VDD
VREG
VIN
VIN
VIN
VIN
VIN
VIN
TPS53318, TPS53319
www.ti.com
SLUSAY8B –JUNE 2012–REVISED MAY 2013
DEVICE INFORMATION
DQP PACKAGE
22 PINS
(TOP VIEW)
PIN FUNCTIONS
PIN I/O/P(1) DESCRIPTION
NAME NO.
EN 2 I Enable pin.Typical turn-on threshold voltage is 1.3 V. Typical turn-off threshold voltage is 1.0 V.
GND G Ground and thermal pad of the device. Use proper number of vias to connect to ground plane.
6
7
8
LL B Output of converted power. Connect this pin to the output Inductor.
9
10
11 Soft-start and mode selection. Connect a resistor to select soft-start time using Table 1. The soft-start time
MODE 20 I is detected and stored into internal register during start-up.
Open drain power good flag. Provides 1-ms start-up delay after VFB falls in specified limits. When VFB
PGOOD 3 O goes out of the specified limits PGOOD goes low after a 2-µs delay
Redundant overvoltage protection (OVP) input. Use a resistor divider to connect this pin to VOUT.
ROVP 5 I Internally pulled down to GND with 1.5-MΩresistor. Float this pin or connect to GND if redundant OVP is
not needed.
Switching frequency selection. Connect a resistor to GND or VREG to select switching frequency using
RF 22 I Table 2. The switching frequency is detected and stored during the startup.
OCL detection threshold setting pin. ITRIP = 10 µA at room temperature, 3000 ppm/°C current is sourced
and set the OCL trip voltage as follows.
TRIP 21 I space VOCL=VTRIP/32 (VTRIP ≤2.4 V, VOCL ≤75 mV)
Supply input for high-side FET gate driver (boost terminal). Connect capacitor from this pin to LL node.
VBST 4 P Internally connected to VREG via bootstrap MOSFET switch.
VDD 19 P Controller power supply input. VDD input voltage range is from 4.5 V to 25 V.
VFB 1 I Output feedback input. Connect this pin to VOUT through a resistor divider.
12
13
14
VIN P Conversion power input.The conversion input voltage range is from 1.5 V to 22 V.
15
16
17
(1) I=Input, O=Output, B=Bidirectional, P=Supply, G=Ground
Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Links: TPS53318 TPS53319
Shutdown VREG
VDDOK
LL
TPS53318/TPS53319
tON
One-
Shot
Control
Logic
+
+OCP
ZC
GND
LL
XCON
GND
+
1.3 V/1.0 V
EN
UVP/OVP
Logic
+
THOK 145°C/
135°C
+
4.2 V/
3.95 V
VIN
VBST
Fault
LL
GND
RF
+
+
PWM
+
OV
+20%
UV
+0.6 V –30% Delay
SS
0.6 V
VFB
TRIP
Enable
+
+
Delay
0.6 V +10/15%
0.6 V –5/10%
PGOOD
Control Logic
·On/Off time
·Minimum On/Off
·Light load
·OVP/UVP
·FCCM/Skip
UDG-12041
10 ?A
VREG
+
SS
FCCM/
Skip
Decode
MODE
VDD
Ramp
Compensation
+
LDO
+ROVP
TPS53318, TPS53319
SLUSAY8B –JUNE 2012–REVISED MAY 2013
www.ti.com
PIN FUNCTIONS (continued)
PIN I/O/P(1) DESCRIPTION
NAME NO.
VREG 18 P 5-V low drop out (LDO) output. Supplies the internal analog circuitry and driver circuitry.
BLOCK DIAGRAM
NOTE
The thresholds shown in this diagram are typical numbers. Refer to the ELECTRICAL
CHARACTERISTICS table for threshold tolerance.
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Product Folder Links: TPS53318 TPS53319
UDG-12077
RF TRIP MODE VDD VREG VIN VIN VIN VIN VINVIN
TPS53318/TPS53319
VFB EN PGOOD VBST ROVP LL LL LL
1 2 3 4 5 6 7 8 9 10 11
22 21 20 19 18 17 16 15 14 13 12
VOUT
1.2V
C5
0.1 µF
VREG
CIN
22 µF
GND
LL LL LL
L1
0.5 ?H
HCB 1175B-501
COUT
330 µF
R1
10 k?
R2
10 k?
R10
100 k?
VIN
12V
R11
NI
C6
NI
COUT
330 µF
R9
0?
CIN
22 µF
CIN
22 µF
CIN
22 µF
R6
200 k?
R8
120 k?
R4
NI
C4
1 µF
C3
1 µF
VVDD
4.5 V to 25 V
EN
PGOOD
UDG-12076
RF TRIP MODE VDD VREG VIN VIN VIN VIN VINVIN
TPS53318/TPS53319
VFB EN PGOOD VBST ROVP LL LL LL
1 2 3 4 5 6 7 8 9 10 11
22 21 20 19 18 17 16 15 14 13 12
VOUT
1.2V
C5
0.1 µF
VREG
CIN
22 µF
GND
LL LL LL
L1
0.5 ?H
HCB1175B-501
COUT
4 x 100 µF
Ceramic
R1 9.76 k?
R2
10 k?
R10
100 k?
VIN
12V
R13
NI
C6
NI
R9
0?
CIN
22 µF
CIN
22 µF
CIN
22 µF
R6
200 k?
R8
120 k?
R4
NI
C4
1 µF
C3
1 µF
VVDD
4.5 V to 25 V
R7
3.01 k?
C1
0.1 µF
C2
1 nF
EN
PGOOD
R12
10 k?
R11
9.76 k?
TPS53318, TPS53319
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SLUSAY8B –JUNE 2012–REVISED MAY 2013
APPLICATION CIRCUIT DIAGRAM
Figure 1. Typical Application Circuit with Ceramic Output Capacitors, ROVP Function Used
Figure 2. Typical Application Circuit with Bulk Output Capacitors, ROVP Function Not Used
Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Links: TPS53318 TPS53319
1
10
100
1000
0.01 0.1 1 10 20
Output Current (A)
Switching Frequency (kHz)
FCCM
Skip Mode
VIN = 12 V
VOUT = 1.2 V
fSW = 300 kHz
G001
1
10
100
1000
0.01 0.1 1 10 20
Output Current (A)
Switching Frequency (kHz)
FCCM
Skip Mode
VIN = 12 V
VOUT = 1.2 V
fSW = 500 kHz
G001
4.0
4.2
4.4
4.6
4.8
5.0
5.2
5.4
5.6
5.8
6.0
−40 −25 −10 5 20 35 50 65 80 95 110 125
Junction Temperature (°C)
Valley OCP Threshold (A)
RTRIP = 66.5 kΩ
G001
0
20
40
60
80
100
120
140
−40 −25 −10 5 20 35 50 65 80 95 110 125
Junction Temperature (°C)
OVP/UVP Trip Threshold (%)
OVP
UVP
G001
0
100
200
300
400
500
600
700
−40 −25 −10 5 20 35 50 65 80 95 110 125
Junction Temperature (°C)
VDD Supply Current (µA)
VEN = 5V
VVDD = 12 V
VVFB = 0.63 V
No Load
G001
0
20
40
60
80
100
120
140
160
−40 −25 −10 5 20 35 50 65 80 95 110 125
Junction Temperature (°C)
VDD Shutdown Current (µA)
VEN = 0 V
VVDD = 12 V
No Load
G001
TPS53318, TPS53319
SLUSAY8B –JUNE 2012–REVISED MAY 2013
www.ti.com
TYPICAL CHARACTERISTICS
Figure 3. VDD Supply Current vs. Junction Temperature Figure 4. VDD Shutdown Current vs. Junction Temperature
Figure 5. Valley OCP Threshold vs Temperature Figure 6. OVP/UVP Trip Threshold vs. Junction
Temperature
Figure 7. Switching Frequency vs. Output Current Figure 8. Switching Frequency vs. Output Current
8Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: TPS53318 TPS53319
1.180
1.185
1.190
1.195
1.200
1.205
1.210
1.215
1.220
4 8 12 16 20 24
Input Voltage (V)
Output Voltage (V)
FCCM, IOUT = 0 A
Skip Mode, IOUT = 0 A
FCCM and Skip Mode, IOUT = 14 A
fSW = 500 kHz
VIN = 12 V
G000
0
10
20
30
40
50
60
70
80
90
100
0.01 0.1 1 10 15
Output Current (A)
Efficiency (%)
Skip Mode, fSW = 500 kHz
FCCM, fSW = 500 kHz
Skip Mode, fSW = 300 kHz
FCCM, fSW = 300 kHz
TPS53319
VIN = 12 V
VOUT = 1.2 V
G001
0
200
400
600
800
1000
1200
0 1 2 3 4 5 6
Output Voltage (V)
Switching Frequency (kHz)
fSET = 300 kHz
fSET = 500 kHz fSET = 750 kHz
fSET = 1 MHz
VIN = 12 V
IOUT = 5 A
G000
1.180
1.185
1.190
1.195
1.200
1.205
1.210
1.215
1.220
0 3 6 9 12 15
Output Current (A)
Output Voltage (V)
Skip Mode
FCCM
TPS53319
fSW = 500 kHz
VIN = 12 V
VOUT = 1.2 V
G001
1
10
100
1000
0.01 0.1 1 10 20
Output Current (A)
Switching Frequency (kHz)
FCCM
Skip Mode
VIN = 12 V
VOUT = 1.2 V
fSW = 750 kHz
G001
1
10
100
1000
0.01 0.1 1 10 20
Output Current (A)
Switching Frequency (kHz)
FCCM
Skip Mode
VIN = 12 V
VOUT = 1.2 V
fSW = 1 MHz
G001
TPS53318, TPS53319
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SLUSAY8B –JUNE 2012–REVISED MAY 2013
TYPICAL CHARACTERISTICS (continued)
Figure 9. Switching Frequency vs. Output Current Figure 10. Switching Frequency vs. Output Current
Figure 11. Switching Frequency vs. Output Voltage Figure 12. Output Voltage vs. Output Current
Figure 13. Output Voltage vs. Input Voltage Figure 14. Efficiency vs Output Current
Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Links: TPS53318 TPS53319
70
74
78
82
86
90
94
98
0 2 4 6 8 10
Output Current (A)
Efficiency (%)
VOUT = 3.3 V
VOUT = 1.8 V
VOUT = 1.5 V
VOUT = 1.2 V
VOUT = 1.1 V
VOUT = 1.0 V
FCCM
VIN = 5 V
VVDD = 5 V
fSW = 500 kHz
TPS53319
G001
70
74
78
82
86
90
94
98
0 2 4 6 8 10
Output Current (A)
Efficiency (%)
VOUT = 3.3 V
VOUT = 1.8 V
VOUT = 1.5 V
VOUT = 1.2 V
VOUT = 1.1 V
VOUT = 1.0 V
Skip Mode
VIN = 5 V
VVDD = 5 V
fSW = 500 kHz
TPS53319
G001
70
74
78
82
86
90
94
98
0 2 4 6 8 10 12 14 16
Output Current (A)
Efficiency (%)
VOUT = 5.0 V
VOUT = 3.3 V
VOUT = 1.8 V
VOUT = 1.5 V
VOUT = 1.2 V
VOUT = 1.1 V
VOUT = 1.0 V
FCCM
VIN = 12 V
VVDD = 5 V
fSW = 500 kHz
TPS53319
G000
70
74
78
82
86
90
94
98
0 2 4 6 8 10 12 14 16
Output Current (A)
Efficiency (%)
VOUT = 5.0 V
VOUT = 3.3 V
VOUT = 1.8 V
VOUT = 1.5 V
VOUT = 1.2 V
VOUT = 1.1 V
VOUT = 1.0 V
Skip Mode
VIN = 12 V
VVDD = 5 V
fSW = 500 kHz
TPS53319
G001
70
74
78
82
86
90
94
98
0 2 4 6 8 10 12 14 16
Output Current (A)
Efficiency (%)
VOUT = 3.3 V
VOUT = 1.8 V
VOUT = 1.5 V
VOUT = 1.2 V
VOUT = 1.1 V
VOUT = 1.0 V
FCCM
VIN = 12 V
VVDD = 5 V
fSW = 300 kHz
TPS53319
G001
70
74
78
82
86
90
94
98
0 2 4 6 8 10 12 14 16
Output Current (A)
Efficiency (%)
VOUT = 3.3 V
VOUT = 1.8 V
VOUT = 1.5 V
VOUT = 1.2 V
VOUT = 1.1 V
VOUT = 1.0 V
Skip Mode
VIN = 12 V
VVDD = 5 V
fSW = 300 kHz
TPS53319
G001
TPS53318, TPS53319
SLUSAY8B –JUNE 2012–REVISED MAY 2013
www.ti.com
TPS53319 TYPICAL CHARACTERISTICS
Figure 15. Efficiency vs Output Current Figure 16. Efficiency vs Output Current
Figure 17. Efficiency vs Output Current Figure 18. Efficiency vs Output Current
Figure 19. Efficiency vs Output Current Figure 20. Efficiency vs Output Current
10 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: TPS53318 TPS53319
70
74
78
82
86
90
94
98
0 1 2 3 4 5 6 7 8 9 10
Output Current (A)
Efficiency (%)
VOUT = 3.3 V
VOUT = 1.8 V
VOUT = 1.5 V
VOUT = 1.2 V
VOUT = 1.1 V
VOUT = 1.0 V
TPS53318
FCCM
VIN = 5 V
VVDD = 5 V
fSW = 500 kHz
G001
70
74
78
82
86
90
94
98
0 1 2 3 4 5 6 7 8 9 10
Output Current (A)
Efficiency (%)
VOUT = 3.3 V
VOUT = 1.8 V
VOUT = 1.5 V
VOUT = 1.2 V
VOUT = 1.1 V
VOUT = 1.0 V
TPS53318
Skip Mode
VIN = 5 V
VVDD = 5 V
fSW = 500 kHz
G001
70
74
78
82
86
90
94
98
0 1 2 3 4 5 6 7 8 9 10
Output Current (A)
Efficiency (%)
VOUT = 5.0 V
VOUT = 3.3 V
VOUT = 1.8 V
VOUT = 1.5 V
VOUT = 1.2 V
VOUT = 1.1 V
VOUT = 1.0 V
FCCM
VIN = 12 V
VVDD = 5 V
fSW = 500 kHz
TPS53318
G000
70
74
78
82
86
90
94
98
0 1 2 3 4 5 6 7 8 9 10
Output Current (A)
Efficiency (%)
VOUT = 5.0 V
VOUT = 3.3 V
VOUT = 1.8 V
VOUT = 1.5 V
VOUT = 1.2 V
VOUT = 1.1 V
VOUT = 1.0 V
Skip Mode
VIN = 12 V
VVDD = 5 V
fSW = 500 kHz
TPS53318
G000
70
74
78
82
86
90
94
98
0 1 2 3 4 5 6 7 8 9 10
Output Current (A)
Efficiency (%)
VOUT = 3.3 V
VOUT = 1.8 V
VOUT = 1.5 V
VOUT = 1.2 V
VOUT = 1.1 V
VOUT = 1.0 V
TPS53318
FCCM
VIN = 12 V
VVDD = 5 V
fSW = 300 kHz
G001
70
74
78
82
86
90
94
98
0 1 2 3 4 5 6 7 8 9 10
Output Current (A)
Efficiency (%)
VOUT = 3.3 V
VOUT = 1.8 V
VOUT = 1.5 V
VOUT = 1.2 V
VOUT = 1.1 V
VOUT = 1.0 V
TPS53318
Skip Mode
VIN = 12 V
VVDD = 5 V
fSW = 300 kHz
G001
TPS53318, TPS53319
www.ti.com
SLUSAY8B –JUNE 2012–REVISED MAY 2013
TPS53318 TYPICAL CHARACTERISTICS
Figure 21. Efficiency vs Output Current Figure 22. Efficiency vs Output Current
Figure 23. Efficiency vs Output Current Figure 24. Efficiency vs Output Current
Figure 25. Efficiency vs Output Current Figure 26. Efficiency vs Output Current
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TYPICAL CHARACTERISTICS
Figure 27. Start-Up Figure 28. Pre-Bias Start-Up
Figure 29. Shutdown Figure 30. UVLO Start-Up
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TYPICAL CHARACTERISTICS (continued)
Figure 31. 1.1-V Output FCCM Mode Steady-State Operation Figure 32. 1.1-V Output Skip Mode Steady-State Operation
Figure 33. CCM to DCM Transition Figure 34. DCM to CCM Transition
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TYPICAL CHARACTERISTICS (continued)
Figure 35. FCCM Load Transient Figure 36. Skip Mode Load Transeint
Figure 37. Overcurrent Protection Figure 38. Over-temperature Protection
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SLUSAY8B –JUNE 2012–REVISED MAY 2013
TYPICAL CHARACTERISTICS (continued)
Figure 39. Short Circuit Protection
.THERMAL CHARACTERISTICS
Thermal signatures for the TPS53319 EVM, VIN = 12 V, IOUT = 14 A, fSW = 500 kHz, TA= 25°C, No airflow
Figure 40. VOUT = 1.2 V Figure 41. VOUT = 5.0 V
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APPLICATION INFORMATION
General Description
The TPS53318 and TPS53319 are high-efficiency, single channel, synchronous buck converters suitable for low
output voltage point-of-load applications in computing and similar digital consumer applications. The device
features proprietary D-CAP™ mode control combined with an adaptive on-time architecture. This combination is
ideal for building modern low duty ratio, ultra-fast load step response DC-DC converters. The output voltage
ranges from 0.6 V to 5.5 V. The conversion input voltage range is from 1.5 V to 22 V and the VDD bias voltage is
from 4.5 V to 25 V. The D-CAP™ mode uses the equivalent series resistance (ESR) of the output capacitor(s) to
sense the device current . One advantage of this control scheme is that it does not require an external phase
compensation network. This allows a simple design with a low external component count. Eight preset switching
frequency values can be chosen using a resistor connected from the RF pin to ground or VREG. Adaptive on-
time control tracks the preset switching frequency over a wide input and output voltage range while allowing the
switching frequency to increase at the step-up of the load.
These devices have a MODE pin to select between auto-skip mode and forced continuous conduction mode
(FCCM) for light load conditions. The MODE pin also sets the selectable soft-start time ranging from 0.7 ms to
5.6 ms as shown in Table 1.
5-V LDO and VREG Start-Up
Both the TPS53318 and TPS53319 have an internal 5-V LDO feature using input from VDD and output to VREG.
When the VDD voltage rises above 1 V, the internal LDO is enabled and outputs voltage to the VREG pin. The
VREG voltage provides the bias voltage for the internal analog circuitry. It also provides the supply voltage for
the gate drives.
NOTE
The 5-V LDO is not controlled by the EN pin. It starts up whenever VDD rises to
approximately 2 V. (see Figure 31).
Enable, Soft Start, and Mode Selection
When the EN pin voltage rises above the enable threshold voltage (typically 1.3 V), the controller enters its start-
up sequence. The internal LDO regulator starts immediately and regulates to 5 V at the VREG pin. The controller
then uses the first 250 μs to calibrate the switching frequency setting resistance attached to the RF pin and
stores the switching frequency code in internal registers. During this period, the MODE pin also senses the
resistance attached to this pin and determines the soft-start time . Switching is inhibited during this phase. In the
second phase, an internal DAC starts ramping up the reference voltage from 0 V to 0.6 V. Depending on the
MODE pin setting, the ramping up time varies from 0.7 ms to 5.6 ms. Smooth and constant ramp-up of the
output voltage is maintained during start-up regardless of load current.
Table 1. Soft-Start and MODE Settings
MODE SELECTION ACTION SOFT-START TIME (ms) RMODE (kΩ)
0.7 39
1.4 100
Auto Skip Pull down to GND 2.8 200
5.6 475
0.7 39
1.4 100
Forced CCM(1) Connect to PGOOD 2.8 200
5.6 475
(1) Device enters FCCM after the PGOOD pin goes high when MODE is connected to PGOOD through
the resistor RMODE.
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Product Folder Links: TPS53318 TPS53319
VFB
Compensation
Ramp
PWM
tON tOFF
VREF
UDG-10209
VFB
VREF
PWM
tON tOFF
UDG-10208
TPS53318, TPS53319
www.ti.com
SLUSAY8B –JUNE 2012–REVISED MAY 2013
After soft-start begins, the MODE pin becomes the input of an internal comparator which determines auto skip or
FCCM mode operation. If MODE voltage is higher than 1.3 V, the converter enters into FCCM mode. Otherwise
it will be in auto skip mode at light load condition. Typically, when FCCM mode is selected, the MODE pin is
connected to PGOOD through the RMODE resistor, so that before PGOOD goes high the converter remains in
auto skip mode.
Adaptive On-Time D-CAP™ Control and Frequency Selection
Neither the TPS53318 nor the TPS53319 has a dedicated oscillator to determine switching frequency. However,
the device operates with pseudo-constant frequency by feed-forwarding the input and output voltages into the
on-time one-shot timer. The adaptive on-time control adjusts the on-time to be inversely proportional to the input
voltage and proportional to the output voltage (tON ∝VOUT/VIN).
This makes the switching frequency fairly constant in steady state conditions over a wide input voltage range.
The switching frequency is selectable from eight preset values by a resistor connected between the RF pin and
GND or between the RF pin and the VREG pin as shown in Table 2. (Maintaining open resistance sets the
switching frequency to 500 kHz.)
Table 2. Resistor and Switching Frequency
RESISTOR (RRF) SWITCHING
CONNECTIONS FREQUENCY
(fSW)
VALUE (kΩ) CONNECT TO (kHz)
0 GND 250
187 GND 300
619 GND 400
OPEN n/a 500
866 VREG 600
309 VREG 750
124 VREG 850
0 VREG 970
The off-time is modulated by a PWM comparator. The VFB node voltage (the mid-point of resistor divider) is
compared to the internal 0.6-V reference voltage added with a ramp signal. When both signals match, the PWM
comparator asserts a set signal to terminate the off time (turn off the low-side MOSFET and turn on high-side
MOSFET). The set signal is valid if the inductor current level is below the OCP threshold, otherwise the off time
is extended until the current level falls below the threshold.
Figure 42 ,Figure 43 show two on-time control schemes.
Figure 42. On-Time Control Without Ramp Figure 43. On-Time Control With Ramp
Compensation Compensation
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Product Folder Links: TPS53318 TPS53319
( )
( )
- ´
= ´
´ ´
IN OUT OUT
OUT LL
SW IN
V V V
1
I
2 L f V
TPS53318, TPS53319
SLUSAY8B –JUNE 2012–REVISED MAY 2013
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Ramp Signal
The TPS53318 and TPS53319 add a ramp signal to the 0.6-V reference in order to improve jitter performance.
As described in the previous section, the feedback voltage is compared with the reference information to keep
the output voltage in regulation. By adding a small ramp signal to the reference, the signal-to-noise ratio at the
onset of a new switching cycle is improved. Therefore the operation becomes less jittery and more stable. The
ramp signal is controlled to start with –7 mV at the beginning of an on-cycle and becomes 0 mV at the end of an
off-cycle in steady state.
During skip mode operation, under discontinuous conduction mode (DCM), the switching frequency is lower than
the nominal frequency and the off-time is longer than the off-time in CCM. Because of the longer off-time, the
ramp signal extends after crossing 0 mV. However, it is clamped at 3 mV to minimize the DC offset.
Auto-Skip Eco-mode™ Light Load Operation
While the MODE pin is pulled low via RMODE, the controller automatically reduces the switching frequency at light
load conditions to maintain high efficiency. Detailed operation is described as follows. As the output current
decreases from heavy load condition, the inductor current is also reduced and eventually comes to the point that
its rippled valley touches zero level, which is the boundary between continuous conduction and discontinuous
conduction modes. The synchronous MOSFET is turned off when this zero inductor current is detected. As the
load current further decreases, the converter runs into discontinuous conduction mode (DCM). The on-time is
kept almost the same as it was in the continuous conduction mode so that it takes longer time to discharge the
output capacitor with smaller load current to the level of the reference voltage. The transition point to the light-
load operation IOUT(LL) (i.e., the threshold between continuous and discontinuous conduction mode) can be
calculated as shown in Equation 1.
where
• ƒSW is the PWM switching frequency (1)
Switching frequency versus output current in the light load condition is a function of L, VIN and VOUT, but it
decreases almost proportionally to the output current from the IOUT(LL) given in Equation 1. For example, it is 60
kHz at IOUT(LL)/5 if the frequency setting is 300 kHz.
Adaptive Zero Crossing
The TPS53318 and TPS53319 have an adaptive zero crossing circuit which performs optimization of the zero
inductor current detection at skip mode operation. This function pursues ideal low-side MOSFET turning off
timing and compensates inherent offset voltage of the Z-C comparator and delay time of the Z-C detection circuit.
It prevents SW-node swing-up caused by too late detection and minimizes diode conduction period caused by
too early detection. As a result, better light load efficiency is delivered.
Forced Continuous Conduction Mode
When the MODE pin is tied to PGOOD through a resistor, the controller keeps continuous conduction mode
(CCM) in light load condition. In this mode, switching frequency is kept almost constant over the entire load
range which is suitable for applications need tight control of the switching frequency at a cost of lower efficiency.
Output Discharge Control
When the EN pin becomes low, the TPS53318 and TPS53319 discharge the output capacitor using the internal
MOSFET connected between the SW pin and the PGND pin while the high-side and low-side MOSFETs are
maintained in the OFF state. The typical discharge resistance is 75 Ω. The soft discharge occurs only as EN
becomes low. The discharge circuit is powered by VDD. While VDD remains high, the discharge circuit remains
active.
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( ) ( ) ( )
= W ´ m
TRIP TRIP TRIP
V mV R k I A
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SLUSAY8B –JUNE 2012–REVISED MAY 2013
Power-Good
The TPS53318 and TPS53319 have power-good output that indicates high when switcher output is within the
target. The power-good function is activated after soft-start has finished. If the output voltage becomes within
+10% and –5% of the target value, internal comparators detect power-good state and the power-good signal
becomes high after a 1-ms internal delay. If the output voltage goes outside of +15% or –10% of the target value,
the power-good signal becomes low after two microsecond (2-μs) internal delay. The power-good output is an
open drain output and must be pulled up externally.
The power-good MOSFET is powered through the VDD pin. VVDD must be >1 V in order to have a valid power-
good logic. It is recommended to pull PGOOD up to VREG (or a voltage divided from VREG) so that the power-
good logic is still valid even without VDD supply.
Current Sense, Overcurrent and Short Circuit Protection
The TPS53318 and TPS53319 have cycle-by-cycle overcurrent limiting control. The inductor current is monitored
during the OFF state and the controller maintains the OFF state during the period in that the inductor current is
larger than the overcurrent trip level. In order to provide both good accuracy and cost effective solution,
TPS53319 supports temperature compensated MOSFET RDS(on) sensing. The TRIP pin should be connected to
GND through the trip voltage setting resistor, RTRIP. The TRIP terminal sources current (ITRIP) which is 10 μA
typically at room temperature, and the trip level is set to the OCL trip voltage VTRIP as shown in Equation 2.
(2)
The inductor current is monitored by the LL pin. The GND pin is used as the positive current sensing node and
the LL pin is used as the negative current sense node. The trip current, ITRIP has a 3000ppm/°C temperature
slope to compensate the temperature dependency of the RDS(on). For each device, ITRIP is also adjusted based on
the device-specific on-resistance measurement in production tests to eliminate the any OCP variation from
device to device.
As the comparison is made during the OFF state, VTRIP sets the valley level of the inductor current. Thus, the
load current at the overcurrent threshold, IOCP, can be calculated as shown in Equation 3.
where
• RTRIP is in kΩ(3)
In an overcurrent or short circuit condition, the current to the load exceeds the current to the output capacitor
thus the output voltage tends to decrease. Eventually, it crosses the undervoltage protection threshold and shuts
down. After a hiccup delay (16 ms with 0.7 ms sort-start), the controller restarts. If the overcurrent condition
remains, the procedure is repeated and the device enters hiccup mode.
For the TPS53318, the OCP threshold is internally clamped to 10.5 A. The RTRIP for TPS53318 should be less
than 150 kΩ.
Overvoltage and Undervoltage Protection
The TPS53318 and TPS53319 monitor the resistor divided feedback voltage to detect over and under voltage.
When the feedback voltage becomes lower than 70% of the target voltage, the UVP comparator output goes
high and an internal UVP delay counter begins counting. After 1 ms, the TPS53319 latches OFF both high-side
and low-side MOSFETs drivers. The controller restarts after a hiccup delay (16 ms with 0.7 ms soft-start). This
function is enabled 1.5-ms after the soft-start is completed.
When the feedback voltage becomes higher than 120% of the target voltage, the OVP comparator output goes
high and the circuit latches OFF the high-side MOSFET driver and latches ON the low-side MOSFET driver. The
output voltage decreases. Before the latch-off action for both the high-side and low-side drivers, the output
voltage must be pulled down below the UVP threshold voltage for a period of 1 ms. After the 1 ms period, the
drivers are latched off.
Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Links: TPS53318 TPS53319
= £
p ´ ´
SW
0
OUT
f
1
f
2 ESR C 4
( )=´ ´ OUT
1
H s
s ESR C
R1
R2
Voltage
Divider
+
VFB
+
0.6 V
PWM Control
Logic
and
Divider
L
ESR
COUT
VC
RLOAD
IIND IOUT
UDG-12051
IC
Switching Modulator
Output
Capacitor
VOUT
VIN
VIN
LL
TPS53318, TPS53319
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Redundant Overvoltage Protection (OVP)
The TPS53318 and TPS53319 have a redundant input for OVP protection. The ROVP pin senses the voltage
divided from output voltage and sends it to the OVP comparator. If this voltage is higher than 120% of the target
voltage, the overvoltage protection engages and the low-side FET is turned on. When the output voltage is lower
than the UVP threshold then the device latches off.
This redundant OVP function typically protects again the feedback loop open or VFB short to GND. The ROVP
pin has an internal 1.5-MΩpull-down resistor. If the redundent OVP feature is not needed then simply leave the
ROVP pin floating or connect it to GND.
UVLO Protection
The TPS53318 and TPS53319 use VREG undervoltage lockout protection (UVLO). When the VREG voltage is
lower than 3.95 V, the device shuts off. When the VREG voltage is higher than 4.2V, the device restarts. This is
a non-latch protection.
Thermal Shutdown
The TPS53318 and TPS53319 monitor the internal die temperature. If the temperature exceeds the threshold
value (typically 145°C), the device shuts down. When the temperature falls about 10°C below the threshold
value, the device will turn back on. This is a non-latch protection.
Small Signal Model
From small-signal loop analysis, a buck converter using D-CAP™ mode can be simplified as shown in Figure 44.
Figure 44. Simplified Modulator Model
The output voltage is compared with the internal reference voltage (ramp signal is ignored here for simplicity).
The PWM comparator determines the timing to turn on the high-side MOSFET. The gain and speed of the
comparator can be assumed high enough to keep the voltage at the beginning of each on cycle substantially
constant.
(4)
For loop stability, the 0-dB frequency, ƒ0, defined below need to be lower than 1/4 of the switching frequency.
(5)
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SLUSAY8B –JUNE 2012–REVISED MAY 2013
According to the equation above, the loop stability of D-CAPTM mode modulator is mainly determined by the
capacitor's chemistry. For example, specialty polymer capacitors (SP-CAP) have an output capacitance in the
order of several 100 µF and ESR in range of 10 mΩ. These makes ƒ0on the order of 100 kHz or less, creating a
stable loop. However, ceramic capacitors have an ƒ0at more than 700 kHz, and need special care when used
with this modulator. An application circuit for ceramic capacitor is described in the External Component Selection
Using All Ceramic Output Capacitors section.
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Product Folder Links: TPS53318 TPS53319
( ) ´
- -
= ´
IND ripple
OUT
I ESR
V 0.6
2
R1 R2
0.6
( )
( )
´ ´ - ´ ´ ´
= = = W
´
OUT SW SW
IND ripple
V 10mV (1 D) 10mV L f L f
ESR 0.6 V I 0.6 V 60
( ) ( )
( )
()
( )
- ´
= + ´
´ ´
IN OUT OUT
max
TRIP
IND peak SW IN
DS on max
V V V
V1
I32 R L f V
( )
( )
()
( ) ( )
( )
()
- ´ - ´
= ´ = ´
´ ´
IN OUT OUT IN OUT OUT
max max
SW IN OUT SW IN(max)
IND ripple max max
V V V V V V
1 3
LI f V I f V
TPS53318, TPS53319
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External Component Selection
The external components selection is a simple process when using organic semiconductors or special polymer
output capacitors.
1. SELECT OPERATION MODE AND SOFT-START TIME
Select operation mode and soft-start time using Table 1.
2. SELECT SWITCHING FREQUENCY
Select the switching frequency from 250 kHz to 1 MHz using Table 2.
3. CHOOSE THE INDUCTOR
The inductance value should be determined to give the ripple current of approximately 1/4 to 1/2 of maximum
output current. Larger ripple current increases output ripple voltage and improves signal-to-noise ratio and
helps ensure stable operation, but increases inductor core loss. Using 1/3 ripple current to maximum output
current ratio, the inductance can be determined by Equation 6.
(6)
The inductor requires a low DCR to achieve good efficiency. It also requires enough room above peak
inductor current before saturation. The peak inductor current can be estimated in Equation 7.
(7)
4. CHOOSE THE OUTPUT CAPACITOR(S)
When organic semiconductor capacitor(s) or specialty polymer capacitor(s) are used, for loop stability,
capacitance and ESR should satisfy Equation 5. For jitter performance, Equation 8 is a good starting point to
determine ESR.
where
• D is the duty factor.
• The required output ripple slope is approximately 10 mV per tSW (switching period) in terms of VFB terminal
voltage. (8)
5. DETERMINE THE VALUE OF R1 AND R2
The output voltage is programmed by the voltage-divider resistor, R1 and R2 shown in Figure 44. R1 is
connected between VFB pin and the output, and R2 is connected between the VFB pin and GND.
Recommended R2 value is from 10 kΩto 20 kΩ. Determine R1 using Equation 9.
(9)
22 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: TPS53318 TPS53319
-
= ´
OUT VFB
VFB
V V
R1 R2
V
+
= + INJ _ SW INJ _ OUT
VFB
V V
V 0.6 2
( )
( )
= ´ + ´ ´
IND ripple
INJ _ OUT IND ripple OUT SW
I
V ESR I 8 C f
-
= ´
´
IN OUT
INJ _ SW
SW
V V D
VR7 C1 f
´
> ´
´
OUT ON
L C t
N
R7 C1 2
( )
IN OUT OUT
TRIP OCP
SW IN
V V V
1
R I 12.3
2 L f V
æ ö
- ´
æ ö
= - ´ ´
ç ÷
ç ÷
ç ÷
´ ´
è ø
è ø
TPS53318, TPS53319
www.ti.com
SLUSAY8B –JUNE 2012–REVISED MAY 2013
6. CHOOSE THE OVERCURRENT SETTING RESISTOR
The overcurrent setting resistor, RTRIP, can be determined by Equation 10.
where
• RTRIP is in kΩ(10)
External Component Selection Using All Ceramic Output Capacitors
When a ceramic output capacitor is used, the stability criteria in Equation 5 cannot be satisfied. The ripple
injection approach as shown in Figure 2 is implemented to increase the ripple on the VFB pin and make the
system stable. In addition to the selections made using steps 1 through step 6 in the External Component
Selection section, the ripple injection components must be selected. The C2 value can be fixed at 1 nF. The
value of C1 can be selected between 10 nF to 200 nF.
where
• N is the coefficient to account for L and COUT variation (11)
N is also used to provide enough margin for stability. It is recommended N=2 for VOUT ≤1.8 V and N=4 for VOUT
≥3.3 V or when L ≤250 nH. The higher VOUT needs a higher N value because the effective output capacitance is
reduced significantly with higher DC bias. For example, a 6.3-V, 22-µF ceramic capacitor may have only 8 µF of
effective capacitance when biased at 5 V.
Because the VFB pin voltage is regulated at the valley, the increased ripple on the VFB pin causes the increase
of the VFB DC value. The AC ripple coupled to the VFB pin has two components, one coupled from SW node
and the other coupled from the VOUT pin and they can be calculated using Equation 12 and Equation 13 when
neglecting the output voltage ripple caused by equivalent series inductance (ESL).
(12)
(13)
It is recommended that VINJ_SW to be less than 50 mV. If the calculated VINJ_SW is higher than 50 mV, then other
parameters need to be adjusted to reduce it. For example, COUT can be increased to satisfy Equation 11 with a
higher R7 value, thereby reducing VINJ_SW.
The DC voltage at the VFB pin can be calculated by Equation 14:
(14)
And the resistor divider value can be determined by Equation 15:
(15)
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LAYOUT CONSIDERATIONS
Certain points must be considered before beginining a design using the TPS53318 or TPS53319.
• The power components (including input/output capacitors, inductor and TPS53318 or TPS53319) should be
placed on one side of the PCB (solder side). At least one inner plane should be inserted, connected to
ground, in order to shield and isolate the small signal traces from noisy power lines.
• All sensitive analog traces and components such as VFB, PGOOD, TRIP, MODE and RF should be placed
away from high-voltage switching nodes such as LL, VBST to avoid coupling. Use internal layer(s) as ground
plane(s) and shield feedback trace from power traces and components.
• Place the VIN decoupling capacitors as close to the VIN and PGND pins as possible to minimize the input AC
current loop.
• Because the TPS53319 controls output voltage referring to voltage across VOUT capacitor, the top-side
resistor of the voltage divider should be connected to the positive node of the VOUT capacitor. The GND of
the bottom side resistor should be connected to the GND pad of the device. The trace from these resistors to
the VFB pin should be short and thin.
• Place the frequency setting resistor (RF), OCP setting resistor (RTRIP) and mode setting resistor (RMODE) as
close to the device as possible. Use the common GND via to connect them to GND plane if applicable.
• Place the VDD and VREG decoupling capacitors as close to the device as possible. Ensure to provide GND
vias for each decoupling capacitor and make the loop as small as possible.
• The PCB trace defined as switch node, which connects the LL pins and high-voltage side of the inductor,
should be as short and wide as possible.
• Connect the ripple injection VOUT signal (VOUT side of the C1 capacitor in Figure 2) from the terminal of
ceramic output capacitor. The AC coupling capacitor (C2 in Figure 2) should be placed near the device, and
R7 and C1 can be placed near the power stage.
• Use separated vias or trace to connect LL node to snubber, boot strap capacitor and ripple injection resistor.
Do not combine these connections.
24 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: TPS53318 TPS53319
To GND Plane
Bottom side
components and trace
Bottom side
component
and trace
GND shape
Keep VFB trace short and
away from noisy signals
VIN shape VOUT shape
LL shape
MODE
TRIP
RF
VDD
VREG
PGOOD
EN
VFB
VOUT
GND
Bottom side
components and trace
VBST
UDG-13111
TPS53318, TPS53319
www.ti.com
SLUSAY8B –JUNE 2012–REVISED MAY 2013
Figure 45. Layout Recommendation
Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback 25
Product Folder Links: TPS53318 TPS53319
TPS53318, TPS53319
SLUSAY8B –JUNE 2012–REVISED MAY 2013
www.ti.com
REVISION HISTORY
Changes from Original (JUNE 2012) to Revision A Page
• Changed "<100 μA Shut Down Current" to "<110 μA Shut Down Current" in FEATURES ................................................. 1
• Changed "Green (RoHS and no Pb/Br)" to "Pb-Free (RoHS Exempt)" in ORDERING INFORMATION table .................... 2
Changes from Revision A (AUGUST 2012) to Revision B Page
• Added clarity to Overvoltage and Undervoltage Protection section ................................................................................... 19
• Changed updated Figure 45 ............................................................................................................................................... 25
26 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: TPS53318 TPS53319
PACKAGE OPTION ADDENDUM
www.ti.com 23-Apr-2013
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Top-Side Markings
(4)
Samples
TPS53318DQPR ACTIVE SON DQP 22 2500 Pb-Free (RoHS
Exempt) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 53318DQP
TPS53318DQPT ACTIVE SON DQP 22 250 Pb-Free (RoHS
Exempt) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 53318DQP
TPS53319DQPR ACTIVE SON DQP 22 2500 Pb-Free (RoHS
Exempt) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 53319DQP
TPS53319DQPT ACTIVE SON DQP 22 250 Pb-Free (RoHS
Exempt) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 53319DQP
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 23-Apr-2013
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS53318DQPR SON DQP 22 2500 330.0 12.4 5.3 6.3 1.8 8.0 12.0 Q1
TPS53318DQPT SON DQP 22 250 180.0 12.4 5.3 6.3 1.8 8.0 12.0 Q1
TPS53319DQPR SON DQP 22 2500 330.0 12.4 5.3 6.3 1.8 8.0 12.0 Q1
TPS53319DQPT SON DQP 22 250 180.0 12.4 5.3 6.3 1.8 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 13-May-2013
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS53318DQPR SON DQP 22 2500 367.0 367.0 35.0
TPS53318DQPT SON DQP 22 250 210.0 185.0 35.0
TPS53319DQPR SON DQP 22 2500 367.0 367.0 35.0
TPS53319DQPT SON DQP 22 250 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 13-May-2013
Pack Materials-Page 2
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