SLOS154B− DECEMBER 1995 − REVISED JUNE 2005
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DInput Offset Voltage Drift ...Typically
0.1 µV/Month, Including the First 30 Days
DWide Range of Supply Voltages Over
Specified Temperature Range:
0°C to 70°C...3 V to 16 V
−40°C to 85°C...4 V to 16 V
−55°C to 125°C...5 V to 16 V
DSingle-Supply Operation
DCommon-Mode Input Voltage Range
Extends Below the Negative Rail (C-Suffix
and I-Suffix Types)
DLow Noise . . . 68 nV/√Hz Typically at
f = 1 kHz
DOutput Voltage Range Includes Negative
Rail
DHigh Input Impedance ...10
12 Ω Typ
DESD-Protection Circuitry
DSmall-Outline Package Option Also
Available in Tape and Reel
DDesigned-In Latch-Up Immunity
description
The TLC27L1 operational amplifier combines a wide range of input offset-voltage grades with low offset-voltage
drift and high input impedance. In addition, the TLC27L1 is a low-bias version of the TLC271 programmable
amplifier. These devices use the Texas Instruments silicon-gate LinCMOS technology, which provides
offset-voltage stability far exceeding the stability available with conventional metal-gate processes.
Three offset-voltage grades are available (C-suffix and I-suffix types), ranging from the low-cost TLC27L1
(10 mV) t o the TLC27L1B (2 mV) low-of fset version. The extremely high input impedance and low bias currents,
in conjunction with good common-mode rejection and supply voltage rejection, make these devices a good
choice for new state-of-the-art designs as well as for upgrading existing designs.
In general, many features associated with bipolar technology are available in LinCMOS operational amplifiers,
without the power penalties of bipolar technology. General applications such as transducer interfacing, analog
calculations, amplifier blocks, active filters, and signal buffering are all easily designed with the TLC27L1. The
devices also exhibit low-voltage single-supply operation, making them ideally suited for remote and
inaccessible battery-powered applications. The common-mode input-voltage range includes the negative rail.
The device inputs and output are designed to withstand −100-mA surge currents without sustaining latch-up.
The TLC27L1 incorporates internal electrostatic-discharge (ESD) protection circuits that prevent functional
failures at voltages up to 2000 V as tested under MIL-STD-883C, Method 3015.2; however, care should be
exercised in handling these devices as exposure to ESD may result in the degradation of the device parametric
performance.
AVAILABLE OPTIONS
PACKAGE
TAVIOmax
AT 25°CSMALL
OUTLINE
(D)
PLASTIC
DIP
(P)
2 mV
TLC27L1BCD
TLC27L1BCP
0
°
C to 70
°
C
2 mV
5 mV
TLC27L1BCD
TLC27L1ACD
TLC27L1BCP
TLC27L1ACP
0C to 70 C
5 mV
10 mV
TLC27L1ACD
TLC27L1CD
TLC27L1ACP
TLC27L1CP
2 mV
TLC27L1BID
TLC27L1BIP
−40
°
C to 85
°
C
2 mV
5 mV
TLC27L1BID
TLC27L1AID
TLC27L1BIP
TLC27L1AIP
−40 C to 85 C
5 mV
10 mV
TLC27L1AID
TLC27L1ID
TLC27L1AIP
TLC27L1IP
−55°C to 125°C10 mV TLC27L1MD TLC27L1MP
The D package is available taped and reeled. Add R suffix to the device type
(e.g., TLC27L1BCDR).
Copyright 1995 − 2005, Texas Instruments Incorporated
!"# $"%&! '#(
'"! ! $#!! $# )# # #* "#
'' +,( '"! $!#- '# #!#&, !&"'#
#- && $##(
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
LinCMOS is a trademark of Texas Instruments.
1
2
3
4
8
7
6
5
OFFSET N1
IN −
IN +
GND
VDD
VDD
OUT
OFFSET N2
D OR P PACKAGE
(TOP VIEW)
SLOS154B− DECEMBER 1995 − REVISED JUNE 2005
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description (continued)
The C-suffix devices are characterized for operation from 0°C to 70°C. The I-suffix devices are characterized
for operation from −40°C to 85°C. The M-suffix devices are characterized for operation over the full military
temperature range of −55°C to 125°C.
equivalent schematic
P3
P1
R1
IN −
IN +
P2 R2
P4 R6
N5
R5 C1
N3
N2N1
R3 D1
R4
D2 N4
OFFSET
N1 N2
OFFSET OUT GND
R7
N6
N10
N7
N9
N13
N12
N11
P12
P11
P10
P7A P8
P9A
P9B
P7B
P6BP6A
P5
V
DD
SLOS154B− DECEMBER 1995 − REVISED JUNE 2005
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absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage, VDD (see Note 1) 18 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Differential input voltage, VID (see Note 2) ±VDD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (any input) −0.3 V to VDD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input current, II ±5 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output current, IO ±30 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Duration of short-circuit current at (or below) 25°C (see Note 3) Unlimited. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature, TA: C suffix 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I suffix −40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
M suffix −55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Case temperature for 60 seconds, TC: FK package 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D or P package 260°C. . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential voltages, are with respect to network ground.
2. Differential voltages are at IN+ with respect to IN−.
3. The output may be shorted to either supply. Temperature and/or supply voltages must be limited to ensure that the maximum
dissipation rating is not exceeded (see application section).
DISSIPATION RATING TABLE
PACKAGE TA ≤ 25°C
POWER RATING DERATING FACTOR
ABOVE TA = 25°CTA = 70°C
POWER RATING TA = 85°C
POWER RATING TA = 125°C
POWER RATING
D725 mW 5.8 mW/°C464 mW 377 mW 145 mW
P1000 mW 8.0 mW/°C640 mW 520 mW 200 mW
recommended operating conditions
C SUFFIX I SUFFIX M SUFFIX
UNIT
MIN MAX MIN MAX MIN MAX
UNIT
Supply voltage, VDD 3 16 4 16 5 16 V
Common-mode input voltage, VIC
VDD = 5 V −0.2 3.5 −0.2 3.5 0 3.5
V
Common-mode input voltage, VIC VDD = 10 V −0.2 8.5 −0.2 8.5 0 8.5 V
Operating free-air temperature, TA0 70 −40 85 −55 125 °C
SLOS154B− DECEMBER 1995 − REVISED JUNE 2005
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics at specified free-air temperature (unless otherwise noted)
TEST
TLC27L1C, TLC27L1AC, TLC27L1BC
PARAMETER
TEST
CONDITIONS
T
A
†VDD = 5 V VDD = 10 V
UNIT
PARAMETER
CONDITIONS
TA†
MIN TYP MAX MIN TYP MAX
UNIT
TLC27L1C
25°C 1.1 10 1.1 10
TLC27L1C
VO = 1.4 V,
Full range 12 12
VIO
Input offset voltage
TLC27L1AC
V
O
= 1.4 V,
VIC = 0 V,
25°C 0.9 5 0.9 5
mV
VIO Input offset voltage TLC27L1AC
VIC = 0 V,
RS = 50 Ω,
RI = 1 MΩ
Full range 6.5 6.5 mV
TLC27L1BC
RS = 50 ,
RI = 1 MΩ25°C 0.24 2 0.26 2
TLC27L1BC Full range 3 3
αVIO Average temperature coefficient of
input offset voltage 25°C to
70°C1.1 1 µV/°C
IIO
Input offset current (see Note 4)
VO = VDD/2,
25°C 0.1 60 0.1 60
pA
IIO Input offset current (see Note 4)
VO = VDD/2,
VIC = VDD/2 70°C 7 300 8 300 pA
IIB
Input bias current (see Note 4)
VO = VDD/2,
25°C 0.6 60 0.7 60
pA
IIB Input bias current (see Note 4)
VO = VDD/2,
VIC = VDD/2 70°C 40 600 50 600 pA
VICR
Common-mode input
25°C−0.2
to
4
−0.3
to
4.2
−0.2
to
9
−0.3
to
9.2 V
VICR
Common-mode input
voltage range (see Note 5) Full range −0.2
to
3.5
−0.2
to
8.5 V
VID = 100 mV,
25°C 3.2 4.1 8 8.9
V
OH
High-level output voltage VID = 100 mV,
RL= 1 MΩ
0°C 3 4.1 7.8 8.9 V
VOH
High-level output voltage
RL= 1 MΩ
70°C 3 4.2 7.8 8.9
V
VID = −100 mV,
25°C 0 50 0 50
V
OL
Low-level output voltage VID = −100 mV,
IOL = 0
0°C 0 50 0 50 mV
VOL
Low-level output voltage
IOL = 0
70°C 0 50 0 50
mV
Large-signal differential
RL= 1 MΩ
25°C 50 520 50 870
A
VD
Large-signal differential
voltage amplification
RL= 1 MΩ,
See Note 6
0°C 50 700 50 1030 V/mV
AVD
voltage amplification
See Note 6
70°C 50 380 50 660
V/mV
25°C 65 94 65 97
CMRR Common-mode rejection ratio V
IC
= V
ICR
min 0°C 60 95 60 97 dB
CMRR
Common-mode rejection ratio
VIC = VICRmin
70°C 60 95 60 97
dB
Supply-voltage rejection ratio
VDD = 5 V to 10 V,
25°C 70 97 70 97
k
SVR
Supply-voltage rejection ratio
(∆VDD/∆VIO)
VDD = 5 V to 10 V,
VO = 1.4 V
0°C 60 97 60 97 dB
kSVR
(∆VDD/∆VIO)
VO = 1.4 V
70°C 60 98 60 98
dB
II(SEL) Input current (BIAS SELECT) VI(SEL) = VDD 25°C 65 95 nA
VO = VDD/2,
25°C 10 17 14 23
I
DD
Supply current
VO = VDD/2,
V
IC
= V
DD
/2,
No load
0°C 12 21 18 33 µA
IDD
Supply current
VIC = VDD/2,
No load 70°C 8 14 11 20
µA
†Full range is 0°C to 70°C.
NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically.
5. This range also applies to each input individually.
6. At VDD = 5 V, VO = 0.25 V to 2 V; at VDD = 10 V, VO = 1 V to 6 V.
SLOS154B− DECEMBER 1995 − REVISED JUNE 2005
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics at specified free-air temperature (unless otherwise noted)
TEST
TLC27L1I, TLC27L1AI, TLC27L1BI
PARAMETER
TEST
CONDITIONS
T
A
†VDD = 5 V VDD = 10 V
UNIT
PARAMETER
CONDITIONS
TA†
MIN TYP MAX MIN TYP MAX
UNIT
TLC27L1I
25°C 1.1 10 1.1 10
TLC27L1I
VO = 1.4 V,
Full range 13 13
VIO
Input offset voltage
TLC27L1AI
V
O
= 1.4 V,
VIC = 0 V,
25°C 0.9 5 0.9 5
mV
VIO Input offset voltage TLC27L1A
I
VIC = 0 V,
RS = 50 Ω,
RL = 1 MΩ
Full range 7 7 mV
TLC27L1BI
RS = 50 ,
RL = 1 MΩ25°C 0.24 2 0.26 2
TLC27L1B
I
Full range 3.5 3.5
αVIO Average temperature coefficient
of input offset voltage 25°C to
85°C1.1 1 µV/°C
IIO
Input offset current (see Note 4)
VO = VDD/2,
25°C 0.1 60 0.1 60
pA
IIO Input offset current (see Note 4)
VO = VDD/2,
VIC = VDD/2 85°C 24 1000 26 1000 pA
IIB
Input bias current (see Note 4)
VO = VDD/2,
25°C 0.6 60 0.7 60
pA
IIB Input bias current (see Note 4)
VO = VDD/2,
VIC = VDD/2 85°C 200 2000 220 2000 pA
VICR
Common-mode input
25°C−0.2
to
4
−0.3
to
4.2
−0.2
to
9
−0.3
to
9.2 V
VICR
Common-mode input
voltage range (see Note 5) Full range −0.2
to
3.5
−0.2
to
8.5 V
VID = 100 mV,
25°C 3 4.1 8 8.9
V
OH
High-level output voltage VID = 100 mV,
RL= 1 MΩ
−40°C 3 4.1 7.8 8.9 V
VOH
High-level output voltage
RL= 1 MΩ
85°C 3 4.2 7.8 8.9
V
VID = −100 mV,
25°C 0 50 0 50
V
OL
Low-level output voltage VID = −100 mV,
IOL = 0
−40°C 0 50 0 50 mV
VOL
Low-level output voltage
IOL = 0
85°C 0 50 0 50
mV
Large-signal differential
RL= 1 MΩ
25°C 50 520 50 870
A
VD
Large-signal differential
voltage amplification
RL= 1 MΩ
See Note 6
−40°C 50 900 50 1550 V/mV
AVD
voltage amplification
See Note 6
85°C 50 330 50 585
V/mV
25°C 65 94 65 97
CMRR Common-mode rejection ratio V
IC
= V
ICR
min −40°C 60 95 60 97 dB
CMRR
Common-mode rejection ratio
VIC = VICRmin
85°C 60 95 60 98
dB
Supply-voltage rejection ratio
VDD = 5 V to 10 V,
25°C 70 97 70 97
k
SVR
Supply-voltage rejection ratio
(∆VDD/∆VIO)
VDD = 5 V to 10 V,
VO = 1.4 V
−40°C 60 97 60 97 dB
kSVR
(∆VDD/∆VIO)
VO = 1.4 V
85°C 60 98 60 98
dB
II(SEL) Input current (BIAS SELECT) VI(SEL) = VDD 25°C 65 95 nA
VO = VDD/2,
25°C 10 17 14 23
I
DD
Supply current
VO = VDD/2,
V
IC
= V
DD
/2,
No load
−40°C 16 27 25 43 µA
IDD
Supply current
VIC = VDD/2,
No load 85°C 17 13 10 18
µA
†Full range is −40 to 85°C.
NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically.
5. This range also applies to each input individually.
6. At VDD = 5 V, VO = 0.25 V to 2 V; at VDD = 10 V, VO = 1 V to 6 V.
SLOS154B− DECEMBER 1995 − REVISED JUNE 2005
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics at specified free-air temperature (unless otherwise noted)
TEST
TLC27L1M
PARAMETER
TEST
CONDITIONS
T
A
†VDD = 5 V VDD = 10 V
UNIT
PARAMETER
CONDITIONS
TA†
MIN TYP MAX MIN TYP MAX
UNIT
VIO
Input offset voltage
VO = 1.4 V,
VIC = 0 V, 25°C 1.1 10 1.1 10
mV
VIO Input offset voltage RS = 50 Ω,
RL = 1 MΩFull range 12 12 mV
αVIO Average temperature coefficient
of input offset voltage 25°C to
125°C1.4 1.4 µV/°C
IIO
Input offset current (see Note 4)
VO = VDD/2,
25°C 0.1 60 0.1 60 pA
IIO Input offset current (see Note 4)
VO = VDD/2,
VIC = VDD/2 125°C 1.4 15 1.8 15 nA
IIB
Input bias current (see Note 4)
VO = VDD/2,
25°C 0.6 60 0.7 60 pA
IIB Input bias current (see Note 4)
VO = VDD/2,
VIC = VDD/2 125°C 9 35 10 35 nA
VICR
Common-mode input
25°C0
to
4
−0.3
to
4.2
0
to
9
−0.3
to
9.2 V
VICR
Common-mode input
voltage range (see Note 5) Full range 0
to
3.5
0
to
8.5 V
VID = 100 mV,
25°C 3.2 4.1 8 8.9
V
OH
High-level output voltage VID = 100 mV,
RL= 1 MΩ
−55°C 3 4.1 7.8 8.8 V
VOH
High-level output voltage
RL= 1 MΩ
125°C 3 4.2 7.8 9
V
VID = −100 mV,
25°C 0 50 0 50
V
OL
Low-level output voltage VID = −100 mV,
IOL = 0
−55°C 0 50 0 50 mV
VOL
Low-level output voltage
IOL = 0
125°C 0 50 0 50
mV
Large-signal differential
RL= 1 MΩ
25°C 50 520 50 870
A
VD
Large-signal differential
voltage amplification
RL= 1 MΩ,
See Note 6
−55°C 25 1000 25 1775 V/mV
AVD
voltage amplification
See Note 6
125°C 25 200 25 380
V/mV
25°C 65 94 65 97
CMRR Common-mode rejection ratio V
IC
= V
ICR
min −55°C 60 95 60 97 dB
CMRR
Common-mode rejection ratio
VIC = VICRmin
125°C 60 85 60 91
dB
Supply-voltage rejection ratio
VDD = 5 V to 10 V,
25°C 70 97 70 97
k
SVR
Supply-voltage rejection ratio
(∆VDD/∆VIO)
VDD = 5 V to 10 V,
VO = 1.4 V
−55°C 60 97 60 97 dB
kSVR
(∆VDD/∆VIO)
VO = 1.4 V
125°C 60 98 60 98
dB
II(SEL) Input current (BIAS SELECT) VI(SEL) = VDD 25°C 65 95 nA
VO = VDD/2,
25°C 10 17 14 23
I
DD
Supply current
VO = VDD/2,
V
IC
= V
DD
/2,
No load
−55°C 17 30 28 48 µA
IDD
Supply current
VIC = VDD/2,
No load 125°C 7 12 9 15
µA
†Full range is −55°C to 125°C.
NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically.
5. This range also applies to each input individually.
6. At VDD = 5 V, VO = 0.25 V to 2 V; at VDD = 10 V, VO = 1 V to 6 V.
SLOS154B− DECEMBER 1995 − REVISED JUNE 2005
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
operating characteristics at specified free-air temperature, VDD = 5 V
PARAMETER TEST CONDITIONS TA
TLC27L1C,
TLC27L1AC,
TLC27L1BC UNIT
MIN TYP MAX
25°C 0.03
R = 1 M ,
V
I(PP)
= 1 V 0°C 0.04
SR
Slew rate at unity gain
RL = 1 MΩ,
CL = 20 pF,
VI(PP) = 1 V
70°C 0.03
V/ s
SR Slew rate at unity gain
L
C
L
= 20 pF,
See Figure 33
25°C 0.03 V/µs
See Figure 33
V
I(PP)
= 2.5 V 0°C 0.03
VI(PP) = 2.5 V
70°C 0.02
VnEquivalent input noise voltage f = 1 kHz,
See Figure 34 RS = 20 Ω,25°C 68 nV/√Hz
VO = VOH,
CL = 20 pF,
25°C 5
B
OM
Maximum output-swing bandwidth VO = VOH,
RL = 1 MΩ,
CL = 20 pF,
See Figure 33
0°C 6 kHz
BOM
Maximum output-swing bandwidth
RL = 1 MΩ,
See Figure 33
70°C 4.5
kHz
VI = 10 mV,
CL = 20 pF,
25°C 85
B
1
Unity-gain bandwidth VI = 10 mV,
See Figure 35
CL = 20 pF, 0°C100 kHz
B1
Unity-gain bandwidth
See Figure 35
70°C 65
kHz
VI = 10 mV,
f = B1,
25°C 34°
φ
m
Phase margin VI = 10 mV,
CL = 20 pF,
f = B1,
See Figure 35
0°C 36°
φm
Phase margin
CL = 20 pF,
See Figure 35
70°C 30°
operating characteristics at specified free-air temperature, VDD = 10 V
PARAMETER TEST CONDITIONS TA
TLC27L1C,
TLC27L1AC,
TLC27L1BC UNIT
MIN TYP MAX
25°C 0.05
R = 1 M ,
V
I(PP)
= 1 V 0°C 0.05
SR
Slew rate at unity gain
RL = 1 MΩ,
CL = 20 pF,
VI(PP) = 1 V
70°C 0.04
V/ s
SR Slew rate at unity gain
L
C
L
= 20 pF,
See Figure 33
25°C 0.04 V/µs
See Figure 33
V
I(PP)
= 5.5 V 0°C 0.05
VI(PP) = 5.5 V
70°C 0.04
VnEquivalent input noise voltage f = 1 kHz,
See Figure 34 RS = 20 Ω,25°C 68 nV/√Hz
VO = VOH,
CL = 20 pF,
25°C 1
B
OM
Maximum output-swing bandwidth VO = VOH,
RL = 1 MΩ,
CL = 20 pF,
See Figure 33
0°C 1.3 kHz
BOM
Maximum output-swing bandwidth
RL = 1 MΩ,
See Figure 33
70°C 0.9
kHz
VI = 10 mV,
CL = 20 pF,
25°C110
B
1
Unity-gain bandwidth VI = 10 mV,
See Figure 35
CL = 20 pF, 0°C125 kHz
B1
Unity-gain bandwidth
See Figure 35
70°C 90
kHz
VI = 10 mV,
f = B1,
25°C 38°
φ
m
Phase margin VI = 10 mV,
CL = 20 pF,
f = B1,
See Figure 35
0°C 40°
φm
Phase margin
CL = 20 pF,
See Figure 35
70°C 34°
SLOS154B− DECEMBER 1995 − REVISED JUNE 2005
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
operating characteristics at specified free-air temperature, VDD = 5 V
PARAMETER TEST CONDITIONS TA
TLC27L1I,
TLC27L1AI,
TLC27L1BI UNIT
MIN TYP MAX
25°C 0.03
R = 1 M ,
V
I(PP)
= 1 V −40°C 0.04
SR
Slew rate at unity gain
RL = 1 MΩ,
CL = 20 pF,
VI(PP) = 1 V
85°C 0.03
V/ s
SR Slew rate at unity gain
L
C
L
= 20 pF,
See Figure 33
25°C 0.03 V/µs
See Figure 33
V
I(PP)
= 2.5 V −40°C 0.04
VI(PP) = 2.5 V
85°C 0.02
VnEquivalent input noise voltage f = 1 kHz,
See Figure 34 RS = 20 Ω,25°C 68 nV/√Hz
VO = VOH,
CL = 20 pF,
25°C 5
B
OM
Maximum output-swing bandwidth VO = VOH,
RL = 1 MΩ,
CL = 20 pF,
See Figure 33
−40°C 7 kHz
BOM
Maximum output-swing bandwidth
RL = 1 MΩ,
See Figure 33
85°C 4
kHz
VI = 10 mV,
CL = 20 pF,
25°C 85
B
1
Unity-gain bandwidth VI = 10 mV,
See Figure 35
CL = 20 pF, −40°C130 MHz
B1
Unity-gain bandwidth
See Figure 35
85°C 55
MHz
VI = 10 mV,
f = B1,
25°C 34°
φ
m
Phase margin VI = 10 mV,
CL = 20 pF,
f = B1,
See Figure 35
−40°C 38°
φm
Phase margin
CL = 20 pF,
See Figure 35
85°C 28°
operating characteristics at specified free-air temperature, VDD = 10 V
PARAMETER TEST CONDITIONS TA
TLC27L1C,
TLC27L1AC,
TLC27L1BC UNIT
MIN TYP MAX
25°C 0.05
R = 1 M ,
V
I(PP)
= 1 V −40°C 0.06
SR
Slew rate at unity gain
RL = 1 MΩ,
CL = 20 pF,
VI(PP) = 1 V
85°C 0.03
V/ s
SR Slew rate at unity gain
L
C
L
= 20 pF,
See Figure 33
25°C 0.04 V/µs
See Figure 33
V
I(PP)
= 5.5 V −40°C 0.05
VI(PP) = 5.5 V
85°C 0.03
VnEquivalent input noise voltage f = 1 kHz,
See Figure 34 RS = 20 Ω,25°C 68 nV/√Hz
VO = VOH,
CL = 20 pF,
25°C 1
B
OM
Maximum output-swing bandwidth VO = VOH,
RL = 1 MΩ,
CL = 20 pF,
See Figure 33
−40°C 1.4 kHz
BOM
Maximum output-swing bandwidth
RL = 1 MΩ,
See Figure 33
85°C 0.8
kHz
VI = 10 mV,
CL = 20 pF,
25°C110
B
1
Unity-gain bandwidth VI = 10 mV,
See Figure 35
CL = 20 pF, −40°C155 MHz
B1
Unity-gain bandwidth
See Figure 35
85°C 80
MHz
VI = 10 mV,l
f = B1,
25°C 38°
φ
m
Phase margin VI = 10 mV,l
CL = 20 pF,
f = B1,
See Figure 35
−40°C 42°
φm
Phase margin
CL = 20 pF,
See Figure 35
85°C 32°
SLOS154B− DECEMBER 1995 − REVISED JUNE 2005
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
operating characteristics at specified free-air temperature, VDD = 5 V
PARAMETER
TEST CONDITIONS
TA
TLC27L1M
UNIT
PARAMETER
TEST CONDITIONS
T
AMIN TYP MAX
UNIT
25°C 0.03
R = 1 M ,
V
I(PP)
= 1 V −55°C 0.04
SR
Slew rate at unity gain
RL = 1 MΩ,
CL = 20 pF,
VI(PP) = 1 V
125°C 0.02
V/ s
SR Slew rate at unity gain
L
C
L
= 20 pF,
See Figure 33
25°C 0.03 V/µs
See Figure 33
V
I(PP)
= 2.5 V −55°C 0.04
VI(PP) = 2.5 V
125°C 0.02
VnEquivalent input noise voltage f = 1 kHz,
See Figure 34 RS = 20 Ω,25°C 68 nV/√Hz
VO = VOH,
CL = 20 pF,
25°C 5
B
OM
Maximum output-swing bandwidth VO = VOH,
RL = 1 MΩ,
CL = 20 pF,
See Figure 33
−55°C 8 kHz
BOM
Maximum output-swing bandwidth
RL = 1 MΩ,
See Figure 33
125°C 3
kHz
VI = 10 mV,
CL = 20 pF,
25°C 85
B
1
Unity-gain bandwidth VI = 10 mV,
See Figure 35
CL = 20 pF, −55°C140 kHz
B1
Unity-gain bandwidth
See Figure 35
125°C 45
kHz
VI = 10 mV,
f = B1,
25°C 34°
φ
m
Phase margin VI = 10 mV,
CL = 20 pF,
f = B1,
See Figure 35
−55°C 39°
φm
Phase margin
CL = 20 pF,
See Figure 35
125°C 25°
operating characteristics at specified free-air temperature, VDD = 10 V
PARAMETER
TEST CONDITIONS
TA
TLC27L1M
UNIT
PARAMETER
TEST CONDITIONS
T
AMIN TYP MAX
UNIT
25°C 0.05
R = 1 M ,
V
I(PP)
= 1 V −55°C 0.06
SR
Slew rate at unity gain
RL = 1 MΩ,
CL = 20 pF,
VI(PP) = 1 V
125°C 0.03
V/ s
SR Slew rate at unity gain
L
C
L
= 20 pF,
See Figure 33
25°C 0.04 V/µs
See Figure 33
V
I(PP)
= 5.5 V −55°C 0.06
VI(PP) = 5.5 V
125°C 0.03
VnEquivalent input noise voltage f = 1 kHz,
See Figure 34 RS = 20 Ω,25°C 68 nV/√Hz
VO = VOH,
CL = 20 pF,
25°C 1
B
OM
Maximum output-swing bandwidth VO = VOH,
RL = 1 MΩ,
CL = 20 pF,
See Figure 33
−55°C 1.5 kHz
BOM
Maximum output-swing bandwidth
RL = 1 MΩ,
See Figure 33
125°C 0.7
kHz
VI = 10 mV,
CL = 20 pF,
25°C110
B
1
Unity-gain bandwidth VI = 10 mV,
See Figure 35
CL = 20 pF, −55°C165 kHz
B1
Unity-gain bandwidth
See Figure 35
125°C 70
kHz
VI = 10 mV,
f = B1,
25°C 38°
φ
m
Phase margin VI = 10 mV,
CL = 20 pF,
f = B1,
See Figure 35
−55°C 43°
φm
Phase margin
CL = 20 pF,
See Figure 35
125°C 29°
SLOS154B− DECEMBER 1995 − REVISED JUNE 2005
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
VIO Input offset voltage Distribution 1, 2
αVIO Temperature coefficient Distribution 3, 4
vs High-level output current
5, 6
VOH
High-level output voltage
vs High-level output current
vs Supply voltage
5, 6
7
VOH
High-level output voltage
vs Supply voltage
vs Free-air temperature
7
8
vs Common-mode input voltage
9, 10
VOL
Low-level output voltage
vs Common-mode input voltage
vs Differential input voltage
9, 10
11
VOL Low-level output voltage
vs Differential input voltage
vs Free-air temperature
11
12
OL
vs Free-air temperature
vs Low-level output current
12
13, 14
vs Supply voltage
15
AVD
Large-signal differential voltage amplification
vs Supply voltage
vs Free-air temperature
15
16
AVD
Large-signal differential voltage amplification
vs Free-air temperature
vs Frequency
16
27, 28
IIB Input bias current vs Free-air temperature 17
IIO Input offset current vs Free-air temperature 17
VIMaximum input voltage vs Supply voltage 18
IDD
Supply current
vs Supply voltage
19
IDD Supply current
vs Supply voltage
vs Free-air temperature
19
20
SR
Slew rate
vs Supply voltage
21
SR Slew rate
vs Supply voltage
vs Free-air temperature
21
22
Bias-select current vs Supply voltage 23
VO(PP) Maximum peak-to-peak output voltage vs Frequency 24
B1
Unity-gain bandwidth
vs Free-air temperature
25
B1Unity-gain bandwidth
vs Free-air temperature
vs Supply voltage
25
26
vs Supply voltage
29
φm
Phase margin
vs Supply voltage
vs Free-air temperature
29
30
φm
Phase margin
vs Free-air temperature
vs Capacitive load
30
31
VnEquivalent input noise voltage vs Frequency 32
Phase shift vs Frequency 27, 28
SLOS154B− DECEMBER 1995 − REVISED JUNE 2005
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS†
Figure 1
−5
0
Percentage of Units − %
VIO − Input Offset Voltage − mV 5
70
−4 −3 −2 −1 0 1 2 3 4
10
20
30
40
50
60
DISTRIBUTION OF TLC27L1
INPUT OFFSET VOLTAGE
VDD = 5 V
TA = 25°C
P Package
ÏÏÏÏÏÏÏÏÏÏÏÏ
905 Amplifiers Tested From 6 W afer Lots
Figure 2
60
50
40
30
20
10
43210−1−2−3−4
70
5
VIO − Input Offset Voltage − mV
Percentage of Units − %
0−5
DISTRIBUTION OF TLC27L1
INPUT OFFSET VOLTAGE
P Package
TA = 25°C
VDD = 10 V
905 Amplifiers Tested From 6 W afer Lots
Figure 3
60
50
40
30
20
10
86420−2−4−6−8
70
10
Percentage of Units − %
0−10
DISTRIBUTION OF TLC27L1
INPUT OFFSET VOLTAGE
TEMPERATURE COEFFICIENT
αVIO − Temperature Coefficient − µV/°C
(1) 12.1 µV/°C
(1) 19.2 µV/°C
Outliers:
P Package
TA = 25°C to 125°C
VDD = 5 V
356 Amplifiers Tested From 8 W afer Lots
Figure 4
−10
0
Percentage of Units − %
αVIO − Temperature Coefficient − µV/°C10
70
−8 −6 −4 −2 0 2 4 6 8
10
20
30
40
50
60
DISTRIBUTION OF TLC27L1
INPUT OFFSET VOLTAGE
TEMPERATURE COEFFICIENT
356 Amplifiers Tested From 8 Wafer Lots
VDD = 10 V
P Package
Outliers:
(1) 18.7 µV/°C
(1) 11.6 µV/°C
ÏÏÏÏÏÏ
TA = 25°C to 125°C
†Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
SLOS154B− DECEMBER 1995 − REVISED JUNE 2005
12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS†
Figure 5
0
0
VOH− High-Level Output Voltage − V
IOH − High-Level Output Current − mA −10
5
−2 −4 −6 −8
1
2
3
4
VDD = 3 V
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
ÁÁ
ÁÁ
ÁÁ
VOH
TA = 25°C
VID = 100 mV
ÏÏÏÏ
ÏÏÏÏ
VDD = 5 V
ÏÏÏÏÏÏ
VDD = 4 V
Figure 6
0
0
IOH − High-Level Output Current − mA −40
16
−10 −20 −30
2
4
6
8
10
12
14 TA = 25°C
VID = 100 mV
VDD = 16 V
VDD = 10 V
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
−35−25−15−5
VOH− High-Level Output Voltage − V
ÁÁ
ÁÁ
ÁÁ
VOH
Figure 7
0
0
VDD − Supply Voltage − V 16
16
2 4 6 8 10 12 14
2
4
6
8
10
12
14 VID = 100 mV
RL = 1 MΩ
TA = 25°C
HIGH-LEVEL OUTPUT VOLTAGE
vs
SUPPLY VOLTAGE
VOH− High-Level Output Voltage − V
ÁÁÁ
ÁÁÁ
ÁÁÁ
VOH
Figure 8
−75
−2.4
TA − Free-Air Temperature − °C125
−1.6
−50 −25 0 25 50 75 100
−2.3
−2.2
−2.1
−2
−1.9
−1.8
−1.7
IOH = −5 mA
VID = 100 mV
VDD = 5 V
VDD = 10 V
HIGH-LEVEL OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
VOH− High-Level Output Voltage − V
ÁÁ
ÁÁ
ÁÁ
VOH
†Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
SLOS154B− DECEMBER 1995 − REVISED JUNE 2005
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS†
Figure 9
0
300
VOL − Low-Level Output Voltage − mV
VIC − Common-Mode Input Voltage − V 4
700
123
400
500
600
LOW-LEVEL OUTPUT VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
650
550
450
350
ÁÁ
ÁÁ
VOL
TA = 25°C
IOL = 5 mA
VDD = 5 V
VID = −1 V
ÏÏÏÏÏÏ
ÏÏÏÏÏÏ
VID = −100 mV
Figure 10
250 0VIC − Common-Mode Input Voltage − V
300
350
400
450
500
246810
LOW-LEVEL OUTPUT VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
13 579
VOL − Low-Level Output Voltage − mV
ÁÁÁ
ÁÁÁ
VOL
VDD = 10 V
IOL = 5 mA
TA = 25°C
VID = −1 V
VID = −2.5 V
VID = −100 mV
Figure 11
LOW-LEVEL OUTPUT VOLTAGE
vs
DIFFERENTIAL INPUT VOLTAGE
0VID − Differential Input Voltage − V −10−2 −4 −6 −8
800
700
600
500
400
300
200
100
0−1 −3 −5 −7 −9
VOL − Low-Level Output Voltage − mV
ÁÁ
ÁÁ
VOL
IOL = 5 mA
VIC = VID/2
TA = 25°C
VDD = 10 V
ÏÏÏÏ
ÏÏÏÏ
VDD = 5 V
Figure 12
−75
0
TA − Free-Air Temperature − °C125
900
−50 −25 0 25 50 75 100
100
200
300
400
500
600
700
800
LOW-LEVEL OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
VOL − Low-Level Output Voltage − mV
ÁÁ
ÁÁ
ÁÁ
VOL
VIC = 0.5 V
VID = −1 V
IOL = 5 mA
ÏÏÏÏ
ÏÏÏÏ
VDD = 10 V
ÏÏÏÏ
ÏÏÏÏ
VDD = 5 V
†Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
SLOS154B− DECEMBER 1995 − REVISED JUNE 2005
14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS†
Figure 13
0
1
8
01 2 3 4 5 6 7
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9 VID = −1 V
VIC = 0.5 V
TA = 25°C
VDD = 3 V
VDD = 4 V
VDD = 5 V
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
IOL − Low-Level Output Current − mA
VOL − Low-Level Output Voltage − V
ÁÁ
ÁÁ
VOL
Figure 14
0IOL − Low-Level Output Current − mA
3
30
05 10 15 20 25
0.5
1
1.5
2
2.5 TA = 25°C
VIC = 0.5 V
VID = −1 V
VDD = 10 V
VDD = 16 V
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
VOL − Low-Level Output Voltage − V
ÁÁ
ÁÁ
ÁÁ
VOL
Figure 15
0VDD − Supply Voltage − V
2000
16
02 4 6 8 10 12 14
200
400
600
800
1000
1200
1400
1600
1800 RL = 1 MΩTA = −55°C
−40°C
TA = 0°C
ÏÏ
25°C
ÏÏÏ
ÏÏÏ
70°C
ÏÏÏ
85°C
125°C
LARGE-SIGNAL
DIFFERENTIAL VOLTAGE AMPLIFICATION
vs
SUPPLY VOLTAGE
ÁÁ
ÁÁ
ÁÁ
AVD − Large-Signal Differential
Á
Á
Á
AVD
Voltage Amplification − V/mV
Figure 16
1007550250−25−50
0125
TA − Free-Air Temperature − °C
−75
RL = 1 MΩ
VDD = 5 V
VDD = 10 V
1800
1600
1400
1200
1000
800
600
400
200
2000
LARGE-SIGNAL
DIFFERENTIAL VOLTAGE AMPLIFICATION
vs
FREE-AIR TEMPERATURE
ÁÁ
ÁÁ
ÁÁ
AVD − Large-Signal Differential
ÁÁ
ÁÁ
ÁÁ
AVD
Voltage Amplification − V/mV
†Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
SLOS154B− DECEMBER 1995 − REVISED JUNE 2005
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS†
Figure 17
0.1 12
5
10000
45 65 85 105
1
10
100
1000
25 TA − Free-Air Temperature − °C
INPUT BIAS AND INPUT OFFSET
CURRENTS
vs
FREE-AIR TEMPERATURE
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
VDD = 10 V
VIC = 5 V
See Note A
35 55 75 95 115
ÏÏ
IIB
ÏÏ
ÏÏ
IIO
NOTE A: The typical values of input bias current and input offset
current below 5 pA were determined mathematically.
− Input Bias and Input Offsert
IB
I and IIO Currents − pA
Figure 18
0
VDD − Supply Voltage − V
16
16
0246 8 10 12 14
2
4
6
8
10
12
14
MAXIMUM INPUT VOLTAGE
vs
SUPPLY VOLTAGE
ÏÏÏÏ
ÏÏÏÏ
TA = 25°C
− Maximum Input Voltage − V
VImax
Figure 19
TA = −55°C
ÏÏÏ
25°C
70°C
125°C
0
IDD − Supply Current − mA
VDD − Supply Voltage − V
45
16
02 4 6 8 10 12 14
5
10
15
20
25
30
35
40
ÏÏÏÏ
−40°C
0°C
No Load
VO = VDD/2
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
ÁÁ
ÁÁ
DD
IAµ
Figure 20
VO = VDD/2
No Load
VDD = 10 V
VDD = 5 V
−75 TA − Free-Air Temperature − °C
30
125
0−50 −25 0 25 50 75 100
5
10
15
20
25
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
IDD − Supply Current − mA
ÁÁ
ÁÁ
DD
IAµ
†Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
SLOS154B− DECEMBER 1995 − REVISED JUNE 2005
16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS†
Figure 21
SR − Slew Rate − V/s
CL = 20 pF
RL = 1 MΩ
VI(PP) = 1 V
AV = 1
See Figure 33
TA= 25°C
0VDD − Supply Voltage − V
0.07
16
0.00 2 4 6 8 10 12 14
0.01
0.02
0.03
0.04
0.05
0.06
SLEW RATE
vs
SUPPLY VOLTAGE
sµ
Figure 22
SLEW RATE
vs
FREE-AIR TEMPERATURE
VI(PP) = 5.5 V
VDD = 10 V
VDD = 5 V
VI(PP) = 1 V
VDD = 5 V
VI(PP) = 2.5 V
VDD = 10 V
VI(PP) = 1 V
−75 TA − Free-Air Temperature − °C
0.07
125
0.00 −50 −25 0 25 50 75 100
0.01
0.02
0.03
0.04
0.05
0.06 CL = 20 pF
RL = 1 MΩ
See Figure 33
AV = 1
SR − Slew Rate − V/s sµ
Figure 23
0
Bias-Select Current − nA
VDD − Supply Voltage − V
150
16
02 4 6 8 10 12 14
30
60
90
120
TA = 25°C
BIAS-SELECT CURRENT
vs
SUPPLY VOLTAGE
135
105
75
45
15
ÏÏÏÏÏ
ÏÏÏÏÏ
VI(SEL) = VDD
Figure 24
0.1 f − Frequency − kHz
10
100
0
1
2
3
4
5
6
7
8
9
110
VDD = 10 V
VDD = 5 V
Á
MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGE
vs
FREQUENCY
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
See Figure 33
RL = 1 MΩ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
TA = 125°C
TA = 25°C
TA = −55°C
− Maximum Peak-to-Peak Output Voltage − V
VO(PP)
†Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
SLOS154B− DECEMBER 1995 − REVISED JUNE 2005
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS†
Figure 25
UNITY-GAIN BANDWIDTH
vs
FREE-AIR TEMPERATURE
VDD = 5 V
VI = 10 mV
CL = 20 pF
See Figure 35
−75
B1 − Unity-Gain Bandwidth − kHz
TA − Free-Air Temperature − °C
150
125
30 −50 −25 0 25 50 75 100
50
70
90
110
130
B1
Figure 26
0VDD − Supply Voltage − V
140
16
50 2468 10 12 14
60
70
80
90
100
110
120
130 TA = 25°C
CL = 20 pF
VI = 10 mV
UNITY-GAIN BANDWIDTH
vs
SUPPLY VOLTAGE
B1 − Unity-Gain Bandwidth − kHz
B1
ÏÏÏÏÏÏ
ÏÏÏÏÏÏ
See Figure 35
1f − Frequency − Hz 1 M
0.1 10 100 1 k 10 k 100 k
1
101
102
103
104
105
106
150°
120°
90°
60°
30°
0°
180°
Phase Shift
TA = 25°C
RL = 1 MΩ
VDD = 5 V
ÏÏÏ
AVD
LARGE-SIGNAL DIFFERENTIAL VOLTAGE
AMPLIFICATION AND PHASE SHIFT
vs
FREQUENCY
107
ÏÏÏÏÏ
ÏÏÏÏÏ
Phase Shift
AVD − Large-Signal Differential
ÁÁ
ÁÁ
AVD
Voltage Amplification − dB
Figure 27
†Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
SLOS154B− DECEMBER 1995 − REVISED JUNE 2005
18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS†
LARGE-SIGNAL DIFFERENTIAL VOLTAGE
AMPLIFICATION AND PHASE SHIFT
vs
FREQUENCY
VDD = 10 V
RL = 1 MΩ
TA = 25°C
Phase Shift
180°
0°
30°
60°
90°
120°
150°
106
104
103
102
101
1
100 k10 k1 k10010
0.1 1 M
f − Frequency − Hz
1
105
107
ÏÏÏÏ
AVD
ÏÏÏÏÏ
ÏÏÏÏÏ
Phase Shift
AVD − Large-Signal Differential
ÁÁ
ÁÁ
AVD
Voltage Amplification − dB
Figure 28
Figure 29
PHASE MARGIN
vs
SUPPLY VOLTAGE
0
m − Phase Margin
VDD − Supply Voltage − V
42°
16
30°2 4 6 8 10 12 14
32°
34°
36°
38°
40°
See Figure 35
VI = 10 mV
TA = 25°C
CL = 20 pF
Á
Á
m
φ
Figure 30
See Figure 35
VI = 10 mV
CL = 20 pF
VDD = 5 mV
−75 TA − Free-Air Temperature − °C
40°
125
20°−50 −25 0 25 50 75 100
24°
28°
32°
36°
PHASE MARGIN
vs
FREE-AIR TEMPERATURE
38°
34°
30°
26°
22°
m − Phase Margin
ÁÁ
ÁÁ
m
φ
†Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
SLOS154B− DECEMBER 1995 − REVISED JUNE 2005
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS†
Figure 31
VDD = 5 mV
TA = 25°C
See Figure 35
VI = 10 mV
0CL − Capacitive Load − pF
37°
100
25°20 40 60 80
27°
29°
31°
33°
35°
PHASE MARGIN
vs
CAPACITIVE LOAD
10 30 50 70 90
m − Phase Margin
ÁÁ
ÁÁ
m
φ
Figure 32
75
1
VN − Equivalent Input Noise Voltage − nV/Hz
f − Frequency − Hz
200
1000
0
25
50
100
125
150
175
10 100
EQUIVALENT INPUT NOISE VOLTAGE
vs
FREQUENCY
Vn
ÁÁ
ÁÁ
ÁÁ
ÁÁ
nV/ Hz
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
TA = 25°C
RS = 20Ω
VDD = 5 V
ÏÏÏÏÏ
ÏÏÏÏÏ
See Figure 34
†Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
PARAMETER MEASUREMENT INFORMATION
single-supply versus split-supply test circuits
Because the TLC27L1 is optimized for single-supply operation, circuit configurations used for the various tests
often present some inconvenience since the input signal, in many cases, must be offset from ground. This
inconvenience can be avoided by testing the device with split supplies and the output load tied to the negative
rail. A comparison of single-supply versus split-supply test circuits is shown below. The use of either circuit gives
the same result.
+
VDD
CLRL
VO
VIVI
VO
RL
CL
−
+
VDD+
VDD−
(a) SINGLE SUPPLY (b) SPLIT SUPPLY
−
Figure 33. Unity-Gain Amplifier
SLOS154B− DECEMBER 1995 − REVISED JUNE 2005
20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
single-supply versus split-supply test circuits (continued)
VDD
−
+
VDD+
−
+
1/2 VDD
20 Ω
VO
2 kΩ
20 Ω
VDD−
20 Ω20 Ω
2 kΩ
VO
(a) SINGLE SUPPLY (b) SPLIT SUPPLY
Figure 34. Noise-Test Circuit
100 ΩVDD
−
+
10 kΩ
VO
CL
1/2 VDD
VIVI
CL
100 Ω
VO
10 kΩ
−
+
VDD+
VDD−
(a) SINGLE SUPPLY (b) SPLIT SUPPLY
Figure 35. Gain-of-100 Inverting Amplifier
input bias current
Due to the high input impedance of the TLC27L1 operational amplifiers, attempts to measure the input bias
current can result in erroneous readings. The bias current at normal room ambient temperature is typically less
than 1 pA, a value that is easily exceeded by leakages on the test socket. Two suggestions are offered to avoid
erroneous measurements:
1. Isolate the device from other potential leakage sources. Use a grounded shield around and between the
device inputs (see Figure 36). Leakages that would otherwise flow to the inputs are shunted away.
2. Compensate for the leakage of the test socket by actually performing an input bias-current test (using a
picoammeter) with no device in the test socket. The actual input bias current can then be calculated by
subtracting the open-socket leakage readings from the readings obtained with a device in the test socket.
One word of caution: many automatic testers as well as some bench-top operational amplifier testers use the
servo-loop technique with a resistor in series with the device input to measure the input bias current (the voltage
drop across the series resistor is measured and the bias current is calculated). This method requires that a
device be inserted into the test socket to obtain a correct reading; therefore, an open-socket reading is not
feasible using this method.
SLOS154B− DECEMBER 1995 − REVISED JUNE 2005
21
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PARAMETER MEASUREMENT INFORMATION
V = VIC
41
58
Figure 36. Isolation Metal Around Device Inputs (JG and P packages)
low-level output voltage
To obtain low-supply-voltage operation, some compromise is necessary in the input stage. This compromise
results in the device low-level output being dependent on both the common-mode input voltage level as well
as the differential input voltage level. When attempting to correlate low-level output readings with those quoted
in the electrical specifications, these two conditions should be observed. When conditions other than these are
to be used, please refer to the Typical Characteristics section of this data sheet.
input offset-voltage temperature coefficient
Erroneous readings often result from attempts to measure the temperature coefficient of input offset voltage.
This parameter is actually a calculation using input offset-voltage measurements obtained at two different
temperatures. When one (or both) of the temperatures is below freezing, moisture can collect on both the device
and the test socket. This moisture results in leakage and contact resistance which can cause erroneous input
offset-voltage readings. The isolation techniques previously mentioned have no effect on the leakage since the
moisture also covers the isolation metal itself, thereby rendering it useless. It is suggested that these
measurements be performed at temperatures above freezing to minimize error.
full-power response
Full-power response, the frequency above which the amplifier slew rate limits the output voltage swing, is often
specified two ways: full-linear response and full-peak response. The full-linear response is generally measured
by monitoring the distortion level of the output while increasing the frequency of a sinusoidal input signal until
the maximum frequency is found above which the output contains significant distortion. The full-peak response
is defined as the maximum output frequency, without regard to distortion, above which full peak-to-peak output
swing cannot be maintained.
Since there is no industry-wide accepted value for significant distortion, the full-peak response is specified in
this data sheet and is measured using the circuit in Figure 33. The initial setup involves the use of a sinusoidal
input to determine the maximum peak-to-peak output of the device (the amplitude of the sinusoidal wave is
increased until clipping occurs). The sinusoidal wave is then replaced with a square wave of the same
amplitude. The frequency is then increased until the maximum peak-to-peak output can no longer be maintained
(Figure 37). A square wave allows a more accurate determination of the point at which the maximum
peak-to-peak output is reached.
SLOS154B− DECEMBER 1995 − REVISED JUNE 2005
22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
full-power response (continued)
(a) f = 100 Hz (b) B
OM
> f > 100 Hz (c) f = B
OM
(d) f > B
OM
Figure 37. Full-Power-Response Output Signal
test time
Inadequate test time is a frequent problem, especially when testing CMOS devices in a high-volume,
short-test-time environment. Internal capacitances are inherently higher in CMOS than in bipolar and BiFET
devices, and require longer test times than their bipolar and BiFET counterparts. The problem becomes more
pronounced with reduced supply levels and lower temperatures.
APPLICATION INFORMATION
single-supply operation
While the TLC27L1 performs well using dual
power supplies (also called balanced or split
supplies), the design is optimized for
single-supply operation. This includes an input
common-mode voltage range that encompasses
ground as well as an output voltage range that
pulls down to ground. The supply voltage range
extends d o w n t o 3 V (C-suffix types), thus allowing
operation with supply levels commonly available
for TTL and HCMOS; however, for maximum
dynamic range, 16-V single-supply operation is
recommended.
Many single-supply applications require that a
voltage be applied to one input to establish a
reference level that is above ground. A resistive voltage divider is usually sufficient to establish this reference
level (see Figure 38). The low-input bias-current consumption of the TLC27L1 permits the use of very large
resistive values to implement the voltage divider, thus minimizing power consumption.
The TLC27L1 works well in conjunction with digital logic; however , when powering both linear devices and digital
logic from the same power supply, the following precautions are recommended:
1. Power the linear devices from separate bypassed supply lines (see Figure 39); otherwise, the linear device
supply rails can fluctuate due to voltage drops caused by high switching currents in the digital logic.
2. Use proper bypass techniques to reduce the probability of noise-induced errors. Single capacitive
decoupling is often adequate; however, RC decoupling may be necessary in high-frequency applications.
−
+
R4
VO
VDD
R2
R1
VI
Vref R3 C
0.01 µF
Vref +VDD R3
R1 )R3
VO+(Vref *VI)R4
R2 )Vref
Figure 38. Inverting Amplifier With Voltage
Reference
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APPLICATION INFORMATION
single-supply operation (continued)
(b) SEPARATE BYPASSED SUPPLY RAILS (preferred)
(a) COMMON SUPPLY RAILS
Logic
−
+
Logic Logic Power
Supply
Supply
Power
LogicLogic
−
+
Logic
OUT
OUT
Figure 39. Common Versus Separate Supply Rails
input offset voltage nulling
The TLC27L1 offers external input-offset null control. Nulling of the input-offset voltage may be achieved by
adjusting a 25-kΩ potentiometer connected between the offset null terminals with the wiper connected as shown
in Figure 40. Total nulling may not be possible.
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
25 kΩ
N2
VDD N2
N1 25 kΩ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
GND
(a) SINGLE SUPPLY (b) SPLIT SUPPLY
−
+
−
+
N1
OUTOUT
IN−
IN+
IN−
IN+
Figure 40. Input Offset-Voltage Null Circuit
input characteristics
The TLC27L1 is specified with a minimum and a maximum input voltage that, if exceeded at either input, could
cause the device to malfunction. Exceeding this specified range is a common problem, especially in
single-supply operation. Note that the lower range limit includes the negative rail, while the upper range limit
is specified at VDD − 1 V at TA = 25°C and at VDD − 1.5 V at all other temperatures.
SLOS154B− DECEMBER 1995 − REVISED JUNE 2005
24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
input characteristics (continued)
The use of the polysilicon-gate process and the careful input circuit design gives the TLC27L1 very good input
offset-voltage drift characteristics relative to conventional metal-gate processes. Offset-voltage drift in CMOS
devices is highly influenced by threshold voltage shifts caused by polarization of the phosphorus dopant
implanted in the oxide. Placing the phosphorus dopant in a conductor (such as a polysilicon gate) alleviates the
polarization problem, thus reducing threshold voltage shifts by more than an order of magnitude. The
offset-voltage drift with time has been calculated to be typically 0.1 µV/month, including the first month of
operation.
Because of the extremely high input impedance and resulting low bias-current requirements, the TLC27L1 is
well suited for low-level signal processing; however, leakage currents on printed circuit boards and sockets can
easily exceed bias-current requirements and cause a degradation in device performance. It is good practice
to include guard rings around inputs (similar to those of Figure 36 in the Parameter Measurement Information
section). These guards should be driven from a low-impedance source at the same voltage level as the
common-mode input (see Figure 41).
noise performance
The noise specifications in operational amplifier circuits are greatly dependent on the current in the first-stage
differential a m p l i fier. The low-input bias-current requirements of the TLC27L1 results in a very-low noise current,
which is insignificant in most applications. This feature makes the devices especially favorable over bipolar
devices when using values of circuit impedance greater than 50 kΩ, since bipolar devices exhibit greater noise
currents.
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
−
+
VI
VOVO
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
−
+
VO
VI
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
−
+
VI
(a) NONINVERTING AMPLIFIER (b) INVERTING AMPLIFIER (c) UNITY-GAIN AMPLIFIER
Figure 41. Guard-Ring Schemes
SLOS154B− DECEMBER 1995 − REVISED JUNE 2005
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APPLICATION INFORMATION
feedback
Operational amplifier circuits almost always
employ feedback, and since feedback is the first
prerequisite for oscillation, a little caution is
appropriate. Most oscillation problems result from
driving capacitive loads and ignoring stray input
capacitance. A small-value capacitor connected
in parallel with the feedback resistor is an effective
remedy (see Figure 42). The value of this
capacitor is optimized empirically.
electrostatic discharge protection
The TLC27L1 incorporates an internal ESD protection circuit that prevents functional failures at voltages up to
2000 V as tested under MIL-STD-883C, Method 3015.2. Care should be exercised, however, when handling
these devices as exposure to ESD may result in the degradation of the device parametric performance. The
protection circuit also causes the input bias currents to be temperature dependent and have the characteristics
of a reverse-biased diode.
latch-up
Because CMOS devices are susceptible to latch-up due to their inherent parasitic thyristors, the TLC27L1 inputs
and output were designed to withstand −100-mA surge currents without sustaining latch-up; however,
techniques should be used to reduce the chance of latch-up whenever possible. Internal protection diodes
should not by design be forward biased. Applied input and output voltage should not exceed the supply voltage
by more than 300 mV. Care should be exercised when using capacitive coupling on pulse generators. Supply
transients should be shunted by the use of decoupling capacitors (0.1 µF typical) located across the supply rails
as close to the device as possible.
The current path established when latch-up occurs is usually between the positive supply rail and ground and
can be triggered by surges on the supply lines and/or voltages on either the output or inputs that exceed the
supply voltage. Once latch-up occurs, the current flow is limited only by the impedance of the power supply and
the forward resistance of the parasitic thyristor and usually results in the destruction of the device. The chance
of latch-up occurring increases with increasing temperature and supply voltages.
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
−
+
Figure 42. Compensation for Input Capacitance
VO
SLOS154B− DECEMBER 1995 − REVISED JUNE 2005
26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
output characteristics
The output stage of the TLC27L1 is designed to
sink and source relatively high amounts of current
(see Typical Characteristics). If the output is
subjected to a short-circuit condition, this high
current capability can cause device damage
under certain conditions. Output current capability
increases with supply voltage (see Figure 43).
All operating characteristics of the TLC27L1 were
measured using a 20-pF load. The devices drive
higher capacitive loads; however, as output load
capacitance increases, the resulting response
pole occurs at lower frequencies, thereby causing
ringing, peaking, or even oscillation (see Figure
44). In many cases, adding some compensation
in the form of a series resistor in the feedback loop
alleviates the problem.
(a) CL = 20 pF, RL = NO LOAD (b) CL = 260 pF, RL = NO LOAD (c) CL = 310 pF, RL = NO LOAD
Figure 44. Effect of Capacitive Loads in Low-Bias Mode
Although the TLC27L1 possesses excellent high-level output voltage and current capability, methods are
available for boosting this capability, if needed. The simplest method involves the use of a pullup resistor (RP)
connected from the output to the positive supply rail (see Figure 45). There are two disadvantages to the use
of this circuit. First, the NMOS pulldown transistor, N4 (see equivalent schematic) must sink a comparatively
large amount of current. In this circuit, N4 behaves like a linear resistor with an on-resistance between
approximately 60 Ω and 180 Ω, depending on how hard the operational amplifier input is driven. With very low
values of RP, a voltage offset from 0 V at the output occurs. Secondly, pullup resistor RP acts as a drain load
to N4 and the gain of the operational amplifier is reduced at output voltage levels where N5 is not supplying the
output current.
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
−
+
2.5 V
VO
CL
− 2.5 V
VITA = 25°C
f = 1 kHz
VI(PP) = 1 V
Figure 43. Test Circuit for Output
Characteristics
SLOS154B− DECEMBER 1995 − REVISED JUNE 2005
27
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
RP+VDD–VO
IF)IL)IP
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
VI
VDD
RP
VO
R2
R1 RL
IP
IF
IL
IP = Pullup current required
by the operational amplifier
(typically 500 mA)
−
+
Figure 45. Resistive Pullup to Increase VOH
5 V
0.016 µF
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
Low Pass
High Pass
Band Pass
R = 5 kΩ(3/d-1)
(see Note A)
0.016 µF
5 V
10 kΩ
10 kΩ
10 kΩ5 V
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
VI
5 kΩ
10 kΩ
10 kΩ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
−
+
TLC27L1 −
+
TLC27L1 −
+
TLC27L1
NOTE A: d = damping factor, I/O
Figure 46. State-Variable Filter
SLOS154B− DECEMBER 1995 − REVISED JUNE 2005
28 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
R1, 100 kΩ
9 V
100 kΩ
C = 0.1 µF
R3, 47 kΩ
10 kΩ
10 kΩ
VO (see Note B)
9 V
VO (see Note A)
R2
9 V
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
FO+1
4C(R2) ƪR1
R3ƫ
−
+
TLC27L1 −
+
TLC27L1
NOTES: A. VO(PP) = 8 V
B. VO(PP) = 4 V
Figure 47. Single-Supply Function Generator
TLC4066
VDD
VI
90 kΩ
9 kΩ
X1
11B
VDD
VI
S1
S2
C
A
C
A2
X2 2B
1 kΩ
Analog
Switch
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
+
−
TLC27L1
AV
Select S1S2
10 100
NOTE A: VDD = 5 V to 12 V
Figure 48. Amplifier With Digital-Gain Selection
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APPLICATION INFORMATION
5 V
500 kΩ
500 kΩ
5 V
500 kΩ
0.1 µF
500 kΩ
VO2
VO1
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
−
+
TLC27L1
+
−
TLC27L1
Figure 49. Multivibrator
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
10 kΩ
VO
100 kΩ
20 kΩ
VI
−
+
TLC27L1
VDD
NOTE A: VDD = 5 V to 16 V
Figure 50. Full-Wave Rectifier
SLOS154B− DECEMBER 1995 − REVISED JUNE 2005
30 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
Set 100 kΩ
VDD
10 kΩ
100 kΩ
Reset
33 Ω
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
+
−
TLC27L1
NOTE A: VDD = 5 V to 16 V
Figure 51. Set/Reset Flip-Flop
5 V
0.016 µF
10 kΩ10 kΩ
VO
0.016 µF
Vi
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
+
−
TLC27L1
NOTE A: Normalized to FC = 1 kHz and RL = 10 kΩ
Figure 52. Two-Pole Low-Pass Butterworth Filter
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31
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MECHANICAL INFORMATION
D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
4040047/ B10/94
0.228 (5,80)
0.244 (6,20)
0.069 (1,75) MAX 0.010 (0,25)
0.004 (0,10)
1
14
0.014 (0,35)
0.020 (0,51)
A
0.157 (4,00)
0.150 (3,81)
7
8
0.044 (1,12)
0.016 (0,40)
Seating Plane
0.010 (0,25)
PINS **
0.008 (0,20) NOM
A MIN
A MAX
DIM
Gage Plane
0.189
(4,80)
(5,00)
0.197
8
(8,55)
(8,75)
0.337
14
0.344
(9,80)
16
0.394
(10,00)
0.386
0.004 (0,10)
M
0.010 (0,25)
0.050 (1,27)
0°−ā8°
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Four center pins are connected to die mount pad.
E. Falls within JEDEC MS-012
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