TOSHIBA TMPZ84C015B TMPZ84C015BF-10 TLCS-Z80 MICROPROCESSOR OUTLINE AND FEATURES The TMPZ84C015B is a high-performance CMOS 8-bit microprocessor incorporating the counter timer circuit (CTC), the serial I/O port (SIO), the parallel I/O port (PIO), the clock generator/controller (CGC), and the watchdog timer (WDT) around the TLCS-Z80 MPU. This microprocessor inherits the basic architecture of the TLCS-Z80 series, allowing the user to utilize the software resources and development tools accumulated so far. The TMPZ84C015B is based on the new CMOS process and housed in a standard 100- pin mini-flat package, greatly contributing to system miniaturization and power saving. The TMPZ84C015B incorporates the high-performance serial /O port, the counter timer circuit which can be used as the baud rate generator, and the watchdog timer indispensable for control applications, offering the user a wide range of system applications such as the communication controllers including a communication adaptor and the various other controllers which need miniaturization. Features e Built-in TLCS-Z80 series MPU, CTC, SIO, PIO,CGC and watchdog timer features. e High speed operation (10MHz operation) e Built-in clock generator (CGC: Clock Generator Controller) e Built-in standby capability (with the controller built in) provides 4 operation modes: Runmode (Normal operation) Idle-1 mode (Only clock oscillation goes on. ) Idle-2 mode (Wake-up by CTC enabled. ) Stop mode (Clock oscillation stopped; standby state) e Wide operational voltage range (5V+10%:10MHz VERSION) supported. e Wide operating temperature range (40C to +70C : 10MHz VERSION) e Low power dissipation Inoperation : (RUNmode) 45mA TYP. at 10 MHz In idle : (IDLE-1 mode) 2.5mA TYP. at 10 MHz (IDLE-2 mode) 19mA TYP. at 10 MHz Instandby : (STOP mode) 500nA TYP. e Built-in TLCS-Z80 series SIO capability MPUZ80ASSP-1TOSHIBA TMPZ84C015B note: A pair of independent full duplex channels supports the asynchronous as well as synchronous byte-oriented (monosync and bisync) and bit-oriented HDLC and CCITT-X. 25 protocols. Built-in CRC generation and check capability. Data transfer rates of up to 2000 K bits/sec (10 MHz). Built-in TLCS-Z80 series CTC capability Four independent built-in channels. The timer or counter modes can be set . Also available as the SIO baud rate generator. Built-in TLCS-Z80 series PIO capability Two programmable independent 8-bit I/O ports having handshaking capability One of 4 operation modes can be selected for each port by using the program: Mode 0 (byte output mode) Mode 1 (byte input mode) Mode 2 (byte input/output mode) Mode 3 (bit mode) Built-in watchdog timer Programmed daisy-chain interrupt control Built-in dynamic RAM refresh controller TTL/CMOS compatible Housed compact standard 100-pin mini-flat package The Toshiba real time emulator (RTE80) and the Z80 ICE commercially available can be used (the TMPZ84CO015B used as the evaluator). The Toshiba evaluator board installed. Z80 is a trade mark of Zilog Inc. MPUZ80ASSP-2TOSHIBA TMPZ84C015B8 2. PIN ASSIGNMENT AND FUNCTIONS 2.1. Pin Assignments (Top View) CLK/TRGO AS CLK/TRGI Aa CLK /TRG2 a3 CLK /TRG3 A2 ZCiTO3 Al 2c1TO2 AO zcrTai RFSH 2c /TO0 mt WDTOUT RESET 1Et BUSREQ \EO wait ATRF BUSACK CLKIN WR CLKOUT RD EV ioRQ TMPZ84C015BF-10 XTALZ vss XTALt MREQ vss HALT NMI int BRDY ARDY BSTB ASTB PB7 PA7 PBE PAG PBS PAS PB4 | PAS PB3 PA3 PB2 PA2 PBI PAI PBO | PAO WRDYB WIRDYA ft ti[aq[q didid[atq[qe VY b [mja[mjo wim(m wo We AUY AjelmimMlauU VY Y jalmleslae Ofuly a Zz |< XR JR IR JU - > [Ue] KKK OX > elelr Flole lla, es (Al leclo Riki o@ wn 110690 Note: TheICT pin is the test pin. Do not make anyexternal connection to this pin. Figure 2.1.1 Pin Assignments MPUZ80ASSP-3TOSHIBA TMPZ84C015B 2.2 (A) Pin Functions (1/6) Pin Q'ty (Number) Type Function DO-D7 8 (82-89) Input/output 3-state The 8-bit bi-directional data bus. A0-A15 16 (91-100) (1-6) Output 3-state The 16-bit address bus. These pins specify memory and 1/O port addresses. During a refresh cycle, the refresh address is output to the low-order 7 bits and A7RF. (8) Output 3-state The Machine Cycle 1 signal. . In an operation code fetch cycle, this pin goes 0 with the MREQ signal. At the execution of a 2-byte operation code, this pin goes 0 for each operation code fetch. In a maskable interrupt acknowledge cycle, this pin goes 0 with the JORQ signal. When the EV signal is applied, this pin is putin the high-impedance state. (14) Output 3-state The Read signal. It indicates that the MPU is ready for accepting data from memory or I/O device. The data from the addressed memory or 1/0 devices is gated by this signal onto the MPU data bus. When the BUSREQ signal is applied, this pin is put in the high-impedance state. (13) Output 3-state The Write signal. This signal is output when the data to be stored in the addressed memory or I/O device is on the data bus. When the BUSREQ signal is applied, this pin is put in the high- impedance state. (17) Output 3-state The Memory Request signal. When the execution address for memory access is on the address bus, this pin goes 0 . During a memory refresh cycle, this pin also goes 0 with RFSH signal. | o xa ce) (15) Output 3-state The Input/Output Request signal. This pin goes 0 when the address for an I/O read or write operation is on the low-order 8 bits (AO through A7) of the address bus. The [ORQ signal is also output with the M1 signal at interrupt acknowledge to tell an I/O device that the interrupt response vector can be placed on the data bus. Note that the interrupt priority among the TMPZ84C015B CTC, and SIO is selected by a program. 170489 MPUZ80ASSP-4TOSHIBA TMPZ84C015B (2/6) Pin O'ty (Number) Type Function IEO 1 (71) Output The Interrupt Enable Output signal. in the daisy chain interrupt control, this signal controls the interrupt from the peripheral LSIs connected next to the TMPZ84C015B. The IEO pin goes 1 only when the IEI pin is 1 and the MPU is not servicing an interrupt from the built-in peripheral LSI. XTAL1 XTAL2 (65) (66) Input Output The crystal oscillator connection. Connects an oscillator having the oscillation frequency 2 times as high as the system clock (CLKOUT) frequency. CLKIN (69) Input The Single-phase Clock Input. When the clock input is placed in the DC state (continued "1" or 0 level), this pin stops operating and holds the state of that time. Normally, this pin is connected with the CLKOUT pin. However, to operate the system with the external clock, connect the external clock to the CLKIN pin. CLKOUT (68) Output The Single-phase Clock Output. When a Halt instruction is executed in the Stop or Idle-1 mode, the CLKOUT output is retained at "QO". Inthe Run and Idle-2 mode the clack is kept output. This pin provides the clock to other peripheral ICs. 7 m wn m (9) Input The Reset signal input. This signal resets the internal states of the TMPZ84C015B. This signal is also used to return from the standby state in the Stop or Idle mode. = (19) Input The Maskable Interrupt signal. An interrupt is caused by the internal CTC, SIO PIO or the peripheral LSI. An interrupt is acknowledged when the interrupt enable flip-flop (IFF) is set to 1" by software. The INT pin is normally wire-ORed and requires an external pullup resistor for these applications. This signal is also used to return from the stand- by state in the Stop or Idle made. (11) Input The Wait Request signal. This signal indicates the MPU that the addressed memory or I/O device is not ready for data transfer. As tong as this signal is "0" , the MPU is in the Wait state. 170489 MPUZ80ASSP-5TOSHIBA TMPZ84C015B (3/6) Q'ty (Number) BUSREQ 1 Input The Bus Request signal. The BUSREQ signal (10) forces the MPU address bus, data bus, and control signals MREQ, IORQ, RD, and WR to be placed in the high-impedance state. This signal is normally Wire-ORed and requires an external pullup resistor for these applications. Pin Type Function BUSACK 1 Output The Bus Acknowledge signal. In response to the (12) BUSREQ signal, the BUSACK signal indicates to the requesting peripheral LSi that the MPU address bus, data bus, and control signals MREQ, IORO, RD and WR have been put in the high- impedance state. HALT 1 Output The Halt signal. This pin goes 0 when the MPU (81) 3-state has executed a Halt instruction and is in the Halt state. itis put in the high-impedance state when the EV signal is applied. RFSH 1 Output The refresh signal. When the dynamic memory (7) refresh address is on the low-order 8 bits of the address bus, this signal goes 0 . At the same time, the MREQ signal also goes active ("0"). This pin is put in the high-impedance state when the EV signal is applied. CLK/TRGO 4 Input The external clock/timer trigger. These 4 ~CLK/TRG3 (78-81) CLK/TRG pins correspond to 4 channels. In the counter mode, the down counter is decremented by 1 and in the timer mode, the timer is activated at each active edge (a rising or falling edge) of the signal which are input by these pins. It can be selected by program whether the active edge is a rising or falling edge. ZC/TOO 4 Output The Zero Count/Timer Out signal. In either the ~2ZC/T03 (74-77) Timer mode, or counter mode, pulses are output from these pins when the down counter has reached zero. tEl 1 , Input The Interrupt Enable Input signal. This signal is (72) used with the IEO to form a priority daisy chain when there is more than one interrupt-driven peripheral LSI. NMI 1 Input The Non-maskable Interrupt Request signal. (63) This interrupt request has a higher priority than the maskable interrupt and 1s not dependent on the interrupt enable flip-flop (IFF) state. This signal is also used to return from the stand-by state in the Stop or idle made. 170489 MPUZB0ASSP-6TOSHIBA TMPZ84C015B (4/6) Q'ty (Number) EV 1 Input The Evaluator signal. When this signal is active, (67) the M1, HALT, and RFSH pins are put in the high- impedance state. In using the TMPZ84CO15B as an evaluator chip, the MPU is electrically disconnected (put in the high-impedance state) after one machine cycle is executed with the EV signal being 1 and the BUSREQ signal being 0, and follows the instructions from other MPU (such as the MPU of ICE). The signals of the disconnected MPU are A0O through A15, DO through D7, MREQ, IORQ, RD, WR, M1, HALT, and RFSH. BUSACK needs to be disconnected by an externally connected circuit. The evaluator board is available to use the TMPZ84C015B as an evaluator chip. Pin Type Function A7RF 1 Output The 1-bit auxiliary address bus. This pin outputs (70) the same signal as the bit 7 (A7) of the address bus. However, during a refresh cycle, this pin outputs the address which is the most significant bit of the 8-bit refresh address signal linked to the low-order 7 bits of the address bus. ASTB 1 Input The Port A Strobe Pulse From Peripheral Device. (21) This signal is used at the handshaking between port A and external circuits. The meaning of this signal depends on the mode of operation selected for part A. (See PIO Basic Timing.) BSTB 1 Input The Port B Strobe Pulse From Peripheral Device. (61) This signal is used at the handshaking between port B and external circuits. The meaning of this signal is the same as the ASTB signal except when port A is in the mode 2. (See PIO Basic Timing. ) ARDY 1 Output The Register A Ready signal. This signal is used at (20) the handshaking between port A and external circuits. The meaning of this signal depends on the mode of operation selected for port A. (See PIO Basic Timing.) BRDY 1 Output The Register B Ready signal. This signal is used at (62) the handshaking between port B and external circuits. The meaning of this signal is the same as the ARDY signal except when port A is in the mode 2. (See "PIO Basic Timing. } PAO-PA7 8 Input/Output | The Port Data A signal. (22-29) 3-state These signals are used for data transfer between port A and external circuits. 170489 MPUZ80ASSP-7TOSHIBA TMPZ84C015B (5/6) . Q'ty P in (Number) Type PBO-PB7 8 Input/Output | The Port Data B signal. (53-60) 3-state These signals are used for data transfer between port B and external circuits. W/RDYA 2 Output The Wait/Ready signal A and the Wait/Ready W/RDYB (30, 52) These signals can be used as the Wait or Ready depending on SIO programming. When these signals are programmed as Wait, they go active at 0 to indicate to the MPU that the addressed memory or I/O devices are not ready for data transfer, requesting the MPU to wait. When these signals are programmed as Ready, they go active at 0 to determine when a peripheral device associated with a DMA port is ready for a read or write data. The DMA is requested to transfer data. SYNCA 2 Input/Output | The Synchronization signal. In the asynchronous SYNCB (31,51) receive mode, these signals act as the CTS and DCD signals. In the external sync mode, these signals act as inputs and in the internal sync mode, they act as outputs. RXDA 2 Input The Serial Receive Data signal. RXDB (32, 50) RXCA 2 Input The Receive Clock signal. In the asynchronous RXCB (33, 49) mode, the Receive Clocks may be 1, 16, 32 or 64 times the data transfer rate. TXCA 2 Input The Transmitter Clock signal. TXCB (34, 48) In the asynchronous mode, the Transmitter Clocks may be 1, 16, 32, or 64 times the data TXDA 2 Output The serial transmit data signal. TXDB (35, 47) DTRA 2 Output The Data Terminal Ready signal. These signals DTRB (36, 46) indicate whether the data terminal is ready to receive serial data or not. When it is ready, these signals go active to enable the transmitter of the terminal. When it is not ready, these signals go inactive to disable the transfer from the terminal. RTSA 2 Output The Request to Send signal. These pins are 0 RTSB (37, 45) when transmitting serial data. That is, to transmit data, these signals are made active to enable their receivers. 170489 MPUZ80ASSP-8TOSHIBA TMPZ84C015B (6/6) : Q'ty . Pin (Number) Type Function CTSA 2 Input The Clear To Send signal. When these pins are CTSB (38, 44) "0", the modem having transmitted these signals is ready to receive seria! data. When it is ready, these signals go active to enable the transmitter of the terminal. When it is not ready, these signals go inactive to disable the transfer from the terminal. DCDA 2 Input The Data Carrier Detect signal. When these pins DCDB (39, 43) are 0 the receive of serial data can be enabled. That is, to transmit data, these signals are made active to enable their receivers. ICT 2 Output The test pins. To be used in the open state. (40, 42) WDTOUT 1 Output The Watchdog Timer signal. (73) The output pulse width depends on the externally connected pin. vcc 2 The power supply (+ 5 V) pins. (41, 90) VSS 1 The ground (0 V) pins. (16, 64) 170489 2.2. (B) TMPZ84C0158 Internal I/O Address Map Internal /O Channel /O Address ch 0 # 10 cTc ch 1 # 11 (Counter Timer) ch 2 # 12 ch 3 # 13 ch A Send/Receive buffer # 18 slo ch A Command /Status Register # #19 (Serial 1/0) ch B Send/Receive buffer # 1A ch B Command/Status Register # 1B A Port Data # 1 PIO A Port Command # 1D (Parallel 1/0) B Port Data # 1E B Port Command #_1F Watch Dog Timer Stand-by mode Register WDTER, WDTPR, HALTMR # FO Watch Dog Timer Clear command (4Ey) #F1 command Register disable command (B1y) Daisy-chaine interrupt . . precedence Register Only use bit2~bit0 # F4 180489 MPUZ80ASSP-9TOSHIBA TMPZ84C015B 3. OPERATIONAL DESCRIPTION 3.1 Block Diagram and Operational Outline 3.1.1 Block Diagram XTAL1 XTAL2 Mi FATT CLKOUT EV BUSREQ CLIK CLKIN 7 HALT Mi NMI BUSACK = a Zz ) Controller =| 2 a za m Ww mi 4 Zz Ss 2C/TOo 5 2C/TO3 : 2] a wi x CLK/TRGo s CLK/TRG3 as So z a Zz 4 9 > oO o i > a qo vi > | g $ {RDYA SYNCA RXDA RXCA TXCA = ASTB ARDY PAQ PAZ i_t_ PBO Mi RESET IEl WR RFSH 5 Do~D7 IEO WotTouT n CLK i A7RF BRDY #FO Watchdog timer #F1 registers ct #F4 MT1- RESET MS1,MS2 Decoder Do~D7 = Ago~Ais Figure 3.1.1 Block Diagram of TMPZ84C015B 170489 MPUZ80ASSP-10TOSHIBA TMPZ84C015B 3.1.2 Operational Outline The TMPZ84C015B largely consists of a processor (MPU), a counter/timer circuit (CTC), a serial input/output controller (SIO), a parallel input/output controller (PIO), a watchdog timer (WDT), and a clock generator/controller (CGC). The MPU provides all the capabilities and pins of the Toshiba TLCS-Z80 MPU (TMPZ84CO00A) to play the role of the TLCS-Z80 microprocessor perfectly. The CTC provides the capabilities of the Toshiba TLCS-Z80 CTC (TMPZ84C30A) and has the pins required to perform the necessary operations as a TLCS-Z80 peripheral LSI. The four independent timer channels are I/O-addressed internally. The SIO provides the capabilities of the Toshiba TLCS-Z80 SIO (TMPZ84C43A) and has the pins required to perform the necessary operations as a TLCS-Z80 peripheral LSI. The two independent serial channels are I/O-addressed internally. The PIO provides the capabilities of the Toshiba TLCS-Z80 PIO (TMPZ84C20A) and has the pins required to perform the necessary operations as a TLCS-Z80 peripheral LSI. The two independent parallel ports are I/O-addressed internally. The WDT incorporates one-channel watchdog timer and the read/write-enabled watchdog timer control registers indispensable for control applications. The WDT also has the register to determine interrupt priorities, allowing the user to set the daisy-chain interrupt priorities by program. Additionally, the WDT has the IEI and IEO pins required to process the daisy- chain interrupts caused by the peripheral LSIs to be added both inside and outside the TMPZ84C015B. The CGC provides the four operation modes to control the entire TMPZ84C015B chip; the Run, Idle-1, Idle-2, and Stop modes. They are program-selectable. This chip has two clock pins: CLKOUT to supply clock from the CGC and CLKIN to get clock from the outside. Therefore, the TMPZ84C015B can be operated on the clock supplied from the outside at the CLKIN pin without using the CGC. The following briefly describes the four operation modes of the CGC with the CLKOUT and CLKIN pins connected: In the Run mode, the clock generated by the CGC is supplied to the TMPZ84CO15B and peripheral LSIs to perform the normal programmed microcomputer operations. In the Idle-1 mode, clock oscillation is going on but the clock is not supplied to the TMPZ84C015B and peripheral LSI, thereby saving the system power consumption and shortening the time required for system restart. MPUZ80ASSP-11TOSHIBA TMPZ84C015B e In the Idle-2 mode, clock oscillation is performed and the clock is output from the CLKOUT pin. The clock is supplied only to the CTC in the TMPZ84C015B, permitting a wake-up operation by the CTC. Like the Idle-1 mode, the Idle-2 mode saves the system power consumption and shortens the time required for system restart. e In the Stop mode, clock oscillation is not performed and the system operation can be stopped completely. In this mode, the system can be restarted with the internal data retained with an extremely low power consumption level unique to the CMOS technology. Note that these modes can be set only when the MPU has executed a HALT instruction. Additionally, the TMPZ84C015B has also the EV pin which is used with the BUSREQ pin to put the MPU in the high-impedance state for electrical disconnection, thus functioning as an evaluator chip. That is, the MPU in the TMPZ84C015B is electrically disconnected by these two pins to implement the emulation by the signal from the in-circuit emulator (ICE). For emulation, one machine cycle is performed on the MPU in the TMPZ84C015B with EV being 1 and the BUSREQ being 0 then the emulation is performed as instructed by the MPU. The MPU signals to be disconnected are A0O through A15, DO through D7, MREQ, IORQ, RD, Mi, HALT, and RFSH, BUSACK needs to be disconnected by an externally connected circuit. MPUZ80ASSP-12TOSHIBA TMPZ84C015B 3.2. MPU Operations This subsection describes the system configuration, functions and the basic operation of the MPU of the TMPZ84CO15B. 3.2.1 Block Diagram Figure 3.2.1 shows the block diagram of the MPU. { T Ao~Ais A7RF Do~As Adress bus output circuit CLK IN ~N >| Accumulator (A) Accumulator (A) Flag (F) Flag (F) 2 B register B' register a Cregister C' register x D register D register x E register E register uw ar / H register H' register 3 L register L' register oe l register R register uw E 7 Ee Zz IX register 2 _ 7 Do~D7 - l register $ Stack pointer (SP) a 5 Program counter (PC) a pw Temporary register Ee re A ss Incrementer/decrementer fe Y 2 \\ __I___Y| instruction 5 decoder zs Ee lu 8 2 Oo W _ Data VO vo Gontrol 12 3 IFFA iFF2 | Control Control onide a = | Interrupt | Control bus controller < <_ _ - contr: I NMI INT , i | IORQ HALT WAIT MREQ a RD Figure 3.2.1 MPU Block Diagram | | BUSREQ BUSACK m v a m wy my a x mn = | Z| 170489 MPUZ80ASSP- 13TOSHIBA TMPZ84C015B 3.2.2 MPU System Configuration [1] The MPU has the configuration shown in Figure 3.2.1. The address signal is put on the address bus via the address buffer. The data bus is controlled for input or output by the data bus interface. Both the address and data buses are put in the high-impedance state by the BUSREQ signal input to make them available for other peripheral LSIs. The Opcode read from memory via the data bus is written to the instruction register. This Opeode is decoded by the instruction decoder. According to the result of the decoding, control signals are sent to the relevant devices. Receiving these control signals, the ALU performs various arithmetic operations. The register array temporarily hold the information required to perform operation. The following describes the MPUs main components and functions which the user must understand to operate the TMPZ84CO15B: Internal Register Groups The configuration of the internal register groups is as follows: (1) Main registers A, F, B,C, D, E, H, L (2) Alternate registers A, F, B,C, D, FE, H, L (3) Special purpose registers I, R, IX, TY, SP, PC Figure 3.2.3 shows the configuration of the internal register groups. The register groups, each being of a static RAM, consists of eighteen 8-bit registers and four 16-bit registers. The following describes the function of each register: (1) Main registers (A, F, B, C, D, E, H, L) (a) Accumulator (A) The accumulator is an 8-bit register used for arithmetic and data transfer operations. (b) Flag register (F) (see Figure 3.2.2) The flag register is an 8-bit register to hold the result of each arithmetic operation. Actually, the 6 of the 8 bits are set(1)/reset(0) according to the condition specified by an instruction. MPUZ80ASSP-14TOSHIBA TMPZ84C015B MSB LSB 5 4 3 2 1 0 (* = Undefined) Tato bee eee] Figure 3.2.2 Flag Register Configuration 170489 The following 4 bits are directly available to the programmer for setting the jump, call and return instruction conditions: MSB LSB MSB LSB 7 07 0 Accumulator Flag register ] A F Main register B Cc General-purpose - register H L Accumulator Flag register | A F B Cc Alternate register D E H Lv Interrupt vector Memory refresh 7] | R MSB LSB 15 Special register Index register IX General-purpose Index register IY register Stack pointer sP Program counter PC 170489 Figure 3.2.3 Flag Register Configuration MPUZ80ASSP-15TOSHIBA TMPZ84C015B Sign flag (S) When the result of an operation is negative, the S flag is set to 1 . Actually, the content of bit 7 of accumulator is stored in this flag. Zero flag (Z) When all bits turn out to be 0 s after operation, the Z flag is set to 1. Otherwise, it is set to 0. With a block search instruction (CPI, CPIR, CPD or CPDR), the Z flag is set to 1 if the source data and the accumulator data match. With a block I/O instruction (INI, IND, OUTI or OUTD), the Z flag is set to 1 if the content of the B register used as the byte counter is 0 at the end of comparison. Parity/overflow flag (P/V) This flag has two functions. One is the parity flag (P) that indicates the result of a logical operation (AND A, B etc.). The P flag is set to 1 if the parity is even asa result of the operation on signed values by twos complement. It is reset to O if the parity is odd. With a block search instruction (CPI, CPIR, CPD or CPDR) anda block transfer instruction (LDI or LDD), the P flag indicates the state of the byte counter (register pair B and C). It is set to 1 if the byte counter is not 0 and reset to 0 when the byte counter becomes0 (at the end of comparison or data transfer). The content of the interrupt enable flip-flop (IFF) is saved to the P flag when the contents of the R register or I register are transferred to the accumulator. The other use of the P/V flag is the overflow flag (V) that indicates whether an overflow has occurred or not as a result of an arithmetic operation. The V flag is set to 1 when the value in the accumulator gets out of a range of the maximum value +127 and the minimum value 128 and therefore cannot be correctly represented as a twos complement notation. Whether the P/V flag operates as the P flag or V flag is determined by the type of the instruction executed. Carry flag (c) The C flag is set to 1 if a carry occurs from bit 7 of the accumulator or a borrow occurs as a result of an operation. The following two flags are not available to the programmer for the test and set (1)/reset (0) purposes. They are internally used by the MPU for BCD arithmetic operations. Half carry flag (H) The H flag is used for holding the carry or borrow from the low-order 4 bits of a BCD operation result. When a DAA instruction (decimal adjust) is executed, the MPU automatically uses the H flag to adjust the result of a decimal addition or MPUZ80ASS5P-16TOSHIBA TMPZ84C015B (c) (2) (3) (a) subtraction. Add/subtract flag (N) In BCD operation, algorithm is different between addition and subtraction. The N flag indicates whether the executed operation is addition or subtraction. For change of the flag state depending on the instruction, see 3.2.4 TMPZ84C015B Instruction Set. General-purpose registers (B, C, D, E, H, L) General-purpose registers consist of 8 bits each. They are used as 16-bit register pairs (BC, DE, HL) as well as independent 8-bit registers to supplement the accumulator. The B register and the register pair BC are used as counters when a block I/O, block transfer, or search instruction is executed. The register pair HL has various memory addressing features as compared with the register pairs BC and DE. Alternate registers (A, F, B, C', D, E', H, L) The configuration of the alternate register is exactly the same as that of the main registers. There is no instruction that handles the alternate registers directly. The data in the alternate registers are processed by moving them into the main registers by means of exchange instructions as shown below: EX AF, AF (AcA, Fe FP) EXX (BeB,CeC, DeD, EsR,HoH,LeL) When a hign-speed interrupt response has been requested within the system, these instruction can be used to quickly move the contents of the accumulator, flag registers, and general-purpose registers into the corresponding registers. This eliminates the need for transferring the register contents to/from the external stack during execution of the interrupt handling routine, thereby shortening the interrupt servicing time greatly. Special purpose registers {I, R, IX, !, SP, PC) Interrupt page address register (I} The TMPZ84C015B provides two kinds of interrupts: maskable interrupt (INT) and non-maskable interrupt (NMI). The maskable interrupt provides three modes (0, 1, and 2) in which the interrupt is handled. These modes can be selected by instructions IMO, IMI, and IM2 respectively. In Mode 2, any memory location can be called indirectly depending on the interrupt. For this purpose, the I register stores the high-order 8 bits of the indirect address. The low-order bits are supplied from the interrupting peripheral LSI. This scheme permits calling the interrupt handling routine from any memory location in an extremely short access MPUZ80ASSP-17TOSHIBA TMPZ84C015B (b) {c) (d) time. For the details of interrupts, see [4] Interrupt Capability. Memory refresh register (R) The R register is used as the memory refresh counter when the dynamic RAM is used for memory. This permits using of the dynamic memory in the same manner as the static memory. This 8-bit register is automatically incremented for each instruction fetch. While the MPU decodes and executes the fetched instruction, the contents of the R register are synchronized with the refresh signal to place the low-order 7 bits and A7RF on the address bus. This operation is all performed by the MPU and, therefore, dose not need a special processing by program. The MPU operation is not delayed by this operation. During refresh, the contents of the I register are placed on the high-order 8 bits of the address bus. Index registers (IX, IY) The two independent index registers IX and IY hold the 16-bit base address when used in the index addressing mode. In this addressing mode, the memory address obtained by adding the contents of an index register to the displacement value (for example, LD IX+40H) is specified. This mode is convenient for using data tables. Also these registers can be used separately for memory addressing and data retaining registers. Stack pointer (SP) The stack pointer is a 16-bit register to provide the start address information in the stack area in the external RAM. The content of the stack pointer is decremented at the execution of a CALL instruction or PUSH instruction or interrupt handling and is incremented at the execution of a RET instruction or POP instruction. At the execution of a CALL instruction or interrupt handling, the current content of the program counter is saved into the stack. At the execution of a RET instruction, the content is restored from the stack to the program counter. These operations are all performed by the MPU automatically. However, the other registers are not saved or restored automatically. For the storing of the contents of these registers, an exchange instruction (EX or EXX) for alternate register, a PUSH or a POP instruction must be used. When a PUSH instruction is executed, the contents of the specified register are saved into the stack. When a POP instruction is executed, the contents of the stack are moved to the specified register. These data are restored on a last-in, first-out basis. Use of the stack permits processing of multiple-level interrupts, deep subroutine nestings, and various data manipulation very easily. The stack pointer is not initialized in the hardware approach. Therefore, it is required to allocate the stack area in RAM to specify initialization (at the highest address of the stack area) in the initial program. MPUZ80ASSP-18TOSHIBA TMPz84C015B [2] (e) (ex) MEMORY The contents of the SP MEMO OO ADDRESS INSTRUCTION before the instruction (HEX) is accepted. c cS LOWER 2 > 1230 CALL 1500H FFF1 : : v uv : : FreB | co | 2 oO : 3 FreC | B2 | 3 1500 PUSH AF FFEF ; A=05, F=23 FFED | 23 | 9 5 1501 PUSH BC FFED ; B=B2, C=CO FFEE | 05 | @ i | FFEF | 33 o FFFO | 12 | : : : 1600 POP BC FFEB HIGHER | 1601 POP AF FFED 1602 RET ~ FFEF The foregoing example shows the stack pointer and stack operations in which the instructions starting with the CALL at address 1230H and ending with the RET at address 1602H have been executed. However, it is assumed that there is no instruction or interrupt other than shown above that uses the stack during the execution. When the value of the stack pointer before executing the CALL instruction at address 1230H indicates address FFF1H, address 1233H is stored at addresses FFFOH and FFEFH because the CALL instruction consists of 3 bytes, then the stack pointer is decremented. Similarly, the data are saved or restored sequentially according to the instructions. These stack and stack pointer operations are all performed automatically. Program counter (PC) The program counter holds, in 16 bits, the memory address of the instruction to be executed next. The MPU fetches the instruction from the memory location indicated by the program counter. When the content of the program counter is put on the address bus, the program counter is incremented automatically. However, it is not incremented with a jump instruction, a call instruction, or interrupt processing. Instead, the specified new address is set on it. With a return instruction, the content restored from the stack is set on the program counter. These operations are all performed automatically and therefore, no care is required for programming. Halt Capability When a HALT instruction has been executed, the MPU is put in the halt state. The halt capability can be used to halt the MPU against the external interrupts, thereby reducing the power dissipation. In the halt state the states of MPUs internal registers are retained. The halt state is cleared by reset or when an interrupt is accepted. MPUZ80ASSP-19TOSHIBA TMPZ84C015B (3] For the details of halt operation, see [3] Basic Timing. (1) (2) Halt operation When a HALT instruction has been executed, the MPU sets the HALT signal to 0 to indicate that the MPU is going to be put in the halt state. Actually, the MPU in the halt state automatically continues executing NOP instructions if there is the system clock input. However, the program counter is not incremented. This keeps the refresh signal generated when the dynamic memory is used. During halt, the MPUs internal states are retained. The TMPZ84C015B contains the clock generator/controller, easily implementing the clock input control for these halt operations. Releasing the halt state The halt state is cleared by accepting an interrupt (the INT or NMI signal input) or by reset (the RESET signal input). When an interrupt is accepted, the halt state is cleared and the interrupt handling routine is executed. However, a maskable interrupt (INT) cannot be accepted unless the interrupt enable flip-flop (IFF) is set. Note that when the halt state is cleared by the RESET signal, the MPU is reset and the program counter is set to 0. RESET Signal Holding the RESET pin at the low level (0) under the following conditions, the MPUs internal states are reset: (1) (2) (3) The supply voltage level is within the operational voltage range. System clock stabilization. Holding the RESET signal at the low level (0) for at least 3 full clock cycles. When the RESET signal goes high (1) , the MPU starts executing instructions from address 0000H after at least 2T state dummy cycles. When reset, the MPU performs the following processing: (1) Program counter O000H is set. (2) Interrupt The interrupt enable flip-flop (IFF) is reset to 0 to disable the maskable interrupt. For the maskable interrupt processing, mode 0 is specified. MPUZ80ASSP-20TOSHIBA TMPZ84C015B [4] (3) Control output All control outputs are made inactive (1) . Therefore, the halt state is also cleared. (4) Interrupt page address register (I register) The content of the R register becomes 00H. (5) Refresh register (R register) The content of the R register becomes 00H. The contents of the registers other than above and the external memory do not change. Therefore, they must be initialized as required. Interrupt Capability The interrupt capability is used to suspend the execution of the current program and execute the processing of the requested peripheral LSI. Normally, this interrupt processing routine contains the data exchange and transfer of status and control information between the MPU and the peripheral LSI. When this routine has been completed, the MPU returns to the state active before the interrupt has been accepted. The TMPZ84CO015B provides the non-maskable interrupt (NMI) and maskable interrupt (INT) capabilities which are detected by the NMI and INT interrupt request signals, respectively. A non-maskable interrupt, when caused by a peripheral LSI, is accepted unconditionally. This interrupt is used to support critical functions such as the protection of the system from unpredictable happening including power failure. A maskable interrupt can be enabled or disabled by program. For example, if the timer is used and, therefore, an interrupt is not desired, the system can be programmed to disable the interrupt. Table 3.2.1 lists the processing by interrupt source. (1) Interrupt enable/disable A non-maskable interrupt cannot be disabled by program, while a maskable interrupt can be enabled or disabled by program. The MPU has the interrupt enable flip-flop (IFF) . A maskable interrupt can be enabled or disabled by setting this flip-flop to 1 (set) or 0 (rest) through an EI instruction (enable) or a DI instruction (disable) in program. Actually, the IFF consists of two flip-flops IFF1 and IFF2. IFF1 is used to select between the enable and disable of a maskable interrupt. IFF2 holds the state of IFF1 before a maskable interrupt has been accepted. Both IFF1 and IFF2 are reset to 0 when any of the following conditions occurs, disabling an interrupt: MPUZ80ASSP-21TOSHIBA TMPZ84C015B @ MPU reset @ Execution of DI instruction Acceptance of maskable interrupt Both IFF1 and IFF2 are set to 1 when the the following condition occurs, enabling an interrupt: @ Execution of El instruction Actually, the waiting maskable interrupt request is accepted after the execution of the instruction that following the El instruction. This delay by one instruction is caused by accepting an interrupt after completion of the execution of a return instruction if the instruction following the EI instruction is a return instruction. In the above operation, the contents of IFF1 and IFF2 are the same. Table 3.2.1 Processing by Interrupt Source Interrupt Interrupt Source Priority | Programmed condition Vector addres return instruction Non-maskable interrupt 1 None Address 66H RETN (the falling edge of NMI) Instruction from Maskable interrupt (INT 2 IFF=1 Mode0O | peripheral LSI. (Note) becomes 0 at Normally, CALL or RST RETI instruction's last clock) instruction. Mode? | Address 38H. The address indicated by the data table (memory) Mode2 | atthe address specified by I register (high-order 8 bits) and data from peripheral LSI (low- order 8 bits, LSB = 0). Note: Mode 0 applies when the instruction from peripheral LSI is CALL or RST instruction. 170489 MPUZ80ASSP-22TOSHIBA TMPZ84C015B | Parity flag (RETN) (LD A, tor LD A, R) (Determination of \FF1 IFF2 actual INT enable | | | | (foar holding IFF1) Misable) Executed instruction 0 0 : MPU reset Di instruction INT acceptance 1 1 : Elinstruction RETN instruction when IFF2 = 1. 0 state of IFF1 : NMt acceptance before NMI acceptance 170489 Figure 3.2.4 Interrupt Enable Flip-Flop (IFF) When a non-maskable interrupt has been accepted, IFF1 is reset to 0 (interrupt disable) until an EI or RETN instruction is executed, so as to prevent from accepting the next interrupt. For this purpose, the state (interrupt enable/disable) of IFF1 immediately before non-maskable interrupt acceptance must be stored. This state is copied into IFF2 upon acceptance of a non-maskable interrupt. The content of IFF2 is copied into the parity flag at the execution of the following instructions, so that the copied data can be tested or stored: e The load instruction (LD A, I) to load the contents of the I register into the accumulator. e The load instruction (LD A, I) to load the contents of the R register into the accumulator. When the return instruction (RETN) from the non-maskable interrupt is executed, the contents of the current IFF2 are copied back to IFF1. If an operation which changes the contents of IFF2 (due to the execution of EI or DI instruction, for example) has not been performed during interrupt handling, IFF1 automatically returns to the state immediately before the interrupt acceptance. Table 3.2.1 lists the states of IFF1 and IFF2 after execution of interrupt-related instructions. MPUZ80ASSP-23TOSHIBA TMPZ84C015B Table 3.2.2 State of IFF1 and IFF2 Operation sequence IFF4 IFF2 Remarks MPU reset E] NMI acceptance LDA, | RETN LDA,R INT acceptance RETt El NMI acceptance DI RETN o eOoo., *0O #]4 #0 = oO *Orwr > *#0O ** += = Parity flag<-IFF2 IFF1-1FF2 Parity flageIFF2 (2) (a) 170489 Note: * =no change. Interrupt processing With a non-maskable interrupt, the internal NMI flip-flop is set to 1 on the falling edge of the interrupt signal, NMI. The state of this flip-flop is sampled on the rising edge of the last clock of each instruction to accept an interrupt. A maskable interrupt is accepted if the interrupt signal INT is low (0) on the rising edge of the last clock of each instruction and the interrupt enable state (IFF=1 and BUSREQ signal=inactive (1) ) is on. The following is the processing to be performed after a non-maskable interrupt and a maskable interrupt are accepted: Non-maskable interrupt (NMI) When a non-maskable interrupt has been accepted, the MPU performs the following processing: 1 The internai NMI flip-flop is reset to 0. 2 IFF'1 is reset to O, disabling the maskable interrupt. The contents of the IFFl immediately before the interrupt acceptance are copied into the IFF2 3 The contents of the current program counter are saved into the stack. 4 The instructions starting from non-maskable interrupt vector address 66H are executed. The non-maskable interrupt processing program terminates after executing the RETN instruction. This return instruction performs the following: 1 The contents of the current IFF2 are copied into IFF1. MPUZ80ASSP-24TOSHIBA TMPZ84C015B 2 The contents of the program counter are restored from the stack. Acceptance of non-maskable interrupt (NMI) | Execution of ordinary program | t Service routine Address 0066H Execution of RETN instruction 170489 Figure 3.2.5 Non-Maskable Interrupt Processing (b) Maskable interrupt (INT) When a maskable interrupt has been accepted, the MPU performs the following processings: 1 Both IFF1 and IFF2 are reset to 0, disabling the maskable interrupts. 2 The contents of the current program counter are saved into the stack. 3 A maskable interrupt is serviced in one of the three modes 0, 1 and 2. A mode is selected by executing the instruction IMO, IM1 or IM2 before the interrupt is serviced. The instructions are executed starting from the vector address corresponding to the selected mode. Mode 0 In mode 0, the interrupting peripheral LSI puts a restart instruction (RST) or a call instruction (CALL) on the data bus and the MPU executes the interrupt service routine according to that instruction. At reset, this mode is automatically set. Acceptance of interrupt in mode 0 | | Execution of ordinary program | t | sevariutne Address specified by CALL or Execution of RETI instruction RST from peripheral LSI. 170489 Figure 3.2.6 Interrupt Processing in Mode 0 MPUZ80ASSP-25TOSHIBA TMPZ84C015B e Mode 1 When an interrupt is accepted in mode 1, restart is performed from address 0038H. Therefore, the service routine for this interrupt is programmed from the address 0038H . Interrupt in mode 1 | | Execution of ordinary program | L[seveauine Address 0038H Execution of RETI instruction 170489 Figure 3.2.7 Interrupt Processing in Mode 1 e Mode 2 The interrupt processing in mode 2 requires a 16-bit pointer consisting of the high-order 8 bits of the I register and the low-order 8 bits (with the LSB="0) of the data fetched from the interrupting CTC or TLCS-Z80 family peripheral LSI. Therefore, the necessary value must be loaded in the I register beforehand. This pointer is used to specify the memory address in the table. The contents of the specified address and the next address provide the start address of the service routine. Therefore, use of this mode requires the table of the service routines start address (16 bits) to be set at appropriate location under software control . This location can be anywhere in memory. The LSB of the table pointer is set to 0 because a 2-byte data is needed to specify the service routine start address in 16 bits and start that address from an even-number address. In the table, the start that address begins with the low-order byte followed by the high-order byte as shown in Figure 3.2.8. MPUZ80ASSP-26TOSHIBA TMPZ84C015B Interrupt in mode 2 | Execution of ordinary program | Table 4 Service routine Execution of | register CTC or TLCS-Z80 family | Higher : Lower RETl instruction 8 bits | 7 bits | 0 / byte | peripheral LS! 170489 Figure 3.2.8 Interrupt Processing in Mode 2 Mode 2 is used in the daisy chain interrupt processing using the CTC and TLCS- 780 family LSI. The CTC and TLCS-Z80 family peripheral LSIs all contain the interrupt priority controller in daisy chain structure. In this interrupt structure, the interrupt request signals are connected one after another and given priorities for processing when two or more maskable interrupt requests occur at a time. Only the interrupt vector from the peripheral LSI having the highest priority is put on the data bus. By receiving the interrupt vector in mode 2, the processing for that peripheral LSI can be performed. When an interrupt requested by a peripheral LSI having a priority higher than that of the current peripheral LSI during the execution of the interrupt processing routine, the higher priority interrupt can be enable by the El instruction to form a interrupt nesting. The maskable interrupt processing program terminates by executing an RETI instruction. This return instruction performs the following processings: @ Restores the content of the program counter from the stack. Notifies the requesting peripheral LSI of the termination of interrupt processing. MPUZ80ASSP-27TOSHIBA TMPZ84C015B 3.2.3 MPU Status Transition Diagram and Basic Timing [1] The following describes the MPU status transition and the basic timing of each MPU operation. Instruction Cycle Each TMPZ84C015B instruction is executed by combining the basic operations of memory read/write, input/output, bus request/acknowledge, and interrupt. These basic operations are performed synchronizing with the system clock (the CLK signal). One clock period is called a state (T). The smallest unit of each basic operation is called a machine cycle (M), Each instruction consists of 1 to 6 machine cycles and each machine cycle consists of 3 to 6 clock states basically. However, the number of clock states in a machine cycle can be increased by the WAIT signal described later on. Figure 3.2.9 shows an example of the basic timing of a 3-machine-cycle instruction. The first machine cycle (M1) of each instruction is the cycle in which the Opcode of the instruction to be executed next is read (this is called the Opcode fetch cycle). The Opcode fetch cycle basically consists of 4 to 6 clock states. In the machine cycle that follows the Opcode fetch cycle, data is transferred between the MPU and the memory or peripheral LSIs. This operation basically consists of 3 to 5 clock states. T cycle <__} cLK 4 Maachine cycle My M2 M3 (Opcode fetch) (Memory read) (Memory write) Cycle instruction 170489 Figure 3.2.9 Example of MPU Basic Timing (3-Machine-Cycle Instruction) MPUZ80ASSP-28TOSHIBA TMPZ84C015B {2] Status Transition Diagram RESET = 0 31: M1 IMMEDIATELY AFTER ACCEPTING INT? eR] fw hrws TW WAIT TW Sows TW WAIT XQ r NO 73 __Tyes iS M 3T STATE Doe Mi=1 NO FALT YES No INSTRUCTION 2 HALT =0 NO 14 1S MAT STATE > NO M1 CYCLE? NO YES TS 1S M ST STATE De 16 + TX WAIT N 0 YES BUSREQ =0 } T NO NO HALT = 1 Figure 3.2.10 Status Transition Diagram 170489 MPUZ80ASSP-29TOSHIBA TMPZ84C015B [3] Basic Timing (1) Opcode fetch cycle (M1) In the Opcode fetch cycle, MPU fetches an Opeode in the machine-language codes in memory. This is also called the M1 cycle because it is the first machine cycle to execute each instruction. Figure 3.2.12 shows the basic timing of a basic Opcode fetch cycle. In clock state T1, the content of the program counter is put on the address bus. The MI signal goes 0, indicating to the MPU that this is the Opcode fetch cycle. At the same time, MREQ and RD signals go 0. When the MREQ signal goes 0, the address signal has already been stabilized. Therefore, this signal can be used for the memory chip enable signal. The RD signal indicates that the MPU is ready to accept the data from memory. By these signals, the MPU accesses memory to fetch the Opcode in the instruction register. The MPU samples the WAIT signal on the falling edge of clock state T2. If the WAIT signal is 0 on the falling edge of clock state T2 and the following wait state (TW), the next state becomes clock state TW. Figure 3.2.13 shows the delay state of the Opcode fetch cycle caused by the WAIT signal. The data (Opcode) on the data bus is fetched on the rising edge of clock state T3 then, the MREQ, RD, and MI signals go 1. In clock state T3, a memory refresh address is put on the 8 bits consisting of the low-order 7 bits of the address bus and the A7RF corresponding to bit 8 and the RFSH signal goes 0 and the MREQ signal goes 0 again. This signal indicates that the memory refresh cycle is on. At this time, the contents of the I register are put on the high-order 8 bits of the address bus and the 7 bits of the R register contents and the A7RF signal corresponding to bit 8 are put on the low-order 8 bits of the address bus. By using the RFSH and MREQ signals, memory refresh is performed in clock state T3 and T4. However, the RD signal remains 1 because the contents of the memory refresh address are not put on the data bus. The address bus of 8 bits consisting of the address low-order 7 bits of address (A6 through AO) and the A7RF are used as the 8-bit refresh address. That is, when A7RF is used for the refresh address, signals OOH through FFH are output. In cycles other than the refresh cycle, the signal equivalent to A7RF are output. However, at reset, the signals to be output are uncertain. Figure 3.2.11 shows the refresh timing. MPUZ80ASSP-30TOSHIBA TMPZ84C015B CLK T2 T3 T4 T1 T2 | | 73 | {74 | {T1, wp As~Ao YX RFSH ADDR=7FH X X RFSH ADDR=00H_ X ; RFSH | | | ATRF Ay \ / Ay / \ Ay 170489 Figure 3.2.11 Refrish Timing In clock state T4, the MREQ signal returns to 1. The refresh address is kept output until the rising edge of the clock state T1 in the next machine cycle, keeping the RFSH signal set to 0. The cycle delay state caused by setting the WAIT signal to 0 is the same in the memory read/write, input/output, and maskable interrupt acknowledge cycles. The diagram of the cycle delay state caused by the WATT signal set to 0 is omitted in the following description. _ Micyle - T1 T2 T3 T4 T1 CLK vo \ / Le Ao~A15 x Proagram counter Refresh address x. MREQ ~~ [ \ | Sf | = > Mi \ < | Do~D7 {_Inpu 7 U \ ie 170489 Figure 3.2.12 Opcode Fetch Timing MPUZ80ASSP-31TOSHIBA TMP284C015B a Micycle T1 T2 TW Tw T3 Ts CLK _f \Y rf fy Ao~ Ais xX _ Program counter Refresh address MREQ 9 [ \_ [\ Lf Ty ns oe / wt YN / Walt f [AY fT / RFSH \ [ Figure 3.2.13 Opcode Fetch Timing Including Wait State (2) Memory read/write operations for the Opcode fetch cycle) in the same diagram for convenience. 170489 Figure 3.2.14 shows the basic timing of memory read/write operations (except In each operation, the memory address signal to read/write data on the address bus is output in clock state T1. The operation in which the WAIT signal is sampled in clock state T2 and the following TW state is the same as the Opcode fetch cycle. RD signals. The MPU reads this data. Im memory read, memory data is put on the data bus by the address MREQ, and In memory write, the memory address signal is put on the address bus then the MREQ signal is set to 0 to put the write data onto the data bus. When the data bus has been stabilized the WR signal is output in clock state T2. The WR signal can be used as the memory write signal. MPUZ80ASSP-32TOSHIBA TMPZ84C015B CLK Ao~A15 s ay ml 2 < Formemoryreadcycle = >\<_ Formemorywrite cycle 9 >| 11 T2 T3 11 T2 T3 fF} MM HY KX Memory address Memory address Xx ~~. \ | \ [\ | \ [ LJ Sst {input} Data output \ / \ / \ 170489 Figure 3.2.14 Memory ReadMrite Cycle Timing input/output operations Figure 3.2.15 shows the basic timing of input/output operations. The feature of the I/O operation timing is that, regardless of the state of the WAIT signal in clock state T2, the I/O cycle automatically goes in the wait state (TW*) after clock T2. The WAIT signal is sampled on the falling edge of TW*. If the WAIT signal is 0 on the falling edges of TW* and the following clock state, the I/O operation enters into clock state TW*. Clock state TW* is inserted because the IORQ signal goes Q in clock state T2, so that it is too late to sample the WAIT signal after decoding the I/O port address. In each of input and output operations, the I/O port address is put on the low-order 8 bits of the address bus in clock state T1. On the high-order 8 bits, the contents of the accumulator or B register are output. In clock state T2, the TORQ signal goes 0 instead of the MREQ signal. The IORQ signal can be used as the chip enable signal for a peripheral LSI. In an input operation, the contents of the input port are read onto the data bus by the address, {ORQ, or RD signals. The MPU reads this data. In an output operation, the output port address and the output data are respectively put on the address bus and data bus in clock state Tl, then the IORQ and WR signals go 0 in clock state T2. The WR signal can be used as the output port write signal. MPUZ80ASSP-33TOSHIBA TMPZ84C015B (4) T1 T2 Tw* T3 T1 CLK fk \Sk* \S } KK \f \ Ag~Az xX. Port address xX TORQ a / RD / Read cycle (input) Do~D7 + Input --____ WAIT / \ WR / Write cycle (output) Do~D7 Output 170489 Figure 3.2.15 1/0 Operating Timing Bus request and bus acknowledge operations Figure 3.2.16 shows the basic timing of bus request and bus acknowledge operations. The address bus (AQ through A15), data bus (DO through D7), MREQ, IORQ, RD, and WR signals controlled by the MPU can be put in the high-impedance state (floating) to electrically disconnect them from the MPU. This operation, after sampling the BUSREQ signal on the rising edge of the last clock of each machine cycle, starts on the rising edge of the next clock if this signal is found 0. Subsequently, these buses are controlled by external peripheral LSIs. For example, data can be directly transferred between memory and these peripheral LSIs. This state is cleared if the BUSREQ signal is found1after sampling it on the rising edge of each subsequent clock state (TX), and enters into the next machine cycle. During the floating state, the BUSACK signal goes 0 to indicate it to the peripheral LSIs. In this state, however, no memory refresh is performed and, therefore, the RFSH signal is set to 1. Hence, to maintain this state for a long time with a system using dynamic memory, memory refresh must be performed by the external controller. Note that, in the floating state, neither maskable interrupt (INT) nor non- maskable interrupts (NMI) can be accepted. MPUZ8DASSP-34TOSHIBA TMPZ84C015B BUSREQ \ Each machine cycle -____-|____. Bus enablestate ~ Last T state TX TX TX T1 CLK VT NN NNN ON Floating state Ao~At5 rr -< MREQ, RD, peated WR, IORQ << RFSH S 170489 Figure 3.2.16 Bus Request and Bus Acknowledge Timing (5) Maskable interrupt acknowledge operation Figure 3.2.17 shows the basic timing of the maskable interrupt acknowledge. The MPU samples the maskable interrupt request signal (INT) on the rising edge of the last. clock of each instruction execution. Ifthe INT signal is found 0, a maskable interrupt is accepted except in the following cases: @ The interrupt enable flip-flop is reset to O. @ The BUSREQ signal is 0. When a maskable interrupt has been accepted, a special Opcode fetch cycle is generated. In this cycle, 2 clock states of wait state (TW*) is automatically inserted after the clock state T2. The WAIT signal is sampled on the falling edges of the second clock state TW* and the following clock state TW and, if the WAIT signal is found 0, the instruction cycle enters in the next clock state TW. In this Opcode fetch cycle, the IORQ signal goes 0 in the first TW* state instead of the MREQ signal while, in a normal Opcode fetch cycle, the MREQ signal goes 0 in clock state T1. This indicates to the maskable interrupt requesting LSI that the 8- bit interrupt vector can be put on the data bus. The MPU reads this data to perform interrupt processing. Therefore, the contents of the program counter put on the address bus are not used. Unlike an ordinary I/O operation, the RD signal does not go 0. MPUZ80ASSP-35TOSHIBA TMPZ84C015B In clock state T3 the memory refresh address signal is put on the address bus for memory refresh like normal Opcode fetch cycle and the RFSH signal goes 0. In the subsequent machine cycles (M2 and M3) , the contents of the current program counter are saved into the stack. In machine cycles M4 and M5, the contents of the I register (the high-order 8 bits) and the contents of the address indicated by the address of the vector (the low-order 8 bits) from the CTC and the peripheral LSI are fetched in the program counter. Instructions last M cycle {_______ yy Last T 1 T2 Tw Tw 73 CLK KN fF VS VPN ff \ INT AT / Do~A15 xX Program counter adda: TORQ > Do~D7 C Input WAIT / \ RD 470489 Figure 3.2.17 Maskable Interrupt Acknowledge Timing (6) Non-maskable interrupt acknowledge operation Figure 3.2.18 shows the basic timing of non-maskable interrupt acknowledge. When the non-maskable interrupt request signal (NMI) goes low, the internal non-maskable flip-flop is set to 1. The NMI signal is detected in any timing of each instruction. However, the internal NMI flip-flop is sampled on the rising edge of the last clock of each instruction. Therefore, the NMI signal should go low by the last clock state of an instruction. MPUZ80ASSP-36TOSHIBA TMPZ84C015B The Opcode fetch cycle for non-maskable interrupt request acknowledge is generally the same as the ordinary Opcode fetch cycle. However, the Opcode on the data bus at the time is ignored. The contents of the current program counter are saved into the stack in the subsequent machine cycles (M2 and M3). In the following machine cycle, the operation jumps to address 0066H, the non-maskable interrupt vector address. The machine cycles after these depend on the contents of the fetched Opcode. fast Mcycle Mi Last T state Ti T2 T3 T4 T1 clk _Y fy \ ae VT YS \ { \f RM OT ep - NMtinternal 7 T 7 latch Vee eee eee ee 4 Ao~Ai5 ~X~_Programcounter | X Refresh address a mt \ mREQ \ J / > \ / (7) RFSH \ [| 170489 Figure 3.2.18 Non-Maskable Inpterrupt Acknowledge Timing Halt operation When a HALT instruction is fetched in the Opcode fetch cycle, the MPU sets the HALT signal to 0 synchronized with the falling edge of clock state T4 to indicate it to the peripheral LSI and stops operating. If the system clock is kept supplied in the halt state, the MPU continues executing NOP instructions. This is done to output refresh signals when the dynamic memory is used. The NOP instruction execution cycle is the same as the ordinary Opcode fetch cycle except the data on the data bus are ignored. The halt state is cleared when an interrupt is accepted or the RESET signal is set to 0 to reset the MPU. Figure 3.2.19 shows the halt state clear operation by interrupt acknowledge. An interrupt is sampled on the rising edge of the last clock (clock state T4) of the NOP instruction. A maskable interrupt can be accepted when the INT signal is 0. A non-maskable interrupt is accepted when the internal NMI flip-flop which is set on the falling edge of the NMI signal is set at MPUZ80ASSP-37TOSHIBA TMPZ84C015B 1. However, it is required that the interrupt enable flip-flop is set to 1 for a maskable interrupt to be accepted. The interrupt processing for the accepted interrupt starts from the next cycle. However, when the supply of the system clock from the CGC has been stopped by the power down operation, it is required to restart the supply of the system clock and input the INT signal until the execution of one instruction is completed or the RESET signal until 3 clocks are output. Figure 3.2.20 shows the timing of clearing the halt state caused by power down. For the reset operation, see (8) Reset operation . Note that the INT and NMI signals are shown on the same diagram in Figures 3.2.19 and 3.2.20 for convenience. (HALT instruction) (NOP instruction) M1 M1 M1 T4 T1 T2 T3 T4 T1 T2 CLK ft VSL VS VY VY rar INT \ \ If [oa a nS ne fa NMI --4t--2- Jj wi _ Lb meee ete see eet ee NMlinternal ~-~-L oot =-=) | 4 4} bom eedowlee latch 7 - 4. e--- Figure 3.2.19 Timing of Clearing Halt State Caused by Interrupt Acknowledge Clock supply stop Restarting clock supply ; . from CGC from CGC | NOP instruction | I NOP instruction 1 i | | I T4 T1 T2 T3 T4 T1 T2 T3 T4 T1 T2 NMI internal latch INT 170489 Figure 3.2.20 Timing of Clearing Halt State Caused By Power Down MPUZ80ASSP-38TOSHIBA TMPZ84C015B (8) Reset operation Figure 3.2.21 shows the basic timing of reset operation. To reset the MPU, the RESET signal must be kept at O for at least 3 clocks. When the RESET signal goes 1, instruction execution starts from address 0000H after a dummy cycle of at least 2T clock states. M1 of address 0 5 _$$_$____ T1 TN NN ND NN NS <- Dummycycle 3 ~ D S 3] 9 Y I I 1 t I 1 I i I I I 1 l I 1 i I I i I 1 t { L dlz $3 ~ E O| if 3 a Oo a bar) wi x a Cc a > oO A x BI oe | 170489 Figure 3.2.21 Reset Timing To clear the power down state by using the RESET signal, the RESET signal must be input until 3 clocks or more are supplied by restarting the supply of the system clock from the CGC. MPUZ80ASSP-39TOSHIBA TMPZ84C015B (9) Evaluation operation Each of the MPU signals (A0 through A15, DO through D7, MREQ, IORQ, RD, WR, HALT, MI, and RFSH) can be put in the high-impedance state by EV and BUSREQ signals to electrically disconnect them from the MPU. Each M cycle Evaluation mode state _. Last T TX TX T1 ak f VP VP LPN NTF". BUSREQ / BUSACK || Floating stare Ao~Ais Drm p ona orcs < Floating stare Do~D7 eee ee eee < R, JOR a---ft--eedeee M1 HALT < EV / 170489 Figure 3.2.22 Evaluation Timing Figure 3.2.23 shows the block diagram of the TMPZ84C015B operating as an evaluator in the evaluation mode. The operations controlled by signals from the external MPU in the evaluation mode are the same as those of each device constituting the TMPZ84CO15B. (However, for the watchdog timer operations, see WDT Operational Description because the watchdog timer is of random logic configuration.) For the electrical characteristics and timing of each device, see Inactive State. MPUZ80ASSP-40TOSHIBA TMPz84C015B XTAL1 XTAL2 Mi HALT = CLKOUT CLKIN CLK Ms1 HALT MS2. coc M1 NMI Zz s NMI Ag~Ats Controller ~*~ mi uw mm 4 2 S Do~D7 ZC/TOo 5 ZC/TO3 CLK/TRGo 5 CLK/TRG3 M7 RESET IE WR RFSH Do~D7 EO CLK #FO #F1 Watchdog timer & reagisters F4 AT-RESET MS1,MS2 170489 Figure 3.2.23 Block Diagram of the TMPZ84C015B Functioning As Evaluator MPUZ80ASSP-41TOSHIBA TMPZ84C015B 3.2.4 TMPZ84C015B Instruction Set This subsection lists the TMPZ84C015B instruction codes and their functions. The table below lists the symbols and abbreviations used to describe the instruction set. The symbols which require special attention are described in the locations in which they appear. e Symbols (1/2) Classification Symbol Meaning Register 9 Register B, C, D, E, H, L, A, t Register pair BC, DE, HL Stack pointer SP q Register pair BC, DE, HL, AF p Register pair BC, DE Index register Ix Stack pointer sP Ss Register pair Bc, DE Index register tY Stack pointer SP tH Higher register of register pair (B, D, H) Higher 8 bits of stack pointer (SP) aH Higher register of register pair (B, D, H, A) IXy Higher 8 bits of index register IX Yu Higher 8 bits of index register lY PCH Higher 8 bits of program counter (PC) tL Lower register of register pair (C, E, L) Lower 8 bits of stack pointer (SP) GL Lower register of register pair (C, E, L, F} IX, Lower 8 bits of index register IX IL Lower 8 bits of index register IY PCL Lower 8 bits of program counter (PC) rb Bit b (0-7) of register (B, C, D, E, H, L, A) 120489 MPUZ80ASSP-42TOSHIBA TMPZ84C015B Symbols (2/2) Classification Symbol Meaning Memory mn Memory address represented in 16 bits. m indicates higher 8 bits and n, lower 8 bits. (HL)p Bit b (0-7) of the contents of the memory address indicated by register pair HL. (IX+d)p Bit b (0-7) of the contents of the memory address indicated by the value obtained by adding 8-bit data d to the content of index register IX. (IY +d)}bp Bit b (0-7) of the contents of the memory address indicated by the value obtained by adding 8-bit data d to the content of index register IY. Flag change symbol 0 Reset to 0 by operation. 1 Setto 1 by operation. - No change * Affected by operation x Undefined P Handled as parity flag. P=0: odd parity P=1: even parity Vv Handled as overflow flag. V=0: No overflow V=1: Overflow Operator < Transfer e Exchange + Add - Subtract A Logical and between bits. Vv Logical or between bits. BS Exclusive or between bits Others \FF Interrupt enable flip-flop cY Carry flag Zz Zero flag 120489 MPUZB80ASSP-43TOSHIBA TMPZ84C015B TMPZ84C015B Instruction Set (1/9) IFF in Flag column indicates that the content of the interrupt enable flip-flop is copied into the PV flag. ITEM Object code CLASSI A 5 euncti -FICA. mnemonic Binary unction TION 543 210 a Pea ie At Ee Sef creer ne stnunnenanunnapurdedenddecdecdect o (HL}+n 4 < B <t a e a o (mn), A \ ata Ed aio os BE ao 1 wo Note : 1g means any of the registers A,B,C, D,E,H, L. ere 990 goo 001 10 O11 100 101 111 120489 MPUZ80ASSP-44TOSHIBA TMPZ84C015B TMPZ84C015B Instruction Set (2/9) ITEM? Object code No. | No. CLASSI bl ; Flag or | oF FICA- ic Binary Hex Function - - cy. | STA. TION 76 543 210 PPV: ces | tes LD TY,mn 11 111 101 FD TYemo - 4] 14 00 100 001 21 na ann nan n mm mam mmm m . __ wd i Gan) seeefe Biot aie seo iic(aneiy ceeneeeeeceaeeaanan ee eantnses ie ae Ao on onn a Le(mn) BC | 00 om mmm mmm m OE] O01 wl i jaay ceeeeecde Taare ED guedamsty oe set acl 10 01 tti O11 4B+tx 10 tie(mn) SP | 11 11011 101 | oD TXye(mn+1) eT 20 00 101 010 | 2A IXLe(mn) nn nan nnn n Of eeesggegenstenenf fm fn ee ceapseengueeseensseeenncecesnssst ontefennsdpeen fetegunctsposesedieneefersef ccc ses q |UD IY,(mn) 41411 101 | FD Tyye(mn+1 6| 20 00 101 010 2A TYL (mn) 4 qn ann nan a mm mmm mmm mo fade < Ca Gey aL So i66 bid | spon antiye ce ceaaeasgeseceaeeeatenaaeenaap eae sp eceedesceadieenebereedieeseeepeessepeerey ig nn ann nnn n (mn }el a mm mmm mmm Mb ieca dessa tececcpeceredl we ina seep Wier ae 1 gece (aeiyety seececceaceeececeeatnenan nee fecseeboer cbse deetsedesseipecenenieeseegerers Tie r 01 ttO O11 434tx 10 (ma)etL o nn ann ann n mm mmm mmm m he ae a der ap (anviyerig ceeeeceseteecesetsenen ee dinssslessachecceteeseeteescstaneaes crates deneeabers Tse - 00 100 010 (| 22 (ne IX an nna ann n fam mmm mmm m wen Gina} aot Mi gee EB (ansiyetig bereeeesteeeereeserseeee fen eT s0 00 100 Dio =| 22 (mn)e1Y Tapa Bc 00 DE | 01 HL | 10 AF | 11 que (SP+1),qie(SP), SPeSP+2 Bh oti ft age fie (SP4iy TRe(S) seteeeeteeee dee 11 100 001 1 SPeSP+2 41 141 101 FD Tyyt(SP+1) ,1Y_#(SP) 11 100 001 El SPeSP+2 1 Note : tisany of the register pairs BC, DE, HL, SP. qis any of the register pairs AF, BC, DE. HL. (PAIR),;, (PAIR), refer to high order and low order eight bits of the register pair respectively. (Ex} BC, = C, AFy =A. wf : EXCHANGE 120489 MPUZ80ASSP-45TOSHIBA TMPZ84C015B TMPZ84C015B Instruction Set (3/9) ITenAr Object code No. | No. CLASSI A bh ; Functi Flag oF | oF FICA- mnemonic Binary Hex unetion TION 76 643 210 w oO Zz uy fex (sPyty Var air tor Fo TYyo(SP+1) w 11 100 011 | E3 IYL@(SP) LOL 11 101 101 | ED (DE }+(HL) , DEDE+1 teseetteestestentessseeade 10/100 G00. [AO J HUSHL+1 BCeBC1 LDIR 11 101 101 [ED (DE)(HL), DE+DE+1 +[BC< >0] 10 110 000 | BO HL+HL+1,BC+BC-1 Repeat until +[BC=0] Bf eeeeceteeeeetetsteafecesessecesestsseresbecsteseareseeresed | OHO oooeccececsecssssesseseesseeanes [top 11 101 101 ED (DE)(HL) DECDE-1 PO cece 10/101 000 748 LHESHL= 1 BCeB don. Z & | LODR i1 101 101 [ED (DE)(HL), DEDE~1 21] [Bc< >0] ew 10 111 000 =| Ba HL+HL-1,BC+BC-1 Repeat until 16 [Bc=0] Tc cccssssusteadf essseesseeteeseeefeccccceceseeeeh BOAO cc ecceeesssseessseeesesseefoseesfevesdesesdusecfiseedeueerbecodecssfrocsebcooee xx [CPI 11 101 101 | p A-(HL) feeceesessssssnsserved to 100 001 Jat | MLeML+1 BCeBCm td a [PIR 11 101 101 | eb A-(HL) HLHL +1, BC+BC-1 +[BC< >0 & ae Repeat until A< > (HL)] Mie vieesttreeseestenesopuseecternatictseeteceesseoeresf REpOMtUMEL ALCMLY orBC=O Pt EE a a6 R[BC=0 or 4) 16) ae (HL)} A-(HL},HLHL-1, BC+BC-1 Vos] 21] -pec< >a 8 Repeat until A=(HL)or BC=0 A< > {KL)] x[BC=0 or slusdnethceeeeeeeesseaseassensucusacasterss es 5 A= (HE)] {rer B | 000 a c | 001 Spit eee Se mee Og dd aca cseeeeeeeceneussstervarsnsnrteeeficseddssesdasssdasadundeesedscosdsssferceb soc o | 010 vu 2 E | 011 uO 2 H {100 mt feesestestetteeceeeesee f OF Odd ddd | 101 afaat a z2 _-__. Tosca cece ene ee een OLD ccsesssceesessssssesnusessssssenmssfasedieedesesdeetecdedeedecdccee u b w Bhan cceentetee| OM S dd dL ecenesereessssssesseessssssnnnnnates) ccatusdesdesntndemedeecd cL. x A,(1Y+d)} < be Oise tteccteeccener sed mann ec cseecssnefesstssessuasersveessutecstesessvitssseeres| seasefesseedccosdenedesns deasuebeteed ccc cc. tbe rt acces eee ee ser sereteealversrt dons deesscccreserersrsetimeeetse | ctanen dead dette he P27, (1X+d) 10 010 110 | 96 detstetteteteteececeees Gd Bd ddd ccd ccccscssessssessntesssessecssseersetessees sup (I+d) | 11 411 101 | Fo ArA-(1+d) 10 010 110 | 96 dd ddd ddd [a Note : *M PA flag is if the result of BC ~ 1 =0, otherwise P/V = 1. *N Z flag is 1 if A =(HL}, otherwise Z=0. | lindicates the total condition of the number of cycles and states indicated by arrow. ft means any of the registers A,B, C,D, E, H, L. 120489 MPUZ80ASSP-46TOSHIBA TMPZ84C015B TMPZ84C015B Instruction Set (4/9) Items Object code No. | No. CLASSI bl - | Flag or | oF -FICA Mnemonic Binary Hex Funetion cy. | STA. TION reer B | coo C | 001 O1010 A, (iX+d) E lou # | 100 L | 101 A, (1Y+d) Ali 1 < uv vo o - a z <q uv B uw = x B oe < oa oO (144) AcAy(1+d) (1X+d} A-(1%+d) (1+d) A-(I+d) (HL)+(HL)+1 (1X4+d) (IX+d)e(LA+d)+1 Note : rmeans any of the registers A,B,C, D, E, H, L. 120489 MPUZ80ASSP-47TOSHIBA TMPZ84C015B TMPZ84C015B Instruction Set (5/9) ITEM? No. No. CLASSI bl OF OF . Function FICA- mnemonic - cy. STA. TION :C | cces] tes uw TINC (1+d) (TY +d)}e(1+d) +1 6| 23 b z | rant FSR Mf 00 2N0 Ot 188 pub e (Hea aes ix ie ix y brie 3 [ar B}o00 z7 (1X+d) c | 001 zo tu D}Oo10 o E}oit Pd fi eee eee eet e eee eee e nee - DEC {I+) Ki 100 = Lj 101 oo A}aiit GENELAL-PURPOSE |THMETIC AND MPU CONTROL /AND AR Set interrupt mode2 TYely-1 HLeHL+t ws BE = | rica 7+ 0 Q e A Note : 55 is any of the register pairs BC, DE, HL, SP. PP is any of the register pairs BC, DE, IX, SP. tris any of the register pairs BC, DE, iY, SP. 120489 MPUZ80ASSP-48TOSHIBA TMPZ84C015B TMPZ84C015B Instruction Set (6/9) tems Object code No. | No. chassi Assembler - ; Flag or | oF ICA mnemonic Binary Hex Function CY. | STA TION 76 543 210 CLES | TES Tere B | 000 C |} oot Oo j}o10 E |} 011 E H | 100 oe dd ddd ddd |d (HL), (1X40), (1+d) L | 101 - 00 000 110 06 cee A] 11 tO aaa peg nen a uw t ee B a Lo r, (HL), (1X+d), (1Y+d} a Uivsa) seeeeeeee BRE AE Be aT De Pret Pee e Basesade aden s iaRe (ii) seeeeeeeeeefereteottintee tee dnettereecereeeed eae ceebaneedesereteneecberereedteceederriabecrerspereee ie r, (HL}, (1X+d), (1+d) TsO PHL PH Ebb de beedeedeeenpens RR (IX+d) 11 011 101 | 00 r, (HL), (1X+d) 11 001 011 cB dd ddd ddd d Oo 012 110 1E Note : rmeans any of the registers 4, B, C,0,,H, L. 120489 MPUZ80ASSP-49TOSHIBA TMPZ84C015B TMPZ84C015B Instruction Set (7/9) rem Object code No. | No. CLASSI bi . lag or | OF FICA- mnemonic Binary Hex Function _____.- cy. | sta TION 76 543 210 Sidi fH: PVE ic Jces| tes RR (1Y+d) 101 | FD eit O:X: PiQgie 6] 23 o11 [ce 70 : ne acco B | 000 C 001 0 | 010 E} ot [To ]< 0 H | 100 r, (HL), (iX+d), (1+d) L | 101 stetceedf ccesesseeecerseeetrer De eeeeeceeeeeee Afi bE uo x w uw e < be ae veccteceveseeceerecece,f GO, 111 110 | 3E . r, (HL), (IX+d), (1Y+d} Gea) Tr te PER G11 =} CB ddd d fees 140 3E . nee RT ae to eg pd ; 111 | 6F al7 43.0] [7 4B 0 | (wy Rap WMD ae PRD ee eee 1 01 100 111 | 67 att 430] [7 430 | HL) _ b | bbb eit br 11 001 011 1B 2/ ef 07000 e Of bbb cee | 40tb x Ber | Ce cdl desde dodo Ld. 1 | vot 9 BIT b, (HL) 11001 011 |cB ~~ 3] 12] 2 | oto to 01 bbb 110 46+bx8 Ze(HL)p 3] oi Co 4 | 100 au 5 | 101 6 | 110 Note : *1: Rotate digit left and right between the accmulator and location (HL). iit The content of the upper half of the accumulator is unaffected. The notation {HL}, indicates bit , (0 to 7) within the contents of the HL register pair. The notation f, indicates bit , (0 to 7) within the r register. 120489 MPUZ80ASSP-50TOSHIBA TMPZ84C015B TMPZ84C015B Instruction Set (8/9) Ive? Object code fo. | No. CLASSI bl . Flag oF | OF FICA. Binary Hex Function cy. | sta TION 76 543 210 cues | TES BIT b,IX+d) ] 11 011 101 DD 5] 20 11 001 011 | cB Ze (1X+d)b d wees 46 oo . BIT b,(TY+d} | FD 5| 20 ra cB Ze(I+d)y wn d w A6+bx . & beers ap oer oan Tee Pager oe sre =] 7 pec c reece eet teen erence eeapar eee e essere cet eeesdaneceaeernctenraratnrsccrcseenssmasnenerarmeeshenirenscsancsragacseaesreartrarenccsseuspiasmaccusaumarccesnvcatrcscccpacass B 900 2 |SET b,(HL) 4| 15] joot 4 | o10 SEG bey perenne steceeeade (ikeapet seceseceneeetansaceeaeenernedensendereeebesctdeataedeeseehseeanedeeeesdeeeeapeas eres] elon & H | 100 w wn Ly] tot ec cicetecceeee cee PAE DOB 110 | PCB BT ac ccesceceesnesteefeetesdestedesrehestebieseedreeteabeessderceaDeseensponees Attn w 6] 23, _b | bbb BE d 0} 000, C8 cssneenetsesetnfeee beer becsfinefetndeeseefiseefecefeseefne 1 | 001 RES bor 2 ge] 2] 010 Lo cnecececee eee ceeeee feet ere ed reco i naniserferseseasaneceesessereteessssescaeasaetasaee|oeece}earsopecesqecsesDesssebeeseeedeseeedeeree 3 O11 7101 REE ikea wefet te ceca tiemt ee detect nec nen cere [peceeeseeeeenn sneeeressersstsasessessesLeaeeebecssbersedeereefecsebereerrduansegercrepees sry 6 fat meee 6| 23 3] 10 e represents the 3) te extension in the relative oe beee. addressing PC+$+e 3 | 12 Jmode,a=e-2. YL eceeacsensnsenenenenenepee B88 Lc ccececcnseecenseeracscnseeteteneveeebecsesbesederessbeeersbaceedeeeseesfeeesedessespecesederrees eisa signed 2 S eseteeseeseeeefees seen aoe acereneersnenercnerenlcriparebiges bar deg Reeve prede donee Tewo's 12, complement 12 [number in the Perera reer rer eerrisrsyy s continue : range of 5 eee Too ier 000 P28 | 126<0 <129 ,PC+S$+e , RF iia 00" 180 o00 P20 continue SoHE ST To bio 900 Pie sR iit we ee ee eee od ce ceeereeeeeeee Been ee ae abe gee Ba eden pene | ccc} Condition Note: ase-2 inthe Opcode provides an effective address of PC +e as PC is incremented by 2 before the addition of e. Wz| 000| Non-Zero $ indicates the reference to the location counter value of the current segment. z| 001] zero The notation (HL),,, {IX +d), indicates bit , (0 to 7) within the contents of the register pair. Nc] 010} No-carry @ The notation r, indicates bit , (0 to 7} within the r register. c| 01a} carry a=e-2 in the op-code provides effective address of PC +e as PC is incremented by 2 prior to the addition of e. PO| 100| Odd Parity PE] 103} Even Parity P] 110] Sign Positive M] 111] Sign Negative 270489 MPUZ80ASSP-51TOSHIBA TMPZ84C015B TMPZ84C015B Instruction Set (9/9) ITEM Object code No. | No. CLASSI A bl | Flag or | oF FICA- mnemonic Binary Hex Function - ~ cy. | sta. TION 76 543 210 Siz: H PP/VE NEC | ces] tes a |dP (IX) O11 DD PC#(IX) : 8 = tees > PC+(1) 8 > Eg CALL soma cD (SP-1}PCq, (SP-2)<PCL a7] _ i [kkk 2 fn nnn nnn n PCemn GOH | 000 a O8H | 001 2 ition c ismet, same as 10H | 010 wu 18H | 011 20H | 100 PCLe(SP), PCYe(SP+1) 28H | 101 a 30H | 110 z 38H | 111 fete cet cernnneneestattesetceseaimnsdesecagestasbesteceertededtatssogteseensedeeneal ee Sache dd, 1 ou Return from interrupt Processing | PIPPy Pay PLe Pepe yy yyy ter : TOURING a ceaneecessesseecssessnseedecsecdesseceeeesdeecesucsesgeraves Hesse feseed|ccccudb coves 8 | 000 < Return from non-maskable | - a] 14] c]oo1 ~ interrupt Processing routing fd Eicsslessehaseesdesefeeeeafeccsbesee DY} o10 (SP~1) PCy, (SP-2)*PC - a [ar] & | ow PCyeO, PCi+j, SP+SP-2 H | 100 IN A,(n) t1 011 O11 OB At{ny - 3 [41 Ly] 101 cessesensenegueeeneeses DPAD~AT A>AB~A1S AL Perret teers be ssece see tsean ss eeeadecs sec sereaenenes [es araeascuersccarenerersases cotnraresssesarbearseEanesiiares teeta edeaseed ca ceaaceearsdencesPeeecrpesses > Picea ceeeeeteee res centn ea see reatecn es cica d cerneseesecececefevecanceccicseatstscesscensesssseststsies Pcesayeesseasaquassageccedeacasaneseaegescee| ecnvedh vonee b +[B<>0] > +[B=0] [*1 OPIN TERY CT er ete cesses t recta Leeeeadeceeeees Genetepiscebeaeeredieees teccePeem eae AO. DO frrtnee secre eeeeeessersPareseescrreerrtsttcedenrateseeesscssescdescesensrecssssascesenseteeecesstercesteses Pocssdscesthvtedeeerefeusechscseredecrttusasefecccecbecees 2 <[8<>0] [B= Sd ceeseteeceeeeef 1D TEL 010 BA | RepeatuntiBeO 0 EEE [a [68 {B 1 | Kb > a Ferenc te ttncnneb cata teeetsccceedscninncsmeretseefecusteseticucsacsersesessutessssesartoesas fecerebaee ceca dresesteveccderssesdosaeduesed|eosreafesees 5 Tan +BE<>0] +[B=0] |*2 (C)*(HL) BeB-2,HeeHL-2 PX EDX TY EK TY TPES Ver +(86>0] 10.111 010 6B Repeat until B=0 4 [16 } +[B=0]_ | Note: *M Ifthe result of B - 1 is zero, the Z flag is set, otherwise it is reset. @ AO through A15 indicate the address bus. [ Jindicates the total condition of the number of cycles and states indicated by arrow. "1 C-A0~A7 BA8~A15 ccc Condition 000 010 On 100 101 110 111 Non-Zero Zero No-Carry Carry Odd Parity Even Parity Sign Positive Sign negative 120489 MPUZ80ASSP-52TOSHIBA TMPZ84C015B TMPZ84C015B Instruction Map (1/7) MPU instruction Table ( I ) 8 ADD ADD ADD ADD ADD ADD ADD ADD ADC ADC ANC ADC ADC ADC ADC ADC A,B AC A.D AE AH AL AAHL) | AA AB ALC A,D AE AH AL AHL | AA : | 4 0 1 2 3 4 5 6 7 8 9 A B c D E F | | 0 nop LD LD INC inc | DEC to | rica | ex | avd | Lo pec | inc | DEC LD | RRCA BC,mn | (BC, A | BC B B B,n AFAF | HCBC | A(BC) | BC c c Gn 1 DINZ | LD LD INC INC | DEC LD RLA JE app | Lb pec | inc | DEC to RRA | e DE, mn | (DE},A DE DB D O.N e HL,DE | 4,{DE) DE E E En 2 Jurnz,| tp LD INC inc | DEC to | Daa | gaz | ano Lo pec | inc | DEC lo CPL e HL, mn J (mn), HL D H Hn e HLHL | Httmn) HL L L La 3. Jurne,} uD LD INC Inc | DEC LD sce | nc | apD | wD vec | inc | DEC LD CCF e | $P,mn |] (mn)a} sp (Hey | ou | CHL e HLsP | Afmn) | SP A A An 4 LD Lo LD Lo Lo Lo Lo LD LD LD LD Lo LD Lo LD LD pp | 8c |] ao | of | BH ] BL {BH |] BA | G8 | ac | cp | Ge | GH | Ge Jam] GA 5 LD LD iD LD LD tD LD to LD LD LO Lo LD LO LD Lo oe | pc | 00 | De | OH | DL Joy! BA | EB Ec | &O | | EH EL | e(HL)| 6A 6 Lo LD LD LO LD LD uo LD Lo LD LD Lo to Lo LD LD | He | He | HO } HE | HH | WL PRK] RA ] Le | up Le | oH ue Jum} oA | | 7 LD Lo LD LD Lo iw} HALT | otp LD LD LD Lo LD to LD LD | (HL. 8 f (HU,C | (HU,D | (HL E | (HLH | (HL), Hua] AB] ac | ao |] Ac | AK | AL TACHI] AA | g SUB SUB sup SUB SUB SUB SUB SUB SBC ssc SBC sBc SBC sac SBC SBC B c D E H Ll (HL) A ALB ALC A,D AE AH AL AHL) | AA A AND AND AND AND AND AND AND ANDO XOR XOR XOR XOR XOR XOR XOR XOR B Cc D E H L (HL} A B Cc D E H L (HL) A | B OR OR OR OR OR OR OR OR cP cP ce cP cP ce cP XOR 8 Cc D E H L (HL) A B Cc DB E H L (HL) A Cc RET POP JP NZ, dP CALL PUSH ADD RST RET RET JP Z, O CALL CALL ADC RST NZ BC mn mn NZ,mn BC An QOH c mn Z,mn mn A.n OBH B RET PoP JP NC, OUT CALL PUSH SUB RST RET EXX JPC, IN CALL @ SBC RST NC DE mn {n).& | NC, ron DE n 10H c mn A, (n) cmn An 1BH E RET POP JP PO, EX CALL PUSH AND RST RET JP JP PE, EX CALL @ xOR RST PO HL mn {SP}.HL | PO, mn HL n 20H PE (HL) mn DE,HL | Pl,mn n 28H F RET POP IPP, Dl CALL PUSH OR RST RET LD JPM, El CALL @ cP RST P AF mn P,mn AF n 30H M SP,HL mn M,mo n 38H 120489 Note D~@: Multi-Opcode Instructions (ref. Table (II )~()) MPUZ80ASSP-53TOSHIBA TMPZ84C015B TMPZ84C015B Instruction Map (2/7) Byte 1CB Instruction Table (II ) (Byte 2 of 2-byte Opcode) H 0 1 2 3 4 5 6 7 8 9 A 8 D E fF 0 RLC RLC RLC RLC RLC RLC RLC RLC RRC RRC RRC RRC RRC RRC RRC RRC B c D E H L (HL) A 8 c D E H L (HL) A 1 RL RL RL RL RL RL RL AL RR RR RR RR RR RR RR RR B c D E H L (HL) A 8 c D E H L (HL) A 2 SLA SLA SLA SLA SLA SLA SLA SLA SRA SRA SRA SRA SRA SRA SRA SRA B Cc D E H L (HL) A B c D E H L (HL) A 3 SRL SRL SRL SRL SRL SRL SRL SAL B c D E H L {HL) A 4 BIT BIT aT BIT BIT BIT BIT BIT BIT alt BIT BIT SIT BIT BIT BIT 0,B G,C 0,D OE 0,H 0b O,{HL) 0A 1,B 10 1,0 iE 1H Wb 1, (HL) LA 5 BIT BIT BIT BIT BITT BIT BIT BIT BIT BIT BIT BIT BIT SIT BIT BIT 2.8 2c 2,0 2,E 2,H 24 2, (HL) 2A 3,B 3. 3,0 3E 3,H 34 3, (HL) 3,4 4,8 4,C 4,D 4,E 4,H al 4, (HL) AA 5,B 5, 5.D 5,E 5,H SL 5, (Ht) 5A 7 BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT 6,B 6c 6D 6,E 6,H 6b 6, (HL) 6,4 7,B 7, 7,0 7,E 7,H 74 7, (HL) 7A 8 RES RES RES. RES RES RES RES RES RES RES RES RES RES RES RES RES 0.8 0, 0,0 0, Q,H O.k 0, (HL) 0A 1.8 1, 1,0 VE 1,H Uk 1, (HL) 1A 9 RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES 2,8 2. 2,0 2, 2.H 21 2, (HL) 2.4 3,B 3. 3,0 3, 3,H 3.4L 3, (HL) 3,4 A RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES 4,B 4, 4,0 4,E 4,H 4,0 4, (HL) 4A 5,B 5, 3.0 5,E 5,H 5.L 5, (RL) SA 8 RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES 6,B 6,C 6,D 6,E 6,H 6&L 6, (HL) 6A 7.8 7,C 7,0 7,E 7H 7L 7, (HL) 7A c SET SET SET SET SET SET SET SET SET SET SET SET SET SET SET SET 0,B 0c 0,D 0,E 0.H OL 0, (HL) OA 1,8 1, 1,D 1.E 1,H at 1, (HL) 14 BD SET SET SET SET SET SET SET SET SET SET SET SET SET SET SET SET 2,8 2. 2,0 2,E 2,H 2.L 2, (HL) 2A 3.8 3, 3,0 3,E 3,H 3,L 3, (HL) 3,4 E SET SET SET SET SET SET SET SET SET SET SET SET SET SET SET SET 4,8 4. 4,0 4e 4,H 4. 4, (HL) 4A 5.8 5.C 5,D 5,E 5.H 5.k 5, (HL) 5.4 F SET SET SET SET SET SET SET SET SET SET SET SET SET SET SET SET 6,8 6.C 6.D 6,E 6,H BL 6, (HL) 6A 7,8 7, 7,0 7,E 7,H 7b 7, (HL} 7A 120489 MPUZ80ASSP-54TOSHIBA TMPZ84C015B TMPZ84C015B Instruction Map (3/7) @ Bytel ED Instruction Table ( III ) ( Byte 2 of 2-byte Opcode ) H 0 1 2 3 4 5 6 7 8 9 A 6B D E F IN OUT sBc LD NEG RETN IMO LD IN QUT ADC LD RETI LD B, (C) {C), 8 HL,BC | (mn)ac LA Cc tc) <0), HL,BC | 8.mn) RA IN OUT sec LD IM1 Lo IN ouT ADC LD IM2 LD B, (C) (c),B HL,DE (mn), AI E.(C) (C),E HL,DE ] DE,(mn) AR IN OUT SBC LD RRD IN GUT ADC LD RLD H, (C) (Q.H HL,HE | (mopHu L(c} (bt HLL | HLtmn) SBC LD IN ouT ADC LD HL,SP | (mn) sp A,(C) (Q.A HL,SP | sp.tmn) LOL CPI INI OUT LDD cro IND OUTD LOIR CPIR INIR OTIR LODR CPOR INDR OTDR 120489 MPUZ80ASSP-55TOSHIBA TMPZ84C015B TMPZ84C015B Instruction Map (4/7) @ Byte1 DD instruction Table ( IV ) ( Byte 2 of 2-byte Opcode) oe 1 2 3 4 5 6 7 8 9 A B c D E F Q ADD IX.BC 1 ADD IX,DE 2 LO Lo INC ADD LD BEC IX, mn | (mny, 1x x IX, IX 1x,(mn} Ix 3 INC DEC LD ADD (IX +d) | UX+d) | (IX 4d) (X, SP n 4 LOB, LDC, (IX +d) (IX +d) 5 LDD, LDE, (IX +d) (1X +d) 6 LDH, LOL, (IX +d) (IX +d) 7 LD LD LD LD LD LD Lo LDA, (IX+d} | (X+d) | (IX+d) | Ux +d) (X4d) | x4 d) (IX +d} (IX + d) 8 c 0 E vH rm iA 8 ADD ADC1, (IX +d) (UX +d} 9 SUB SBCA, {IX +d) (iX+d)} B AND XOR (IX +d) (IX +d) 9 OR cP (IX +d) UX +d) c D E POP EX PUSH JP ix (SP), IX Ix (xy F LD SP, IX 120489 Note : Special 2 byte Opcode Instructions (ref. Table (VI )) MPUZ80ASSP-56TOSHIBA TMPZ84C015B TMPZ84C015B Instruction Map (5/7) @ = Bytel FD Instruction Table ( V ) (Byte 2 of 2-byte Opcade ) H L 0 1 2 3 4 5 6 7 8 9 A B Cc D E F 0 ADD ly,BC 1 ADD lY,DE 2 LD ID INC ADD Lb DEC I,nn | mn),ty lv ly, 1 SY, (mn) ly 3 INC DEC LD ADD (y+d) | (+d) | ( +d) 1Y. SP An 4 LDB, LDC, (Iv +d) (ly +d) 5 LOD, LDE, (IY +d) diy +d) 6 LDH, LDL, (Iv +d) {I +d) 7 LD LD LO LD Lo LD LD LDA, {l +d) | ( +d) | ( +d) | (ly +d) | UY 4d) | d+d) ay +d) (IY +d} +B ac DB ve iH al A 8 ADD ADDC A, (lv +d) (Iv +d) 3 SUB SUBC A {Il +d) (Iv +d) 8 AND xOR ay +d) (y +d) 9 OR cP dy +d) (ly +d) c Dd E POP Ex PUSH JP YY (5), 1Y ly ty) F LD SP, l 120489 Note : Special 2 byte Opcode Instructions (ref. Table (W)) MPUZ80ASSP-57TOSHIBA TMPZ84C015B TMPZ84C015B Instruction Map (6/7) @ Byte1DD Byte 2 CB Instruction Table (VI) ( Special case of 2-byte Opcode: Byte 3) y fe t 2 3 4 5 6 7 8 9 A 8 c D E F 0 RLC RRC (IX +d) (IX+d} 1 RL RR (X40) 0X+d) 2 SLA SRA (4d) (+d) 3 / SRL (X+d) 4a BITO, BIT 1, (X+d) (IX+d) 5 BIT2, BIT 3, (IX +d} (IX +d) 6 BIT 4, BITS, (X44) (+d) 7 BIT 6, BIT7, ux+d) (x+d) a RES Q, RES 1, (IX +d) (xX +d) 9 RES 2, RES 3, (K4d) (IX+d) A RES4, RES 5, (IX +d) (IX +d) B RES 6, RES 7, (x+d) (IX +d) SETO, SETI, (x+d) (IX +d) D : SET 2, SET 3, (K+) (iX4d) E SET 4, SETS, (IX+d) (K+ d) F SET6, SET 7, (X +d) (UX +d) 120089 MPUZ80ASSP-58TOSHIBA TMPZ84C015B TMPZ84C015B Instruction Map (7/7) Bytel FD Byte 2 CB Instruction Table ( VII) (Special case of 2-byte Opcode : Byte 3) H tt og 1 2 3 4 5 6 7 8 9 A 8 c E F 0 RLC RRC (ly +d} ly +d) 1 aL RR (I +d) (lv +d) 2 SLA SRA (iy +d) ay +d) 3 SRL (I% +d} 4 BITO, BIT I, dY +d) (iY +d) 5 BIT2, BIT 3, (v4d) (v+d) 6 BIT 4, BITS, ay +d) (Y+d) 7 BITS, BIT?, (l +d) {I +d) 8 RESO, RES 1, dy +d) (iy +d) 9 RES 2, RES 3, (iy +d) (+d) A RES 4, RESS, (ly +d) (y+d) B RES 6, RES7, ay +d) (Wy +d) SETO, SETI, (ly +d) ay +d) D SET 2, SET3, (iy +d) (v+d) E SET 4, SETS. (I +d) (iY +d} F SET6, SET 7, (Iv +d) (I +d) 120489 MPUZ80ASSP-59TOSHIBA TMPZ84C015B 3.3 CGC Operations This subsection describes the system configuration, functions, and basic operations of the clock generator/controller (CGC). 3.3.1 Block Diagram Figure 3.3.1 shows the block diagram of CGC. HALTMODESETTINGREGISTER HALT (HALTMR : bit 4, bit 3) INT NMI Mi RESET & at xtal2 | | 2 CLK <5 CONTROL CIRCUIT 0a xTaur_ | |= O A INTERNAL COUNTER 170489 Figure 3.3.1 Block Diagram 3.3.2 CGC System Configuration The internal configuration of the CGC is shown in Figure 3.3.1. The waveform from the external oscillator oscillated by the internal oscillator and divided by the divider is converted into the square wave for clock. The clock is controlled by the control circuit and the counter to be sent to the outside the CGC. The following describes the CGCs main components and their functions. (1) Clock Generation (2) Operation Modes MPUZB80ASSP-60TOSHIBA TMPZ84C015B [1] Clock Generation The CGC contains an oscillation circuit. By connecting oscillator to external pins (XTALI and XTAL2), the required clock can be generated easily. The CGC provides the clock whose frequency is 1/2 of the osicillation frequency. Figure 3.3.2 shows an example of oscillator connection. Cs Ik XTAL1 XTAL2 { IL L Cc Rs Cin > Cout > 170489 170489 Figure 3.3.2 (b) Oscillator Figure 3.3.2 (a) Example of Crystal Equivalent Circuit Connection (1) For the quartz crystal oscillator, use the MR8000-C20 (oscillation frequency 8 MHz) or MR12000-C20 (oscillation frequency 12 MHz) manufactured by Tokyo Denpa Company Ltd., or the equivalent, . Quartz Crystal ; Condition Product No Holder| Frequency | Cin | Cout Parameter (Typ.) Drive Level [Load * | Type MHz F F mv) Capacitance ype | (MHz) | (PF) | (PA) Tom] comA [Ria] rary MR8000-C20 8 22 | 33 | 4.00 | 30.0 _ MRs000-c14_| HC-49 8 20 | 20 |0.0189| 3.87 6.0 0.5 12.67 MR12000-c20] YU 12 33. | 33 | | 400 | 250 MR12000-C14 |(TR-49) 12 20 | 20 |0.0190}] 3.81 6.9 0.5 12.55 MR16000-C14 16 20 | 20 [0.0197| 4.00 57 0.5 12.20 MR20000-C14 20 20 | 20 | 4.00 | 25.0 0.5 14.00 020790 Note: The load capacitance in the condition does not include any stray capacitance. (2) For the ceramic resonater, use the CSA8.00MT, CST8.00MT (oscillation frequency 8 MHz) or CSA12.00MT, CST12.00MT (osillation frequency 12 MHz) manufactured by Murata MFG Co., Ltd. Product No. Frequency (MHz) Cin (pF) Cout (pF) CSA8.00MT 8 30 30 CST8.00MT 8 CSA12.0MT 12 30 30 CST12.0MT 12 CSA20.00MX040 20 5 5 Note: The CST8.00MT and CST12,.0MT need no outer capacitance. 020790 MPUZ80ASSP-61TOSHIBA [2] Operation Modes TMPZ84C015B The CGC has the capability to control 4 operation modes; Run, Idle 1, Idle 2, and Stop. Any one of them can be selected through the mode setting register (#F0: bit4, bit3: HALTMR). These modes become valid when the MPU executes a HALT instruction. Fetching a HALT instruction, the MPU sets the HALT signal to 0, indicating that it has been put in the halt state. After the execution of the HALT instruction, the CGC performs the operation in the specified mode. Table 3.3.1 shows the operations in each mode. Table 3.3.1 CGC Operation Modes Hait mode setting register (#F0:HALTMR) Operational Description Bit4 Bit 3 Only the internal oscillator operates, stopping the 0 0 IDLE1 Mode supply of clock outside. The clock output (CLKOUT) is held at 0. The internal oscillator continues operating with the supply of clock outside (CLKOUT) continued. When 0 ' IDLE2 Mode pins CLKOUT and CLKIN are connected, only the supply of clock (CLKOUT) to the CTC is continued. All internal operations are stopped. The clock 1 8 STOP Mode output (CLK) is held at 0. 1 1 RUN Mode The supply of clack outside is continued. 170489 The restart from the clock stop state in Idle 1, Idle 2 (these two modes are referred to as Idle mode hereafter), or Stop mode is performed by reset (RESET signal) or acknowledge of maskable interrupt (INT signal) or non-maskable interrupt (NMI signal). MPUZ80ASSP-62TOSHIBA TMPZ84C015B [3] Warm-up Time for Restart (from Stop mode) Releasing the halt state by interrupt acknowledge, the MPU begins executing interrupt processing. Therefore, when restarting the clock by the NMI or INT restart signal in the Stop mode, the oscillation must be fully stabilized before supplied outside. The CGC provides, by means of the internal counter, the warm-up time enough for the clock to stabilize frequency. The warm-up ends on the rising edge of the internal counter output dividing the oscillation frequency to start clock output. The warm-up time is equal to the time derived by dividing the frequency of the externally attached oscillator by gi Figure 3.3.3 shows the block diagram of the internal counter. Table 3.3.2 shows the relationship between the oscillation frequency and the warm-up time. In the restart by the RESET signal, no warm-up is performed for the quick operation at power-on. Therefore, expand the width of the RESET signal adequately to provide the warm-up time. we Ww a > Court O C COUNTER 215 + Cin CONTROL |, CLK OUT CIRCUIT (fe) CONTROL CIRCUIT baa ene nn new rn nnn nnn mtn nn nn nnn nnn nn nen nnn mn nnn nnn cnn as 170489 Figure 3.3.3 Block Diagram of internal Counter Table 3.3.2. Warm-up Time Counter output Warm-up Time fXTAL=12MHz | fXTAL=8MHz 2.7. ms 4 ms 215 214/ fc 170489 *fe=fypaL/2 MPUZ80ASSP-63TOSHIBA TMPZ84C015B 3.3.3 CGC Status Transition Diagram and Basic Timing The following describes the status transition and basic timing to be provided when the CGC operates. [1] Status Transition Diagram RESET = a TERNAL OSCILLATOR MODE NO CHANGE? CLOCK OUTPUT ] SUCCESSION - IDLE MODE INTERNAL CLOCK OUTPUT OSCILLATION STOP STOP (CLOCK OUTPUT STOP) STOP MODE CLock ouTPUT J STOP INTERNAL OSCILLATOR START IDLE MODE WARMING-UP (214/ fc) CLOCK OUTPUT START L L 170489 Figure 3.3.4 Status Transition Diagram MPUZ80ASSP-64TOSHIBA TMPZ84C015B [2] Basic Timing The following describes the CGC basic timing when the CGC clock output pin (CLKOUT) and clock input pin (CLKIN) are connected. (1) Operation at execution of HALT instruction The following describes the basic timing in each mode to be provided when the MPU executes a HALT instruction. The MPU sets the HALT signal to 0 synchronized with the falling edge of clock state T4 of the HALT Instruction Opcode fetch cycle (M1). This signal indicates to the CGC that the MPU is going to enter into the halt state. (a) Run mode (#F0: bit 4= 1, bit 3= 1: HALTMR) Figure 3.3.5 shows the basic timing in the Run mode. In the Run mode, the CGC continues supplying the clock to the outside even when the MPU is in the halt state. Therefore, the MPU continues executing NOPs during the halt state. The systems which need memory address refresh use this mode. M1 cycle |._ M1 cycle __|. M1 cycle T4 TI T2 T3 T4 T1 T2 T3 cu __| LI + LJ AL 4 L_ wa TN HALT J / \ \ Mi HALT instruciton ; Opecode fetch cycle . NOP execution < NOP execution 170489 Figure 3.3.5 Basic Timing in Run Mode (b) Idle 1 mode (#F0: bit 4=0, bit 3=0: HALTMR), idle 2 mode (#F0: bit 4=0, bit 3=1: HALTMR), and Stop mode (#F0: bit 4= 1, bit 3=0) Figure 3.3.6 shows the basic timing in the Idle modes and Stop mode. In these modes, the clock output is stopped with clock state T4 being 0 by the HALT signal and the MI signal which follows the HALT instruction. However, in the Stop mode, the CGCs internal oscillator also stops. MPUZ80ASSP-65TOSHIBA TMPZ84C015B T4 T1 T2 T3 T4 HALT instruction Opecode fetch cycle CLK Stopped }=> + NOP exection 170489 Figure 3.3.6 Basic Timing in idle and Stop Modes (2) Clock output restart from each mode The clock stopped state in the Idle or Stop mode is cleared by setting any of the following signals to 0 (for the system restart operation, see Subsection 3.3.4): e INT (level trigger input) = =6NMI (edge trigger input) e RESET (level trigger input) (a) Clock output restart from Idle mode Figure 3.3.7 (a) shows the basic timing for the sequence of the output restart from the clock stopped state in the Idle 1 mode. In the restart in the Idle 1 mode, the clock output is restarted in a relatively short delay time because the internal oscillator operates even in the clock stopped state. CLK OUT v4 r ? = wp voce (Clock stopped state) TL TL TL. Farr o" MI \ / INT MI RESE LI Figure 3.3.7 (a) Basic Timing for Sequence of Restart from Clock stopped State (idle 1 Mode) | 170489 MPUZ80ASSP-66TOSHIBA TMPZ84C015B (b) Clock output restart from Stop mode Figure 3.3.8 shows the basic timing for the sequence of the restart from the clock stopped state in the Stop mode. When restarting by setting the INT or NMI signal to 0, the warm-up time is automatically created by the internal counter. In the restart by the RESET signal, oscillation restarts without warm-up. akot [ LT LE LS LI LCI LI LI lw Ta Ti T2 T3 ye (Clock stopped state} 1 rd TL HALT o" M1 \ {f iNT NM! RESET LJ 170089 | Figre 3.3.7 (b) Basic Timing for Sequency of Restart from Clock stopped State (Idle 2 Mode) | 1 T2 73 | CLK OUT TLS LI 1 WALT ge [ | a sc Mt " Warm-up < 3 time ' INT * { i NMI | ' Warm-up _., _) ! time 170489 Figre 3.3.8 Basic Timing for Sequency of Restart from Clock stopped State (Stop Mode) MPUZ80ASSP-67TOSHIBA TMPZ84C015B 3.3.4 Relationship with MPU The following describes the relationship between the CGC and the MPU mainly in terms of the halt clear operation. [1] RESET Signal Figure 3.3.9 shows an example of the timing for the restart from the Stop mode on the TMPZ84C015A using RESET signal for both the MPU and CGC. To reset the MPU, the RESET signal must be set to 0 for at least 3 stable clocks. When the RESET signal goes 1, the MPU releases the halt state after a dummy cycle of 2T clock states to start executing instructions from address 0000H. To restart the clock output by the RESET signal in the Stop mode, the internal counter to determine the warm-up time does not operate. Therefore, if the MPU does not restart correctly due to the unstable clock output immediately after the restart of the internal osciliator, or the unstability of the crystal at power-on, the RESET signal must be held at 0 for a time long enough for the MPU to be reset securely. | NOP . > Dummy Execution from execution ~ cycle -| * address 00O00H Ce T2 T3 T4 T1 T2 T3 T4 HALT ~~ \ ic { gf a a ? M\ 4 Vf RESET + Ay / Figure 3.3.9 Example of clock Restart Timing by RESET Signal 170489 [2] Releasing Halt State by Interrupt Signal The CGC restarts the clock output from the Idle or Stop mode by the input of INT or NMI signal. By this clock, the MPU starts operating. However, when the CGC restarts the clock output, the MPU is still in the halt state executing NOPs. To clear the halt state, the interrupt signal must be entered into the MPU (in the case of the INT signal) for at least one instruction. The MPU interrupt is detected on the rising edge of the last clock of each instruction (NOP for the halt state). MPUZ80ASSP-68TOSHIBA TMPZ84C015B (1) When using non-maskable interrupt (NMI) MPUs non-maskable interrupt is edge trigger input. The MPU contains the flip-flop to detect an interrupt. The state of this internal NMI flip-flop is sampled on the rising edge of the last clock of each instruction. Therefore, when a short active low (0) pulse has been inserted before the interrupt detection timing, the interrupt is acknowledged. The NMI input of the TMPZ84C015A is connected to the NMI input of the MPU via the CGC, performing the same operations as above. (See Figure 3.3.11) | | | | | | | (2) When using maskable interrupt (INT) With a maskable interrupt, the maskable interrupt enable flip-flop (IFF) must be set to 1 by program before the INT input signal is detected 0. Even if the CGC accepts the INT signal to restart supply of the clock, no interrupt is acknowledged unless the INT signal is kept inserted until one instruction (NOP) has been executed. Figure 3.3.10 shows the timing for clearing the halt state by the interrupt signal. T4 #171 T2 T3 8674 CLK OUT INTERRUPT SAMPLING TIMING 170489 Figure 3.3.10 Timing for Clearing Halt State by Interrupt Signal MPUZ80ASSP-69TOSHIBA TMPZ84C015B [3] Connecting CGC to MPU on TMPZ84C015A Figure 3.3.11 shows the connection between the CGC and the MPU on the TMPZ84CO15A Cin 7 - C out CLKIN _ ra CLKOUL | HALT Mi XTAL1 aL MPU HALTMR CLK CLK Bit4 MS1 HALT HALT Bit 3 MS2 CGC M1 M1 | Z| _ Z| Z zl Ss RESET INT RESET t RESET wt iNT 1 CTC, PIO, SIO Internal Internal INT CLK M1 170489 Figure 3.3.11 Connection Between CGC and MPU MPUZ80ASSP-70TOSHIBA TMPZ84C015B 3.4 . CTC Operational Description The CTC has 4 independent channels. To these channels, addresses are allocated on the TMPZ84C015As I/O map, permitting the read/write of the channels in the MPUs I/O cycle. (See Figure 3.4.1) This subsection mainly describes the CTC operation to be performed after accessed. 3.4.1 CTC Block Diagram Figure 3.4.1 shows the block diagram of the CTC. INTERNAL CONTROL ofan CIRCUIT \ CHANNELO ZC/TOo DATA | <-> a F < CLK/TRGo Do~D7 MPU BUS vO |> ZC/TO, LOGICAL INTERNAL BUS CHANNEL 1 CONTROL OPERATION < CLK/TRG) CE (A7~A2}< >] circuit CS (Ao) i> ZC/TO2 CS1 (At) NZ CHANNEL 2 ca eat j cLKTRG 2 IORQ LOGICAL RD OPERATION CIRCUIT H> ZC/TO3 CHANNEL 3 | f V i< CLK/TRG3 IEOQ lel INT 470889 Figure 3.4.1 Block Diagram of CTC 3.4.2 CTC System Configuration The CTC system consists of the following 4 logic circuits: (1) MPU bus I/O logic circuit (2) Internal control logic circuit (3) Interrupt control logic circuit (4) Four independent counter/timer channel logic circuits {1] MPU Bus I/O Logic Circuit This circuit transfers data between the MPU and the CTC. [2] Internal Control Logic Circuit This circuit controls the CTC operational functions such as the CTC selecting chip enable, reset, and read/write circuits. MPUZ80ASSP-71TOSHIBA TMPZ84C015B {3] Interrupt Contro! Logic Circuit This circuit performs the MPU interrupt related processing such as priority determination. The order of priority with other LSIs is determined according to the physical location in daisy chain connection. [4] Counter/Timer Channel Logic Circuit This circuit consists of the following 2 registers and 2 counters. Figure 3.4.2 shows the configuration of this circuit. e e e e | | | Time-constant register (8 bits) Channel control register (8 bits) Down-counter (8 bits) Prescaler (8 bits) CHANNEL CONTROL TIME CONSTANT REGISTER (8 BITS) REGISTER (8 BITS) INTERNAL BUS SYSTEM CLOCK PRESCALER DOWN COUNTER | Zc/TO SI rc (8 BITS) (8 BITS) (1) (2) f CLK/TRG 170889 Figure 3.4.2 Configuration of Counter/Timer Channel Logic Circuit Time-constant register This register holds the time constant to be written in the down counter. When the CTC is initialized or the down-counter has reached zero, the time constant is loaded into down-counter. The time constant is set immediately after the MPU has written the channel control word in the channel control register. For a time constant, an integer from 1 to 256 can be used. Channel control register This register is used to choose the channel mode or condition according to the channel control word sent from the MPU. MPUZ80ASSP-72TOSHIBA TMPZ84C015B (3) Down-counter The contents of the time-constant register are loaded into the down counter. In the counter mode, these contents are decremented for each edge of the external clock; in the timer mode, they are decremented for each prescaler clock output. The contents of the time-constant register are loaded at initialization or when the down-counter has reached zero. The contents of the down-counter can be read any time. Also, the system can be programmed so that an interrupt request is generated each time the down-counter has reached zero. (4) Prescaler The prescaler, used only in the timer mode, divides the system clock by 16 or 256. The dividing number is programmed by channel control word. The output of the prescaler becomes the clock input to the down-counter. 3.4.3 CTC Basic Operations [1] [2] Reset The state of the CTC is unstable after it is powered on. To initialize the CTC, the low level signal needs to be applied to the RESET pin. On any channel, the channel control word and time-constant data must be written to be started before it is started in the counter or timer mode. To program the system to enable interrupts, the interrupt vector word must be written in the interrupt controller. When these data have been written in the CTC, it is ready to start. Interrupt The CTC can cause an interrupt when the MPU is operating in the mode 2. The CTC interrupt can be programmed for each channel. Each time the channels down-counter has reached zero, the CTC outputs the interrupt request signal (INT). When the MPU accepts the CTCs interrupt request, the CTC outputs the interrupt vector. Based on this interrupt vector, the MPU specifies the start address of the interrupt processing routine and calls it to start interrupt processing. The MPU specifies the start address of the interrupt processing routine by the interrupt vector output from the CTC, so that the user can change the vector value to call any desired address. The interrupt processing is terminated when the MPU executes an RETI instruction. The CTC has the circuit which decodes the RETI instruction. By constantly monitoring the data bus the CTC can detect the termination of the interrupt processing. MPUZ80ASSP-73TOSHIBA TMPZ84C015B [3] The order of interrupt priority with the Z80 peripheral LSIs is determined by the daisy chain connection. That is, the peripheral LSIs are connected one after another and the one physically near the MPU is given a higher priority. The priority of the Z80 peripheral LSIs (CTC, PIO, and SIO) contained in the TMPZ84CO15<A is determined by the contents of the interrupt priority register (#F4: bits 2 through 0). Inside the CTC, channel 0 is given the highest priority, followed by channels 1, 2 and 3 in this order. The CTC and other peripheral LSIs on the TMPZ84C015A have the signal lines IEO and IEI. Connect the IEO of a higher peripheral LSI to the IEI of a lower perpheral LSI. Connect the IEI of the highest peripheral LSI to VCC. Leave the IEO of the peripheral LSI unused. In this connection, the CTC interrupt is caused under the following conditions: , e When both IEI and IEO are high, no interrupt is caused. At this time, the INT signal is high. An interrupt can be requested in this state. When the CTC outputs the interrupt request signal (INT), the IEO of the CTC becomes low. When the MPU accepts the interrupt, the INT goes high again. e When the IEI goes low, the IEO also goes low. e While the IEI is low, no interrupt can be requested. e When the IEI goes low while an interrupt is being serviced, the interrupt processing is aborted. Operation Modes The CTC operates in either the counter mode or the timer mode. Mode is selected by writing the channel control word. (1) Counter mode In the counter mode, the number of edge of the pulses applied to the channels CLK/TRG pin is counted. When pulses have been input, the contents of the down- counter are decremented synchronizing with the rising edge of the next system clock. The pulses rising edge or falling edge to be counted can be specified by the channel control word. When the contents of the down-counter has reached zero, the high level pulse is output from the ZC/TO pin. When the interrupt is enabled by the channel control word, the INT pin goes low and an interrupt is requested. When the contents of the down-counter has reached zero, the time constant data written in the time constant register is automatically loaded into the down-counter. To load a new time constant value into the down-counter, write the data to the time constant register, and it is loaded into the down-counter after the current count operation is terminated. MPUZ80ASSP-74TOSHIBA TMPZ84C015B (2) Timer mode In the timer mode, the time intervals which are integral multiples of the system clock period. A timer interval is measured according to the system clock. The system clock is supplied to the prescaler which divides it by a factor of 16 or 256. The output of the prescaler provides the clock to decrement the down-counter by 1. The time constant data is automatically loaded into the down-counter each time it has reached zero as in the counter mode. When the contents of the down-counter has reached zero, the high level pulse is output from the ZC/TO pin. This pulse period is given by the following expression: te*P*TC Where, tc = System clock period P = Prescaler value (16 or 256) TC = Time constant data (256 for 00H) The user can select, by means of the channel control word, to start the timer automatically or to start the timer on the edge of the pulse at CLK/TRG pin. In case the user select the CLK/TRG pin, the user can also select the rising edge or falling edge of the pulse. MPUZ80ASSP-75TOSHIBA TMPZ84C015B 3.4.4 CTC Status Transition Diagram and Basic Timing [1] Transition Diagram Figure 3.4.3 shows the CTC status transition diagram. POWER ON RD=H LEVEL? NO CHANNEL DESIGNATION 1 DESIGNATION | DATA RECEIVE LOAD OF DOWNCOUNTER CHANNEL | | | | NO INTERRUPT VECTOR OUTPUT TO MPU DGEMEN OF CONTROL WORD BIT O = 12 YES CHANNEL CONTROL WRITE GF CHANNEL| WORD | write OF INTERRUPT CONTROL WORD VECTOR WORD TIME CONSTANT DATA DATA RECEIVE I WRITE OF TIME CONSTANT I UDGEMEN. OF OPERATION MODE TIMER MODE DIVIDE THE MEASUREMENT OF SYSTEM CLOCK INPUT EDGE I PULSE OUTPUT OF INTERNAL NUMBER TIME OF THE CLOCK COUNTER MODE PULSE OUTPUT FROM ZC/TO I INTERRUPT VECTOR OUTPUT I TIME CONSTANT LOAD CL 170489 Figure 3.4.3 (a) CTC Transition Diagram (a) MPUZ80ASSP-76TOSHIBA TMPZ84C015B DOWN COUNTER TIME CONSTANT LOAD DOWN COUNTER-1 (DECREMENT) DOWNCOUNTER = 0? YES TIME CONSTANT LOAD | 170489 Figure 3.4.3 (b) CTC Transition Diagram (b) [2] Basic Timing {1) Write cycle The write cycle is used to write a channel control word, an interrupt vector, or a time constant. The C MPU drives the IORQ pin of the CTC low in the subsequent system clock cycle T2 to start the write cycle. It is required to make the MI pin of the CTC high to indicate that the write cycle is on. At the start of the cycle, the channel is specified by CS1 (A1) or CS0 (AO) of the CTC. Thus, the CTCs internal registers are ready to accept data in system clock T3. Twis the state to be automatically inserted by the MPU. 71 T2 TW T3 T1 CLK IN __ J |_| LJ L__J L__J L_ CSo, C54, CE (Ao), (At), (Az~7) x CHANNEL ADDRESS x fORQ \ / al DATA x INPUT x Figure 3.4.4 Write Timing 170489 MPUZ80ASSP-77TOSHIBA TMPZ84C015B (2) Read cycle The read cycle is used to read the contents of the down-counter. During clock cycle T2, the MPU initiates a read cycle by driving the RD and IORQ pins low. It is required to make the MI pin high to indicate that the read cycle ison. At the start of the read cycle, the channel is specified by CS (Ay) or CSp (Ag) of the CTC. At the rising edge of system clock TW, the contents of the down-counter at the time of the rising edge of T2 are put on the data bus. TW is the wait state to be automatically inserted by the MPU. T1 T2 TW T3 Ti akin} LF LL LL a, a. (ary) xX CHANNEL ADDRESS x TORQ NN RD MT > (High) DATA << outeut > 170489 Figure 3.4.5 Read Timing [3] Counter mode In the counter mode, the down-counter is decremented synchronizing with the system clock, at the edge of the pulse applied from the external circuit connected to the CLK/TRG pin. The period of the pulse to be applied to the CLK/TRG pin must be greater than 2 times the system clock period. Also, it is required to insert the setup time between the active edge of the CLK/TRG pin signal and the rising edge of the succeeding system clock. When the interval between these pulses is short, the down-counter is decremented one system clock later. When the down-counter has reached zero, a high level pulse is output from the ZC/TO pin. CLK IN | CLK/TRG INTERNAL COUNTER 2C/TO 170489 Figure 3.4.6 Counter Mode Timing MPUZ80ASSP-78TOSHIBA TMPZ84C015B [4] | | INTERNAL [5 Timer mode The timer starts operating at the second rising edge of the system clock from the rising edge of the pulse applied from the external circuit connected to the CLK/TRG pin. The period of the pulse to be applied to the CLK/TRG pin must be greater than 2 times the system clock period. Also, it is required to insert the setup time between the active edge of the CLK/TRG pin signal and the rising edge of the succeeding system clock. When the interval between these pulses is short, the timer starts one system clock cycle later. cx fF L_J Lt CLK/TRG TIMER S/ATIMER OPERATION START 170489 Figure 3.4.7. Timer Mode Timing ] Interrupt acknowledge cycle Having received the interrupt request signal (INT) from the CTC, the MPU drives the CTCs MI pin and JORQ pin low to provide the acknowledge signal. The IORQ pin goes low 2.5 system clocks later than the M1 pin. To stabilize the signal lines (IEI and EEO) in daisy chain connection, the interrupt request cannot be changed on each channel while the MI pin is low. The RD pin is held high to make distinction between the instruction fetch cycle and the interrupt acknowledge cycle. While the RD pin is high, the CTCs interrupt control circuit determines the interrupt-requesting channel of highest priority. When the CTCs IEI is high and the MI pin and IORQ pin go low, the interrupt vector is output from the interrupt requesting channel of highest priority. At this time, 2 system clock cycles are automatically inserted by the MPU as a wait state to maintain the stabilization of the daisy chain connection. T1 T2 TW TW T3 T4 amt LF UT L_ LI Li LI LI wt lo 170489 Figure 3.4.8 Interrupt Acknowledge Timing MPUZ80ASSP-79TOSHIBA TMPZ84C015B [6] Return from interrupt processing Return from the interrupt processing is performed when the MPU executes the RETI instruction. This RET] instruction must be used at the end of the interrupt processing routine. When this instruction is executed by the MPU, the CTCs IEI and IEO return to the state active before the interrupt has been serviced. The RETI instruction is a 2-byte instruction. Its code is EDH 4DH. The CTC decodes this instruction to check if there is the next interrupt request channel. In the daisy chain structure, the interrupting LSIs IEI and IEO are held high and low respectively at the time the instruction code EDH has been decoded. The code following EDH is 4DH, only the peripheral LSI which has sent the last interrupt vector (that is, the LSI whose IEI is high and IEO is low) returns from the interrupt processing. This restarts the processing of the suspended interrupt of the peripheral LSI of the next higher priority. T1 T1 T2 T2 73 14 T3 14 ok IN TF LJ LI LS LS LSP LY LS kL. WEN F+1__ 170489 Figure 3.4.9 Interrupt Return Timing MPUZ80ASSP-80TOSHIBA TMPZ84C015B 3.4.5 CTC Operational Procedure [1] To operate the CTC in the counter mode or the timer mode, the channel control word and time-constant data must be written in the CTC. To enable interrupts by the channel control word, the interrupt vector must be written in the CTC. /O Address and Channel Control Word To write the channel control word in the CTC, the channel must be specified by the corresponding channel I/O address. Table 3.4.1 Channel I/O Addresses Channe! /O address 0 #10 1 #11 2 #12 3 #13 170489 The channel control word to be written in the CTC consists of 8 bits. The system data bus DO through D7 correspond to bit 0 through 7 respectively. Figure 3.4.10 shows the meaning of each bit. Table 3.4.2 shows the function of each bit. D7 D6 DS D4 D3 D2 Di DO Counter/ Prescaler Edge Trigger Time Reset 1 timer constant interrupt 170489 Figure 3.4.10 Channel Control Word For the channel control word, D0 must always be 1. Table 3.4.2. Meanings and Function of Channel Control Words (1/3) Meaning and function Bit 0 1 Bit7 | Disables channel interrupt Enables channel interrupt. In either (D7) counter or timer mode, the interrupt is requested every time the down-counter has reached zero. When this bit is set to 1", the interrupt vector must be written in the CTC before the down-counter starts. When the channel control word whose D7 bit is 1 is written in an already operating channel, the interrupt occurs only when the down-counter has reached zero for the first time after the writing of the new channel control word. 170489 MPUZ&80ASSP-81TOSHIBA TMPZ84C015B (2/3) Bit Meaning and function 0 1 Bit 6 (D6) Puts the channel in the timer mode. Puts the system clock into the prescaler and outputs the divided signal to the down- counter. Puts the channel in the counter mode. The down-counter is decremented for each edge trigger applied to the CLK/TRG pin. In the counter mode, the prescaier is not used. Bit (D5) Used only in the timer mode. The prescaler is set to divide the system clock by 16. Used only in the timer mode. The prescaler is set to divide the system clock by 256. Bit 4 (D4) In the timer mode, the timer operation starts on the falling edge of the trigger PULSE (CLK/TRG). In the counter mode, the down-counter is decremented at the falling edge of the external clock pulse (CLK/TRG) In the timer mode, the timer operation starts on the rising edge of the trigger pulse (CLK/TRG). In the counter mode, the down-counter is decremented at the rising edge of the trigger pulse (CLK /TRG). Bit3 (D3) Used only in the timer mode. The timer oparation starts on the rising edge of the trigger pulse clocks after a time constant is loaded onto the down- counter. Used only in the timer mode. The timer operation is started at the leading edge of the external trigger pulse that inputs 2 system clocks after a time constant is loaded onto the down counter. when a time lag between the system clock and trigger pulse satisfies a setup time, the prescaler starts to operate from the second leading edge of the trigger pulse. If a time lag between the system clock and trigger pulse dose not satisfy the setup time, the prescaler starts to operate at the leading edge of the trigger pulse after 3 system clocks. If the trigger pulse is input before loading of a time constant, the operation is the same as that when Bit 3=0. Bit 2 (D2) This bit (0) indicates that there is no time constant written after channel control word. However, when the channel is in the reset state and this bit cannot be changed to 0 in the channel control word which is given first after the channel reset. To change other state without changing a time constant, input a channel control word with this bit changed to 0. This bit (1) indicates that there is a time constant written immediately after a channel control word. If a time constant is written while the downcounter is operating, a new time constant is set in the time constant register. The counting which is in progress is carried out continuously when the downcounter becomes zero, and a new time constant is loaded onto the downcounter. 170489 MPUZ80ASSP-82TOSHIBA TMPZ84C015B [2] [3] (3/3) Meaning and function Bit 0 1 Bit1 | Continues the current channel operation | Stops the down-counter operation. (D1) When this bit is set to 1, the channel operation stops but all the channel control register bits remain unchanged. When bit 2 = 1 and bit1 = 1%, the channel operation remains stopped until a new time constant is written. Channel restart is set up after the new time constant is programmed. The channel is restarted acoording to the state of bit 3. When bit 2 = 0 and bit 1 = 1, the channel operation does not start until a new channei control word is written. 170489 Time-Constant Data In either the time mode or the counter mode, the time-constant data must be loaded into the time constant register. When bit 2 (D2) of the channel control word is 1, the time constant is loaded into the time constant register immediately after the channel control word is written. A time-constant value must be an integer in a range of 1 to 256. When the 8 bits of a time constant are all 0s, such a time constant is assumed to be 256. Figure 3.4.11 shows the bit configuration of time-constant data. [07 [ be [ 05 | ba | p3 | p2 | 01 | bo | Tc? TC6 TCS TC4 Te3 Tc2 Tc1 TCO 170489 Figure 3.4.11 Time-Constant Data Interrupt Vector In interrupt in the MPU mode-2, the interrupting channel must give an interrupt vector to the MPU. An interrupt vector is written in the channel-0 interrupt vector register with bit 0 (D0) =0. The vector is written in the same way as the channel control word is written on channel 0. However, bit 0 (D0) of the vector should always be Q. Bit 7 (D7) through bit 3 (D3) are user-defined values. Bit 2 (D2) and bit 1 (D1) are automatically given and contain the code of the interrupt-requesting channel having the highest priority. Table 3.4.3 shows the channel codes. Figure 3.4.12 shows the interrupt vector bit configuration. MPUZ80ASSP-83TOSHIBA TMPZ84C015B Table 3.4.3. Channel Codes Bit 2 (D2) Bit 1(D1) Channel number | interrupt priority 0 0 ft) (High) 0 1 1 1 0 2 1 1 3 (Low) 170489 [vw f[ve[vs[v[vs[ x |x] o | L pots Fix to 0 Channel codes interrupt vector given by user 170489 Figure 3.4.12 Interrupt Vector 3.4.6 Using CTC {1] Counter Mode The following describes how to use the CTC by referring to a program using channel 0 with interrupt disabled. (a) The counter programming procedure is shown in Figure 3.4.13 START LOAD OF CHANNEL CONTROL WORD LOAD OF TIME CONSTANT Figure 3.4.13 Counter Programming Procedure 170489 MPUZ80ASSP-84TOSHIBA TMPZ84C015B (b) The block diagram for converting the 100 kHz system clock into the 10 kHz equivalent is shown in Figure 3.4.14. CHANNEL O TIME CONSTANT PRESCALER REGISTER NOT USED 10 A TIME CONSTANT IS LOADED EVERY TIME : WHEN THE DOWN COUNTER COUNTS ZERO CLK/TRGO (100kHz) DOWN COUNTER INPUT OUTPUT | ZC/TOO (10kHz) 170489 Figure 3.4.14 Down-Counter Block Diagram (c) The channel control word configuration is shown in Figure 3.4.15 D7 +4D6 D5 D4 D3 D2 DI DO ota fTotTrtoftrtarts| | INTERRUPT DISABLE NOT USED NOT USED Reon COUNTERMODE -1ATTHE SETTING OF CHANNEL RISING EDGE TIME CONSTANT CONTROL WORD OF EXTERNAL CLOCK 170489 Figure 3.4.15 Channel Control Word Configuration MPUZ80ASSP-85TOSHIBA TMPZ84C015B [2] Timer Mode (a) The timer programming procedure without using interrupt is shown in Figure 3.4.16. START LOAD OF CHANNEL CONTROL WORD TIME CONSTANT LOAD Figure 3.4.16 Timer Programming Procedure 170489 (b) The block diagram for converting the 4 MHz system clock into the 1 kHz equivalent is shown in Figure 3.4.17. CHANNEL 1 TIME CONSTANT PRESCALER REEGISTER SYSTEM CLOCK (4MHZ)l 16 pipe 250 INPUT (250kHz) : A TIME CONSTANT IS LOADED EVERY TIME ; WHEN THE DOWN COUNTER COUNTS ZERO. DOWN COUNTER OUTPUT |zcro1 (1kHz) 170489 Figure 3.4.17 Timer Block Diagram (c) The channel control word is shown in Figure 3.4.18. D7 D6 D5 D4 D3 D2 v1 ovo Lo fofo fo To Ts ts Ti | INTERRUPT PRESCALER TIMER CHANNEL DISABLE VALUE (16) START RESET TIMER MODE STARTTHETIMER SETTING OF CHANNEL OPERATION ATTHE TIMECONSTANT CONTROL WORD FALLING EDGE OF THE EXTERNAL CLOCK. 170489 Figure 3.4.18 Channel Control Word MPUZ80ASSP-86TOSHIBA TMPZ84C015B 3.5. PIO Operational Description The PIO has two independent, programmable 8-bit ports. These ports are assigned addresses on the TMPZ84C015Bs I/O map and therefore can be read/written in the MPUs I/O cycle. This subsection mainly describes the operations that take place after accessing the PIO. 3.5.1 PIO Block Diagram Figure 3.5.1 shows the PIO block diagram aera LOGICAL PORTA PAg~PAz OPERATION vo DATA CONTROL LINE CIRCUIT rN LOGICAL | (PORT VO LINE) 2s OPERATION |}-- ASTB |, ARDY 3 CIRCUIT HANDSHAKE MPU BUS CONTROL LINE Po~D7 vo |A DATA BUS LOGICAL INTERNAL BUS oe OPERATION | N CE, MT, TORQ 6 | CIRCUIT C/D, B/A, RD ~~ CONTROLLINE TORTS PBy~PBy ab vO DATA CONTROL LINE LOGICAL | (PORT I/O LINE) INTERRUPT _ CONTROL V| OPERATION }- BS TB LOGICAL circuit 'b--_ > BRDY OPERATION HANDSHAKE CIRCUIT CONTROL LINE INT <___] IEO | 11 NTERUPT CONTROL LINE 170489 Figure 3.5.1 PIO Block Diagaram 3.5.2 PIO System Configuration The PIO system consists of the four logic circuits: (1) MPU bus I/O logic circuit (2) Internal control logic circuit (3) Interrupt control logic circuit (4) Port I/O logic circuit [1] MPU Bus I/O Logic circuit The MPU bus I/O logic circuit transfers data between the MPU and the PIO. [2] Internal Control Logic circuit The internal control logic circuit controls the PIO operating functions like the PIO selecting chip enable and the read/write circuits. MPUZ80ASSP-87TOSHIBA TMPZ84C015B [3] [4] interrupt Control Logic circuit The interrupt control logic circuit performs the MPU interrupt-associated processing such as determining interrupt priorities. The priorities with other LSI peripherals are determined by the physical location in daisy chain connection. Port I/O Logic Circuit The port I/O logic circuits are used to directly connect to peripheral devices. Each consists of the following 7 registers and 1 flip-flop. Data are written in the registers by the MPU as specified in the program. Figure 3.5.2 shows the internal configuration of the ports e Data output register (8 bits) e Data input register (8 bits) e Mode control register (2 bits) e Interrupt vector register (8 bits) e Interrupt control register (2 bits) e Mask control register (8 bits) e Data I/O control register (8 bits) e Handshake control logic circuit DATA INPUT/ "vee | | ees. | \ Page CONTROL REGISTER REGISTER rV/|_ REGISTER (8 BITS) (2 BITS) (8 BITS) 4 | OUTPUT ENABLE \ MODE CONTROL | INTERNAL BUS | REGISTER (8 BITS) DATA x Z CONTROL LINE INTERRUPT MASK DATA CONTROL CONTROL INPUT REGISTER 1] REGISTER K AMPUT DATA _ REGISTER (2BITS) (8 BITS) (B BITS) gy HANDSHAKE | READY HANDSHAKE INTERRUPT CONTROL CONTROL LINE REQUEST CIRCUIT STROBE \\ 170489 Figure 3.5.2 Port Internal Configuration MPUZ80ASSP-88TOSHIBA TMPZ84C015B (1) (2) (3) (4) (5) (6) (7) (8) Data Output register This register holds the data to be transferred from the MPU to peripheral devices. Data input register This register latches the data to be transferred from peripheral devices to the MPU. The input data to the MPU is read through this register Mode control register This register specifies the operation mode. The operation mode is set by MPU control. Interrupt vector register This register holds the vector which makes up the address of the table storing the start address of the interrupt processing routine. This register is used only for interrupt processing. Interrupt control register This register specifies how the I/O ports are to be monitored. This register is used only in the PIO mode 3. Mask control register This register specifies which I/O port pin is to be monitored. This register is used only in the PIO mode 3. Data I/O control register This register specifies whether each port pin is to be used as output or input. This register is used only in PIO mode 8. Handshake control logic This circuit controls the data transfer to the peripheral devices connected to the 8-bit I/O ports. 3.5.3 PIO Basic Operations [1] Reset (1) The PIO provides the following two reset capabilities: Power-on reset The PIO contains the circuit which automatically resets the PIO at the time of power-on. MPUZ80ASSP-89TOSHIBA TMPZ84C015B [2] (2) Hardware reset Making the RESET pin low for 2 system clock periods with the RD and TORQ pins being high resets the PIO on the rising edge of the RESET pin. This hardware reset inside the TMPZ84C015B by external pin is possible because the output of the AND circuit between the RESET and Mi pins is put on the M1 signal of the PIO. Reset state (a) The operation mode is set to mode 1 for both ports. (b) Interrupt is disabled (c) All the bits of the data I/O register of each port are reset. (d) All the bits of the mask control register of each port are set and masked. (e) The port I/O lines of each port are put in the high-impedance state (floating) . (f) The RDY pin of each port goes low. The reset state is held until the control word is written. For the function of the control word, see Subsection 3.5.5 Operational Procedure. Interrupt The PIO can cause an interrupt when the MPU is operating in mode 2. The interrupt request signal (INT) from the PIO is accepted when the MPU is in the interrupt enabled state (caused after the execution of E1 instruction). Receiving the INT signal, the MPU latches the interrupt vector (8-bit data) sent from the PIO, specifies the start address of the interrupt processing routine based on the vector, and calls the routine to start the processing. Thus, since the start address of the interrupt processing routine can be specified by the interrupt vector sent from the PIO, the user can change the vector value to call any desired address. Interrupt processing is terminated when the MPU executes the RET! instruction. The PIO has the circuit to decode the RETI instruction to detect the termination of interrupt processing by constantly monitoring the data bus. The interrupt priority among the Z80 peripheral LSIs is determined by the daisy chain structure. In daisy chain, the peripheral LSIs are connected one after another as shown in Figure 3.5.3. The more a peripheral LSI is physically located near the MPU, the higher the priority of the peripheral is. Actually, the priority of the Z80 peripheral LSIs (CTC, PIO, and SIO) on the TMPZ84CO15B is specified by the contents of the interrupt priority register (# F4 bits 2 through 0). Within the PIO, port A is given higher priority than port B. MPUZ80ASSP-90TOSHIBA TMPZ84C015B The TMPZ84C015Bs PIO and peripheral LSIs have the signal lines [EO and IEI connected to the IEO of a higher peripheral LSIs and the IE] of a lower peripheral LSI respectively. However, the IEI of the highest peripheral LSI is connected to the IEI pin and the IEO of the lowest peripheral LSI is connected to the IEO pin. In this state, the PIO interrupt follows the conditions: @ When both JEI and IEO are high, no interrupt has occurred. This time, the interrupt request signal (INT) is high. In this state, the PIO can request interrupt. e When the PIO sends the INT signal, it sets the IEO line to the low level. When the interrupt request is accepted by the MPU, INT goes back to the low level. When the IEI goes low, the IEO also goes low. e When the IEI is low, the PIO cannot request an interrupt. If the IEI goes low during interrupt occurrence, the interrupt processing is suspended. The operations of the 4 Z80 peripheral LSIs (the states of IEI, IEO and INT signal) daisy-chained as shown in Figure 3.5.3 are as follows: (1) Before interrupt occurrence Vcc __|H = MPU INT L | L Vee? 4 | INT INT INT INT lEl [EO iE! |EO IEI IEO lel IEO (1) (2) (3) (4) (2) Interrupt request from LSI-2 to the MPU ? Vec s __[L zt MPU INT | L | Veco INT iNT INT INT IE] IEO 1Ei IEO IEl ie) iEt IEO (1) (2) (3) (4) MPUZ80ASSP-91TOSHIBA TMPZ84C015B (3) The MPU acknowledges (enables) the interrupt. Interrupt processing for LSI-2 is performed. gus =| H 4 MPU INT } | | Veeco INT INT INT INT | IE] [EO 1EI IEO IEI IEO lel IEO (1) (2) (4) (4) Interrupt request from LSI-1 to the MPU. The interrupt processing for LSI-2 is suspended. g Vec _| tT MPU INT | if Vece y | INT INT INT INT IE] [EO IEt 1EO tEi 1EO IEl [EO (1) (2) (3) (4) (5) The MPU acknowledges (enables) the interrupt. Interrupt processing for LSI-1 is performed. gus H : MPU INT | | | Veco y INT INT INT INT = IEI IEO IE! IEO JEI [EO IEt [EO (1) (2) (3) (4) (6) Interrupt processing for LSI-l terminates {upon execution of the RETI instruction). Interrupt processing for LSI-2 is restarted. MPU g Vec INT Vee H IEI INT IEO (4) MPUZ80ASSP-92TOSHIBA TMPZ84C015B (7) Interrupt processing for LSI-2 terminates (upon execution of the RETI [3] instruction). L Vcc __|H z MPU INT | L. | Vee? uy | INT INT INT INT IEl IEO IEt IEO (El EO IEI {EO (1) (2) (3) (4) Interrupt priority is given to LSI-1, LSI-2, LSI-3 and LSI-4 in this order. 170489 Figure 3.5.3 Signal States in Daisy Chain Structure Operation Modes The PIO operates in one of the 4 operation modes. The mode is selected by writing the mode control word. (1) (2) (3) Mode 0 (byte output mode) Mode 1 (byte input mode) Mode 2 (byte I/O mode) Mode 3 (bit mode) Mode 0 (byte output mode) In mode 0, the PIO sends the data received from the MPU to the external device through the port data output register. The contents of this register can be rewritten by using an output instruction. If the data on the bus change, the register contents remain unchanged until the next output instruction is executed. When the MPU executes an output instruction, the write signal is generated in the PIO in the write cycle. Using the signal, the data on the data bus can be latched in the data output register. Mode 1 (byte input mode) In this mode, the PIO sends the data received from the external device to the MPU through the port data input register. The data transfer to the MPU is suspended until the MPU has read the current data. Mode 2 (byte I/O mode) Mode 2 is a combination of mode 0 and mode 1. This mode is used only for port A. In this mode, all 4 handshake control lines are used. Port As handshake control lines are used for data output and the port Bs handshake control lines are used for data input. For data transfer, port A is used. Port B is set in mode 3 (bit mode) in which no handshake control line is used. MPUZ80ASSP-93TOSHIBA TMPZ84C015B (4) In this mode, the interrupt timing occurs almost at the same time in mode 0 and mode 1. In an input operation, the port Bs handshake control lines are used, so that the interrupt vector written in port B is transferred. Therefore, the interrupts in input and output can be controlled by different vectors. Mode 3 (bit mode) In mode 3, the 8-bit port I/O lines are controlled for each bit. Since no handshake control lines are used, ordinary read/write operations can be performed. I/O operations can be performed on the port as well. In a write operation, the data sent from the MPU to the PIO are latched in the data output register corresponding to the bit set for output in the same timing as in mode 0. An interrupt occurs in the interrupt enabled state and when the bit set for input satisfies the condition specified in the interrupt control word. However, if port A is operating in mode 2, port B cannot cause an interrupt in the bit mode. Note that, to use the interrupt capability, the mask control register bit corresponding to the bit set for output must be set to 1 to disable its interrupt. MPUZ80ASSP-94TOSHIBA 3.5.4 PIO Transition and Basic Timing {1] Statis Transition Figure 3.5.4 shows the pio status transition diagram. @) | SELECT PORT cD=H TMPZ84C015B MODE 0 LEVEL ? JUDGMENT INITIAL SETTING | OF MODE | | DATA RECEIVE FROM DATA RECEIVE FROM | DATA RECEIVE THE EXTERNAL DATA RECEIVE THE EXTERNAL FROM MPU DEVICE FROM MPU DEVICE I I I I : WRITE TO OUTPUT WRITE TO INPUT WRITE TO OUTPUT WRITE TO INPUT REGISTER REGISTER REGISTER REGISTER I I = T OUTPUT TO OUTPUT TO MPU DXTERNAL DEVICE DATA COMPOSITION I COMPLETION DATA OUTPUT OF READING COINCIDENCE IN INTERRUPT CONDITION, INTERRUPTABLE OUTPUT OF INTERRUPT VECTOR OUTPUT OF INTERRUPT VECTOR Figure 3.5.4(a) PIO Status Transition 170489 MPUZ80ASSP-95TOSHIBA TMPZ84C015B DATA RECEIVE FROM MPU JUDGMENT OF CONTROL INTERRUPT CONTROL INTERRUPT CHARACTER VECTOR MODE CONTROL WORD SETTING OF SETTING MODE SE ioe WRITE OF INTERRUPT CONDITION VECTOR NO, NO YES YES DATA RECEIVE FROM MPU SETTING OF PORT INPUT/OUTPUT DATA RECEIVE FROM MPU SETTING OF MASK @ Figure 3.5.4(b) PIO Status Transition 200589 MPUZ80ASSP-96TOSHIBA TMPZ84C015B [2] Write Cycle The TORQ, RD, C/D (AO), B/A (A1), and CE (A7 through A2) signals generate the write signal (*WR) inside the PIO. The MPU sets the PIOs IORQ signal to the low level at system clock T2, to start the write cycle. At this time, to indicate that this cycle is a write cycle, the PIOs MI signal must be set to the high level. At the same time, the MPU sends signals to the PIOs B/A (A1) and C/D (AO) to specify the port or select control signal or the data. This allows the port data output register of the PIOs selected port to latch the data at system clock TS. TW is a wait state automatically inserted by the MPU. T1 T2 Tw T3 T1 CLKIN TLS LI LI LIB LI Le C/D, B/A (Ao) (A) x CHANNEL ADDRESS x CE To / (A2~A7) ORQ \W RD MT DATA BUS x INPUT xX WR oF *WR=C/D-CE-RD-IORQ 170489 Figure 3.5.5 Write Cycle Timing [3] Read Cycle The MPU sets the PIOs, RD pin, CE signal, and IORQ pin to the low level at system clock T2 to start the read cycle. At this time, to indicate that this cycle is a read cycle, the PIOs M1 pin must be set to the high level. The PIO outputs data in the CE, IORQ, and RD signals. TW is a wait state automatically inserted by the MPU. MPUZ80ASSP-97TOSHIBA TMPZ84C015B [4] [5] T1 T2 TW T3 T1 aw J LI LI LPLIE LS] (io) (ay) >< OC DATA BUS Coureur) *RD=C/D-CE-RD-[ORQ 170489 Figure 3.5.6 Read Cycle Timing Mode 0 (Byte Output Mode) The mode 0 output cycle starts when the MPU executes an output instruction. When an output instruction is executed, the write signal (*WR) is generated in the PIO in the write cycle. This signal latches the data on the data bus to the data output register of the selected port. The RDY pin goes high on the first falling edge of the system clock after the rise of the write signal (*WR). This indicates that the data in the data output register are already on the port I/O pin. The peripheral device sets the RDY pin to the low level on the first falling edge of the system clock after the rise of the STB pin to be input to the PIO to indicate that the peripheral device has received the data from the port I/O pin, waiting for the next output instruction. If, at this time, the PIO is enabled for interrupts, it sets the INT pin to the low level on the rising edge of the STB signal to output the interrupt request signal to the MPU. Figure 3.5.7 shows the timing chart of mode 0. Mode 1 (Byte Input Mode) The input cycle starts when the MPU has completed the previous data read operation. The peripheral device sets the PIOs STB pin to the lower level, putting data on the port 1/0 line. The RDY pin is driven low on the first falling edge of the system clock after the rise of the STB pin, disabling the peripheral device to send the next data. If at this time, the PIO is enabled for interrupts,it sets the INT pin to the low level on the rising edge of the STB pin, making an interrupt request to the MPU. When the MPU executes the input instruction in the interrupt processing routine, the read signal (*RD) is generated MPUZ80ASSP-98TOSHIBA - TMPZ84C015B in the PIO in the read cycle. This signal puts the data in the data input register of the selected port on the data bus. The MPU receives this data. The PIO sets the RDY pin to the high level on the first falling edge of the system clock after the rise of the read signal (*RD) to wait for the input of the next data. Figure 3.5.8 shows the mode I timing chart. T2 TWA 73 CLKIN _] |__| v LI Lo} L_| L_ RDY [ | \ PORT INPUT/ y OUTPUT LINE PREVIOUS DATA | DATA FROM MPU *WR , | y *WR=C/D-CE-RD-IORQ 170489 STB Figure 3.5.7 Mode 0 Timing Chart CLKIN | | | | | t | RDY = Rn / STB oF INT PORT INPUT/ 7 7 7 77 XX 5 OUTPUT LINE --= 170489 Figure 3.5.8 Mode 1 Timing Chart MPUZ80ASSP-99TOSHIBA TMPZ84C015B [6] Mode 2 (Byte I/O Mode) Mode 2 is a combination of mode O and mode 1. The timing for output operation is generally the same as in mode 0 except that, in mode 2, data is output only when the ASTB pin is low while, in mode 0, data is always on the port I/O line. The peripheral device can receive data on the rising edge of the ASTB signal being used as the latch signal. The input timing is the same as in mode 1. The port A handshake line is used as output control and the port B handshake line is as input control. The value of the interrupt vector generated by the BSTB signal during a port A input operation is the same as the value of the interrupt vector generated when port B is used in mode 3. Hence, all port B bits are masked by setting the mask control word to disable port B for the interrupt capability. CLKIN ARDY ASTB _' PORT A INPUT [ [ | | /OUTPUT LINE : OUTPUT <input > =C/D-CE-RD-1ORO 170489 3 5 * Figure 3.5.9 Mode 2 Timing Chart [7] Mode 3 (Bit Mode) In this mode, no handshake line is used. Therefore, the ordinary port read/write operations can be performed, permitting access to the ports any time. The write data from the MPU is latched to the data output register corresponding to the bit set for output in the same timing as in mode 0. Except when port B is used in mode 2, the STB pin of the port operating in mode 3 is fixed to the low level. The transfer data consists of the data in the data output register and in the data input register. That is, the data of the bit set for output and the data of the bit set for input make up the transfer data. MPUZ80ASSP-100TOSHIBA TMPZ84C015B [8] An interrupt occurs when the interrupt enabled state is on and the bits set for input satisfy the condition specified by the mask control word, ete. However, if port A is operating in mode 2, port B is disabled for interrupt in the bit mode. Note that, to use the interrupt capability, the bit of the mask register corresponding to the bit set for output must be set to 1 to disable it for interrupts. An interrupt request occurs when the logic condition becomes true. If the logic condition becomes true immediately before the MI pin becomes low or while MI pin is low, an interrupt request occurs on the rising edge of the MI pin. l i 171 T2 TW 13 1 PORT INPUT/ OUTPUT LINE X DATA 1 _X DATA2 X INTERRUPT CONDITION ( DATA 1 IS PUT ON BUS IS SATISFIED 170489 Figure 3.5.10 Mode 3 Timng Chart Interrupt Acknowledge Cycle Outputting the interrupt request signal (INT) , the PIO sets the IEO signal to the low level, disabling the low-priority peripheral LSIs for interrupt requests. Receiving the interrupt request signal (INT) from the PIO, the MPU sets the PIOs MI and IORQ pins to the low level to indicate that the MPU has acknowledged the interrupt request. The [ORQ pin goes low 2.5 system clocks later than the MI pin. To stabilize the daisy-chained signal lines (IEI and IEO), the ports and peripheral LSIs cannot change the interrupt request. The RD pin remains high to make distinction between the instruction fetch and interrupt acknowledge cycles. While the RD pin is high, the interrupt control logic in the PIO determines the interrupt requesting port of the highest priority. When the TORQ pin goes low with the IEI pin being high, the interrupt vector is put on the data bus from the interrupt requesting port. At the same time, two system clocks are automatically inserted by the MPU as a wait state to stabilize the daisy chain structure. MPUZ80ASSP-101TOSHIBA TMPZ84C015B [9] CLKIN | LIOLS UL LSP LY LIL. Tt 7 Te TORQ ~ a | RD | f IEO A JE] 170489 Figure 3.5.11 interrupt Acknowledge Cycle Timing Charts Return from Interrupt Cycle Return from interrupt processing is performed when the MPU executes the RETI instruction. This RETI instruction must be used at the end of the interrupt processing routine. When the MPU executes this instruction, the PIOs IEI and IEO return to the states active before interrupt processing. The RETI instruction consists of two bytes and its code are EDH and 4DH. The PIO decodes the RETI instruction to determine whether there is any interrupt requesting port. In the daisy chain structure, the IEI and IEO of the interrupting LSI remain high and low respectively at the time the instruction code EDH has been decoded. If the code following EDH is 4DH, only the peripheral LSI which has sent an interrupt vector immediately before, that is, the LSI whose IEI is high and IEO is low, returns from interrupt processing. This restarts the interrupt processing of the suspended peripheral LSI of lower interrupt priority. MPUZ80ASSP-102TOSHIBA TMPZ84C015B DATA BUS o_o a ~oo eee eee ; ep 7 1EO / 170489 Figure 3.5.12 Interrupt Cycle Return Timing Chart 3.5.5 PIO Operational Procedure To operate the PIO the control words shown below must be written in it as the initial settings. They must be written in the PIOs ports, A and B, separately. Specify the Vo address listed in Table 3.5.1 to write control words and data in the PIO. Table 3.5.1 \/OAddresses I/O function /O address Port A data #1C Port A command #1D Port B data #1E Port B command #1F 170489 (1) Interrupt vector word [p7 | pe [| 05 | v4 | v3 | 2 | pr | o | l ! ol J L. Identifies the interrupt vector word. User-defined interrupt vector 170489 e Using this vector and the contents of the address indicated by the MPUs I register, the MPU generates the start address of the interrupt processing routine. e D0 through D7 are written in the interrupt vector register. e This word is not needed when the interrupt capability is not used. MPUZ80ASSP-103TOSHIBA TMPZ84C015B (2) (3) Mode control word Lov [os [os [oa]. [a [4 | l L | UL | Le, Identifies the mode control word. Don't care Mode Select D7=0,D6=0 : Modeo D7=0,D6=1 : Mode 1 D7=1,D6=0 : Mode2 D7=1,D6=1 : Mode3 170489 This word specifies an operation mode. D7 and D6 are written in the mode control register. Data I/O control word Lov | ve | os | oa | bs [ v2 | 01 | bo | Ll j 0: output 1: input e This word is needed only in mode 3. 170489 e When mode 3 is specified by the mode control word, the data I/O control word is written after it. Each port is specified for output or input. e DO through D7 are written in the data I/O register. MPUZ80ASSP-104TOSHIBA TMPZ84C015B (4) Interrupt control word [p7 | 06 | 05 | va | o [ 1 [ 1 ft | [identities the interrupt | | | | contro! word. lo : Mask word not required. [1 : Mask word requied. 0 : Active level is low. 1: Active level is high [o : Interrupt accurs when logic condition is OR. 1 : Interrupt occurs when logic contidion is AND. [o : Interrupt disabled. [! : Interrupt enabled 170489 e This word is for interrupt control such as interrupt condition setting. : e D4, D5, and D6 are used only in mode 3. e With D6=0, interrupt occurs when one of the bits not masked (the bit to be monitored) by the mask control word goes active. e With D6=1, interrupt occurs when all bits not masked (the bits to be monitored) by the mask control word go active. e With D4=1, the suspended interrupts are all reset regardless of the mode. e D5 and D6 are written in the control register. (5) Mask control word [p7 | v6 | v5 | pa | 03 | v2 | v1 | bo | l | : Not masked (to be monitored) 1: Masked (not to be monitored) 170489 e This word is needed only in mode 3. e When D4=1 is set by the interrupt control word, the mask control word must be written after it. e This word specifies whether to monitor the port I/O line specified for input by the data I/O control word. e When the bit is set to 0, the corresponding input line is monitored and regarded as the input associated with interrupt occurrence. MPUZB0ASSP-105TOSHIBA TMPZ84C015B e When the bit is set to 1, the corresponding input line is masked to provide the input not related to interrupt occurrence. e The PIO checks only the input line with the bit being 0 to see if the interrupt condition is satisfied. If the condition is satisfied, the PIO requests an interrupt. D0 through D7 are written in the mask control register. When port A is put in mode 2, all 4 handshake lines are used, so that port B must be set in mode 3 which uses no handshake lines. At the same time, all mask control word bits must be set to 1 (masked). Note: Only interrupt enable/disable can be set by the following control word: Lor [oe [osfosfofo],1f[.1] Le ! Identifies the control word which sets only interrupt enable/disable. Dont care fo : Disables interrupt. [1 : Enables interrupt. 170489 3.5.6 Using PIO The following is a programming example to operate the PIOs port in mode 3. This program is followed by the main routine and the interrupt processing program. @ The MPU is used in the mode 2 interrupt. e The table storing the start address of the interrupt processing routine is 0802H. e Interrupts occur when both PIOs port input lines A6 and A5 go high. e The I/O addresses of the PIO are the addresses listed in Table 3.5.1. AO~A7 DO~D7 ; MPU oN PIO External device DO~D7 i p__ It D2~D7 PAO PAI AO c/D Pag Al B/A PAA > PAS Address PAG A2~A7 decoder cE PA7 _ INT INT INT 170489 Figure 3.5.13 PlO Connection MPUZ80ASSP-106TOSHIBA TMPZ84C015B ORG 100H LD SP, 100H ot LM 2 eee LD A, O8H oe LD I, A LD A, 02H aaa OUT ~(1DH) , A LD =A, OCFH oe OUT (1DH) , A LD A, 62H a OUT (10H) , A LD A, OF7H - OUT (1DH) , A LD A, QFH OUT (10H) , A EI te + Sets the stack pointer. + Sets for MPU mode 2 interrupt. + Writes data in MPU I register. + Writes the interrupt vector word. - Writes the mode control word. + Writes interrupt control word. + Writes the mask control word. + Sets interrupt enable. 3.6 SIO Operational Description Writes the data I/O control word, Sets PIO. The SIO has two independent, programmable full-duplex serial ports. These ports are assigned addresses on the TMPZ84C015Bs I/O map. This subsection mainly describes the operations that take place after accessing the SIO. 3.6.1 SIO Block Diagram - internal Read/Write } data control register y Channel [ cLock ircui Ch 1A A <> SYNC circuit (Channel A) WANTREADY Do~7 External [> ( meu |, control (> | control line BUS \, Internal bus (Channel A) |< 5 WO SIO control line _ | data CE, M1, IRQ iN! channel [E7crock ? A rY B za SYNC Internal ReadMWrite WAIT/READY control register circuit (Channel B) INT T External [> 1EO central Control line El (Channel B) |< Interruput control line Figure 3.6.1 SIO Block Diagram 170489 MPUZ80ASSP-107TOSHIBA TMPZ84C015B 3.6.2 SIO System Configuration As shown in Figure 3.6.1, the SIO consists of the MPU bus interface, the internal controller, the interrupt controller, and two independently operating full-duplex channels. Each channel has the read register, the write register, and the external controller which controls the connection with peripheral LSIs or external devices. The TMPZ84CO15B contains all the functions and pins of the 40-pin, DIP-type TMPZ84C40A (SIO/0), TMPZ84C41A (SIO/1), and TMPZ84C42A (SIO/2). However, when using the SIO of the TMPZ84C015B, the SIO/0, SIO/1, or SIO/2 must be used alone. The pin assignments are as shown in Figure 3.6.2. PB3 PB2 PBI PBO PAG PAZ PAZ PAI PAG WIRDYB WIRBYA SYNCB > L(y dityqyaq faq re UH ymjmyenyn mynja (a) SiO/O Vi alyly alajulujau uv vu folwleale afulu a 2 x/x<><x XjE [EE ]U > - Jole[e|eE xix|x x > wlecle tlalelula * * lalulela cle le PAS PB PA3 PB2 PA2 PBI PAI PaO PAO WIRDYB WIRDYA SYNCB > Lidl dip jaar UG ob yojayaje mymim o 2 ae gleieleiee v eleills sek 3 (b) sio/1 2 /x)< XE le [E JU - > = Jalelele xjulx x > ele Hlaja lula * Taloleloa tlelae kn N.C PAa PB3 PA3 PB2 PA2 PBI PAI PBO PAG WRDYB WIRDYA SYNCB N.C tt [tyt ayqyt pq far Uo b+ ymyaynyo wyajo om (c) SIO/2 V O]YIY Ole |niola vu vu falwluje olulu ao Zp JR fE pe fo - > - [Ole [e]R xxl x > wlaetr rlale lula * * loalulela tele & wn HL vo Figure 3.6.2 SIO Pin Assignments MPUZ80ASSP-108TOSHIBA TMPZ84C015B Table 3.6.1 shows the types and functions of the SIO registers. Hach channel has 8 write registers and 3 read registers. (1) Communication data path Figure 3.6.2 shows the communication path of each channels transfer data. 1 Receive operation The receiver has an 8-bit receive register and a 3-stage 8-bit buffer register in FIFO configuration. This saves time in high-speed data block transfers. The receivers also have the receive error FIFO which holds the status information such as parity and framing errors. The receive data follow different paths according to the operation mode and character length as shown in Figure 3.6.3. Table 3.6.1 (a) Write Regosters Register Function Write register (WRO) |Resets CRC. Sets pointers of registers, and commands. Write register (WR1) | Sets the interrupt mode. Write register2 (WR2) |Sets the vector to be transmitted at interrupt. Write register3 (WR3) | Provides the parameters to control the receiver. Write register4 (WR4) | Provides the parameters to control the receiver and transmitter. Write register5 (WR5) | Controls the transmitter. Write register6 (WR6) | Sets the sync character or the SDLC address field. Write register? (WR7) | Sets the sync character or the SDLC flag 170489 Table 3.6.1 (b) Read Regosters Register Function Read register0 (RRO) | Indicates the receive/transmit buffer state and the pin state. Read register (RR1)_ | Indicates the error status and the end-of-frame code. Read register2 (RR2)_ |Indicates the interrupt vector contents. (Channel B only) 170489 MPUZ80ASSP-109TOSHIBA TMPZ84C015B MPU, 1/0 VO data biffer Omternal data bus : if ! Receiving Receiving WR? WRE Transmission Pott { pr-n-----4 synchronous synchronous data | __Data Iti. Error | register register FIFO FIFO I Ir Receiving 20-bit 1 i Start Great transmission | Shiftregistaer | bit ih . aynchronous Asynchronous Hunt mode (bibsychronous: CRC data porate neon ene 1 t t i i Transmit RxD | 41-bit Delete Receiving sDLC data multiplexer | TxDA ee zeroot =| 3-bit shiftregister 2-bit delay dela synchronous [f| | g y register (8 BITS) ZERO INSERTION [ttt (bits h Asynchronous data SDLC-CRC syncharohous Receivi CRC crc | eceivin delay register RKCA clock 8 BITS synchronous CRC Tranmission |7xcA circuit data GENERATOR check = [< circuit CRC checker SDLC-CRC Assemble CRC 170089 Figure 3.6.3 Transfer Data Path (Channel A) e Asynchronous mode In the asynchronous mode, the receive data enters the 3-bit buffer if the character length is 7 or 8 bits or the 8-bit receive shift register if the character length is 5 or 6 bits. e Synchronous mode In the synchronous mode, the data path depends on the receive processing phase at the time. The receiver operation starts from the hunt phase. In this mode, the receiver searches the receiver data for the bit pattern which matches the specified sync character. If the SIO is set in the monosync mode, the receiver searches for MPUZ80ASSP-110TOSHIBA TMPZ84C015B the bit pattern which matches the sync character set in WR7;if the SIO is set in the bisyne mode, the receiver searches for the bit pattern which matches two consecutive syne characters set in WR6 and WR7. When synchronization has been established, the subsequent data enter the 3-bit buffer by bypassing the sync register. SDLC mode In the SDLC mode, the sync register constantly monitors the receive data performing zero deletion as required. When the sync register detects 5 1s consecutively in the receive data, the following bit is deleted if it is O. If itis 1, the bit that follows is checked. If it is 0, it is assumed as a flag, if it is 1, it is assumed an abort sequence (7 consecutive 1s). The reformatted data are put in the receive shift register via the 3-bit buffer. When synchronization has been established, the subsequent data follow the same path regardless of the character length. Transmission The transmitter has an 8-bit transmit data register and a 20-bit transmit shift register. The 20-bit transmit shift register holds the data from the WR6, WR7, and transmit data register. Asynchronous mode In the asynchronous mode, the data in the 20-bit transmit shift register are added with the start and stop bits to be sent to the transmit multiplexer. Synchronous mode In the synchronous mode, the WR6 and WR7 hold the sync character. The contents of these registers are sent to the 20-bit transmit register as the sync character at the transmission of data blocks or as the idle sync character if a transmitter underrun occurs in data block transmission. SDLC mode In the SDLC mode, the WR6 holds the station address and the WR7 holds the flag. The flag (WR7) is sent to the 20-bit transmit register at the start and end of each frame. For each of the other data fields, one 0 follows five consecutive 1s. MPUZ80ASSP-111TOSHIBA TMPZ84C015B (2) /O functions To transfer data from the MPU, the SIO must be set in the polling, interrupt, or block transfer mode. Polling To operate the SIO in the polling mode, all interrupts mode must be disabled. In the polling mode, the MPU reads the status bits DO and D2 in each channels RRO to check for reception or transmission. Interrupts There are 3 types of SIO interrupt: transmit interrupt, receive interrupt, and external/status interrupt. These interrupts can be enabled by program. The receive interrupt is further divided into the following three: Interrupt on the first received character @ Interrupt on all received characters Interrupt on special receive conditions Higher priority is given to channel A than channel B. On the same channel, higher priority is given to reception, transmission, and external/status in this order. The SIO provides the daisy-chained interrupt priority control feature and the interrupt vector generating feature. Further, it provides the status affected vector feature. This feature outputs 4 interrupts depending on the interrupt source. Block transfer The SIO has the block transfer mode to adapt to the MPUs block transfer and the DMA controller. For block transfer, the W/RDY line is used. For the MPUs block transfer, this line is used as the wait line;for the DMA biock transfer, it is used as the ready line. The SIOs ready output indicates to the DMA controller that the data is ready to transfer. The SIOs wait output indicates to the MPU that the SIO is not ready for data transfer and therefore requesting the extension of the output cycle. MPUZ80ASSP-112TOSHIBA TMPZ84C015B 3.6.3 SIO Basic Operations (1) Asynchronous mode For data transfer in the asynchronous mode, the character length, clock rate, and interrupt mode must be set. These parameters are written in the write registers. Note that WR4 must be set before the other registers are set. Data transfer does not start until the transmit enable bit is set. When the auto enable bit is set, the SIO starts transmission upon the CTS pins going 0, allowing the programmer to send a message to the SIO without waiting for the CTS signal. Figure 3.6.4 shows the data format of the asynchronous mode. ae ae ee Marking | 1 Piety its J Marking Start bit Parity bit Stop bit Message direction 170489 Figure 3.6.4 Data Format of Asynchronous Mode 1 Transmission Serial data are output from the TxD pin. Its transfer clock rate can be set to one of 1, 1/16, 1/32, and 1/64 times the clock rate ot be supplied to the trandmit clock input (TxC). The serial data are output on the falling edge of TxC. 2 Reception The receiver operation in the asynchronous mode starts when the receive enable bit (DO of WR3) is set. When the receive data input RxD is set to 0 for the duration of at least 1/2 bit time, the SIO interprets it as the start bit, sampling the input data at the middle of the bit time. The sampling is performed on the rising edge of the RxC signal. When the receiver receives the data whose character length is not 8 bits, it converts the data into the one composed of the necessary bits, the parity bit and the unused bit set to 1. Example: a 6-bit character | 1 | P | DS | D4 | D3 | D2 |b1 | bo | MPUZ80ASSP-113TOSHIBA TMPZ84C015B (2) When the external/status interrupt is enabled and a break state is detected in the receive data, the interrupt is generated and the break/abort status bit (D7 of RRO) is set and the SIO monitors the transmit data until the break state is cleared. The interrupt is also generated when the DCD signal is in the inactive state for more than the specified pulse width. The DCD status bit is set to 1. In the polling mode, the MPU must refer the receive character valid bit (DO of RRO) to read the data. This bit is automatically reset when the receive buffer is read. In the polling mode, the transmit buffer status must be checked before writing data in the transmitter to avoid overwrite. Synchronous mode There are 3 kinds of character synchronization : monosync, bisync, and external sync. In each of these synchronous modes, the times J clock rate is used for both transmission and reception. The receive data is sampled on the rising edge of the receive clock input (RxC). The transmit data changes on the falling edge of the transmit clock input. ( aT smode Synchronous . CRC CRC character Data field 1 2 45 m Monosynchronou aF Synchronous Synchronous . CRC CRC character character Data field 1 2 iM Bisynchronous mode ae Data field cRe cre CC Ped Message direction < External synchronous mode Figure 3.6.5 Data Format of Synchronous Mode 170489 MPUZ80ASSP-114TOSHIBA TMPZ84C015B 1 (a) (b) Monosync In this mode, synchronization is established when a match with the sync character (8 bits) set to WR7 is found, enabling data transfer. Bisync In this mode, synchronization is established when a match with 2 consecutive sync characters set to WR6 and WR7 is found, enabling data transfer. In this mode as well as the monosync mode SYNC is active during the receive clock period in which the sync character is being detected. External sync In this mode, synchronization is performed externally. When synchronization is established, it is indicated by the SYNC pin. The SYNC input must be kept to 0 until the character synchronization is lost. Character assembly starts from the rising edge of the RxC after the falling of the SYNC. After reset, the SIO enters the hunt phase to search for the sync character. If synchronization is lost, the SIO sets the enter-hunt-phase-bit (D4 of WR3) to reenter the hunt phase. Transmission. Data transfer using interrupt When the transmit interrupt is enabled, the interrupt is caused upon the transmit buffers being emptied. For the interrupt processing, other data are written in the transmitter. If these data are not ready for some reason, the transmit underrun condition occurs. Bisync mode In the bisync mode, if the transmitter runs out of data during transmission, supply characters are inserted. This is done in two methods. In one method, sync characters are inserted. In the other, characters generated so far are transmitted followed by sync characters. Either of these methods can be selected by the reset transmit underrun/EOM command in WRO. End of transmission Break can be performed by setting bit D4 of WR5. When break is performed, the data in the transmit buffer and the shift register are lost. When the external/status interrupt is enabled, the SIO generates the interrupt depending on the transmitter state and outputs the vector. This mode can be used for block transfer. MPUZ80ASSP-115TOSHIBA TMPZ84C015B (3) e Reception (a) Interrupt on the first received character This mode is used for ordinary block transfer. In this mode, the SIO generates the interrupt only for the first character;subsequently, it does not generate the interrupt unless special receive conditions are satisfied. To initialize these settings, command 4 of WRO (to be enabled by the next receive interrupt) must be set in advance. (b) Interrupt on all received characters In this mode, the SIO generates the interrupt for all characters coming into the receive buffer. When the status affect vector has been set, a special vector is generated on a special receive condition. (c) Special receive condition interrupt This interrupt occurs when any of the above interrupts is selected. The special receive conditions include parity error, receive overrun error, framing error, and end-of-frame (SDLC). These error status bits are latched, so that they must be reset after they are read. They can be reset by command 6 of WRO (error reset). SDLC mode The SIO supports both the SDLC and HDLC protocols. They resemble each other, so that only the SDLC mode is explained here. Figure 3.6.6 shows the data format in the SDLC mode. In the SDLC mode, one data block is called a frame and the message in it is put between the open flag and the close. The address field in the frame contains the address of a secondary station. Checking this address, the SIO receives or ignores the frame. Frame | ss Open flag Aacress Data field cRe cre Close flag Sf Message direction __ 170489 Figure 3.6.6 Data Format in SDLC Mode MPUZ80ASSP-116TOSHIBA TMPZ84C015B (a) (b) (c) (d) {e) Transmission Data transfer using interrupt When the transmit interrupt has been set, the interrupt occurs each time the transmit buffer becomes empty. In the SDLC mode, data are sent to the SIO by this interrupt. Data transfer using wait/ready The wait function in the wait/ready capability is used to make the MPU extend the output cycle when the SIOs transmit buffer is not empty. The ready function indicates to the DMA that the SIOs transmit buffer is empty and therefore ready to receive data. If no data has been written in the transmit shift register before transmission, the SIO goes in the underrun state. This capability permits data transfer to the SIO. Transmit underrun/EOM The SIO automatically ends the SDLC frame if there is no data to be transmitted to the transmit data buffer. To implement this, the SIO sends a 2-byte CRC when there is no data to send, then the SIO transmits one or more flags. After reset, the transmit underrun/EOM status bit is set to prevent the CRC character from being inserted when there is no data to be sent. Using this function, the SIO starts frame transmission. Here, the transmit underrun/EOM reset command must be set in advance between the transmission of the first data and the data end. Thus, the SIO goes in the reset state at the end of each message with the CRC character being sent automatically. CRC generation For CRC calculation, the CRC generator must be reset before transmission (bits D6 and D7 of WRO). CRC calculation starts when the address field is written in the SIO (WR6). The transmit CRC enable bit (DO of WR5) must be set before the address field is written. End of transmission When the transmitter is disabled during transmission, the data currently transmitted is all transmitted to its end. The subsequent data is put in the marking state. When the transmitter is disabled, characters remain in the buffer. However, the abort sequence is made active when the abort command is written in the command register, deleting all data. MPUZ80ASSP-117TOSHIBA TMPZ84C015B (a) (b) (c) (d) (e) Reception As in the transmit mode, several parameters must be preset in the receive mode. The address field is written in WR7 and the flag character in WR7. Receiving the open flag, the receiver compares the contents of the following address field with the address set in WR6 or the global address (1111 1111). If the contents of the address field in frame matches either of these address, the SIO starts reception. Interrupt on the first received character This mode is generally used for the block transfer using the wait/ready capability. In this mode, the SIO generates the interrupt only on the first character. The status flag of this interrupt is latched, so that command 4 (to be enabled by the next received character) of WRO must be preset for re-initialization. When the external/status interrupt is set, an interrupt occurs every time the DCD changes. This interrupt also occurs when the special receive condition is satisfied. Interrupt on all received characters In this mode, the SIO generates an interrupt on all received characters. When the status affect vector has been set, the SIO generates a special vector on the special receive condition interrupt. Special receive condition interrupt Using the special receive condition, the interrupt on the first received character or the interrupt on all received characters must be selected in advance. The receive overrun status of the special receive condition interrupt is latched. The status bit can be reset by the error reset command (WRO command). CRC check The receive CRC check is reset when the open flag at the head of a frame is received. CRC calculation is performed on the subsequent characters up to the close flag. In the SDLC mode, the transmit CRC is inverted, so that a special check sequence is used. The check must end with 0001 1101 0000 1111. Since SIO handles the CRC character as a data, the MPU must discard it after reading it. End of transmission When the SIO receives the close flag, the end-of-frame-bit is set to indicate that the close flag has been received. When the status affect vector has been set, the special receive condition interrupt occurs and the interrupt vector is output. Any frame can be aborted by abort transmission. When the external/status interrupt has been set, the interrupt occurs and the break/abort bit in RRO is set. MPUZ80ASSP-118TOSHIBA TMPZ84C015B 3.6.4 SIO Status Transition Diagram and Basic Timing [1] Status Transition Diagram Figure 3.6.7 shows the SIO status transition diagram. | ASynchronous mode transmission Ke c/B=1 NO CE, IORQ =0 Status read RRO RD=0 < Buffer empty? D=1CE,JORO YES 20RD= B ciD=0 7 Te YES aE TARA Write transmission Ce, OR = data character ~ Transmission Set command interrupt write mode Transmission (WRO-WR7) (TxD) | ; | Start bit "0" Do | m1 | : | (Receiving : | Auto enable? Receiving : ! YES Dn $$$ . A Parity bit | Stop bit 1" | YES External / Status interrupt ! aS YES Enable End of frame transmission Figure 3.6.7 (b) State Transition Diagram transmission 170489 Mono or bisynchronous? YES YES Asynchronous mode Synchronous mode SDLC External synchronous transmission transmission transmission transmission 170489 Figure 3.6.7 (a) SIO Status Transition Diagram MPUZ80ASSP-119TOSHIBA Synchronous mode transmission TxD telminals TMPZ84C015B TxCINPUT | Synchronouscharacter | __ SYNCH1 (D0~D7) feed (TXD) SYNCH2 (DO~D7) c/D=1 CE, TORQ=0 Status read RRO RD=0 Buffer empty ? YES =0 : wa == TA Write transmission , TORQ _ data character Transmission interrupt Transmission (TxD) End of transmission ? YES NO Add CRC? CRC feed wo---- > CRC (D0~D15) End of CRC feed ? YES Synchronous ss f[__. SYNCH1 (D0~D7) character feed SYNCH2 (DO~D7) End of frame transmission 170489 Figure 3.6.7 (c) State Transition Diagram MPUZ80ASSP-120TOSHIBA SDLC transmission TxD terminal Open flag character 9 fo----- >| (7EH) feed TxC INPUT Open flag character (7EH) Status read RRO Buffer empty ? 1. Write address | 2. Write transmission data Transmission (TxD) }-----7 > derrun/tOM Add CRC? YES Transmission interrupt 1. Address (D0-D7) 2 RO data [ CRC feed End of CRC feed ? CRC (DO~D15) Close flag transmission ( End of frame ) transmission (7EH) TMPZ84C015B 170489 Figure 3.6.7 (d) SIO Status Transition Diagram MPUZ80ASSP-121TOSHIBA TMPZ84C015B NO Auto enable ? |< YES Enable receiving Synchronous mode ? SDLC mode ? Synchronous receving SOLC receiving RxD: Receiving External RxC: data sampling Meceivine. Synchronous < L S$DLC _____ Character NO hunt ? Open flag (7EH) YES Asynchronous angie YES. _ external /Status ln interrupt Data receiving Address OK 7 Receiving character effective? RxDB=0 {start bit) ? Receiving error? Receiving data sampling Read receiving data NO Receiving End of data ? ~ character interrupt YES Yes Add CRC? YES Synchronous Receiving error ? NO Read receiving data RD =0 LT Synchronous Close flag (7EH) character |___secewing __] s ceiving Receiving data End of re error ra Lr Special receiving interrupt ( sreakaboart) (Framing CRC erton) i Parity error ) ( Overunerror_) ( End of frame ) Figure 3.6.7 (e) State Transition Diagram 170489 MPUZ80ASSP-122TOSHIBA TMPZ84C015B [2] B/A,C/D, CE Basic Timing Figure 3.6.8 shows the timing in which data or a command is written from the MPU to the SIO. Figure 3.6.9 shows the timing in which data is read from the SIO to the MPU. Figure 3.6.10 shows the interrupt acknowledge timing in which the MPU gives an interrupt response to the SIOs interrupt request to set the TORQ pin to 0 several clocks after setting the MI pin to 0 as the acknowledge signal. To maintain the interrupt serviced state in daisy chain structure, the interrupt request state cannot be changed while MI is active. Figure 3.6.11 shows the timing in which the return from interrupt is performed. Figure 3.6.12 shows how the daisy chain structure works. First, suppose that the SIO is servicing interrupt. When the PIO issues an interrupt request immediately before the first byte EDH of the RETI instruction is decoded with M1 being active, IEO of the PIO goes 0. However, when EDH is decoded, the PIOs interrupt request is not acknowledged. Therefore, the PIOs IEO returns to 1. When the second byte 4DH is decoded, the SIOs IEO returns to 1. Therefore, the IEI and IEO of each peripheral LSI at this point of time all go 1, or out of the interrupt serviced state. The PIO keeps the INT pin at 0 until this state is set. Then, the interrupt is serviced starting with the peripheral device of the higher priority. T1 T2 TW T3 T1 CLKIN J | f | J | (Ao). (A1), (Ag~A7) _X X. TORQ \ / RD MI DATA. es Input data _)+- 170489 Figure 3.6.8 Write Timing MPUZ80ASSP-123TOSHIBA TMPZ84C015B Ti T2 Tw T3 Tl CLKIN FTL J | | i | | B/A,C/D, CE (Aj), (Ao), (Ao~Ayz) _X_ X. TORQ f[-S a {/ DATA Output data 170489 Figure 3.6.9 Read Timing DATA nter ypt vecto. 170489 Figure 3.6.10 Interrupt Acknowledge Timing MPUZ80ASSP-124TOSHIBA CLKIN TMPZ84C015B T1 T2 T3 T4 71 T2 T3 T4 T1 -~ 170489 Figure 3.6.11 Return Timing from Interrupt MPUZ80ASSP-125TOSHIBA TMPZ84C015B 1 The SIO has made an interrupt request aqn aye INT po es IEl 1EO sIEI IEO sIEl IEO EI (EO {Ei tO 2 The SIO is servicing the interrupt. aqe ag" eH 0 L__] 3 The PIO has made an interrupt request immediately before EDH is decoded by the SIO. By the PlOs interrupt request, PIOs IEO isset to 0. ye low 0 0 Q" {He FY Hs Hd 4 Because EDH has been decoded, the PIOs interrupt request is not acknowledged. Therefore, PIOs IEO returns to 1. 1 | am wqe 4 a "0 o or = ol ee TH 30 If | 5 Because 4DH has been decoded, the SIOsIEO issetto 1. re HE se 6 The PIO's interrupt request is acknowledged and the PIOs IEO is setto "0". aqn uae 49" Q" g" TH eH Ff 1704B9 Figure 3.6.12 Daisy Chain at Execution of RETI Instruction MPUZ80ASSP-126TOSHIBA TMPZ84C015B 3.6.5 SIO Operational Procedure The following mainly describes the meaning of each bit of the write and read registers. Special attention should be directed to the fact that the parameters of the write register (WR4) should be set before the others. Some registers can use only a signal channel. The I/O addresses listed in Table 3.6.2 must be specified to write the control word and read/write data on the SIO. Table 3.6.2 1/O Addresses 1/0 function 1/O address Channel A data #18 Channel A command #19 Channel B data #1A Channel B command #1B 170489 [1] Write Registers 1 |WR 0; Write register 0 Table 3.6.3 Configuration of Write Register 0 p7_| 06 ps | oa | ps oz | or | vo ] CRC reset code Primary command bit Register pointer bit | | | | | 170489 Bits DO through D2: Register pointer bits These bits specify the register on which read/write is performed by the next byte. When read/write is completed, the register pointer points to WRO. Bits D3 through D5: Basic command bits e Command 0 (=000): No operation This command only sets the register pointer without making the SIO operate. It is used te invalidate the command in the command chain for the SIO or hold the location at which a command is inserted in the command chain if required. Command 1 (=001): Abort sequence generation This command is used to generate the abort sequence (7 or more consecutive 1s). Note that command 1 is used only in the SDLC. MPUZ80ASSP-127TOSHIBA TMPZ84C015B e Command 2 (=010): External/status interrupt reset Once an external interrupt or a status interrupt has occurred, the status bit of RRO is latched. This command is issued to enable the RROs status bit in order to enable the interrupt again. e Command 3 (=011): Channel reset This command performs generally the same operation as when the RESET pin is set. The difference is that reset is performed only on a single channel. The command for channel A resets the interrupt priority circuit as well. e Command 4(=100): Enable the interrupt at the next character reception. This command is used to enable an interrupt when the end of block a data block has been detected followed by the reception of the next block. e Command 5 (=101): Reset transmit interrupt pending If the transmit buffer becomes empty in the transmit interrupt enable mode, an interrupt occurs. This command is used to disable the transmit interrupt when there is no data in the transmit buffer. e Command 6 (=110): Error reset The error (parity or overrun error) caused in block transfer is latched in bits D4 and D5 of RR1. This commands is used to clear these bits. e Command 7 (=111): Return from interrupt This command performs the same operation as the operation required to execute the RETI instruction on the SIOs data bus. Therefore, non-Z80 MPUs (that is, systems using no RETI instruction) can use the daisy chain in the SIO. This command is available only on channel A. Bits D6 and D7: CRC reset code These 2 bits allow the programmer to select between the receive CRC checker reset, the transmit CRC generator reset, and the transmit underrun/EOM reset. Table 3.6.4 List of Reset Command Codes Reset command D7 D6 No operation 0 0 Reset the receive CRC checker 0 1 Reset the transmit CRC generator 1 0 Reset the transmit underrun / EOM 1 1 170489 MPUZ80ASSP-128TOSHIBA TMPZ84C015B 2 |WR1; Write register 1 Table 3.6.5 Configuration of Write Register 1 D7 D6 | DS D4 | D3 D2 D1 bo | i Stgtus Enable | Enable Wait/ready select veces aHect trans-__| external / receiving / interr pe vector mission} status Select transmission mode Interrupt | interrupt Enable | function | | 170489 Bit DO: External/status interrupt enable When this bit is set, an interrupt is generated at the start of sync character transmission even if the execution is terminated upon detection of break/abort, the DCD, CTS or SYNC signal has changed, or the transmit underrun/EOM latch is set. Bit D1: Transmit interrupt enable When this bit is set, a transmit interrupt is generated upon the transmit buffer becoming empty. Bit D2: Status affect vector When this bit is set, bits D1 through D3 (V1 through V3) of WR2 is changed. When this bit is not set, the same interrupt vector as the contents of WR2 issued. Note that this bit is available only on channel B. Bits D3 and D4; Receive interrupt mode These bits are used to select a receive interrupt mode. Bits D5 through D7: Selection wait/ready functions These 3 bits are used to select a W/RDY pin function. The wait or the ready function is selected by program and they are not used simultaneously. The meaning of these bits are: When D5 is set to 1 , it indicates that the W/RDY pin responds to the receive buffer; when D5 is reset to 0, it indicates that the pin responds to the transmit buffer. When D6 is set to 1, the W/RDY pin functions as the READY pin; when D6 is reset to 0, the pin functions as the WAIT pin. MPUZ80ASSP-129TOSHIBA TMPZ84C015B e When D7 is set to 1, the wait/ready function is enabled;when D7 is reset to 0, the function is disabled. For example, when D7, D6, and D5 are 1, 1, and O respectively, and the transmit buffer is full, the READY pin goes 1, when the transmit buffer is empty, the pin goes 0. Table 3.6.6 shows the summary of the above description of bits D3 and D4 and D5 through D7. Table 3.6.6 List of Receive Interrupt Mode Codes Receive interrupt mode D4 D3 Receive interrupt disable 0 0 Interrupt on first received character or special receive condition* 0 1 Interrupt on received character or special receive condition* 1 0 Interrupt on received character or special receive condition 1 1 * (except for parity error) 170489 *Special receive conditions: e End of frame (in SDLC mode only) e Receive overrun error Parity error e Framing error Table 3.6.7 Wait / Ready Select Function (D5 through D7) Pin state Pin (Function) [Pin output Buffer state D7 | DG | DS WAIT | Floating - 0 DISABLE, 0 - READY | High - 1 Low The transmit buffer is full and WAIT the SIO data port is selected. 0 Floating | The transmit buffer is empty. 0 READY High The transmit buffer is full. ' 1 ENABLE Low | The transmit buffer is empty. Floating |The receive buffer is full. WAIT The receive buffer is empty 0 Low and the SIO data port is 1 selected. Low The receive buffer is full. High The receive buffer is empty. 170489 MPUZ80ASSP-130TOSHIBA TMPZ84C015B 3 |WR 2; Write register 2 Table 3.6.8 Configuration of Write Register 2 D7 | D6 | D5 | D4 | D3 | D2 | D1 | DO V7 | V6 | V5 | V4 V3 V2 v1 vo Subject to change under different interrupt conditions if the status- affect vector bit is set. 170489 This write register is the interrupt vector register. When bit D2 of WR1 (B channel) is not set, the interrupt vector is issued. When bit D2 of WR1 (B channel) is set, bits D1 through D3 (V1 through V3) are changed depending on the interrupt generation condition. This time, the contents of WR2 remain unchanged. Because WR2 is available only on channel B, WR2 must be programmed even if only channel A of the SIO is used. Table 3.6.9 shows the WR2 bit states in the interrupt condition with the status affect vector being set. Table 3.6.9 Channel interrupt Condition Codes Channel Interrupt condition v3 V2 V1 Transmit buffer empty 0 0 0 B Change of external / status 0 0 1 Received character condition available 0 1 0 Special receive condition* 0 1 1 Transmit buffer empty 1 0 0 A Change of external / status 1 0 1 Received character available 1 1 0 Special receive condition* 1 1 1 *Special receive conditions: e End of frame (in SDLC mode only) e Receive overrun error e Parity error e Framing error 170489 MPUZ80ASSP-131TOSHIBA TMPZ84C015B 4 {WR 3; Write register 3 Table 3.6.10 Configuration of Write Register 3 D7 | D6 DS D4 D3 D2 D1 DO Prohibit Receiving bit Auto Enter enable Address synchro- Enable / character enable phase CRC 9 mode nous receiving character | load 170489 Bit DO: Receive enable When this bit is set, the receive operation starts. Because this bit is used to start the receive operation, it must be set after the receive-associated programming has been all completed. Bit D1: Sync character load inhibit When this bit is set in the sync mode, the sync character is not loaded into the receive buffer. This bit is used to remove the sync character and idle syne from the received characters. Bit D2: Address search mode When this bit is set in the SDLC mode, any message having a programmed address or an address other than the global address (FFH) is not received by WR6. Therefore, the receive interrupt does not occur unless an address match occurs. Bit D3: Receive CRC enable When this bit is set, CRC calculation starts at the start of the last data transfer from the receive shift register to the receiver buffer. Bit D4: Enter hunt Phase When the establishment of synchronization is required, set this bit to enter the SIO into the hunt phase. The hunt phase is automatically cleared upon establishment of synchronization. Bit D5: Auto enable When this bit is set, the transmitter is enabled at the time the CTS pin is 0. When the DCD pin is 0, the receiver is enabled. MPUZ80ASSP-132TOSHIBA TMPZ84C015B Bits D6 and D7: Receive character length These bits are used to specify the number of receive bits which make up one character (character length). Table 3.6.11 shows the number of bits per character. Table 3.6.11 Receive Character Length Codes Bits / character D7 D6 5 7 6 8 170889 5 |WR 4; Write register 4 Table 3.6.12 Configuration of Write Register 4 D7 D6 DS | D4 D3 D2 D1 DO Clock mode Synchronous mode I Stop bit | Parity Even / Odd | Enable 170489 Bit DO: Parity enable When this bit is set, 1-bit transmit data is added to the number of bits specified by D6 and D7 of WR3 and the data is received in the resulting number of bits. If a character length other than 8 bits is selected, the added parity bit is set to the MSB side to be transferred to the receive data FIFO. When the 8-bit character length is selected, the parity bit is not transferred to the receive data FIFO. Bit D1: Parity even/odd This bit is used to determine whether to perform transfer and check in even or odd parity. (Even parity = 1, odd parity =0) Bit D2 and D3: Stop bit length These bits are used to select the stop bit length in the asynchronous mode. In the synchronous mode, both D2 and D3 must be set to 0. MPUZ80ASSP-133TOSHIBA Table 3.6.13 Stop Bit Length Codes TMPZ84C015B Bits D4 and D5: Sync mode Stop bit D3 D2 Sync mode 0 a 1 stop bit/ character 0 1 1.5 stop bits / character 1 0 2 stop bits / character 1 1 170489 These bits are used to select the sync mode. Table 3.6.14 Sync Mode Codes Sync mode DS D4 8-bit sync mode 0 0 16-bit sync mode (bisync mode) 0 1 SDLC mode (flag character ; 7EH) 1 0 External sync mode 1 1 Bits D6 and D7: Clock mode 170489 These bits are used to select the factor between the transmit/receive clock and the data transfer rate. In the synchronous mode, the X1 clock mode must be set. In the asynchronous mode, the transmit side and the receive side must have the same factor. Table 3.6.15 Clock Mode Codes (d ata fransioe rate) Db? D6 x 1 data transfer rate 0 0 x 16 data transfer rate 0 1 x 32 data transfer rate 1 0 x 64 data transfer rate 1 1 170489 MPUZ80ASSP-134TOSHIBA TMPZ84C015B 6 |WRS; Write register 5 Table 3.6.16 Configuration of Write Register 5 D7 D6 | DS D4 D3 D2 D1 DO Transmit bit Break Enable CRC-16 Enable DTR {character trans- trans- /SDLC RTS CRC trans- | mission mission mission 170489 Bit DO: Transmit CRC enable When this bit is set at the time the transmit data is loaded from the transmit data buffer into the transmit shift register, the CRC calculation is performed on that data. If this bit is not set, the CRC calculation and transmission are not performed in the transmit underrun state in the synchronous or SDLC mode. Bit D1: Request to send When this bit is set, the RTS pin goes 0. When this bit is not set, the RTS pin goes 1, In the asynchronous mode, the RTS pin goes 1 when the transmit buffer becomes empty. In the synchronous or SDLC mode, this bit state is followed by the RTS pin state. Bit D2: CRC-16/SDLC When this bit is set, the CRC-16 polynomial (X/+x1!5+X?+1) is selected. When this bit is reset to O, the CRC-CCITT polynomial (X!+x!7+X5+1) is selected. Bit D3: Transmit enable When this bit is set, the transmitter is enabled. Even if this bit is reset to 0 after the start of transmission, the syne character and the data being transmitted are transmitted to the last. Bit D4: Transmit break When this bit is set, transmitting any data forcibly puts the transmit data line (TxD pin) in the space state. When this bit is reset to 0, the TxD pin is put in the marking state. Bits D5 and D6: Transmit character length These bits indicate the character length of transmit data. MPUZ80ASSP-135TOSHIBA TMPZ84C015B Table 3.6.17 Transmit Character Length Codes Bits / character D6 D5 Less than 5 bits 0 ) 7 bits 0 1 6 bits 1 0 8 bits 1 1 170489 As shown in Table 3.6.17, for the transmission of less than 5 bits (4 bits or 3 bits) per character, D6 and D5 are 0 and 0, which do not indicate how many bits the transmit data consists of. To solve this problem, the data characters must be processed by the format shown in Table 3.6.18. Note that D indicates data. Tabie 3.6.18 Data Transfer Format with Transmit Data Consisting of Less than 5 bits Transmit bits / character D7 D6 D5 D4 D3 D2 D1 DO 1 1 1 1 1 1 1 1 0 0 0 0 0 0 D 2 3 4 5 170489 Bit D7: Data terminal ready This bit indicates the DTR pin state. When this bit is set, the DTR pin goes 0, when it is reset, the DTR pin goes 1. 7 |WR6; Write register 6 Table 3.6.19 Configuration of Write Register 6 D7 | D6 | D5 | D4 | D3 | D2 | D1 | DO ted eit debe 170489 MPUZ80ASSP-136TOSHIBA TMPZ84C015B This register is programmed as follows: e In the external syne mode Transmit sync character e In the monosync mode Transmit sync character e In the bisync mode First syne character e In the SDLC mode Slave station address 8 |WR7; Write register 7 Table 3.6.20 Configuration of Write Register 7 D7 | D6 | D5 | D4 | D3 | D2 | D1 | DO SYNC 15 14 13 12 11 10 9 8 (7} (6) (5) (4) (3) (2) (1} (0) 170489 This register is programmed as follows: e Inthe monosyne mode : Receive sync character e In the bisync mode Second syne character e In the SDLC mode Flag character (7EH) This register is not used in the external sync mode. [2] Read Registers 1 |RRO; READ REGISTER 0 Table 3.6.21 Configuration of Read Register 0 D7 D6 D5 D4 D3 D2 Di DO Trasmission woos _ Synchro- Trasmission Receiving Break/ | underrun ; Interrupt cTs nize DCD buffer : character Abort /EOM /Hunt empty pending effective | _| Used with the external /status interrupt 170489 MPUZ80ASSP-137TOSHIBA TMPZ84C015B Bit DO: Receive character available This bit is set when the receive buffer holds characters of 1 byte or more. This bit is reset when the buffer becomes empty. Bit D1; Interrupt pending This bit is set when an interrupt occurs in the SIO regardless of the interrupt condition type. This bit is available only on channel A. Bit D2: Transmit buffer empty This bit is set when the transmit data buffer becomes empty or the SIO is reset. However, in the sync and SDLC modes where the CRC character is being transmitted, bit D2 is reset. Bit D3: Data carrier detect This bit indicates the DCD pin input state. This bit is latched when the external/status interrupt occurs. Bit D4: Sync/hunt The meaning of this bit depends on the operation mode: (i) | Asynchronous mode Bit D4 indicates the SIOs SYNC pin state. When the SYNC pin state changes, the external/status interrupt occurs. (ii) External sync mode When synchronization has been established by the detection of external synchronization, the last bit of the sync character must be set to 0 at the second RxC falling edge from the rising edge of the received RxC. That is, to set the SYNC input to O by the external circuit after the detection of synchronization, full 2 receive cycle clocks must be awaited. When the SYNC input goes 0, the sync hunt bit is set. When synchronization is lost or the end of message is detected, the enter hunt phase bit is set. (ii) Internal sync mode In the monosynce and bisyne modes, bit D4 is initialized to 1 by the enter hunt phase command (D4 of WR3). This bit is reset when the SIO detects the syne character. (iv) SDLC mode Bit D4 is set when the receiver is disabled or the enter hunt phase command is issued. Then, when the frame open flag is detected, this bit is reset. MPUZB8O0ASSP-138TOSHIBA TMPZ84C015B Bit D5: Clear to send This bit indicates the opposite of the CTS pin input state. Bit D6: Transmit underrun/EOM This bit is set when the SIO is reset (including channel reset). Only the reset transmitter underrun/EOM latch command (WRO bits D7, D=1, 1) can reset this bit. When the transmit underrun state occurs, the external/status interrupt is generated. Bit D5 is also used to control transmission in the syne or SDLC mode. Bit D7: Break/abort In the asynchronous mode in reception, this bit indicates the break state detection. When the break state is detected, this bit is set, generating the external/status interrupt. This bit is reset by the external/status interrupt reset command. After break, the external/status interrupt is generated again. In the SDLC mode, bit D7 is set when the abort sequence is detected, generating the external/status interrupt. 2 |RR1; READ REGISTER 1 Table 3.6.22 Configuration of Read Register 4 D7 D6 D5 D4 D3 | D2 | D1 DO End of framing | Receiving Parit | | Feed frame error overrun crton Fraction all error characters | | 170489 Bit DO: All sent In the asynchronous mode, this bit is set when all characters are sent from the transmitter or there is no transmit data in the SIO. In the synchronous mode, this bit is always set. Bits D1 through D3: Fraction codes Normally, I field is an integral multiple of character Jength. If it is not, these bits show the number of fraction bits. These codes are effective only for the transmission for which the end of frame bit is set in the SDLC mode. Example: Figure 3.6.13 shows examples of fractions in which the number of bits/character at the end of I field is 8 bits (1) and 4 bits (2). MPUZ80ASSP-139TOSHIBA TMPZ84C015B = _,,__ 1 field @ SF CRC; CRC, \ 1 field | _ > 170489 Figure 3.6.13 Examples of Fraction Bits Field Table 3.6.23 (a) shows the fraction codes for the receive character whose character length is 8 bits. Table 3.6.23 (a) Bit Patterns by Fraction Bits at End of | Field Number of fraction bits at end of | field D3 D2 D1 1 byte before 2 bytes before 3 170489 The same table can also be provided for each character length when the receive character length of I field is other than 8 bits. Table 3.6.23 (b) Bit Patterns by Number of Bit / Character (No Fractions) Bits / character D3 D2 D1 5 bits / Character 0 0 1 6 bits / Character ) 1 0 7 bits / Character 0 0 0 8 bits / Character 0 1 1 170489 MPUZ80ASSP-140TOSHIBA TMPZ84C015B Bit D4: Parity error This bit is latched when the parity select bit (D0 of WR4) is set and a parity error is detected in the receive data. Latch can be cleared by the error reset command (WRO0O bits D5, D4, D3 =1", 1, Q), Bit D5: Receive overrun error The receive data FIFO holds up to 3 characters. When more characters are received without read out by the MPU, the excess character is set to the receive FIFO. When this character is read by the MPU, this receive overrun error is set. Once set, bit D5 latches that state. When the error reset command (command 6 of WRO bits D3 through D5) is written, this bit is also reset. Bit D6: CRC/framing error In the asynchronous mode, this bit is set when a framing error is detected in the received character. Because this bit is not latched, it is always updated. In the synchronous and SDLC modes, this bit indicates the transmitted CRC check result. This bit is reset when the error reset command (command 6 of WRO bits D3 through D5) is written. Bit D7: End of frame This bit is set when the end flag is detected in the receive data and the CRC check and the fraction code are found normal. This bit is reset when the error reset command (command 6 of WRO bits D3 through D5) is written. This bit is used only in the SDLC mode and is updated when the first character of the next frame is received. 3 |RR2; Read register 2 Tabie 3.6.24 Configuration of Read Register 2 D7 | D6 | DS | D4 | D3 | D2 | D1 | DO Interrupt vector V7 | V6 | V5 | V4 V3 V2 v1 vo Subject to change under different interrupt conditions if the status-affect bit is set 170489 MPUZ80ASSP-141TOSHIBA TMPZ84C015B When the status affect vector bit (D2 of WR1 (Channel B) ) is set, bits V3 through V1 are changed depending on the interrupt condition at the time. The vector to be read is determined by the interrupt condition having the highest priority at the time of read. When the status affect vector bit is reset, the contents of this register are the same as those of WR2. 3.6.6 Using SIO The following describes some system examples using the SIO. Figure 3.6.14 shows an inter-processor communication system. In this example, the MPU on the left side controls the data transfer with the modules on the right side. Both diagrams shown in Figure 3.6.14 (a) and (b) are communication systems. As shown, the SIO is used to interface with external devices in data communication. The greatest advantage of the SIO is the smaller number of data lines than parallel communication. RSXYZ driver /receiver Z80 280 RSXYZ =) driver MPU slo /receiver ry RSXYZ Z80 280 LN driver =< = receiver Y SIO MPU Figure 3.6.14 (a) Example of Data Communication Between Processors Channel No.1 CHA Modem 280 280 RS232C (Synchro- | sta linking ic driver/ nous, |> forremote MPU SIO receiver (i) Asynchro- processor CH.B nous) Chnnel No.2 170489 Figure 3.6.14(b) Example of Data Communication Between Processors 170489 MPUZ80ASSP-142TOSHIBA TMPZ84C015B 3.7 3.7.1 Standby Capability When a HALT instruction is executed, the TMPZ84C015B is put in one of the Run, Idle-1, Idle-2, or Stop mode depending on the contents of the halt mode setting register (#FO:bit 4, bit 3:HALTMR). (However, the TMPZ84C015B is put in the Run mode immediately after the reset operation by the RESET pin.) The halt mode setting register is set as follows. For the description and timing of each mode, see Subsection 3.3 CGC Operations. The halt mode setting register is assigned to bits 4 and 3 of address FO in the I/O address area. The halt mode is releasad by the interrupt (the nonmaskable interrupt by the NMI pin or the maskable interrupt by the INT pin) or by the reset through the RESET pin. A maskable interrupt is accepted when the MPU is in the EI state (in the state after the execution of EI instruction). A nonmaskable interrupt is accepted unconditionally. When an interrupt is accepted, the interrupt processing starts. When the MPU is in the DI state (after the reset operation and the execution of DI instruction) with maskable interrupt, the TMPZ84C015B returns to the halt mode after executing a HALT instruction (actually a NOP instruction). Setting Halt Mode Duplicate control is provided to prevent the stop of the watchdog timer operation which may be caused by the halt mode setting error due to program runaway. The halt mode is set by the halt mode setting register (HALTMR) and the halt mode control register (#F1:bits 7 through 0:HALTMCR). Figure 3.7.1 shows the contents of the halt mode control register (HALTMCR). Figure 3.7.2 shows the contents of the halt mode setting register (HALTMR). MPUZ80ASSP-143TOSHIBA TMPZ84C015B Address F1 ; 6 ; 5 ; 4 ; 3 ; ; ' ; 0 (HALTCR) | 117 0%4 #94. O. 4 1 | Write only ; ; 4 4 4 * : L_ i 170489 Figure 3.7.1 Halt Mode Control Register (HLTMCR) 6 5 4 3 2 1 0 Address FO Write T 7 |worer} WOTPR | HALTMR | 0 [1 [1 | See 3.8 Watchdog Timer. Always write 011. 0 0 = IDLE1 0 1 = I[DLE2 1 QO = STOP *1 1 = RUN 7 6 5 4 3 2 1 0 Address FO Write worea] WDTPR | HavTMR fo [4 1 | See 3.8 Watchdog Timer. Read written data 011". (Note) *: State after reset 170489 Figure 3.7.2 Halt Mode Set Register Figure 3.7.3 shows the device states in the halt state with the CLKOUT pin connected to the CLKIN pin. MPUZ80ASSP-144TOSHIBA TMPZ84C015B 170489 | move | ccc | mpu | cTC PIO silo. | 7Watchdeg, | CLERUT IDLE1 O x x x x x x IDLE2 O x CO x x x O STOP x x x x x x x RUN oO oO O O O O | ++ Operating Koreeee Stop Note : CLKOUT and CLKIN must be connected. | | | Figure 3.7.3 Device States in Halt State : For the halt mode in which the clock is supplied from the CLKIN pin (with the CGC oscillator unused), the Run mode must be used. 3.7.2 Halt Mode Setting procedure After reset, the halt mode is changed to the Run mode. Figure 3.7.4 shows the procedure to set a new mode. ( START ) Write Data DB into F1 address (HALTMCR) Write new mode into address FQ. END 170489 Figure 3.7.4 Setting Halt Mode MPUZBO0ASSP-145TOSHIBA 3.8 Watchdog Timer TMPZ84C015B The watchdog timer (WDT) detects an operation error caused by the program runaway to return to the normal operation. 3.8.1 Block Diagram of Watchdog Timer Figure 3.8.1 shows the block diagram of the watchdog timer. WDTOUT #FO WDTPR enable (Bits 6 and 5) > 216% 2184 2204 222 22-step binary counter io. (WDTCLK) for watchdog timer R S reset reset reset BIH WDTE J LA4EH write = _TLAwrite ] Watchdog timer control Watchdog timer : enable register register #F1 (WDTCR) #FO (WDTER) ft Internal data bus Figure 3.8.1 Block Diagram of Watchdog Timer 170489 MPUZ80ASSP-146TOSHIBA TMPZ84C015B 3.8.2 Setting Watchdog Timer (1) Enabling the watchdog timer The watchdog timer can be set by the watchdog timer enable register (#FO:bit 7: WDTER) and the watchdog timer periodic register (#F0:bit 6, bit 5: WDTPR). Address FO 6 1 4 1 3 2 ' 0 Write [worer| WDTPR | HALTMR | 0 | 1 | 1 | {L__J |__,__ See 3.7 Always write 011. Standby functiuon 0 O = TcC+216 0 1 = TeC+218 1 0 = TcC220 * = 22 ' 1 Tete2 (TcC: Master clock) *1=Enable *. 0 =Disable (Note) : State after reset 170489 Figure 3.8.2 Enabling Watching Timer (2) Disabling the watchdog timer The watchdog timer can be disabled by disabling the watchdog timer enable register (WDTER) then writing data B1 in the watchdog timer control register (#F1:bit 7 through bit 0:WDTCR). This function has a duplicate structure to prevent the watchdog timer setting error, which may lead to the watchdog timer operation stop, caused by program runaway. 7 6 5 4 3 2 1 0 Address FO Write [worer| WDTPR | Haurme | 0 | 1 | 1 | 0 =Disable See 3.7 Always write 011. Standby | function l 1 Address F1 r 1 ; t 1 ; ; (WDTCR) 1 0 1 1 0 0 0 1 Write only , + * ; , . * 170489 Figure 3.8.3 Disabling Watchdog Timer MPUZ80ASSP-147TOSHIBA TMPZ84C015B (3) Clearing the watchdog timer The watchdog timer can be cleared by writing data 4E in the watchdog timer control register (WDTCR). Address F1 ; : ; (woTcR) | 0 170 70 411 0 Write only ! 170489 Figure 3.8.4 Clearing Watchdog Timer Address FO 7 6 5 4 3 2 1 0 (Read) [woreR] WD'TPR | HALTMR [ 0 | 1 | i] L_ J L______} See 3.7 Read out writen data011 Standby function 0 0 = TeC+216 0 1 = TcC+218 1 0 = TcC+220 1 1 = TcCx222 0 =Disable 1=Enable 170489 Figure 3.8.5 Reading Watchdog Timer Setting Register 3.8.3 Watchdog Timer Output When the enabled watchdog timer is used, the 0 level signal is output to the WDTOUT pin after the duration of time specified in the watchdog timer periodic register (WDTPR). The output pulse width is one of the following two types depending on the WDTOUT pin connection: (1) The WDTOUT connected to the RESET pin:The 0 level pulse of 5TcC (System clock) is output. (2) The WDTOUT connected to a pin other than RESET pin :The 0 level pulse is kept output until the watchdog timer is cleared by software or reset by the RESET pin. MPUZ80ASSP-148TOSHIBA TMPZ84C015B 3.9 Interrupt Priority The programmable interrupt priority register (#F4:bits 2 through 0:INTPR) is provided to determine the interrupt priority for the CTC, SIO, and PIO in the TMPZ84CO15B. Figure 3.9.1 shows the register to determine the daisy chain interrupt priority for the CTC, SIO, and PIO. Address F4 3.9.1 Setting Interrupt Priority | | (INTPR) T T T T T T T Write only | 1 1 1 1. 1 1 1 | Priority order High Low * CTC- SIO - PIO SiO - CTC- PIO cTC- PIO- sid PIO - SIO - CTC PIO - CTC- SIO SIO - PIO- CTC = (Note) * State after reset wiwnd =30000 @2o3300 =O-0-0 170489 Figure 3.9.1 Interrupt priority Register (INTPR) Example: When 101 is written in address F4 (INTPR), the daisy chain interrupt priority is given as shown in Figure 3.9.2. IEO [ | Il sIO 1EO iE] PIO EO lEl CTC 1EO 170489 Figure 3.9.2 Daisy Chain Interrupt Priority MPUZ80ASSP-149TOSHIBA TMPZ84C015B 4. ELECTRICAL CHARACTERISTICS 4.1 Maximum Ratings SYMBOL ITEM RATING vcc Vcc Supply Voltage with respect to Vss -O0.5V to +7.0V VIN Input Voltage -0.5V to Vcc + 0.5V PD Power Dissipation (10MHz VERSION : TA = 70C) 250mW TSOLDER | Soldering Temperature (Soldering Time 10 sec) 260C TSTG Storage Temperature - 55C to 125C TOPR Operating Temperature 10MHz VERSION - 40C to 70C 4.2 DC Electrical Characteristics 020790 10MHz VERSION TOPR= 40C to + 70C, VCC=5V 110%, VSS=0V a) SYMBOL PARAMETER TEST CONDITION min. | Typ. | max. | UNIT. VILC apt Low Voltage -03 _ 06 Vv VIHC ceeLe High Voltage vec-0.6 | |vec+o3 | v oe f= |p ww [Ra ha 2|- [me | 9 VILR ORESED Voltage -05 | - 045] Vv VIHR RES Voltage vec-0.6 | vec V VOLC vaKouy eee lOL =2.0mA - - o6 | v VOHC ov encouny Voltage IOH = -2.0mA vec-06 | - V vot Ouieut mt cLeOUN IOL=2.0ma - - 04] v VOH1 ov ecept LKOUT 1 | loH= ~1.6ma 24] - - v VOH2 econ etKOu 2 | oH = ~250pa vec-08 | - v thi Input Leakage Current Vss 3 VINS Vee - _ +10 pA ~ = uo [Pisoupainione[Vsaveu ) = [se [= 020790 MPUZ80ASSP-150TOSHIBA TMPZ84C015B (2/2) SYMBOL PARAMETER TEST CONDITION MIN. TYP. MAX. UNIT. ICC Power Supply Current VCC =5V fCLK =( 1) VIHC = VIHR = VIH =VCC-0.2V, VILC = VILR =VIL=0.2V AF-10 45 55 mA Icc2 Stand-by Supply Current (See Note (2) ) vcc=5V fCLK =( 1) VIHC = VIH = VIHR =VCC-0.2V, VILC = VIL =VILR =0.2V AF-t0 0.5 50 pA Icc3 Power Supply Current (IDLE 1 Mode) vcc =5V fCLK =( 1) VIHC = VIH = VIHR =VCC-0.2V, VILC = VIL = VILR = 0.2V AF-10 2.5 Icc4 Power Supply Current (IDLE 2 Mode) vcc =5V fCLK =( 1) VIHC = VIH = VIHR = VCC-0.2V, VILC = VIL = VILR =0.2V AF-10 19 25 mA Note 1: Note 2: fCLK =1/TcC (MIN) 110690 ICC2 Stand-by Supply Current is guaranteed only when the supplied clock is stopped ata low level during T4 state of the following machine Cycle (M1) next to OP code fetch Cycle of HALT instruction. Except SYNCA =0 or SYNCB=0 state MPUZ80ASSP-151TOSHIBA TMPZ84C015B 4.3 AC Electrical Characteristics (1) (in Active State) 10MHz VERSION : TA=-40C~70C, VCC =5V+ 10%, VSS=0V 4.3.1 AC Characteristics of MPU (in Active State) (1/2) TMPZ84C015BF-10 NO. SYMBOL PARAMETER (10MHz} UNIT MIN. | TYP. | MAX. 1 [Tee Clock Cycle Time 100 | DC ns 2 |TwCh Clock Pulse Width (High) 38 - DC ns 3 | Twel Clock Pulse Width (Low) 38 - Dc ns 4 |Tfc Clock Fali Time _ - 12 ns 5 |Trc Clock Rise Time - - 12 ns 6 {TdCr(A) Clock f to Address Valid Delay - - 75 ns 7 |TdA (MREQF) Address Valid to MREQ | Delay 5] - ns 8 | TdCf (MREQF) Clock | to MREQ | Delay - _ 55] ns 9 |TdCr (MREQr) Clock f to MREQ f Delay _ _ 55 ns 10 | TWMREQh MREQ Pulse Width (High) 32] - - ns 11 | TWMREQI MREO Pulse Width (Low) 75) - - ns 12 | TdCf (MREQr) Clack | to MREQ 7 Delay - - 55] ns 13 | TdCf (RDf) Clock | to RD | Delay _ - 65] ns 14 | Tdr (RDr) Clock f to RD f Delay - - 55 ns 15 | TsD (r) Data Setup Time to Clock } 25 - - ns 16 |ThD (RDr) Data Hold Time to RD } Oo; - ns 17 | TSWAIT (Cf) WAIT Setup Time to Clock J 25/ - ns 18 | THWAIT (Cf) WATT Hold Time after Clock J 0} - - ns 19 |TdCr (M1f) Clock f to M7 | Delay - > 65 ns 20 | TdCr (M1r) Clock T to M7 f Delay _ - 65 | ns 21 | TdCr (RFSHf) Clock f to RFSH | Delay - - 80 ns 22 | TdCr (RFSHr} Clock f to RFSH 7 Delay _ - 80 ns 23 | TdCf (RDr) Clock | to RD f Delay _ ~ 55 | ns 24 |TdCr (RDf) Ciock f to RD | Delay _ - 55 ns 25 |TsD (cA | Md or Mi Gide { during M2, M3, 25 _ _ ns 26 | TdA (IORQF) Address Stable prior IORQ | 70 _ _ ns 27 | TdCr (IORQF) Clock f to IORQ | Delay _ - 50 ns 110690 MPUZ80ASSP-152TOSHIBA TMPZ84C015B (2/2) TMPZ84C015BF-10 NO. SYMBOL PARAMETER (10MHz} UNIT MIN. | TYP. | MAX. 28 | TdCf(IORQr) Clock | to JORQ 7 Delay - - 55 ns 29 |TdD (WRf) Data Stable Prior to WR | 40) - - ns 30 | TdCf (WRf) Clock | to WR | Delay - _ 55| ns 31 |TwWWR WR Pulse Width 754 - - ns 32 | TdCf (WRr) Clock | to WR f Delay - - 55 | ns 33 |TdD (WRf) Data Stable Prior to WR | -8) - - ns 34 |TdCr (WRf) Clock t to WR | Delay - - 50| ns 35 | TdwWRr (D) Data Stable from WR T 12] - - ns 36 | TdCf (HALT) Clock | to HALT for | - - 90 | ns 37 |TwNMI NMI Pulse Width 65} - ns 38 | TsBUSREQ (Cr) BUSREQ Setup Time to Clock 30; - - ns 39 |ThBUSREQ (Cr) | BUSREQ Hold Time after Clack T 10} - ns 40 |TdCr(BUSACKf) | Clock T to BUSACK | Delay - - 75) ns 41 |TdCf(BUSACKr) | Clock | to BUSACK f Delay ~_ - 75 ns 42 |TdCr (Dz) Clock f to Data Float Delay _ > 65 | ns 43. |Tdcr (CT2) CAREC ORGY BO, ou Delay) | | 60] ns 44 |TdCr (Az) Clock T to Adress Float Delay - - 65 ns 45 |Tdcr (A) Adie yon TBD T,and WR f to 32{| | - | ns 46 | TsRESET (Cr) RESET to Clock f Setup Time 40} _ ns 47 | ThRESET (Cr) RESET to Clock ? Hold Time 10) - ns 48 | TsINTf (Cr) INT to Clock T Setup Time 50; - ns 49 | TsINTr (Cr) INT to Clock f Hold Time w, - - ns 50 |TdMif(IORQF) | M1 to IORQ | Delay 222 | - ns 51 | TdCf (IORQF Clock | to TORQ | Delay - - 55| ns 52 | TdCr (}ORQr) Clock to IORQ 7 Delay - - 55| ns 53 | TdCf (D) Clock | to Data Valid Delay - - 110 ns 120690 MPUZ80ASSP-153TOSHIBA TMPZ84C015B 4.3.2 AC Characteristics of CGC (in Active State) TMPZ84C015BF-10 NO. SYMBOL PARAMETER (10MHz2) UNIT MIN. | TYP. | MAX. 54 |TcC CLK Output-Clock Cycle _ 100 _ ns 55 |TwCh CLK Output-Clock Width(High) 40 - - ns S6 |TwCl CLK Output-Clock Width(Low) 40 - - ns 57 |TfC CLK Output Clock fall time - - 10 ns 58 /TrC CLK Output Clock rise time - - 10 ns CLKOUT restart time by _ [2144 _ 59 TRST (INT) S INT (STOP Mode) 2.5TcC ns CLKOUT restart time by NMI (STOP| (2144 _ 60 | TRST (NMI) S$ Mode) b 5Tcc ns CLKOUT restart time by _ 2.5 _ 61 | TRST (INT) | INT (IDLE 1/2 Mode) aTcC ns CLKOUT restart time by NMI (IDLE 1/2 _ 2.5 _ 62 | TRST (NMi) | Mode) Tee ns CLKOUT restart time by RESET T 63 | TRST (RESET) | (IDLE 1/2 Mode) - TeC | ns 020790 MPUZ80ASSP-154TOSHIBA TMPZ84C015B 4.3.3 AC Characteristics of CTC (in Active State) TMPZ84C015BF-10 NO. SYMBOL PARAMETER (10MHz) UNIT MIN. | TYP. | MAX. Delay from M7 fall to IEO fall 64 | TdM1 (IEO) (in case of generating only interrupt - - 130 ns immediately before M1 cycle) Delay from IEI rise to IEO rise | | . 65 | TdlEt (IEOF) Delay from IEI fall to IEO fall - - 50 ns 66 | TdIEl (IEOr) (after ED decode) - - 120 ns CLK /TRG setup to TL f for detection of | TcC interrupt +100) _ _ tsCTR (c) Satisfied +768 +748 67 | IsCLK (INT) ns tsCTR (c) not Satisfied 2TcC +100); _ _ +768 +T48 68 |TcCTR CLK / TRG Frequency 2Tcec _ _ ns (counter mode) 69 |TrCTR CLK /TRG rising time - _ 30 ns | 70 |TfCTR CLK /TRG falling time - - 30 | ns 71 =|TwCTRi CLK / TRG Pulse Width (Low) 90 _ - ns 72 = |TwCTRh CLK / TRG Pulse Width (High) 90 - - ns CLK/TRG 7 to Clock f Setup Time for 73 | TsCTR (Cs) Immediate count 110} - ns (counter mode) CLK/TRG 7 to Clock T Setup Time for 74 | TsCTR (CT) enabling of Prescaler on following 110} - ns clock 7 (timer mode) 75 |Tdc (ZC /TOr) Clock f to ZC/TO 7 Delay - - 110 ns 76 |TdC (ZC/TOF) Clock | to ZC/TO | Delay - - 110 ns 110690 MPUZ80ASSP-155TOSHIBA TMPZ84C015B 4.3.4 AC Characteristics of PIO (in Active State) TMPZ84C015BF-10 NO. SYMBOL PARAMETER (10MHz) UNIT MIN. | TYP. | MAX. 77 | TdM1 (IEO) Delay from MT fall to IEO fall - - 100 ns 78 | TsIEI (10) (INTAGuie) for JORQ fall so} | - | ns 79 | TdlEl (IEOF} Delay from IE! fall to 1EO fall - - 50 ns 80 | TdIEl (IEOr) Delay from IEI rise to IEO rise - _ 120 ns 81 |TdC (RDYr) Delay from clock fall to READY rise - - 150 ns 82 |TdC(RDYf) Delay from clock fall to READY fall - - 110 ns 83 | TwSTB (C) STROBE pulse width 100 - - ns Set-up time of STROBE rise for clock 84 | TsSTB (C) fan case of making READY to active by 100 ~ ~ ns next cycle) Delay from IORQ rise to port data 85 | TdlO (PD) stable - _ 140 ns (Mode 0) Port Data set-up time for STROBE rise (Mode 1) 86 | TsPD (STB) Output Port data delay time from 87 |TdSTB (PD) STROBE fall _ - 150 ns (Mode 2) Delay from STROBE rise to data float (Mode 2) STROBE setup to TL f for detection of 350 interrupt +T48 88 | TdSTB (PDr) - - 120 ns 89 | IsSTRB Port data stable setup to TL? for 350 90 | IsPD detection of inter-rupt +748] - ns (Mode 3) Data Hold time for STROBE rise 91 | ThPD (STB) (Mode 1) 40 _ - ns 110690 MPUZ80ASSP-156TOSHIBA TMPZ84C015B 4.3.5 AC Characteristics of SIO {in Active State) (1/2) TMPZ84C015BF-10 NO. SYMBOL PARAMETER (10MHz) UNIT MIN. | TYP. (MAX. 92 |TsM1(C) M1 f to clock f Setup time 50 - - ns 1E1 | to IORQ | Setup time _ _ 93. | TslEI (10) (INTACK cycle) 100 ns M1 | to lEO | Delay |e 94 |TdM1 (IEO) (interrupt before M1) 120 ns IEI } to IEO f Delay _ |. 95 1|TdiEl (IEOr) (after ED decode) 120 ns 96 | TdIEt (IEOf) IEl | to 1EO | Delay _ _ 50 ns 97 |Tdio (wRWA) 1ORQ | or CE | to W/RDY | Delay _ _ 130 ns (Wait mode) Clock f to W/RDY | delay _ _ 98 | TdC (VW/RRf) (Ready Mode) 80 ns Clock | to W/RDY float delay _ _ 99 | TdC (W/RWZ) (Wait mode) 90 ns 100 | TwPh Pulse Width (High) 200 - - ns 101 | TwPl Pulse Width (Low) 200 - > ns 102 | TcTxC Tx cycle time 250 - 0 ns 103 | TwTxcl TxC Width (Low) 80 | - co ns 104 | TwTxCh TxC Width (High) 80 - oo ns 105 {TdTxc (TxD) _| PxC | to TxD delay - | = | 180 | ns {x1 mode) 106 |TdTxc (WRRF) | TxC | to WIRDY | delay (Ready mode) 5 | - 9 mains 107 | TcRxC RxC cycle time 250 - 00 ns 108 | TWRxCcl RxC Width (Low) 80 - 20 ns 109 | TwRxCh RxC Width (High) 80 - ns RxD to Rx f Setup _ _ 110 | TSRxD (Rxc) time (x1 mode) 10 ns 111 | THRxD (Rxo) RxC f to RxD hold time 80 _ _ ns (x1 mode) 112 [TARxc (W/RRF) | RXCT to WIRDY | delay 10 | - 13, | CLK (Ready mode) Periods RxC 7} to SYNC | delay _ CLK 113 | TARKC (SYNC) (Output mode) 4 7 Periods 110690 MPUZ80ASSP-157TOSHIBA TMPZ84C015B8 (2/2) TMPZ84C015BF-10 NO. SYMBOL PARAMETER (10MHz) UNIT MIN. | TYP. | MAX. 114 | TsSYNC (Rxe) TON U0 Rac setup, 100 | | | os 115 |IsTxc ret to TL f for detection of on _ oe ns 116 | IsRxc ee to TL f for detection of On _ Set ns 110690 4.3.6 AC Characteristic of WDT (in Active State) TMPZ84C015BF-10 NO. SYMBOL PARAMETER (t0MHz) UNIT MIN. | TYP. | MAX. 117 | Tde (WOTF) Clock f to WOTOUT J Delay _ _ 120 ns 118 | Tdc (WDTr) Clock f to WDTOUT f Delay - - 125 ns WDTOUT Out put period WDT Mode 0 jT14216} ns 119 | TcWDT WDT Mode 1 1714218) ns WDT Mode 2 {714220} ns WDT Made 3 1714222; ns 110690 Note 1: Timing Measurements are made at the following voltage. Input VIH =2.4V, VIL=0.4V, VIHC=VCC_ 0.6V, VILC =0.6V Output VOH =2.2V, VOL=0.8V (Exept CLKOUT) CL=100pF MPUZ80ASSP-158TOSHIBA TMPZ84C015B 44 AC Timing Charts (1) (in Active State) 4.4.1 AC Timing Charts of MPU (in Active State) Figures 4.4.1 through 4.4.8 show the basic timing charts. The circled numbers in these charts correspond to the numbers in the number column of the AC Electrical Characteristics Tables. 11 T2 TW T3 T4 CLKIN 2 4 1 AO~A15 A7RF 300389 Figure 4.4.1 Opcode Fetch Cycle MPUZ80ASSP-159TOSHIBA TMPZ84C015B Ti T2 TW T3 CLKIN AQ~A15 RD Input data Read operation DO~D7 Write operation DO~D7 output 300389 Figure 4.4.2. Memory Read / Write Cycle T2 Tw TW T3 CLKIN AQ~A7 {ORQ WAIT RD Input f operatio Input data DO~D7 WR Output operatio DO~D7 Notel: waitstate (TW*) is inserted automatically by MPU. 300389 Figure 4.4.3 1/0 Cycle MPUZ80ASSP-160TOSHIBA TMPZ84C015B TL T1 T2 TW: TW: TW T3 CLKIN | ) AO~A15 ram counter |g a QD | WAIT DO~D7 4 *1: VALID DATA Notes 1. TL: Last state of instruction 2. 2-wait state (TW*) is inserted automatically by MPU 300389 Figure 4.4.4 Interrupt Request/Acknowledge Cycle Last M cycle AO~A15 | e + < MT 1@ 6 MREQ } N Y RD ry f ___ @ @Q- | RFSH Note: NMI is asynchronous, but its falling edge signal must occur synchroncusly with the rising edge of previous TL state for correct response to the subsequent machine cycles. 300389 Figure 4.4.5 Non-maskable Interrupt Request Cycle MPUZ80ASSP-161TOSHIBA CLKIN BUSREQ BUSACK A0~A15 DO~D7 eM Floating state Notes 1. TL: Last state ofa given machine cycle 2. Tx: Clock used by peripheral LSI that made request. Figure 4.4.6 Bus Request / Acknowlege Cycle M1 of halt instruction TMPZ84C015B 300389 M1 | M1 | T4 TI T2 T3 T4 T1 CLKIN _ <>| <~|6) HALT f NMI V Note: INT signal is also used for releasing HALT state. Figure 4.4.7 HALT Acknowledge Cycle 300389 MPUZ80ASSP-162TOSHIBA TMPZ84C015B j~ M1 +----- 71 T2 a) __ @, <= g 71 RESET f_\ wt h_/ AOQ~A15 Floating state oO Pe >1@\< DO~D7 5 \ Floating state >| ~< MT ec -MREO *F RD, WR LLL \ 1ORQ RFSH BUSACK HALT 300389 Figure 4.4.8 Reset Cycle 4.4.2 AC Timing Charts of CGC (in Active State) The following Figures show the timings in each operation mode with the CLKOUT pin connected to the CLKIN pin. CLKOUT Ne 6) YY S/S WY YS bt @~ <_ ) 300389 Figure 4.4.9 CLKOUT Waveform TI T2 T3 CLKOUT 14 Ne <6) > \ / \ >| <<_ > -<(58) @ _ iNT | NMI \ / 300389 Figure 4.4.10 Clock Restart Timing (STOP Mode) MPUZ80ASSP-163TOSHIBA TMPZ84C015B T1 T2 T3 CLKOUT 14 Fo \NL TS NL SF 67) INT | | NMI t__/ 300389 Figure 4.4.11 Clock Restart Timing (IDLE1 Mode) CLKOUT SVS VS LSD TI T2 Internal CLK 14 Li \ / \ > INT | NMI U/l 300389 Figure 4.4.12 Clock Restart Timing (IDLE2 Mode) 71 cCLKOUT + / / \aamend <) >| RESET \ / 300389 Figure 4.4.13 Timing of Clock Start by RESET (IDLE1 and IDLE2 Modes) MPUZ80ASSP-164TOSHIBA TMPZ84C015B 4.4.3 AC Timing Charts of CTC (in Active State) 3 CLKIN 2 @ 1 M1 tEl 1EO CLK / TRGO-3 {Counter mode) CLK / TRGO-3 (Timer mode) ZC/TOo-3 300389 Figure 4.4.14 CTC Timing Diagram TL CLKIN JS WSs XY, / \ K \ / \ C0 een enn nen ene se INT Wee ee ee LL ee eee ee (63) A, Y CLK / TRGD-3 _} 5 TL : Last state of instruction 300389 Figure 4.4.15 CTC Interrupt Occurrence Timing MPUZ80ASSP-165TOSHIBA TMPZ84C015B 4.4.4 AC Timing Charts of PIO (in Active State) CLK IN | 5 a OQ 1E1 IEO READY (ARDY OR BRDY) STROBE (ASTB OR BSTB) MODEO PAO~PA7 } MODE] PBO~PB7 MODE2 300389 Figure 4.4.16 PIO Timing Diagram CLK IN S-\__/ \x / \ f \ / \ INT noe 4-5 eee ee ee Le 4E9) STROBE - (ASTB OR BSTB) ar (3) PAQ~PA7 gS PBO~PB7 MODE3 ts TL: Last state of instruction 300389 Figure 4.4.17 PIO Interrupt Occurrence Timing MPUZ80ASSP-166TOSHIBA TMPZ84C0158 4.4.5 AC Timing Charts of SIO (in Active State) CLKIN {El IEO W/RDY \ 300389 Figure 4.4.18 (a) SiO Timing Diagram MPUZ80ASSP-167TOSHIBA TMPZ84C015B CTS, DCD, SYNC 2S @ TxC TxD W/RDY RxD 300389 Figure 4.4.18 (b) SIO Timing Diagram MPUZ80ASSP-168TOSHIBA TMPZ84C015B TL CLKIN Sf \ Ss \s / \ j \ / \ INT TOT TTT eee to ~ { TXC \ @- 5 RXC j TL : Last state of instruction 300389 Figure 4.4.19 SIO Interrupt Occurrence Timing 4.4.6 AC Timing Charts of WDT (in Active State) _4 - WDTOUT | F 5 \ wag . 300389 Figure 4.4.20 WDT Timing Diagram MPUZ80ASSP-169TOSHIBA TMPZ84C015B 4.5 AC Electrical Characteristics (2) (in Inactive State) TA=40C~ + 70C, VCC =5V+ 10%, VSS=0V 4.5.1 AC Characteristics of CGC (in Inactive State) TMPZ84C015BF-10 NO. SYMBOL PARAMETER (10MHz) UNIT MIN. | FYP. |} MAX. 1 | FeCCLK Output Clock Cycle - 100 - ns 2 | TwChCLK Output Clock Width (High) - 40 - ns 3) |TwCICLK Output Clock Width (Low) - 40 - ns 4 |TfCCLK Output Clock fall Time _ 10 - ns 5 | TrCCLK Output Clock rise Time - 10 ns Clock (CLKOUT) restart Time by INT _ fae yp 6 | TRST (INT) S (STOP mode) 2.5TcC ns Clock (CLKOUT) restart Time by NMI {244 ] 7 JTRST(NMI)S | erOp mode) 2.5TcC ns Clock (CLKOUT) restart Time by INT _ 2.5] _ 8 [TRST (INT) | (IDLE 1/2 mode) acc ns Clock (CLKOUT) restart Time by NMI _ 25) _ 9 TRST (NMI) | (IDLE 1/2 mode) Tec ns Clock (CLKOUT) restart Time by RESET _ _ 10 | TRST (RESET) I (IDLE 1/2 mode} 1TcC ns 11. | TSHALT (M1r) HALT Set up Time 10 - - ns 020790 4.5.2 AC Characteristics of CTC (in Inactive State) (1/2) TMPZ84C015BF-10 NO.| SYMBOL PARAMETER (10MHz) UNIT MIN. | TYP. | MAX. 12 |TeC ClocK Cycle Time 100 - _- ns 13 |Twch ClocK width (High) 38 - - ns 14 | Twel Clock width (Low) 38 - - ns 15 |Tfc Clock falling time - 12 ns 16 |Trc ClocK rising time - - 12 ns 17 |Th Hold Time 10 - - ns 18 | TcCS(C) CS (A1, AO) Set up time to clock t 100 - - ns 19 | TSCE (Cc) CE (A7~A2) Set up time to clock t 80 - - ns 20 | TstO (Cc) IORG | Set up time to clock f a i - ns 20790 MPUZ80ASSP-170TOSHIBA TMPZ84C015B (2/2) TMPZ84C015BF-10 NO. SYMBOL PARAMETER (10MHz) UNIT MIN. | TYP. | MAX. 21 | TsRD (C) RD | Setup time to clock T 55 | - ns 22 |TdC (DO) Clock f to Data Valid Delay - - 110 ns 23 |Tdc (DOz) IORQ, RD 7 to Data Float Delay _ - 85 ns 24 |TdCr (M1f) Data Input Set up time to clock 40 - - ns 25 | TsM1 (C) M1 Set up time to clock T 55 |] - ns Mi | tolEO | Delay 26 |TdM1 (IEO) {in case of generating only interrupt ~ - 110 ns immediately before MT cycle) , 27 | TdiO (DOI) IORQ |, to Data out Delay (INTA Cycle) - _ 85 ns 28 | TdiEl (IEOf) JEL |} to lEO | Delay _ _- 60 ns 29 | TdiEl (IEOf) IEl t to IEO 7 Delay (after ED decode) - - 160 ns a TcC 30 | TdC (INT) Clock f to INT | Delay - leq} CLK/TRG 7 to INT | Delay TcC | TsCTR (c) Satisfied |+110) ! +737 | 31 |TdA (lORQf) ns 2TcC TsCTR {c) not Satisfied |+110;) +137 32 |TcCTR CLK / TRG Frequency - 2TcC _ ns | 33 | TrCTR CLK /TRG rising time - - 30 ns 34 |TfCTR CLK / TRG falling time - - 30 ns 35 | TwCTRI CLK / TRG pulse width (Low) 90 _ _ ns 36 |TwCTRh CLK /TRG pulse width (High) 90 - - ns CLK/TKG fF to clock t Setup 37 | TsCFR (CS) Time for Immediate Count 410 - _ ns (counter mode) CLK/TRG f to clock T Setup 38. | TsCTR (CT) Time for enabliling of Prescaler on 110 _ _ ns following clock (timer mode) 39 |Tdc (ZC /TOr) Clock f to ZC/TO 7 Delay - - 110 ns 40 |TdC (ZC/TOF) Clock | to ZC/TO |, Delay - - 110 ns 030790 MPUZ80ASSP-171TOSHIBA TMPZ84C015B 4.5.3 AC Characteristics of PIO (in Inactive State) TMPZ84C015BF-10 NO.{ SYMBOL PARAMETER (10MHz) UNIT MIN. | TYP. | MAX. 41 |Tscs (RN cr $00) BALAN), C/D(Ao) Set up} sy | | _ | ng 42 |Th Hold Time 40 - - ns 43 |TsRI(C) RD, TORQ Set up time to clock } 60 _ ~_ ns 44 |TdRI (DO) RD, iORQ | to Data out Delay - | 200 | ns 45 |TdRI (DOs) RD, IORQ * to Data float Delay ~ 70 ns 46 | TsDI(C) Data Set up time to clock T 40 - _ ns 47 |TdlO (DOI) TORQ | to Data out Delay (INTA Cycle) - _ 85 ns 48 |TsM1 (Cr) M1 | Setup time to clock T 50 | - ns 49 |TsM1(Cf) M17? Setup time to clock | (M1 cycle) 0 _ - ns 50 |TdM1 (IEO) (interrupt immed rely receding M1) ~ ; ~ 100 ns 51 | TsIEI (10) 1El Set up time to TORQ | (INTA Cycle) 80 - - ns 52 | TdlEt (IEOf) IEl | tolEO | Delay _ _ 70 ns 53 | TdiEl (IEOr) IEl T to IEO } Delay (after ED Decade) - - 120 ns 54 |TdlO (Cc) TORQ Set up time to Clock | 120 - - ns 55 |TdC (RDYr) Clock | to READY 7 Delay - - 150 ns 56 |TdC (RDYf) Clock | to READY | Delay _ _ 110 ns 57 | TWSTB (C) STROBE Pulse width 100 |} - ns Set up time of STROBE rise for clock fall 58 | TsSTB (C) {in case of making READY to active by 100 - - ns next cycle) 59 |TdlO (PD) may rom TORQ rise to Portdata stable | _ _ 140 ns 60 | TsPD (sTB) ee set up time for STROBE rise 150 | _ ns 61 | TdSTB (PD) et Ma seo time from | | 150 | ns 62. |TdSTB (PDr) hoot Msc ise to Port data | | 120 | ns 63. [TdPD (INT) may fom port data match to INT fall _ _ 350 ns 64 | TdSTB (INT) Delay from STROBE rise to INT fall - - 250 ns 020790 MPUZ8&CASSP-172TOSHIBA TMPZ84C015B 4.5.4 AC Characteristics of SIO (in Inactive State) (1/2) TMPZ84C015BF-10 NO. SYMBOL PARAMETER (10MHz) UNIT MIN. | TYP. | MAX. CE (A7 to A2),C/D(A0), _ _ 65 | TsCS(C) B/A (A1) Set up time to clock T 40 ns 66 |TsRD (C) TORQ, RD Set up Time to clock T 55 - - ns 67 |TdC (DO) Clock f to Data output Delay - _ 100 ns Data input set up time to clock _ _ 68 | TsDI(C) (write cycle or Mi cycle) 30 ns 69 |TdRD (DOz) RD f to Data Out Float Delay - - 70 ns IORQ | to Data out put Delay _ _ 70 |TdlO (DON) (INTACK cycle) 85 | ns 71 | TsM1(C) M1 Set up time to clock T 50 - _ ns 72 (| TslEl (lO) TEI Set up time to TORQ | (INTACK Cycle) 80 - - ns M1 | tolEO | Delay M1 (IE . - _ 73 |Td (1EO) (interrupt before M1) 120 ns 74 | TdIlEl (lEOr) IEI f to IEO T Delay (After ED Decode) - - 120 ns 75 | TdiEl (LEOf) IEl | to 1EO | Delay - _ 50 ns 76 | TdC (INT) Clock 7 to INT | Delay - - 100 ns IORQ, CE (A7 to A2) | to f _ _ 77 |TAIO (WIRWA) arRDY | Delay (Wait Mode) 130 | ns 78 |Tdc (W/RRf) Clack T to W/RDY | Delay (Ready Mode) - - 80 ns Clock | to W/RDY Float Delay _ _ 79 | Tdc (W/RWz) (Wait Mode) 90 ns 80 | Th, Thics) Any unspecified hold When set up is 0 _ _ ns specified 81 |TwPh Pulse width (High) 200 - - ns 82 | TwPI Pulse width (Low) 200 - - ns 83 | TcTxc TxC Cycle time 250 | co ns 84 | TwTxCcl TxC width (Low) 80 - oo ns 85 | TwTxch TxC width (High) 80 - oo ns 86 | TdTxC (TxD) TxC | to TxD Delay (x1 Mode) - _ 180 ns 87 |TdTxc (W/RRf) |TxC | to WRDY | Delay (Ready mode) 5 | - 9 pain is 88 | TdTxC (INT) TxC | to INT | Delay 5 - g |, clk Periods 89 |TcRxC RxC Cycle time 250 | co ns 020790 MPUZ80ASSP-173TOSHIBA TMPZ84C015B (2/2) TMPZ84C015BF-10 NO. SYMBOL PARAMETER (10MHz) UNIT MIN. | TYP. | MAX. 90 | TWwRxcl Rx width (Low} 80 _ ns 91 | TwRxCh RxC width (High) 80 - 0 ns 92 | TsRxD (RxC) RxD to RxC * Set up time (x1 mode) 0 _ - ns 93 | ThRxD (RxC) RxC f to RxD Hold time (x1 mode) so | - ns 94 |TdRxC (W/RRf) |RxC T to W/RDY | Delay (Ready mode) 10 - 13 Perinds 95 {TdRxC{INT) | RxC T to INT | Delay 1o | | 13 f, CLK Periods 96 |TdRxC (SYNC) |RxC f to SYNC | Delay (output modes) 4 ~ 7 Prins 97 | TsSYNC (RxC) Ce fo RCT Set up Time -o0f - | | ns 98 | TsAdd (Cr) Address Set up time to clock T 150 - - ns 99 |TstO (Cr) TORQ | Set up time to clock t 70 | - ns 100 |TdRD (Cr) RD | Set up time to clock T 70 | - ns 101 |TdCr (Do) Data out Delay to clock t - - 130 ns 102 | TdIORDr(DoZ) | Data Float Delay to IORQ 4 ,RDT - - 90 ns 103 | TsWR (Cr) WR | Set up time to clock f 70} - - ns 104 | TsDI (Cr) Data Input Set up time to clock T 0 - - ns 105 | THlOWRE (D) Data Hold time to IORQ 7, WR 20 _ _ ns 020790 MPUZ80ASSP-174TOSHIBA TMPZ84C015B 4.5.5.AC Characteristics of WDT (in Inactive State) TMPZ84C015BF-10 NO. SYMBOL PARAMETER (10MHz) UNIT MIN. | TYP. | MAX. 106 | TdC (WDTF) Clock f to WDTOUT |, Delay - - 120 ns 107 | TdC (WDTr) Clock T to WDTOUT f Delay _ _ 125 ns WDTOUT out put period WDT Mode 0 |t12,/ - ns 216 WDT Mode 1 - |T12,]) - ns 108 | TCWDT 218 WODT Mode 2 - |T12,]) 7 ns 220 WDT Mode 3 - |T12,] 7 ns 222 020790 Notel: Timing Measurements are made at the following voltage. Input VIH =2.4V, VIL=0.4V VIHC=VCC 0.6V, VILC =0.6V Output VOH=2.2V, VOL=0.8V (Except CLKOUT) CL=100pF MPUZ80ASSP-175TOSHIBA TMPZ84C015B 4.6 AC Timing Charts (2) (in Inactive State) 4.6.1 AC Timing Charts of CGC (in Inactive State) The following Figures show the timing charts in each operation mode with the CLKOUT pin connected to the CLKIN pin. CLKOUT W-Q= o> PN NNN >*=E (4) Y 300389 Figure 4.6.1 CLKOUT waveform TI T2 73 CLKOUT 4 j <> (2) @-||- +|--@ <_(1) > | INT ye @ | NMI \ __/ 300389 Figure 4.6.2 Clock restart timing (STOP mode) MPUZ80ASSP-176TOSHIBA TMPZ84C015B T1 T2 T3 (8) INT | NMI XY / 300389 Figure 4.6.3 Clock restart timing (IDLE1 mode) cakout_/S ViHS We S/S WS YX 11 12 INTERNAL 14 x \ / \ CLK ~ _ INT \ _ NMI / 300389 Figure 4.6.4 Clock restart timing (IDLE2 mode) 300389 Figure 4.6.5 Timing of clock restart by RESET (IDLE1, IDLE2 mode) Ta T1 T? T3 T4 cK fA fT MN CD IL 3) G HALT \ 300389 Figure 4.6.6 Clock suspension timing (IDLE1,IDLE2 and STOP modes) MPUZ80ASSP-177TOSHIBA 4.6.2 AC Timing Charts of CTC (in Inactive State) [ CLKIN CSo0.1 (Ao.1) CE (Ao~7) Read 1OR' CLK/TRGo.3 (COUNTER MODE) CLK/TRGo.3 (TIMER MODE) ZC/TO93 Figure 4.6.7 CTC timing diagram (Inactive) TMPZ84C015B 300389 MPUZ80ASSP-178TOSHIBA TMPZ84C015B 4.6.3 AC Timing Charts of PIO (in Inactive State) CE (A7~A2) B/A(A1), C/D(A0) RD, CLKIN 1ORQ 1El READY (ARDY OR BRDY) STROBE {ASTB OR BSTB) Pao~Paz Pgo~Pa7 MODEO MODE! MODE2 MODE3 2 ql Figure 4.6.8 PIO timing diagram (Inactive) 300389 MPUZ80ASSP-179TOSHIBA TMPZ84C015B 4.6.4 AC Timing Charts of SIO (in Inactive State) CE, C/D, BA (A7~A2) (AO) (A1) CLKIN RD, TORQ DQ~D7 1El IEO W/RDY 300389 Figure 4.6.9 SIO timing diagram (a) (Inactive) MPUZ80ASSP-180TOSHIBA TMPZ84C015B CTS, DCD, SYNC TxC TxD W/RDY RxD WIRDY INT 300389 Figure 4.6.9 SIO timing diagram (b) (Inactive) MPUZ80ASSP-181TOSHIBA TMPZ84C015B 4.6.5 AC Timing Charts of WDT (in Inactive State) (The mode setting and daisy chain interrupt setting registers on WDT) Read Write T1 T2 TW T3 (D7~Do) A7~Ao 5 z oO (D7~Do) CLKIN SV te OT WDTOUT "ON j 300389 Figure 4.6.10 RD/WRITE, WDTOUT timing Diagram MPUZ80ASSP-182TOSHIBA 4.7 Pin Capacitance TMPZ84C015B SYMBOL ITEM TEST CONDITION MIN. | TYP. }| MAX. | UNIT CLOCK | Clock Input Capacitance - - . F=1MHz CIN Input Capacitance All terminals except that to - - TBD PF COUT | Output Capacitance be measured be earthed - - 020790 MPUZ80ASSP-183TOSHIBA TMPZ84C015B 5. EXTERNAL DIMENSIONS QFP100-P-1420A Unit: mm 23.840.3 20.0+0.2 50 0.825TYP 2 14.0 +0.2 17.840.3 100 31 O.S75TYP 3 =" 3.0 SMAX <| 240789 MPUZ80ASSP-184TOSHIBA (UC/UP) L3E D M@@.9097249 0017680 T TOSHIBA TMPZ84C015A 5. EXETERNAL DIMENSIONS T- 49-17-07 Unit: mm QFP100-P-1420B 14.040.1 16.220.4 19.6 0.3 20.0240,1 22.240.4 (2,9MAX,) MPUZ80-757