Product Folder Order Now Support & Community Tools & Software Technical Documents Reference Design TPS51200 SLUS812C - FEBRUARY 2008 - REVISED NOVEMBER 2016 TPS51200 Sink and Source DDR Termination Regulator 1 Features 3 Description * * * The TPS51200 device is a sink and source double data rate (DDR) termination regulator specifically designed for low input voltage, low-cost, low-noise systems where space is a key consideration. 1 * * * * * * * * * * Input Voltage: Supports 2.5-V Rail and 3.3-V Rail VLDOIN Voltage Range: 1.1 V to 3.5 V Sink and Source Termination Regulator Includes Droop Compensation Requires Minimum Output Capacitance of 20-F (Typically 3 x 10-F MLCCs) for Memory Termination Applications (DDR) PGOOD to Monitor Output Regulation EN Input REFIN Input Allows for Flexible Input Tracking Either Directly or Through Resistor Divider Remote Sensing (VOSNS) 10-mA Buffered Reference (REFOUT) Built-in Soft Start, UVLO, and OCL Thermal Shutdown Supports DDR, DDR2, DDR3, DDR3L, LowPower DDR3, and DDR4 VTT Applications 10-Pin VSON Package With Thermal Pad The TPS51200 maintains a fast transient response and requires a minimum output capacitance of only 20 F. The TPS51200 supports a remote sensing function and all power requirements for DDR, DDR2, DDR3, DDR3L, Low-Power DDR3 and DDR4 VTT bus termination. In addition, the TPS51200 provides an open-drain PGOOD signal to monitor the output regulation and an EN signal that can be used to discharge VTT during S3 (suspend to RAM) for DDR applications. The is available in the thermally efficient 10-pin VSON thermal pad package, and is rated both Green and Pb-free. It is specified from -40C to +85C. Device Information(1) PART NUMBER TPS51200 2 Applications * * * * * * * PACKAGE VSON (10) BODY SIZE (NOM) 3.00 mm x 3.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Memory Termination Regulator for DDR, DDR2, DDR3, DDR3L, Low-Power DDR3 and DDR4 Notebooks, Desktops, and Servers Telecom and Datacom Base Stations LCD-TVs and PDP-TVs Copiers and Printers Set-Top Boxes Simplified DDR Application VDDQ 1 REFIN VIN 10 3.3 VIN TPS51200 PGOOD VLDOIN 2 VLDOIN PGOOD 9 VTT 3 VO GND 8 4 PGND EN 7 SLP_S3 5 VOSNS REFOUT 6 VTTREF Copyright (c) 2016, Texas Instruments Incorporated 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPS51200 SLUS812C - FEBRUARY 2008 - REVISED NOVEMBER 2016 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 4 4 4 4 5 7 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Typical Characteristics .............................................. Detailed Description ............................................ 10 7.1 7.2 7.3 7.4 Overview ................................................................. Functional Block Diagram ....................................... Feature Description................................................. Device Functional Modes........................................ 10 10 10 16 8 Application and Implementation ........................ 17 8.1 Application Information............................................ 17 8.2 Typical Application ................................................. 17 8.3 System Examples ................................................... 20 9 Power Supply Recommendations...................... 26 10 Layout................................................................... 26 10.1 Layout Guidelines ................................................. 26 10.2 Layout Example .................................................... 27 10.3 Thermal Design Considerations............................ 27 11 Device and Documentation Support ................. 29 11.1 11.2 11.3 11.4 11.5 11.6 Device Support...................................................... Documentation Support ....................................... Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 29 29 29 29 29 29 12 Mechanical, Packaging, and Orderable Information ........................................................... 30 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (September 2016) to Revision C Page * Added references to DDR3L DRAM technology throughout .................................................................................................. 1 * Added DDR3L test conditions to Output DC voltage, VO and REFOUT specification .......................................................... 5 * Added Figure 4 ....................................................................................................................................................................... 7 * Added Figure 9 ....................................................................................................................................................................... 8 * Updated Figure 16 to include DDR3L data ............................................................................................................................ 9 Changes from Revision A (September 2015) to Revision B Page * Changed " -10 mA < IREFOUT < 10 mA" to "-1 mA < IREFOUT < 1 mA" in all test conditions for the REFOUT voltage tolerance to VREFIN specification ............................................................................................................................................. 6 * Changed all MIN and MAX values from "15" to "12" for all test conditions for the REFOUT voltage tolerance to VREFIN specification ................................................................................................................................................................. 6 * Updated Figure 19 ............................................................................................................................................................... 11 * Added REFOUT (VREF) Consideration for DDR2 Applications section................................................................................. 15 * Updated Figure 28 and Table 3............................................................................................................................................ 20 * Added clarity to Layout Guidelines section. ......................................................................................................................... 26 Changes from Original (February 2008) to Revision A Page * Added Pin Configuration and Functions section, ESD Rating table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section. .............................. 1 * Changed "PowerPAD" references to "thermal pad" throughout ............................................................................................. 3 * Deleted Dissipation Ratings table .......................................................................................................................................... 4 2 Submit Documentation Feedback Copyright (c) 2008-2016, Texas Instruments Incorporated Product Folder Links: TPS51200 TPS51200 www.ti.com SLUS812C - FEBRUARY 2008 - REVISED NOVEMBER 2016 5 Pin Configuration and Functions DRC Package 10-Pin VSON Top View REFIN 1 10 VIN VLDOIN 2 9 PGOOD VO 3 PGND 4 Thermal Pad VOSNS 5 8 GND 7 EN 6 REFOUT Pin Functions PIN NAME NO. I/O (1) DESCRIPTION EN 7 I For DDR VTT application, connect EN to SLP_S3. For any other application, use the EN pin as the ON/OFF function. GND 8 G Signal ground. PGND (2) 4 G Power ground for the LDO. PGOOD 9 O Open-drain, power-good indicator. REFIN 1 I Reference input. REFOUT 6 O Reference output. Connect to GND through 0.1-F ceramic capacitor. VIN 10 I 2.5-V or 3.3-V power supply. A ceramic decoupling capacitor with a value between 1-F and 4.7-F is required. VLDOIN 2 I Supply voltage for the LDO. VO 3 O Power output for the LDO. VOSNS 5 I Voltage sense input for the LDO. Connect to positive terminal of the output capacitor or the load. (1) (2) I = Input, O = Output , G = Ground Thermal pad connection. See Figure 35 in the Thermal Design Considerations section for additional information. Submit Documentation Feedback Copyright (c) 2008-2016, Texas Instruments Incorporated Product Folder Links: TPS51200 3 TPS51200 SLUS812C - FEBRUARY 2008 - REVISED NOVEMBER 2016 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN MAX REFIN, VIN, VLDOIN, VOSNS -0.3 3.6 EN -0.3 6.5 PGND to GND -0.3 0.3 REFOUT, VO -0.3 3.6 PGOOD -0.3 6.5 Operating junction temperature, TJ -40 150 C Storage temperature, Tstg -55 150 C Input voltage (2) Output voltage (2) (1) (2) UNIT V V Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to the network ground terminal unless otherwise noted. 6.2 ESD Ratings VALUE Electrostatic discharge V(ESD) (1) (2) Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) 2000 Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) 500 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN Supply voltages VIN EN, VLDOIN, VOSNS REFIN Voltage MAX UNIT 2.375 NOM 3.500 V -0.1 3.5 0.5 1.8 PGOOD, VO -0.1 3.5 REFOUT -0.1 1.8 PGND -0.1 0.1 -40 85 Operating free-air temperature, TA V C 6.4 Thermal Information TPS51200 THERMAL METRIC (1) DRC (VSON) UNIT 10 PINS RJA Junction-to-ambient thermal resistance 55.6 C/W RJC(top) Junction-to-case (top) thermal resistance 84.6 C/W RJB Junction-to-board thermal resistance 30.0 C/W JT Junction-to-top characterization parameter 5.5 C/W JB Junction-to-board characterization parameter 30.1 C/W RJC(bot) Junction-to-case (bottom) thermal resistance 10.9 C/W (1) 4 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright (c) 2008-2016, Texas Instruments Incorporated Product Folder Links: TPS51200 TPS51200 www.ti.com SLUS812C - FEBRUARY 2008 - REVISED NOVEMBER 2016 6.5 Electrical Characteristics Over recommended free-air temperature range, VVIN = 3.3 V, VVLDOIN = 1.8 V, VREFIN = 0.9 V, VVOSNS = 0.9 V, VEN = VVIN, COUT = 3 x 10 F and circuit shown in Figure 24. (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TA = 25 C, VEN = 3.3 V, No Load 0.7 1 TA = 25 C, VEN = 0 V, VREFIN = 0, No Load 65 80 200 400 1 50 A 0.1 50 A 1 A 15 mV 15 mV 15 mV 15 mV -15 15 mV SUPPLY CURRENT IIN Supply current IIN(SDN) Shutdown current A TA = 25 C, VEN = 0 V, VREFIN > 0.4 V, No Load ILDOIN Supply current of VLDOIN TA = 25 C, VEN = 3.3 V, No Load ILDOIN(SDN) Shutdown current of VLDOIN TA = 25 C, VEN = 0 V, No Load mA INPUT CURRENT IREFIN Input current, REFIN VEN = 3.3 V VO OUTPUT VREFOUT = 1.25 V (DDR1), IO = 0 A VREFOUT = 0.9 V (DDR2), IO = 0 A VVOSNS Output DC voltage, VO VREFOUT = 0.75 V (DDR3), IO = 0 A VREFOUT = 0.675 V (DDR3L), IO = 0 A VREFOUT = 0.6 V (DDR4), IO = 0 A VVOTOL 1.25 -15 V 0.9 -15 V 0.75 -15 V 0.675 -15 V 0.6 V Output voltage tolerance to REFOUT -2 A < IVO < 2 A -25 25 mV IVOSRCL VO source current Limit With reference to REFOUT, VOSNS = 90% x VREFOUT 3 4.5 A IVOSNCL VO sink current Limit With reference to REFOUT, VOSNS = 110% x VREFOUT 3.5 5.5 A IDSCHRG Discharge current, VO VREFIN = 0 V, VVO = 0.3 V, VEN = 0 V, TA = 25C 18 25 POWERGOOD COMPARATOR VTH(PG) VO PGOOD threshold PGOOD window lower threshold with respect to REFOUT -23.5% -20% -17.5% PGOOD window upper threshold with respect to REFOUT 17.5% 20% 23.5% PGOOD hysteresis tPGSTUPDLY PGOOD start-up delay Start-up rising edge, VOSNS within 15% of REFOUT VPGOODLOW Output low voltage ISINK = 4 mA tPBADDLY PGOOD bad delay VOSNS is outside of the 20% PGOOD window IPGOODLK Leakage current (1) VOSNS = VREFIN (PGOOD high impedance), VPGOOD = VVIN + 0.2 V 5% 2 ms 0.4 10 V s 1 A REFIN AND REFOUT VREFIN REFIN voltage range VREFINUVLO REFIN undervoltage lockout VREFINUVHYS REFIN undervoltage lockout hysteresis VREFOUT REFOUT voltage (1) 0.5 REFIN rising 360 390 1.8 V 420 mV 20 REFIN mV V Ensured by design. Not production tested. Submit Documentation Feedback Copyright (c) 2008-2016, Texas Instruments Incorporated Product Folder Links: TPS51200 5 TPS51200 SLUS812C - FEBRUARY 2008 - REVISED NOVEMBER 2016 www.ti.com Electrical Characteristics (continued) Over recommended free-air temperature range, VVIN = 3.3 V, VVLDOIN = 1.8 V, VREFIN = 0.9 V, VVOSNS = 0.9 V, VEN = VVIN, COUT = 3 x 10 F and circuit shown in Figure 24. (unless otherwise noted) PARAMETER VREFOUTTOL REFOUT voltage tolerance to VREFIN TEST CONDITIONS MIN TYP MAX -1 mA < IREFOUT < 1 mA, VREFIN = 1.25 V -12 12 -1 mA < IREFOUT < 1 mA, VREFIN = 0.9 V -12 12 -1 mA < IREFOUT < 1 mA, VREFIN = 0.75 V -12 12 -1 mA < IREFOUT < 1 mA, VREFIN = 0.675 V -12 12 -1 mA < IREFOUT < 1 mA, VREFIN = 0.6 V -12 12 UNIT mV IREFOUTSRCL REFOUT source current limit VREFOUT = 0 V 10 40 mA IREFOUTSNCL REFOUT sink current limit VREFOUT = 0 V 10 40 mA Wake up, TA = 25C 2.2 2.3 UVLO AND EN LOGIC THRESHOLD VVINUVVIN UVLO threshold VENIH High-level input voltage Enable VENIL Low-level input voltage Enable VENYST Hysteresis voltage Enable IENLEAK Logic input leakage current EN, TA = 25C Hysteresis 2.375 50 V mV 1.7 0.3 V 1 A 0.5 -1 THERMAL SHUTDOWN TSON 6 Thermal shutdown threshold (1) Shutdown temperature Hysteresis Submit Documentation Feedback 150 25 C Copyright (c) 2008-2016, Texas Instruments Incorporated Product Folder Links: TPS51200 TPS51200 www.ti.com SLUS812C - FEBRUARY 2008 - REVISED NOVEMBER 2016 6.6 Typical Characteristics 3 x 10-mF MLCCs (0805) are used on the output 1.3 40C 0C 25C 85C 1.26 TA 40C 0C 25C 85C 930 Output Voltage (mV) 1.28 Output Voltage (V) 940 TA 1.24 1.22 1.2 920 910 900 890 880 1.18 870 3 2 1 0 1 Output Current (A) 2 3 VVIN = 3.3 V 3 1 0 1 Output Current (A) 2 DDR 2 VVIN = 3.3 V Figure 1. Load Regulation DDR2 Figure 2. Load Regulation 790 720 TA 780 700 Output Voltage (mV) Output Voltage (mV) 760 TA 40C 0C 25C 85C 710 40C 0C 25C 85C 770 750 740 730 720 690 680 670 660 650 710 700 640 3 2 1 0 1 Output Current (A) 2 VVIN = 3.3 V 3 3 2 670 Output Voltage (V) 1.2 590 1.15 1.1 1.05 TA 1 570 40C 0C 25C 85C 0.95 550 0.9 2 1 0 1 Output Current (A) VVIN = 3.3 V DDR3L 1.25 610 3 3 2 1.3 40C 0C 25C 85C 630 0 1 Output Current (mA) Figure 4. Load Regulation TA 650 1 VVIN = 3.3 V DDR3 Figure 3. Load Regulation Output Voltage (mV) 3 2 3 3 LP DDR3 or DDR4 Figure 5. Load Regulation 2 1 0 1 Output Current (A) 2 VVIN = 2.5 V 3 DDR Figure 6. Load Regulation Submit Documentation Feedback Copyright (c) 2008-2016, Texas Instruments Incorporated Product Folder Links: TPS51200 7 TPS51200 SLUS812C - FEBRUARY 2008 - REVISED NOVEMBER 2016 www.ti.com Typical Characteristics (continued) 1 800 0.95 825 Output Voltage (mV) Output Voltage (V) 3 x 10-mF MLCCs (0805) are used on the output 0.9 0.85 0.8 TA 40C 0C 25C 85C 0.75 0.8 3 2 TA 40C 0C 25C 85C 750 725 700 675 650 1 0 1 Output Current (A) 2 VVIN = 2.5 V 3 3 DDR2 2 2 VVIN = 2.5 V Figure 7. Load Regulation 3 DDR3 Figure 8. Load Regulation 720 750 TA 40C 0C 25C 85C 700 690 TA 40C 0C 25C 85C 700 Output Voltage (mV) 710 Output Voltage (mV) 1 0 1 Output Current (A) 680 670 660 650 640 650 600 550 630 620 3 2 1 0 1 Output Current (mA) VVIN = 2.5 V 500 3 2 3 DDR3L 2 VVIN = 2.5 V Figure 9. Load Regulation 1.255 40C 25C 85C TA 40C 25C 85C Output Voltage (mV) 904 1.252 1.251 1.25 1.249 1.248 903 902 901 900 899 898 10 5 0 5 REFOUT Output Current (mA) 10 15 897 15 10 5 0 5 REFOUT Output Current (mA) 10 DDR Figure 11. REFOUT Load Regulation 8 3 LP DDR3 or DDR4 905 TA 1.253 Output Voltage (V) 2 Figure 10. Load Regulation 1.254 1.247 15 1 0 1 Output Current (A) Submit Documentation Feedback 15 DDR2 Figure 12. REFOUT Load Regulation Copyright (c) 2008-2016, Texas Instruments Incorporated Product Folder Links: TPS51200 TPS51200 www.ti.com SLUS812C - FEBRUARY 2008 - REVISED NOVEMBER 2016 Typical Characteristics (continued) 3 x 10-mF MLCCs (0805) are used on the output 680 755 TA 678 Output Voltage (mV) Output Voltage (mV) 753 752 751 750 749 677 676 675 674 673 748 747 15 TA 40C 25C 85C 679 40C 25C 85C 754 672 10 5 0 5 REFOUT Output Current (mA) 10 -15 15 -10 15 -5 0 5 10 REFOUT Output Current (mA) DDR3L DDR3 Figure 14. REFOUT Load Regulation Figure 13. REFOUT Load Regulation 605 40C 25C 85C 603 1.2 DROPOUT Voltage (V) 604 Output Voltage (mV) 1.4 TA 602 601 600 599 1 0.8 0.6 0.2 598 597 15 VOUT (V) 0.6 0.675 0.75 0.9 1.25 0.4 0 10 5 0 5 REFOUT Output Current (mA) 10 15 0 0.5 1 2 2.5 1.5 Output Current (A) 3 3.5 LP DDR3 or DDR4 50 40 60 200 150 50 150 50 0 10 30 1k Gain Phase 10 k 100 k Frequency (Hz) 1M Phase () 0 10 100 30 Phase () 50 20 20 40 100 30 Gain (dB) Figure 16. DROPOUT Voltage vs. Output Current 200 0 10 50 0 100 10 150 20 200 10 M 50 20 Gain (dB) Figure 15. REFOUT Load Regulation 60 100 Gain Phase 30 1k DDR2 Figure 17. Bode Plot 10 k 150 100 k Frequency (Hz) 1M 200 10 M DDR3 Figure 18. Bode Plot Submit Documentation Feedback Copyright (c) 2008-2016, Texas Instruments Incorporated Product Folder Links: TPS51200 9 TPS51200 SLUS812C - FEBRUARY 2008 - REVISED NOVEMBER 2016 www.ti.com 7 Detailed Description 7.1 Overview The TPS51200 device is a sink and source double data rate (DDR) termination regulator specifically designed for low input voltage, low-cost, low-noise systems where space is a key consideration. The device maintains a fast transient response and only requires a minimum output capacitance of 20 F. The device supports a remote sensing function and all power requirements for DDR, DDR2, DDR3, DDR3L, Low Power DDR3, and DDR4 VTT bus termination. 7.2 Functional Block Diagram REFIN + 1 2.3 V VIN 10 VOSNS 2 VLDOIN 6 REFOUT 3 VO 4 PGND 9 PGOOD UVLO + Gm DchgREF 5 + 7 GND 8 ENVTT DchgVTT Gm REFINOK + + + EN Start-up Delay + Copyright (c) 2016, Texas Instruments Incorporated 7.3 Feature Description 7.3.1 Sink and Source Regulator (VO Pin) The TPS51200 is a sink and source tracking termination regulator specifically designed for low input voltage, low-cost, and low external component count systems where space is a key application parameter. The device integrates a high-performance, low-dropout (LDO) linear regulator that is capable of both sourcing and sinking current. The LDO regulator employs a fast feedback loop so that small ceramic capacitors can be used to support the fast load transient response. To achieve tight regulation with minimum effect of trace resistance, connect a remote sensing terminal, VOSNS, to the positive terminal of each output capacitor as a separate trace from the high current path from VO. 7.3.2 Reference Input (REFIN Pin) The output voltage, VO, is regulated to REFOUT. When REFIN is configured for standard DDR termination applications, REFIN can be set by an external equivalent ratio voltage divider connected to the memory supply bus (VDDQ). The TPS51200 device supports REFIN voltages from 0.5 V to 1.8 V, making it versatile and ideal for many types of low-power LDO applications. 10 Submit Documentation Feedback Copyright (c) 2008-2016, Texas Instruments Incorporated Product Folder Links: TPS51200 TPS51200 www.ti.com SLUS812C - FEBRUARY 2008 - REVISED NOVEMBER 2016 Feature Description (continued) 7.3.3 Reference Output (REFOUT Pin) When it is configured for DDR termination applications, REFOUT generates the DDR VTT reference voltage for the memory application. It is capable of supporting both a sourcing and sinking load of 10 mA. REFOUT becomes active when REFIN voltage rises to 0.390 V and VIN is above the UVLO threshold. When REFOUT is less than 0.375 V, it is disabled and subsequently discharges to GND through an internal 10-k MOSFET. REFOUT is independent of the EN pin state. 7.3.4 Soft-Start Sequencing A current clamp implements the soft-start function of the VO pin. The current clamp allows the output capacitors to be charged with low and constant current, providing a linear ramp-up of the output voltage. When VO is outside of the powergood window, the current clamp level is one-half of the full overcurrent limit (OCL) level. When VO rises or falls within the PGOOD window, the current clamp level switches to the full OCL level. The soft-start function is completely symmetrical and the overcurrent limit works for both directions. The soft-start function works not only from GND to the REFOUT voltage, but also from VLDOIN to the REFOUT voltage. 7.3.5 Enable Control (EN Pin) When EN is driven high, the VO regulator begins normal operation. When the device drives EN low, VO discharges to GND through an internal 18- MOSFET. REFOUT remains on when the device drives EN low. Ensure that the EN pin voltage remains lower than or equal to VVIN at all times. 7.3.6 Powergood Function (PGOOD Pin) The TPS51200 device provides an open-drain PGOOD output that goes high when the VO output is within 20% of REFOUT. PGOOD de-asserts within 10 s after the output exceeds the size of the powergood window. During initial VO start-up, PGOOD asserts high 2 ms (typ) after the VO enters power good window. Because PGOOD is an open-drain output, a pull-up resistor with a value between 1 k and 100 k, placed between PGOOD and a stable active supply voltage rail is required. 7.3.7 Current Protection (VO Pin) The LDO has a constant overcurrent limit (OCL). The OCL level reduces by one-half when the output voltage is not within the powergood window. This reduction is a non-latch protection. 7.3.8 UVLO Protection (VIN Pin) For VIN undervoltage lockout (UVLO) protection, the TPS51200 monitors VIN voltage. When the VIN voltage is lower than the UVLO threshold voltage, both the VO and REFOUT regulators are powered off. This shutdown is a non-latch protection. 7.3.9 Thermal Shutdown The TPS51200 monitors junction temperature. If the device junction temperature exceeds the threshold value, (typically 150C), the VO and REFOUT regulators both shut off, discharged by the internal discharge MOSFETs. This shutdown is a non-latch protection. 7.3.10 Tracking Start-up and Shutdown The TPS51200 also supports tracking start-up and shutdown when the EN pin is tied directly to the system bus and not used to turn on or turn off the device. During tracking start-up, VO follows REFOUT once REFIN voltage is greater than 0.39 V. REFIN follows the rise of VDDQ rail through a voltage divider. The typical soft-start time (tSS) for the VDDQ rail is approximately 3 ms, however it may vary depending on the system configuration. The soft-start time of the VO output no longer depends on the OCL setting, but it is a function of the soft-start time of the VDDQ rail. PGOOD is asserted 2 ms after VVO is within 20% of REFOUT. During tracking shutdown, the VO pin voltage falls following REFOUT until REFOUT reaches 0.37 V. When REFOUT falls below 0.37 V, the internal discharge MOSFETs turn on and quickly discharge both REFOUT and VO to GND. PGOOD is deasserted when VO is beyond the 20% range of REFOUT. Figure 20 shows the typical timing diagram for an application that uses tracking start-up and shutdown. Submit Documentation Feedback Copyright (c) 2008-2016, Texas Instruments Incorporated Product Folder Links: TPS51200 11 TPS51200 SLUS812C - FEBRUARY 2008 - REVISED NOVEMBER 2016 www.ti.com Feature Description (continued) 3.3VIN VVDDQ = 1.5 V VLDOIN REFIN REFOUT (VTTREF) EN (S3_SLP) VVO = 0.75 V tSS . VO tSS = PGOOD COUT x VO IOOCL 2 ms Figure 19. Typical Timing Diagram for S3 and Pseudo-S5 Support 3.3VIN EN VLDOIN REFIN REFOUT (VTTREF) VO tSS determined by the SS time of VLDOIN VVO = 0.75 V PGOOD 2 ms Figure 20. Typical Timing Diagram of Tracking Start-up and Shutdown 12 Submit Documentation Feedback Copyright (c) 2008-2016, Texas Instruments Incorporated Product Folder Links: TPS51200 TPS51200 www.ti.com SLUS812C - FEBRUARY 2008 - REVISED NOVEMBER 2016 Feature Description (continued) 7.3.11 Output Tolerance Consideration for VTT DIMM Applications The TPS51200 is specifically designed to power up the memory termination rail (as shown in Figure 21). The DDR memory termination structure determines the main characteristics of the VTT rail, which is to be able to sink and source current while maintaining acceptable VTT tolerance. See Figure 22 for typical characteristics for a single memory cell. Vtt SPD DQ CA Vdd Vtt Vdd CA Vdd DQ DDR3 240 Pin Socket VO TPS51200 10 mF 10 mF 10 mF UDG-08022 Figure 21. Typical Application Diagram for DDR3 VTT DIMM using TPS51200 VDDQ VTT Q1 25 W RS 20 W Ouput Buffer (Driver) Receiver Q2 VOUT VIN VSS UDG-08023 Figure 22. DDR Physical Signal System Bi-Directional SSTL Signaling In Figure 22, when Q1 is on and Q2 is off: * Current flows from VDDQ via the termination resistor to VTT * VTT sinks current In Figure 22, when Q2 is on and Q1 is off: * Current flows from VTT via the termination resistor to GND * VTT sources current Submit Documentation Feedback Copyright (c) 2008-2016, Texas Instruments Incorporated Product Folder Links: TPS51200 13 TPS51200 SLUS812C - FEBRUARY 2008 - REVISED NOVEMBER 2016 www.ti.com Feature Description (continued) Because VTT accuracy has a direct impact on the memory signal integrity, it is imperative to understand the tolerance requirement on VTT. Equation 1 applies to both DC and AC conditions and is based on JEDEC VTT specifications for DDR and DDR2 (JEDEC standard: DDR JESD8-9B May 2002; DDR2 JESD8-15A Sept 2003). VVTTREF - 40 mV < VVTT < VVTTREF + 40 mV (1) The specification itself indicates that VTT must keep track of VTTREF for proper signal conditioning. The TPS51200 ensures the regulator output voltage to be as shown in Equation 2, which applies to both DC and AC conditions. VVTTREF -25 mV < VVTT < VVTTREF + 25 mV where * -2 A < IVTT < 2 A (2) The regulator output voltage is measured at the regulator side, not the load side. The tolerance is applicable to DDR, DDR2, DDR3, DDR3L, Low Power DDR3, and DDR4 applications (see Table 1 for detailed information). To meet the stability requirement, a minimum output capacitance of 20 F is needed. Considering the actual tolerance on the MLCC capacitors, three 10-F ceramic capacitors sufficiently meet the VTT accuracy requirement. Table 1. DDR, DDR2, DDR3 and LP DDR3 Termination Technology DDR DDR2 FSB Data Rates 200, 266, 333, and 400 MHz 400, 533, 677, and 800 MHz 800, 1066, 1330, and 1600 MHz Termination Motherboard termination to VTT for all signals On-die termination for data group. VTT termination for address, command and control signals On-die termination for data group. VTT termination for address, command and control signals Not as demanding Not as demanding Termination Current Demand Voltage Level Only 34 signals (address, command, control) tied to Maximum source/sink transient currents of up to 2.6 VTT A to 2.9 A ODT handles data signals 2.5-V Core and I/O 1.25-V VTT DR3 LOW POWER DDR3 Only 34 signals (address, command, control) tied to VTT ODT handles data signals Less than 1-A of burst current Less than 1-A of burst current 1.8-V Core and I/O 0.9-V VTT 1.5-V Core and I/O 0.75-V VTT 1.2-V Core and I/O 0.6-V VTT The TPS51200 uses transconductance (gM) to drive the LDO. The transconductance and output current of the device determine the voltage droop between the reference input and the output regulator. The typical transconductance level is 250 S at 2 A and changes with respect to the load in order to conserve the quiescent current (that is, the transconductance is very low at no load condition). The (gM) LDO regulator is a single pole system. Only the output capacitance determines the unity gain bandwidth for the voltage loop, as a result of the bandwidth nature of the transconductance (see Equation 3). gM UGBW = 2 p COUT where * * * UGBW is the unity gain bandwidth gM is transconductance COUT is the output capacitance (3) Consider these two limitations to this type of regulator that come from the output bulk capacitor requirement. In order to maintain stability, the zero location contributed by the ESR of the output capacitors must be greater than the -3-dB point of the current loop. This constraint means that higher ESR capacitors should not be used in the design. In addition, the impedance characteristics of the ceramic capacitor should be well understood in order to prevent the gain peaking effect around the transconductance (gM) -3-dB point because of the large ESL, the output capacitor and parasitic inductance of the VO pin voltage trace. 14 Submit Documentation Feedback Copyright (c) 2008-2016, Texas Instruments Incorporated Product Folder Links: TPS51200 TPS51200 www.ti.com SLUS812C - FEBRUARY 2008 - REVISED NOVEMBER 2016 7.3.12 REFOUT (VREF) Consideration for DDR2 Applications During TPS51200 tracking start-up, the REFIN voltage follows the rise of the VDDQ rail through a voltage divider, and REFOUT (VREF) follows REFIN once the REFIN voltage is greater than 0.39 V. When the REFIN voltage is lower than 0.39 V, VREF is 0 V. The JEDEC DDR2 SDRAM Standard (JESD79-2E) states that VREF must track VDDQ/2 within 0.3 V accuracy during the start-up period. To allow the TPS51200 device to meet the JEDEC DDR2 specification, a resistor divider can be used to provide the VREF signal to the DIMM. The resistor divider ratio is 0.5 to ensure that the VREF voltage equals VDDQ/2. VVDDQ DDR RREF VREF RREF Figure 23. Resistor Divider Circuit When selecting the resistor value, consider the impact of the leakage current from the DIMM VREF pin on the reference voltage. Use Equation 4 to calculate resistor values. R REF Q 2 x VREF IREF where * * * RREF is the resistor value VREF is the VREF DC variation requirement IREF is the maximum total VREF leakage current from DIMMs (4) Consider the MT47H64M16 DDR2 SDRAM component from Micron as an example. The MT47H64M16 datasheet shows the maximum VREF leakage current of each DIMM is 2 A, and VREF(DC) variation must be within 1% of VDDQ. In this DDR2 application, the VDDQ voltage is 1.8 V. Assuming one TPS51200 device needs to power 4 DIMMs, the maximum total VREF leakage current is 8 A. Based on the calculations, the resistor value should be lower than 4.5 k. To ensure sufficient margin, 100 is the suggested resistor value. With two 100- resistors, the maximum VREF variation is 0.4 mV, and the power loss on each resistor is 8.1 mW. Submit Documentation Feedback Copyright (c) 2008-2016, Texas Instruments Incorporated Product Folder Links: TPS51200 15 TPS51200 SLUS812C - FEBRUARY 2008 - REVISED NOVEMBER 2016 www.ti.com 7.4 Device Functional Modes 7.4.1 Low Input Voltage Applications TPS51200 can be used in an application system that offers either a 2.5-V rail or a 3.3-V rail. If only a 5-V rail is available, consider using the TPS51100 device as an alternative. The TPS51200 device has a minimum input voltage requirement of 2.375 V. If a 2.5-V rail is used, ensure that the absolute minimum voltage (both DC and transient) at the device pin is be 2.375 V or greater. The voltage tolerance for a 2.5-V rail input is between -5% and 5% accuracy, or better. 7.4.2 S3 and Pseudo-S5 Support The TPS51200 provides S3 support by an EN function. The EN pin could be connected to an SLP_S3 signal in the end application. Both REFOUT and VO are on when EN = high (S0 state). REFOUT is maintained while VO is turned off and discharged via an internal discharge MOSFET when EN = low (S3 state). When EN = low and the REFIN voltage is less than 0.390 V, TPS51200 enters pseudo-S5 state. Both VO and REFOUT outputs are turned off and discharged to GND through internal MOSFETs when pseudo-S5 support is engaged (S4 or S5 state). Figure 19 shows a typical start-up and shutdown timing diagram for an application that uses S3 and pseudo-S5 support. 16 Submit Documentation Feedback Copyright (c) 2008-2016, Texas Instruments Incorporated Product Folder Links: TPS51200 TPS51200 www.ti.com SLUS812C - FEBRUARY 2008 - REVISED NOVEMBER 2016 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information 8.2 Typical Application This design example describes a 3.3-VIN, DDR3 configuration. R1 10 kW TPS51200 1 VVDDQ = 1.5 V R2 10 kW VVLDOIN = VVDDQ = 1.5 V C7 10 mF C2 10 mF 3.3 VIN R3 100 kW 2 VLDOIN PGOOD 9 3 VO GND 8 4 PGND EN 7 5 VOSNS REFOUT 6 C6 4.7 mF PGOOD C8 10 mF VVTT = 0.75 V C1 10 mF VIN 10 REFIN C4 1000 pF C3 10 mF SLP_S3 VTTREF C5 0.1 mF UDG-08029 Figure 24. 3.3-VIN, DDR3 Configuration Table 2. 3.3-VIN, DDR3 Application List of Materials REFERENCE DESIGNATOR R1, R2 R3 DESCRIPTION Resistor C1, C2, C3 PART NUMBER MANUFACTURER GRM21BR70J106KE76L Murata 10 k 100 k 10 F, 6.3 V C4 C5 SPECIFICATION 1000 pF Capacitor 0.1 F C6 4.7 F, 6.3 V GRM21BR60J475KA11L Murata C7, C8 10 F, 6.3 V GRM21BR70J106KE76L Murata Submit Documentation Feedback Copyright (c) 2008-2016, Texas Instruments Incorporated Product Folder Links: TPS51200 17 TPS51200 SLUS812C - FEBRUARY 2008 - REVISED NOVEMBER 2016 www.ti.com 8.2.1 Design Requirements * VIN = 3.3 V * VDDDQ = 1.5 V * VVLDOIN = VVDDQ = 1.5 V * VVTT = 0.75 V 8.2.2 Detailed Design Procedure 8.2.2.1 Input Voltage Capacitor Add a ceramic capacitor, with a value between 1.0-F and 4.7-F, placed close to the VIN pin, to stabilize the bias supply (2.5-V rail or 3.3-V rail) from any parasitic impedance from the supply. 8.2.2.2 VLDO Input Capacitor Depending on the trace impedance between the VLDOIN bulk power supply to the device, a transient increase of source current is supplied mostly by the charge from the VLDOIN input capacitor. Use a 10-F (or greater) ceramic capacitor to supply this transient charge. Provide more input capacitance as more output capacitance is used at the VO pin. In general, use one-half of the COUT value for input. 8.2.2.3 Output Capacitor For stable operation, the total capacitance of the VO output pin must be greater than 20 F. Attach three, 10-F ceramic capacitors in parallel to minimize the effect of equivalent series resistance (ESR) and equivalent series inductance (ESL). If the ESR is greater than 2 m, insert an RC filter between the output and the VOSNS input to achieve loop stability. The RC filter time constant should be almost the same as or slightly lower than the time constant of the output capacitor and its ESR. 18 Submit Documentation Feedback Copyright (c) 2008-2016, Texas Instruments Incorporated Product Folder Links: TPS51200 TPS51200 www.ti.com SLUS812C - FEBRUARY 2008 - REVISED NOVEMBER 2016 8.2.3 Application Curves Figure 25 shows the bode plot simulation for this DDR3 design example of the TPS51200 device. The unity-gain bandwidth is approximately 1 MHz and the phase margin is 52. The 0-dB level is crossed, the gain peaks because of the ESL effect. However, the peaking maintains a level well below 0 dB. 0 40 90 0 180 Gain (dB) 80 Phase () Figure 26 shows the load regulation and Figure 27 shows the transient response for a typical DDR3 configuration. When the regulator is subjected to 1.5-A load step and release, the output voltage measurement shows no difference between the dc and ac conditions. 270 40 Gain Phase 80 1 10 100 1000 10 k 100 k 1M 10 M 360 100 M Frequency (Hz) VIN = 3.3 V IIO = 2 A VVLDOIN = 1.5 V 3 x 10-F capacitors VVO = 0.75 V ESR = 2.5 m ESL = 800 pH Figure 25. DDR3 Design Example Bode Plot 790 TA 780 40C 0C 25C 85C Output Voltage (mV) 770 760 750 740 730 720 710 700 3 2 1 0 1 Output Current (A) VVIN = 3.3 V 2 3 DDR3 Figure 26. Load Regulation Figure 27. Transient Waveform Submit Documentation Feedback Copyright (c) 2008-2016, Texas Instruments Incorporated Product Folder Links: TPS51200 19 TPS51200 SLUS812C - FEBRUARY 2008 - REVISED NOVEMBER 2016 www.ti.com 8.3 System Examples 8.3.1 3.3-VIN, DDR2 Configuration This section describes a 3.3-VIN, DDR2 configuration application. R1 10 k: TPS51200 1 VVDDQ = 1.8 V R2 10 k: C7 10 PF VVTT = 0.9 V C2 10 PF VIN 10 3.3 VIN R3 100 k: 2 VVLDOIN = VVDDQ = 1.8 V C1 10 PF REFIN C4 1000 pF C3 10 PF VLDOIN PGOOD C6 4.7 PF PGOOD 9 C8 10 PF VVDDQ = 1.8 V 3 VO GND 8 4 PGND EN 7 5 VOSNS REFOUT 6 SLP_S3 R4 100 Y VTTREF C5 0.1 PF R5 100 Y Figure 28. 3.3-VIN, DDR2 Configuration Table 3. 3.3-VIN, DDR2 Configuration List of Materials REFERENCE DESIGNATOR DESCRIPTION R1, R2 SPECIFICATION MANUFACTURER GRM21BR70J106KE76L Murata 10 k R3 Resistor 100 k R4, R5 100 C1, C2, C3 10 F, 6.3 V C4 C5 PART NUMBER 1000 pF Capacitor 0.1 F C6 4.7 F, 6.3 V GRM21BR60J475KA11L Murata C7, C8 10 F, 6.3 V GRM21BR70J106KE76L Murata 20 Submit Documentation Feedback Copyright (c) 2008-2016, Texas Instruments Incorporated Product Folder Links: TPS51200 TPS51200 www.ti.com SLUS812C - FEBRUARY 2008 - REVISED NOVEMBER 2016 8.3.2 2.5-VIN, DDR3 Configuration This design example describes a 2.5-VIN, DDR3 configuration application. R1 10 kW TPS51200 1 VVDDQ = 1.5 V R2 10 kW VVLDOIN = VVDDQ = 1.5 V C7 10 mF C2 10 mF 2.5 VIN R3 100 kW C6 4.7 mF 2 VLDOIN PGOOD 9 3 VO GND 8 4 PGND EN 7 SLP_S3 5 VOSNS REFOUT 6 VTTREF PGOOD C8 10 mF VVTT = 0.75 V C1 10 mF VIN 10 REFIN C4 1000 pF C3 10 mF C5 0.1 mF UDG-08030 Figure 29. 2.5-VIN, DDR3 Configuration Table 4. 2.5-VIN, DDR3 Configuration List of Materials REFERENCE DESIGNATOR R1, R2 R3 DESCRIPTION Resistor C1, C2, C3 PART NUMBER MANUFACTURER GRM21BR70J106KE76L Murata 10 k 100 k 10 F, 6.3 V C4 C5 SPECIFICATION 1000 pF Capacitor 0.1 F C6 4.7 F, 6.3 V GRM21BR60J475KA11L Murata C7, C8 10 F, 6.3 V GRM21BR70J106KE76L Murata Submit Documentation Feedback Copyright (c) 2008-2016, Texas Instruments Incorporated Product Folder Links: TPS51200 21 TPS51200 SLUS812C - FEBRUARY 2008 - REVISED NOVEMBER 2016 www.ti.com 8.3.3 3.3-VIN, LP DDR3 or DDR4 Configuration This example describes a 3.3-VIN, LP DDR3 or DDR4 configuration application. R1 10 kW TPS51200 1 VVDDQ = 1.2 V R2 10 kW VVLDOIN = VVDDQ = 1.2 V C7 10 mF C2 10 mF 3.3 VIN R3 100 kW C6 4.7 mF 2 VLDOIN PGOOD 9 3 VO GND 8 4 PGND EN 7 SLP_S3 5 VOSNS REFOUT 6 VTTREF PGOOD C8 10 mF VVTT = 0.6 V C1 10 mF VIN 10 REFIN C4 1000 pF C3 10 mF C5 0.1 mF UDG-08031 Figure 30. 3.3-VIN, LP DDR3 or DDR4 Configuration Table 5. 3.3-VIN, LP DDR3 or DDR4 Configuration REFERENCE DESIGNATOR R1, R2 DESCRIPTION Resistor R3 C1, C2, C3 PART NUMBER MANUFACTURER GRM21BR70J106KE76L Murata 10 k 100 k 10 F, 6.3 V C4 C5 SPECIFICATION 1000 pF Capacitor 0.1 F C6 4.7 F, 6.3 V GRM21BR60J475KA11L Murata C7, C8 10 F, 6.3 V GRM21BR70J106KE76L Murata 22 Submit Documentation Feedback Copyright (c) 2008-2016, Texas Instruments Incorporated Product Folder Links: TPS51200 TPS51200 www.ti.com SLUS812C - FEBRUARY 2008 - REVISED NOVEMBER 2016 8.3.4 3.3-VIN, DDR3 Tracking Configuration This design example describes a 3.3-VIN, DDR3 tracking configuration application. R1 10 kW TPS51200 1 VVDDQ = 1.5 V R2 10 kW VVLDOIN = VVDDQ = 1.5 V C7 10 mF C2 10 mF VIN 10 3.3 VIN R3 100 kW 2 VLDOIN PGOOD 9 3 VO GND 8 4 PGND EN 7 5 VOSNS REFOUT 6 C6 4.7 mF PGOOD C8 10 mF VVTT = 0.75 V C1 10 mF REFIN C4 1000 pF C3 10 mF VTTREF C5 0.1 mF UDG-08032 Figure 31. 3.3-VIN, DDR3 Tracking Configuration Table 6. 3.3-VIN, DDR3 Tracking Configuration List of Materials REFERENCE DESIGNATOR R1, R2 R3 DESCRIPTION Resistor SPECIFICATION GRM21BR70J106KE76L Murata 100 k 10 F, 6.3 V C4 1000 pF Capacitor MANUFACTURER 10 k C1, C2, C3 C5 PART NUMBER 0.1 F C6 4.7 F, 6.3 V GRM21BR60J475KA11L Murata C7, C8 10 F, 6.3 V GRM21BR70J106KE76L Murata Submit Documentation Feedback Copyright (c) 2008-2016, Texas Instruments Incorporated Product Folder Links: TPS51200 23 TPS51200 SLUS812C - FEBRUARY 2008 - REVISED NOVEMBER 2016 www.ti.com 8.3.5 3.3-VIN, LDO Configuration This example describes a 3.3-VIN, LDO configuration application. R1 3.86 k: TPS51200 2.5 V 1 R2 10 k: VVLDOIN = VVLDOREF = 2.5 V C7 10 PF C2 10 PF VIN 10 3.3 VIN R3 100 k: 2 VLDOIN PGOOD 9 3 VO GND 8 4 PGND EN 7 5 VOSNS REFOUT 6 C6 4.7 PF PGOOD C8 10 PF VVLDO = 1.8 V C1 10 PF REFIN C4 1000 pF C3 10 PF ENABLE REFOUT C5 0.1 PF UDG-08033 Figure 32. 3.3-VIN, LDO Configuration Table 7. 3.3-VIN, LDO Configuration List of Materials REFERENCE DESIGNATOR DESCRIPTION R1 SPECIFICATION MANUFACTURER GRM21BR70J106KE76L Murata 3.86 k R2 Resistor 10 k R3 100 k C1, C2, C3 10 F, 6.3 V C4 1000 pF C5 PART NUMBER Capacitor 0.1 F C6 4.7 F, 6.3 V GRM21BR60J475KA11L Murata C7, C8 10 F, 6.3 V GRM21BR70J106KE76L Murata 24 Submit Documentation Feedback Copyright (c) 2008-2016, Texas Instruments Incorporated Product Folder Links: TPS51200 TPS51200 www.ti.com SLUS812C - FEBRUARY 2008 - REVISED NOVEMBER 2016 8.3.6 3.3-VIN, DDR3 Configuration with LFP This design example describes a 3.3-VIN, DDR3 configuration with LFP application. R1 10 kW TPS51200 1 VVDDQ = 1.5 V R2 10 kW VIN 10 REFIN C4 1000 pF R3 100 kW VVLDOIN = VVDDQ = 1.5 V C7 10 mF 3.3 VIN C6 4.7 mF 2 VLDOIN PGOOD 9 3 VO GND 8 4 PGND EN 7 SLP_S3 5 VOSNS REFOUT 6 VTTREF PGOOD C8 10 mF VVTT = 0.75 V R4(1) C1 10 mF C2 10 mF C3 10 mF C5 0.1 mF C9(1) UDG-08034 Figure 33. 3.3-VIN, DDR3 Configuration with LFP Table 8. 3.3-VIN, DDR3 Configuration with LFP List of Materials REFERENCE DESIGNATOR DESCRIPTION R1, R2 R3 SPECIFICATION PART NUMBER MANUFACTURER GRM21BR70J106KE76L Murata 4.7 F, 6.3 V GRM21BR60J475KA11L Murata 10 F, 6.3 V GRM21BR70J106KE76L Murata 10 k Resistor 100 k R4 (1) C1, C2, C3 10 F, 6.3 V C4 1000 pF C5 Capacitor C6 C7, C8 0.1 F C9 (1) (1) Choose values for R4 and C9 to reduce the parasitic effect of the trace (between VO and the output MLCCs) and the output capacitors (ESR and ESL). Submit Documentation Feedback Copyright (c) 2008-2016, Texas Instruments Incorporated Product Folder Links: TPS51200 25 TPS51200 SLUS812C - FEBRUARY 2008 - REVISED NOVEMBER 2016 www.ti.com 9 Power Supply Recommendations This device is designed to operate from an input bias voltage from 2.375 V to 3.5 V, with LDO input from 1.1 V to 3.5 V. Refer to Figure 19 and Figure 20 for recommended power-up sequence. Maintain a EN voltage equal or lower than VVIN at all times. VLDOIN can ramp up earlier than VIN if the sequence in Figure 19 and Figure 20 cannot be used. The input supplies should be well regulated. VLDOIN decoupling capacitance of 2 x 10 F is recommended, and VIN decoupling capacitance of 1 x 4.7 F is recommended. 10 Layout 10.1 Layout Guidelines Consider the following points before starting the TPS51200 device layout design. * Place the input capacitors as close to VDLOIN pin as possible with short and wide connection. * Place the output capacitor as close to VO pin as possible with short and wide connection. Place a ceramic capacitor with a value of at least 10-F as close to VO pin if the rest of output capacitors need to be placed on the load side. * Connect the VOSNS pin to the positive node of output capacitors as a separate trace. In DDR VTT application, connect the VO sense trace to DIMM side to ensure the VTT voltage at DIMM side is well regulated. * Consider adding low-pass filter at VOSNS if the VO sense trace is very long. * Connect the GND pin and PGND pin to the thermal pad directly. * TPS51200 uses its thermal pad to dissipate heat. In order to effectively remove heat fromTPS51200 package, place numerous ground vias on the thermal pad. Use large ground copper plane, especially the copper plane on surface layer, to pour over those vias on thermal pad. * Consult the TPS51200EVM User's Guide (SLUU323) for detailed layout recommendations. 26 Submit Documentation Feedback Copyright (c) 2008-2016, Texas Instruments Incorporated Product Folder Links: TPS51200 TPS51200 www.ti.com SLUS812C - FEBRUARY 2008 - REVISED NOVEMBER 2016 10.2 Layout Example VDDQ Trace VIN Trace To GND Plane VLDOIN GND PGOOD Trace EN Trace VTT Sense Trace, terminate near the load VTT Figure 34. Layout Recommendation 10.3 Thermal Design Considerations Because the TPS51200 is a linear regulator, the VO current flows in both source and sink directions, thereby dissipating power from the device. When the device is sourcing current, the voltage difference shown in Equation 5 calculates the power dissipation. PD _ SRC = (VVLDOIN - VVO ) IO _ SRC (5) In this case, if the VLDOIN pin is connected to an alternative power supply lower than the VDDQ voltage, overall power loss can be reduced. During the sink phase, the device applies the VO voltage across the internal LDO regulator. Equation 6 calculates he power dissipation, PD_SNK can be calculated by . PD _ SNK = VVO ISNK (6) Because the device does not sink and source current at the same time and the I/O current may vary rapidly with time, the actual power dissipation should be the time average of the above dissipations over the thermal relaxation duration of the system. The current used for the internal current control circuitry from the VIN supply and the VLDOIN supply are other sources of power consumption. This power can be estimated as 5 mW or less during normal operating conditions and must be effectively dissipated from the package. Submit Documentation Feedback Copyright (c) 2008-2016, Texas Instruments Incorporated Product Folder Links: TPS51200 27 TPS51200 SLUS812C - FEBRUARY 2008 - REVISED NOVEMBER 2016 www.ti.com Thermal Design Considerations (continued) Maximum power dissipation allowed by the package is calculated by Equation 7. TJ(max) - TA(max) PPKG = qJA where * * * TJ(max) is 125C TA(max) is the maximum ambient temperature in the system JA is the thermal resistance from junction to ambient (7) NOTE Because Equation 7 demonstrates the effects of heat spreading in the ground plane, use it as a guideline only. Do not use Equation 7 to estimate actual thermal performance in real application environments. In an application where the device is mounted on PCB, TI strongly recommends using JT and JB, as explained in the section pertaining to estimating junction temperature in the Semiconductor and IC Package Thermal Metrics application report, SPRA953. Using the thermal metrics JT and JB, as shown in the Thermal Information table, estimate the junction temperature with corresponding formulas shown in Equation 8. The older JC top parameter specification is listed as well for the convenience of backward compatibility. TJ = TT + Y JT PD (8) TJ = TB + Y JB PD where * * * PD is the power dissipation shown in Equation 5 and Equation 6 TT is the temperature at the center-top of the IC package TB is the PCB temperature measured 1-mm away from the thermal pad package on the PCB surface (see Figure 36). (9) NOTE Both TT and TB can be measured on actual application boards using a thermo-gun (an infrared thermometer). For more information about measuring TT and TB, see the application report Using New Thermal Metrics (SBVA025). . TT on top of package Land Pad 3 mm x 1.9 mm TB on PCB surface Exposed Thermal Die Pad, 2.48 mm x 1.74 mm 1 mm UDG-08018 Figure 35. Recommended Land Pad Pattern 28 Figure 36. Package Thermal Measurement Submit Documentation Feedback Copyright (c) 2008-2016, Texas Instruments Incorporated Product Folder Links: TPS51200 TPS51200 www.ti.com SLUS812C - FEBRUARY 2008 - REVISED NOVEMBER 2016 11 Device and Documentation Support 11.1 Device Support 11.1.1 Third-Party Products Disclaimer TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE. 11.1.2 Development Support 11.1.2.1 Evaluation Modules An evaluation module (EVM) is available to assist in the initial circuit performance evaluation using the TPS51200 device. The TPS51200EVM evaluation module and related user's guide (SLUU323) can be requested at the Texas Instruments website through the product folders or purchased directly from the TI eStore. 11.1.2.2 Spice Models Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of analog circuits and systems. A SPICE model for the TPS51200 device is available here. 11.2 Documentation Support 11.2.1 Related Documentation * Using New Thermal Metrics, SBVA025 * Semiconductor and IC Package Thermal Metrics, SPRA953 * Using the TPS51200 EVM Sink/Source DDR Termination Regulator, SLUU323 * For more information on the TPS51100 device, see the product folder on ti.com. 11.3 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2ETM Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.4 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 11.5 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 11.6 Glossary SLYZ022 -- TI Glossary. This glossary lists and explains terms, acronyms, and definitions. Submit Documentation Feedback Copyright (c) 2008-2016, Texas Instruments Incorporated Product Folder Links: TPS51200 29 TPS51200 SLUS812C - FEBRUARY 2008 - REVISED NOVEMBER 2016 www.ti.com 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 30 Submit Documentation Feedback Copyright (c) 2008-2016, Texas Instruments Incorporated Product Folder Links: TPS51200 PACKAGE OPTION ADDENDUM www.ti.com 3-Nov-2016 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) TPS51200DRCR ACTIVE VSON DRC 10 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 1200 TPS51200DRCRG4 ACTIVE VSON DRC 10 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 1200 TPS51200DRCT ACTIVE VSON DRC 10 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 1200 TPS51200DRCTG4 ACTIVE VSON DRC 10 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 1200 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 3-Nov-2016 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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OTHER QUALIFIED VERSIONS OF TPS51200 : * Automotive: TPS51200-Q1 * Enhanced Product: TPS51200-EP NOTE: Qualified Version Definitions: * Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects * Enhanced Product - Supports Defense, Aerospace and Medical Applications Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 16-Mar-2017 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS51200DRCR VSON DRC 10 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS51200DRCT VSON DRC 10 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 16-Mar-2017 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS51200DRCR VSON DRC 10 3000 367.0 367.0 35.0 TPS51200DRCT VSON DRC 10 250 210.0 185.0 35.0 Pack Materials-Page 2 GENERIC PACKAGE VIEW DRC 10 VSON - 1 mm max height PLASTIC SMALL OUTLINE - NO LEAD Images above are just a representation of the package family, actual package may vary. Refer to the product data sheet for package details. 4204102-3/M PACKAGE OUTLINE DRC0010J VSON - 1 mm max height SCALE 4.000 PLASTIC SMALL OUTLINE - NO LEAD 3.1 2.9 A B PIN 1 INDEX AREA 3.1 2.9 1.0 0.8 C SEATING PLANE 0.05 0.00 0.08 C 1.65 0.1 2X (0.5) EXPOSED THERMAL PAD (0.2) TYP 4X (0.25) 5 2X 2 6 11 SYMM 2.4 0.1 10 1 8X 0.5 PIN 1 ID (OPTIONAL) 10X SYMM 0.5 10X 0.3 0.30 0.18 0.1 0.05 C A B C 4218878/B 07/2018 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance. www.ti.com EXAMPLE BOARD LAYOUT DRC0010J VSON - 1 mm max height PLASTIC SMALL OUTLINE - NO LEAD (1.65) (0.5) 10X (0.6) 1 10 10X (0.24) 11 (2.4) SYMM (3.4) (0.95) 8X (0.5) 6 5 (R0.05) TYP ( 0.2) VIA TYP (0.25) (0.575) SYMM (2.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:20X 0.07 MAX ALL AROUND 0.07 MIN ALL AROUND EXPOSED METAL EXPOSED METAL SOLDER MASK OPENING METAL METAL UNDER SOLDER MASK NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK OPENING SOLDER MASK DEFINED SOLDER MASK DETAILS 4218878/B 07/2018 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. www.ti.com EXAMPLE STENCIL DESIGN DRC0010J VSON - 1 mm max height PLASTIC SMALL OUTLINE - NO LEAD 2X (1.5) (0.5) SYMM EXPOSED METAL TYP 11 10X (0.6) 1 10 (1.53) 10X (0.24) 2X (1.06) SYMM (0.63) 8X (0.5) 6 5 (R0.05) TYP 4X (0.34) 4X (0.25) (2.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 11: 80% PRINTED SOLDER COVERAGE BY AREA SCALE:25X 4218878/B 07/2018 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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