TPS74801 SBVS074J - JANUARY 2007 - REVISED JANUARY 2012 www.ti.com 1.5A Low-Dropout Linear Regulator with Programmable Soft-Start Check for Samples: TPS74801 FEATURES 1 * * * * * 2 * * * * * VOUT Range: 0.8V to 3.6V Ultralow VIN Range: 0.8V to 5.5V VBIAS Range 2.7V to 5.5V Low Dropout: 60mV typ at 1.5A, VBIAS = 5V Power Good (PG) Output Allows Supply Monitoring or Provides a Sequencing Signal for Other Supplies 2% Accuracy Over Line/Load/Temperature Programmable Soft-Start Provides Linear Voltage Startup VBIAS Permits Low VIN Operation with Good Transient Response Stable with Any Output Capacitor 2.2F Available in a Small 3mm x 3mm x 1mm SON-10 and 5 x 5 QFN-20 Packages APPLICATIONS * * * * * FPGA Applications DSP Core and I/O Voltages Post-Regulation Applications Applications with Special Start-Up Time or Sequencing Requirements Hot-Swap and Inrush Controls DESCRIPTION The TPS74801 low-dropout (LDO) linear regulator provides an easy-to-use robust power management solution for a wide variety of applications. User-programmable soft-start minimizes stress on the input power source by reducing capacitive inrush current on start-up. The soft-start is monotonic and well-suited for powering many different types of processors and ASICs. The enable input and power good output allow easy sequencing with external regulators. This complete flexibility permits the user to configure a solution that meets the sequencing requirements of FPGAs, DSPs, and other applications with special start-up requirements. A precision reference and error amplifier deliver 2% accuracy over load, line, temperature, and process. The device is stable with any type of capacitor greater than or equal to 2.2F, and is fully specified from -40C to +125C. The TPS74801 is offered in a small 3mm x 3mm SON-10 package, yielding a highly compact, total solution size. It is also available in a 5 x 5 QFN-20 for compatibility with the TPS74401. CSS = 0nF CSS = 1nF 0.5V/div VIN IN CIN VBIAS R3 TPS74801 1.2V VEN R1 GND CSS VOUT OUT SS CBIAS CSS = 2.2nF PG BIAS EN VOUT COUT FB 1V/div 0V R2 Time (1ms/div) Figure 2. Turn-On Response Figure 1. Typical Application Circuit (Adjustable) 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2007-2012, Texas Instruments Incorporated TPS74801 SBVS074J - JANUARY 2007 - REVISED JANUARY 2012 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) PRODUCT TPS748xx yyy z (1) (2) (3) VOUT (2) XX is nominal output voltage (for example, 12 = 1.2V, 15 = 1.5V, 01 = Adjustable). (3) YYY is package designator. Z is package quantity. For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. Fixed output voltages from 0.8V to 3.3V are available; minimum order quantities may apply. Contact factory for details and availability. For fixed 0.8V operation, tie FB to OUT. ABSOLUTE MAXIMUM RATINGS (1) At TJ = -40C to +125C, unless otherwise noted. All voltages are with respect to GND. TPS74801 UNIT VIN, VBIAS Input voltage range -0.3 to +6 V VEN Enable voltage range -0.3 to +6 V VPG Power good voltage range -0.3 to +6 V IPG PG sink current 0 to +1.5 mA VSS Soft-start voltage range -0.3 to +6 V VFB Feedback voltage range -0.3 to +6 V VOUT Output voltage range -0.3 to VIN + 0.3 V IOUT Maximum output current Internally limited Output short-circuit duration Indefinite PDISS Continuous total power dissipation TJ Operating junction temperature range -40 to +150 C TSTG Storage junction temperature range -55 to +150 C (1) 2 See Thermal Information Table Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Link(s): TPS74801 TPS74801 SBVS074J - JANUARY 2007 - REVISED JANUARY 2012 www.ti.com THERMAL INFORMATION TPS74801 (2) THERMAL METRIC (1) Junction-to-ambient thermal resistance (3) JA (4) RGW DRC 20 PINS 10 PINS 30.5 41.5 JCtop Junction-to-case (top) thermal resistance 27.6 78 JB Junction-to-board thermal resistance (5) N/A N/A JT Junction-to-top characterization parameter (6) 0.37 0.7 JB Junction-to-board characterization parameter (7) 10.6 11.3 JCbot Junction-to-case (bottom) thermal resistance (8) 4.1 6.6 (1) (2) (3) (4) (5) (6) (7) (8) UNITS C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953A. Thermal data for the RGW and DRC packages are derived by thermal simulations based on JEDEC-standard methodology as specified in the JESD51 series. The following assumptions are used in the simulations: (a) i. RGW: The exposed pad is connected to the PCB ground layer through a 4x4 thermal via array. . ii. DRC: The exposed pad is connected to the PCB ground layer through a 3x2 thermal via array. (b) i. RGW: Each of top and bottom copper layers has a dedicated pattern for 20% copper coverage. . ii. DRC: The top and bottom copper layers are assumed to have a 20% thermal conductivity of copper representing a 20% copper coverage. (c) These data were generated with only a single device at the center of a JEDEC high-K (2s2p) board with 3in x 3in copper area. To understand the effects of the copper area on thermal performance, see the Power Dissipation and Estimating Junction Temperature sections of this data sheet. The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the top of the package. No specific JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. The junction-to-top characterization parameter, JT, estimates the junction temperature of a device in a real system and is extracted from the simulation data to obtain JA using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-board characterization parameter, JB, estimates the junction temperature of a device in a real system and is extracted from the simulation data to obtain JA using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Link(s): TPS74801 3 TPS74801 SBVS074J - JANUARY 2007 - REVISED JANUARY 2012 www.ti.com ELECTRICAL CHARACTERISTICS At VEN = 1.1V, VIN = VOUT + 0.3V, CBIAS = 0.1F, CIN = COUT = 10F, CNR = 1nF, IOUT = 50mA, VBIAS = 5.0V, and TJ = -40C to +125C, unless otherwise noted. Typical values are at TJ = +25C. TPS74801 PARAMETER TEST CONDITIONS MIN UNIT VIN Input voltage range VOUT + VDO 5.5 V 2.7 5.5 V 0.804 V 3.6 V 2 % VOUT TJ = +25C 0.796 Output voltage range VIN = 5V, IOUT = 1.5A VREF Accuracy (1) 2.97V VBIAS 5.5V, 50mA IOUT 1.5A -2 VOUT/VIN Line regulation VOUT VOUT/IOUT Load regulation VDO VIN dropout voltage (2) VBIAS dropout voltage (2) ICL Current limit (NOM) + 0.3 VIN 5.5V ISHDN Shutdown supply current (IGND) PSRR Power-supply rejection (VBIAS to VOUT) Noise Output noise voltage tSTR Minimum startup time ISS Soft-start charging current 0.09 60 165 mV IOUT = 1.5A, VIN = VBIAS 1.31 1.6 V VOUT = 80% x VOUT (NOM) 2.0 VEN 0.4V -1 LO PG output low voltage PG leakage current TJ Operating junction temperature TSD Thermal shutdown temperature mA 1 50 A 0.150 1 A 30 1kHz, IOUT = 1.5A, VIN = 1.8V, VOUT = 1.5V 50 300kHz, IOUT = 1.5A, VIN = 1.8V, VOUT = 1.5V 30 100Hz to 100kHz, IOUT = 1.5A, CSS = 0.001F 25 x VOUT RLOAD for IOUT = 1.0A, CSS = open 200 s VSS = 0.4V 440 nA dB dB 5.5 0 0.4 VEN = 5V VOUT decreasing VRMS 1.1 85 VHYS PG trip hysteresis LKG A 2 300kHz, IOUT = 1.5A, VIN = 1.8V, VOUT = 1.5V VEN, DG Enable pin deglitch time VPG, 5.5 1 60 VEN, HYS Enable pin hysteresis IPG, %/A 1kHz, IOUT = 1.5A, VIN = 1.8V, VOUT = 1.5V VEN, HI Enable input high level IEN Enable pin current %/V IOUT = 1.5A, VBIAS - VOUT (NOM) 3.25V (3) VEN, LO Enable input low level VIT PG trip threshold 0.5 50mA IOUT 1.5A IFB Feedback pin current Power-supply rejection (VIN to VOUT) 0.8 0.03 IBIAS Bias pin current 4 MAX VBIAS Bias pin voltage range VREF Internal reference (Adj.) (1) (2) (3) TYP V 50 mV 20 s 0.1 1 A 90 94 %VOUT 3 IPG = 1mA (sinking), VOUT < VIT VPG = 5.25V, VOUT > VIT V 0.1 -40 Shutdown, temperature increasing +165 Reset, temperature decreasing +140 %VOUT 0.3 V 1 A +125 C C Adjustable devices tested at 0.8V; resistor tolerance is not taken into account. Dropout is defined as the voltage from VIN to VOUT when VOUT is 3% below nominal. 3.25V is a test condition of this device and can be adjusted by referring to Figure 8. Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Link(s): TPS74801 TPS74801 SBVS074J - JANUARY 2007 - REVISED JANUARY 2012 www.ti.com BLOCK DIAGRAM IN Current Limit BIAS UVLO OUT Thermal Limit 0.44mA VOUT R1 SS CSS Soft-Start Discharge 0.8V Reference FB PG EN Hysteresis and Deglitch R2 0.9 VREF GND Table 1. Standard 1% Resistor Values for Programming the Output Voltage (1) (1) R1 (k) R2 (k) VOUT (V) Short Open 0.8 0.619 4.99 0.9 1.13 4.53 1.0 1.37 4.42 1.05 1.87 4.99 1.1 2.49 4.99 1.2 4.12 4.75 1.5 3.57 2.87 1.8 3.57 1.69 2.5 3.57 1.15 3.3 VOUT = 0.8 x (1 + R1/R2). Table 2. Standard Capacitor Values for Programming the Soft-Start Time (1) tSS(s) = (1) CSS SOFT-START TIME Open 0.1ms 270pF 0.5ms 560pF 1ms 2.7nF 5ms 5.6nF 10ms 0.01F 18ms VREF x CSS 0.8V x CSS(F) = 0.44mA ISS where tSS(s) = soft-start time in seconds. Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Link(s): TPS74801 5 TPS74801 SBVS074J - JANUARY 2007 - REVISED JANUARY 2012 www.ti.com DEVICE INFORMATION NC NC NC OUT 4 3 2 1 IN 6 20 OUT IN 7 19 OUT IN 8 18 OUT PG 9 17 NC BIAS 10 16 FB 13 14 15 NC NC SS TPS74801 GND 12 EN 5 8 FB 7 SS 6 GND GND Thermal Pad 11 PG 3 BIAS 4 IN 10 OUT 9 OUT IN 2 EN IN 1 RGW PACKAGE 5 x 5 QFN (TOP VIEW) 5 DRC PACKAGE 3mm x 3mm SON (TOP VIEW) PIN DESCRIPTIONS 6 NAME DRC (SON) RGW (QFN) IN 1, 2 5-8 DESCRIPTION Input to the device. EN 5 11 Enable pin. Driving this pin high enables the regulator. Driving this pin low puts the regulator into shutdown mode. This pin must not be left unconnected. SS 7 15 Soft-Start pin. A capacitor connected on this pin to ground sets the start-up time. If this pin is left unconnected, the regulator output soft-start ramp time is typically 200s. BIAS 4 10 Bias input voltage for error amplifier, reference, and internal control circuits. PG 3 9 Power Good pin. An open-drain, active-high output that indicates the status of VOUT. When VOUT exceeds the PG trip threshold, the PG pin goes into a high-impedance state. When VOUT is below this threshold the pin is driven to a low-impedance state. A pull-up resistor from 10k to 1M should be connected from this pin to a supply of up to 5.5V. The supply can be higher than the input voltage. Alternatively, the PG pin can be left unconnected if output monitoring is not necessary. FB 8 16 Feedback pin. The feedback connection to the center tap of an external resistor divider network that sets the output voltage. This pin must not be left floating. OUT 9, 10 1, 18-20 NC N/A 2-4, 13, 14, 17 GND 6 12 Thermal Pad -- Regulated output voltage. A small capacitor (total typical capacitance 2.2F, ceramic) is needed from this pin to ground to assure stability. No connection. This pin can be left floating or connected to GND to allow better thermal contact to the top-side plane. Ground Should be soldered to the ground plane for increased thermal performance. Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Link(s): TPS74801 TPS74801 SBVS074J - JANUARY 2007 - REVISED JANUARY 2012 www.ti.com TYPICAL CHARACTERISTICS At TJ = +25C, VIN = VOUT(TYP) + 0.3V, VBIAS = 5V, IOUT = 50mA, VEN = VIN, CIN = 1F, CBIAS = 4.7F, and COUT = 10F, unless otherwise noted. VBIAS LINE REGULATION 0.5 0.15 0.4 0.3 0.10 Change in VOUT (%) Change in VOUT (%) VIN LINE REGULATION 0.20 -40C 0.05 0 +25C +125C -0.05 0.2 -40C 0.1 0 -0.1 +125C +25C -0.2 -0.01 -0.3 -0.15 -0.4 -0.20 -0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 0.5 5.0 1.0 1.5 2.0 2.5 3.0 VIN - VOUT (V) VBIAS - VOUT (V) Figure 3. Figure 4. LOAD REGULATION 3.5 4.0 LOAD REGULATION 1.2 0.5 0.4 0.3 Change in VOUT (%) Change in VOUT (%) 1.0 0.8 0.6 0.4 0.2 +125C 0.1 0 -40C +25C -0.1 -0.2 -0.3 0.2 -0.4 0 0 10 20 30 40 -0.5 0.05 50 1.0 1.5 IOUT (mA) IOUT (A) Figure 5. Figure 6. VIN DROPOUT VOLTAGE vs IOUT AND TEMPERATURE (TJ) VIN DROPOUT VOLTAGE vs (VBIAS - VOUT) AND TEMPERATURE (TJ) 100 200 90 180 80 IOUT = 1.5A 160 +125C VDO (VIN - VOUT) (mV) VDO (VIN - VOUT) (mV) 0.5 70 60 50 40 +25C 30 20 140 120 +125C 100 +25C 80 60 40 -40C 10 -40C 20 0 0 0 0.5 1.0 1.5 1.0 IOUT (A) 1.5 2.0 2.5 3.0 3.5 4.0 4.5 VBIAS - VOUT (V) Figure 7. Figure 8. Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Link(s): TPS74801 7 TPS74801 SBVS074J - JANUARY 2007 - REVISED JANUARY 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) At TJ = +25C, VIN = VOUT(TYP) + 0.3V, VBIAS = 5V, IOUT = 50mA, VEN = VIN, CIN = 1F, CBIAS = 4.7F, and COUT = 10F, unless otherwise noted. VIN DROPOUT VOLTAGE vs (VBIAS - VOUT) AND TEMPERATURE (TJ) VBIAS DROPOUT VOLTAGE vs IOUT AND TEMPERATURE (TJ) 200 2200 IOUT = 0.5A 180 2000 VDO (VBIAS - VOUT) (mV) VDO (VIN - VOUT) (mV) 160 140 120 100 +25C 80 +125C 60 40 -40C 1800 1600 +125C 1400 1200 +25C 1000 -40C 800 20 600 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0 4.5 0.5 VBIAS - VOUT (V) Figure 10. VBIAS PSRR vs FREQUENCY VIN PSRR vs FREQUENCY 90 80 IOUT = 0.1A IOUT = 1.5A 70 60 50 40 IOUT = 0.5A 30 VIN = 1.8V VOUT = 1.2V VBIAS = 5V CSS = 1nF 20 10 0 10 Power-Supply Rejection Ratio (dB) Power-Supply Rejection Ratio (dB) 90 80 70 IOUT = 100mA 60 50 40 30 20 VIN = 1.8V VOUT = 1.2V CSS = 1nF 10 0 100 1k 10k 100k 1M 10 10M 100 IOUT = 1.5A 1k Frequency (Hz) 10k 70 1kHz 60 10kHz 50 40 100kHz 30 20 500kHz 10 0 0 0.25 0.50 0.75 1.00 1.25 10M NOISE SPECTRAL DENSITY 1.50 1.75 2.00 2.25 Output Spectral Noise Density (mV/OHz) VOUT = 1.2V IOUT = 1.5A CSS = 1nF 80 1M Figure 12. VIN PSRR vs (VIN - VOUT) 90 100k Frequency (Hz) Figure 11. Power-Supply Rejection Ratio (dB) 1.5 IOUT (A) Figure 9. 1 IOUT = 100mA VOUT = 1.2V CSS = 0nF 0.1 CSS = 10nF CSS = 1nF 0.01 100 VIN - VOUT (V) 1k 10k 100k Frequency (Hz) Figure 13. 8 1.0 Figure 14. Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Link(s): TPS74801 TPS74801 SBVS074J - JANUARY 2007 - REVISED JANUARY 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) At TJ = +25C, VIN = VOUT(TYP) + 0.3V, VBIAS = 5V, IOUT = 50mA, VEN = VIN, CIN = 1F, CBIAS = 4.7F, and COUT = 10F, unless otherwise noted. BIAS PIN CURRENT vs IOUT AND TEMPERATURE (TJ) BIAS PIN CURRENT vs VBIAS AND TEMPERATURE (TJ) 2.0 2.0 1.8 1.8 +125C 1.6 1.6 1.4 1.4 IBIAS (mA) IBIAS (mA) +125C 1.2 1.0 0.8 +25C 1.0 0.8 +25C -40C 0.6 1.2 0.6 -40C 0.4 0.4 0.2 0.2 0 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 2.0 1.6 2.5 3.0 3.5 IOUT (A) 4.5 5.0 5.5 VBIAS (V) Figure 15. Figure 16. SOFT-START CHARGING CURRENT (ISS) vs TEMPERATURE (TJ) LOW-LEVEL PG VOLTAGE vs CURRENT 1.0 500 0.9 VOL Low-Level PG Voltage (V) 475 450 ISS (nA) 4.0 425 400 375 350 325 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 300 -50 -25 0 25 50 75 100 125 0 2 4 Junction Temperature (C) Figure 17. 8 10 12 Figure 18. CURRENT LIMIT vs (VBIAS - VOUT) 4.0 VOUT = 0.8V 3.8 +125C 3.6 Current Limit (A) 6 PG Current (mA) 3.4 3.2 3.0 -40C 2.8 +25C 2.6 2.4 2.2 2.0 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VBIAS - VOUT (V) Figure 19. Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Link(s): TPS74801 9 TPS74801 SBVS074J - JANUARY 2007 - REVISED JANUARY 2012 www.ti.com TYPICAL CHARACTERISTICS At TJ = +25C, VIN = VOUT(TYP) + 0.3V, VBIAS = 5V, IOUT = 1A, VEN = VIN = 1.8V, VOUT = 1.5V, CIN = 1F, CBIAS = 4.7F, and COUT = 10F, unless otherwise noted. VBIAS LINE TRANSIENT VIN LINE TRANSIENT CSS = 1nF COUT = 10mF (Ceramic) COUT = 10mF (Ceramic) 100mV/div 100mV/div COUT = 2.2mF (Ceramic) 100mV/div CSS = 1nF 3.8V 5.0V 1V/div 1V/div 1V/ms 3.3V 1V/ms 1.8V Time (50ms/div) Time (50ms/div) Figure 20. Figure 21. OUTPUT LOAD TRANSIENT RESPONSE TURN-ON RESPONSE COUT = 470mF (OSCON) CSS = 0nF 100mV/div COUT = 10mF (Ceramic) 100mV/div CSS = 1nF 0.5V/div VOUT CSS = 2.2nF COUT = 2.2mF (Ceramic) 100mV/div 1.2V 1.5A CSS = 1nF 1A/div 1V/div VEN 0V 1A/ms 50mA Time (50ms/div) Time (1ms/div) Figure 22. Figure 23. POWER-UP/POWER-DOWN VIN = VBIAS = VEN 1V/div VPG (500mV/div) VOUT Time (20ms/div) Figure 24. 10 Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Link(s): TPS74801 TPS74801 SBVS074J - JANUARY 2007 - REVISED JANUARY 2012 www.ti.com APPLICATION INFORMATION The TPS74801 belongs to a family of low dropout regulators that feature soft-start capability. These regulators use a low current bias input to power all internal control circuitry, allowing the NMOS pass transistor to regulate very low input and output voltages. The use of an NMOS-pass FET offers several critical advantages for many applications. Unlike a PMOS topology device, the output capacitor has little effect on loop stability. This architecture allows the TPS74801 to be stable with any capacitor type of value 2.2F or greater. Transient response is also superior to PMOS topologies, particularly for low VIN applications. The TPS74801 features a programmable voltage-controlled soft-start circuit that provides a smooth, monotonic start-up and limits startup inrush currents that may be caused by large capacitive loads. A power good (PG) output is available to allow supply monitoring and sequencing of other supplies. An enable (EN) pin with hysteresis and deglitch allows slow-ramping signals to be used for sequencing the device. The low VIN and VOUT capability allows for inexpensive, easy-to-design, and efficient linear regulation between the multiple supply voltages often present in processor-intensive systems. Figure 25 illustrates the typical application circuit for the TPS74801 adjustable output device. VIN IN CIN 1mF PG R3 BIAS EN VBIAS TPS74801 R1 SS CBIAS 1mF VOUT OUT FB GND CSS COUT 10mF R2 ( VOUT = 0.8 1 + R1 R2 ) Figure 25. Typical Application Circuit for the TPS74801 (Adjustable) R1 and R2 can be calculated for any output voltage using the formula shown in Figure 25. Refer to Table 1 for sample resistor values of common output voltages. In order to achieve the maximum accuracy specifications, R2 should be 4.99k. INPUT, OUTPUT, AND BIAS CAPACITOR REQUIREMENTS The device is designed to be stable for all available types and values of output capacitors 2.2F. The device is also stable with multiple capacitors in parallel, which can be of any type or value. The capacitance required on the IN and BIAS pins strongly depends on the input supply source impedance. To counteract any inductance in the input, the minimum recommended capacitor for VIN and VBIAS is 1F. If VIN and VBIAS are connected to the same supply, the recommended minimum capacitor for VBIAS is 4.7F. Good quality, low ESR capacitors should be used on the input; ceramic X5R and X7R capacitors are preferred. These capacitors should be placed as close the pins as possible for optimum performance. TRANSIENT RESPONSE The TPS74801 was designed to have excellent transient response for most applications with a small amount of output capacitance. In some cases, the transient response may be limited by the transient response of the input supply. This limitation is especially true in applications where the difference between the input and output is less than 300mV. In this case, adding additional input capacitance improves the transient response much more than just adding additional output capacitance would do. With a solid input supply, adding additional output capacitance reduces undershoot and overshoot during a transient event; refer to Figure 22 in the Typical Characteristics section. Because the TPS74801 is stable with output capacitors as low as 2.2F, many applications may then need very little capacitance at the LDO output. For these applications, local bypass capacitance for the powered device may be sufficient to meet the transient requirements of the application. This design reduces the total solution cost by avoiding the need to use expensive, high-value capacitors at the LDO output. Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Link(s): TPS74801 11 TPS74801 SBVS074J - JANUARY 2007 - REVISED JANUARY 2012 www.ti.com DROPOUT VOLTAGE The TPS74801 offers very low dropout performance, making it well-suited for high-current, low VIN/low VOUT applications. The low dropout of the TPS74801 allows the device to be used in place of a dc/dc converter and still achieve good efficiency. This provides designers with the power architecture for their application to achieve the smallest, simplest, and lowest cost solution. There are two different specifications for dropout voltage with the TPS74801. The first specification (shown in Figure 26) is referred to as VIN Dropout and is used when an external bias voltage is applied to achieve low dropout. This specification assumes that VBIAS is at least 3.25V (1) above VOUT, which is the case for VBIAS when powered by a 5.0V rail with 5% tolerance and with VOUT = 1.5V. If VBIAS is higher than VOUT +3.25V (1), VIN dropout is less than specified. BIAS IN Reference VBIAS = 5V 5% VIN = 1.8V VOUT = 1.5V IOUT = 1.5A Efficiency = 83% OUT VOUT COUT FB Simplified Block Diagram Figure 26. Typical Application of the TPS74801 Using an Auxiliary Bias Rail VIN BIAS IN Reference VBIAS = 3.3V 5% VIN = 3.3V 5V VOUT = 1.5V IOUT = 1.5A Efficiency = 45% OUT VOUT COUT Figure 27. Typical Application of the TPS74801 Without an Auxiliary Bias Rail 12 PROGRAMMABLE SOFT-START The TPS74801 features a programmable, monotonic, voltage-controlled soft-start that is set with an external capacitor (CSS). This feature is important for many applications because it eliminates power-up initialization problems when powering FPGAs, DSPs, or other processors. The controlled voltage ramp of the output also reduces peak inrush current during start-up, minimizing start-up transient events to the input power bus. To achieve a linear and monotonic soft-start, the TPS74801 error amplifier tracks the voltage ramp of the external soft-start capacitor until the voltage exceeds the internal reference. The soft-start ramp time depends on the soft-start charging current (ISS), soft-start capacitance (CSS), and the internal reference voltage (VREF), and can be calculated using Equation 1: (VREF CSS) tSS = ISS (1) If large output capacitors are used, the device current limit (ICL) and the output capacitor may set the start-up time. In this case, the start-up time is given by Equation 2: (VOUT(NOM) COUT) tSSCL = ICL(MIN) (2) where: VOUT(NOM) is the nominal output voltage, COUT is the output capacitance, and ICL(MIN) is the minimum current limit for the device. In applications where monotonic startup is required, the soft-start time given by Equation 1 should be set greater than Equation 2. FB Simplified Block Diagram (1) The second specification (shown in Figure 27) is referred to as VBIAS Dropout and applies to applications where IN and BIAS are tied together. This option allows the device to be used in applications where an auxiliary bias voltage is not available or low dropout is not required. Dropout is limited by BIAS in these applications because VBIAS provides the gate drive to the pass FET; therefore, VBIAS must be 1.6V above VOUT. Because of this usage, IN and BIAS tied together easily consume huge power. Pay attention not to exceed the power rating of the IC package. 3.25V is a test condition of this device and can be adjusted by referring to Figure 8. The maximum recommended soft-start capacitor is 0.015F. Larger soft-start capacitors can be used and do not damage the device; however, the soft-start capacitor discharge circuit may not be able to fully discharge the soft-start capacitor when enabled. Soft-start capacitors larger than 0.015F could be a problem in applications where it is necessary to Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Link(s): TPS74801 TPS74801 SBVS074J - JANUARY 2007 - REVISED JANUARY 2012 www.ti.com rapidly pulse the enable pin and still require the device to soft-start from ground. CSS must be low-leakage; X7R, X5R, or C0G dielectric materials are preferred. Refer to Table 2 for suggested soft-start capacitor values. SEQUENCING REQUIREMENTS VIN, VBIAS, and VEN can be sequenced in any order without causing damage to the device. However, for the soft-start function to work as intended, certain sequencing rules must be applied. Connecting EN to IN is acceptable for most applications, as long as VIN is greater than 1.1V and the ramp rate of VIN and VBIAS is faster than the set soft-start ramp rate. If the ramp rate of the input sources is slower than the set soft-start time, the output tracks the slower supply minus the dropout voltage until it reaches the set output voltage. If EN is connected to BIAS, the device soft-starts as programmed, provided that VIN is present before VBIAS. If VBIAS and VEN are present before VIN is applied and the set soft-start time has expired, then VOUT tracks VIN. If the soft-start time has not expired, the output tracks VIN until VOUT reaches the value set by the charging soft-start capacitor. Figure 28 shows the use of an RC-delay circuit to hold off VEN until VBIAS has ramped. This technique can also be used to drive EN from VIN. An external control signal can also be used to enable the device after VIN and VBIAS are present. NOTE: When VBIAS and VEN are present and VIN is not supplied, this device outputs approximately 50A of current from OUT. Although this condition does not cause any damage to the device, the output current may charge up the OUT node if total resistance between OUT and GND (including external feedback resistors) is greater than 10k. VIN IN VOUT OUT R1 CIN BIAS TPS74801 FB EN SS COUT R2 R VBIAS CBIAS C GND CSS Figure 28. Soft-Start Delay Using an RC Circuit to Enable the Device OUTPUT NOISE The TPS74801 provides low output noise when a soft-start capacitor is used. When the device reaches the end of the soft-start cycle, the soft-start capacitor serves as a filter for the internal reference. By using a 0.001F soft-start capacitor, the output noise is reduced by half and is typically 30VRMS for a 1.2V output (10Hz to 100kHz). Further increasing CSS has little effect on noise. Because most of the output noise is generated by the internal reference, the noise is a function of the set output voltage. The RMS noise with a 0.001F soft-start capacitor is given in Equation 3: ( VN(mVRMS) = 25 mVRMS V )x V OUT(V) (3) The low output noise of the TPS74801 makes it a good choice for powering transceivers, PLLs, or other noise-sensitive circuitry. ENABLE/SHUTDOWN The enable (EN) pin is active high and is compatible with standard digital signaling levels. VEN below 0.4V turns the regulator off, while VEN above 1.1V turns the regulator on. Unlike many regulators, the enable circuitry has hysteresis and deglitching for use with relatively slowly ramping analog signals. This configuration allows the TPS74801 to be enabled by connecting the output of another supply to the EN pin. The enable circuitry typically has 50mV of hysteresis and a deglitch circuit to help avoid on-off cycling as a result of small glitches in the VEN signal. The enable threshold is typically 0.8V and varies with temperature and process variations. Temperature variation is approximately -1mV/C; process variation accounts for most of the rest of the variation to the 0.4V and 1.1V limits. If precise turn-on timing is required, a fast rise-time signal must be used to enable the TPS74801. If not used, EN can be connected to either IN or BIAS. If EN is connected to IN, it should be connected as close as possible to the largest capacitance on the input to prevent voltage droops on that line from triggering the enable circuit. POWER GOOD The power good (PG) pin is an open-drain output and can be connected to any 5.5V or lower rail through an external pull-up resistor. This pin requires at least 1.1V on VBIAS in order to have a valid output. The PG output is high-impedance when VOUT is greater than VIT + VHYS. If VOUT drops below VIT or if VBIAS drops below 1.9V, the open-drain output turns on and pulls the PG output low. The PG pin also asserts when the device is disabled. The recommended operating condition of PG pin sink current is up to 1mA, so the pull-up resistor for PG should be in the range of 10k to 1M. If output voltage monitoring is not needed, the PG pin can be left floating. Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Link(s): TPS74801 13 TPS74801 SBVS074J - JANUARY 2007 - REVISED JANUARY 2012 www.ti.com INTERNAL CURRENT LIMIT The TPS74801 features a factory-trimmed, accurate current limit that is flat over temperature and supply voltage. The current limit allows the device to supply surges of up to 2A and maintain regulation. The current limit responds in approximately 10s to reduce the current during a short-circuit fault. The internal current limit protection circuitry of the TPS74801 is designed to protect against overload conditions. It is not intended to allow operation above the rated current of the device. Continuously running the TPS74801 above the rated current degrades device reliability. THERMAL PROTECTION Thermal protection disables the output when the junction temperature rises to approximately +160C, allowing the device to cool. When the junction temperature cools to approximately +140C, the output circuitry is enabled. Depending on power dissipation, thermal resistance, and ambient temperature the thermal protection circuit may cycle on and off. This cycling limits the dissipation of the regulator, protecting it from damage as a result of overheating. Activation of the thermal protection circuit indicates excessive power dissipation or inadequate heatsinking. For reliable operation, junction temperature should be limited to +125C maximum. To estimate the margin of safety in a complete design (including heatsink), increase the ambient temperature until thermal protection is triggered; use worst-case loads and signal conditions. For good reliability, thermal protection should trigger at least +40C above the maximum expected ambient condition of the application. This condition produces a worst-case junction temperature of +125C at the highest expected ambient temperature and worst-case load. R1 in Figure 25 should be connected as close as possible to the load. If BIAS is connected to IN, it is recommended to connect BIAS as close to the sense point of the input supply as possible. This connection minimizes the voltage drop on BIAS during transient conditions and can improve the turn-on response. Knowing the device power dissipation and proper sizing of the thermal plane that is connected to the thermal pad is critical to avoiding thermal shutdown and ensuring reliable operation. Power dissipation of the device depends on input voltage and load conditions and can be calculated using Equation 4: PD = (VIN - VOUT) IOUT (4) Power dissipation can be minimized and greater efficiency can be achieved by using the lowest possible input voltage necessary to achieve the required output voltage regulation. On both the SON (DRC) and QFN (RGW) packages, the primary conduction path for heat is through the exposed pad to the printed circuit board (PCB). The pad can be connected to ground or be left floating; however, it should be attached to an appropriate amount of copper PCB area to ensure the device does not overheat. The maximum junction-to-ambient thermal resistance depends on the maximum ambient temperature, maximum device junction temperature, and power dissipation of the device and can be calculated using Equation 5: (+125C - TA) RqJA = PD (5) Knowing the maximum RJA, the minimum amount of PCB copper area needed for appropriate heatsinking can be estimated using Figure 29. 140 DRC RGW 120 LAYOUT RECOMMENDATIONS AND POWER DISSIPATION An optimal layout can greatly improve transient performance, PSRR, and noise. To minimize the voltage drop on the input of the device during load transients, the capacitance on IN and BIAS should be connected as close as possible to the device. This capacitance also minimizes the effects of parasitic inductance and resistance of the input source and can, therefore, improve stability. To achieve optimal transient performance and accuracy, the top side of 14 qJA (C/W) 100 The internal protection circuitry of the TPS74801 is designed to protect against overload conditions. It is not intended to replace proper heatsinking. Continuously running the TPS74801 into thermal shutdown degrades device reliability. 80 60 40 20 0 0 Note: 1 2 4 5 7 3 6 Board Copper Area (in2) 8 9 10 JA value at board size of 9in2 (that is, 3in x 3in) is a JEDEC standard. Submit Documentation Feedback Figure 29. JA vs Board Size Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Link(s): TPS74801 TPS74801 SBVS074J - JANUARY 2007 - REVISED JANUARY 2012 www.ti.com NOTE: When the device is mounted on an application PCB, it is strongly recommended to use JT and JB, as explained in the Estimating Junction Temperature section. ESTIMATING JUNCTION TEMPERATURE Using the thermal metrics JT and JB, as shown in the Thermal Information table, the junction temperature can be estimated with corresponding formulas (given in Equation 6). For backwards compatibility, an older JC,Top parameter is listed as well. YJT: TJ = TT + YJT * PD YJB: TJ = TB + YJB * PD (6) Where PD is the power dissipation shown by Equation 4, TT is the temperature at the center-top of the IC package, and TB is the PCB temperature measured 1mm away from the IC package on the PCB surface (see Figure 31). NOTE: Both TT and TB can be measured on actual application boards using a thermo-gun (an infrared thermometer). By looking at Figure 30, the new thermal metrics (JT and JB) have very little dependency on board size. That is, using JT or JB with Equation 6 is a good way to estimate TJ by simply measuring TT or TB, regardless of the application board size. 12 10 YJB YJT and YJB (C/W) Figure 29 shows the variation of JA as a function of ground plane copper area in the board. It is intended only as a guideline to demonstrate the effects of heat spreading in the ground plane and should not be used to estimate actual thermal performance in real application environments. 8 DRC RGW 6 4 2 YJT 0 0 1 2 3 4 5 6 7 8 9 10 Board Copper Area (in2) Figure 30. JT and JB vs Board Size For a more detailed discussion of why TI does not recommend using JC(top) to determine thermal characteristics, refer to application report SBVA025, Using New Thermal Metrics, available for download at www.ti.com. For further information, refer to application report SPRA953, IC Package Thermal Metrics, also available on the TI website. For more information about measuring TT and TB, see the application note SBVA025, Using New Thermal Metrics, available for download at www.ti.com. Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Link(s): TPS74801 15 TPS74801 SBVS074J - JANUARY 2007 - REVISED JANUARY 2012 www.ti.com TT on top of IC TB on PCB surface TB on PCB TT on top of IC 1mm 1mm (a) Example DRC (SON) Package Measurement (b) Example RGW (QFN) Package Measurement Figure 31. Measuring Points for TT and TB 16 Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Link(s): TPS74801 TPS74801 SBVS074J - JANUARY 2007 - REVISED JANUARY 2012 www.ti.com REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision I (November 2010) to Revision J * Page Changed TJ range in Absolute Maximum Ratings table ....................................................................................................... 2 Changes from Revision H (October, 2010) to Revision I * Page Corrected equation for Table 2 ............................................................................................................................................. 5 Submit Documentation Feedback Copyright (c) 2007-2012, Texas Instruments Incorporated Product Folder Link(s): TPS74801 17 PACKAGE OPTION ADDENDUM www.ti.com 20-Aug-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (C) Device Marking (3) (4/5) TPS74801DRCR ACTIVE SON DRC 10 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 BTO TPS74801DRCRG4 ACTIVE SON DRC 10 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 BTO TPS74801DRCT ACTIVE SON DRC 10 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 BTO TPS74801DRCTG4 ACTIVE SON DRC 10 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 BTO TPS74801QRGWRQ1 ACTIVE VQFN RGW 20 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 TPS 74801Q TPS74801RGWR ACTIVE VQFN RGW 20 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 TPS 74801 TPS74801RGWRG4 ACTIVE VQFN RGW 20 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 TPS 74801 TPS74801RGWT ACTIVE VQFN RGW 20 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 TPS 74801 TPS74801RGWTG4 ACTIVE VQFN RGW 20 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 TPS 74801 TPS74801TDRCRQ1 ACTIVE SON DRC 10 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 105 QVK (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 20-Aug-2013 (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. 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OTHER QUALIFIED VERSIONS OF TPS74801, TPS74801-Q1 : * Catalog: TPS74801 * Automotive: TPS74801-Q1 NOTE: Qualified Version Definitions: * Catalog - TI's standard catalog product * Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 19-Aug-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device TPS74801DRCR Package Package Pins Type Drawing SON DRC 10 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS74801DRCT SON DRC 10 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS74801QRGWRQ1 VQFN RGW 20 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 TPS74801RGWR VQFN RGW 20 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 TPS74801RGWT VQFN RGW 20 250 180.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 TPS74801TDRCRQ1 SON DRC 10 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 19-Aug-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS74801DRCR SON DRC 10 3000 367.0 367.0 35.0 TPS74801DRCT SON DRC 10 250 210.0 185.0 35.0 TPS74801QRGWRQ1 VQFN RGW 20 3000 367.0 367.0 35.0 TPS74801RGWR VQFN RGW 20 3000 367.0 367.0 35.0 TPS74801RGWT VQFN RGW 20 250 210.0 185.0 35.0 TPS74801TDRCRQ1 SON DRC 10 3000 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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