5 V, Slew-Rate Limited, Half-Duplex and
Full-Duplex RS-485/RS-422 Transceivers
ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/ADM4855/ADM4856/ADM4857
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
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Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2004–2012 Analog Devices, Inc. All rights reserved.
FEATURES
EIA RS-485-/RS-422-compliant
Data rate options
ADM4850/ADM4854: 115 kbps
ADM4851/ADM4855: 500 kbps
ADM4852/ADM4856: 2.5 Mbps
ADM4853/ADM4857: 10 Mbps
Half- and full-duplex options
Reduced slew rates for low EMI
True fail-safe receiver inputs
5 μA (maximum) supply current in shutdown mode
Up to 256 transceivers on one bus
Outputs high-Z when disabled or powered off
−7 V to +12 V bus common-mode range
Thermal shutdown and short-circuit protection
Pin-compatible with the MAX308x
Specified over the −40°C to +85°C temperature range
Available in 8-lead SOIC, LFCSP, and MSOP packages
Qualified for automotive applications
APPLICATIONS
Low power RS-485 applications
EMI-sensitive systems
DTE-DCE interfaces
Industrial control
Packet switching
Local area networks
Level translators
FUNCTIONAL BLOCK DIAGRAMS
04931-001
RO
RE
R
DE
DI D
A
B
GND
V
CC
ADM4850/ADM4851/
ADM4852/ADM4853
Figure 1.
04931-028
RO R
A
B
DI D
Z
Y
GND
V
CC
ADM4854/ADM4855/
ADM4856/ADM4857
Figure 2.
GENERAL DESCRIPTION
The ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/
ADM4855/ADM4856/ADM4857 are differential line transceivers
suitable for high speed half- and full-duplex data communication on
multipoint bus transmission lines. They are designed for balanced
data transmission and comply with EIA Standards RS-485 and
RS-422. The ADM4850/ADM4851/ADM4852/ADM4853 are half-
duplex transceivers that share differential lines and have separate
enable inputs for the driver and receiver. The full-duplex
ADM4854/ADM4855/ADM4856/ADM4857 transceivers have
dedicated differential line driver outputs and receiver inputs.
The parts have a 1/8-unit-load receiver input impedance, which
allows up to 256 transceivers on one bus. Because only one driver
should be enabled at any time, the output of a disabled or pow-
ered-down driver is three-stated to avoid overloading the bus.
The receiver inputs have a true fail-safe feature, which ensures
a logic high output level when the inputs are open or shorted.
This guarantees that the receiver outputs are in a known state
before communication begins and when communication ends.
The driver outputs are slew-rate limited to reduce EMI and data
errors caused by reflections from improperly terminated buses.
Excessive power dissipation caused by bus contention or by output
shorting is prevented with a thermal shutdown circuit.
The parts are fully specified over the commercial and industrial
temperature ranges and are available in 8-lead SOIC, LFCSP
(ADM4850/ADM4851/ADM4852/ADM4853), and MSOP
(ADM4850 only) packages.
Table 1. Selection Table
Part No. Half-/Full-Duplex Data Rate
ADM4850 Half 115 kbps
ADM4851 Half 500 kbps
ADM4852 Half 2.5 Mbps
ADM4853 Half 10 Mbps
ADM4854 Full 115 kbps
ADM4855 Full 500 kbps
ADM4856 Full 2.5 Mbps
ADM4857 Full 10 Mbps
ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/ADM4855/ADM4856/ADM4857
Rev. D | Page 2 of 16
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagrams............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
ADM4850/ADM4854 Timing Specifications........................... 4
ADM4851/ADM4855 Timing Specifications........................... 4
ADM4852/ADM4856 Timing Specifications........................... 5
ADM4853/ADM4857 Timing Specifications........................... 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configurations and Function Descriptions ........................... 7
Typical Performance Characteristics ............................................. 9
Test Circuits..................................................................................... 11
Switching Characteristics .............................................................. 12
Circuit Description......................................................................... 13
Slew-Rate Control ...................................................................... 13
Receiver Input Filtering............................................................. 13
Half-/Full-Duplex Operation ................................................... 13
High Receiver Input Impedance .............................................. 14
Three-State Bus Connection..................................................... 14
Shutdown Mode ......................................................................... 14
Fail-Safe Operation .................................................................... 14
Current Limit and Thermal Shutdown ................................... 14
Outline Dimensions ....................................................................... 15
Ordering Guide .......................................................................... 16
Automotive Product................................................................... 16
REVISION HISTORY
1/12—Rev. C to Rev. D
Change to Features Section ............................................................. 1
Changes to Ordering Guide .......................................................... 15
Added Automotive Products Section .......................................... 15
1/11—Rev. B to Rev. C
Change to Table 8, Pin 3 Description ............................................ 7
Changes to Figure 29...................................................................... 12
Changes to Ordering Guide .......................................................... 15
7/09—Rev. A to Rev. B
Added MSOP Package .................................................. Throughout
Changes to Table 2............................................................................ 3
Changes to Table 7............................................................................ 6
Added Figure 4; Renumbered Figures Sequentially..................... 7
Moved Typical Performance Characteristics Section.................. 8
Changes to Figure 24, Figure 27 ................................................... 11
Changes to Figure 29...................................................................... 12
Change to Shutdown Mode Section............................................. 13
Updated Outline Dimensions....................................................... 14
Changes to Ordering Guide .......................................................... 15
4/09—Rev. 0 to Rev. A
Changes to Ordering Guide .......................................................... 15
10/04—Revision 0: Initial Version
ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/ADM4855/ADM4856/ADM4857
Rev. D | Page 3 of 16
SPECIFICATIONS
VCC = 5 V ± 5%, TA = TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter Min Typ Max Unit Test Conditions/Comments
DRIVER
Differential Output Voltage, VOD V
CC V R = ∞, see Figure 181
2.0 5 V R = 50 Ω (RS-422), see Figure 18
1.5 5 V R = 27 Ω (RS-485), see Figure 18
|VOD3| 1.5 5 V VTST = −7 V to 12 V, see Figure 19
∆|VOD| for Complementary Output States 0.2 V R = 27 Ω or 50 Ω, see Figure 18
Common-Mode Output Voltage, VOC 3 V R = 27 Ω or 50 Ω, see Figure 18
∆|VOC| for Complementary Output States 0.2 V R = 27 Ω or 50 Ω, see Figure 18
Output Short-Circuit Current, VOUT = High −200 +200 mA −7 V < VOUT < +12 V
Output Short-Circuit Current, VOUT = Low −200 +200 mA −7 V < VOUT < +12 V
DRIVER INPUT LOGIC
CMOS Input Logic Threshold Low 0.8 V
CMOS Input Logic Threshold High 2.0 V
CMOS Logic Input Current (DI) ±1 μA
DE Input Resistance to GND 220 kΩ
RECEIVER
Differential Input Threshold Voltage, VTH −200 −125 −30 mV −7 V < VOC < +12 V
Input Hysteresis 20 mV −7 V < VOC < +12 V
Input Resistance (A, B) 96 150 kΩ −7 V < VOC < +12 V
Input Current (A, B) 0.125 mA VIN = +12 V
−0.1 mA V
IN = −7 V
CMOS Logic Input Current (RE) ±1 μA
CMOS Output Voltage Low 0.4 V IOUT = +4 mA
CMOS Output Voltage High 4.0 V IOUT = −4 mA
Output Short-Circuit Current 7 85 mA VOUT = GND or VCC
Three-State Output Leakage Current ±2 μA 0.4 V ≤ VOUT ≤ 2.4 V
POWER SUPPLY CURRENT
115 kbps Options (ADM4850/ADM4854) 5 μA DE = 0 V, RE = VCC (shutdown)
36 60 μA
DE = 0 V, RE = 0 V
100 160 μA DE = VCC
500 kbps Options (ADM4851/ADM4855) 5 μA DE = 0 V, RE = VCC (shutdown)
80 120 μA
DE = 0 V, RE = 0 V
120 200 μA DE = VCC
2.5 Mbps Options (ADM4852/ADM4856) 5 μA DE = 0 V, RE = VCC (shutdown)
250 400 μA
DE = 0 V, RE = 0 V
320 500 μA DE = VCC
10 Mbps Options (ADM4853/ADM4857) 5 μA DE = 0 V, RE = VCC (shutdown)
250 400 μA
DE = 0 V, RE = 0 V
320 500 μA DE = VCC
1 Guaranteed by design.
ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/ADM4855/ADM4856/ADM4857
Rev. D | Page 4 of 16
ADM4850/ADM4854 TIMING SPECIFICATIONS
VCC = 5 V ± 5%, TA = TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter Min Typ Max Unit Test Conditions/Comments
DRIVER
Maximum Data Rate 115 kbps
Propagation Delay, tPLH, tPHL 600 2500 ns RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 20
Skew, tSKEW 70 ns RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 20
Rise/Fall Times, tR, tF 600 2400 ns RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 20
Enable Time, tZH 2000 ns RL = 500 Ω, CL = 100 pF, see Figure 21, ADM4850
Disable Time, tZL 2000 ns RL = 500 Ω, CL = 15 pF, see Figure 21, ADM4850
Enable Time from Shutdown 4000 ns RL = 500 Ω, CL = 100 pF, see Figure 21, ADM4850
RECEIVER
Propagation Delay, tPLH, tPHL 400 1000 ns CL = 15 pF, see Figure 22
Differential Skew, tSKEW 255 ns CL = 15 pF, see Figure 22
Enable Time 5 50 ns RL = 1 kΩ, CL = 15 pF, see Figure 23, ADM4850
Disable Time 20 50 ns RL = 1 kΩ, CL = 15 pF, see Figure 23, ADM4850
Enable Time from Shutdown 4000 ns RL = 1 kΩ, CL = 15 pF, see Figure 23, ADM4850
Time to Shutdown 50 330 3000 ns ADM48501
1 The half-duplex device is put into shutdown mode by driving RE high and DE low. If these inputs are in this state for less than 50 ns, the device is guaranteed not to
enter shutdown mode. If the enable inputs are in this state for at least 3000 ns, the device is guaranteed to enter shutdown mode.
ADM4851/ADM4855 TIMING SPECIFICATIONS
VCC = 5 V ± 5%, TA = TMIN to TMAX, unless otherwise noted.
Table 4.
Parameter Min Typ Max Unit Test Conditions/Comments
DRIVER
Maximum Data Rate 500 kbps
Propagation Delay, tPLH, tPHL 250 600 ns RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 20
Skew, tSKEW 40 ns RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 20
Rise/Fall Times, tR, tF 200 600 ns RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 20
Enable Time, tZH 1000 ns RL = 500 Ω, CL = 100 pF, see Figure 21, ADM4851
Disable Time, tZL 1000 ns RL = 500 Ω, CL = 15 pF, see Figure 21, ADM4851
Enable Time from Shutdown 4000 ns RL = 500 Ω, CL = 100 pF, see Figure 21, ADM4851
RECEIVER
Propagation Delay, tPLH, tPHL 400 1000 ns CL = 15 pF, see Figure 22
Differential Skew, tSKEW 250 ns CL = 15 pF, see Figure 22
Enable Time 5 50 ns RL = 1 kΩ, CL = 15 pF, see Figure 23, ADM4851
Disable Time 20 50 ns RL = 1 kΩ, CL = 15 pF, see Figure 23, ADM4851
Enable Time from Shutdown 4000 ns RL = 1 kΩ, CL = 15 pF, see Figure 23, ADM4851
Time to Shutdown 50 330 3000 ns ADM48511
1 The half-duplex device is put into shutdown mode by driving RE high and DE low. If these inputs are in this state for less than 50 ns, the device is guaranteed not to
enter shutdown mode. If the enable inputs are in this state for at least 3000 ns, the device is guaranteed to enter shutdown mode.
ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/ADM4855/ADM4856/ADM4857
Rev. D | Page 5 of 16
ADM4852/ADM4856 TIMING SPECIFICATIONS
VCC = 5 V ± 5%, TA = TMIN to TMAX, unless otherwise noted.
Table 5.
Parameter Min Typ Max Unit Test Conditions/Comments
DRIVER
Maximum Data Rate 2.5 Mbps
Propagation Delay, tPLH, tPHL 50 180 ns RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 20
Skew, tSKEW 50 ns RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 20
Rise/Fall Times, tR, tF 140 ns RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 20
Enable Time, tZH 180 ns RL = 500 Ω, CL = 100 pF, see Figure 21, ADM4852
Disable Time, tZL 180 ns RL = 500 Ω, CL = 15 pF, see Figure 21, ADM4852
Enable Time from Shutdown 4000 ns RL = 500 Ω, CL = 100 pF, see Figure 21, ADM4852
RECEIVER
Propagation Delay, tPLH, tPHL 55 190 ns CL = 15 pF, see Figure 22
Differential Skew, tSKEW 50 ns CL = 15 pF, see Figure 22
Enable Time 5 50 ns RL = 1 kΩ, CL = 15 pF, see Figure 23, ADM4852
Disable Time 20 50 ns RL = 1 kΩ, CL = 15 pF, see Figure 23, ADM4852
Enable Time from Shutdown 4000 ns RL = 1 kΩ, CL = 15 pF, see Figure 23, ADM4852
Time to Shutdown 50 330 3000 ns ADM48521
1 The half-duplex device is put into shutdown mode by driving RE high and DE low. If these inputs are in this state for less than 50 ns, the device is guaranteed not to
enter shutdown mode. If the enable inputs are in this state for at least 3000 ns, the device is guaranteed to enter shutdown mode.
ADM4853/ADM4857 TIMING SPECIFICATIONS
VCC = 5 V ± 5%, TA = TMIN to TMAX, unless otherwise noted.
Table 6.
Parameter Min Typ Max Unit Test Conditions/Comments
DRIVER
Maximum Data Rate 10 Mbps
Propagation Delay, tPLH, tPHL 0 30 ns RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 20
Skew, tSKEW 10 ns RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 20
Rise/Fall Times, tR, tF 30 ns RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 20
Enable Time, tZH 35 ns RL = 500 Ω, CL = 100 pF, see Figure 21, ADM4853
Disable Time, tZL 35 ns RL = 500 Ω, CL = 15 pF, see Figure 21, ADM4853
Enable Time from Shutdown 4000 ns RL = 500 Ω, CL = 100 pF, see Figure 21, ADM4853
RECEIVER
Propagation Delay, tPLH, tPHL 55 190 ns CL = 15 pF, see Figure 22
Differential Skew, tSKEW 30 ns CL = 15 pF, see Figure 22
Enable Time 5 50 ns RL = 1 kΩ, CL = 15 pF, see Figure 23, ADM4853
Disable Time 20 50 ns RL = 1 kΩ, CL = 15 pF, see Figure 23, ADM4853
Enable Time from Shutdown 4000 ns RL = 1 kΩ, CL = 15 pF, see Figure 23, ADM4853
Time to Shutdown 50 330 3000 ns ADM48531
1 The half-duplex device is put into shutdown mode by driving RE high and DE low. If these inputs are in this state for less than 50 ns, the device is guaranteed not to
enter shutdown mode. If the enable inputs are in this state for at least 3000 ns, the device is guaranteed to enter shutdown mode.
ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/ADM4855/ADM4856/ADM4857
Rev. D | Page 6 of 16
ABSOLUTE MAXIMUM RATINGS
Table 7.
Parameter Rating
VCC to GND 6 V
Digital I/O Voltage (DE, RE, DI, RO) −0.3 V to VCC + 0.3 V
Driver Output/Receiver Input Voltage −9 V to +14 V
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +125°C
θJA Thermal Impedance
SOIC 110°C/W
LFCSP 62°C/W
MSOP 133.1°C/W
Lead Temperature
Soldering (10 sec) 300°C
Vapor Phase (60 sec) 215°C
Infrared (15 sec) 220°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/ADM4855/ADM4856/ADM4857
Rev. D | Page 7 of 16
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
RO 1VCC
8
DI 4GND5
ADM4850/
ADM4851/
ADM4852/
ADM4853
TOP VIEW
(Not to Scale)
RE 2B
7
04931-002
DE A63
PIN 1
INDICATOR
NOTES
1. THE EXPOSED PADDLE ON THE UNDERSIDE
OF THE PACKAGE SHOULD BE SOLDERED
TO THE GROUND PLANE TO INCREASE THE
RELIABILITY OF THE SOLDER JOINTS AND
TO MAXIMIZE THE THERMAL CAPABILITY OF
THE PACKAGE.
1RO
2RE
3DE
4DI
7B
8V
CC
TOP VIEW
(Not to Scale)
A
DM4850/ADM4851/
ADM4852/ADM4853
6A
5GND
04931-029
Figure 3. ADM4850/ADM4851/ADM4852/ADM4853 Pin Configuration,
SOIC and MSOP
Figure 4. ADM4850/ADM4851/ADM4852/ADM4853 Pin Configuration, LFCSP
Table 8. ADM4850/ADM4851/ADM4852/ADM4853 Pin Descriptions
Pin No. Mnemonic Description
1 RO Receiver Output. When RO is enabled, if (A − B) ≥ −30 mV, RO = high; if (A − B) ≤ −200 mV, RO = low.
2 RE Receiver Output Enable. A low level on this pin enables the receiver output, RO. A high level places RO
into a high impedance state.
3 DE Driver Output Enable. A high level on this pin enables the driver differential outputs, A and B. A low level
places them into a high impedance state.
4 DI Driver Input. When the driver is enabled, a logic low on DI forces A low and B high, whereas a logic high
on DI forces A high and B low.
5 GND Ground.
6 A Noninverting Receiver Input A/Noninverting Driver Output A.
7 B Inverting Receiver Input B/Inverting Driver Output B.
8 VCC 5 V Power Supply.
ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/ADM4855/ADM4856/ADM4857
Rev. D | Page 8 of 16
V
CC 1
A
8
GND
4
Y
5
ADM4854/
ADM4855/
ADM4856/
ADM4857
TOP VIEW
(Not to Scale)
RO
2
B
7
04931-003
DI Z
63
Figure 5. ADM4854/ADM4855/ADM4856/ADM4857 Pin Configuration, SOIC
Table 9. ADM4854/ADM4855/ADM4856/ADM4857 Pin Descriptions
Pin No. Mnemonic Description
1 VCC 5 V Power Supply.
2 RO Receiver Output. When RO is enabled, if (A − B) ≥ −30 mV, RO = high; if (A − B) ≤ −200 mV, RO = low.
3 DI Driver Input. When the driver is enabled, a logic low on DI forces Y low and Z high, whereas a logic high
on DI forces Y high and Z low.
4 GND Ground.
5 Y Noninverting Driver Output.
6 Z Inverting Driver Output.
7 B Inverting Receiver Input.
8 A Noninverting Receiver Input.
ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/ADM4855/ADM4856/ADM4857
Rev. D | Page 9 of 16
TYPICAL PERFORMANCE CHARACTERISTICS
400
0
50
100
150
200
250
300
350
–50 –25 0 25 50 75 100 125
04931-014
TEMPERATURE (°C)
UNLOADED SUPPLY CURRENT (μA)
ADM4853: DE = V
CC
ADM4853: DE = GND
ADM4850: DE = V
CC
ADM4850: DE = GND
Figure 6. Unloaded Supply Current vs. Temperature
04931-015
50
0
5
10
15
20
25
30
35
40
45
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
RECEIVER OUTPUT LOW VOLTAGE (V)
RECEIVER OUTPUT CURRENT (mA)
Figure 7. Receiver Output Current vs. Receiver Output Low Voltage
04931-016
5
0
–5
–10
–15
–20
3.5 4.0 4.5 5.0 5.5
RECEIVER OUTPUT HIGH VOLTAGE (V)
RECEIVER OUTPUT CURRENT (mA)
Figure 8. Receiver Output Current vs. Receiver Output High Voltage
04931-017
0.40
0.15
0.20
0.25
0.30
0.35
–50–250 255075100125
TEMPERATURE (
°
C)
OUTPUT LOW VOLTAGE (V)
Figure 9. Receiver Output Low Voltage vs. Temperature
04931-018
4.6
4.0
4.1
4.2
4.3
4.4
4.5
–50 –25 0 25 50 75 100 125
TEMPERATURE (°C)
OUTPUT HIGH VOLTAGE (V)
Figure 10. Receiver Output High Voltage vs. Temperature
04931-019
90
0
10
20
30
40
50
60
70
80
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
DIFFERENTIAL OUTPUT VOLTAGE (V)
DRIVER OUTPUT CURRENT (mA)
Figure 11. Driver Output Current vs. Differential Output Voltage
ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/ADM4855/ADM4856/ADM4857
Rev. D | Page 10 of 16
04931-020
120
100
80
60
40
20
0
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
OUTPUT VOLTAGE (V)
OUTPUT CURRENT (mA)
Figure 12. Output Current vs. Driver Output Low Voltage
04931-021
–10
–30
–50
–70
–90
–110
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
OUTPUT VOLTAGE (V)
OUTPUT CURRENT (mA)
Figure 13. Output Current vs. Driver Output High Voltage
450
0
50
100
150
200
250
300
350
400
–50 –25 0 25 50 75 100 125
04931-022
TEMPERATURE (°C)
PROPAGATION DELAY (ns)
ADM4855
ADM4853
Figure 14. Driver Propagation Delay vs. Temperature
800
700
600
500
400
300
200
100
0
–50 –25 0 25 50 75 100 125
04931-023
TEMPERATURE (°C)
PROPAGATION DELAY (ns)
ADM4855
ADM4853
Figure 15. Receiver Propagation Delay vs. Temperature
04931-024
CH1 1.00V
Ω
BW
CH2 1.00V
Ω
BW
M 400ns CH3 2.00V
CH3 2.00V
Ω
BW
CH4 5.00VΩ
3
2
4
Figure 16. Driver/Receiver Propagation Delay (ADM4855, 500 kbps)
04931-025
CH1 2.00VΩ
BW
CH2 1.00VΩM 50.0ns CH1 480mV
CH3 1.00VΩ
BW
CH4 5.00VΩ
1
2
4
Figure 17. Driver/Receiver Propagation Delay (ADM4857, 4 Mbps)
ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/ADM4855/ADM4856/ADM4857
Rev. D | Page 11 of 16
TEST CIRCUITS
04931-004
V
OD
R
RV
OC
Figure 18. Driver Voltage Measurement
04931-005
V
OD3
60Ω
375Ω
375Ω
V
TST
Figure 19. Driver Voltage Measurement over Common-Mode Voltage Range
04931-006
C
L1
C
L2
R
LDIFF
A
B
Figure 20. Driver Propagation Delay
04931-007
RL
VCC
S2
VOUT
DE IN
0V OR 3V
DE S1
B
A
CL
Figure 21. Driver Enable/Disable
04931-008
RE
B
A
C
L
V
OUT
Figure 22. Receiver Propagation Delay
RE
04931-009
R
L
V
CC
S2
V
OUT
S1
C
L
+1.5V
–1.5V
RE IN
Figure 23. Receiver Enable/Disable
ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/ADM4855/ADM4856/ADM4857
Rev. D | Page 12 of 16
SWITCHING CHARACTERISTICS
04931-010
3
V
0V
5V
0V
A
B
V
OD
t
R
t
F
t
PLH
t
PHL
90% POINT
10% POINT
90% POINT
10% POINT
t
SKEW
=
|t
PLH –
t
PHL
|
1/2V
OD
1.5V
1.5V
Figure 24. Driver Propagation Delay, Rise/Fall Timing
04931-011
t
SKEW
=
|t
PLH –
t
PHL
|
1.5V 1.5V
t
PLH
t
PHL
RO
V
OH
0V
A
, B 0V
V
OL
Figure 25. Receiver Propagation Delay
04931-012
A
, B
A
, B
DE
3V
0V
0V
V
OH
V
OL
1.5V
t
LZ
t
ZL
1.5V
t
HZ
t
ZH
2.3V
2.3V V
OL
+ 0.5V
V
OH
– 0.5V
Figure 26. Driver Enable/Disable Timing
04931-013
RO
RO
RE
3V
0V
0V
V
OH
V
OL
1.5V
t
LZ
t
ZL
1.5V
t
HZ
t
ZH
1.5V
1.5V V
OL
+ 0.5V
V
OH
– 0.5V
OUTPUT HIGH
OUTPUT LOW
Figure 27. Receiver Enable/Disable Timing
ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/ADM4855/ADM4856/ADM4857
Rev. D | Page 13 of 16
CIRCUIT DESCRIPTION
The ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/
ADM4855/ADM4856/ADM4857 are high speed RS-485/
RS-422 transceivers offering enhanced performance over
industry-standard devices. All devices in the family contain
one driver and one receiver, but offer a choice of performance
options. The devices feature true fail-safe operation, which
means that a logic high receiver output is guaranteed when
the receiver inputs are open-circuit or short-circuit, or when
they are connected to a terminated transmission line with all
drivers disabled (see the Fail-Safe Operation section).
SLEW-RATE CONTROL
The ADM4850 and ADM4854 feature a controlled slew-rate
driver that minimizes electromagnetic interference (EMI) and
reduces reflections caused by incorrectly terminated cables,
allowing error-free data transmission rates up to 115 kbps. The
ADM4851 and ADM4855 offer a higher limit on driver output
slew rate, allowing data transmission rates up to 500 kbps. The
driver slew rates of the ADM4852 and ADM4856 and the
ADM4853 and ADM4857 are not limited, offering data
transmission rates up to 2.5 Mbps and 10 Mbps, respectively.
RECEIVER INPUT FILTERING
The receivers of all the devices incorporate input hysteresis. In
addition, the receivers of the 115 kbps ADM4850 and ADM4854
and the 500 kbps ADM4851 and ADM4855 incorporate input
filtering. This enhances noise immunity with differential signals
that have very slow rise and fall times. However, it causes the
propagation delay to increase by 20%.
HALF-/FULL-DUPLEX OPERATION
Half-duplex operation implies that the transceiver can transmit
and receive, but it can do only one of these at any given time. How-
ever, with full-duplex operation, the transceiver can transmit and
receive simultaneously. The ADM4850/ADM4851/ADM4852/
ADM4853 are half-duplex devices in which the driver and the
receiver share differential bus terminals. The ADM4854/
ADM4855/ADM4856/ADM4857 are full-duplex devices that
have dedicated driver output and receiver input pins. Figure 28
and Figure 29 show typical half- and full-duplex topologies.
04931-026
RO
RE
DE
DI
D
R
A
B
MAXIMUM NUMBER OF TRANSCEIVERS ON BUS: 256
RO
RE
DE
DI D
RA
B
R
D
RO RE DE DI
AB
R
D
RO RE DE DI
AB
ADM4850/ADM4851/
ADM4852/ADM4853
ADM4850/ADM4851/
ADM4852/ADM4853
ADM4850/ADM4851/
ADM4852/ADM4853
ADM4850/ADM4851/
ADM4852/ADM4853
Figure 28. Typical Half-Duplex RS-485 Network Topology
04931-027
GND
RO
DI D
R
A
B
RO
DI
D
A
B
Z
Y
R
GND
V
CC
V
CC
Z
Y
ADM4854/ADM4855/
ADM4856/ADM4857
ADM4854/ADM4855/
ADM4856/ADM4857
Figure 29. Typical Full-Duplex Point-to-Point RS-485 Network Topology
ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/ADM4855/ADM4856/ADM4857
Rev. D | Page 14 of 16
HIGH RECEIVER INPUT IMPEDANCE
The input impedance of the ADM4850/ADM4851/ADM4852/
ADM4853/ADM4854/ADM4855/ADM4856/ADM4857 receivers
is 96 kΩ, which is eight times higher than the standard RS-485
unit load of 12 kΩ. This 96 kΩ impedance enables a standard
driver to drive 32 unit loads or to be connected to 256 ADM4850/
ADM4851/ADM4852/ADM4853/ADM4854/ADM4855/
ADM4856/ADM4857 receivers. An RS-485 bus, driven by a
single standard driver, can be connected to a combination of
ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/
ADM4855/ADM4856/ADM4857 devices and standard unit
load receivers, up to an equivalent of 32 standard unit loads.
THREE-STATE BUS CONNECTION
The half-duplex parts (ADM4850/ADM4851/ADM4852/
ADM4853) have a driver enable (DE) pin that enables the
driver outputs when taken high, or puts the driver outputs
into a high impedance state when taken low. Similarly, the
half-duplex devices have an active low receiver enable (RE) pin.
Taking this pin low enables the receiver, whereas taking it high
puts the receiver outputs into a high impedance state. This
allows several driver outputs to be connected to an RS-485 bus.
Note that only one driver should be enabled at a time, but that
many receivers can be enabled.
SHUTDOWN MODE
The ADM4850/ADM4851/ADM4852/ADM4853 have a low
power shutdown mode, which is enabled by taking RE high and
DE low. If shutdown mode is not used, the fact that DE is active
high and RE is active low offers a convenient way of switching the
device between transmit and receive by tying DE and RE together.
If DE is driven low and RE is driven high for less than 50 ns,
the devices are guaranteed not to enter shutdown mode. If DE
is driven low and RE is driven high for at least 3000 ns, the
devices are guaranteed to enter shutdown mode.
FAIL-SAFE OPERATION
The ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/
ADM4855/ADM4856/ADM4857 offer true fail-safe operation
while remaining fully compliant with the ±200 mV EIA/TIA-485
standard. A logic high receiver output is generated when the
receiver inputs are shorted together or open circuit, or when
they are connected to a terminated transmission line with all
drivers disabled. This is done by setting the receiver threshold
between −30 mV and −200 mV. If the differential receiver input
voltage (A − B) is greater than or equal to −30 mV, RO is logic
high. If (A − B) is less than or equal to −200 mV, RO is logic low.
In the case of a terminated bus with all transmitters disabled,
the differential input voltage of the receiver is pulled to 0 V by
the internal circuitry of the ADM4850/ADM4851/ADM4852/
ADM4853/ADM4854/ADM4855/ADM4856/ADM4857, which
results in a logic high with 30 mV minimum noise margin.
CURRENT LIMIT AND THERMAL SHUTDOWN
The ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/
ADM4855/ADM4856/ADM4857 incorporate two protection
mechanisms to guard the drivers against short circuits, bus con-
tention, or other fault conditions. The first is a current limiting
output stage, which protects the driver against short circuits over
the entire common-mode voltage range by limiting the output
current to approximately 70 mA. Under extreme fault conditions
where the current limit is not effective, a thermal shutdown circuit
puts the driver outputs into a high impedance state if the die
temperature exceeds 150°C, and does not turn them back on
until the temperature falls to 130°C.
ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/ADM4855/ADM4856/ADM4857
Rev. D | Page 15 of 16
OUTLINE DIMENSIONS
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-012-AA
012407-A
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
0.50 (0.0196)
0.25 (0.0099) 45°
8°
0°
1.75 (0.0688)
1.35 (0.0532)
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0040)
4
1
85
5.00 (0.1968)
4.80 (0.1890)
4.00 (0.1574)
3.80 (0.1497)
1.27 (0.0500)
BSC
6.20 (0.2441)
5.80 (0.2284)
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
Figure 30. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
COMPLIANT TO JEDEC STANDARDS MO-187-AA
6°
0°
0.80
0.55
0.40
4
8
1
5
0.65 BSC
0.40
0.25
1.10 MAX
3.20
3.00
2.80
COPLANARITY
0.10
0.23
0.09
3.20
3.00
2.80
5.15
4.90
4.65
PIN 1
IDENTIFIER
15° MAX
0.95
0.85
0.75
0.15
0.05
10-07-2009-B
Figure 31. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeter
s
0
90308-B
1
EXPOSED
PA D
(BOTTOM VIEW)
0.50
BSC
PIN 1
INDICATOR
0.50
0.40
0.30
TOP
VIEW
12° MAX 0.70 MAX
0.65 TYP
0.90 MAX
0.85 NOM 0.05 MAX
0.01 NOM
0.20 REF
1.89
1.74
1.59
4
1.60
1.45
1.30
3.25
3.00 SQ
2.75
2.95
2.75 SQ
2.55
58
PIN 1
INDICATOR
SEATING
PLANE
0.30
0.23
0.18
0.60 MAX
0.60 MAX
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
Figure 32. 8-Lead Lead Frame Chip Scale Package [LFCSP_VD]
3 mm × 3 mm Body, Very Thin, Dual Lead
(CP-8-2)
Dimensions shown in millimeters
ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/ADM4855/ADM4856/ADM4857
Rev. D | Page 16 of 16
ORDERING GUIDE
Model1 , 2 Temperature Range Package Description Package Option Branding
ADM4850ACPZ-REEL7 −40°C to +85°C 8-Lead LFCSP_VD CP-8-2 M8Q
ADM4850ARZ −40°C to +85°C 8-Lead SOIC_N R-8
ADM4850ARZ-REEL7 −40°C to +85°C 8-Lead SOIC_N R-8
ADM4850ARMZ −40°C to +85°C 8-Lead MSOP RM-8 M8Q
ADM4850ARMZ-REEL7 −40°C to +85°C 8-Lead MSOP RM-8 M8Q
ADM4851ARZ −40°C to +85°C 8-Lead SOIC_N R-8
ADM4851ARZ-REEL7 −40°C to +85°C 8-Lead SOIC_N R-8
ADM4852ACPZ-REEL7 −40°C to +85°C 8-Lead LFCSP_VD CP-8-2 M9M
ADM4852ARZ −40°C to +85°C 8-Lead SOIC_N R-8
ADM4852ARZ-REEL7 −40°C to +85°C 8-Lead SOIC_N R-8
ADM4853ACPZ-REEL7 −40°C to +85°C 8-Lead LFCSP_VD CP-8-2 F0B
ADM4853ARZ −40°C to +85°C 8-Lead SOIC_N R-8
ADM4853ARZ-REEL7 −40°C to +85°C 8-Lead SOIC_N R-8
ADM4853WARZ-RL7 −40°C to +85°C 8-Lead SOIC_N R-8
ADM4854ARZ −40°C to +85°C 8-Lead SOIC_N R-8
ADM4855AR-REEL7 −40°C to +85°C 8-Lead SOIC_N R-8
ADM4855ARZ −40°C to +85°C 8-Lead SOIC_N R-8
ADM4856ARZ −40°C to +85°C 8-Lead SOIC_N R-8
ADM4856ARZ-REEL7 −40°C to +85°C 8-Lead SOIC_N R-8
ADM4857ARZ −40°C to +85°C 8-Lead SOIC_N R-8
ADM4857ARZ-REEL7 −40°C to +85°C 8-Lead SOIC_N R-8
1 Z = RoHS Compliant Part.
2 W = qualified for automotive products.
AUTOMOTIVE PRODUCT
The ADM4853WARZ-RL7 model is available with controlled manufacturing to support the quality and reliability requirements of
automotive applications. Note that these automotive models may have specifications that differ from the commercial models; therefore,
designers should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for
use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and
to obtain the specific Automotive Reliability reports for this model.
©2004–2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04931-0-1/12(D)
