PIC18F8722 Family Data Sheet 64/80-Pin, 1-Mbit, Enhanced Flash Microcontrollers with 10-bit A/D and nanoWatt Technology 2004 Microchip Technology Inc. Preliminary DS39646B Note the following details of the code protection feature on Microchip devices: * Microchip products meet the specification contained in their particular Microchip Data Sheet. * Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. * There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. * Microchip is willing to work with the customer who is concerned about the integrity of their code. * Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB, PICMASTER, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2004, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona and Mountain View, California in October 2003. The Company's quality system processes and procedures are for its PICmicro(R) 8-bit MCUs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. DS39646B-page ii Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY 64/80-Pin, 1-Mbit, Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology Peripheral Highlights: Power-Managed Modes: * Two Master Synchronous Serial Port (MSSP) modules supporting 2/3/4-wire SPITM (all 4 modes) and I2CTM Master and Slave modes * Two Capture/Compare/PWM (CCP) modules * Three Enhanced Capture/Compare/PWM (ECCP) modules: - One, two or four PWM outputs - Selectable polarity - Programmable dead time - Auto-Shutdown and Auto-Restart * Two Enhanced Addressable USART modules: - Supports RS-485, RS-232 and LIN 1.2 - Auto-Wake-up on Start bit - Auto-Baud Detect * 10-bit, up to 16-channel Analog-to-Digital Converter module (A/D) - Auto-acquisition capability - Conversion available during Sleep * Dual analog comparators with input multiplexing * High-current sink/source 25 mA/25 mA * Four programmable external interrupts * Four input change interrupts * * * * * * * Run: CPU on, peripherals on Idle: CPU off, peripherals on Sleep: CPU off, peripherals off Idle mode currents down to 15 A typical Sleep current down to 0.2 A typical Timer1 Oscillator: 1.8 A, 32 kHz, 2V Watchdog Timer: 2.1 A Special Microcontroller Features: * C compiler optimized architecture: - Optional extended instruction set designed to optimize re-entrant code * 100,000 erase/write cycle Enhanced Flash program memory typical * 1,000,000 erase/write cycle Data EEPROM memory typical * Flash/Data EEPROM Retention: 100 years typical * Self-programmable under software control * Priority levels for interrupts * 8 x 8 Single-Cycle Hardware Multiplier * Extended Watchdog Timer (WDT): - Programmable period from 4 ms to 131s * Single-Supply In-Circuit Serial ProgrammingTM (ICSPTM) via two pins * In-Circuit Debug (ICD) via two pins * Wide operating voltage range: 2.0V to 5.5V * Fail-Safe Clock Monitor * Two-Speed Oscillator Start-up * nanoWatt Technology External Memory Interface (PIC18F8527/8622/8627/8722 only): EUSART Comparators Timers 8/16-bit External Bus * Address capability of up to 2 Mbytes * 8-bit or 16-bit interface * 8, 12, 16 and 20-bit Address modes PIC18F6527 48K 24576 3936 1024 54 12 2/3 2 Y Y 2 2 2/3 N PIC18F6622 64K 32768 3936 1024 54 12 2/3 2 Y Y 2 2 2/3 N PIC18F6627 96K 49152 3936 1024 54 12 2/3 2 Y Y 2 2 2/3 N PIC18F6722 128K 65536 3936 1024 54 12 2/3 2 Y Y 2 2 2/3 N PIC18F8527 48K 24576 3936 1024 70 16 2/3 2 Y Y 2 2 2/3 Y PIC18F8622 64K 32768 3936 1024 70 16 2/3 2 Y Y 2 2 2/3 Y PIC18F8627 96K 49152 3936 1024 70 16 2/3 2 Y Y 2 2 2/3 Y PIC18F8722 128K 65536 3936 1024 70 16 2/3 2 Y Y 2 2 2/3 Y Program Memory Device Data Memory MSSP Flash # Single-Word SRAM EEPROM (bytes) Instructions (bytes) (bytes) 2004 Microchip Technology Inc. I/O 10-bit CCP/ A/D ECCP (ch) (PWM) Preliminary SPITM Master I2CTM DS39646B-page 1 PIC18F8722 FAMILY Pin Diagrams RD7/PSP7/SS2 RD6/PSP6/SCK2/SCL2 RD5/PSP5/SDI2/SDA2 RD4/PSP4/SDO2 RD3/PSP3 RD2/PSP2 RD1/PSP1 VSS VDD RD0/PSP0 RE7/ECCP2(1)/P2A(1) RE6/P1B RE5/P1C RE4/P3B RE2/CS/P2B RE3/P3C 64-Pin TQFP 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 RE1/WR/P2C RE0/RD/P2D RG0/ECCP3/P3A RG1/TX2/CK2 RF4/AN9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 RF3/AN8 RF2/AN7/C1OUT 15 16 RG2/RX2/DT2 RG3/CCP4/P3D RG5/MCLR/VPP RG4/CCP5/P1D VSS VDD RF7/SS1 RF6/AN11 RF5/AN10/CVREF 48 47 46 45 44 43 42 41 40 PIC18F6527 PIC18F6622 PIC18F6627 PIC18F6722 39 38 37 36 35 34 33 RB0/INT0 RB1/INT1 RB2/INT2 RB3/INT3 RB4/KBI0 RB5/KBI1/PGM RB6/KBI2/PGC VSS OSC2/CLKO/RA6 OSC1/CLKI/RA7 VDD RB7/KBI3/PGD RC5/SDO1 RC4/SDI1/SDA1 RC3/SCK1/SCL1 RC2/ECCP1/P1A Note 1: DS39646B-page 2 RC7/RX1/DT1 RC6/TX1/CK1 RC0/T1OSO/T13CKI RA4/T0CKI RC1/T1OSI/ECCP2(1)/P2A(1) RA5/AN4/HLVDIN VDD VSS RA0/AN0 RA1/AN1 RA2/AN2/VREF- AVSS RA3/AN3/VREF+ AVDD RF0/AN5 RF1/AN6/C2OUT 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 The ECCP2/P2A pin placement is determined by the CCP2MX configuration bit. Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY Pin Diagrams (Continued) RE5/AD13/P1C(2) RE6/AD14/P1B(2) RE7/AD15/ECCP2(1)/P2A(1) RD0/AD0/PSP0 VDD VSS RD1/AD1/PSP1 RD2/AD2/PSP2 RD3/AD3/PSP3 RD4/AD4/PSP4/SDO2 RD5/AD5/PSP5/SDI2/SDA2 RD6/AD6/PSP6/SCK2/SCL2 RD7/AD7/PSP7/SS2 RJ0/ALE RJ1/OE RH1/A17 RH0/A16 RE2/AD10/CS/P2B RE3/AD11/P3C(2) RE4/AD12/P3B(2) 80-Pin TQFP 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 RH2/A18 RH3/A19 RE1/AD9/WR/P2C RE0/AD8/RD/P2D RG0/ECCP3/P3A RG1/TX2/CK2 RG2/RX2/DT2 RG3/CCP4/P3D RG5/MCLR/VPP RG4/CCP5/P1D VSS VDD RF7/SS1 RF6/AN11 RF5/AN10/CVREF RF4/AN9 RF3/AN8 RF2/AN7/C1OUT RH7/AN15/P1B(2) RH6/AN14/P1C(2) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 PIC18F8527 PIC18F8622 PIC18F8627 PIC18F8722 RJ2/WRL RJ3/WRH RB0/INT0 RB1/INT1 RB2/INT2 RB3/INT3/ECCP2(1)/P2A(1) RB4/KBI0 RB5/KBI1/PGM RB6/KBI2/PGC VSS OSC2/CLKO/RA6 OSC1/CLKI/RA7 VDD RB7/KBI3/PGD RC5/SDO1 RC4/SDI1/SDA1 RC3/SCK1/SCL1 RC2/ECCP1/P1A RJ7/UB RJ6/LB Note 1: 2: RJ4/BA0 RJ5/CE RC0/T1OSO/T13CKI RC6/TX1/CK1 RC7/RX1/DT1 RA5/AN4/HLVDIN RA4/T0CKI RC1/T1OSI/ECCP2(1)/P2A(1) RA1/AN1 RA0/AN0 VSS VDD RF1/AN6/C2OUT RF0/AN5 AVDD AVSS RA3/AN3/VREF+ RA2/AN2/VREF- RH5/AN13/P3B(2) RH4/AN12/P3C(2) 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 The ECCP2/P2A pin placement is determined by the CCP2MX configuration bit and Processor mode settings. P1B, P1C, P3B and P3C pin placement is determined by the ECCPMX configuration bit. 2004 Microchip Technology Inc. Preliminary DS39646B-page 3 PIC18F8722 FAMILY Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 7 2.0 Oscillator Configurations ............................................................................................................................................................ 31 3.0 Power-Managed Modes ............................................................................................................................................................. 41 4.0 Reset .......................................................................................................................................................................................... 49 5.0 Memory Organization ................................................................................................................................................................. 63 6.0 Flash Program Memory .............................................................................................................................................................. 87 7.0 External Memory Bus ................................................................................................................................................................. 97 8.0 Data EEPROM Memory ........................................................................................................................................................... 111 9.0 8 x 8 Hardware Multiplier.......................................................................................................................................................... 117 10.0 Interrupts .................................................................................................................................................................................. 119 11.0 I/O Ports ................................................................................................................................................................................... 135 12.0 Timer0 Module ......................................................................................................................................................................... 161 13.0 Timer1 Module ......................................................................................................................................................................... 165 14.0 Timer2 Module ......................................................................................................................................................................... 171 15.0 Timer3 Module ......................................................................................................................................................................... 173 16.0 Timer4 Module ......................................................................................................................................................................... 177 17.0 Capture/Compare/PWM (CCP) Modules ................................................................................................................................. 179 18.0 Enhanced Capture/Compare/PWM (ECCP) Module................................................................................................................ 187 19.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 205 20.0 Enhanced Universal Synchronous Receiver Transmitter (EUSART) ....................................................................................... 247 21.0 10-Bit Analog-to-Digital Converter (A/D) Module ..................................................................................................................... 271 22.0 Comparator Module.................................................................................................................................................................. 281 23.0 Comparator Voltage Reference Module ................................................................................................................................... 287 24.0 High/Low-Voltage Detect (HLVD)............................................................................................................................................. 291 25.0 Special Features of the CPU .................................................................................................................................................... 297 26.0 Instruction Set Summary .......................................................................................................................................................... 321 27.0 Development Support............................................................................................................................................................... 371 28.0 Electrical Characteristics .......................................................................................................................................................... 377 29.0 DC and AC Characteristics Graphs and Tables ....................................................................................................................... 421 30.0 Packaging Information.............................................................................................................................................................. 423 Appendix A: Revision History............................................................................................................................................................. 427 Appendix B: Device Differences......................................................................................................................................................... 427 Appendix C: Conversion Considerations ........................................................................................................................................... 428 Appendix D: Migration From Baseline to Enhanced Devices............................................................................................................. 428 Appendix E: Migration From Mid-Range to Enhanced Devices ......................................................................................................... 429 Appendix F: Migration From High-End to Enhanced Devices............................................................................................................ 429 Index .................................................................................................................................................................................................. 431 On-Line Support................................................................................................................................................................................. 443 Systems Information and Upgrade Hot Line ...................................................................................................................................... 443 Reader Response .............................................................................................................................................................................. 444 PIC18F8722 Family Product Identification System............................................................................................................................ 445 DS39646B-page 4 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@.microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: * Microchip's Worldwide Web site; http://www.microchip.com * Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. 2004 Microchip Technology Inc. Preliminary DS39646B-page 5 PIC18F8722 FAMILY NOTES: DS39646B-page 6 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY 1.0 DEVICE OVERVIEW 1.1.2 This document contains device specific information for the following devices: * PIC18F6527 * PIC18LF6527 * PIC18F6622 * PIC18LF6622 * PIC18F6627 * PIC18LF6627 * PIC18F6722 * PIC18LF6722 * PIC18F8527 * PIC18LF8527 * PIC18F8622 * PIC18LF8622 * PIC18F8627 * PIC18LF8627 * PIC18F8722 * PIC18LF8722 This family offers the advantages of all PIC18 microcontrollers - namely, high computational performance at an economical price - with the addition of highendurance, Enhanced Flash program memory. On top of these features, the PIC18F8722 family introduces design enhancements that make these microcontrollers a logical choice for many high-performance, power sensitive applications. 1.1 1.1.1 New Core Features nanoWatt TECHNOLOGY All of the devices in the PIC18F8722 family incorporate a range of features that can significantly reduce power consumption during operation. Key items include: * Alternate Run Modes: By clocking the controller from the Timer1 source or the internal oscillator block, power consumption during code execution can be significantly reduced. * Multiple Idle Modes: The controller can also run with its CPU core disabled but the peripherals still active. In these states, power consumption can be reduced even further. * On-the-fly Mode Switching: The powermanaged modes are invoked by user code during operation, allowing the user to incorporate powersaving ideas into their application's software design. * Low Consumption in Key Modules: The power requirements for both Timer1 and the Watchdog Timer are minimized. See Section 28.0 "Electrical Characteristics" for values. 2004 Microchip Technology Inc. EXPANDED MEMORY The PIC18F8722 family provides ample room for application code and includes members with 48, 64, 96 or 128 Kbytes of code space. * Data RAM and Data EEPROM: The PIC18F8722 family also provides plenty of room for application data. The devices have 3936 bytes of data RAM, as well as 1024 bytes of data EEPROM, for long term retention of nonvolatile data. * Memory Endurance: The Enhanced Flash cells for both program memory and data EEPROM are rated to last for many thousands of erase/write cycles, up to 100,000 for program memory and 1,000,000 for EEPROM. Data retention without refresh is conservatively estimated to be greater than 40 years. 1.1.3 MULTIPLE OSCILLATOR OPTIONS AND FEATURES All of the devices in the PIC18F8722 family offer ten different oscillator options, allowing users a wide range of choices in developing application hardware. These include: * Four Crystal modes, using crystals or ceramic resonators * Two External Clock modes, offering the option of using two pins (oscillator input and a divide-by-4 clock output) or one pin (oscillator input, with the second pin reassigned as general I/O) * Two External RC Oscillator modes with the same pin options as the External Clock modes * An internal oscillator block which provides an 8 MHz clock and an INTRC source (approximately 31 kHz), as well as a range of 6 user selectable clock frequencies, between 125 kHz to 4 MHz, for a total of 8 clock frequencies. This option frees the two oscillator pins for use as additional general purpose I/O. * A Phase Lock Loop (PLL) frequency multiplier, available to both the high-speed crystal and internal oscillator modes, which allows clock speeds of up to 40 MHz. Used with the internal oscillator, the PLL gives users a complete selection of clock speeds, from 31 kHz to 32 MHz - all without using an external crystal or clock circuit. Preliminary DS39646B-page 7 PIC18F8722 FAMILY Besides its availability as a clock source, the internal oscillator block provides a stable reference source that gives the family additional features for robust operation: * Fail-Safe Clock Monitor: This option constantly monitors the main clock source against a reference signal provided by the internal oscillator. If a clock failure occurs, the controller is switched to the internal oscillator block, allowing for continued low-speed operation or a safe application shutdown. * Two-Speed Start-up: This option allows the internal oscillator to serve as the clock source from Power-on Reset, or wake-up from Sleep mode, until the primary clock source is available. 1.1.4 EXTERNAL MEMORY INTERFACE In the unlikely event that 128 Kbytes of program memory is inadequate for an application, the PIC18F8527/8622/8627/8722 members of the family also implement an external memory interface. This allows the controller's internal program counter to address a memory space of up to 2 Mbytes, permitting a level of data access that few 8-bit devices can claim. With the addition of new operating modes, the external memory interface offers many new options, including: * Operating the microcontroller entirely from external memory * Using combinations of on-chip and external memory, up to the 2-Mbyte limit * Using external Flash memory for reprogrammable application code or large data tables * Using external RAM devices for storing large amounts of variable data 1.1.5 EASY MIGRATION Regardless of the memory size, all devices share the same rich set of peripherals, allowing for a smooth migration path as applications grow and evolve. The consistent pinout scheme used throughout the entire family also aids in migrating to the next larger device. This is true when moving between the 64-pin members, between the 80-pin members, or even jumping from 64-pin to 80-pin devices. DS39646B-page 8 1.2 Other Special Features * Communications: The PIC18F8722 family incorporates a range of serial communication peripherals, including 2 independent Enhanced USARTs and 2 Master SSP modules capable of both SPI and I2C (Master and Slave) modes of operation. Also, one of the general purpose I/O ports can be reconfigured as an 8-bit Parallel Slave Port for direct processor-to-processor communications. * CCP Modules: All devices in the family incorporate two Capture/Compare/PWM (CCP) modules and three Enhanced CCP (ECCP) modules to maximize flexibility in control applications. Up to four different time bases may be used to perform several different operations at once. Each of the three ECCP modules offer up to four PWM outputs, allowing for a total of 12 PWMs. The ECCPs also offer many beneficial features, including polarity selection, Programmable Dead-Time, Auto-Shutdown and Restart and Half-Bridge and Full-Bridge Output modes. * Self-Programmability: These devices can write to their own program memory spaces under internal software control. By using a bootloader routine located in the protected Boot Block at the top of program memory, it becomes possible to create an application that can update itself in the field. * Extended Instruction Set: The PIC18F8722 family introduces an optional extension to the PIC18 instruction set, which adds 8 new instructions and an Indexed Addressing mode. This extension, enabled as a device configuration option, has been specifically designed to optimize re-entrant application code originally developed in high-level languages, such as C. * 10-bit A/D Converter: This module incorporates programmable acquisition time, allowing for a channel to be selected and a conversion to be initiated without waiting for a sampling period and thus, reduce code overhead. * Extended Watchdog Timer (WDT): This enhanced version incorporates a 16-bit prescaler, allowing an extended time-out range that is stable across operating voltage and temperature. See Section 28.0 "Electrical Characteristics" for time-out periods. Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY 1.3 Details on Individual Family Members All other features for devices in this family are identical. These are summarized in Table 1-2 and Table 1-2. The pinouts for all devices are listed in Table 1-3 and Table 1-4. Devices in the PIC18F8722 family are available in 64-pin and 80-pin packages. Block diagrams for the two groups are shown in Figure 1-1 and Figure 1-2. Like all Microchip PIC18 devices, members of the PIC18F8722 family are available as both standard and low-voltage devices. Standard devices with Enhanced Flash memory, designated with an "F" in the part number (such as PIC18F6627), accommodate an operating VDD range of 4.2V to 5.5V. Low-voltage parts, designated by "LF" (such as PIC18LF6627), function over an extended VDD range of 2.0V to 5.5V. The devices are differentiated from each other in five ways: 1. 2. 3. 4. Flash program memory (48 Kbytes for PIC18F6527/8527 devices, 64 Kbytes for PIC18F6622/8622 devices, 96 Kbytes for PIC18F6627/8627 devices and 128 Kbytes for PIC18F6722/8722). A/D channels (12 for 64-pin devices, 16 for 80-pin devices). I/O ports (7 bidirectional ports on 64-pin devices, 9 bidirectional ports on 80-pin devices). External Memory Bus, configurable for 8 and 16-bit operation, is available on PIC18F8527/ 8622/8627/8722 devices. TABLE 1-1: DEVICE FEATURES (PIC18F6527/6622/6627/6722) Features PIC18F6527 PIC18F6622 PIC18F6627 PIC18F6722 Operating Frequency DC - 40 MHz DC - 40 MHz DC - 40 MHz DC - 40 MHz Program Memory (Bytes) 48K 64K 96K 128K Program Memory (Instructions) 24576 32768 49152 65536 Data Memory (Bytes) 3936 3936 3936 3936 Data EEPROM Memory (Bytes) 1024 1024 1024 1024 Interrupt Sources 28 28 28 28 Ports A, B, C, D, E, F, G Ports A, B, C, D, E, F, G Ports A, B, C, D, E, F, G Ports A, B, C, D, E, F, G Timers 5 5 5 5 Capture/Compare/PWM Modules 2 2 2 2 Enhanced Capture/Compare/ PWM Modules 3 3 3 3 I/O Ports Enhanced USART Serial Communications 2 2 2 2 MSSP, Enhanced USART MSSP, Enhanced USART MSSP, Enhanced USART MSSP, Enhanced USART Parallel Communications (PSP) Yes Yes Yes Yes 10-bit Analog-to-Digital Module 12 Input Channels 12 Input Channels 12 Input Channels 12 Input Channels Resets (and Delays) POR, BOR, POR, BOR, POR, BOR, POR, BOR, RESET Instruction, RESET Instruction, RESET Instruction, RESET Instruction, Stack Full, Stack Stack Full, Stack Stack Full, Stack Stack Full, Stack Underflow (PWRT, OST), Underflow (PWRT, OST), Underflow (PWRT, OST), Underflow (PWRT, OST), MCLR (optional), WDT MCLR (optional), WDT MCLR (optional), WDT MCLR (optional), WDT Programmable High/Low-Voltage Detect Yes Yes Yes Yes Programmable Brown-out Reset Yes Yes Yes Yes 75 Instructions; 83 with Extended Instruction Set enabled 75 Instructions; 83 with Extended Instruction Set enabled 75 Instructions; 83 with Extended Instruction Set enabled 75 Instructions; 83 with Extended Instruction Set enabled 64-pin TQFP 64-pin TQFP 64-pin TQFP 64-pin TQFP Instruction Set Packages 2004 Microchip Technology Inc. Preliminary DS39646B-page 9 PIC18F8722 FAMILY TABLE 1-2: DEVICE FEATURES (PIC18F8527/8622/8627/8722) Features PIC18F8527 PIC18F8622 PIC18F8627 PIC18F8722 DC - 40 MHz DC - 40 MHz DC - 40 MHz DC - 40 MHz 48K 64K 96K 128K Program Memory (Instructions) 24576 32768 49152 65536 Data Memory (Bytes) 3936 3936 3936 3936 Data EEPROM Memory (Bytes) 1024 1024 1024 1024 29 29 29 29 Ports A, B, C, D, E, F, G, H, J Ports A, B, C, D, E, F, G, H, J Ports A, B, C, D, E, F, G, H, J Ports A, B, C, D, E, F, G, H, J Timers 5 5 5 5 Capture/Compare/PWM Modules 2 2 2 2 Enhanced Capture/Compare/ PWM Modules 3 3 3 3 Operating Frequency Program Memory (Bytes) Interrupt Sources I/O Ports Enhanced USART Serial Communications Parallel Communications (PSP) 10-bit Analog-to-Digital Module Resets (and Delays) 2 2 2 2 MSSP, Enhanced USART MSSP, Enhanced USART MSSP, Enhanced USART MSSP, Enhanced USART Yes Yes Yes Yes 16 Input Channels 16 Input Channels 16 Input Channels 16 Input Channels POR, BOR, POR, BOR, POR, BOR, POR, BOR, RESET Instruction, RESET Instruction, RESET Instruction, RESET Instruction, Stack Full, Stack Stack Full, Stack Stack Full, Stack Stack Full, Stack Underflow (PWRT, OST), Underflow (PWRT, OST), Underflow (PWRT, OST), Underflow (PWRT, OST), MCLR (optional), WDT MCLR (optional), WDT MCLR (optional), WDT MCLR (optional), WDT Programmable High/Low-Voltage Detect Yes Yes Yes Yes Programmable Brown-out Reset Yes Yes Yes Yes 75 Instructions; 83 with Extended Instruction Set enabled 75 Instructions; 83 with Extended Instruction Set enabled 75 Instructions; 83 with Extended Instruction Set enabled 75 Instructions; 83 with Extended Instruction Set enabled 80-pin TQFP 80-pin TQFP 80-pin TQFP 80-pin TQFP Instruction Set Packages DS39646B-page 10 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY FIGURE 1-1: PIC18F6527/6622/6627/6722 (64-PIN) BLOCK DIAGRAM Data Bus<8> Table Pointer<21> RA0:RA7(1) Data Memory (3.9 Kbytes) PCLATU PCLATH 21 PORTA Data Latch 8 8 inc/dec logic Address Latch 20 PCU PCH PCL Program Counter 12 Data Address<12> PORTB RB0:RB7(1) 31 Level Stack 4 BSR Address Latch Program Memory (48/64/96/128 Kbytes) STKPTR 4 Access Bank 12 FSR0 FSR1 FSR2 12 PORTC Data Latch RC0:RC7(1) inc/dec logic 8 Table Latch Address Decode ROM Latch Instruction Bus <16> PORTD RD0:RD7(1) IR 8 Instruction Decode and Control State Machine Control Signals PRODH PRODL 8 x 8 Multiply 3 OSC1(3) OSC2 Internal Oscillator Block (3) T1OSI INTRC Oscillator T1OSO 8 MHz Oscillator MCLR(2) VDD, VSS Power-up Timer 8 BITOP W 8 8 8 Oscillator Start-up Timer Power-on Reset Single-Supply Programming In-Circuit Debugger 8 RF0:RF7(1) ALU<8> Watchdog Timer Brown-out Reset Fail-Safe Clock Monitor Precision Band Gap Reference 8 PORTG RG0:RG5(1) ADC 10-bit Timer0 Timer1 Timer2 Timer3 Timer4 ECCP1 ECCP2 ECCP3 CCP4 CCP5 EUSART1 EUSART2 1: PORTF 8 BOR HLVD Note PORTE RE0:RE7(1) Comparators MSSP1 MSSP2 See Table 1-3 for I/O port pin descriptions. 2: RG5 is only available when MCLR functionality is disabled. 3: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O. Refer to Section 2.0 "Oscillator Configurations" for additional information. 2004 Microchip Technology Inc. Preliminary DS39646B-page 11 PIC18F8722 FAMILY FIGURE 1-2: PIC18F8527/8622/8627/8722 (80-PIN) BLOCK DIAGRAM Data Bus<8> Table Pointer<21> 8 inc/dec logic 21 PORTA Data Latch 8 RA0:RA7(1) Data Memory (3.9 Kbytes) PCLATU PCLATH Address Latch 20 PCU PCH PCL Program Counter PORTB RB0:RB7(1) 12 Data Address<12> 31 Level Stack 4 System Bus Interface Address Latch Program Memory (48/64/96/128 Kbytes) 12 BSR STKPTR 4 PORTC Access Bank FSR0 FSR1 FSR2 RC0:RC7(1) 12 Data Latch inc/dec logic 8 Table Latch PORTD RD0:RD7(1) Address Decode ROM Latch Instruction Bus <16> PORTE IR RE0:RE7(1) AD15:AD0, A19:A16 (Multiplexed with PORTD, PORTE and PORTH) 8 RF0:RF7(1) 3 8 x 8 Multiply 8 W BITOP 8 OSC1(3) T1OSI INTRC Oscillator T1OSO 8 MHz Oscillator 8 Power-up Timer 8 Oscillator Start-up Timer 8 ALU<8> Power-on Reset RH0:RH7(1) Watchdog Timer MCLR(2) Single-Supply Programming VDD, VSS In-Circuit Debugger Precision Band Gap Reference Brown-out Reset Fail-Safe Clock Monitor PORTJ RJ0:RJ7(1) ADC 10-bit Timer0 Timer1 Timer2 Timer3 Timer4 ECCP1 ECCP2 ECCP3 CCP4 CCP5 EUSART1 EUSART2 1: PORTH 8 BOR HLVD Note PORTG 8 RG0:RG5(1) Internal Oscillator Block OSC2(3) PORTF PRODH PRODL Instruction Decode & Control State Machine Control Signals Comparators MSSP1 MSSP2 See Table 1-4 for I/O port pin descriptions. 2: RG5 is only available when MCLR functionality is disabled. 3: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O. Refer to Section 2.0 "Oscillator Configurations" for additional information. DS39646B-page 12 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY TABLE 1-3: PIC18F6527/6622/6627/6722 PINOUT I/O DESCRIPTIONS Pin Number Pin Name TQFP RG5/MCLR/VPP RG5 MCLR I I ST ST P 39 I CLKI I RA7 OSC2/CLKO/RA6 OSC2 Buffer Type 7 VPP OSC1/CLKI/RA7 OSC1 Pin Type I/O Description Master Clear (input) or programming voltage (input). Digital input. Master Clear (Reset) input. This pin is an active-low Reset to the device. Programming voltage input. Oscillator crystal or external clock input. Oscillator crystal input or external clock source input. ST buffer when configured in RC mode, CMOS otherwise. CMOS External clock source input. Always associated with pin function OSC1. (See related OSC1/CLKI, OSC2/CLKO pins.) TTL General purpose I/O pin. ST 40 O -- CLKO O -- RA6 I/O TTL Oscillator crystal or clock output. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. In RC mode, OSC2 pin outputs CLKO, which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. General purpose I/O pin. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output = I2C/SMBus input buffer P = Power I2CTM Note 1: Default assignment for ECCP2 when configuration bit CCP2MX is set. 2: Alternate assignment for ECCP2 when configuration bit CCP2MX is cleared. 2004 Microchip Technology Inc. Preliminary DS39646B-page 13 PIC18F8722 FAMILY TABLE 1-3: PIC18F6527/6622/6627/6722 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP Pin Type Buffer Type Description PORTA is a bidirectional I/O port. RA0/AN0 RA0 AN0 24 RA1/AN1 RA1 AN1 23 RA2/AN2/VREFRA2 AN2 VREF- 22 RA3/AN3/VREF+ RA3 AN3 VREF+ 21 RA4/T0CKI RA4 T0CKI 28 RA5/AN4/HLVDIN RA5 AN4 HLVDIN 27 I/O I TTL Analog Digital I/O. Analog input 0. I/O I TTL Analog Digital I/O. Analog input 1. I/O I I TTL Analog Analog Digital I/O. Analog input 2. A/D reference voltage (low) input. I/O I I TTL Analog Analog Digital I/O. Analog input 3. A/D reference voltage (high) input. I/O I ST ST I/O I I TTL Analog Analog Digital I/O. Timer0 external clock input. Digital I/O. Analog input 4. High/Low-Voltage Detect input. RA6 See the OSC2/CLKO/RA6 pin. RA7 See the OSC1/CLKI/RA7 pin. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output = I2C/SMBus input buffer P = Power I2CTM Note 1: Default assignment for ECCP2 when configuration bit CCP2MX is set. 2: Alternate assignment for ECCP2 when configuration bit CCP2MX is cleared. DS39646B-page 14 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY TABLE 1-3: PIC18F6527/6622/6627/6722 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP Pin Type Buffer Type Description PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs. RB0/INT0/FLT0 RB0 INT0 FLT0 48 RB1/INT1 RB1 INT1 47 RB2/INT2 RB2 INT2 46 RB3/INT3 RB3 INT3 45 RB4/KBI0 RB4 KBI0 44 RB5/KBI1/PGM RB5 KBI1 PGM 43 RB6/KBI2/PGC RB6 KBI2 PGC 42 RB7/KBI3/PGD RB7 KBI3 PGD 37 I/O I I TTL ST ST Digital I/O. External interrupt 0. PWM Fault input for ECCPx. I/O I TTL ST Digital I/O. External interrupt 1. I/O I TTL ST Digital I/O. External interrupt 2. I/O I TTL ST Digital I/O. External interrupt 3. I/O I TTL TTL Digital I/O. Interrupt-on-change pin. I/O I I/O TTL TTL ST Digital I/O. Interrupt-on-change pin. Low-Voltage ICSPTM Programming enable pin. I/O I I/O TTL TTL ST Digital I/O. Interrupt-on-change pin. In-Circuit Debugger and ICSP programming clock pin. I/O I I/O TTL TTL ST Digital I/O. Interrupt-on-change pin. In-Circuit Debugger and ICSP programming data pin. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output = I2C/SMBus input buffer P = Power I2CTM Note 1: Default assignment for ECCP2 when configuration bit CCP2MX is set. 2: Alternate assignment for ECCP2 when configuration bit CCP2MX is cleared. 2004 Microchip Technology Inc. Preliminary DS39646B-page 15 PIC18F8722 FAMILY TABLE 1-3: PIC18F6527/6622/6627/6722 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP Pin Type Buffer Type Description PORTC is a bidirectional I/O port. RC0/T1OSO/T13CKI RC0 T1OSO T13CKI 30 RC1/T1OSI/ECCP2/P2A RC1 T1OSI ECCP2(1) 29 P2A(1) RC2/ECCP1/P1A RC2 ECCP1 I/O O I ST -- ST I/O I I/O ST CMOS ST O -- I/O I/O ST ST O -- Digital I/O. Enhanced Capture 1 input/Compare 1 output/ PWM 1 output. ECCP1 PWM output A. I/O I/O I/O ST ST ST Digital I/O. Synchronous serial clock input/output for SPITM mode. Synchronous serial clock input/output for I2CTM mode. I/O I I/O ST ST ST Digital I/O. SPI data in. I2C data I/O. I/O O ST -- Digital I/O. SPI data out. I/O O I/O ST -- ST Digital I/O. EUSART1 asynchronous transmit. EUSART1 synchronous clock (see related RX1/DT1). I/O I I/O ST ST ST Digital I/O. EUSART1 asynchronous receive. EUSART1 synchronous data (see related TX1/CK1). Digital I/O. Timer1 oscillator output. Timer1/Timer3 external clock input. Digital I/O. Timer1 oscillator input. Enhanced Capture 2 input/Compare 2 output/ PWM 2 output. ECCP2 PWM output A. 33 P1A RC3/SCK1/SCL1 RC3 SCK1 SCL1 34 RC4/SDI1/SDA1 RC4 SDI1 SDA1 35 RC5/SDO1 RC5 SDO1 36 RC6/TX1/CK1 RC6 TX1 CK1 31 RC7/RX1/DT1 RC7 RX1 DT1 32 Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output = I2C/SMBus input buffer P = Power I2CTM Note 1: Default assignment for ECCP2 when configuration bit CCP2MX is set. 2: Alternate assignment for ECCP2 when configuration bit CCP2MX is cleared. DS39646B-page 16 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY TABLE 1-3: PIC18F6527/6622/6627/6722 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP Pin Type Buffer Type Description PORTD is a bidirectional I/O port. RD0/PSP0 RD0 PSP0 58 RD1/PSP1 RD1 PSP1 55 RD2/PSP2 RD2 PSP2 54 RD3/PSP3 RD3 PSP3 53 RD4/PSP4/SDO2 RD4 PSP4 SDO2 52 RD5/PSP5/SDI2/SDA2 RD5 PSP5 SDI2 SDA2 51 RD6/PSP6/SCK2/SCL2 RD6 PSP6 SCK2 SCL2 50 RD7/PSP7/SS2 RD7 PSP7 SS2 49 I/O I/O ST TTL Digital I/O. Parallel Slave Port data. I/O I/O ST TTL Digital I/O. Parallel Slave Port data. I/O I/O ST TTL Digital I/O. Parallel Slave Port data. I/O I/O ST TTL Digital I/O. Parallel Slave Port data. I/O I/O O ST TTL -- Digital I/O. Parallel Slave Port data. SPI data out. I/O I/O I I/O ST TTL ST I2C/SMB Digital I/O. Parallel Slave Port data. SPITM data in. I2CTM data I/O. I/O I/O I/O I/O ST TTL ST I2C/SMB Digital I/O. Parallel Slave Port data. Synchronous serial clock input/output for SPI mode. Synchronous serial clock input/output for I2C mode. I/O I/O I ST TTL TTL Digital I/O. Parallel Slave Port data. SPI slave select input. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output = I2C/SMBus input buffer P = Power I2CTM Note 1: Default assignment for ECCP2 when configuration bit CCP2MX is set. 2: Alternate assignment for ECCP2 when configuration bit CCP2MX is cleared. 2004 Microchip Technology Inc. Preliminary DS39646B-page 17 PIC18F8722 FAMILY TABLE 1-3: PIC18F6527/6622/6627/6722 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP Pin Type Buffer Type Description PORTE is a bidirectional I/O port. RE0/RD/P2D RE0 RD P2D 2 RE1/WR/P2C RE1 WR P2C 1 RE2/CS/P2B RE2 CS P2B 64 RE3/P3C RE3 P3C 63 RE4/P3B RE4 P3B 62 RE5/P1C RE5 P1C 61 RE6/P1B RE6 P1B 60 RE7/ECCP2/P2A RE7 ECCP2(2) 59 P2A(2) I/O I O ST TTL -- Digital I/O. Read control for Parallel Slave Port. ECCP2 PWM output D. I/O I O ST TTL -- Digital I/O. Write control for Parallel Slave Port. ECCP2 PWM output C. I/O I O ST TTL -- Digital I/O. Chip select control for Parallel Slave Port. ECCP2 PWM output B. I/O O ST -- Digital I/O. ECCP3 PWM output C. I/O O ST -- Digital I/O. ECCP3 PWM output B. I/O O ST -- Digital I/O. ECCP1 PWM output C. I/O O ST -- Digital I/O. ECCP1 PWM output B. I/O I/O ST ST O -- Digital I/O. Enhanced Capture 2 input/Compare 2 output/ PWM 2 output. ECCP2 PWM output A. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output = I2C/SMBus input buffer P = Power I2CTM Note 1: Default assignment for ECCP2 when configuration bit CCP2MX is set. 2: Alternate assignment for ECCP2 when configuration bit CCP2MX is cleared. DS39646B-page 18 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY TABLE 1-3: PIC18F6527/6622/6627/6722 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP Pin Type Buffer Type Description PORTF is a bidirectional I/O port. RF0/AN5 RF0 AN5 18 RF1/AN6/C2OUT RF1 AN6 C2OUT 17 RF2/AN7/C1OUT RF2 AN7 C1OUT 16 RF3/AN8 RF3 AN8 15 RF4/AN9 RF4 AN9 14 RF5/AN10/CVREF RF5 AN10 CVREF 13 RF6/AN11 RF6 AN11 12 RF7/SS1 RF7 SS1 11 I/O I ST Analog Digital I/O. Analog input 5. I/O I O ST Analog -- Digital I/O. Analog input 6. Comparator 2 output. I/O I O ST Analog -- Digital I/O. Analog input 7. Comparator 1 output. I/O I ST Analog Digital I/O. Analog input 8. I/O I ST Analog Digital I/O. Analog input 9. I/O I O ST Analog Analog Digital I/O. Analog input 10. Comparator reference voltage output. I/O I ST Analog Digital I/O. Analog input 11. I/O I ST TTL Digital I/O. SPITM slave select input. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output = I2C/SMBus input buffer P = Power I2CTM Note 1: Default assignment for ECCP2 when configuration bit CCP2MX is set. 2: Alternate assignment for ECCP2 when configuration bit CCP2MX is cleared. 2004 Microchip Technology Inc. Preliminary DS39646B-page 19 PIC18F8722 FAMILY TABLE 1-3: PIC18F6527/6622/6627/6722 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP Pin Type Buffer Type Description PORTG is a bidirectional I/O port. RG0/ECCP3/P3A RG0 ECCP3 3 P3A RG1/TX2/CK2 RG1 TX2 CK2 4 RG2/RX2/DT2 RG2 RX2 DT2 5 RG3/CCP4/P3D RG3 CCP4 P3D 6 RG4/CCP5/P1D RG4 CCP5 P1D 8 I/O I/O ST ST O -- Digital I/O. Enhanced Capture 3 input/Compare 3 output/ PWM 3 output. ECCP3 PWM output A. I/O O I/O ST -- ST Digital I/O. EUSART2 asynchronous transmit. EUSART2 synchronous clock (see related RX2/DT2). I/O I I/O ST ST ST Digital I/O. EUSART2 asynchronous receive. EUSART2 synchronous data (see related TX2/CK2). I/O I/O O ST ST -- Digital I/O. Capture 4 input/Compare 4 output/PWM 4 output. ECCP3 PWM output D. I/O I/O O ST ST -- Digital I/O. Capture 5 input/Compare 5 output/PWM 5 output. ECCP1 PWM output D. See RG5/MCLR/VPP pin. RG5 VSS 9, 25, 41, 56 P -- Ground reference for logic and I/O pins. VDD 10, 26, 38, 57 P -- Positive supply for logic and I/O pins. AVSS 20 P -- Ground reference for analog modules. AVDD 19 P -- Positive supply for analog modules. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output = I2C/SMBus input buffer P = Power I2CTM Note 1: Default assignment for ECCP2 when configuration bit CCP2MX is set. 2: Alternate assignment for ECCP2 when configuration bit CCP2MX is cleared. DS39646B-page 20 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY TABLE 1-4: PIC18F8527/8622/8627/8722 PINOUT I/O DESCRIPTIONS Pin Number Pin Name TQFP RG5/MCLR/VPP RG5 MCLR I I ST ST P 49 I CLKI I RA7 OSC2/CLKO/RA6 OSC2 Buffer Type 9 VPP OSC1/CLKI/RA7 OSC1 Pin Type I/O Description Master Clear (input) or programming voltage (input). Digital input. Master Clear (Reset) input. This pin is an active-low Reset to the device. Programming voltage input. Oscillator crystal or external clock input. Oscillator crystal input or external clock source input. ST buffer when configured in RC mode, CMOS otherwise. CMOS External clock source input. Always associated with pin function OSC1. (See related OSC1/CLKI, OSC2/CLKO pins.) TTL General purpose I/O pin. ST 50 O -- CLKO O -- RA6 I/O TTL Oscillator crystal or clock output. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. In RC mode, OSC2 pin outputs CLKO, which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. General purpose I/O pin. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power I2CTM/SMB = I2C/SMBus input buffer Note 1: Alternate assignment for ECCP2 when configuration bit CCP2MX is cleared (all operating modes except Microcontroller mode). 2: Default assignment for ECCP2 in all operating modes (CCP2MX is set). 3: Alternate assignment for ECCP2 when CCP2MX is cleared (Microcontroller mode only). 4: Default assignment for P1B/P1C/P3B/P3C (ECCPMX is set). 5: Alternate assignment for P1B/P1C/P3B/P3C (ECCPMX is clear). 2004 Microchip Technology Inc. Preliminary DS39646B-page 21 PIC18F8722 FAMILY TABLE 1-4: PIC18F8527/8622/8627/8722 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP Pin Type Buffer Type Description PORTA is a bidirectional I/O port. RA0/AN0 RA0 AN0 30 RA1/AN1 RA1 AN1 29 RA2/AN2/VREFRA2 AN2 VREF- 28 RA3/AN3/VREF+ RA3 AN3 VREF+ 27 RA4/T0CKI RA4 T0CKI 34 RA5/AN4/HLVDIN RA5 AN4 HLVDIN 33 I/O I TTL Analog Digital I/O. Analog input 0. I/O I TTL Analog Digital I/O. Analog input 1. I/O I I TTL Analog Analog Digital I/O. Analog input 2. A/D reference voltage (low) input. I/O I I TTL Analog Analog Digital I/O. Analog input 3. A/D reference voltage (high) input. I/O I ST/OD ST Digital I/O. Open-drain when configured as output. Timer0 external clock input. I/O I I TTL Analog Analog Digital I/O. Analog input 4. High/Low-Voltage Detect input. RA6 See the OSC2/CLKO/RA6 pin. RA7 See the OSC1/CLKI/RA7 pin. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power I2CTM/SMB = I2C/SMBus input buffer Note 1: Alternate assignment for ECCP2 when configuration bit CCP2MX is cleared (all operating modes except Microcontroller mode). 2: Default assignment for ECCP2 in all operating modes (CCP2MX is set). 3: Alternate assignment for ECCP2 when CCP2MX is cleared (Microcontroller mode only). 4: Default assignment for P1B/P1C/P3B/P3C (ECCPMX is set). 5: Alternate assignment for P1B/P1C/P3B/P3C (ECCPMX is clear). DS39646B-page 22 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY TABLE 1-4: PIC18F8527/8622/8627/8722 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP Pin Type Buffer Type Description PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs. RB0/INT0/FLT0 RB0 INT0 FLT0 58 RB1/INT1 RB1 INT1 57 RB2/INT2 RB2 INT2 56 RB3/INT3/ECCP2/P2A RB3 INT3 ECCP2(1) 55 P2A(1) RB4/KBI0 RB4 KBI0 54 RB5/KBI1/PGM RB5 KBI1 PGM 53 RB6/KBI2/PGC RB6 KBI2 PGC 52 RB7/KBI3/PGD RB7 KBI3 PGD 47 I/O I I TTL ST ST Digital I/O. External interrupt 0. PWM Fault input for ECCPx. I/O I TTL ST Digital I/O. External interrupt 1. I/O I TTL ST Digital I/O. External interrupt 2. I/O I O TTL ST -- O -- Digital I/O. External interrupt 3. Enhanced Capture 2 input/Compare 2 output/ PWM 2 output. ECCP2 PWM output A. I/O I TTL TTL Digital I/O. Interrupt-on-change pin. I/O I I/O TTL TTL ST Digital I/O. Interrupt-on-change pin. Low-Voltage ICSPTM Programming enable pin. I/O I I/O TTL TTL ST Digital I/O. Interrupt-on-change pin. In-Circuit Debugger and ICSPTM programming clock pin. I/O I I/O TTL TTL ST Digital I/O. Interrupt-on-change pin. In-Circuit Debugger and ICSP programming data pin. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power I2CTM/SMB = I2C/SMBus input buffer Note 1: Alternate assignment for ECCP2 when configuration bit CCP2MX is cleared (all operating modes except Microcontroller mode). 2: Default assignment for ECCP2 in all operating modes (CCP2MX is set). 3: Alternate assignment for ECCP2 when CCP2MX is cleared (Microcontroller mode only). 4: Default assignment for P1B/P1C/P3B/P3C (ECCPMX is set). 5: Alternate assignment for P1B/P1C/P3B/P3C (ECCPMX is clear). 2004 Microchip Technology Inc. Preliminary DS39646B-page 23 PIC18F8722 FAMILY TABLE 1-4: PIC18F8527/8622/8627/8722 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP Pin Type Buffer Type Description PORTC is a bidirectional I/O port. RC0/T1OSO/T13CKI RC0 T1OSO T13CKI 36 RC1/T1OSI/ECCP2/P2A RC1 T1OSI ECCP2(2) 35 P2A(2) RC2/ECCP1/P1A RC2 ECCP1 I/O O I ST -- ST Digital I/O. Timer1 oscillator output. Timer1/Timer3 external clock input. I/O I I/O ST CMOS ST O -- I/O I/O ST ST O -- Digital I/O. Enhanced Capture 1 input/Compare 1 output/ PWM 1 output. ECCP1 PWM output A. I/O I/O I/O ST ST ST Digital I/O. Synchronous serial clock input/output for SPITM mode. Synchronous serial clock input/output for I2CTM mode. I/O I I/O ST ST ST Digital I/O. SPI data in. I2C data I/O. I/O O ST -- Digital I/O. SPI data out. I/O O I/O ST -- ST Digital I/O. EUSART1 asynchronous transmit. EUSART1 synchronous clock (see related RX1/DT1). I/O I I/O ST ST ST Digital I/O. EUSART1 asynchronous receive. EUSART1 synchronous data (see related TX1/CK1). Digital I/O. Timer1 oscillator input. Enhanced Capture 2 input/Compare 2 output/ PWM 2 output. ECCP2 PWM output A. 43 P1A RC3/SCK1/SCL1 RC3 SCK1 SCL1 44 RC4/SDI1/SDA1 RC4 SDI1 SDA1 45 RC5/SDO1 RC5 SDO1 46 RC6/TX1/CK1 RC6 TX1 CK1 37 RC7/RX1/DT1 RC7 RX1 DT1 38 Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power I2CTM/SMB = I2C/SMBus input buffer Note 1: Alternate assignment for ECCP2 when configuration bit CCP2MX is cleared (all operating modes except Microcontroller mode). 2: Default assignment for ECCP2 in all operating modes (CCP2MX is set). 3: Alternate assignment for ECCP2 when CCP2MX is cleared (Microcontroller mode only). 4: Default assignment for P1B/P1C/P3B/P3C (ECCPMX is set). 5: Alternate assignment for P1B/P1C/P3B/P3C (ECCPMX is clear). DS39646B-page 24 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY TABLE 1-4: PIC18F8527/8622/8627/8722 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP Pin Type Buffer Type Description PORTD is a bidirectional I/O port. RD0/AD0/PSP0 RD0 AD0 PSP0 72 RD1/AD1/PSP1 RD1 AD1 PSP1 69 RD2/AD2/PSP2 RD2 AD2 PSP2 68 RD3/AD3/PSP3 RD3 AD3 PSP3 67 RD4/AD4/PSP4/SDO2 RD4 AD4 PSP4 SDO2 66 RD5/AD5/PSP5/ SDI2/SDA2 RD5 AD5 PSP5 SDI2 SDA2 65 RD6/AD6/PSP6/ SCK2/SCL2 RD6 AD6 PSP6 SCK2 SCL2 64 RD7/AD7/PSP7/SS2 RD7 AD7 PSP7 SS2 63 I/O I/O I/O ST TTL TTL Digital I/O. External memory address/data 0. Parallel Slave Port data. I/O I/O I/O ST TTL TTL Digital I/O. External memory address/data 1. Parallel Slave Port data. I/O I/O I/O ST TTL TTL Digital I/O. External memory address/data 2. Parallel Slave Port data. I/O I/O I/O ST TTL TTL Digital I/O. External memory address/data 3. Parallel Slave Port data. I/O I/O I/O O ST TTL TTL -- Digital I/O. External memory address/data 4. Parallel Slave Port data. SPITM data out. I/O I/O I/O I I/O ST TTL TTL ST I2C/SMB Digital I/O. External memory address/data 5. Parallel Slave Port data. SPI data in. I2CTM data I/O. I/O I/O I/O I/O I/O ST TTL TTL ST I2C/SMB Digital I/O. External memory address/data 6. Parallel Slave Port data. Synchronous serial clock input/output for SPI mode. Synchronous serial clock input/output for I2C mode. I/O I/O I/O I ST TTL TTL TTL Digital I/O. External memory address/data 7. Parallel Slave Port data. SPI slave select input. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power I2CTM/SMB = I2C/SMBus input buffer Note 1: Alternate assignment for ECCP2 when configuration bit CCP2MX is cleared (all operating modes except Microcontroller mode). 2: Default assignment for ECCP2 in all operating modes (CCP2MX is set). 3: Alternate assignment for ECCP2 when CCP2MX is cleared (Microcontroller mode only). 4: Default assignment for P1B/P1C/P3B/P3C (ECCPMX is set). 5: Alternate assignment for P1B/P1C/P3B/P3C (ECCPMX is clear). 2004 Microchip Technology Inc. Preliminary DS39646B-page 25 PIC18F8722 FAMILY TABLE 1-4: PIC18F8527/8622/8627/8722 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP Pin Type Buffer Type Description PORTE is a bidirectional I/O port. RE0/AD8/RD/P2D RE0 AD8 RD P2D 4 RE1/AD9/WR/P2C RE1 AD9 WR P2C 3 RE2/AD10/CS/P2B RE2 AD10 CS P2B 78 RE3/AD11/P3C RE3 AD11 P3C(4) 77 RE4/AD12/P3B RE4 AD12 P3B(4) 76 RE5/AD13/P1C RE5 AD13 P1C(4) 75 RE6/AD14/P1B RE6 AD14 P1B(4) 74 RE7/AD15/ECCP2/P2A RE7 AD15 ECCP2(3) 73 P2A(3) I/O I/O I O ST TTL TTL -- Digital I/O. External memory address/data 8. Read control for Parallel Slave Port. ECCP2 PWM output D. I/O I/O I O ST TTL TTL -- Digital I/O. External memory address/data 9. Write control for Parallel Slave Port. ECCP2 PWM output C. I/O I/O I O ST TTL TTL -- Digital I/O. External memory address/data 10. Chip select control for Parallel Slave Port. ECCP2 PWM output B. I/O I/O O ST TTL -- Digital I/O. External memory address/data 11. ECCP3 PWM output C. I/O I/O O ST TTL -- Digital I/O. External memory address/data 12. ECCP3 PWM output B. I/O I/O O ST TTL -- Digital I/O. External memory address/data 13. ECCP1 PWM output C. I/O I/O O ST TTL -- Digital I/O. External memory address/data 14. ECCP1 PWM output B. I/O I/O I/O ST TTL ST O -- Digital I/O. External memory address/data 15. Enhanced Capture 2 input/Compare 2 output/ PWM 2 output. ECCP2 PWM output A. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power I2CTM/SMB = I2C/SMBus input buffer Note 1: Alternate assignment for ECCP2 when configuration bit CCP2MX is cleared (all operating modes except Microcontroller mode). 2: Default assignment for ECCP2 in all operating modes (CCP2MX is set). 3: Alternate assignment for ECCP2 when CCP2MX is cleared (Microcontroller mode only). 4: Default assignment for P1B/P1C/P3B/P3C (ECCPMX is set). 5: Alternate assignment for P1B/P1C/P3B/P3C (ECCPMX is clear). DS39646B-page 26 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY TABLE 1-4: PIC18F8527/8622/8627/8722 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP Pin Type Buffer Type Description PORTF is a bidirectional I/O port. RF0/AN5 RF0 AN5 24 RF1/AN6/C2OUT RF1 AN6 C2OUT 23 RF2/AN7/C1OUT RF2 AN7 C1OUT 18 RF3/AN8 RF3 AN8 17 RF4/AN9 RF4 AN9 16 RF5/AN10/CVREF RF5 AN10 CVREF 15 RF6/AN11 RF6 AN11 14 RF7/SS1 RF7 SS1 13 I/O I ST Analog Digital I/O. Analog input 5. I/O I O ST Analog -- Digital I/O. Analog input 6. Comparator 2 output. I/O I O ST Analog -- Digital I/O. Analog input 7. Comparator 1 output. I/O I ST Analog Digital I/O. Analog input 8. I/O I ST Analog Digital I/O. Analog input 9. I/O I O ST Analog Analog Digital I/O. Analog input 10. Comparator reference voltage output. I/O I ST Analog Digital I/O. Analog input 11. I/O I ST TTL Digital I/O. SPITM slave select input. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power I2CTM/SMB = I2C/SMBus input buffer Note 1: Alternate assignment for ECCP2 when configuration bit CCP2MX is cleared (all operating modes except Microcontroller mode). 2: Default assignment for ECCP2 in all operating modes (CCP2MX is set). 3: Alternate assignment for ECCP2 when CCP2MX is cleared (Microcontroller mode only). 4: Default assignment for P1B/P1C/P3B/P3C (ECCPMX is set). 5: Alternate assignment for P1B/P1C/P3B/P3C (ECCPMX is clear). 2004 Microchip Technology Inc. Preliminary DS39646B-page 27 PIC18F8722 FAMILY TABLE 1-4: PIC18F8527/8622/8627/8722 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP Pin Type Buffer Type Description PORTG is a bidirectional I/O port. RG0/ECCP3/P3A RG0 ECCP3 5 P3A RG1/TX2/CK2 RG1 TX2 CK2 6 RG2/RX2/DT2 RG2 RX2 DT2 7 RG3/CCP4/P3D RG3 CCP4 P3D 8 RG4/CCP5/P1D RG4 CCP5 P1D 10 RG5 I/O I/O ST ST O -- Digital I/O. Enhanced Capture 3 input/Compare 3 output/ PWM 3 output. ECCP3 PWM output A. I/O O I/O ST -- ST Digital I/O. EUSART2 asynchronous transmit. EUSART2 synchronous clock (see related RX2/DT2). I/O I I/O ST ST ST Digital I/O. EUSART2 asynchronous receive. EUSART2 synchronous data (see related TX2/CK2). I/O I/O O ST ST -- Digital I/O. Capture 4 input/Compare 4 output/PWM 4 output. ECCP3 PWM output D. I/O I/O O ST ST -- Digital I/O. Capture 5 input/Compare 5 output/PWM 5 output. ECCP1 PWM output D. See RG5/MCLR/VPP pin. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power I2CTM/SMB = I2C/SMBus input buffer Note 1: Alternate assignment for ECCP2 when configuration bit CCP2MX is cleared (all operating modes except Microcontroller mode). 2: Default assignment for ECCP2 in all operating modes (CCP2MX is set). 3: Alternate assignment for ECCP2 when CCP2MX is cleared (Microcontroller mode only). 4: Default assignment for P1B/P1C/P3B/P3C (ECCPMX is set). 5: Alternate assignment for P1B/P1C/P3B/P3C (ECCPMX is clear). DS39646B-page 28 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY TABLE 1-4: PIC18F8527/8622/8627/8722 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP Pin Type Buffer Type Description PORTH is a bidirectional I/O port. RH0/A16 RH0 A16 79 RH1/A17 RH1 A17 80 RH2/A18 RH2 A18 1 RH3/A19 RH3 A19 2 RH4/AN12/P3C RH4 AN12 P3C(5) 22 RH5/AN13/P3B RH5 AN13 P3B(5) 21 RH6/AN14/P1C RH6 AN14 P1C(5) 20 RH7/AN15/P1B RH7 AN15 P1B(5) 19 I/O I/O ST TTL Digital I/O. External memory address/data 16. I/O I/O ST TTL Digital I/O. External memory address/data 17. I/O I/O ST TTL Digital I/O. External memory address/data 18. I/O I/O ST TTL Digital I/O. External memory address/data 19. I/O I O ST Analog -- Digital I/O. Analog input 12. ECCP3 PWM output C. I/O I O ST Analog -- Digital I/O. Analog input 13. ECCP3 PWM output B. I/O I O ST Analog -- Digital I/O. Analog input 14. ECCP1 PWM output C. I/O I O ST Analog -- Digital I/O. Analog input 15. ECCP1 PWM output B. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power I2CTM/SMB = I2C/SMBus input buffer Note 1: Alternate assignment for ECCP2 when configuration bit CCP2MX is cleared (all operating modes except Microcontroller mode). 2: Default assignment for ECCP2 in all operating modes (CCP2MX is set). 3: Alternate assignment for ECCP2 when CCP2MX is cleared (Microcontroller mode only). 4: Default assignment for P1B/P1C/P3B/P3C (ECCPMX is set). 5: Alternate assignment for P1B/P1C/P3B/P3C (ECCPMX is clear). 2004 Microchip Technology Inc. Preliminary DS39646B-page 29 PIC18F8722 FAMILY TABLE 1-4: PIC18F8527/8622/8627/8722 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP Pin Type Buffer Type Description PORTJ is a bidirectional I/O port. RJ0/ALE RJ0 ALE 62 RJ1/OE RJ1 OE 61 RJ2/WRL RJ2 WRL 60 RJ3/WRH RJ3 WRH 59 RJ4/BA0 RJ4 BA0 39 RJ5/CE RJ4 CE 40 RJ6/LB RJ6 LB 41 RJ7/UB RJ7 UB 42 VSS 11, 31, 51, 70 I/O O ST -- Digital I/O. External memory address latch enable. I/O O ST -- Digital I/O. External memory output enable. I/O O ST -- Digital I/O. External memory write low control. I/O O ST -- Digital I/O. External memory write high control. I/O O ST -- Digital I/O. External memory byte address 0 control. I/O O ST -- Digital I/O External memory chip enable control. I/O O ST -- Digital I/O. External memory low byte control. I/O O ST -- Digital I/O. External memory high byte control. P -- Ground reference for logic and I/O pins. VDD 12, 32, 48, 71 P -- Positive supply for logic and I/O pins. AVSS 26 P -- Ground reference for analog modules. AVDD 25 P -- Positive supply for analog modules. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power I2CTM/SMB = I2C/SMBus input buffer Note 1: Alternate assignment for ECCP2 when configuration bit CCP2MX is cleared (all operating modes except Microcontroller mode). 2: Default assignment for ECCP2 in all operating modes (CCP2MX is set). 3: Alternate assignment for ECCP2 when CCP2MX is cleared (Microcontroller mode only). 4: Default assignment for P1B/P1C/P3B/P3C (ECCPMX is set). 5: Alternate assignment for P1B/P1C/P3B/P3C (ECCPMX is clear). DS39646B-page 30 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY 2.0 OSCILLATOR CONFIGURATIONS 2.1 Oscillator Types FIGURE 2-1: C1(1) The PIC18F8722 family of devices can be operated in ten different oscillator modes. The user can program the configuration bits, FOSC3:FOSC0, in Configuration Register 1H to select one of these ten modes: 1. 2. 3. 4. Low-Power Crystal Crystal/Resonator High-Speed Crystal/Resonator High-Speed Crystal/Resonator with PLL enabled 5. RC External Resistor/Capacitor with FOSC/4 output on RA6 6. RCIO External Resistor/Capacitor with I/O on RA6 7. INTIO1 Internal Oscillator with FOSC/4 output on RA6 and I/O on RA7 8. INTIO2 Internal Oscillator with I/O on RA6 and RA7 9. EC External Clock with FOSC/4 output 10. ECIO External Clock with I/O on RA6 C2(1) To Internal Logic RF(3) Sleep RS(2) PIC18FXXXX OSC2 Note 1: See Table 2-1 and Table 2-2 for initial values of C1 and C2. 2: A series resistor (RS) may be required for AT strip cut crystals. 3: RF varies with the oscillator mode chosen. TABLE 2-1: CAPACITOR SELECTION FOR CERAMIC RESONATORS Typical Capacitor Values Used: Crystal Oscillator/Ceramic Resonators Mode Freq OSC1 OSC2 XT 3.58 MHz 22 pF 22 pF Capacitor values are for design guidance only. In XT, LP, HS or HSPLL Oscillator modes, a crystal or ceramic resonator is connected to the OSC1 and OSC2 pins to establish oscillation. Figure 2-1 shows the pin connections. The oscillator design requires the use of a parallel cut crystal. Note: OSC1 XTAL LP XT HS HSPLL 2.2 CRYSTAL/CERAMIC RESONATOR OPERATION (XT, LP, HS OR HSPLL CONFIGURATION) Use of a series cut crystal may give a frequency out of the crystal manufacturer's specifications. Different capacitor values may be required to produce acceptable oscillator operation. The user should test the performance of the oscillator over the expected VDD and temperature range for the application. Refer to the following application notes for oscillator specific information: * AN588 - PICmicro(R) Microcontroller Oscillator Design Guide * AN826 - Crystal Oscillator Basics and Crystal Selection for rfPICTM and PICmicro(R) Devices * AN849 - Basic PICmicro(R) Oscillator Design * AN943 - Practical PICmicro(R) Oscillator Analysis and Design * AN949 - Making Your Oscillator Work See the notes following Table 2-2 for additional information. Note: 2004 Microchip Technology Inc. Preliminary When using resonators with frequencies above 3.5 MHz, the use of HS mode, rather than XT mode, is recommended. HS mode may be used at any VDD for which the controller is rated. If HS is selected, it is possible that the gain of the oscillator will overdrive the resonator. Therefore, a series resistor may be placed between the OSC2 pin and the resonator. As a good starting point, the recommended value of RS is 330. DS39646B-page 31 PIC18F8722 FAMILY TABLE 2-2: Osc Type CAPACITOR SELECTION FOR QUARTZ CRYSTALS Crystal Freq Typical Capacitor Values Tested: C1 C2 LP 32 kHz 22 pF 22 pF XT 1 MHz 4 MHz 22 pF 22 pF 22 pF 22 pF HS 4 MHz 10 MHz 20 MHz 25 MHz 22 pF 22 pF 22 pF 22 pF 22 pF 22 pF 22 pF 22 pF An external clock source may also be connected to the OSC1 pin in the HS mode, as shown in Figure 2-2. When operated in this mode, parameters D033 and D043 apply. FIGURE 2-2: EXTERNAL CLOCK INPUT OPERATION (HS OSC CONFIGURATION) OSC1 Clock from Ext. System PIC18FXXXX Open (HS Mode) OSC2 Capacitor values are for design guidance only. Different capacitor values may be required to produce acceptable oscillator operation. The user should test the performance of the oscillator over the expected VDD and temperature range for the application. Refer to the following application notes for oscillator specific information: 2.3 * AN588 - PICmicro(R) Microcontroller Oscillator Design Guide * AN826 - Crystal Oscillator Basics and Crystal Selection for rfPICTM and PICmicro(R) Devices * AN849 - Basic PICmicro(R) Oscillator Design * AN943 - Practical PICmicro(R) Oscillator Analysis and Design * AN949 - Making Your Oscillator Work In the EC Oscillator mode, the oscillator frequency divided by 4 is available on the OSC2 pin. This signal may be used for test purposes or to synchronize other logic. Figure 2-3 shows the pin connections for the EC Oscillator mode. External Clock Input The EC and ECIO Oscillator modes require an external clock source to be connected to the OSC1 pin. There is no oscillator start-up time required after a Power-on Reset or after an exit from Sleep mode. FIGURE 2-3: See the notes following this table for additional information. OSC1/CLKI Clock from Ext. System 2: When operating below 3V VDD, or when using certain ceramic resonators at any voltage, it may be necessary to use the HS mode or switch to a crystal oscillator. 3: Since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components. 4: Rs may be required to avoid overdriving crystals with low drive level specification. 5: Always verify oscillator performance over the VDD and temperature range that is expected for the application. DS39646B-page 32 PIC18FXXXX FOSC/4 Note 1: Higher capacitance increases the stability of the oscillator but also increases the start-up time. EXTERNAL CLOCK INPUT OPERATION (EC CONFIGURATION) OSC2/CLKO The ECIO Oscillator mode functions like the EC mode, except that the OSC2 pin becomes an additional general purpose I/O pin. The I/O pin becomes bit 6 of PORTA (RA6). Figure 2-4 shows the pin connections for the ECIO Oscillator mode. When operated in this mode, parameters D033A and D043A apply. FIGURE 2-4: OSC1/CLKI Clock from Ext. System Preliminary EXTERNAL CLOCK INPUT OPERATION (ECIO CONFIGURATION) PIC18FXXXX RA6 I/O (OSC2) 2004 Microchip Technology Inc. PIC18F8722 FAMILY 2.4 RC Oscillator 2.5 For timing insensitive applications, the RC and RCIO Oscillator modes offer additional cost savings. The actual oscillator frequency is a function of several factors: * supply voltage * values of the external resistor (REXT) and capacitor (CEXT) * operating temperature A Phase Locked Loop (PLL) circuit is provided as an option for users who wish to use a lower frequency oscillator circuit or to clock the device up to its highest rated frequency from a crystal oscillator. This may be useful for customers who are concerned with EMI due to high-frequency crystals or users who require higher clock speeds from an internal oscillator. 2.5.1 Given the same device, operating voltage and temperature and component values, there will also be unit-to-unit frequency variations. These are due to factors such as: * normal manufacturing variation * difference in lead frame capacitance between package types (especially for low CEXT values) * variations within the tolerance of limits of REXT and CEXT In the RC Oscillator mode, the oscillator frequency divided by 4 is available on the OSC2 pin. This signal may be used for test purposes or to synchronize other logic. Figure 2-5 shows how the R/C combination is connected. FIGURE 2-5: PLL Frequency Multiplier HSPLL OSCILLATOR MODE The HSPLL mode makes use of the HS mode oscillator for frequencies up to 10 MHz. A PLL then multiplies the oscillator output frequency by 4 to produce an internal clock frequency up to 40 MHz. The PLLEN bit is not available when this mode is configured as the primary clock source. The PLL is only available to the crystal oscillator when the FOSC3:FOSC0 configuration bits are programmed for HSPLL mode (= 0110). FIGURE 2-7: HSPLL BLOCK DIAGRAM HS Oscillator Enable PLL Enable (from Configuration Register 1H) RC OSCILLATOR MODE VDD OSC2 HS Mode OSC1 Crystal Osc REXT OSC1 Internal Clock FIN FOUT Loop Filter CEXT PIC18FXXXX VSS FOSC/4 OSC2/CLKO /4 The RCIO Oscillator mode (Figure 2-6) functions like the RC mode, except that the OSC2 pin becomes an additional general purpose I/O pin. The I/O pin becomes bit 6 of PORTA (RA6). RCIO OSCILLATOR MODE VDD REXT OSC1 VCO MUX Recommended values: 3 k REXT 100 k 20 pF CEXT 300 pF FIGURE 2-6: Phase Comparator Internal Clock 2.5.2 SYSCLK PLL AND INTOSC The PLL is also available to the internal oscillator block when the internal oscillator block is configured as the primary clock source. In this configuration, the PLL is enabled in software and generates a clock output of up to 32 MHz. The operation of INTOSC with the PLL is described in Section 2.6.4 "PLL in INTOSC Modes". CEXT PIC18FXXXX VSS RA6 I/O (OSC2) Recommended values: 3 k REXT 100 k 20 pF CEXT 300 pF 2004 Microchip Technology Inc. Preliminary DS39646B-page 33 PIC18F8722 FAMILY 2.6 2.6.2 Internal Oscillator Block The PIC18F8722 family of devices includes an internal oscillator block which generates two different clock signals; either can be used as the microcontroller's clock source. This may eliminate the need for external oscillator circuits on the OSC1 and/or OSC2 pins. The main output (INTOSC) is an 8 MHz clock source, which can be used to directly drive the device clock. It also drives a postscaler, which can provide a range of clock frequencies from 31 kHz to 4 MHz. The INTOSC output is enabled when a clock frequency from 125 kHz to 8 MHz is selected. The INTOSC output can also be enabled when 31 kHz is selected, depending on the INTSRC bit (OSCTUNE<7>). The other clock source is the internal RC oscillator (INTRC), which provides a nominal 31 kHz output. INTRC is enabled if it is selected as the device clock source; it is also enabled automatically when any of the following are enabled: * * * * Power-up Timer Fail-Safe Clock Monitor Watchdog Timer Two-Speed Start-up These features are discussed in greater detail in Section 25.0 "Special Features of the CPU". The clock source frequency (INTOSC direct, INTRC direct or INTOSC postscaler) is selected by configuring the IRCF bits of the OSCCON register (page 39). 2.6.1 INTIO MODES Using the internal oscillator as the clock source eliminates the need for up to two external oscillator pins, which can then be used for digital I/O. Two distinct configurations are available: The internal oscillator block is calibrated at the factory to produce an INTOSC output frequency of 8 MHz. The INTRC oscillator operates independently of the INTOSC source. Any changes in INTOSC across voltage and temperature are not necessarily reflected by changes in INTRC or vice versa. 2.6.3 RA7 FOSC/4 OSCTUNE REGISTER The INTOSC output has been calibrated at the factory but can be adjusted in the user's application. This is done by writing to TUN4:TUN0 (OSCTUNE<4:0>) in the OSCTUNE register (Register 2-1). When the OSCTUNE register is modified, the INTOSC frequency will begin shifting to the new frequency. The INTOSC clock will stabilize within 1 ms. Code execution continues during this shift. There is no indication that the shift has occurred. The INTRC is not affected by OSCTUNE. The OSCTUNE register also implements the INTSRC (OSCTUNE<7>) and PLLEN (OSCTUNE<6>) bits, which control certain features of the internal oscillator block. The INTSRC bit allows users to select which internal oscillator provides the clock source when the 31 kHz frequency option is selected. This is covered in greater detail in Section 2.7.1 "Oscillator Control Register". The PLLEN bit controls the operation of the Phase Locked Loop (PLL) in internal oscillator modes (see Figure 2-10). FIGURE 2-10: INTOSC AND PLL BLOCK DIAGRAM 8 or 4 MHz PLLEN (OSCTUNE<6>) * In INTIO1 mode, the OSC2 pin outputs FOSC/4, while OSC1 functions as RA7 (see Figure 2-8) for digital input and output. * In INTIO2 mode, OSC1 functions as RA7 and OSC2 functions as RA6 (see Figure 2-9), both for digital input and output. FIGURE 2-8: INTOSC OUTPUT FREQUENCY FOUT INTIO1 OSCILLATOR MODE I/O (OSC1) Loop Filter PIC18FXXXX OSC2 /4 OSC2 I/O (OSC1) RA6 I/O (OSC2) DS39646B-page 34 PIC18FXXXX SYSCLK MUX INTIO2 OSCILLATOR MODE RA7 VCO MUX CLKO FIGURE 2-9: Phase Comparator FIN INTOSC RA6 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY 2.6.4 PLL IN INTOSC MODES 2.6.5 The 4x Phase Locked Loop (PLL) can be used with the internal oscillator block to produce faster device clock speeds than are normally possible with the internal oscillator sources. When enabled, the PLL produces a clock speed of 16 MHz or 32 MHz. Unlike HSPLL mode, the PLL is controlled through software. The control bit, PLLEN (OSCTUNE<6>), is used to enable or disable its operation. The PLL is available when the device is configured to use the internal oscillator block as its primary clock source (FOSC3:FOSC0 = 1001 or 1000). Additionally, the PLL will only function when the selected output frequency is either 4 MHz or 8 MHz (OSCCON<6:4> = 111 or 110). If both of these conditions are not met, the PLL is disabled and the PLLEN bit remains clear (writes are ignored). REGISTER 2-1: INTOSC FREQUENCY DRIFT The factory calibrates the internal oscillator block output (INTOSC) for 8 MHz. However, this frequency may drift as VDD or temperature changes and can affect the controller operation in a variety of ways. It is possible to adjust the INTOSC frequency by modifying the value in the OSCTUNE register. Depending on the device, this may have no effect on the INTRC clock source frequency. Tuning the INTOSC source requires knowing when to make the adjustment, in which direction it should be made and in some cases, how large a change is needed. Three compensation techniques are discussed in Section 2.6.5.1 "Compensating with the EUSART", Section 2.6.5.2 "Compensating with the Timers" and Section 2.6.5.3 "Compensating with the CCP Module in Capture Mode" but other techniques may be used. OSCTUNE: OSCILLATOR TUNING REGISTER R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 INTSRC PLLEN(1) -- TUN4 TUN3 TUN2 TUN1 TUN0 bit 7 bit 0 bit 7 INTSRC: Internal Oscillator Low-Frequency Source Select bit 1 = 31.25 kHz device clock derived from 8 MHz INTOSC source (divide-by-256 enabled) 0 = 31 kHz device clock derived directly from INTRC internal oscillator bit 6 PLLEN: Frequency Multiplier PLL for INTOSC Enable bit(1) 1 = PLL enabled for INTOSC (4 MHz and 8 MHz only) 0 = PLL disabled Note 1: Available only in certain oscillator configurations; otherwise, this bit is unavailable and reads as `0'. See Section 2.6.4 "PLL in INTOSC Modes" for details. bit 5 Unimplemented: Read as `0' bit 4-0 TUN4:TUN0: Frequency Tuning bits 01111 = Maximum frequency * * * * 00001 00000 = Center frequency. Oscillator module is running at the calibrated frequency. 11111 * * * * 10000 = Minimum frequency Legend: R = Readable bit -n = Value at POR 2004 Microchip Technology Inc. W = Writable bit `1' = Bit is set Preliminary U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown DS39646B-page 35 PIC18F8722 FAMILY 2.6.5.1 Compensating with the EUSART 2.6.5.3 An adjustment may be required when the EUSART begins to generate framing errors or receives data with errors while in Asynchronous mode. Framing errors indicate that the device clock frequency is too high. To adjust for this, decrement the value in OSCTUNE to reduce the clock frequency. On the other hand, errors in data may suggest that the clock speed is too low. To compensate, increment OSCTUNE to increase the clock frequency. 2.6.5.2 Compensating with the Timers This technique compares device clock speed to some reference clock. Two timers may be used; one timer is clocked by the peripheral clock, while the other is clocked by a fixed reference source, such as the Timer1 oscillator. Both timers are cleared, but the timer clocked by the reference generates interrupts. When an interrupt occurs, the internally clocked timer is read and both timers are cleared. If the internally clocked timer value is much greater than expected, then the internal oscillator block is running too fast. To adjust for this, decrement the OSCTUNE register. DS39646B-page 36 Compensating with the CCP Module in Capture Mode A CCP module can use free running Timer1 (or Timer3), clocked by the internal oscillator block and an external event with a known period (i.e., AC power frequency). The time of the first event is captured in the CCPRxH:CCPRxL registers and is recorded for use later. When the second event causes a capture, the time of the first event is subtracted from the time of the second event. Since the period of the external event is known, the time difference between events can be calculated. If the measured time is much greater than the calculated time, the internal oscillator block is running too fast. To compensate, decrement the OSCTUNE register. If the measured time is much less than the calculated time, the internal oscillator block is running too slow. To compensate, increment the OSCTUNE register. Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY 2.7 Clock Sources and Oscillator Switching The PIC18F8722 family of devices includes a feature that allows the device clock source to be switched from the main oscillator to an alternate clock source. These devices also offer two alternate clock sources. When an alternate clock source is enabled, the various power-managed operating modes are available. Essentially, there are three clock sources for these devices: * Primary oscillators * Secondary oscillators * Internal oscillator block The PIC18F8722 family of devices offers the Timer1 oscillator as a secondary oscillator. This oscillator, in all power-managed modes, is often the time base for functions such as a real-time clock. Most often, a 32.768 kHz watch crystal is connected between the RC0/T1OSO/T13CKI and RC1/T1OSI pins. Like the LP mode oscillator circuit, loading capacitors are also connected from each pin to ground. The Timer1 oscillator is discussed in greater detail in Section 13.3 "Timer1 Oscillator". The primary oscillators include the External Crystal and Resonator modes, the External RC modes, the External Clock modes and the internal oscillator block. The particular mode is defined by the FOSC3:FOSC0 configuration bits. The details of these modes are covered earlier in this chapter. FIGURE 2-11: The secondary oscillators are those external sources not connected to the OSC1 or OSC2 pins. These sources may continue to operate even after the controller is placed in a power-managed mode. In addition to being a primary clock source, the internal oscillator block is available as a power-managed mode clock source. The INTRC source is also used as the clock source for several special features, such as the WDT and Fail-Safe Clock Monitor. The clock sources for the PIC18F8722 family of devices are shown in Figure 2-11. See Section 25.0 "Special Features of the CPU" for Configuration register details. PIC18F8722 FAMILY CLOCK DIAGRAM PIC18F6527/6622/6627/6722/8527/8622/8627/8722 Primary Oscillator LP, XT, HS, RC, EC OSC2 Sleep 4 x PLL OSC1 OSCTUNE<6> Secondary Oscillator T1OSCEN Enable Oscillator OSCCON<6:4> 8 MHz OSCCON<6:4> INTRC Source Internal Oscillator CPU 111 110 2 MHz 31 kHz (INTRC) 1 MHz 500 kHz 250 kHz 125 kHz IDLEN 101 100 011 MUX 8 MHz (INTOSC) Postscaler Internal Oscillator Block 8 MHz Source 4 MHz Peripherals MUX T1OSC T1OSO T1OSI HSPLL, INTOSC/PLL 010 001 1 31 kHz 000 0 Clock Control FOSC3:FOSC0 OSCCON<1:0> Clock Source Option for other Modules OSCTUNE<7> WDT, PWRT, FSCM and Two-Speed Start-up 2004 Microchip Technology Inc. Preliminary DS39646B-page 37 PIC18F8722 FAMILY 2.7.1 OSCILLATOR CONTROL REGISTER The OSCCON register (Register 2-2) controls several aspects of the device clock's operation, both in full power operation and in power-managed modes. The System Clock Select bits, SCS1:SCS0, select the clock source. The available clock sources are the primary clock (defined by the FOSC3:FOSC0 configuration bits), the secondary clock (Timer1 oscillator) and the internal oscillator block. The clock source changes immediately after either of the SCSI:SCSO bits are changed, following a brief clock transition interval. The SCS bits are reset on all forms of Reset. The Internal Oscillator Frequency Select bits (IRCF2:IRCF0) select the frequency output of the internal oscillator block to drive the device clock. The choices are the INTRC source (31 kHz), the INTOSC source (8 MHz) or one of the frequencies derived from the INTOSC postscaler (31.25 kHz to 4 MHz). If the internal oscillator block is supplying the device clock, changing the states of these bits will have an immediate change on the internal oscillator's output. On device Resets, the default output frequency of the internal oscillator block is set at 1 MHz. When a nominal output frequency of 31 kHz is selected (IRCF2:IRCF0 = 000), users may choose which internal oscillator acts as the source. This is done with the INTSRC bit in the OSCTUNE register (OSCTUNE<7>). Setting this bit selects INTOSC as a 31.25 kHz clock source derived from the INTOSC postscaler. Clearing INTSRC selects INTRC (nominally 31 kHz) as the clock source and disables the INTOSC to reduce current consumption. The IDLEN bit controls whether the device goes into Sleep mode or one of the Idle modes when the SLEEP instruction is executed. The use of the flag and control bits in the OSCCON register is discussed in more detail in Section 3.0 "Power-Managed Modes". Note 1: The Timer1 oscillator must be enabled to select the secondary clock source. The Timer1 oscillator is enabled by setting the T1OSCEN bit in the Timer1 Control register (T1CON<3>). If the Timer1 oscillator is not enabled, then any attempt to select a secondary clock source will be ignored. 2: It is recommended that the Timer1 oscillator be operating and stable before selecting the secondary clock source or a very long delay may occur while the Timer1 oscillator starts. 2.7.2 OSCILLATOR TRANSITIONS The PIC18F8722 family of devices contains circuitry to prevent clock "glitches" when switching between clock sources. A short pause in the device clock occurs during the clock switch. The length of this pause is the sum of two cycles of the old clock source and three to four cycles of the new clock source. This formula assumes that the new clock source is stable. Clock transitions are discussed in greater detail in Section 3.1.2 "Entering Power-Managed Modes". This option allows users to select the tunable and more precise INTOSC as a clock source, while maintaining power savings with a very low clock speed. Additionally, the INTOSC source will already be stable should a switch to a higher frequency be needed quickly. Regardless of the setting of INTSRC, INTRC always remains the clock source for features such as the Watchdog Timer and the Fail-Safe Clock Monitor. The OSTS, IOFS and T1RUN bits indicate which clock source is currently providing the device clock. The OSTS bit indicates that the Oscillator Start-up Timer and PLL Start-up Timer (if enabled) have timed out and the primary clock is providing the device clock in primary clock modes. The IOFS bit indicates when the internal oscillator block has stabilized and is providing the device clock in RC Clock modes. The T1RUN bit (T1CON<6>) indicates when the Timer1 oscillator is providing the device clock in secondary clock modes. In power-managed modes, only one of these three bits will be set at any time. If none of these bits are set, the INTRC is providing the clock or the internal oscillator block has just started and is not yet stable. DS39646B-page 38 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY REGISTER 2-2: OSCCON: OSCILLATOR CONTROL REGISTER R/W-0 R/W-1 R/W-0 R/W-0 R(1) R-0 R/W-0 R/W-0 IDLEN IRCF2 IRCF1 IRCF0 OSTS IOFS SCS1 SCS0 bit 7 bit 0 bit 7 IDLEN: Idle Enable bit 1 = Device enters an Idle mode when a SLEEP instruction is executed 0 = Device enters Sleep mode when a SLEEP instruction is executed bit 6-4 IRCF2:IRCF0: Internal Oscillator Frequency Select bits(5) 111 = 8 MHz (INTOSC drives clock directly) 110 = 4 MHz 101 = 2 MHz 100 = 1 MHz(3) 011 = 500 kHz 010 = 250 kHz 001 = 125 kHz 000 = 31 kHz (from either INTOSC/256 or INTRC directly)(2) bit 3 OSTS: Oscillator Start-up Time-out Status bit(1) 1 = Oscillator Start-up Timer (OST) time-out has expired; primary oscillator is running 0 = Oscillator Start-up Timer (OST) time-out is running; primary oscillator is not ready bit 2 IOFS: INTOSC Frequency Stable bit 1 = INTOSC frequency is stable 0 = INTOSC frequency is not stable bit 1-0 SCS1:SCS0: System Clock Select bits(4) 1x = Internal oscillator block 01 = Secondary (Timer1) oscillator 00 = Primary oscillator Note 1: Reset state depends on state of the IESO configuration bit. 2: Source selected by the INTSRC bit (OSCTUNE<7>), see text. 3: Default output frequency of INTOSC on Reset. 4: Modifying the SCSI:SCSO bits will cause an immediate clock source switch. 5: Modifying the IRCF3:IRCF0 bits will cause an immediate clock frequency switch if the internal oscillator is providing the device clocks. Legend: R = Readable bit -n = Value at POR 2004 Microchip Technology Inc. W = Writable bit `1' = Bit is set Preliminary U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown DS39646B-page 39 PIC18F8722 FAMILY 2.8 Effects of Power-Managed Modes on the Various Clock Sources When PRI_IDLE mode is selected, the configured oscillator continues to run without interruption. For all other power-managed modes, the oscillator using the OSC1 pin is disabled. The OSC1 pin (and OSC2 pin in crystal oscillator modes) will stop oscillating. In secondary clock modes (SEC_RUN and SEC_IDLE), the Timer1 oscillator is operating and providing the device clock. The Timer1 oscillator may also run in all power-managed modes if required to clock Timer1 or Timer3. In internal oscillator modes (RC_RUN and RC_IDLE), the internal oscillator block provides the device clock source. The 31 kHz INTRC output can be used directly to provide the clock and may be enabled to support various special features, regardless of the powermanaged mode (see Section 25.2 "Watchdog Timer (WDT)" and Section 25.4 "Fail-Safe Clock Monitor" for more information). The INTOSC output at 8 MHz may be used directly to clock the device or may be divided down by the postscaler. The INTOSC output is disabled if the clock is provided directly from the INTRC output. The INTOSC output is also enabled for TwoSpeed Start-up at 1 MHz after Resets and when configured for wake from Sleep mode. If the Sleep mode is selected, all clock sources are stopped. Since all the transistor switching currents have been stopped, Sleep mode achieves the lowest current consumption of the device (only leakage currents). Enabling any on-chip feature that will operate during Sleep will increase the current consumed during Sleep. The INTRC is required to support WDT operation. The Timer1 oscillator may be operating to support a realtime clock. Other features may be operating that do not require a device clock source (i.e., SSP slave, PSP, INTn pins and others). Peripherals that may add significant current consumption are listed in Section 28.2 "DC Characteristics". TABLE 2-3: 2.9 Power-up Delays Power-up delays are controlled by two or three timers, so that no external Reset circuitry is required for most applications. The delays ensure that the device is kept in Reset until the device power supply is stable under normal circumstances and the primary clock is operating and stable. For additional information on power-up delays, see Section 4.5 "Device Reset Timers". The first timer is the Power-up Timer (PWRT) which provides a fixed delay on power-up (parameter 33, Table 28-12). It is enabled by clearing (= 0) the PWRTEN configuration bit (CONFIG2L<0>). 2.9.1 DELAYS FOR POWER-UP AND RETURN TO PRIMARY CLOCK The second timer is the Oscillator Start-up Timer (OST), intended to delay execution until the crystal oscillator is stable (LP, XT and HS modes). The OST does this by counting 1024 oscillator cycles before allowing the oscillator to clock the device. When the HSPLL Oscillator mode is selected, a third timer delays execution for an additional 2 ms following the HS mode OST delay, so the PLL can lock to the incoming clock frequency. At the end of these delays, the OSTS bit (OSCCON<3>) is set. There is a delay of interval TCSD (parameter 38, Table 28-12), once execution is allowed to start, when the controller becomes ready to execute instructions. This delay runs concurrently with any other delays. This may be the only delay that occurs when any of the EC, RC or INTIO modes are used as the primary clock source. OSC1 AND OSC2 PIN STATES IN SLEEP MODE OSC Mode OSC1 Pin OSC2 Pin RC, INTIO1 Floating, external resistor pulls high At logic low (clock/4 output) RCIO Floating, external resistor pulls high Configured as PORTA, bit 6 INTIO2 Configured as PORTA, bit 7 Configured as PORTA, bit 6 ECIO Floating, driven by external clock Configured as PORTA, bit 6 EC Floating, driven by external clock At logic low (clock/4 output) LP, XT and HS Feedback inverter disabled at quiescent voltage level Feedback inverter disabled at quiescent voltage level Note: See Table 4-2 in Section 4.0 "Reset" for time-outs due to Sleep and MCLR Reset. DS39646B-page 40 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY 3.0 POWER-MANAGED MODES 3.1.1 The PIC18F8722 family of devices offers a total of seven operating modes for more efficient power management. These modes provide a variety of options for selective power conservation in applications where resources may be limited (i.e., battery-powered devices). CLOCK SOURCES The SCS1:SCS0 bits allow the selection of one of three clock sources for power-managed modes. They are: * the primary clock, as defined by the FOSC3:FOSC0 configuration bits * the secondary clock (the Timer1 oscillator) * the internal oscillator block (for INTOSC modes) There are three categories of power-managed modes: 3.1.2 * Run modes * Idle modes * Sleep mode These categories define which portions of the device are clocked and sometimes, what speed. The Run and Idle modes may use any of the three available clock sources (primary, secondary or internal oscillator block); the Sleep mode does not use a clock source. The power-managed modes include several powersaving features offered on previous PICmicro devices. One is the clock switching feature, offered in other PIC18 devices, allowing the controller to use the Timer1 oscillator in place of the primary oscillator. Also included is the Sleep mode, offered by all PICmicro devices, where all device clocks are stopped. 3.1 Selecting Power-Managed Modes Selecting a power-managed mode requires two decisions: if the CPU is to be clocked or not and the selection of a clock source. The IDLEN bit (OSCCON<7>) controls CPU clocking, while the SCS1:SCS0 bits (OSCCON<1:0>) select the clock source. The individual modes, bit settings, clock sources and affected modules are summarized in Table 3-1. TABLE 3-1: Switching from one power-managed mode to another begins by loading the OSCCON register. The SCS1:SCS0 bits select the clock source and determine which Run or Idle mode is to be used. Changing these bits causes an immediate switch to the new clock source, assuming that it is running. The switch may also be subject to clock transition delays. These are discussed in Section 3.1.3 "Clock Transitions and Status Indicators" and subsequent sections. Entry to the power-managed Idle or Sleep modes is triggered by the execution of a SLEEP instruction. The actual mode that results depends on the status of the IDLEN bit. Depending on the current mode and the mode being switched to, a change to a power-managed mode does not always require setting all of these bits. Many transitions may be done by changing the oscillator select bits, or changing the IDLEN bit, prior to issuing a SLEEP instruction. If the IDLEN bit is already configured correctly, it may only be necessary to perform a SLEEP instruction to switch to the desired mode. POWER-MANAGED MODES OSCCON Bits Mode ENTERING POWER-MANAGED MODES Module Clocking Available Clock and Oscillator Source IDLEN<7>(1) SCS<1:0> CPU Peripherals 0 N/A Off Off N/A 00 Clocked Clocked SEC_RUN N/A 01 Clocked Clocked Secondary - Timer1 Oscillator RC_RUN N/A 1x Clocked Clocked Internal Oscillator Block(2) PRI_IDLE 1 00 Off Clocked Primary - LP, XT, HS, HSPLL, RC, EC SEC_IDLE 1 01 Off Clocked Secondary - Timer1 Oscillator RC_IDLE 1 1x Off Clocked Internal Oscillator Block(2) Sleep PRI_RUN Note 1: 2: None - All clocks are disabled Primary - LP, XT, HS, HSPLL, RC, EC and Internal Oscillator Block(2). This is the normal full power execution mode. IDLEN reflects its value when the SLEEP instruction is executed. Includes INTOSC and INTOSC postscaler, as well as the INTRC source. 2004 Microchip Technology Inc. Preliminary DS39646B-page 41 PIC18F8722 FAMILY 3.1.3 CLOCK TRANSITIONS AND STATUS INDICATORS The length of the transition between clock sources is the sum of two cycles of the old clock source and three to four cycles of the new clock source. This formula assumes that the new clock source is stable. Three bits indicate the current clock source and its status. They are: * OSTS (OSCCON<3>) * IOFS (OSCCON<2>) * T1RUN (T1CON<6>) In general, only one of these bits will be set while in a given power-managed mode. When the OSTS bit is set, the primary clock is providing the device clock. When the IOFS bit is set, the INTOSC output is providing a stable 8 MHz clock source to a divider that actually drives the device clock. When the T1RUN bit is set, the Timer1 oscillator is providing the clock. If none of these bits are set, then either the INTRC clock source is clocking the device, or the INTOSC source is not yet stable. If the internal oscillator block is configured as the primary clock source by the FOSC3:FOSC0 configuration bits, then both the OSTS and IOFS bits may be set when in PRI_RUN or PRI_IDLE modes. This indicates that the primary clock (INTOSC output) is generating a stable 8 MHz output. Entering another INTOSC powermanaged mode at the same frequency would clear the OSTS bit. 3.2 In the Run modes, clocks to both the core and peripherals are active. The difference between these modes is the clock source. 3.2.1 3.1.4 MULTIPLE SLEEP COMMANDS The power-managed mode that is invoked with the SLEEP instruction is determined by the setting of the IDLEN bit at the time the instruction is executed. If another SLEEP instruction is executed, the device will enter the power-managed mode specified by IDLEN at that time. If IDLEN has changed, the device will enter the new power-managed mode specified by the new setting. DS39646B-page 42 PRI_RUN MODE The PRI_RUN mode is the normal, full power execution mode of the microcontroller. This is also the default mode upon a device Reset, unless Two-Speed Start-up is enabled (see Section 25.3 "Two-Speed Start-up" for details). In this mode, the OSTS bit is set. The IOFS bit may be set if the internal oscillator block is the primary clock source (see Section 2.7.1 "Oscillator Control Register"). 3.2.2 SEC_RUN MODE The SEC_RUN mode is the compatible mode to the "clock switching" feature offered in other PIC18 devices. In this mode, the CPU and peripherals are clocked from the Timer1 oscillator. This gives users the option of lower power consumption while still using a high accuracy clock source. SEC_RUN mode is entered by setting the SCS1:SCS0 bits to `01'. The device clock source is switched to the Timer1 oscillator (see Figure 3-1), the primary oscillator is shut down, the T1RUN bit (T1CON<6>) is set and the OSTS bit is cleared. Note: Note 1: Caution should be used when modifying a single IRCF bit. If VDD is less than 3V, it is possible to select a higher clock speed than is supported by the low VDD. Improper device operation may result if the VDD/FOSC specifications are violated. 2: Executing a SLEEP instruction does not necessarily place the device into Sleep mode. It acts as the trigger to place the controller into either the Sleep mode or one of the Idle modes, depending on the setting of the IDLEN bit. Run Modes The Timer1 oscillator should already be running prior to entering SEC_RUN mode. If the T1OSCEN bit is not set when the SCS1:SCS0 bits are set to `01', entry to SEC_RUN mode will not occur. If the Timer1 oscillator is enabled, but not yet running, device clocks will be delayed until the oscillator has started; in such situations, initial oscillator operation is far from stable and unpredictable operation may result. On transitions from SEC_RUN mode to PRI_RUN, the peripherals and CPU continue to be clocked from the Timer1 oscillator while the primary clock is started. When the primary clock becomes ready, a clock switch back to the primary clock occurs (see Figure 3-2). When the clock switch is complete, the T1RUN bit is cleared, the OSTS bit is set and the primary clock is providing the clock. The IDLEN and SCS bits are not affected by the wake-up; the Timer1 oscillator continues to run. Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY FIGURE 3-1: TRANSITION TIMING FOR ENTRY TO SEC_RUN MODE Q1 Q2 Q3 Q4 Q1 Q2 1 T1OSI 2 3 n-1 Q3 Q4 Q1 Q2 Q3 n Clock Transition(1) OSC1 CPU Clock Peripheral Clock Program Counter PC PC + 2 PC + 4 Note 1: Clock transition typically occurs within 2-4 TOSC. FIGURE 3-2: TRANSITION TIMING FROM SEC_RUN MODE TO PRI_RUN MODE (HSPLL) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 T1OSI OSC1 TOST(1) TPLL(1) 1 PLL Clock Output 2 n-1 n Clock Transition(2) CPU Clock Peripheral Clock Program Counter SCS1:SCS0 bits Changed PC + 2 PC PC + 4 OSTS bit Set Note1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale. 2: Clock transition typically occurs within 2-4 TOSC. 3.2.3 RC_RUN MODE In RC_RUN mode, the CPU and peripherals are clocked from the internal oscillator block using the INTOSC multiplexer. In this mode, the primary clock is shut down. When using the INTRC source, this mode provides the best power conservation of all the Run modes, while still executing code. It works well for user applications which are not highly timing sensitive or do not require high-speed clocks at all times. This mode is entered by setting the SCS1 bit to `1'. Although it is ignored, it is recommended that the SCS0 bit also be cleared; this is to maintain software compatibility with future devices. When the clock source is switched to the INTOSC multiplexer (see Figure 3-3), the primary oscillator is shut down and the OSTS bit is cleared. The IRCF bits may be modified at any time to immediately change the clock speed. Note: If the primary clock source is the internal oscillator block (either INTRC or INTOSC), there are no distinguishable differences between PRI_RUN and RC_RUN modes during execution. However, a clock switch delay will occur during entry to and exit from RC_RUN mode. Therefore, if the primary clock source is the internal oscillator block, the use of RC_RUN mode is not recommended. 2004 Microchip Technology Inc. Preliminary Caution should be used when modifying a single IRCF bit. If VDD is less than 3V, it is possible to select a higher clock speed than is supported by the low VDD. Improper device operation may result if the VDD/FOSC specifications are violated. DS39646B-page 43 PIC18F8722 FAMILY If the IRCF bits and the INTSRC bit are all clear, the INTOSC output is not enabled and the IOFS bit will remain clear; there will be no indication of the current clock source. The INTRC source is providing the device clocks. On transitions from RC_RUN mode to PRI_RUN mode, the device continues to be clocked from the INTOSC multiplexer while the primary clock is started. When the primary clock becomes ready, a clock switch to the primary clock occurs (see Figure 3-4). When the clock switch is complete, the IOFS bit is cleared, the OSTS bit is set and the primary clock is providing the device clock. The IDLEN and SCS bits are not affected by the switch. The INTRC source will continue to run if either the WDT or the Fail-Safe Clock Monitor is enabled. If the IRCF bits are changed from all clear (thus, enabling the INTOSC output) or if INTSRC is set, the IOFS bit becomes set after the INTOSC output becomes stable. Clocks to the device continue while the INTOSC source stabilizes after an interval of TIOBST (parameter 39, Table 28-12). If the IRCF bits were previously at a non-zero value, or if INTSRC was set before setting SCS1 and the INTOSC source was already stable, the IOFS bit will remain set. FIGURE 3-3: TRANSITION TIMING TO RC_RUN MODE Q1 Q2 Q3 Q4 Q1 Q2 1 INTRC 2 3 n-1 Q3 Q4 Q1 Q2 Q3 n Clock Transition(1) OSC1 CPU Clock Peripheral Clock Program Counter PC PC + 2 PC + 4 Note 1: Clock transition typically occurs within 2-4 TOSC. FIGURE 3-4: TRANSITION TIMING FROM RC_RUN MODE TO PRI_RUN MODE Q1 Q2 Q3 Q4 Q2 Q3 Q4 Q1 Q2 Q3 Q1 INTOSC Multiplexer OSC1 TOST(1) TPLL(1) 1 PLL Clock Output 2 n-1 n Clock Transition(2) CPU Clock Peripheral Clock Program Counter SCS1:SCS0 bits Changed PC + 2 PC PC + 4 OSTS bit Set Note1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale. 2: Clock transition typically occurs within 2-4 TOSC. DS39646B-page 44 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY 3.3 Sleep Mode 3.4 The power-managed Sleep mode in the PIC18F8722 family of devices is identical to the legacy Sleep mode offered in all other PICmicro devices. It is entered by clearing the IDLEN bit (the default state on device Reset) and executing the SLEEP instruction. This shuts down the selected oscillator (Figure 3-5). All clock source status bits are cleared. Idle Modes The Idle modes allow the controller's CPU to be selectively shut down while the peripherals continue to operate. Selecting a particular Idle mode allows users to further manage power consumption. If the IDLEN bit is set to a `1' when a SLEEP instruction is executed, the peripherals will be clocked from the clock source selected using the SCS1:SCS0 bits; however, the CPU will not be clocked. The clock source status bits are not affected. Setting IDLEN and executing a SLEEP instruction provides a quick method of switching from a given Run mode to its corresponding Idle mode. Entering the Sleep mode from any other mode does not require a clock switch. This is because no clocks are needed once the controller has entered Sleep. If the WDT is selected, the INTRC source will continue to operate. If the Timer1 oscillator is enabled, it will also continue to run. If the WDT is selected, the INTRC source will continue to operate. If the Timer1 oscillator is enabled, it will also continue to run. When a wake event occurs in Sleep mode (by interrupt, Reset or WDT time-out), the device will not be clocked until the clock source selected by the SCS1:SCS0 bits becomes ready (see Figure 3-6), or it will be clocked from the internal oscillator block if either the TwoSpeed Start-up or the Fail-Safe Clock Monitor are enabled (see Section 25.0 "Special Features of the CPU"). In either case, the OSTS bit is set when the primary clock is providing the device clocks. The IDLEN and SCS bits are not affected by the wake-up. Since the CPU is not executing instructions, the only exits from any of the Idle modes are by interrupt, WDT time-out or a Reset. When a wake event occurs, CPU execution is delayed by an interval of TCSD (parameter 38, Table 28-12) while it becomes ready to execute code. When the CPU begins executing code, it resumes with the same clock source for the current Idle mode. For example, when waking from RC_IDLE mode, the internal oscillator block will clock the CPU and peripherals (in other words, RC_RUN mode). The IDLEN and SCS bits are not affected by the wake-up. While in any Idle mode or the Sleep mode, a WDT time-out will result in a WDT wake-up to the Run mode currently specified by the SCS1:SCS0 bits. FIGURE 3-5: TRANSITION TIMING FOR ENTRY TO SLEEP MODE Q1 Q2 Q3 Q4 Q1 OSC1 CPU Clock Peripheral Clock Sleep Program Counter PC FIGURE 3-6: PC + 2 TRANSITION TIMING FOR WAKE FROM SLEEP (HSPLL) Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 OSC1 TOST(1) PLL Clock Output TPLL(1) CPU Clock Peripheral Clock Program Counter PC + 2 PC Wake Event PC + 4 PC + 6 OSTS bit Set Note1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale. 2004 Microchip Technology Inc. Preliminary DS39646B-page 45 PIC18F8722 FAMILY 3.4.1 PRI_IDLE MODE 3.4.2 This mode is unique among the three low-power Idle modes, in that it does not disable the primary device clock. For timing sensitive applications, this allows for the fastest resumption of device operation with its more accurate primary clock source, since the clock source does not have to "warm-up" or transition from another oscillator. PRI_IDLE mode is entered from PRI_RUN mode by setting the IDLEN bit and executing a SLEEP instruction. If the device is in another Run mode, set IDLEN first, then clear the SCS bits and execute SLEEP. Although the CPU is disabled, the peripherals continue to be clocked from the primary clock source specified by the FOSC3:FOSC0 configuration bits. The OSTS bit remains set (see Figure 3-7). In SEC_IDLE mode, the CPU is disabled but the peripherals continue to be clocked from the Timer1 oscillator. This mode is entered from SEC_RUN by setting the IDLEN bit and executing a SLEEP instruction. If the device is in another Run mode, set the IDLEN bit first, then set the SCS1:SCS0 bits to `01' and execute SLEEP. When the clock source is switched to the Timer1 oscillator, the primary oscillator is shut down, the OSTS bit is cleared and the T1RUN bit is set. When a wake event occurs, the peripherals continue to be clocked from the Timer1 oscillator. After an interval of TCSD following the wake event, the CPU begins executing code being clocked by the Timer1 oscillator. The IDLEN and SCS bits are not affected by the wake-up; the Timer1 oscillator continues to run (see Figure 3-8). When a wake event occurs, the CPU is clocked from the primary clock source. A delay of interval TCSD (parameter 39, Table 28-12) is required between the wake event and when code execution starts. This is required to allow the CPU to become ready to execute instructions. After the wake-up, the OSTS bit remains set. The IDLEN and SCS bits are not affected by the wake-up (see Figure 3-8). FIGURE 3-7: SEC_IDLE MODE Note: The Timer1 oscillator should already be running prior to entering SEC_IDLE mode. If the T1OSCEN bit is not set when the SLEEP instruction is executed, the SLEEP instruction will be ignored and entry to SEC_IDLE mode will not occur. If the Timer1 oscillator is enabled but not yet running, peripheral clocks will be delayed until the oscillator has started. In such situations, initial oscillator operation is far from stable and unpredictable operation may result. TRANSITION TIMING FOR ENTRY TO IDLE MODE Q1 Q4 Q3 Q2 Q1 OSC1 CPU Clock Peripheral Clock Program Counter PC FIGURE 3-8: PC + 2 TRANSITION TIMING FOR WAKE FROM IDLE TO RUN MODE Q1 Q2 Q3 Q4 OSC1 TCSD CPU Clock Peripheral Clock Program Counter PC Wake Event DS39646B-page 46 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY 3.4.3 RC_IDLE MODE In RC_IDLE mode, the CPU is disabled but the peripherals continue to be clocked from the internal oscillator block using the INTOSC multiplexer. This mode allows for controllable power conservation during Idle periods. From RC_RUN, this mode is entered by setting the IDLEN bit and executing a SLEEP instruction. If the device is in another Run mode, first set IDLEN, then set the SCS1 bit and execute SLEEP. Although its value is ignored, it is recommended that SCS0 also be cleared; this is to maintain software compatibility with future devices. The INTOSC multiplexer may be used to select a higher clock frequency by modifying the IRCF bits before executing the SLEEP instruction. When the clock source is switched to the INTOSC multiplexer, the primary oscillator is shut down and the OSTS bit is cleared. If the IRCF bits are set to any non-zero value, or the INTSRC bit is set, the INTOSC output is enabled. The IOFS bit becomes set, after the INTOSC output becomes stable, after an interval of TIOBST (parameter 39, Table 28-12). Clocks to the peripherals continue while the INTOSC source stabilizes. If the IRCF bits were previously at a non-zero value, or INTSRC was set before the SLEEP instruction was executed and the INTOSC source was already stable, the IOFS bit will remain set. If the IRCF bits and INTSRC are all clear, the INTOSC output will not be enabled, the IOFS bit will remain clear and there will be no indication of the current clock source. When a wake event occurs, the peripherals continue to be clocked from the INTOSC multiplexer. After a delay of TCSD (parameter 38, Table 28-12) following the wake event, the CPU begins executing code being clocked by the INTOSC multiplexer. The IDLEN and SCS bits are not affected by the wake-up. The INTRC source will continue to run if either the WDT or the Fail-Safe Clock Monitor is enabled. 3.5 Exiting Idle and Sleep Modes An exit from Sleep mode or any of the Idle modes is triggered by an interrupt, a Reset or a WDT time-out. This section discusses the triggers that cause exits from power-managed modes. The clocking subsystem actions are discussed in each of the power-managed modes (see Section 3.2 "Run Modes", Section 3.3 "Sleep Mode" and Section 3.4 "Idle Modes"). 3.5.1 EXIT BY INTERRUPT Any of the available interrupt sources can cause the device to exit from an Idle mode or the Sleep mode to a Run mode. To enable this functionality, an interrupt source must be enabled by setting its enable bit in one of the INTCON or PIE registers. The exit sequence is initiated when the corresponding interrupt flag bit is set. 2004 Microchip Technology Inc. On all exits from Idle or Sleep modes by interrupt, code execution branches to the interrupt vector if the GIE/ GIEH bit (INTCON<7>) is set. Otherwise, code execution continues or resumes without branching (see Section 10.0 "Interrupts"). A fixed delay of interval TCSD following the wake event is required when leaving Sleep and Idle modes. This delay is required for the CPU to prepare for execution. Instruction execution resumes on the first clock cycle following this delay. 3.5.2 EXIT BY WDT TIME-OUT A WDT time-out will cause different actions depending on which power-managed mode the device is in when the time-out occurs. If the device is not executing code (all Idle modes and Sleep mode), the time-out will result in an exit from the power-managed mode (see Section 3.2 "Run Modes" and Section 3.3 "Sleep Mode"). If the device is executing code (all Run modes), the time-out will result in a WDT Reset (see Section 25.2 "Watchdog Timer (WDT)"). The WDT timer and postscaler are cleared by executing a SLEEP or CLRWDT instruction, the loss of a currently selected clock source (if the Fail-Safe Clock Monitor is enabled) and modifying the IRCF bits in the OSCCON register if the internal oscillator block is the device clock source. 3.5.3 EXIT BY RESET Normally, the device is held in Reset by the Oscillator Start-up Timer (OST) until the primary clock becomes ready. At that time, the OSTS bit is set and the device begins executing code. If the internal oscillator block is the new clock source, the IOFS bit is set instead. The exit delay time from Reset to the start of code execution depends on both the clock sources before and after the wake-up and the type of oscillator if the new clock source is the primary clock. Exit delays are summarized in Table 3-2. Code execution can begin before the primary clock becomes ready. If either the Two-Speed Start-up (see Section 25.3 "Two-Speed Start-up") or Fail-Safe Clock Monitor (see Section 25.4 "Fail-Safe Clock Monitor") is enabled, the device may begin execution as soon as the Reset source has cleared. Execution is clocked by the INTOSC multiplexer driven by the internal oscillator block. Execution is clocked by the internal oscillator block until either the primary clock becomes ready or a power-managed mode is entered before the primary clock becomes ready; the primary clock is then shut down. Preliminary DS39646B-page 47 PIC18F8722 FAMILY 3.5.4 EXIT WITHOUT AN OSCILLATOR START-UP DELAY Certain exits from power-managed modes do not invoke the OST at all. There are two cases: * PRI_IDLE mode, where the primary clock source is not stopped and * the primary clock source is not any of the LP, XT, HS or HSPLL modes. TABLE 3-2: In these instances, the primary clock source either does not require an oscillator start-up delay since it is already running (PRI_IDLE), or normally does not require an oscillator start-up delay (RC, EC and INTIO Oscillator modes). However, a fixed delay of interval TCSD following the wake event is still required when leaving Sleep and Idle modes to allow the CPU to prepare for execution. Instruction execution resumes on the first clock cycle following this delay. EXIT DELAY ON WAKE-UP BY RESET FROM SLEEP MODE OR ANY IDLE MODE (BY CLOCK SOURCES) Clock Source before Wake-up Clock Source after Wake-up Exit Delay Clock Ready Status Bit (OSCCON) LP, XT, HS Primary Device Clock (PRI_IDLE mode) HSPLL EC, RC TCSD(1) INTOSC(2) T1OSC or INTRC INTOSC(2) None (Sleep mode) 2: 3: 4: IOFS LP, XT, HS TOST(3) HSPLL TOST + trc(3) OSTS EC, RC INTOSC(2) TCSD(1) TIOBST(4) IOFS LP, XT, HS TOST(4) HSPLL TOST + trc(3) OSTS EC, RC TCSD(1) INTOSC(2) None LP, XT, HS TOST(3) HSPLL TOST + trc(3) OSTS EC, RC TCSD(1) TIOBST(4) IOFS INTOSC(2) Note 1: OSTS IOFS TCSD (parameter 38, Table 28-12) is a required delay when waking from Sleep and all Idle modes and runs concurrently with any other required delays (see Section 3.4 "Idle Modes"). Includes both the INTOSC 8 MHz source and postscaler derived frequencies. On Reset, INTOSC defaults to 1 MHz. TOST is the Oscillator Start-up Timer (parameter 32, Table 28-12). trc is the PLL Lock-out Timer (parameter F12, Table 28-7); it is also designated as TPLL. Execution continues during TIOBST (parameter 39, Table 28-12), the INTOSC stabilization period. DS39646B-page 48 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY 4.0 RESET A simplified block diagram of the On-Chip Reset Circuit is shown in Figure 4-1. The PIC18F8722 family of devices differentiates between various kinds of Reset: a) b) c) d) e) f) g) h) Power-on Reset (POR) MCLR Reset during normal operation MCLR Reset during power-managed modes Watchdog Timer (WDT) Reset (during execution) Programmable Brown-out Reset (BOR) RESET Instruction Stack Full Reset Stack Underflow Reset RCON Register Device Reset events are tracked through the RCON register (Register 4-1). The lower five bits of the register indicate that a specific Reset event has occurred. In most cases, these bits can only be cleared by the event and must be set by the application after the event. The state of these flag bits, taken together, can be read to indicate the type of Reset that just occurred. This is described in more detail in Section 4.6 "Reset State of Registers". This section discusses Resets generated by MCLR, POR and BOR and covers the operation of the various start-up timers. Stack Reset events are covered in Section 5.1.3.4 "Stack Full and Underflow Resets". WDT Resets are covered in Section 25.2 "Watchdog Timer (WDT)". FIGURE 4-1: 4.1 The RCON register also has control bits for setting interrupt priority (IPEN) and software control of the BOR (SBOREN). Interrupt priority is discussed in Section 10.0 "Interrupts". BOR is covered in Section 4.4 "Brown-out Reset (BOR)". SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT RESET Instruction Stack Full/Underflow Reset Stack Pointer External Reset MCLR MCLRE ( )_IDLE Sleep WDT Time-out VDD Rise Detect POR Pulse VDD Brown-out Reset S BOREN OST/PWRT OST 1024 Cycles Chip_Reset 10-bit Ripple Counter R Q OSC1 31 s INTRC(1) PWRT 64 ms 11-bit Ripple Counter Enable PWRT Enable OST(2) Note 1: 2: This is the INTRC source from the internal oscillator block and is separate from the RC oscillator of the CLKI pin. See Table 4-2 for time-out situations. 2004 Microchip Technology Inc. Preliminary DS39646B-page 49 PIC18F8722 FAMILY REGISTER 4-1: RCON: RESET CONTROL REGISTER R/W-0 R/W-1(1) U-0 R/W-1 R-1 R-1 R/W-0(2) R/W-0 IPEN SBOREN -- RI TO PD POR BOR bit 7 bit 0 bit 7 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode) bit 6 SBOREN: BOR Software Enable bit(1) If BOREN1:BOREN0 = 01: 1 = BOR is enabled 0 = BOR is disabled If BOREN1:BOREN0 = 00, 10 or 11: Bit is disabled and read as `0'. bit 5 Unimplemented: Read as `0' bit 4 RI: RESET Instruction Flag bit 1 = The RESET instruction was not executed (set by firmware only) 0 = The RESET instruction was executed causing a device Reset (must be set in software after a Brown-out Reset occurs) bit 3 TO: Watchdog Time-out Flag bit 1 = Set by power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT time-out occurred bit 2 PD: Power-down Detection Flag bit 1 = Set by power-up or by the CLRWDT instruction 0 = Set by execution of the SLEEP instruction bit 1 POR: Power-on Reset Status bit(2) 1 = A Power-on Reset has not occurred (set by firmware only) 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0 BOR: Brown-out Reset Status bit 1 = A Brown-out Reset has not occurred (set by firmware only) 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) Note 1: If SBOREN is enabled, its Reset state is `1'; otherwise, it is `0'. 2: The actual Reset value of POR is determined by the type of device Reset. See the notes following this register and Section 4.6 "Reset State of Registers" for additional information. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown Note 1: It is recommended that the POR bit be set after a Power-on Reset has been detected so that subsequent Power-on Resets may be detected. 2: Brown-out Reset is said to have occurred when BOR is `0' and POR is `1' (assuming that POR was set to `1' by software immediately after POR). DS39646B-page 50 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY 4.2 FIGURE 4-2: Master Clear (MCLR) The MCLR pin provides a method for triggering an external Reset of the device. A Reset is generated by holding the pin low. These devices have a noise filter in the MCLR Reset path which detects and ignores small pulses. In the PIC18F8722 family of devices, the MCLR input can be disabled with the MCLRE configuration bit. When MCLR is disabled, the pin becomes a digital input. See Section 11.5 "PORTE, TRISE and LATE Registers" for more information. 4.3 VDD VDD The MCLR pin is not driven low by any internal Resets, including the WDT. EXTERNAL POWER-ON RESET CIRCUIT (FOR SLOW VDD POWER-UP)(1) D R(2) R1(3) MCLR C PIC18FXXXX Note 1: External Power-on Reset circuit is required only if the VDD power-up slope is too slow. The diode D helps discharge the capacitor quickly when VDD powers down. 2: R < 40 k is recommended to make sure that the voltage drop across R does not violate the device's electrical specification. 3: R1 1 k will limit any current flowing into MCLR from external capacitor C, in the event of MCLR/VPP pin breakdown, due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS). Power-on Reset (POR) A Power-on Reset pulse is generated on-chip whenever VDD rises above a certain threshold. This allows the device to start in the initialized state when VDD is adequate for operation. To take advantage of the POR circuitry, tie the MCLR pin through a resistor (1 k to 10 k) to VDD. This will eliminate external RC components usually needed to create a Power-on Reset delay. A minimum rise rate for VDD is specified (parameter D004, "Section 28.2 "DC Characteristics: Power-Down and Supply Current"). For a slow rise time, see Figure 4-2. When the device starts normal operation (i.e., exits the Reset condition), device operating parameters (voltage, frequency, temperature, etc.) must be met to ensure operation. If these conditions are not met, the device must be held in Reset until the operating conditions are met. POR events are captured by the POR bit (RCON<1>). The state of the bit is set to `0' whenever a POR occurs; it does not change for any other Reset event. POR is not reset to `1' by any hardware event. To capture multiple events, the user manually resets the bit to `1' in software following any POR. 2004 Microchip Technology Inc. Preliminary DS39646B-page 51 PIC18F8722 FAMILY 4.4 Brown-out Reset (BOR) The PIC18F8722 family of devices implements a BOR circuit that provides the user with a number of configuration and power-saving options. The BOR is controlled by the BORV1:BORV0 and BOREN1:BOREN0 configuration bits. There are a total of four BOR configurations which are summarized in Table 4-1. The BOR threshold is set by the BORV1:BORV0 bits. If BOR is enabled (any values of BOREN1:BOREN0, except `00'), any drop of VDD below VBOR (parameter D005, Section 28.1 "DC Characteristics") for greater than TBOR (parameter 35, Table 28-12) will reset the device. A Reset may or may not occur if VDD falls below VBOR for less than TBOR. The chip will remain in Brown-out Reset until VDD rises above VBOR. If the Power-up Timer is enabled, it will be invoked after VDD rises above VBOR; it then will keep the chip in Reset for an additional time delay, TPWRT (parameter 33, Table 28-12). If VDD drops below VBOR while the Power-up Timer is running, the chip will go back into a Brown-out Reset and the Power-up Timer will be initialized. Once VDD rises above VBOR, the Power-up Timer will execute the additional time delay. BOR and the Power-on Timer (PWRT) are independently configured. Enabling BOR Reset does not automatically enable the PWRT. 4.4.1 SOFTWARE ENABLED BOR When BOREN1:BOREN0 = 01, the BOR can be enabled or disabled by the user in software. This is done with the control bit, SBOREN (RCON<6>). Setting SBOREN enables the BOR to function as previously described. Clearing SBOREN disables the BOR entirely. The SBOREN bit operates only in this mode; otherwise it is read as `0'. TABLE 4-1: Placing the BOR under software control gives the user the additional flexibility of tailoring the application to its environment without having to reprogram the device to change the BOR configuration. It also allows the user to tailor device power consumption in software by eliminating the incremental current that the BOR consumes. While the BOR current is typically very small, it may have some impact in low-power applications. Note: 4.4.2 Even when BOR is under software control, the BOR Reset voltage level is still set by the BORV1:BORV0 configuration bits. It cannot be changed in software. DETECTING BOR When BOR is enabled, the BOR bit always resets to `0' on any BOR or POR event. This makes it difficult to determine if a BOR event has occurred just by reading the state of BOR alone. A more reliable method is to simultaneously check the state of both POR and BOR. This assumes that the POR bit is reset to `1' in software immediately after any POR event. If BOR is `0' while POR is `1', it can be reliably assumed that a BOR event has occurred. 4.4.3 DISABLING BOR IN SLEEP MODE When BOREN1:BOREN0 = 10, the BOR remains under hardware control and operates as previously described. Whenever the device enters Sleep mode, however, the BOR is automatically disabled. When the device returns to any other operating mode, BOR is automatically re-enabled. This mode allows for applications to recover from brown-out situations, while actively executing code, when the device requires BOR protection the most. At the same time, it saves additional power in Sleep mode by eliminating the small incremental BOR current. BOR CONFIGURATIONS BOR Configuration BOREN1 BOREN0 Status of SBOREN (RCON<6>) 0 0 Unavailable 0 1 Available 1 0 Unavailable BOR enabled in hardware in Run and Idle modes, disabled during Sleep mode. 1 1 Unavailable BOR enabled in hardware; must be disabled by reprogramming the configuration bits. DS39646B-page 52 BOR Operation BOR disabled; must be enabled by reprogramming the configuration bits. BOR enabled in software; operation controlled by SBOREN. Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY 4.5 4.5.3 Device Reset Timers The PIC18F8722 family of devices incorporates three separate on-chip timers that help regulate the Power-on Reset process. Their main function is to ensure that the device clock is stable before code is executed. These timers are: * Power-up Timer (PWRT) * Oscillator Start-up Timer (OST) * PLL Lock Time-out 4.5.1 With the PLL enabled in its PLL mode, the time-out sequence following a Power-on Reset is slightly different from other oscillator modes. A separate timer is used to provide a fixed time-out that is sufficient for the PLL to lock to the main oscillator frequency. This PLL lock time-out (TPLL) is typically 2 ms and follows the oscillator start-up time-out. 4.5.4 TIME-OUT SEQUENCE On power-up, the time-out sequence is as follows: POWER-UP TIMER (PWRT) The Power-up Timer (PWRT) of the PIC18F8722 family of devices is an 11-bit counter which uses the INTRC source as the clock input. While the PWRT is counting, the device is held in Reset. The power-up time delay depends on the INTRC clock and will vary from chip-to-chip due to temperature and process variation. See DC parameter 33 in Table 28-12 for details. The PWRT is enabled by clearing the PWRTEN configuration bit. 4.5.2 PLL LOCK TIME-OUT OSCILLATOR START-UP TIMER (OST) The Oscillator Start-up Timer (OST) provides a 1024 oscillator cycle (from OSC1 input) delay after the PWRT delay is over (parameter 33, Table 28-12). This ensures that the crystal oscillator or resonator has started and stabilized. 1. 2. After the POR pulse has cleared, PWRT time-out is invoked (if enabled). Then, the OST is activated. The total time-out will vary based on oscillator configuration and the status of the PWRT. Figure 4-3, Figure 4-4, Figure 4-5, Figure 4-6 and Figure 4-7 all depict time-out sequences on power-up, with the Power-up Timer enabled and the device operating in HS Oscillator mode. Figures 4-3 through 4-6 also apply to devices operating in XT or LP modes. For devices in RC mode and with the PWRT disabled, on the other hand, there will be no time-out at all. Since the time-outs occur from the POR pulse, if MCLR is kept low long enough, all time-outs will expire. Bringing MCLR high will begin execution immediately (Figure 4-5). This is useful for testing purposes or to synchronize more than one PIC18F8722 family device operating in parallel. The OST time-out is invoked only for XT, LP, HS and HSPLL modes and only on Power-on Reset, or on exit from most power-managed modes. TABLE 4-2: TIME-OUT IN VARIOUS SITUATIONS Power-up(2) and Brown-out Oscillator Configuration HSPLL PWRTEN = 1 Exit from Power-Managed Mode 1024 TOSC + TPLL(2) 1024 TOSC + TPLL(2) PWRTEN = 0 TPWRT (1) + 1024 TOSC + TPLL(2) HS, XT, LP TPWRT(1) + 1024 TOSC 1024 TOSC 1024 TOSC EC, ECIO TPWRT(1) -- -- RC, RCIO TPWRT(1) TPWRT(1) -- -- -- -- INTIO1, INTIO2 Note 1: See parameter 33, Table 28-12. 2: 2 ms is the nominal time required for the PLL to lock. 2004 Microchip Technology Inc. Preliminary DS39646B-page 53 PIC18F8722 FAMILY FIGURE 4-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD, VDD RISE < TPWRT) VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1 FIGURE 4-4: VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 FIGURE 4-5: VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET DS39646B-page 54 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY FIGURE 4-6: SLOW RISE TIME (MCLR TIED TO VDD, VDD RISE > TPWRT) VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET TIME-OUT SEQUENCE ON POR w/PLL ENABLED (MCLR TIED TO VDD) FIGURE 4-7: VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST TPLL OST TIME-OUT PLL TIME-OUT INTERNAL RESET Note: TOST = 1024 clock cycles. TPLL 2 ms is the nominal time required for the PLL to lock. 2004 Microchip Technology Inc. Preliminary DS39646B-page 55 PIC18F8722 FAMILY 4.6 Reset State of Registers Most registers are unaffected by a Reset. Their status is unknown on POR and unchanged by all other Resets. All other registers are forced to a "Reset state" depending on the type of Reset that occurred. Table 4-4 describes the Reset states for all of the Special Function Registers. These are categorized by Power-on and Brown-out Resets, Master Clear and WDT Resets and WDT wake-ups. Most registers are not affected by a WDT wake-up, since this is viewed as the resumption of normal operation. Status bits from the RCON register, RI, TO, PD, POR and BOR, are set or cleared differently in different Reset situations, as indicated in Table 4-3. These bits are used in software to determine the nature of the Reset. TABLE 4-3: STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR RCON REGISTER RCON Register STKPTR Register Program Counter SBOREN RI TO PD 0000h 1 1 1 1 0 0 0 0 RESET Instruction 0000h u(2) 0 u u u u u u Brown-out Reset 0000h u(2) 1 1 1 u 0 u u MCLR during Power-Managed Run Modes 0000h u(2) u 1 u u u u u MCLR during Power-Managed Idle Modes and Sleep Mode 0000h u(2) u 1 0 u u u u WDT Time-out during Full Power or Power-Managed Run Mode 0000h u(2) u 0 u u u u u MCLR during Full Power Execution 0000h u(2) u u u u u u u Stack Full Reset (STVREN = 1) 0000h u(2) u u u u u 1 u Stack Underflow Reset (STVREN = 1) 0000h u (2) u u u u u u 1 Stack Underflow Error (not an actual Reset, STVREN = 0) 0000h u(2) u u u u u u 1 WDT Time-out during Power-Managed Idle or Sleep Modes PC + 2 u(2) u 0 0 u u u u Interrupt Exit from Power-Managed Modes PC + 2(1) u(2) u u 0 u u u u Condition Power-on Reset POR BOR STKFUL STKUNF Legend: u = unchanged Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the interrupt vector (008h or 0018h). 2: Reset state is `1' for POR and unchanged for all other Resets when software BOR is enabled (BOREN1:BOREN0 configuration bits = 01 and SBOREN = 1). Otherwise, the Reset state is `0'. DS39646B-page 56 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS Register Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets, WDT Reset, RESET Instruction, Stack Resets Wake-up via WDT or Interrupt TOSU 6X27 6X22 8X27 8X22 ---0 0000 ---0 0000 ---0 uuuu(3) TOSH 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu(3) TOSL 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu(3) STKPTR 6X27 6X22 8X27 8X22 00-0 0000 uu-u uuuu uu-u uuuu(3) PCLATU 6X27 6X22 8X27 8X22 ---0 0000 ---0 0000 ---u uuuu PCLATH 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu PCL 6X27 6X22 8X27 8X22 0000 0000 0000 0000 PC + 2(2) TBLPTRU 6X27 6X22 8X27 8X22 --00 0000 --00 0000 --uu uuuu TBLPTRH 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu TBLPTRL 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu TABLAT 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu PRODH 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu PRODL 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu INTCON 6X27 6X22 8X27 8X22 0000 000x 0000 000u uuuu uuuu(1) INTCON2 6X27 6X22 8X27 8X22 1111 1111 1111 1111 uuuu uuuu(1) INTCON3 6X27 6X22 8X27 8X22 1100 0000 1100 0000 uuuu uuuu(1) INDF0 6X27 6X22 8X27 8X22 N/A N/A N/A POSTINC0 6X27 6X22 8X27 8X22 N/A N/A N/A POSTDEC0 6X27 6X22 8X27 8X22 N/A N/A N/A PREINC0 6X27 6X22 8X27 8X22 N/A N/A N/A PLUSW0 6X27 6X22 8X27 8X22 N/A N/A N/A FSR0H 6X27 6X22 8X27 8X22 ---- 0000 ---- 0000 ---- uuuu FSR0L 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu WREG 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu INDF1 6X27 6X22 8X27 8X22 N/A N/A N/A POSTINC1 6X27 6X22 8X27 8X22 N/A N/A N/A POSTDEC1 6X27 6X22 8X27 8X22 N/A N/A N/A PREINC1 6X27 6X22 8X27 8X22 N/A N/A N/A 6X27 6X22 8X27 8X22 N/A N/A N/A PLUSW1 Legend: Note 1: 2: 3: 4: 5: u = unchanged, x = unknown, - = unimplemented bit, read as `0', q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. See Table 4-3 for Reset value for specific condition. Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read `0'. 2004 Microchip Technology Inc. Preliminary DS39646B-page 57 PIC18F8722 FAMILY TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets, WDT Reset, RESET Instruction, Stack Resets Wake-up via WDT or Interrupt FSR1H 6X27 6X22 8X27 8X22 ---- 0000 ---- 0000 ---- uuuu FSR1L 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu BSR 6X27 6X22 8X27 8X22 ---- 0000 ---- 0000 ---- uuuu INDF2 6X27 6X22 8X27 8X22 N/A N/A N/A POSTINC2 6X27 6X22 8X27 8X22 N/A N/A N/A POSTDEC2 6X27 6X22 8X27 8X22 N/A N/A N/A PREINC2 6X27 6X22 8X27 8X22 N/A N/A N/A PLUSW2 6X27 6X22 8X27 8X22 N/A N/A N/A FSR2H 6X27 6X22 8X27 8X22 ---- 0000 ---- 0000 ---- uuuu FSR2L 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu STATUS 6X27 6X22 8X27 8X22 ---x xxxx ---u uuuu ---u uuuu TMR0H 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu TMR0L 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu T0CON 6X27 6X22 8X27 8X22 1111 1111 1111 1111 uuuu uuuu OSCCON 6X27 6X22 8X27 8X22 0100 q000 0100 q000 uuuu uuqu HLVDCON 6X27 6X22 8X27 8X22 0-00 0101 0-00 0101 u-uu uuuu WDTCON 6X27 6X22 8X27 8X22 ---- ---0 ---- ---0 ---- ---u (4) 6X27 6X22 8X27 8X22 0q-1 11q0 0q-q qquu uq-u qquu TMR1H 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu TMR1L 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu T1CON 6X27 6X22 8X27 8X22 0000 0000 u0uu uuuu uuuu uuuu TMR2 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu PR2 6X27 6X22 8X27 8X22 1111 1111 uuuu uuuu uuuu uuuu T2CON 6X27 6X22 8X27 8X22 -000 0000 -000 0000 -uuu uuuu SSP1BUF 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu SSP1ADD 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu SSP1STAT 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu SSP1CON1 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu SSP1CON2 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu RCON Legend: Note 1: 2: 3: 4: 5: u = unchanged, x = unknown, - = unimplemented bit, read as `0', q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. See Table 4-3 for Reset value for specific condition. Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read `0'. DS39646B-page 58 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register ADRESH Power-on Reset, Brown-out Reset MCLR Resets, WDT Reset, RESET Instruction, Stack Resets Wake-up via WDT or Interrupt 8X22 xxxx xxxx uuuu uuuu uuuu uuuu Applicable Devices 6X27 6X22 8X27 ADRESL 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu ADCON0 6X27 6X22 8X27 8X22 --00 0000 --00 0000 --uu uuuu ADCON1 6X27 6X22 8X27 8X22 --00 0000 --00 0000 --uu uuuu ADCON2 6X27 6X22 8X27 8X22 0-00 0000 0-00 0000 u-uu uuuu CCPR1H 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu CCPR1L 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu CCP1CON 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu CCPR2H 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu CCPR2L 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu CCP2CON 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu CCPR3H 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu CCPR3L 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu CCP3CON 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu ECCP1AS 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu CVRCON 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu CMCON 6X27 6X22 8X27 8X22 0000 0111 0000 0111 uuuu uuuu TMR3H 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu TMR3L 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu T3CON 6X27 6X22 8X27 8X22 0000 0000 uuuu uuuu uuuu uuuu PSPCON 6X27 6X22 8X27 8X22 0000 ---- 0000 ---- uuuu ---- SPBRG1 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu RCREG1 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu TXREG1 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu TXSTA1 6X27 6X22 8X27 8X22 0000 0010 0000 0010 uuuu uuuu RCSTA1 6X27 6X22 8X27 8X22 0000 000x 0000 000x uuuu uuuu EEADRH 6X27 6X22 8X27 8X22 ---- --00 ---- --00 ---- --uu EEADR 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu EEDATA 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu EECON2 6X27 6X22 8X27 8X22 0000 0000 0000 0000 0000 0000 EECON1 6X27 6X22 8X27 8X22 xx-0 x000 uu-0 u000 uu-u uuuu Legend: Note 1: 2: 3: 4: 5: u = unchanged, x = unknown, - = unimplemented bit, read as `0', q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. See Table 4-3 for Reset value for specific condition. Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read `0'. 2004 Microchip Technology Inc. Preliminary DS39646B-page 59 PIC18F8722 FAMILY TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Power-on Reset, Brown-out Reset Applicable Devices MCLR Resets, WDT Reset, RESET Instruction, Stack Resets Wake-up via WDT or Interrupt IPR3 6X27 6X22 8X27 8X22 1111 1111 1111 1111 uuuu uuuu PIR3 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu(1) PIE3 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu IPR2 6X27 6X22 8X27 8X22 11-1 1111 11-1 1111 uu-u uuuu PIR2 6X27 6X22 8X27 8X22 00-0 0000 00-0 0000 uu-u uuuu(1) PIE2 6X27 6X22 8X27 8X22 00-0 0000 00-0 0000 uu-u uuuu IPR1 6X27 6X22 8X27 8X22 1111 1111 1111 1111 uuuu uuuu PIR1 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu(1) PIE1 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu MEMCON 6X27 6X22 8X27 8X22 0-00 --00 0-00 --00 u-uu --uu OSCTUNE 6X27 6X22 8X27 8X22 00-0 0000 00-0 0000 uu-u uuuu TRISJ 6X27 6X22 8X27 8X22 1111 1111 1111 1111 uuuu uuuu TRISH 6X27 6X22 8X27 8X22 1111 1111 1111 1111 uuuu uuuu TRISG 6X27 6X22 8X27 8X22 ---1 1111 ---1 1111 ---u uuuu TRISF 6X27 6X22 8X27 8X22 1111 1111 1111 1111 uuuu uuuu TRISE 6X27 6X22 8X27 8X22 1111 1111 1111 1111 uuuu uuuu TRISD 6X27 6X22 8X27 8X22 1111 1111 1111 1111 uuuu uuuu TRISC 6X27 6X22 8X27 8X22 1111 1111 1111 1111 uuuu uuuu TRISB 6X27 6X22 8X27 8X22 1111 1111 1111 1111 uuuu uuuu TRISA(5) 6X27 6X22 8X27 8X22 1111 1111(5) 1111 1111(5) uuuu uuuu(5) LATJ 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu LATH 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu LATG 6X27 6X22 8X27 8X22 --xx xxxx --uu uuuu --uu uuuu LATF 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu LATE 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu LATD 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu LATC 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu LATB 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu LATA(5) 6X27 6X22 8X27 8X22 xxxx xxxx(5) uuuu uuuu(5) uuuu uuuu(5) PORTJ 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu PORTH 6X27 6X22 8X27 8X22 0000 xxxx uuuu uuuu uuuu uuuu PORTG 6X27 6X22 8X27 8X22 --xx xxxx --uu uuuu --uu uuuu PORTF 6X27 6X22 8X27 8X22 x000 0000 u000 0000 uuuu uuuu PORTE 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu PORTD 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu PORTC 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu PORTB 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu Legend: Note 1: 2: 3: 4: 5: u = unchanged, x = unknown, - = unimplemented bit, read as `0', q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. See Table 4-3 for Reset value for specific condition. Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read `0'. DS39646B-page 60 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register PORTA(5) Power-on Reset, Brown-out Reset MCLR Resets, WDT Reset, RESET Instruction, Stack Resets Wake-up via WDT or Interrupt 8X22 xx0x 0000(5) uu0u 0000(5) uuuu uuuu(5) Applicable Devices 6X27 6X22 8X27 SPBRGH1 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu BAUDCON1 6X27 6X22 8X27 8X22 01-0 0-00 01-0 0-00 uu-u u-uu SPBRGH2 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu BAUDCON2 6X27 6X22 8X27 8X22 01-0 0-00 01-0 0-00 uu-u u-uu ECCP1DEL 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu TMR4 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu PR4 6X27 6X22 8X27 8X22 1111 1111 uuuu uuuu uuuu uuuu T4CON 6X27 6X22 8X27 8X22 -000 0000 -000 0000 -uuu uuuu CCPR4H 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu CCPR4L 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu CCP4CON 6X27 6X22 8X27 8X22 --00 0000 --00 0000 --uu uuuu CCPR5H 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu CCPR5L 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu CCP5CON 6X27 6X22 8X27 8X22 --00 0000 --00 0000 --uu uuuu SPBRG2 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu RCREG2 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu TXREG2 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu TXSTA2 6X27 6X22 8X27 8X22 0000 0010 0000 0010 uuuu uuuu RCSTA2 6X27 6X22 8X27 8X22 0000 000x 0000 000x uuuu uuuu ECCP3AS 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu ECCP3DEL 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu ECCP2AS 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu ECCP2DEL 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu SSP2BUF 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu SSP2ADD 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu SSP2STAT 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu SSP2CON1 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu SSP2CON2 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu Legend: Note 1: 2: 3: 4: 5: u = unchanged, x = unknown, - = unimplemented bit, read as `0', q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. See Table 4-3 for Reset value for specific condition. Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read `0'. 2004 Microchip Technology Inc. Preliminary DS39646B-page 61 PIC18F8722 FAMILY NOTES: DS39646B-page 62 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY 5.0 MEMORY ORGANIZATION 5.1.1 There are three types of memory in PIC18 Enhanced microcontroller devices: * Program Memory * Data RAM * Data EEPROM As Harvard architecture devices, the data and program memories use separate busses; this allows for concurrent access of the two memory spaces. The data EEPROM, for practical purposes, can be regarded as a peripheral device, since it is addressed and accessed through a set of control registers. Additional detailed information on the operation of the Flash program memory is provided in Section 6.0 "Flash Program Memory". Data EEPROM is discussed separately in Section 8.0 "Data EEPROM Memory". 5.1 PIC18F8527/8622/8627/8722 PROGRAM MEMORY MODES PIC18F8527/8622/8627/8722 devices differ significantly from their PIC18 predecessors in their utilization of program memory. In addition to available on-chip Flash program memory, these controllers can also address up to 2 Mbytes of external program memory through the external memory interface. There are four distinct operating modes available to the controllers: * * * * Microprocessor (MP) Microprocessor with Boot Block (MPBB) Extended Microcontroller (EMC) Microcontroller (MC) The program memory mode is determined by setting the two Least Significant bits of the Configuration Register 3L (CONFIG3L) as shown in Register 25-4 (see Section 25.1 "Configuration Bits" for additional details on the device configuration bits). The program memory modes operate as follows: Program Memory Organization PIC18 microcontrollers implement a 21-bit program counter, which is capable of addressing a 2-Mbyte program memory space. Accessing a location between the upper boundary of the physically implemented memory and the 2-Mbyte address will return all `0's (a NOP instruction). The PIC18F6527 and PIC18F8527 each have 48 Kbytes of Flash memory and can store up to 24,576 single-word instructions. The PIC18F6622 and PIC18F8622 each have 64 Kbytes of Flash memory and can store up to 32,768 single-word instructions. The PIC18F6627 and PIC18F8627 each have 96 Kbytes of Flash memory and can store up to 49,152 single-word instructions. The PIC18F6722 and PIC18F8722 each have 128 Kbytes of Flash memory and can store up to 65,536 single-word instructions. PIC18 devices have two interrupt vectors. The Reset vector address is at 0000h and the interrupt vector addresses are at 0008h and 0018h. The program memory map for the PIC18F8722 family of devices is shown in Figure 5-1. * The Microprocessor Mode permits access only to external program memory; the contents of the on-chip Flash memory are ignored. The 21-bit program counter permits access to a 2-Mbyte linear program memory space. * The Microprocessor with Boot Block Mode accesses on-chip Flash memory from the Boot Block. Above this, external program memory is accessed all the way up to the 2-Mbyte limit. Program execution automatically switches between the two memories as required. The Boot Block is configurable to 1, 2 or 4 Kbytes. * The Microcontroller Mode accesses only on-chip Flash memory. Attempts to read above the physical limit of the on-chip Flash (0BFFFh for the PIC18F8527, 0FFFFh for the PIC18F8622, 17FFFh for the PIC18F8627, 1FFFFh for the PIC18F8722) causes a read of all `0's (a NOP instruction). The Microcontroller mode is also the only operating mode available to PIC18F6527/6622/6627/6722 devices. * The Extended Microcontroller Mode allows access to both internal and external program memories as a single block. The device can access its entire on-chip Flash memory; above this, the device accesses external program memory up to the 2-Mbyte program space limit. As with Boot Block mode, execution automatically switches between the two memories as required. In all modes, the microcontroller has complete access to data RAM and EEPROM. Figure 5-2 compares the memory maps of the different program memory modes. The differences between on-chip and external memory access limitations are more fully explained in Table 5-1. 2004 Microchip Technology Inc. Preliminary DS39646B-page 63 PIC18F8722 FAMILY FIGURE 5-1: PROGRAM MEMORY MAP AND STACK FOR PIC18F8722 FAMILY DEVICES PC<20:0> 21 CALL,RCALL,RETURN RETFIE,RETLW Stack Level 1 * * * Stack Level 31 Reset Vector 0000h High Priority Interrupt Vector 0008h Low Priority Interrupt Vector 0018h On-Chip Program Memory On-Chip Program Memory On-Chip Program Memory On-Chip Program Memory PIC18FX527 PIC18FX622 PIC18FX627 PIC18FX722 User Memory Space 0BFFFh 0C000h 0FFFFh 10000h 017FFFh 018000h Read `0' Read `0' Read `0' 01FFFFh 1FFFFFh TABLE 5-1: MEMORY ACCESS FOR PIC18F8527/8622/8627/8722 PROGRAM MEMORY MODES Internal Program Memory Operating Mode External Program Memory Execution From Table Read From Table Write To Microprocessor No Access No Access No Access Microprocessor w/ Boot Block Yes Yes Yes Microcontroller Yes Yes Yes Extended Microcontroller Yes Yes Yes DS39646B-page 64 Preliminary Execution From Table Read From Table Write To Yes Yes Yes Yes Yes Yes No Access No Access No Access Yes Yes Yes 2004 Microchip Technology Inc. PIC18F8722 FAMILY FIGURE 5-2: MEMORY MAPS FOR PIC18F8722 FAMILY PROGRAM MEMORY MODES Microprocessor with Boot Block Mode Microprocessor Mode 000000h On-Chip Program Memory (No Program Space Execution access) External Program Memory External Program Memory 1FFFFFh External Memory 1: 2: 3: 4: 5: 6: 0007FFh(6) or 000FFFh(6) or 001FFFh(6) 000800h(6) or 001000h(6) or (6) On-Chip Flash 0BFFFh(1) 0FFFFh(2) 017FFFh(3) 01FFFFh(4) 0C000h(1) 010000h(2) 018000h(3) 020000h(4) On-Chip Program Memory Reads `0's 1FFFFFh External Memory On-Chip Flash Extended Microcontroller Mode 000000h 000000h On-Chip Program Memory 002000h 1FFFFFh Note 000000h Microcontroller Mode(5) 0BFFFh(1) 0FFFFh(2) 017FFFh(3) 01FFFFh(4) 0C000h(1) 010000h(2) 018000h(3) External 020000h(4) Program Memory On-Chip Program Memory 1FFFFFh On-Chip Flash External Memory On-Chip Flash PIC18F6527 and PIC18F8527. PIC18F6622 and PIC18F8622. PIC18F6627 and PIC18F8627. PIC18F6722 and PIC18F8722. This is the only mode available on PIC18F6527/6622/6627/6722 devices. Boot Block size is determined by the BBSIZ<1:0> bits in CONFIG4L. 2004 Microchip Technology Inc. Preliminary DS39646B-page 65 PIC18F8722 FAMILY 5.1.2 PROGRAM COUNTER The Program Counter (PC) specifies the address of the instruction to fetch for execution. The PC is 21 bits wide and is contained in three separate 8-bit registers. The low byte, known as the PCL register, is both readable and writable. The high byte, or PCH register, contains the PC<15:8> bits; it is not directly readable or writable. Updates to the PCH register are performed through the PCLATH register. The upper byte is called PCU. This register contains the PC<20:16> bits; it is also not directly readable or writable. Updates to the PCU register are performed through the PCLATU register. The contents of PCLATH and PCLATU are transferred to the program counter by any operation that writes PCL. Similarly, the upper two bytes of the program counter are transferred to PCLATH and PCLATU by an operation that reads PCL. This is useful for computed offsets to the PC (see Section 5.1.5.1 "Computed GOTO"). The PC addresses bytes in the program memory. To prevent the PC from becoming misaligned with word instructions, the Least Significant bit of PCL is fixed to a value of `0'. The PC increments by 2 to address sequential instructions in the program memory. The CALL, RCALL, GOTO and program branch instructions write to the program counter directly. For these instructions, the contents of PCLATH and PCLATU are not transferred to the program counter. 5.1.3 RETURN ADDRESS STACK The return address stack allows any combination of up to 31 program calls and interrupts to occur. The PC is pushed onto the stack when a CALL or RCALL instruction is executed or an interrupt is acknowledged. The PC value is pulled off the stack on a RETURN, RETLW or a RETFIE instruction. PCLATU and PCLATH are not affected by any of the RETURN or CALL instructions. FIGURE 5-3: The stack operates as a 31-word by 21-bit RAM and a 5-bit Stack Pointer, STKPTR. The stack space is not part of either program or data space. The Stack Pointer is readable and writable and the address on the top of the stack is readable and writable through the top-ofstack Special File Registers. Data can also be pushed to, or popped from the stack, using these registers. A CALL type instruction causes a push onto the stack; the Stack Pointer is first incremented and the location pointed to by the Stack Pointer is written with the contents of the PC (already pointing to the instruction following the CALL). A RETURN type instruction causes a POP from the stack; the contents of the location pointed to by the STKPTR are transferred to the PC and then the Stack Pointer is decremented. The Stack Pointer is initialized to `00000' after all Resets. There is no RAM associated with the location corresponding to a Stack Pointer value of `00000'; this is only a Reset value. Status bits indicate if the stack is full or has overflowed or has underflowed. 5.1.3.1 Top-of-Stack Access Only the top of the return address stack (TOS) is readable and writable. A set of three registers, TOSU:TOSH:TOSL, hold the contents of the stack location pointed to by the STKPTR register (Figure 5-3). This allows users to implement a software stack if necessary. After a CALL, RCALL or interrupt, the software can read the pushed value by reading the TOSU:TOSH:TOSL registers. These values can be placed on a user defined software stack. At return time, the software can return these values to TOSU:TOSH:TOSL and do a return. The user must disable the global interrupt enable bits while accessing the stack to prevent inadvertent stack corruption. RETURN ADDRESS STACK AND ASSOCIATED REGISTERS Return Address Stack <20:0> 11111 11110 11101 Top-of-Stack Registers TOSU 00h TOSH 1Ah STKPTR<4:0> 00010 TOSL 34h Top-of-Stack DS39646B-page 66 Stack Pointer 001A34h 000D58h Preliminary 00011 00010 00001 00000 2004 Microchip Technology Inc. PIC18F8722 FAMILY 5.1.3.2 Return Stack Pointer (STKPTR) When the stack has been popped enough times to unload the stack, the next POP will return a value of zero to the PC and set the STKUNF bit, while the Stack Pointer remains at zero. The STKUNF bit will remain set until cleared by software or until a POR occurs. The STKPTR register (Register 5-1) contains the Stack Pointer value, the STKFUL (Stack Full) status bit and the STKUNF (Stack Underflow) status bits. The value of the Stack Pointer can be 0 through 31. The Stack Pointer increments before values are pushed onto the stack and decrements after values are popped off the stack. On Reset, the stack pointer value will be zero. The user may read and write the stack pointer value. This feature can be used by a Real-Time Operating System (RTOS) for return stack maintenance. Note: After the PC is pushed onto the stack 31 times (without popping any values off the stack), the STKFUL bit is set. The STKFUL bit is cleared by software or by a POR. 5.1.3.3 PUSH and POP Instructions Since the Top-of-Stack is readable and writable, the ability to push values onto the stack and pull values off the stack without disturbing normal program execution is a desirable feature. The PIC18 instruction set includes two instructions, PUSH and POP, that permit the TOS to be manipulated under software control. TOSU, TOSH and TOSL can be modified to place data or a return address on the stack. The action that takes place when the stack becomes full depends on the state of the STVREN (Stack Overflow Reset Enable) configuration bit. (Refer to Section 25.1 "Configuration Bits" for a description of the device configuration bits.) If STVREN is set (default), the 31st PUSH will push the (PC + 2) value onto the stack, set the STKFUL bit and reset the device. The STKFUL bit will remain set and the Stack Pointer will be set to zero. The PUSH instruction places the current PC value onto the stack. This increments the Stack Pointer and loads the current PC value onto the stack. If STVREN is cleared, the STKFUL bit will be set on the 31st PUSH and the Stack Pointer will increment to 31. Any additional pushes will not overwrite the 31st PUSH and STKPTR will remain at 31. REGISTER 5-1: Returning a value of zero to the PC on an underflow has the effect of vectoring the program to the Reset vector, where the stack conditions can be verified and appropriate actions can be taken. This is not the same as a Reset, as the contents of the SFRs are not affected. The POP instruction discards the current TOS by decrementing the Stack Pointer. The previous value pushed onto the stack then becomes the TOS value. STKPTR: STACK POINTER REGISTER R/C-0 R/C-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 STKFUL(1) STKUNF(1) -- SP4 SP3 SP2 SP1 SP0 bit 7 bit 0 bit 7 STKFUL: Stack Full Flag bit(1) 1 = Stack became full or overflowed 0 = Stack has not become full or overflowed bit 6 STKUNF: Stack Underflow Flag bit(1) 1 = Stack underflow occurred 0 = Stack underflow did not occur bit 5 Unimplemented: Read as `0' bit 4-0 SP4:SP0: Stack Pointer Location bits Note 1: Bit 7 and bit 6 are cleared by user software or by a POR. Legend: R = Readable bit W = Writable bit U = Unimplemented C = Clearable only bit -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown 2004 Microchip Technology Inc. Preliminary DS39646B-page 67 PIC18F8722 FAMILY 5.1.3.4 Stack Full and Underflow Resets EXAMPLE 5-1: Device Resets on stack overflow and stack underflow conditions are enabled by setting the STVREN bit in Configuration Register 4L. When STVREN is set, a full or underflow will set the appropriate STKFUL or STKUNF bit and then cause a device Reset. When STVREN is cleared, a full or underflow condition will set the appropriate STKFUL or STKUNF bit, but not cause a device Reset. The STKFUL or STKUNF bits are cleared by the user software or a Power-on Reset. 5.1.4 ;STATUS, WREG, BSR ;SAVED IN FAST REGISTER ;STACK * * * * RETURN, FAST SUB1 ;RESTORE VALUES SAVED ;IN FAST REGISTER STACK FAST REGISTER STACK A fast register stack is provided for the Status, WREG and BSR registers, to provide a "fast return" option for interrupts. The stack for each register is only one level deep and is neither readable nor writable. It is loaded with the current value of the corresponding register when the processor vectors for an interrupt. All interrupt sources will push values into the stack registers. The values in the registers are then loaded back into their associated registers if the RETFIE, FAST instruction is used to return from the interrupt. If both low and high priority interrupts are enabled, the stack registers cannot be used reliably to return from low priority interrupts. If a high priority interrupt occurs while servicing a low priority interrupt, the stack register values stored by the low priority interrupt will be overwritten. In these cases, users must save the key registers in software during a low priority interrupt. If interrupt priority is not used, all interrupts may use the fast register stack for returns from interrupt. If no interrupts are used, the fast register stack can be used to restore the STATUS, WREG and BSR registers at the end of a subroutine call. To use the fast register stack for a subroutine call, a CALL label, FAST instruction must be executed to save the STATUS, WREG and BSR registers to the fast register stack. A RETURN, FAST instruction is then executed to restore these registers from the fast register stack. Example 5-1 shows a source code example that uses the fast register stack during a subroutine call and return. EXAMPLE 5-2: MAIN: CALL SUB1, FAST FAST REGISTER STACK CODE EXAMPLE 5.1.5 LOOK-UP TABLES IN PROGRAM MEMORY There may be programming situations that require the creation of data structures, or look-up tables, in program memory. For PIC18 devices, look-up tables can be implemented in two ways: * Computed GOTO * Table Reads 5.1.5.1 Computed GOTO A computed GOTO is accomplished by adding an offset to the program counter. An example is shown in Example 5-2. A look-up table can be formed with an ADDWF PCL instruction and a group of RETLW nn instructions. The W register is loaded with an offset into the table before executing a call to that table. The first instruction of the called routine is the ADDWF PCL instruction. The next instruction executed will be one of the RETLW nn instructions that returns the value `nn' to the calling function. The offset value (in WREG) specifies the number of bytes that the program counter should advance and should be multiples of 2 (LSb = 0). In this method, only one data byte may be stored in each instruction location and room on the return address stack is required. Note: The "ADDWF PCL" instruction does not update the PCLATH and PCLATU registers. A read operation on PCL must be performed to update PCLATH and PCLATU. COMPUTED GOTO USING AN OFFSET VALUE ORG 0x0000 MOVLW 0x00 CALL TABLE ... TABLE ORG MOVF RLNCF ADDWF RETLW RETLW RETLW RETLW RETLW END DS39646B-page 68 0x8000 PCL, F W, W PCL `A' `B' `C' `D' `E' ; A simple read of PCL will update PCLATH, PCLATU ; Multiply by 2 to get correct offset in table ; Add the modified offset to force jump into table Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY 5.1.5.2 Table Reads and Table Writes on every Q1; the instruction is fetched from the program memory and latched into the instruction register during Q4. The instruction is decoded and executed during the following Q1 through Q4. The clocks and instruction execution flow are shown in Figure 5-4. A better method of storing data in program memory allows two bytes of data to be stored in each instruction location. Look-up table data may be stored two bytes per program word by using table reads and writes. The Table Pointer (TBLPTR) register specifies the byte address and the Table Latch (TABLAT) register contains the data that is read from or written to program memory. Data is transferred to or from program memory one byte at a time. 5.2.2 An "Instruction Cycle" consists of four Q cycles: Q1 through Q4. The instruction fetch and execute are pipelined in such a manner that a fetch takes one instruction cycle, while the decode and execute take another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the program counter to change (e.g., GOTO), then two cycles are required to complete the instruction (Example 5-3). Table read and table write operations are discussed further in Section 6.1 "Table Reads and Table Writes". 5.2 PIC18 Instruction Cycle 5.2.1 A fetch cycle begins with the program counter incrementing in Q1. CLOCKING SCHEME In the execution cycle, the fetched instruction is latched into the Instruction Register (IR) in cycle Q1. This instruction is then decoded and executed during the Q2, Q3 and Q4 cycles. Data memory is read during Q2 The microcontroller clock input, whether from an internal or external source, is internally divided by four to generate four non-overlapping quadrature clocks (Q1, Q2, Q3 and Q4). Internally, the program counter is incremented FIGURE 5-4: INSTRUCTION FLOW/PIPELINING CLOCK/INSTRUCTION CYCLE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 Q1 Q2 Internal Phase Clock Q3 Q4 PC PC PC + 2 PC + 4 OSC2/CLKO (RC mode) Execute INST (PC - 2) Fetch INST (PC) EXAMPLE 5-3: TCY0 TCY1 Fetch 1 Execute 1 2. MOVWF PORTB 4. BSF Execute INST (PC + 2) Fetch INST (PC + 4) INSTRUCTION PIPELINE FLOW 1. MOVLW 55h 3. BRA Execute INST (PC) Fetch INST (PC + 2) SUB_1 Fetch 2 TCY2 TCY3 TCY4 TCY5 Execute 2 Fetch 3 Execute 3 Fetch 4 PORTA, BIT3 (Forced NOP) Flush (NOP) Fetch SUB_1 Execute SUB_1 5. Instruction @ address SUB_1 All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is "flushed" from the pipeline while the new instruction is being fetched and then executed. 2004 Microchip Technology Inc. Preliminary DS39646B-page 69 PIC18F8722 FAMILY 5.2.3 INSTRUCTIONS IN PROGRAM MEMORY The program memory is addressed in bytes. Instructions are stored as two bytes or four bytes in program memory. The Least Significant Byte of an instruction word is always stored in a program memory location with an even address (LSb = 0). To maintain alignment with instruction boundaries, the PC increments in steps of 2 and the LSb will always read `0' (see Section 5.1.2 "Program Counter"). Figure 5-5 shows an example of how instruction words are stored in the program memory. FIGURE 5-5: The CALL and GOTO instructions have the absolute program memory address embedded into the instruction. Since instructions are always stored on word boundaries, the data contained in the instruction is a word address. The word address is written to PC<20:1>, which accesses the desired byte address in program memory. Instruction #2 in Figure 5-5 shows how the instruction GOTO 0006h is encoded in the program memory. Program branch instructions, which encode a relative address offset, operate in the same manner. The offset value stored in a branch instruction represents the number of single-word instructions that the PC will be offset by. Section 26.0 "Instruction Set Summary" provides further details of the instruction set. INSTRUCTIONS IN PROGRAM MEMORY LSB = 1 LSB = 0 0Fh EFh F0h C1h F4h 55h 03h 00h 23h 56h Program Memory Byte Locations Instruction 1: Instruction 2: MOVLW GOTO 055h 0006h Instruction 3: MOVFF 123h, 456h DS39646B-page 70 Preliminary Word Address 000000h 000002h 000004h 000006h 000008h 00000Ah 00000Ch 00000Eh 000010h 000012h 000014h 2004 Microchip Technology Inc. PIC18F8722 FAMILY 5.2.4 TWO-WORD INSTRUCTIONS The standard PIC18 instruction set has 8 two-word instructions: CALL, MOVFF, GOTO, LSFR, ADDULNK, CALLW, MOVSS and SUBULNK. In all cases, the second word of the instructions always has `1111' as its four Most Significant bits; the other 12 bits are literal data, usually a data memory address. the instruction sequence. If the first word is skipped for some reason and the second word is executed by itself, a NOP is executed instead. This is necessary for cases when the two-word instruction is preceded by a conditional instruction that changes the PC. Example 5-4 shows how this works. Note: The use of `1111' in the 4 MSbs of an instruction specifies a special form of NOP. If the instruction is executed in proper sequence - immediately after the first word - the data in the second word is accessed and used by EXAMPLE 5-4: See Section 5.6 "PIC18 Instruction Execution and the Extended Instruction Set" for information on two-word instructions in the extended instruction set. TWO-WORD INSTRUCTIONS CASE 1: Object Code 0110 0110 0000 1100 0001 0010 1111 0100 0101 0010 0100 0000 0000 0011 0110 0000 Source Code TSTFSZ REG1 ; is RAM location 0? MOVFF REG1, REG2 ; No, skip this word ; Execute this word as a NOP ADDWF REG3 ; continue code 0000 0011 0110 0000 Source Code TSTFSZ REG1 ; is RAM location 0? MOVFF REG1, REG2 ; Yes, execute this word ; 2nd word of instruction ADDWF REG3 ; continue code CASE 2: Object Code 0110 0110 0000 1100 0001 0010 1111 0100 0101 0010 0100 0000 2004 Microchip Technology Inc. Preliminary DS39646B-page 71 PIC18F8722 FAMILY 5.3 Note: 5.3.1 Data Memory Organization The operation of some aspects of data memory are changed when the PIC18 extended instruction set is enabled. See Section 5.5 "Data Memory and the Extended Instruction Set" for more information. The data memory in PIC18 devices is implemented as static RAM. Each register in the data memory has a 12-bit address, allowing up to 4096 bytes of data memory. The memory space is divided into as many as 16 banks that contain 256 bytes each; the PIC18F8722 family of devices implements all 16 banks. Figure 5-6 shows the data memory organization for the PIC18F8722 family of devices. The data memory contains Special Function Registers (SFRs) and General Purpose Registers (GPRs). The SFRs are used for control and status of the controller and peripheral functions, while GPRs are used for data storage and scratchpad operations in the user's application. Any read of an unimplemented location will read as `0's. The instruction set and architecture allow operations across all banks. The entire data memory may be accessed by Direct, Indirect or Indexed Addressing modes. Addressing modes are discussed later in this subsection. To ensure that commonly used registers (SFRs and select GPRs) can be accessed in a single cycle, PIC18 devices implement an Access Bank. This is a 256-byte memory space that provides fast access to SFRs and the lower portion of GPR Bank 0 without using the BSR. Section 5.3.2 "Access Bank" provides a detailed description of the Access RAM. BANK SELECT REGISTER (BSR) Large areas of data memory require an efficient addressing scheme to make rapid access to any address possible. Ideally, this means that an entire address does not need to be provided for each read or write operation. For PIC18 devices, this is accomplished with a RAM banking scheme. This divides the memory space into 16 contiguous banks of 256 bytes. Depending on the instruction, each location can be addressed directly by its full 12-bit address, or an 8-bit low-order address and a 4-bit bank pointer. Most instructions in the PIC18 instruction set make use of the bank pointer, known as the Bank Select Register (BSR). This SFR holds the 4 Most Significant bits of a location's address; the instruction itself includes the 8 Least Significant bits. Only the four lower bits of the BSR are implemented (BSR3:BSR0). The upper four bits are unused; they will always read `0' and cannot be written to. The BSR can be loaded directly by using the MOVLB instruction. The value of the BSR indicates the bank in data memory; the 8 bits in the instruction show the location in the bank and can be thought of as an offset from the bank's lower boundary. The relationship between the BSR's value and the bank division in data memory is shown in Figure 5-7. Since up to 16 registers may share the same low-order address, the user must always be careful to ensure that the proper bank is selected before performing a data read or write. For example, writing what should be program data to an 8-bit address of F9h while the BSR is 0Fh will end up resetting the program counter. While any bank can be selected, only those banks that are actually implemented can be read or written to. Writes to unimplemented banks are ignored, while reads from unimplemented banks will return `0's. Even so, the STATUS register will still be affected as if the operation was successful. The data memory map in Figure 5-6 indicates which banks are implemented. In the core PIC18 instruction set, only the MOVFF instruction fully specifies the 12-bit address of the source and target registers. This instruction ignores the BSR completely when it executes. All other instructions include only the low-order address as an operand and must use either the BSR or the Access Bank to locate their target registers. DS39646B-page 72 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY FIGURE 5-6: DATA MEMORY MAP FOR THE PIC18F8722 FAMILY OF DEVICES BSR<3:0> = 0000 00h Access RAM FFh 00h GPR Bank 0 = 0001 = 0011 = 0100 = 0101 = 0110 = 0111 = 1000 = 1001 = 1010 = 1011 = 1100 = 1101 = 1110 = 1111 1FFh 200h FFh 00h Bank 2 Bank 3 Bank 4 Bank 5 2FFh 300h GPR 3FFh 400h FFh 00h Bank 12 The BSR specifies the Bank used by the instruction. 5FFh 600h GPR 6FFh 700h GPR 7FFh 800h FFh 00h GPR Access Bank Access RAM Low 00h 5Fh Access RAM High 60h (SFRs) FFh 8FFh 900h FFh 00h GPR 9FFh A00h FFh 00h GPR AFFh B00h FFh 00h GPR BFFh C00h FFh 00h GPR FFh Bank 13 00h CFFh D00h GPR DFFh E00h FFh 00h Bank 14 GPR FFh 00h GPR FFh SFR Bank 15 2004 Microchip Technology Inc. When `a' = 1: GPR Bank 7 Bank 11 The second 160 bytes are Special Function Registers (from Bank 15). 4FFh 500h FFh 00h Bank 10 The first 96 bytes are general purpose RAM (from Bank 0). GPR FFh 00h Bank 6 Bank 9 The BSR is ignored and the Access Bank is used. GPR FFh 00h FFh 00h Bank 8 000h 05Fh 060h 0FFh 100h GPR Bank 1 = 0010 When `a' = 0: Data Memory Map EFFh F00h F5Fh F60h FFFh Preliminary DS39646B-page 73 PIC18F8722 FAMILY FIGURE 5-7: USE OF THE BANK SELECT REGISTER (DIRECT ADDRESSING) 0 Data Memory BSR(1) 7 0 0 0 0 0 0 1 1 000h 00h Bank 0 FFh 00h 100h Bank 1 Bank Select(2) From Opcode(2) 7 1 1 1 1 1 1 0 1 1 FFh 00h 200h Bank 2 FFh 00h 300h Bank 3 through Bank 13 FFh 00h E00h Bank 14 FFh 00h F00h Bank 15 FFFh Note 1: 2: 5.3.2 FFh The Access RAM bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to the registers of the Access Bank. The MOVFF instruction embeds the entire 12-bit address in the instruction. ACCESS BANK While the use of the BSR with an embedded 8-bit address allows users to address the entire range of data memory, it also means that the user must always ensure that the correct bank is selected. Otherwise, data may be read from or written to the wrong location. This can be disastrous if a GPR is the intended target of an operation, but an SFR is written to instead. Verifying and/or changing the BSR for each read or write to data memory can become very inefficient. To streamline access for the most commonly used data memory locations, the data memory is configured with an Access Bank, which allows users to access a mapped block of memory without specifying a BSR. The Access Bank consists of the first 96 bytes of memory (00h-5Fh) in Bank 0 and the last 160 bytes of memory (60h-FFh) in Block 15. The lower half is known as the "Access RAM" and is composed of GPRs. This upper half is also where the device's SFRs are mapped. These two areas are mapped contiguously in the Access Bank and can be addressed in a linear fashion by an 8-bit address (Figure 5-6). The Access Bank is used by core PIC18 instructions that include the Access RAM bit (the `a' parameter in the instruction). When `a' is equal to `1', the instruction uses the BSR and the 8-bit address included in the opcode for the data memory address. When `a' is `0', DS39646B-page 74 however, the instruction is forced to use the Access Bank address map; the current value of the BSR is ignored entirely. Using this "forced" addressing allows the instruction to operate on a data address in a single cycle, without updating the BSR first. For 8-bit addresses of 60h and above, this means that users can evaluate and operate on SFRs more efficiently. The Access RAM below 60h is a good place for data values that the user might need to access rapidly, such as immediate computational results or common program variables. Access RAM also allows for faster and more code efficient context saving and switching of variables. The mapping of the Access Bank is slightly different when the extended instruction set is enabled (XINST configuration bit = 1). This is discussed in more detail in Section 5.5.3 "Mapping the Access Bank in Indexed Literal Offset Mode". 5.3.3 GENERAL PURPOSE REGISTER FILE PIC18 devices may have banked memory in the GPR area. This is data RAM, which is available for use by all instructions. GPRs start at the bottom of Bank 0 (address 000h) and grow upwards towards the bottom of the SFR area. GPRs are not initialized by a Power-on Reset and are unchanged on all other Resets. Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY 5.3.4 SPECIAL FUNCTION REGISTERS The Special Function Registers (SFRs) are registers used by the CPU and peripheral modules for controlling the desired operation of the device. These registers are implemented as static RAM. SFRs start at the top of data memory (FFFh) and extend downward to occupy the top half of Bank 15 (F60h to FFFh). A list of these registers is given in Table 5-2 and Table 5-3. The SFRs can be classified into two sets: those associated with the "core" device functionality (ALU, Resets and interrupts) and those related to the peripheral functions. The Reset and interrupt registers are described in their respective chapters, while the ALU's STATUS register is described later in this section. Registers related to the operation of a peripheral feature are described in the chapter for that peripheral. The SFRs are typically distributed among the peripherals whose functions they control. Unused SFR locations are unimplemented and read as `0's. TABLE 5-2: SPECIAL FUNCTION REGISTER MAP FOR THE PIC18F8722 FAMILY OF DEVICES Address Name Address FFFh TOSU FDFh FFEh TOSH FDEh POSTINC2(1) FBEh FFDh TOSL FDDh POSTDEC2(1) FBDh FFCh STKPTR FDCh PREINC2(1) FBCh FFBh PCLATU FDBh PLUSW2(1) FBBh FFAh PCLATH FDAh Name INDF2(1) FSR2H Address FBFh FBAh Name Address Name Address F9Fh IPR1 F7Fh SPBRGH1 CCPR1L F9Eh PIR1 F7Eh BAUDCON1 CCP1CON F9Dh PIE1 F7Dh SPBRGH2 CCPR2H F9Ch MEMCON F7Ch BAUDCON2 CCPR2L F9Bh OSCTUNE F7Bh --(2) F9Ah TRISJ(3) F7Ah --(2) (3) CCPR1H CCP2CON TRISH Name FF9h PCL FD9h FSR2L FB9h CCPR3H F99h F79h ECCP1DEL FF8h TBLPTRU FD8h STATUS FB8h CCPR3L F98h TRISG F78h TMR4 FF7h TBLPTRH FD7h TMR0H FB7h CCP3CON F97h TRISF F77h PR4 FF6h TBLPTRL FD6h TMR0L FB6h ECCP1AS F96h TRISE F76h T4CON FF5h TABLAT FD5h T0CON FB5h CVRCON F95h TRISD F75h CCPR4H FF4h PRODH FD4h --(2) FB4h CMCON F94h TRISC F74h CCPR4L FF3h PRODL FD3h OSCCON FB3h TMR3H F93h TRISB F73h CCP4CON FF2h INTCON FD2h HLVDCON FB2h TMR3L F92h TRISA F72h CCPR5H FF1h INTCON2 FD1h WDTCON FB1h T3CON F91h LATJ(3) F71h CCPR5L FF0h INTCON3 FD0h RCON FB0h PSPCON F90h LATH(3) F70h CCP5CON FEFh INDF0(1) FCFh TMR1H FAFh SPBRG1 F8Fh LATG F6Fh SPBRG2 FEEh POSTINC0(1) FCEh TMR1L FAEh RCREG1 F8Eh LATF F6Eh RCREG2 FEDh POSTDEC0(1) FCDh T1CON FADh TXREG1 F8Dh LATE F6Dh TXREG2 FECh PREINC0(1) FCCh TMR2 FACh TXSTA1 F8Ch LATD F6Ch TXSTA2 FEBh PLUSW0(1) FCBh PR2 FABh RCSTA1 F8Bh LATC F6Bh RCSTA2 FEAh FSR0H FCAh T2CON FAAh EEADRH F8Ah LATB F6Ah ECCP3AS FE9h FSR0L FC9h SSP1BUF FA9h EEADR F89h LATA F69h ECCP3DEL FE8h WREG FC8h SSP1ADD FA8h EEDATA F88h PORTJ(3) F68h ECCP2AS FE7h INDF1(1) FC7h SSP1STAT FA7h EECON2(1) F87h PORTH(3) F67h ECCP2DEL FE6h POSTINC1(1) FC6h SSP1CON1 FA6h EECON1 F86h PORTG F66h SSP2BUF FE5h POSTDEC1(1) FC5h SSP1CON2 FA5h IPR3 F85h PORTF F65h SSP2ADD FE4h PREINC1(1) FC4h ADRESH FA4h PIR3 F84h PORTE F64h SSP2STAT FE3h PLUSW1(1) FC3h ADRESL FA3h PIE3 F83h PORTD F63h SSP2CON1 FE2h FSR1H FC2h ADCON0 FA2h IPR2 F82h PORTC F62h SSP2CON2 FE1h FSR1L FC1h ADCON1 FA1h PIR2 F81h PORTB F61h --(2) FE0h BSR FC0h ADCON2 FA0h PIE2 F80h PORTA F60h --(2) Note 1: 2: 3: This is not a physical register. Unimplemented registers are read as `0'. This register is not available on 64-pin devices. 2004 Microchip Technology Inc. Preliminary DS39646B-page 75 PIC18F8722 FAMILY TABLE 5-3: File Name TOSU REGISTER FILE SUMMARY Bit 7 Bit 6 Bit 5 -- -- -- Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Details on page: ---0 0000 57, 66 TOSH Top-of-Stack High Byte (TOS<15:8>) 0000 0000 57, 66 TOSL Top-of-Stack Low Byte (TOS<7:0>) 0000 0000 57, 66 00-0 0000 57, 67 ---0 0000 57, 66 STKPTR STKFUL(6) STKUNF(6) -- PCLATU -- -- -- Top-of-Stack Upper Byte (TOS<20:16>) Value on POR, BOR SP4 SP3 SP2 SP1 SP0 Holding Register for PC<20:16> PCLATH Holding Register for PC<15:8> 0000 0000 57, 66 PCL PC Low Byte (PC<7:0>) 0000 0000 57, 66 --00 0000 57, 90 TBLPTRU -- -- bit 21(7) Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) TBLPTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 0000 0000 57, 90 TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) 0000 0000 57, 90 TABLAT Program Memory Table Latch 0000 0000 57, 90 PRODH Product Register High Byte xxxx xxxx 57, 117 PRODL Product Register Low Byte INTCON xxxx xxxx 57, 117 RBIF 0000 000x 57, 121 INT3IP RBIP 1111 1111 57, 122 INT2IF INT1IF 1100 0000 57, 123 GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INTCON3 INT2IP INT1IP INT3IE INT2IE INT1IE INT3IF INDF0 Uses contents of FSR0 to address data memory - value of FSR0 not changed (not a physical register) N/A 57, 82 POSTINC0 Uses contents of FSR0 to address data memory - value of FSR0 post-incremented (not a physical register) N/A 57, 82 POSTDEC0 Uses contents of FSR0 to address data memory - value of FSR0 post-decremented (not a physical register) N/A 57, 82 PREINC0 Uses contents of FSR0 to address data memory - value of FSR0 pre-incremented (not a physical register) N/A 57, 82 PLUSW0 Uses contents of FSR0 to address data memory - value of FSR0 pre-incremented (not a physical register) - value of FSR0 offset by W N/A 57, 82 FSR0H ---- 0000 57, 82 FSR0L Indirect Data Memory Address Pointer 0 Low Byte -- xxxx xxxx 57, 82 WREG Working Register xxxx xxxx 57 INDF1 Uses contents of FSR1 to address data memory - value of FSR1 not changed (not a physical register) N/A 57, 82 POSTINC1 Uses contents of FSR1 to address data memory - value of FSR1 post-incremented (not a physical register) N/A 57, 82 POSTDEC1 Uses contents of FSR1 to address data memory - value of FSR1 post-decremented (not a physical register) N/A 57, 82 PREINC1 Uses contents of FSR1 to address data memory - value of FSR1 pre-incremented (not a physical register) N/A 57, 82 PLUSW1 Uses contents of FSR1 to address data memory - value of FSR1 pre-incremented (not a physical register) - value of FSR1 offset by W N/A 57, 82 ---- 0000 58, 82 xxxx xxxx 58, 82 ---- 0000 58, 72 FSR1H -- FSR1L -- -- -- -- -- -- Indirect Data Memory Address Pointer 0 High Indirect Data Memory Address Pointer 1 High Indirect Data Memory Address Pointer 1 Low Byte BSR -- -- -- -- Bank Select Register INDF2 Uses contents of FSR2 to address data memory - value of FSR2 not changed (not a physical register) N/A 58, 82 POSTINC2 Uses contents of FSR2 to address data memory - value of FSR2 post-incremented (not a physical register) N/A 58, 82 POSTDEC2 Uses contents of FSR2 to address data memory - value of FSR2 post-decremented (not a physical register) N/A 58, 82 PREINC2 Uses contents of FSR2 to address data memory - value of FSR2 pre-incremented (not a physical register) N/A 58, 82 PLUSW2 Uses contents of FSR2 to address data memory - value of FSR2 pre-incremented (not a physical register) - value of FSR2 offset by W N/A 58, 82 ---- 0000 58, 82 xxxx xxxx 58, 82 FSR2H -- FSR2L -- -- -- Indirect Data Memory Address Pointer 2 High Indirect Data Memory Address Pointer 2 Low Byte Legend: Note 1: 2: 3: 4: 5: 6: 7: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition The SBOREN bit is only available when the BOREN1:BOREN0 configuration bits = 01; otherwise, this bit reads as `0'. These registers and/or bits are not implemented on 64-pin devices and are read as `0'. Reset values are shown for 80-pin devices; individual unimplemented bits should be interpreted as `-'. The PLLEN bit is only available in specific oscillator configuration; otherwise, it is disabled and reads as `0'. See Section 2.6.4 "PLL in INTOSC Modes". RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as `0'. RG5 and LATG5 are only available when Master Clear is disabled (MCLRE configuration bit = 0); otherwise, RG5 and LATG5 read as `0'. Bit 7 and Bit 6 are cleared by user software or by a POR. Bit 21 of TBLPTRU allows access to the device configuration bits. DS39646B-page 76 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY TABLE 5-3: File Name STATUS REGISTER FILE SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR -- -- -- N OV Z DC C ---x xxxx 58, 80 0000 0000 58, 163 TMR0H Timer0 Register High Byte TMR0L Timer0 Register Low Byte Details on page: xxxx xxxx 58, 163 TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 1111 1111 58, 161 OSCCON IDLEN IRCF2 IRCF1 IRCF0 OSTS IOFS SCS1 SCS0 0100 q000 39, 58 HLVDCON VDIRMAG -- IRVST HLVDEN HLVDL3 HLVDL2 HLVDL1 HLVDL0 0-00 0101 58, 291 -- -- -- -- -- -- -- SWDTEN --- ---0 58, 313 IPEN SBOREN(1) -- RI TO PD POR BOR 0q-1 11q0 50, 56, 58, 133 58, 169 T0CON WDTCON RCON TMR1H Timer1 Register High Byte xxxx xxxx TMR1L Timer1 Register Low Byte xxxx xxxx 58, 169 0000 0000 58, 165 58, 172 T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON TMR2 Timer2 Register 0000 0000 PR2 Timer2 Period Register 1111 1111 58, 172 -000 0000 58, 171 xxxx xxxx 58, 169, 170 T2CON -- T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 SSP1BUF MSSP1 Receive Buffer/Transmit Register SSP1ADD MSSP1 Address Register in I2CTM Slave mode. MSSP1 Baud Rate Reload Register in I2C Master mode. 0000 0000 58, 170 SSP1STAT SMP CKE D/A P S R/W UA BF 0000 0000 58, 162, 171 SSP1CON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 58, 163, 172 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN SSP1CON2 0000 0000 58, 173 ADRESH A/D Result Register High Byte xxxx xxxx 59, 280 ADRESL A/D Result Register Low Byte xxxx xxxx 59, 280 ADCON0 -- -- CHS3 CHS2 CHS1 CHS0 GO/DONE ADON --00 0000 59, 271 ADCON1 -- -- VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 --00 0000 59, 272 ADCON2 ADFM -- ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 0-00 0000 59, 273 CCPR1H Enhanced Capture/Compare/PWM Register 1 High Byte xxxx xxxx 59, 180 CCPR1L Enhanced Capture/Compare/PWM Register 1 Low Byte xxxx xxxx 59, 180 0000 0000 59, 187 CCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 CCPR2H Enhanced Capture/Compare/PWM Register 2 High Byte xxxx xxxx 59, 180 CCPR2L Enhanced Capture/Compare/PWM Register 2 Low Byte xxxx xxxx 59, 180 0000 0000 59, 179 CCP2CON P2M1 P2M0 DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 CCPR3H Enhanced Capture/Compare/PWM Register 3 High Byte xxxx xxxx 59, 180 CCPR3L Enhanced Capture/Compare/PWM Register 3 Low Byte xxxx xxxx 59, 180 CCP3CON ECCP1AS P3M1 P3M0 ECCP1ASE ECCP1AS2 DC3B1 DC3B0 CCP3M3 CCP3M2 CCP3M1 CCP3M0 0000 0000 59, 179 ECCP1AS1 ECCP1AS0 PSS1AC1 PSS1AC0 PSS1BD1 PSS1BD0 0000 0000 59, 201 CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 0000 0000 59, 287 CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0111 59, 281 TMR3H Timer3 Register High Byte xxxx xxxx 59, 175 TMR3L Timer3 Register Low Byte xxxx xxxx 59, 175 0000 0000 59, 173 T3CON RD16 Legend: Note 1: 2: 3: 4: 5: 6: 7: T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON x = unknown, u = unchanged, - = unimplemented, q = value depends on condition The SBOREN bit is only available when the BOREN1:BOREN0 configuration bits = 01; otherwise, this bit reads as `0'. These registers and/or bits are not implemented on 64-pin devices and are read as `0'. Reset values are shown for 80-pin devices; individual unimplemented bits should be interpreted as `-'. The PLLEN bit is only available in specific oscillator configuration; otherwise, it is disabled and reads as `0'. See Section 2.6.4 "PLL in INTOSC Modes". RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as `0'. RG5 and LATG5 are only available when Master Clear is disabled (MCLRE configuration bit = 0); otherwise, RG5 and LATG5 read as `0'. Bit 7 and Bit 6 are cleared by user software or by a POR. Bit 21 of TBLPTRU allows access to the device configuration bits. 2004 Microchip Technology Inc. Preliminary DS39646B-page 77 PIC18F8722 FAMILY TABLE 5-3: File Name PSPCON REGISTER FILE SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR IBF OBF IBOV PSPMODE -- -- -- -- Details on page: 0000 ---- 59, 252 EUSART1 Baud Rate Generator Register Low Byte 0000 0000 59, 252 RCREG1 EUSART1 Receive Register 0000 0000 59, 260 TXREG1 EUSART1 Transmit Register 0000 0000 59, 257 SPBRG1 TXSTA1 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 59, 248 RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 59, 249 EEADRH -- -- -- -- -- -- ---- --00 59, 111 EEPROM Address Register High Byte EEADR EEPROM Address Register Low Byte 0000 0000 59, 111 EEDATA EEPROM Data Register 0000 0000 59, 111 EECON2 EEPROM Control Register 2 (not a physical register) 0000 0000 59, 88 EECON1 EEPGD CFGS -- FREE WRERR WREN WR RD xx-0 x000 59, 89 IPR3 SSP2IP BCL2IP RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP 1111 1111 60, 131 PIR3 SSP2IF BCL2IF RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF 0000 0000 60, 125 PIE3 SSP2IE BCL2IE RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE 0000 0000 60, 128 IPR2 OSCFIP CMIP -- EEIP BCL1IP HLVDIP TMR3IP CCP2IP 11-1 1111 60, 131 PIR2 OSCFIF CMIF -- EEIF BCL1IF HLVDIF TMR3IF CCP2IF 00-0 0000 60, 125 PIE2 OSCFIE CMIE -- EEIE BCL1IE HLVDIE TMR3IE CCP2IE 00-0 0000 60, 128 IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 1111 1111 60, 130 PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 0000 0000 60, 124 PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 0000 0000 60, 127 MEMCON(2) EBDIS -- WAIT1 WAIT0 -- -- WM1 WM0 0-00 --00 60, 96 INTSRC PLLEN(3) -- TUN4 TUN3 TUN2 TUN1 TUN0 00-0 0000 35, 60 OSCTUNE TRISJ(2) TRISJ7 TRISJ6 TRISJ5 TRISJ4 TRISJ3 TRISJ2 TRISJ1 TRISJ0 1111 1111 60, 157 TRISH(2) TRISH7 TRISH6 TRISH5 TRISH4 TRISH3 TRISH2 TRISH1 TRISH0 1111 1111 60, 155 TRISG -- -- -- TRISG4 TRISG3 TRISG2 TRISG1 TRISG0 ---1 1111 60, 153 TRISF TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0 1111 1111 60, 150 TRISE TRISE7 TRISE6 TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 TRISE0 1111 1111 60, 148 TRISD TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 1111 1111 60, 143 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 60, 140 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 60, 137 TRISA TRISA7(4) TRISA6(4) TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 60, 135 LATJ(2) LATJ7 LATJ6 LATJ5 LATJ4 LATJ3 LATJ2 LATJ1 LATJ0 xxxx xxxx 60, 156 LATH(2) LATH7 LATH6 LATH5 LATH4 LATH3 LATH2 LATH1 LATH0 xxxx xxxx 60, 154 -- -- LATG5(5) LATG4 LATG3 LATG2 LATG1 LATG0 --xx xxxx 60, 151 LATG LATF LATF7 LATF6 LATF5 LATF4 LATF3 LATF2 LATF1 LATF0 xxxx xxxx 60, 149 LATE LATE7 LATE6 LATE5 LATE4 LATE3 LATE2 LATE1 LATE0 xxxx xxxx 60, 146 LATD LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 xxxx xxxx 60, 143 LATC LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 xxxx xxxx 60, 140 LATB LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 xxxx xxxx 60, 137 LATA LATA7(4) LATA6(4) LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 xxxx xxxx 60, 135 Legend: Note 1: 2: 3: 4: 5: 6: 7: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition The SBOREN bit is only available when the BOREN1:BOREN0 configuration bits = 01; otherwise, this bit reads as `0'. These registers and/or bits are not implemented on 64-pin devices and are read as `0'. Reset values are shown for 80-pin devices; individual unimplemented bits should be interpreted as `-'. The PLLEN bit is only available in specific oscillator configuration; otherwise, it is disabled and reads as `0'. See Section 2.6.4 "PLL in INTOSC Modes". RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as `0'. RG5 and LATG5 are only available when Master Clear is disabled (MCLRE configuration bit = 0); otherwise, RG5 and LATG5 read as `0'. Bit 7 and Bit 6 are cleared by user software or by a POR. Bit 21 of TBLPTRU allows access to the device configuration bits. DS39646B-page 78 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY TABLE 5-3: File Name REGISTER FILE SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Details on page: PORTJ(2) RJ7 RJ6 RJ5 RJ4 RJ3 RJ2 RJ1 RJ0 xxxx xxxx 60, 156 PORTH(2) RH7 RH6 RH5 RH4 RH3 RH2 RH1 RH0 0000 xxxx 60, 154 PORTG -- -- RG5(5) RG4 RG3 RG2 RG1 RG0 --xx xxxx 60, 151 PORTF RF7 RF6 RF5 RF4 RF3 RF2 RF1 RF0 x000 0000 60, 149 PORTE RE7 RE6 RE5 RE4 RE3 RE2 RE1 RE0 xxxx xxxx 60, 146 PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx 60, 143 PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx 60, 140 PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx 60, 137 PORTA RA7(4) RA6(4) RA5 RA4 RA3 RA2 RA1 RA0 xx0x 0000 61, 135 0000 0000 61, 252 BRG16 -- WUE ABDEN 01-0 0-00 61, 250 0000 0000 61, 252 SPBRGH1 BAUDCON1 SPBRGH2 EUSART1 Baud Rate Generator Register High Byte ABDOVF RCIDL -- SCKP EUSART2 Baud Rate Generator Register High Byte BAUDCON2 ABDOVF RCIDL -- SCKP BRG16 -- WUE ABDEN 01-0 0-00 61, 250 ECCP1DEL P1RSEN P1DC6 P1DC5 P1DC4 P1DC3 P1DC2 P1DC1 P1DC0 0000 0000 61, 200 61, 178 TMR4 Timer4 Register 0000 0000 PR4 Timer4 Period Register 1111 1111 61, 178 -000 0000 61, 178 T4CON -- T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0 CCPR4H Capture/Compare/PWM Register 4 High Byte xxxx xxxx 61, 180 CCPR4L Capture/Compare/PWM Register 4 Low Byte xxxx xxxx 61, 180 --00 0000 61, 179 CCP4CON -- -- DC4B1 DC4B0 CCP4M3 CCP4M2 CCP4M1 CCP4M0 CCPR5H Capture/Compare/PWM Register 5 High Byte xxxx xxxx 61, 180 CCPR5L Capture/Compare/PWM Register 5 Low Byte xxxx xxxx 61, 180 --00 0000 61, 179 CCP5CON -- -- DC5B1 DC5B0 CCP5M3 CCP5M2 CCP5M1 CCP5M0 SPBRG2 EUSART2 Baud Rate Generator Register Low Byte 0000 0000 61, 252 RCREG2 EUSART2 Receive Register 0000 0000 61, 260 TXREG2 EUSART2 Transmit Register 0000 0000 61, 257 TXSTA2 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 61, 248 RCSTA2 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 61, 249 ECCP3AS1 ECCP3AS0 PSS3AC1 PSS3AC0 PSS3BD1 PSS3BD0 0000 0000 61, 201 P3DC5 P3DC4 P3DC3 P3DC2 P3DC1 P3DC0 0000 0000 61, 200 ECCP2AS1 ECCP2AS0 PSS2AC1 PSS2AC0 PSS2BD1 PSS2BD0 0000 0000 61, 201 P2DC5 P2DC4 P2DC3 P2DC2 P2DC1 P2DC0 0000 0000 61, 200 ECCP3AS ECCP3DEL ECCP2AS ECCP2DEL ECCP3ASE ECCP3AS2 P3RSEN P3DC6 ECCP2ASE ECCP2AS2 P2RSEN P2DC6 SSP2BUF MSSP2 Receive Buffer/Transmit Register xxxx xxxx 61, 170 SSP2ADD MSSP2 Address Register in I2CTM Slave mode. MSSP2 Baud Rate Reload Register in I2C Master mode. 0000 0000 61, 170 SSP2STAT SMP CKE D/A P S R/W UA BF 0000 0000 61, 216 SSP2CON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 61, 217 SSP2CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 61, 218 Legend: Note 1: 2: 3: 4: 5: 6: 7: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition The SBOREN bit is only available when the BOREN1:BOREN0 configuration bits = 01; otherwise, this bit reads as `0'. These registers and/or bits are not implemented on 64-pin devices and are read as `0'. Reset values are shown for 80-pin devices; individual unimplemented bits should be interpreted as `-'. The PLLEN bit is only available in specific oscillator configuration; otherwise, it is disabled and reads as `0'. See Section 2.6.4 "PLL in INTOSC Modes". RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as `0'. RG5 and LATG5 are only available when Master Clear is disabled (MCLRE configuration bit = 0); otherwise, RG5 and LATG5 read as `0'. Bit 7 and Bit 6 are cleared by user software or by a POR. Bit 21 of TBLPTRU allows access to the device configuration bits. 2004 Microchip Technology Inc. Preliminary DS39646B-page 79 PIC18F8722 FAMILY 5.3.5 STATUS REGISTER The STATUS register, shown in Register 5-2, contains the arithmetic status of the ALU. As with any other SFR, it can be the operand for any instruction. If the STATUS register is the destination for an instruction that affects the Z, DC, C, OV or N bits, the results of the instruction are not written; instead, the STATUS register is updated according to the instruction performed. Therefore, the result of an instruction with the STATUS register as its destination may be different than intended. As an example, CLRF STATUS will set the Z bit and leave the remaining Status bits unchanged (`000u u1uu'). REGISTER 5-2: It is recommended that only BCF, BSF, SWAPF, MOVFF and MOVWF instructions are used to alter the STATUS register, because these instructions do not affect the Z, C, DC, OV or N bits in the STATUS register. For other instructions that do not affect Status bits, see the instruction set summaries in Table 26-2 and Table 26-3. Note: The C and DC bits operate as the borrow and digit borrow bits, respectively, in subtraction. STATUS: ARITHMETIC STATUS REGISTER U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x -- -- -- N OV Z DC C bit 7 bit 0 bit 7-5 Unimplemented: Read as `0' bit 4 N: Negative bit This bit is used for signed arithmetic (2's complement). It indicates whether the result was negative (ALU MSB = 1). 1 = Result was negative 0 = Result was positive bit 3 OV: Overflow bit This bit is used for signed arithmetic (2's complement). It indicates an overflow of the 7-bit magnitude which causes the sign bit (bit 7 of the result) to change state. 1 = Overflow occurred for signed arithmetic (in this arithmetic operation) 0 = No overflow occurred bit 2 Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1 DC: Digit Carry/borrow bit For ADDWF, ADDLW, SUBLW and SUBWF instructions: 1 = A carry-out from the 4th low-order bit of the result occurred 0 = No carry-out from the 4th low-order bit of the result Note: bit 0 For borrow, the polarity is reversed. A subtraction is executed by adding the 2's complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either bit 4 or bit 3 of the source register. C: Carry/borrow bit For ADDWF, ADDLW, SUBLW and SUBWF instructions: 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note: For borrow, the polarity is reversed. A subtraction is executed by adding the 2's complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low-order bit of the source register. Legend: DS39646B-page 80 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared Preliminary x = Bit is unknown 2004 Microchip Technology Inc. PIC18F8722 FAMILY 5.4 Data Addressing Modes Note: The execution of some instructions in the core PIC18 instruction set are changed when the PIC18 extended instruction set is enabled. See Section 5.5 "Data Memory and the Extended Instruction Set" for more information. The data memory space can be addressed in several ways. For most instructions, the addressing mode is fixed. Other instructions may use up to three modes, depending on which operands are used and whether or not the extended instruction set is enabled. The addressing modes are: * * * * Inherent Literal Direct Indirect An additional addressing mode, Indexed Literal Offset, is available when the extended instruction set is enabled (XINST configuration bit = 1). Its operation is discussed in greater detail in Section 5.5.1 "Indexed Addressing with Literal Offset". 5.4.1 INHERENT AND LITERAL ADDRESSING Many PIC18 control instructions do not need any argument at all; they either perform an operation that globally affects the device or they operate implicitly on one register. This addressing mode is known as Inherent Addressing. Examples include SLEEP, RESET and DAW. Other instructions work in a similar way but require an additional explicit argument in the opcode. This is known as Literal Addressing mode because they require some literal value as an argument. Examples include ADDLW and MOVLW, which respectively, add or move a literal value to the W register. Other examples include CALL and GOTO, which include a 20-bit program memory address. 5.4.2 The Access RAM bit `a' determines how the address is interpreted. When `a' is `1', the contents of the BSR (Section 5.3.1 "Bank Select Register (BSR)") are used with the address to determine the complete 12-bit address of the register. When `a' is `0', the address is interpreted as being a register in the Access Bank. Addressing that uses the Access RAM is sometimes also known as Direct Forced Addressing mode. A few instructions, such as MOVFF, include the entire 12-bit address (either source or destination) in their opcodes. In these cases, the BSR is ignored entirely. The destination of the operation's results is determined by the destination bit `d'. When `d' is `1', the results are stored back in the source register, overwriting its original contents. When `d' is `0', the results are stored in the W register. Instructions without the `d' argument have a destination that is implicit in the instruction; their destination is either the target register being operated on or the W register. 5.4.3 INDIRECT ADDRESSING Indirect addressing allows the user to access a location in data memory without giving a fixed address in the instruction. This is done by using File Select Registers (FSRs) as pointers to the locations to be read or written to. Since the FSRs are themselves located in RAM as Special File Registers, they can also be directly manipulated under program control. This makes FSRs very useful in implementing data structures, such as tables and arrays in data memory. The registers for indirect addressing are also implemented with Indirect File Operands (INDFs) that permit automatic manipulation of the pointer value with auto-incrementing, auto-decrementing or offsetting with another value. This allows for efficient code, using loops, such as the example of clearing an entire RAM bank in Example 5-5. EXAMPLE 5-5: DIRECT ADDRESSING LFSR CLRF Direct addressing specifies all or part of the source and/or destination address of the operation within the opcode itself. The options are specified by the arguments accompanying the instruction. NEXT In the core PIC18 instruction set, bit-oriented and byteoriented instructions use some version of direct addressing by default. All of these instructions include some 8-bit literal address as their Least Significant Byte. This address specifies either a register address in one of the banks of data RAM (Section 5.3.3 "General Purpose Register File") or a location in the Access Bank (Section 5.3.2 "Access Bank") as the data source for the instruction. BRA CONTINUE 2004 Microchip Technology Inc. BTFSS Preliminary HOW TO CLEAR RAM (BANK 1) USING INDIRECT ADDRESSING FSR0, 100h ; POSTINC0 ; Clear INDF ; register then ; inc pointer FSR0H, 1 ; All done with ; Bank1? NEXT ; NO, clear next ; YES, continue DS39646B-page 81 PIC18F8722 FAMILY 5.4.3.1 FSR Registers and the INDF Operand 5.4.3.2 At the core of indirect addressing are three sets of registers: FSR0, FSR1 and FSR2. Each represents a pair of 8-bit registers, FSRnH and FSRnL. The four upper bits of the FSRnH register are not used so each FSR pair holds a 12-bit value. This represents a value that can address the entire range of the data memory in a linear fashion. The FSR register pairs, then, serve as pointers to data memory locations. In addition to the INDF operand, each FSR register pair also has four additional indirect operands. Like INDF, these are "virtual" registers that cannot be indirectly read or written to. Accessing these registers actually accesses the associated FSR register pair, but also performs a specific action on its stored value. They are: * POSTDEC: accesses the FSR value, then automatically decrements it by 1 afterwards * POSTINC: accesses the FSR value, then automatically increments it by 1 afterwards * PREINC: increments the FSR value by 1, then uses it in the operation * PLUSW: adds the signed value of the W register (range of -127 to 128) to that of the FSR and uses the new value in the operation. Indirect addressing is accomplished with a set of Indirect File Operands, INDF0 through INDF2. These can be thought of as "virtual" registers: they are mapped in the SFR space but are not physically implemented. Reading or writing to a particular INDF register actually accesses its corresponding FSR register pair. A read from INDF1, for example, reads the data at the address indicated by FSR1H:FSR1L. Instructions that use the INDF registers as operands actually use the contents of their corresponding FSR as a pointer to the instruction's target. The INDF operand is just a convenient way of using the pointer. In this context, accessing an INDF register uses the value in the FSR registers without changing them. Similarly, accessing a PLUSW register gives the FSR value offset by the value in the W register; neither value is actually changed in the operation. Accessing the other virtual registers changes the value of the FSR registers. Because indirect addressing uses a full 12-bit address, data RAM banking is not necessary. Thus, the current contents of the BSR and the Access RAM bit have no effect on determining the target address. FIGURE 5-8: FSR Registers and POSTINC, POSTDEC, PREINC and PLUSW Operations on the FSRs with POSTDEC, POSTINC and PREINC affect the entire register pair; that is, rollovers of the FSRnL register from FFh to 00h carry over to the FSRnH register. On the other hand, results of these operations do not change the value of any flags in the STATUS register (e.g., Z, N, OV, etc.). INDIRECT ADDRESSING 000h Using an instruction with one of the indirect addressing registers as the operand.... Bank 0 ADDWF, INDF1, 1 100h Bank 1 200h Bank 2 ...uses the 12-bit address stored in the FSR pair associated with that register.... 300h FSR1H:FSR1L 7 0 x x x x 1 1 1 0 7 0 Bank 3 through Bank 13 1 1 0 0 1 1 0 0 ...to determine the data memory location to be used in that operation. E00h In this case, the FSR1 pair contains ECCh. This means the contents of location ECCh will be added to that of the W register and stored back in ECCh. Bank 14 F00h Bank 15 FFFh Data Memory DS39646B-page 82 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY The PLUSW register can be used to implement a form of indexed addressing in the data memory space. By manipulating the value in the W register, users can reach addresses that are fixed offsets from pointer addresses. In some applications, this can be used to implement some powerful program control structure, such as software stacks, inside of data memory. 5.4.3.3 Operations by FSRs on FSRs Indirect addressing operations that target other FSRs or virtual registers represent special cases. For example, using an FSR to point to one of the virtual registers will not result in successful operations. As a specific case, assume that FSR0H:FSR0L contains FE7h, the address of INDF1. Attempts to read the value of the INDF1 using INDF0 as an operand will return 00h. Attempts to write to INDF1 using INDF0 as the operand will result in a NOP. On the other hand, using the virtual registers to write to an FSR pair may not occur as planned. In these cases, the value will be written to the FSR pair but without any incrementing or decrementing. Thus, writing to INDF2 or POSTDEC2 will write the same value to the FSR2H:FSR2L. Since the FSRs are physical registers mapped in the SFR space, they can be manipulated through all direct operations. Users should proceed cautiously when working on these registers, particularly if their code uses indirect addressing. Similarly, operations by indirect addressing are generally permitted on all other SFRs. Users should exercise the appropriate caution that they do not inadvertently change settings that might affect the operation of the device. 5.5 Data Memory and the Extended Instruction Set Enabling the PIC18 extended instruction set (XINST configuration bit = 1) significantly changes certain aspects of data memory and its addressing. Specifically, the use of the Access Bank for many of the core PIC18 instructions is different; this is due to the introduction of a new addressing mode for the data memory space. What does not change is just as important. The size of the data memory space is unchanged, as well as its linear addressing. The SFR map remains the same. Core PIC18 instructions can still operate in both Direct and Indirect Addressing mode; inherent and literal instructions do not change at all. Indirect addressing with FSR0 and FSR1 also remain unchanged. 2004 Microchip Technology Inc. 5.5.1 INDEXED ADDRESSING WITH LITERAL OFFSET Enabling the PIC18 extended instruction set changes the behavior of indirect addressing using the FSR2 register pair within Access RAM. Under the proper conditions, instructions that use the Access Bank - that is, most bit-oriented and byte-oriented instructions - can invoke a form of indexed addressing using an offset specified in the instruction. This special addressing mode is known as Indexed Addressing with Literal Offset, or Indexed Literal Offset mode. When using the extended instruction set, this addressing mode requires the following: * The use of the Access Bank is forced (`a' = 0) and * The file address argument is less than or equal to 5Fh. Under these conditions, the file address of the instruction is not interpreted as the lower byte of an address (used with the BSR in direct addressing), or as an 8-bit address in the Access Bank. Instead, the value is interpreted as an offset value to an address pointer, specified by FSR2. The offset and the contents of FSR2 are added to obtain the target address of the operation. 5.5.2 INSTRUCTIONS AFFECTED BY INDEXED LITERAL OFFSET MODE Any of the core PIC18 instructions that can use direct addressing are potentially affected by the Indexed Literal Offset Addressing mode. This includes all byte-oriented and bit-oriented instructions, or almost one-half of the standard PIC18 instruction set. Instructions that only use Inherent or Literal Addressing modes are unaffected. Additionally, byte-oriented and bit-oriented instructions are not affected if they do not use the Access Bank (Access RAM bit is `1'), or include a file address of 60h or above. Instructions meeting these criteria will continue to execute as before. A comparison of the different possible addressing modes when the extended instruction set is enabled in shown in Figure 5-9. Those who desire to use byte-oriented or bit-oriented instructions in the Indexed Literal Offset mode should note the changes to assembler syntax for this mode. This is described in more detail in Section 26.2.1 "Extended Instruction Syntax". Preliminary DS39646B-page 83 PIC18F8722 FAMILY FIGURE 5-9: COMPARING ADDRESSING OPTIONS FOR BIT-ORIENTED AND BYTE-ORIENTED INSTRUCTIONS (EXTENDED INSTRUCTION SET ENABLED) EXAMPLE INSTRUCTION: ADDWF, f, d, a (Opcode: 0010 01da ffff ffff) When `a' = 0 and f 60h: The instruction executes in Direct Forced mode. `f' is interpreted as a location in the Access RAM between 060h and 0FFh. This is the same as locations 060h to 07Fh (Bank 0) and F80h to FFFh (Bank 15) of data memory. 000h Locations below 60h are not available in this addressing mode. F00h 060h 080h Bank 0 100h 00h Bank 1 through Bank 14 60h 80h Access RAM Valid range for `f' FFh Bank 15 F80h SFRs FFFh Data Memory When `a' = 0 and f 5Fh: The instruction executes in Indexed Literal Offset mode. `f' is interpreted as an offset to the address value in FSR2. The two are added together to obtain the address of the target register for the instruction. The address can be anywhere in the data memory space. Note that in this mode, the correct syntax is now: ADDWF [k], d where `k' is the same as `f'. 000h Bank 0 080h 100h 001001da ffffffff Bank 1 through Bank 14 FSR2H FSR2L F00h Bank 15 F80h SFRs FFFh Data Memory When `a' = 1 (all values of f): The instruction executes in Direct mode (also known as Direct Long mode). `f' is interpreted as a location in one of the 16 banks of the data memory space. The bank is designated by the Bank Select Register (BSR). The address can be in any implemented bank in the data memory space. BSR 00000000 000h Bank 0 080h 100h Bank 1 through Bank 14 001001da ffffffff F00h Bank 15 F80h SFRs FFFh Data Memory DS39646B-page 84 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY 5.5.3 MAPPING THE ACCESS BANK IN INDEXED LITERAL OFFSET MODE The use of Indexed Literal Offset Addressing mode effectively changes how the first 96 locations of Access RAM (00h to 5Fh) are mapped. Rather than containing just the contents of the bottom half of Bank 0, this mode maps the contents from Bank 0 and a user defined "window" that can be located anywhere in the data memory space. The value of FSR2 establishes the lower boundary of the addresses mapped into the window, while the upper boundary is defined by FSR2 plus 95 (5Fh). Addresses in the Access RAM above 5Fh are mapped as previously described (see Section 5.3.2 "Access Bank"). An example of Access Bank remapping in this addressing mode is shown in Figure 5-10. FIGURE 5-10: Remapping of the Access Bank applies only to operations using the Indexed Literal Offset mode. Operations that use the BSR (Access RAM bit is `1') will continue to use direct addressing as before. 5.6 PIC18 Instruction Execution and the Extended Instruction Set Enabling the extended instruction set adds eight additional commands to the existing PIC18 instruction set. These instructions are executed as described in Section 26.2 "Extended Instruction Set". REMAPPING THE ACCESS BANK WITH INDEXED LITERAL OFFSET ADDRESSING Example Situation: ADDWF f, d, a FSR2H:FSR2L = 120h Locations in the region from the FSR2 pointer (120h) to the pointer plus 05Fh (17Fh) are mapped to the bottom of the Access RAM (000h-05Fh). 000h 05Fh 07Fh Bank 0 100h 120h 17Fh 200h Bank 0 addresses below 5Fh can still be addressed by using the BSR. Bank 1 Window 00h Bank 1 Bank 1 "Window" 5Fh Locations in Bank 0 from 060h to 07Fh are mapped, as usual, to the middle half of the Access Bank. Special File Registers at F80h through FFFh are mapped to 80h through FFh, as usual. Bank 0 Bank 0 Bank 2 through Bank 14 7Fh 80h SFRs FFh Access Bank F00h Bank 15 F80h SFRs FFFh Data Memory 2004 Microchip Technology Inc. Preliminary DS39646B-page 85 PIC18F8722 FAMILY NOTES: DS39646B-page 86 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY 6.0 FLASH PROGRAM MEMORY 6.1 Table Reads and Table Writes The Flash program memory is readable, writable and erasable during normal operation over the entire VDD range. In order to read and write program memory, there are two operations that allow the processor to move bytes between the program memory space and the data RAM: A read from program memory is executed on one byte at a time. A write to program memory is executed on blocks of 64 bytes at a time. Program memory is erased in blocks of 64 bytes at a time. A bulk erase operation may not be issued from user code. * Table Read (TBLRD) * Table Write (TBLWT) Writing or erasing program memory will cease instruction fetches until the operation is complete. The program memory cannot be accessed during the write or erase, therefore, code cannot execute. An internal programming timer terminates program memory writes and erases. A value written to program memory does not need to be a valid instruction. Executing a program memory location that forms an invalid instruction results in a NOP. The program memory space is 16 bits wide, while the data RAM space is 8 bits wide. Table reads and table writes move data between these two memory spaces through an 8-bit register (TABLAT). Table read operations retrieve data from program memory and place it into the data RAM space. Figure 6-1 shows the operation of a table read with program memory and data RAM. Table write operations store data from the data memory space into holding registers in program memory. The procedure to write the contents of the holding registers into program memory is detailed in Section 6.5 "Writing to Flash Program Memory". Figure 6-2 shows the operation of a table write with program memory and data RAM. Table operations work with byte entities. A table block containing data, rather than program instructions, is not required to be word aligned. Therefore, a table block can start and end at any byte address. If a table write is being used to write executable code into program memory, program instructions will need to be word aligned. FIGURE 6-1: TABLE READ OPERATION Instruction: TBLRD* Program Memory Table Pointer(1) TBLPTRU TBLPTRH Table Latch (8-bit) TBLPTRL TABLAT Program Memory (TBLPTR) Note 1: Table Pointer register points to a byte in program memory. 2004 Microchip Technology Inc. Preliminary DS39646B-page 87 PIC18F8722 FAMILY FIGURE 6-2: TABLE WRITE OPERATION Instruction: TBLWT* Program Memory Holding Registers Table Pointer(1) TBLPTRU TBLPTRH Table Latch (8-bit) TBLPTRL TABLAT Program Memory (TBLPTR) Note 1: Table Pointer actually points to one of 64 holding registers, the address of which is determined by TBLPTRL<5:0>. The process for physically writing data to the program memory array is discussed in Section 6.5 "Writing to Flash Program Memory". 6.2 Control Registers Several control registers are used in conjunction with the TBLRD and TBLWT instructions. These include the: * * * * EECON1 register EECON2 register TABLAT register TBLPTR registers 6.2.1 The FREE bit, when set, will allow a program memory erase operation. When FREE is set, the erase operation is initiated on the next WR command. When FREE is clear, only writes are enabled. The WREN bit, when set, will allow a write operation. On power-up, the WREN bit is clear. The WRERR bit is set in hardware when the WR bit is set and cleared when the internal programming timer expires and the write operation is complete. EECON1 AND EECON2 REGISTERS Note: The EECON1 register (Register 6-1) is the control register for memory accesses. The EECON2 register is not a physical register; it is used exclusively in the memory write and erase sequences. Reading EECON2 will read all `0's. The EEPGD control bit determines if the access will be a program or data EEPROM memory access. When clear, any subsequent operations will operate on the data EEPROM memory. When set, any subsequent operations will operate on the program memory. The WR control bit initiates write operations. The bit cannot be cleared, only set, in software; it is cleared in hardware at the completion of the write operation. Note: The CFGS control bit determines if the access will be to the Configuration/Calibration registers or to program memory/data EEPROM memory. When set, subsequent operations will operate on Configuration registers regardless of EEPGD (see Section 25.0 "Special Features of the CPU"). When clear, memory selection access is determined by EEPGD. DS39646B-page 88 During normal operation, the WRERR is read as `1'. This can indicate that a write operation was prematurely terminated by a Reset, or a write operation was attempted improperly. Preliminary The EEIF interrupt flag bit (PIR2<4>) is set when the write is complete. It must be cleared in software. 2004 Microchip Technology Inc. PIC18F8722 FAMILY REGISTER 6-1: EECON1: EEPROM CONTROL REGISTER 1 R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0 EEPGD CFGS -- FREE WRERR WREN WR RD bit 7 bit 0 bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit 1 = Access Flash program memory 0 = Access data EEPROM memory bit 6 CFGS: Flash Program/Data EEPROM or Configuration Select bit 1 = Access Configuration registers 0 = Access Flash program or data EEPROM memory bit 5 Unimplemented: Read as `0' bit 4 FREE: Flash Row Erase Enable bit 1 = Erase the program memory row addressed by TBLPTR on the next WR command (cleared by completion of erase operation) 0 = Perform write only bit 3 WRERR: Flash Program/Data EEPROM Error Flag bit 1 = A write operation is prematurely terminated (any Reset during self-timed programming in normal operation, or an improper write attempt) 0 = The write operation completed Note: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error condition. bit 2 WREN: Flash Program/Data EEPROM Write Enable bit 1 = Allows write cycles to Flash program/data EEPROM 0 = Inhibits write cycles to Flash program/data EEPROM bit 1 WR: Write Control bit 1 = Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle. (The operation is self-timed and the bit is cleared by hardware once write is complete. The WR bit can only be set (not cleared) in software.) 0 = Write cycle to the EEPROM is complete bit 0 RD: Read Control bit 1 = Initiates an EEPROM read (Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared) in software. RD bit cannot be set when EEPGD = 1 or CFGS = 1.) 0 = Does not initiate an EEPROM read Legend: R = Readable bit W = Writable bit S = Bit can be set by software, but not cleared U = Unimplemented bit, read as `0' -n = Value at POR `0' = Bit is cleared 2004 Microchip Technology Inc. `1' = Bit is set Preliminary x = Bit is unknown DS39646B-page 89 PIC18F8722 FAMILY 6.2.2 TABLAT - TABLE LATCH REGISTER 6.2.4 The Table Latch (TABLAT) is an 8-bit register mapped into the SFR space. The Table Latch register is used to hold 8-bit data during data transfers between program memory and data RAM. 6.2.3 TBLPTR is used in reads, writes and erases of the Flash program memory. When a TBLRD is executed, all 22 bits of the TBLPTR determine which byte is read from program memory into TABLAT. TBLPTR - TABLE POINTER REGISTER When a TBLWT is executed, the six LSbs of the Table Pointer register (TBLPTR<5:0>) determine which of the 64 program memory holding registers is written to. When the timed write to program memory begins (via the WR bit), the 16 MSbs of the TBLPTR (TBLPTR<21:6>) determine which program memory block of 64 bytes is written to. For more detail, see Section 6.5 "Writing to Flash Program Memory". The Table Pointer (TBLPTR) register addresses a byte within the program memory. The TBLPTR is comprised of three SFR registers: Table Pointer Upper Byte, Table Pointer High Byte and Table Pointer Low Byte (TBLPTRU:TBLPTRH:TBLPTRL). These three registers join to form a 22-bit wide pointer. The low-order 21 bits allow the device to address up to 2 Mbytes of program memory space. The 22nd bit allows access to the device ID, the user ID and the configuration bits. When an erase of program memory is executed, the 16 MSbs of the Table Pointer register (TBLPTR<21:6>) point to the 64-byte block that will be erased. The Least Significant bits (TBLPTR<5:0>) are ignored. The Table Pointer register, TBLPTR, is used by the TBLRD and TBLWT instructions. These instructions can update the TBLPTR in one of four ways based on the table operation. These operations are shown in Table 6-1. These operations on the TBLPTR only affect the low-order 21 bits. TABLE 6-1: TABLE POINTER BOUNDARIES Figure 6-3 describes the relevant boundaries of TBLPTR based on Flash program memory operations. TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS Example Operation on Table Pointer TBLRD* TBLWT* TBLPTR is not modified TBLRD*+ TBLWT*+ TBLPTR is incremented after the read/write TBLRD*TBLWT*- TBLPTR is decremented after the read/write TBLRD+* TBLWT+* TBLPTR is incremented before the read/write FIGURE 6-3: 21 TABLE POINTER BOUNDARIES BASED ON OPERATION TBLPTRU 16 15 TBLPTRH 8 TABLE ERASE/WRITE TBLPTR<21:6> 7 TBLPTRL 0 TABLE WRITE TBLPTR<5:0> TABLE READ - TBLPTR<21:0> DS39646B-page 90 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY 6.3 Reading the Flash Program Memory The TBLRD instruction is used to retrieve data from program memory and places it into data RAM. Table reads from program memory are performed one byte at a time. FIGURE 6-4: TBLPTR points to a byte address in program space. Executing TBLRD places the byte pointed to into TABLAT. In addition, TBLPTR can be modified automatically for the next table read operation. The internal program memory is typically organized by words. The Least Significant bit of the address selects between the high and low bytes of the word. Figure 6-4 shows the interface between the internal program memory and the TABLAT. READS FROM FLASH PROGRAM MEMORY Program Memory (Even Byte Address) (Odd Byte Address) TBLPTR = xxxxx1 Instruction Register (IR) EXAMPLE 6-1: FETCH TBLRD TBLPTR = xxxxx0 TABLAT Read Register READING A FLASH PROGRAM MEMORY WORD MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF CODE_ADDR_UPPER TBLPTRU CODE_ADDR_HIGH TBLPTRH CODE_ADDR_LOW TBLPTRL ; Load TBLPTR with the base ; address of the word READ_WORD TBLRD*+ MOVF MOVWF TBLRD*+ MOVF MOVF TABLAT, W WORD_EVEN TABLAT, W WORD_ODD 2004 Microchip Technology Inc. ; read into TABLAT and increment ; get data ; read into TABLAT and increment ; get data Preliminary DS39646B-page 91 PIC18F8722 FAMILY 6.4 Erasing Flash Program Memory The minimum erase block is 32 words or 64 bytes. Only through the use of an external programmer, or through ICSP control, can larger blocks of program memory be bulk erased. Word erase in the Flash array is not supported. When initiating an erase sequence from the microcontroller itself, a block of 64 bytes of program memory is erased. The Most Significant 16 bits of the TBLPTR<21:6> point to the block being erased. TBLPTR<5:0> are ignored. 6.4.1 The sequence of events for erasing a block of internal program memory location is: 1. 3. 4. 5. 6. For protection, the write initiate sequence for EECON2 must be used. 7. EXAMPLE 6-2: Load Table Pointer register with address of row being erased. Set the EECON1 register for the erase operation: * set EEPGD bit to point to program memory; * clear the CFGS bit to access program memory; * set WREN bit to enable writes; * set FREE bit to enable the erase. Disable interrupts. Write 55h to EECON2. Write 0AAh to EECON2. Set the WR bit. This will begin the row erase cycle. The CPU will stall for duration of the erase for TIW (see parameter D133A). Re-enable interrupts. 2. The EECON1 register commands the erase operation. The EEPGD bit must be set to point to the Flash program memory. The WREN bit must be set to enable write operations. The FREE bit is set to select an erase operation. A long write is necessary for erasing the internal Flash. Instruction execution is halted while in a long write cycle. The long write will be terminated by the internal programming timer. FLASH PROGRAM MEMORY ERASE SEQUENCE 8. ERASING A FLASH PROGRAM MEMORY ROW MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF CODE_ADDR_UPPER TBLPTRU CODE_ADDR_HIGH TBLPTRH CODE_ADDR_LOW TBLPTRL ; load TBLPTR with the base ; address of the memory block BSF BCF BSF BSF BCF MOVLW MOVWF MOVLW MOVWF BSF BSF EECON1, EECON1, EECON1, EECON1, INTCON, 55h EECON2 0AAh EECON2 EECON1, INTCON, ; ; ; ; ; ERASE_ROW Required Sequence DS39646B-page 92 EEPGD CFGS WREN FREE GIE point to Flash program memory access Flash program memory enable write to memory enable Row Erase operation disable interrupts ; write 55h WR GIE ; write 0AAh ; start erase (CPU stall) ; re-enable interrupts Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY 6.5 Writing to Flash Program Memory The minimum programming block is 32 words or 64 bytes. Word or byte programming is not supported. The long write is necessary for programming the internal Flash. Instruction execution is halted while in a long write cycle. The long write will be terminated by the internal programming timer. Table writes are used internally to load the holding registers needed to program the Flash memory. There are 64 holding registers used by the table writes for programming. The EEPROM on-chip timer controls the write time. The write/erase voltages are generated by an on-chip charge pump, rated to operate over the voltage range of the device. Since the Table Latch (TABLAT) is only a single byte, the TBLWT instruction may need to be executed 64 times for each programming operation. All of the table write operations will essentially be short writes because only the holding registers are written. At the end of updating the 64 holding registers, the EECON1 register must be written to in order to start the programming operation with a long write. FIGURE 6-5: Note: The default value of the holding registers on device Resets and after write operations is FFh. A write of FFh to a holding register does not modify that byte. This means that individual bytes of program memory may be modified, provided that the change does not attempt to change any bit from a `0' to a `1'. When modifying individual bytes, it is not necessary to load all 64 holding registers before executing a write operation. TABLE WRITES TO FLASH PROGRAM MEMORY TABLAT Write Register 8 8 TBLPTR = xxxxx0 TBLPTR = xxxxx1 Holding Register 8 TBLPTR = xxxx3F TBLPTR = xxxxx2 Holding Register 8 Holding Register Holding Register Program Memory 6.5.1 FLASH PROGRAM MEMORY WRITE SEQUENCE The sequence of events for programming an internal program memory location should be: 1. 2. 3. 4. 5. 6. 7. Read 64 bytes into RAM. Update data values in RAM as necessary. Load Table Pointer register with address being erased. Execute the row erase procedure. Load Table Pointer register with address of first byte being written. Write the 64 bytes into the holding registers with auto-increment. Set the EECON1 register for the write operation: * set EEPGD bit to point to program memory; * clear the CFGS bit to access program memory; * set WREN to enable byte writes. 2004 Microchip Technology Inc. 8. 9. 10. 11. 12. Disable interrupts. Write 55h to EECON2. Write 0AAh to EECON2. Set the WR bit. This will begin the write cycle. The CPU will stall for duration of the write for TIW (see parameter D133A). 13. Re-enable interrupts. 14. Verify the memory (table read). An example of the required code is shown in Example 6-3 on the following page. Note: Preliminary Before setting the WR bit, the Table Pointer address needs to be within the intended address range of the 64 bytes in the holding register. DS39646B-page 93 PIC18F8722 FAMILY EXAMPLE 6-3: WRITING TO FLASH PROGRAM MEMORY MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF D'64' COUNTER BUFFER_ADDR_HIGH FSR0H BUFFER_ADDR_LOW FSR0L CODE_ADDR_UPPER TBLPTRU CODE_ADDR_HIGH TBLPTRH CODE_ADDR_LOW TBLPTRL ; number of bytes in erase block TBLRD*+ MOVF MOVWF DECFSZ BRA TABLAT, W POSTINC0 COUNTER READ_BLOCK MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF DATA_ADDR_HIGH FSR0H DATA_ADDR_LOW FSR0L NEW_DATA_LOW POSTINC0 NEW_DATA_HIGH INDF0 MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF BSF BCF BSF BSF BCF MOVLW MOVWF MOVLW MOVWF BSF BSF TBLRD*MOVLW MOVWF MOVLW MOVWF CODE_ADDR_UPPER TBLPTRU CODE_ADDR_HIGH TBLPTRH CODE_ADDR_LOW TBLPTRL EECON1, EEPGD EECON1, CFGS EECON1, WREN EECON1, FREE INTCON, GIE 55h EECON2 0AAh EECON2 EECON1, WR INTCON, GIE MOVLW MOVWF D'64' COUNTER ; number of bytes in holding register MOVFF MOVWF TBLWT+* POSTINC0, WREG TABLAT DECFSZ BRA COUNTER WRITE_WORD_TO_HREGS ; ; ; ; ; ; point to buffer ; Load TBLPTR with the base ; address of the memory block READ_BLOCK ; ; ; ; ; read into TABLAT, and inc get data store data done? repeat MODIFY_WORD ; point to buffer ; update buffer word ERASE_BLOCK Required Sequence BUFFER_ADDR_HIGH FSR0H BUFFER_ADDR_LOW FSR0L ; load TBLPTR with the base ; address of the memory block ; ; ; ; ; point to Flash program memory access Flash program memory enable write to memory enable Row Erase operation disable interrupts ; write 55h ; ; ; ; ; write 0AAh start erase (CPU stall) re-enable interrupts dummy read decrement point to buffer WRITE_BUFFER_BACK WRITE_BYTE_TO_HREGS DS39646B-page 94 Preliminary get low byte of buffer data present data to table latch write data, perform a short write to internal TBLWT holding register. loop until buffers are full 2004 Microchip Technology Inc. PIC18F8722 FAMILY EXAMPLE 6-3: WRITING TO FLASH PROGRAM MEMORY (CONTINUED) PROGRAM_MEMORY BSF BCF BSF BCF MOVLW MOVWF MOVLW MOVWF BSF BSF BCF Required Sequence 6.5.2 EECON1, EECON1, EECON1, INTCON, 55h EECON2 0AAh EECON2 EECON1, INTCON, EECON1, EEPGD CFGS WREN GIE ; ; ; ; ; write 55h ; ; ; ; WR GIE WREN UNEXPECTED TERMINATION OF WRITE OPERATION If a write is terminated by an unplanned event, such as loss of power or an unexpected Reset, the memory location just programmed should be verified and reprogrammed if needed. If the write operation is interrupted by a MCLR Reset or a WDT Time-out Reset during normal operation, the user can check the WRERR bit and rewrite the location(s) as needed. TABLE 6-2: write 0AAh start program (CPU stall) re-enable interrupts disable write to memory 6.5.4 WRITE VERIFY Depending on the application, good programming practice may dictate that the value written to the memory should be verified against the original value. This should be used in applications where excessive writes can stress bits near the specification limit. 6.5.3 point to Flash program memory access Flash program memory enable write to memory disable interrupts PROTECTION AGAINST SPURIOUS WRITES To protect against spurious writes to Flash program memory, the write initiate sequence must also be followed. See Section 25.0 "Special Features of the CPU" for more detail. 6.6 Flash Program Operation During Code Protection See Section 25.5 "Program Verification and Code Protection" for details on code protection of Flash program memory. REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY Name Bit 7 Bit 6 TBLPTRU -- -- Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 bit 21(1) Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) Reset Values on page 57 TBPLTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 57 TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) 57 TABLAT 57 Program Memory Table Latch INTCON GIE/GIEH PEIE/GIEL TMR0IE EECON2 EEPROM Control Register 2 (not a physical register) INT0IE RBIE TMR0IF INT0IF RBIF 57 59 EECON1 EEPGD CFGS -- FREE WRERR WREN WR RD 59 IPR2 OSCFIP CMIP -- EEIP BCL1IP HLVDIP TMR3IP CCP2IP 60 PIR2 OSCFIF CMIF -- EEIF BCL1IF HLVDIF TMR3IF CCP2IF 60 PIE2 OSCFIE CMIE -- EEIE BCL1IE HLVDIE TMR3IE CCP2IE 60 Legend: -- = unimplemented, read as `0'. Shaded cells are not used during Flash/EEPROM access. Note 1: Bit 21 of TBLPTRU allows access to the device configuration bits. 2004 Microchip Technology Inc. Preliminary DS39646B-page 95 PIC18F8722 FAMILY NOTES: DS39646B-page 96 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY 7.0 EXTERNAL MEMORY BUS Note: The bus is implemented with 28 pins, multiplexed across four I/O ports. Three ports (PORTD, PORTE and PORTH) are multiplexed with the address/data bus for a total of 20 available lines, while PORTJ is multiplexed with the bus control signals. The external memory bus is not implemented on PIC18F6527/6622/6627/6722 (64-pin) devices. The External Memory Bus allows the device to access external memory devices (such as Flash, EPROM, SRAM, etc.) as program or data memory. It supports both 8-bit and 16-bit Data Width modes and four address widths from 8 to 20 bits. TABLE 7-1: A list of the pins and their functions is provided in Table 7-1. PIC18F8527/8622/8627/8722 EXTERNAL BUS - I/O PORT FUNCTIONS Name Port Bit External Memory Bus Function RD0/AD0 PORTD 0 Address bit 0 or Data bit 0 RD1/AD1 PORTD 1 Address bit 1 or Data bit 1 RD2/AD2 PORTD 2 Address bit 2 or Data bit 2 RD3/AD3 PORTD 3 Address bit 3 or Data bit 3 RD4/AD4 PORTD 4 Address bit 4 or Data bit 4 RD5/AD5 PORTD 5 Address bit 5 or Data bit 5 RD6/AD6 PORTD 6 Address bit 6 or Data bit 6 RD7/AD7 PORTD 7 Address bit 7 or Data bit 7 RE0/AD8 PORTE 0 Address bit 8 or Data bit 8 RE1/AD9 PORTE 1 Address bit 9 or Data bit 9 RE2/AD10 PORTE 2 Address bit 10 or Data bit 10 RE3/AD11 PORTE 3 Address bit 11 or Data bit 11 RE4/AD12 PORTE 4 Address bit 12 or Data bit 12 RE5/AD13 PORTE 5 Address bit 13 or Data bit 13 RE6/AD14 PORTE 6 Address bit 14 or Data bit 14 RE7/AD15 PORTE 7 Address bit 15 or Data bit 15 RH0/A16 PORTH 0 Address bit 16 RH1/A17 PORTH 1 Address bit 17 RH2/A18 PORTH 2 Address bit 18 RH3/A19 PORTH 3 Address bit 19 RJ0/ALE PORTJ 0 Address Latch Enable (ALE) Control pin RJ1/OE PORTJ 1 Output Enable (OE) Control pin RJ2/WRL PORTJ 2 Write Low (WRL) Control pin RJ3/WRH PORTJ 3 Write High (WRH) Control pin RJ4/BA0 PORTJ 4 Byte Address bit 0 (BA0) RJ5/CE PORTJ 5 Chip Enable (CE) Control pin RJ6/LB PORTJ 6 Lower Byte Enable (LB) Control pin RJ7/UB PORTJ 7 Upper Byte Enable (UB) Control pin Note: For the sake of clarity, only I/O port and external bus assignments are shown here. One or more additional multiplexed features may be available on some pins. 2004 Microchip Technology Inc. Preliminary DS39646B-page 97 PIC18F8722 FAMILY 7.1 External Memory Bus Control The operation of the interface is controlled by the MEMCON register (Register 7-1). This register is available in all program memory operating modes except Microcontroller mode. In this mode, the register is disabled and cannot be written to. The EBDIS bit (MEMCON<7>) controls the operation of the bus and related port functions. Clearing EBDIS enables the interface and disables the I/O functions of the ports, as well as any other functions multiplexed to those pins. Setting the bit enables the I/O ports and other functions but allows the interface to override everything else on the pins when an external memory operation is required. By default, the external bus is always enabled and disables all other I/O. REGISTER 7-1: The operation of the EBDIS bit is also influenced by the program memory mode being used. This is discussed in more detail in Section 7.4 "Program Memory Modes and the External Memory Bus". The WAIT bits allow for the addition of wait states to external memory operations. The use of these bits is discussed in Section 7.3 "Wait States". The WM bits select the particular operating mode used when the bus is operating in 16-bit Data Width mode. These are discussed in more detail in Section 7.5 "16-bit Data Width Modes". These bits have no effect when an 8-bit Data Width mode is selected. MEMCON: EXTERNAL MEMORY BUS CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 EBDIS -- WAIT1 WAIT0 -- -- WM1 WM0 bit7 bit 7 bit0 EBDIS: External Bus Disable bit 1 = External bus enabled when microcontroller accesses external memory; otherwise, all external bus drivers are mapped as I/O ports 0 = External bus always enabled, I/O ports are disabled bit 6 Unimplemented: Read as `0' bit 5-4 WAIT1:WAIT0: Table Reads and Writes Bus Cycle Wait Count bits 11 = Table reads and writes will wait 0 TCY 10 = Table reads and writes will wait 1 TCY 01 = Table reads and writes will wait 2 TCY 00 = Table reads and writes will wait 3 TCY bit 3-2 Unimplemented: Read as `0' bit 1-0 WM1:WM0: TBLWT Operation with 16-bit Data Bus Width Select bits 1x = Word Write mode: TABLAT0 and TABLAT1 word output, WRH active when TABLAT1 written 01 = Byte Select mode: TABLAT data copied on both MSB and LSB, WRH and (UB or LB) will activate 00 = Byte Write mode: TABLAT data copied on both MSB and LSB, WRH or WRL will activate Legend: DS39646B-page 98 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared Preliminary x = Bit is unknown 2004 Microchip Technology Inc. PIC18F8722 FAMILY 7.2 7.2.1 Address and Data Width 21-BIT ADDRESSING PIC18F8527/8622/8627/8722 devices can be independently configured for different address and data widths on the same memory bus. Both address and data width are set by configuration bits in the CONFIG3L register. As configuration bits, this means that these options can only be configured by programming the device and are not controllable in software. As an extension of 20-bit address width operation, the external memory bus can also fully address a 2 Mbyte memory space. This is done by using the Bus Address bit 0 (BA0) control line as the Least Significant bit of the address. The UB and LB control signals may also be used with certain memory devices to select the upper and lower bytes within a 16-bit wide data word. The BW bit selects an 8-bit or 16-bit data bus width. Setting this bit (default) selects a data width of 16 bits. This addressing mode is available in both 8-bit and certain 16-bit Data Width modes. Additional details are provided in Section 7.5.3 "16-bit Byte Select Mode" and Section 7.6 "8-bit Data Width Modes". The ADW1:ADW0 bits determine the address bus width. The available options are 20-bit (default), 16-bit, 12-bit and 8-bit. Selecting any of the options other than 20-bit width makes a corresponding number of high-order lines available for I/O functions; these pins are no longer affected by the setting of the EBDIS bit. For example, selecting a 16-bit Address mode (ADW1:ADW0 = 10) disables A19:A16 and allows PORTH<3:0> to function without interruptions from the bus. Using smaller address widths allows users to tailor the memory bus to the size of the external memory space for a particular design while freeing up pins for dedicated I/O operation. Because the ADW bits have the effect of disabling pins for memory bus operations, it is important to always select an address width at least equal to the data width. If 8-bit or 12-bit address widths are used with a 16-bit data width, the upper bits of data will not be available on the bus. 7.3 Wait States While it may be assumed that external memory devices will operate at the microcontroller clock rate, this is often not the case. In fact, many devices require longer times to write or retrieve data than the time allowed by the execution of table read or table write operations. To compensate for this, the external memory bus can be configured to add a fixed delay to each table operation using the bus. Wait states are enabled by setting the WAIT configuration bit. When enabled, the amount of delay is set by the WAIT1:WAIT0 bits (MEMCON<5:4>). The delay is based on multiples of microcontroller instruction cycle time and are added following the instruction cycle when the table operation is executed. The range is from no delay to 3 TCY (default value). All combinations of address and data widths require multiplexing of address and data information on the same lines. The address and data multiplexing, as well as I/O ports made available by the use of smaller address widths, are summarized in Table 7-2. TABLE 7-2: Data Width 8-bit ADDRESS AND DATA LINES FOR DIFFERENT ADDRESS AND DATA WIDTHS Address Width Multiplexed Data and Address-Only Address Lines (and Lines (and Corresponding Ports) Corresponding Ports) 8-bit -- All of PORTE and PORTH 12-bit AD11:AD8 (PORTE<3:0>) PORTE<7:4>, All of PORTH AD15:AD8 (PORTE<7:0>) All of PORTH A19:A16, AD15:AD8 (PORTH<3:0>, PORTE<7:0>) -- -- All of PORTH A19:A16 (PORTH<3:0>) -- 16-bit AD7:AD0 (PORTD<7:0>) 20-bit 16-bit 16-bit Ports Available for I/O 20-bit 2004 Microchip Technology Inc. AD15:AD0 (PORTD<7:0>, PORTE<7:0>) Preliminary DS39646B-page 99 PIC18F8722 FAMILY 7.4 Program Memory Modes and the External Memory Bus PIC18F8527/8622/8627/8722 devices are capable of operating in any one of four program memory modes, using combinations of on-chip and external program memory. The functions of the multiplexed port pins depends on the program memory mode selected, as well as the setting of the EBDIS bit. In Microcontroller Mode, the bus is not active and the pins have their port functions only. Writes to the MEMCOM register are not permitted. The Reset value of EBDIS (`0') is ignored and EMB pins behave as I/O ports. In Microprocessor Mode, the external bus is always active and the port pins have only the external bus function. The value of EBDIS is ignored. In Microprocessor with Boot Block or Extended Microcontroller Mode, the external program memory bus shares I/O port functions on the pins. When the device is fetching or doing table read/table write operations on the external program memory space, the pins will have the external bus function. If the device is fetching and accessing internal program memory locations only, the EBDIS control bit will change the pins from external memory to I/O port functions. When EBDIS = 0, the pins function as the external bus. When EBDIS = 1, the pins function as I/O ports. If the device fetches or accesses external memory while EBDIS = 1, the pins will switch from I/O to external bus. If the EBDIS bit is set by a program executing from external memory, the action of setting the bit will be delayed until the program branches into the internal memory. At that time, the pins will change from external bus to I/O ports. 7.5 16-bit Data Width Modes In 16-bit Data Width mode, the external memory bus can be connected to external memories in three different configurations: * 16-bit Byte Write * 16-bit Word Write * 16-bit Byte Select The configuration to be used is determined by the WM1:WM0 bits in the MEMCON register (MEMCON<1:0>). These three different configurations allow the designer maximum flexibility in using both 8-bit and 16-bit devices with 16-bit data. For all 16-bit modes, the Address Latch Enable (ALE) pin indicates that the address bits AD<15:0> are available on the external memory interface bus. Following the address latch, the Output Enable signal (OE) will enable both bytes of program memory at once to form a 16-bit instruction word. The Chip Enable signal (CE) is active at any time that the microcontroller accesses external memory, whether reading or writing; it is inactive (asserted high) whenever the device is in Sleep mode. In Byte Select mode, JEDEC standard Flash memories will require BA0 for the byte address line and one I/O line to select between Byte and Word mode. The other 16-bit modes do not need BA0. JEDEC standard static RAM memories will use the UB or LB signals for byte selection. If the device is executing out of internal memory when EBDIS = 0, the memory bus address/data and control pins will not be active. They will go to a state where the active address/data pins are tri-state; the CE, OE, WRH, WRL, UB and LB signals are `1'; and ALE and BA0 are `0'. Note that only those pins associated with the current address width are forced to tri-state; the other pins continue to function as I/O. In the case of 16-bit address width, for example, only AD<15:0> (PORTD and PORTE) are affected; A<19:16> (PORTH<3:0>) continue to function as I/O. In all external memory modes, the bus takes priority over any other peripherals that may share pins with it. This includes the Parallel Slave Port and serial communications modules which would otherwise take priority over the I/O port. DS39646B-page 100 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY 7.5.1 16-BIT BYTE WRITE MODE During a TBLWT instruction cycle, the TABLAT data is presented on the upper and lower bytes of the AD15:AD0 bus. The appropriate WRH or WRL control line is strobed on the LSb of the TBLPTR. Figure 7-1 shows an example of 16-bit Byte Write mode for PIC18F8527/8622/8627/8722 devices. This mode is used for two separate 8-bit memories connected for 16-bit operation. This generally includes basic EPROM and Flash devices. It allows table writes to byte-wide external memories. FIGURE 7-1: 16-BIT BYTE WRITE MODE EXAMPLE D<7:0> PIC18F8X27/8X22 AD<7:0> (MSB) 373 A<19:0> D<15:8> (LSB) A<x:0> A<x:0> D<7:0> D<7:0> CE AD<15:8> 373 OE D<7:0> CE WR(2) OE WR(2) ALE A<19:16>(1) CE OE WRH WRL Address Bus Data Bus Control Lines Note 1: 2: Upper-order address lines are used only for 20-bit address widths. This signal only applies to table writes. See Section 6.1 "Table Reads and Table Writes". 2004 Microchip Technology Inc. Preliminary DS39646B-page 101 PIC18F8722 FAMILY 7.5.2 16-BIT WORD WRITE MODE Figure 7-2 shows an example of 16-bit Word Write mode for PIC18F8527/8622/8627/8722 devices. This mode is used for word-wide memories which includes some of the EPROM and Flash-type memories. This mode allows opcode fetches and table reads from all forms of 16-bit memory and table writes to any type of word-wide external memories. This method makes a distinction between TBLWT cycles to even or odd addresses. During a TBLWT cycle to an even address (TBLPTR<0> = 0), the TABLAT data is transferred to a holding latch and the external address data bus is tri-stated for the data portion of the bus cycle. No write signals are activated. FIGURE 7-2: During a TBLWT cycle to an odd address (TBLPTR<0> = 1), the TABLAT data is presented on the upper byte of the AD15:AD0 bus. The contents of the holding latch are presented on the lower byte of the AD15:AD0 bus. The WRH signal is strobed for each write cycle; the WRL pin is unused. The signal on the BA0 pin indicates the Least Significant bit of TBLPTR but it is left unconnected. Instead, the UB and LB signals are active to select both bytes. The obvious limitation to this method is that the table write must be done in pairs on a specific word boundary to correctly write a word location. 16-BIT WORD WRITE MODE EXAMPLE PIC18F8X27/8X22 AD<7:0> 373 A<20:1> D<15:0> A<x:0> D<15:0> CE AD<15:8> JEDEC Word EPROM Memory OE WR(2) 373 ALE A<19:16>(1) CE OE WRH Address Bus Data Bus Control Lines Note 1: 2: DS39646B-page 102 Upper-order address lines are used only for 20-bit address widths. This signal only applies to table writes. See Section 6.1 "Table Reads and Table Writes". Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY 7.5.3 16-BIT BYTE SELECT MODE Figure 7-3 shows an example of 16-bit Byte Select mode. This mode allows table write operations to word-wide external memories with byte selection capability. This generally includes both word-wide Flash and SRAM devices. During a TBLWT cycle, the TABLAT data is presented on the upper and lower byte of the AD15:AD0 bus. The WRH signal is strobed for each write cycle; the WRL pin is not used. The BA0 or UB/LB signals are used to select the byte to be written, based on the Least Significant bit of the TBLPTR register. FIGURE 7-3: Flash and SRAM devices use different control signal combinations to implement Byte Select mode. JEDEC standard Flash memories require that a controller I/O port pin be connected to the memory's BYTE/WORD pin to provide the select signal. They also use the BA0 signal from the controller as a byte address. JEDEC standard static RAM memories, on the other hand, use the UB or LB signals to select the byte. 16-BIT BYTE SELECT MODE EXAMPLE PIC18F8X27/8X22 AD<7:0> 373 A<20:1> A<x:1> JEDEC Word Flash Memory D<15:0> D<15:0> 138(3) AD<15:8> 373 ALE A<19:16> CE A0 BYTE/WORD OE WR(1) (2) OE WRH WRL A<20:1> A<x:1> BA0 JEDEC Word SRAM Memory I/O D<15:0> D<15:0> CE LB LB UB UB OE WR(1) Address Bus Data Bus Control Lines Note 1: This signal only applies to table writes. See Section 6.1 "Table Reads and Table Writes". 2: Upper-order address lines are used only for 20-bit address width. 3: Demultiplexing is only required when multiple memory devices are accessed. 2004 Microchip Technology Inc. Preliminary DS39646B-page 103 PIC18F8722 FAMILY 7.5.4 16-BIT MODE TIMING The presentation of control signals on the external memory bus is different for the various operating modes. Typical signal timing diagrams are shown in Figure 7-4 through Figure 7-6. All examples assume either 20-bit or 21-bit address widths. FIGURE 7-4: EXTERNAL MEMORY BUS TIMING FOR TBLRD WITH A 1 TCY WAIT STATE (MICROPROCESSOR MODE) Apparent Q Actual Q Q1 Q1 Q2 Q2 Q3 Q3 Q4 Q4 Q1 Q1 Q2 Q2 Q3 Q3 Q4 Q4 00h A<19:16> 3AABh AD<15:0> Q4 Q1 Q4 Q2 Q4 Q3 Q4 Q4 0Ch 0E55h 9256h CF33h BA0 ALE OE WRH `1' `1' WRL `1' `1' CE `0' `0' 1 TCY Wait Memory Cycle Opcode Fetch MOVLW 55h from 007556h Table Read of 92h from 199E67h Instruction Execution TBLRD Cycle 1 TBLRD Cycle 2 FIGURE 7-5: EXTERNAL MEMORY BUS TIMING FOR TBLRD (EXTENDED MICROCONTROLLER MODE) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 0Ch A<19:16> CF33h AD<15:0> 9256h CE ALE OE Memory Cycle Opcode Fetch TBLRD * from 000100h Opcode Fetch MOVLW 55h from 000102h TBLRD 92h from 199E67h Instruction Execution INST(PC - 2) TBLRD Cycle 1 TBLRD Cycle 2 DS39646B-page 104 Preliminary Opcode Fetch ADDLW 55h from 000104h MOVLW 2004 Microchip Technology Inc. PIC18F8722 FAMILY FIGURE 7-6: EXTERNAL MEMORY BUS TIMING FOR SLEEP (MICROPROCESSOR MODE) Q1 Q2 Q4 Q1 Q2 3AAAh Q3 Q4 Q1 00h 00h A<19:16> AD<15:0> Q3 0003h 3AABh 0E55h CE ALE OE Memory Cycle Instruction Execution Note 1: Opcode Fetch SLEEP from 007554h Opcode Fetch MOVLW 55h from 007556h INST(PC - 2) SLEEP Sleep Mode, Bus Inactive(1) Bus becomes inactive regardless of power-managed mode entered when SLEEP is executed. 2004 Microchip Technology Inc. Preliminary DS39646B-page 105 PIC18F8722 FAMILY 7.6 8-bit Data Width Modes The Address Latch Enable (ALE) pin indicates that the address bits A<15:0> are available on the External Memory Interface bus. The Output Enable signal (OE) will enable one byte of program memory for a portion of the instruction cycle, then BA0 will change and the second byte will be enabled to form the 16-bit instruction word. The least significant bit of the address, BA0, must be connected to the memory devices in this mode. The Chip Enable signal (CE) is active at any time that the microcontroller accesses external memory, whether reading or writing; it is inactive (asserted high) whenever the device is in Sleep mode. In 8-bit Data Width mode, the external memory bus operates only in Multiplexed mode; that is, data shares the 8 least significant bits of the address bus. Figure 7-7 shows an example of 8-bit Multiplexed mode for PIC18F8527/8622/8627/8722 devices. This mode is used for a single 8-bit memory connected for 16-bit operation. The instructions will be fetched as two 8-bit bytes on a shared data/address bus. The two bytes are sequentially fetched within one instruction cycle (TCY). Therefore, the designer must choose external memory devices according to timing calculations based on 1/2 TCY (2 times the instruction rate). For proper memory speed selection, glue logic propagation delay times must be considered along with setup and hold times. FIGURE 7-7: This generally includes basic EPROM and Flash devices. It allows table writes to byte-wide external memories. The appropriate level of BA0 control line is strobed on the LSb of the TBLPTR. 8-BIT MULTIPLEXED MODE EXAMPLE D<7:0> PIC18F8X27/8X22 AD<7:0> ALE 373 A<19:0> A<x:1> A0 D<15:8> D<7:0> AD<15:8>(1) CE A<19:16>(1) OE WR(2) BA0 CE OE WRL Address Bus Data Bus Control Lines Note 1: Upper-order address bits are used only for 20-bit address width. The upper AD byte is used for all address widths except 8-bit. 2: This signal only applies to table writes. See Section 6.1 "Table Reads and Table Writes". DS39646B-page 106 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY 7.6.1 8-BIT MODE TIMING The presentation of control signals on the external memory bus is different for the various operating modes. Typical signal timing diagrams are shown in Figure 7-8 through Figure 7-11. FIGURE 7-8: EXTERNAL BUS TIMING FOR TBLRD (MICROPROCESSOR MODE) Q1 Q2 AD<15:8>, A<19:16>(1) Q3 Q4 Q1 Q2 03Ah 08h AAh AD<7:0> Q3 Q4 Q1 Q2 03Ah 00h ABh 55h Q3 Q4 Q1 Q2 CCFh 0Eh 33h Q3 Q4 03Ah 92h ACh 55h 0Fh BA0 ALE OE `1' WRH `1' WRL `1' `1' Memory Cycle Instruction Execution Note 1: Opcode Fetch Opcode Fetch Table Read 92h Opcode Fetch TBLRD * from 007554h MOVLW 55h from 007556h from 199E67h ADDLW 55h from 007558h INST(PC - 2) TBLRD Cycle 1 TBLRD Cycle 2 MOVLW The address lines actually used depends on the address width selected. This example assumes 20-bit addressing. FIGURE 7-9: EXTERNAL BUS TIMING FOR TBLRD (EXTENDED MICROCONTROLLER MODE) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 A<19:16>(1) 0Ch AD<15:8>(1) CFh 33h AD<7:0> Q4 Q1 Q2 Q3 Q4 92h CE ALE OE Memory Cycle Instruction Execution Note 1: Opcode Fetch TBLRD * from 000100h Opcode Fetch MOVLW 55h from 000102h TBLRD 92h from 199E67h INST(PC - 2) TBLRD Cycle 1 TBLRD Cycle 2 Opcode Fetch ADDLW 55h from 000104h MOVLW The address lines actually used depends on the address width selected. This example assumes 20-bit addressing. 2004 Microchip Technology Inc. Preliminary DS39646B-page 107 PIC18F8722 FAMILY FIGURE 7-10: EXTERNAL MEMORY BUS TIMING FOR SLEEP (MICROPROCESSOR MODE) Q1 Q2 A<19:16>(1) Q3 Q4 Q1 Q2 AAh 00h Q1 3Ah 3Ah AD<7:0> Q4 00h 00h AD<15:8>(1) Q3 ABh 03h 55h 0Eh BA0 CE ALE OE Memory Cycle Instruction Execution Note 1: 2: Opcode Fetch SLEEP from 007554h Opcode Fetch MOVLW 55h from 007556h INST(PC - 2) SLEEP Sleep Mode, Bus Inactive(2) The address lines actually used depends on the address width selected. This example assumes 20-bit addressing. Bus becomes inactive regardless of power-managed mode entered when SLEEP is executed. FIGURE 7-11: TYPICAL OPCODE FETCH, 8-BIT MODE Q1 Q2 AD<15:8>(1) Q3 Q4 03Ah AD<7:0> 55h 0Eh 55h BA0 ALE OE `1' `1' WRL Memory Cycle Note 1: Opcode Fetch MOVLW 55h from 007556h The address lines actually used depends on the address width selected. This example assumes 16-bit addressing. DS39646B-page 108 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY 7.7 Operation in Power-Managed Modes In alternate power-managed Run modes, the external bus continues to operate normally. If a clock source with a lower speed is selected, bus operations will run at that speed. In these cases, excessive access times for the external memory may result if wait states have been enabled and added to external memory operations. If operations in a lower power Run mode are anticipated, users should provide in their applications for adjusting memory access times at the lower clock speeds. TABLE 7-3: In Sleep and Idle modes, the microcontroller core does not need to access data; bus operations are suspended. The state of the external bus is frozen with the address/data pins and most of the control pins holding at the same state they were in when the mode was invoked. The only potential changes are the CE, LB and UB pins which are held at logic high. SUMMARY OF REGISTERS ASSOCIATED WITH POWER-MANAGED MODES Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page MEMCON(1) EBDIS -- WAIT1 WAIT0 -- -- WM1 WM0 60 WAIT BW ABW1 ABW0 -- -- PM1 PM0 302 MCLRE -- -- -- -- CONFIG3L(2) CONFIG3H LPT1OSC ECCPMX(2) CCP2MX 303 Legend: -- = unimplemented, read as `0'. Shaded cells are not used by the external memory bus. Note 1: This register is not implemented on 64-pin devices. 2: Unimplemented in PIC18F6527/6622/6627/6722 devices. 2004 Microchip Technology Inc. Preliminary DS39646B-page 109 PIC18F8722 FAMILY NOTES: DS39646B-page 110 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY 8.0 DATA EEPROM MEMORY The data EEPROM is a nonvolatile memory array, separate from the data RAM and program memory, that is used for long-term storage of program data. It is not directly mapped in either the register file or program memory space, but is indirectly addressed through the Special Function Registers (SFRs). The EEPROM is readable and writable during normal operation over the entire VDD range. Five SFRs are used to read and write to the data EEPROM, as well as the program memory. They are: * * * * * EECON1 EECON2 EEDATA EEADR EEADRH The EEPROM data memory is rated for high erase/write cycle endurance. A byte write automatically erases the location and writes the new data (erase-before-write). The write time is controlled by an on-chip timer; it will vary with voltage and temperature, as well as from chipto-chip. Please refer to parameter D122 (Table 28-1 in Section 28.0 "Electrical Characteristics") for exact limits. EEADR and EEADRH Registers The EEADRH:EEADR register pair is used to address the data EEPROM for read and write operations. EEADRH holds the two MSbs of the address; the upper 6 bits are ignored. The 10-bit range of the pair can address a memory range of 1024 bytes (00h to 3FFh). 8.2 Control bit CFGS determines if the access will be to the Configuration registers or to program memory/data EEPROM memory. When set, subsequent operations access Configuration registers. When CFGS is clear, the EEPGD bit selects either program Flash or data EEPROM memory. The WREN bit, when set, will allow a write operation. On power-up, the WREN bit is clear. The WRERR bit is set in hardware when the WREN bit is set and cleared when the internal programming timer expires and the write operation is complete. The data EEPROM allows byte read and write. When interfacing to the data memory block, EEDATA holds the 8-bit data for read/write and the EEADRH:EEADR register pair holds the address of the EEPROM location being accessed. 8.1 The EECON1 register (Register 8-1) is the control register for data and program memory access. Control bit EEPGD determines if the access will be to program or data EEPROM memory. When clear, operations will access the data EEPROM memory. When set, program memory is accessed. EECON1 and EECON2 Registers Note: During normal operation, the WRERR is read as `1'. This can indicate that a write operation was prematurely terminated by a Reset, or a write operation was attempted improperly. The WR control bit initiates write operations. The bit cannot be cleared, only set, in software; it is cleared in hardware at the completion of the write operation. Note: The EEIF interrupt flag bit (PIR2<4>) is set when the write is complete. It must be cleared in software. Control bits, RD and WR, start read and erase/write operations, respectively. These bits are set by firmware and cleared by hardware at the completion of the operation. The RD bit cannot be set when accessing program memory (EEPGD = 1). Program memory is read using table read instructions. See Section 6.1 "Table Reads and Table Writes" regarding table reads. The EECON2 register is not a physical register. It is used exclusively in the memory write and erase sequences. Reading EECON2 will read all `0's. Access to the data EEPROM is controlled by two registers: EECON1 and EECON2. These are the same registers which control access to the program memory and are used in a similar manner for the data EEPROM. 2004 Microchip Technology Inc. Preliminary DS39646B-page 111 PIC18F8722 FAMILY REGISTER 8-1: EECON1: DATA EEPROM CONTROL REGISTER 1 R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0 EEPGD CFGS -- FREE WRERR WREN WR RD bit 7 bit 0 bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit 1 = Access Flash program memory 0 = Access data EEPROM memory bit 6 CFGS: Flash Program/Data EEPROM or Configuration Select bit 1 = Access Configuration registers 0 = Access Flash program or data EEPROM memory bit 5 Unimplemented: Read as `0' bit 4 FREE: Flash Row Erase Enable bit 1 = Erase the program memory row addressed by TBLPTR on the next WR command (cleared by completion of erase operation) 0 = Perform write only bit 3 WRERR: Flash Program/Data EEPROM Error Flag bit 1 = A write operation is prematurely terminated (any Reset during self-timed programming in normal operation, or an improper write attempt) 0 = The write operation completed Note: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error condition. bit 2 WREN: Flash Program/Data EEPROM Write Enable bit 1 = Allows write cycles to Flash program/data EEPROM 0 = Inhibits write cycles to Flash program/data EEPROM bit 1 WR: Write Control bit 1 = Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle. (The operation is self-timed and the bit is cleared by hardware once write is complete. The WR bit can only be set (not cleared) in software.) 0 = Write cycle to the EEPROM is complete bit 0 RD: Read Control bit 1 = Initiates an EEPROM read (Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared) in software. RD bit cannot be set when EEPGD = 1 or CFGS = 1.) 0 = Does not initiate an EEPROM read Legend: DS39646B-page 112 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared Preliminary x = Bit is unknown 2004 Microchip Technology Inc. PIC18F8722 FAMILY 8.3 Reading the Data EEPROM Memory To read a data memory location, the user must write the address to the EEADRH:EEADR register pair, clear the EEPGD control bit (EECON1<7>) and then set control bit, RD (EECON1<0>). The data is available on the very next instruction cycle; therefore, the EEDATA register can be read by the next instruction. EEDATA will hold this value until another read operation, or until it is written to by the user (during a write operation). The basic process is shown in Example 8-1. 8.4 Writing to the Data EEPROM Memory To write an EEPROM data location, the address must first be written to the EEADRH:EEADR register pair and the data written to the EEDATA register. The sequence in Example 8-2 must be followed to initiate the write cycle. The write will not begin if this sequence is not exactly followed (write 55h to EECON2, write 0AAh to EECON2, then set WR bit) for each byte. It is strongly recommended that interrupts be disabled during this code segment. EXAMPLE 8-1: MOVLW MOVWF MOVLW MOVWF BCF BCF BSF MOVF EXAMPLE 8-2: Required Sequence Additionally, the WREN bit in EECON1 must be set to enable writes. This mechanism prevents accidental writes to data EEPROM due to unexpected code execution (i.e., runaway programs). The WREN bit should be kept clear at all times, except when updating the EEPROM. The WREN bit is not cleared by hardware. After a write sequence has been initiated, EECON1, EEADRH:EEADR and EEDATA cannot be modified. The WR bit will be inhibited from being set unless the WREN bit is set. The WREN bit must be set on a previous instruction. Both WR and WREN cannot be set with the same instruction. At the completion of the write cycle, the WR bit is cleared in hardware and the EEPROM Interrupt Flag bit (EEIF) is set. The user may either enable this interrupt, or poll this bit. EEIF must be cleared by software. 8.5 Write Verify Depending on the application, good programming practice may dictate that the value written to the memory should be verified against the original value. This should be used in applications where excessive writes can stress bits near the specification limit. DATA EEPROM READ DATA_EE_ADDRH EEADRH DATA_EE_ADDR EEADR EECON1, EEPGD EECON1, CFGS EECON1, RD EEDATA, W ; ; ; ; ; ; ; ; Upper bits of Data Memory Address to read Lower bits of Data Memory Address to read Point to DATA memory Access EEPROM EEPROM Read W = EEDATA DATA EEPROM WRITE MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF BCF BCF BSF DATA_EE_ADDRH EEADRH DATA_EE_ADDR EEADR DATA_EE_DATA EEDATA EECON1, EPGD EECON1, CFGS EECON1, WREN ; ; ; ; ; ; ; ; ; BCF MOVLW MOVWF MOVLW MOVWF BSF BSF INTCON, GIE 55h EECON2 0AAh EECON2 EECON1, WR INTCON, GIE ; ; ; ; ; ; ; BCF EECON1, WREN ; User code execution ; Disable writes on write complete (EEIF set) 2004 Microchip Technology Inc. Upper bits of Data Memory Address to write Lower bits of Data Memory Address to write Data Memory Value to write Point to DATA memory Access EEPROM Enable writes Disable Interrupts Write 55h Write 0AAh Set WR bit to begin write Enable Interrupts Preliminary DS39646B-page 113 PIC18F8722 FAMILY 8.6 Operation During Code-Protect 8.8 Data EEPROM memory has its own code-protect bits in Configuration Words. External read and write operations are disabled if code protection is enabled. The microcontroller itself can both read and write to the internal data EEPROM regardless of the state of the code-protect configuration bit. Refer to Section 25.0 "Special Features of the CPU" for additional information. 8.7 Protection Against Spurious Write There are conditions when the device may not want to write to the data EEPROM memory. To protect against spurious EEPROM writes, various mechanisms have been implemented. On power-up, the WREN bit is cleared. In addition, writes to the EEPROM are blocked during the Power-up Timer period (TPWRT, parameter 33). Using the Data EEPROM The data EEPROM is a high endurance, byte addressable array that has been optimized for the storage of frequently changing information (e.g., program variables or other data that are updated often). Frequently changing values will typically be updated more often than specification D124. If this is not the case, an array refresh must be performed. For this reason, variables that change infrequently (such as constants, IDs, calibration, etc.) should be stored in Flash program memory. A simple data EEPROM refresh routine is shown in Example 8-3. Note: If data EEPROM is only used to store constants and/or data that changes often, an array refresh is likely not required. See specification D124. The write initiate sequence and the WREN bit together help prevent an accidental write during brown-out, power glitch or software malfunction. EXAMPLE 8-3: DATA EEPROM REFRESH ROUTINE CLRF CLRF BCF BCF BCF BSF EEADR EEADRH EECON1, EECON1, INTCON, EECON1, BSF MOVLW MOVWF MOVLW MOVWF BSF BTFSC BRA INCFSZ BRA INCFSZ BRA EECON1, RD 55h EECON2 0AAh EECON2 EECON1, WR EECON1, WR $-2 EEADR, F LOOP EEADRH, F LOOP BCF BSF EECON1, WREN INTCON, GIE CFGS EEPGD GIE WREN Loop DS39646B-page 114 ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; Start at address 0 Set for memory Set for Data EEPROM Disable interrupts Enable writes Loop to refresh array Read current address Write 55h Write 0AAh Set WR bit to begin write Wait for write to complete Increment Not zero, Increment Not zero, address do it again the high address do it again ; Disable writes ; Enable interrupts Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY TABLE 8-1: Name INTCON EEADRH REGISTERS ASSOCIATED WITH DATA EEPROM MEMORY Bit 7 Bit 6 GIE/GIEH PEIE/GIEL -- -- Bit 5 Bit 4 Bit 3 Bit 2 TMR0IE INT0IE RBIE TMR0IF -- -- -- -- Bit 1 Bit 0 INT0IF RBIF EEPROM Address Register High Byte Reset Values on page 57 59 EEADR EEPROM Address Register Low Byte 59 EEDATA EEPROM Data Register 59 EECON2 EEPROM Control Register 2 (not a physical register) 59 EECON1 EEPGD CFGS -- FREE WRERR WREN WR RD 59 IPR2 OSCFIP CMIP -- EEIP BCL1IP HLVDIP TMR3IP CCP2IP 60 PIR2 OSCFIF CMIF -- EEIF BCL1IF HLVDIF TMR3IF CCP2IF 60 PIE2 OSCFIE CMIE -- EEIE BCL1IE HLVDIE TMR3IE CCP2IE 60 Legend: -- = unimplemented, read as `0'. Shaded cells are not used during Flash/EEPROM access. 2004 Microchip Technology Inc. Preliminary DS39646B-page 115 PIC18F8722 FAMILY NOTES: DS39646B-page 116 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY 9.0 8 x 8 HARDWARE MULTIPLIER 9.1 Introduction EXAMPLE 9-1: MOVF MULWF All PIC18 devices include an 8 x 8 hardware multiplier as part of the ALU. The multiplier performs an unsigned operation and yields a 16-bit result that is stored in the product register pair, PRODH:PRODL. The multiplier's operation does not affect any flags in the STATUS register. ARG1, W ARG2 ; ; ARG1 * ARG2 -> ; PRODH:PRODL EXAMPLE 9-2: Making multiplication a hardware operation allows it to be completed in a single instruction cycle. This has the advantages of higher computational throughput and reduced code size for multiplication algorithms and allows the PIC18 devices to be used in many applications previously reserved for digital signal processors. A comparison of various hardware and software multiply operations, along with the savings in memory and execution time, is shown in Table 9-1. 9.2 8 x 8 UNSIGNED MULTIPLY ROUTINE 8 x 8 SIGNED MULTIPLY ROUTINE MOVF MULWF ARG1, W ARG2 BTFSC SUBWF ARG2, SB PRODH, F MOVF BTFSC SUBWF ARG2, W ARG1, SB PRODH, F ; ; ; ; ; ARG1 * ARG2 -> PRODH:PRODL Test Sign Bit PRODH = PRODH - ARG1 ; Test Sign Bit ; PRODH = PRODH ; - ARG2 Operation Example 9-1 shows the instruction sequence for an 8 x 8 unsigned multiplication. Only one instruction is required when one of the arguments is already loaded in the WREG register. Example 9-2 shows the sequence to do an 8 x 8 signed multiplication. To account for the sign bits of the arguments, each argument's Most Significant bit (MSb) is tested and the appropriate subtractions are done. TABLE 9-1: PERFORMANCE COMPARISON FOR VARIOUS MULTIPLY OPERATIONS Routine 8 x 8 unsigned 8 x 8 signed 16 x 16 unsigned 16 x 16 signed Multiply Method Without hardware multiply Program Memory (Words) Cycles (Max) @ 40 MHz @ 10 MHz @ 4 MHz 13 69 6.9 s 27.6 s 69 s Time Hardware multiply 1 1 100 ns 400 ns 1 s Without hardware multiply 33 91 9.1 s 36.4 s 91 s Hardware multiply 6 6 600 ns 2.4 s 6 s Without hardware multiply 21 242 24.2 s 96.8 s 242 s Hardware multiply 28 28 2.8 s 11.2 s 28 s Without hardware multiply 52 254 25.4 s 102.6 s 254 s Hardware multiply 35 40 4.0 s 16.0 s 40 s 2004 Microchip Technology Inc. Preliminary DS39646B-page 117 PIC18F8722 FAMILY Example 9-3 shows the sequence to do a 16 x 16 unsigned multiplication. Equation 9-1 shows the algorithm that is used. The 32-bit result is stored in four registers (RES3:RES0). EQUATION 9-1: RES3:RES0 = = EXAMPLE 9-3: 16 x 16 UNSIGNED MULTIPLICATION ALGORITHM ARG1H:ARG1L * ARG2H:ARG2L (ARG1H * ARG2H * 216) + (ARG1H * ARG2L * 28) + (ARG1L * ARG2H * 28) + (ARG1L * ARG2L) EQUATION 9-2: RES3:RES0 = ARG1H:ARG1L * ARG2H:ARG2L = (ARG1H * ARG2H * 216) + (ARG1H * ARG2L * 28) + (ARG1L * ARG2H * 28) + (ARG1L * ARG2L) + (-1 * ARG2H<7> * ARG1H:ARG1L * 216) + (-1 * ARG1H<7> * ARG2H:ARG2L * 216) EXAMPLE 9-4: 16 x 16 UNSIGNED MULTIPLY ROUTINE MOVF MULWF ARG1L, W ARG2L MOVFF MOVFF PRODH, RES1 PRODL, RES0 MOVF MULWF ARG1H, W ARG2H MOVFF MOVFF PRODH, RES3 PRODL, RES2 MOVF MULWF ARG1L, W ARG2H MOVF ADDWF MOVF ADDWFC CLRF ADDWFC PRODL, W RES1, F PRODH, W RES2, F WREG RES3, F MOVF MULWF ARG1H, W ARG2L MOVF ADDWF MOVF ADDWFC CLRF ADDWFC PRODL, W RES1, F PRODH, W RES2, F WREG RES3, F ; ARG1L * ARG2L-> ; PRODH:PRODL ; ; ARG1L * ARG2H-> PRODH:PRODL Add cross products ARG1H * ARG2L-> PRODH:PRODL Add cross products MOVFF MOVFF PRODH, RES1 PRODL, RES0 MOVF MULWF ARG1H, W ARG2H MOVFF MOVFF PRODH, RES3 PRODL, RES2 MOVF MULWF ARG1L, W ARG2H MOVF ADDWF MOVF ADDWFC CLRF ADDWFC PRODL, W RES1, F PRODH, W RES2, F WREG RES3, F MOVF MULWF ARG1H, W ARG2L MOVF ADDWF MOVF ADDWFC CLRF ADDWFC PRODL, W RES1, F PRODH, W RES2, F WREG RES3, F BTFSS BRA MOVF SUBWF MOVF SUBWFB ARG2H, 7 SIGN_ARG1 ARG1L, W RES2 ARG1H, W RES3 ; ARG2H:ARG2L neg? ; no, check ARG1 ; ; ; ARG1H, 7 CONT_CODE ARG2L, W RES2 ARG2H, W RES3 ; ARG1H:ARG1L neg? ; no, done ; ; ; ; ARG1L * ARG2L -> ; PRODH:PRODL ; ; ; ARG1H * ARG2H -> ; PRODH:PRODL ; ; ; ; ; ; ; ; ; ; ARG1L * ARG2H -> PRODH:PRODL Add cross products ; ; ; ; ; ; ; ; ; ARG1H * ARG2L -> PRODH:PRODL Add cross products ; Example 9-4 shows the sequence to do a 16 x 16 signed multiply. Equation 9-2 shows the algorithm used. The 32-bit result is stored in four registers (RES3:RES0). To account for the sign bits of the arguments, the MSb for each argument pair is tested and the appropriate subtractions are done. DS39646B-page 118 ARG1L, W ARG2L ; ; ; ; ; ; ; ; ; ; ; MOVF MULWF ; ; ; ; ; ; ; ; ; ; 16 x 16 SIGNED MULTIPLY ROUTINE ; ; ; ARG1H * ARG2H-> ; PRODH:PRODL ; ; 16 x 16 SIGNED MULTIPLICATION ALGORITHM ; SIGN_ARG1 BTFSS BRA MOVF SUBWF MOVF SUBWFB ; CONT_CODE : Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY 10.0 INTERRUPTS The PIC18F8722 family of devices have multiple interrupt sources and an interrupt priority feature that allows most interrupt sources to be assigned a high priority level or a low priority level. The high priority interrupt vector is at 0008h and the low priority interrupt vector is at 0018h. High priority interrupt events will interrupt any low priority interrupts that may be in progress. There are ten registers which are used to control interrupt operation. These registers are: * * * * * * * RCON INTCON INTCON2 INTCON3 PIR1, PIR2, PIR3 PIE1, PIE2, PIE3 IPR1, IPR2, IPR3 It is recommended that the Microchip header files supplied with MPLAB(R) IDE be used for the symbolic bit names in these registers. This allows the assembler/ compiler to automatically take care of the placement of these bits within the specified register. In general, interrupt sources have three bits to control their operation. They are: * Flag bit to indicate that an interrupt event occurred * Enable bit that allows program execution to branch to the interrupt vector address when the flag bit is set * Priority bit to select high priority or low priority When the IPEN bit is cleared (default state), the interrupt priority feature is disabled and interrupts are compatible with PICmicro(R) mid-range devices. In Compatibility mode, the interrupt priority bits for each source have no effect. INTCON<6> is the PEIE bit, which enables/disables all peripheral interrupt sources. INTCON<7> is the GIE bit, which enables/disables all interrupt sources. All interrupts branch to address 0008h in Compatibility mode. When an interrupt is responded to, the global interrupt enable bit is cleared to disable further interrupts. If the IPEN bit is cleared, this is the GIE bit. If interrupt priority levels are used, this will be either the GIEH or GIEL bit. High priority interrupt sources can interrupt a low priority interrupt. Low priority interrupts are not processed while high priority interrupts are in progress. The return address is pushed onto the stack and the PC is loaded with the interrupt vector address (0008h or 0018h). Once in the Interrupt Service Routine, the source(s) of the interrupt can be determined by polling the interrupt flag bits. The interrupt flag bits must be cleared in software before re-enabling interrupts to avoid recursive interrupts. The "return from interrupt" instruction, RETFIE, exits the interrupt routine and sets the GIE bit (GIEH or GIEL if priority levels are used), which re-enables interrupts. For external interrupt events, such as the INT pins or the PORTB input change interrupt, the interrupt latency will be three to four instruction cycles. The exact latency is the same for one or two-cycle instructions. Individual interrupt flag bits are set, regardless of the status of their corresponding enable bit or the GIE bit. Note: The interrupt priority feature is enabled by setting the IPEN bit (RCON<7>). When interrupt priority is enabled, there are two bits which enable interrupts globally. Setting the GIEH bit (INTCON<7>) enables all interrupts that have the priority bit set (high priority). Setting the GIEL bit (INTCON<6>) enables all interrupts that have the priority bit cleared (low priority). When the interrupt flag, enable bit and appropriate global interrupt enable bit are set, the interrupt will vector immediately to address 0008h or 0018h, depending on the priority bit setting. Individual interrupts can be disabled through their corresponding enable bits. 2004 Microchip Technology Inc. Preliminary Do not use the MOVFF instruction to modify any of the interrupt control registers while any interrupt is enabled. Doing so may cause erratic microcontroller behavior. DS39646B-page 119 PIC18F8722 FAMILY FIGURE 10-1: PIC18F8722 FAMILY INTERRUPT LOGIC Wake-up if in Idle or Sleep modes TMR0IF TMR0IE TMR0IP RBIF RBIE RBIP INT0IF INT0IE INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP INT3IF INT3IE INT3IP PIR1<7:0> PIE1<7:0> IPR1<7:0> PIR2<7:6, 4:0> PIE2<7:6, 4:0> IPR2<7:6, 4:0> Interrupt to CPU Vector to Location 0008h GIEH/GIE IPEN PIR3<7:0> PIE3<7:0> IPR3<7:0> IPEN GIEL/PEIE IPEN High Priority Interrupt Generation Low Priority Interrupt Generation PIR1<7:0> PIE1<7:0> IPR1<7:0> PIR2<7:6, 4:0> PIE2<7:6, 4:0> IPR2<7:6, 4:0> PIR3<7:0> PIE3<7:0> IPR3<7:0> TMR0IF TMR0IE TMR0IP RBIF RBIE RBIP Interrupt to CPU Vector to Location 0018h IPEN GIEH/GIE GIEL/PEIE INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP INT3IF INT3IE INT3IP DS39646B-page 120 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY 10.1 INTCON Registers Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. The INTCON registers are readable and writable registers which contain various enable, priority and flag bits. REGISTER 10-1: INTCON: INTERRUPT CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF bit 7 bit 0 bit 7 GIE/GIEH: Global Interrupt Enable bit When IPEN = 0: 1 = Enables all unmasked interrupts 0 = Disables all interrupts When IPEN = 1: 1 = Enables all high priority interrupts 0 = Disables all interrupts bit 6 PEIE/GIEL: Peripheral Interrupt Enable bit When IPEN = 0: 1 = Enables all unmasked peripheral interrupts 0 = Disables all peripheral interrupts When IPEN = 1: 1 = Enables all low priority peripheral interrupts 0 = Disables all low priority peripheral interrupts bit 5 TMR0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 overflow interrupt 0 = Disables the TMR0 overflow interrupt bit 4 INT0IE: INT0 External Interrupt Enable bit 1 = Enables the INT0 external interrupt 0 = Disables the INT0 external interrupt bit 3 RBIE: RB Port Change Interrupt Enable bit 1 = Enables the RB port change interrupt 0 = Disables the RB port change interrupt bit 2 TMR0IF: TMR0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow bit 1 INT0IF: INT0 External Interrupt Flag bit 1 = The INT0 external interrupt occurred (must be cleared in software) 0 = The INT0 external interrupt did not occur bit 0 RBIF: RB Port Change Interrupt Flag bit 1 = At least one of the RB7:RB4 pins changed state (must be cleared in software) 0 = None of the RB7:RB4 pins have changed state Note: A mismatch condition will continue to set this bit. Reading PORTB will end the mismatch condition and allow the bit to be cleared. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared 2004 Microchip Technology Inc. Preliminary x = Bit is unknown DS39646B-page 121 PIC18F8722 FAMILY REGISTER 10-2: INTCON2: INTERRUPT CONTROL REGISTER 2 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 RBPU INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INT3IP RBIP bit 7 bit 0 bit 7 RBPU: PORTB Pull-up Enable bit 1 = All PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values bit 6 INTEDG0: External Interrupt 0 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 5 INTEDG1: External Interrupt 1 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 4 INTEDG2: External Interrupt 2 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 3 INTEDG3: External Interrupt 3 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 2 TMR0IP: TMR0 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 INT3IP: INT3 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 RBIP: RB Port Change Interrupt Priority bit 1 = High priority 0 = Low priority Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared Note: DS39646B-page 122 x = Bit is unknown Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY REGISTER 10-3: INTCON3: INTERRUPT CONTROL REGISTER 3 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 INT2IP INT1IP INT3IE INT2IE INT1IE INT3IF INT2IF INT1IF bit 7 bit 0 bit 7 INT2IP: INT2 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 INT1IP: INT1 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 INT3IE: INT3 External Interrupt Enable bit 1 = Enables the INT3 external interrupt 0 = Disables the INT3 external interrupt bit 4 INT2IE: INT2 External Interrupt Enable bit 1 = Enables the INT2 external interrupt 0 = Disables the INT2 external interrupt bit 3 INT1IE: INT1 External Interrupt Enable bit 1 = Enables the INT1 external interrupt 0 = Disables the INT1 external interrupt bit 2 INT3IF: INT3 External Interrupt Flag bit 1 = The INT3 external interrupt occurred (must be cleared in software) 0 = The INT3 external interrupt did not occur bit 1 INT2IF: INT2 External Interrupt Flag bit 1 = The INT2 external interrupt occurred (must be cleared in software) 0 = The INT2 external interrupt did not occur bit 0 INT1IF: INT1 External Interrupt Flag bit 1 = The INT1 external interrupt occurred (must be cleared in software) 0 = The INT1 external interrupt did not occur Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared Note: 2004 Microchip Technology Inc. x = Bit is unknown Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. Preliminary DS39646B-page 123 PIC18F8722 FAMILY 10.2 PIR Registers Note 1: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Interrupt Enable bit, GIE (INTCON<7>). The PIR registers contain the individual flag bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Request (Flag) registers (PIR1, PIR2, PIR3). 2: User software should ensure the appropriate interrupt flag bits are cleared prior to enabling an interrupt and after servicing that interrupt. REGISTER 10-4: PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1 R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 PSPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF bit 7 bit 0 bit 7 PSPIF: Parallel Slave Port Read/Write Interrupt Flag bit 1 = A read or a write operation has taken place (must be cleared in software) 0 = No read or write has occurred bit 6 ADIF: A/D Converter Interrupt Flag bit 1 = An A/D conversion completed (must be cleared in software) 0 = The A/D conversion is not complete bit 5 RC1IF: EUSART1 Receive Interrupt Flag bit 1 = The EUSART1 receive buffer, RCREG1, is full (cleared when RCREG1 is read) 0 = The EUSART1 receive buffer is empty bit 4 TX1IF: EUSART1 Transmit Interrupt Flag bit 1 = The EUSART1 transmit buffer, TXREG1, is empty (cleared when TXREG1 is written) 0 = The EUSART1 transmit buffer is full bit 3 SSP1IF: MSSP1 Interrupt Flag bit 1 = The transmission/reception is complete (must be cleared in software) 0 = Waiting to transmit/receive bit 2 CCP1IF: ECCP1 Interrupt Flag bit Capture mode: 1 = A TMR1/TMR3 register capture occurred (must be cleared in software) 0 = No TMR1/TMR3 register capture occurred Compare mode: 1 = A TMR1/TMR3 register compare match occurred (must be cleared in software) 0 = No TMR1/TMR3 register compare match occurred PWM mode: Unused in this mode. bit 1 TMR2IF: TMR2 to PR2 Match Interrupt Flag bit 1 = TMR2 to PR2 match occurred (must be cleared in software) 0 = No TMR2 to PR2 match occurred bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = TMR1 register overflowed (must be cleared in software) 0 = TMR1 register did not overflow Legend: DS39646B-page 124 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared Preliminary x = Bit is unknown 2004 Microchip Technology Inc. PIC18F8722 FAMILY REGISTER 10-5: PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 OSCFIF CMIF -- EEIF BCL1IF HLVDIF TMR3IF CCP2IF bit 7 bit 0 bit 7 OSCFIF: Oscillator Fail Interrupt Flag bit 1 = Device oscillator failed, clock input has changed to INTOSC (must be cleared in software) 0 = Device clock operating bit 6 CMIF: Comparator Interrupt Flag bit 1 = Comparator input has changed (must be cleared in software) 0 = Comparator input has not changed bit 5 Unimplemented: Read as `0' bit 4 EEIF: EEPROM or Flash Write Operation Interrupt Flag bit 1 = The write operation is complete (must be cleared in software) 0 = The write operation is not complete or has not been started bit 3 BCL1IF: MSSP1 Bus Collision Interrupt Flag bit 1 = A bus collision occurred while the MSSP1 module configured in I2CTM Master mode was transmitting (must be cleared in software) 0 = No bus collision occurred bit 2 HLVDIF: High/Low-Voltage Detect Interrupt Flag bit 1 = A low-voltage condition occurred (must be cleared in software) 0 = The device voltage is above the Low-Voltage Detect trip point bit 1 TMR3IF: TMR3 Overflow Interrupt Flag bit 1 = TMR3 register overflowed (must be cleared in software) 0 = TMR3 register did not overflow bit 0 CCP2IF: ECCP2 Interrupt Flag bit Capture mode: 1 = A TMR1/TMR3 register capture occurred (must be cleared in software) 0 = No TMR1/TMR3 register capture occurred Compare mode: 1 = A TMR1/TMR3 register compare match occurred (must be cleared in software) 0 = No TMR1/TMR3 register compare match occurred PWM mode: Unused in this mode. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared 2004 Microchip Technology Inc. Preliminary x = Bit is unknown DS39646B-page 125 PIC18F8722 FAMILY REGISTER 10-6: PIR3: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 3 R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 SSP2IF BCL2IF RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF bit 7 bit 0 bit 7 SSP2IF: MSSP2 Interrupt Flag bit 1 = The transmission/reception is complete (must be cleared in software) 0 = Waiting to transmit/receive bit 6 BCL2IF: MSSP2 Bus Collision Interrupt Flag bit 1 = A bus collision has occurred while the MSSP2 module configured in I2CTM master was transmitting (must be cleared in software) 0 = No bus collision occurred bit 5 RC2IF: EUSART2 Receive Interrupt Flag bit 1 = The EUSART2 receive buffer, RCREG2, is full (cleared when RCREG2 is read) 0 = The EUSART2 receive buffer is empty bit 4 TX2IF: EUSART2 Transmit Interrupt Flag bit 1 = The EUSART2 transmit buffer, TXREG2, is empty (cleared when TXREG2 is written) 0 = The EUSART2 transmit buffer is full bit 3 TMR4IF: TMR4 to PR4 Match Interrupt Flag bit 1 = TMR4 to PR4 match occurred (must be cleared in software) 0 = No TMR4 to PR4 match occurred bit 2 CCP5IF: CCP5 Interrupt Flag bit Capture Mode: 1 = A TMR register capture occurred (must be cleared in software) 0 = No TMR register capture occurred Compare Mode: 1 = A TMR register compare match occurred (must be cleared in software) 0 = No TMR register compare match occurred PWM Mode: Not used in PWM mode bit 1 CCP4IF: CCP4 Interrupt Flag bit Capture Mode: 1 = A TMR register capture occurred (must be cleared in software) 0 = No TMR register capture occurred Compare Mode: 1 = A TMR register compare match occurred (must be cleared in software) 0 = No TMR register compare match occurred PWM Mode: Not used in PWM mode bit 0 CCP3IF: ECCP3 Interrupt Flag bit Capture Mode: 1 = A TMR register capture occurred (must be cleared in software) 0 = No TMR register capture occurred Compare Mode: 1 = A TMR register compare match occurred (must be cleared in software) 0 = No TMR register compare match occurred PWM Mode: Not used in PWM mode Legend: DS39646B-page 126 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared Preliminary x = Bit is unknown 2004 Microchip Technology Inc. PIC18F8722 FAMILY 10.3 PIE Registers The PIE registers contain the individual enable bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Enable registers (PIE1, PIE2, PIE3). When IPEN = 0, the PEIE bit must be set to enable any of these peripheral interrupts. REGISTER 10-7: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PSPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE bit 7 bit 0 bit 7 PSPIE: Parallel Slave Port Read/Write Interrupt Enable bit 1 = Enables the PSP read/write interrupt 0 = Disables the PSP read/write interrupt bit 6 ADIE: A/D Converter Interrupt Enable bit 1 = Enables the A/D interrupt 0 = Disables the A/D interrupt bit 5 RC1IE: EUSART1 Receive Interrupt Enable bit 1 = Enables the EUSART1 receive interrupt 0 = Disables the EUSART1 receive interrupt bit 4 TX1IE: EUSART1 Transmit Interrupt Enable bit 1 = Enables the EUSART1 transmit interrupt 0 = Disables the EUSART1 transmit interrupt bit 3 SSP1IE: MSSP1 Interrupt Enable bit 1 = Enables the MSSP1 interrupt 0 = Disables the MSSP1 interrupt bit 2 CCP1IE: ECCP1 Interrupt Enable bit 1 = Enables the ECCP1 interrupt 0 = Disables the ECCP1 interrupt bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared 2004 Microchip Technology Inc. Preliminary x = Bit is unknown DS39646B-page 127 PIC18F8722 FAMILY REGISTER 10-8: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 OSCFIE CMIE -- EEIE BCL1IE HLVDIE TMR3IE CCP2IE bit 7 bit 0 bit 7 OSCFIE: Oscillator Fail Interrupt Enable bit 1 = Enabled 0 = Disabled bit 6 CMIE: Comparator Interrupt Enable bit 1 = Enabled 0 = Disabled bit 5 Unimplemented: Read as `0' bit 4 EEIE: Interrupt Enable bit 1 = Enabled 0 = Disabled bit 3 BCL1IE: MSSP1 Bus Collision Interrupt Enable bit 1 = Enabled 0 = Disabled bit 2 HLVDIE: High/Low-Voltage Detect Interrupt Enable bit 1 = Enabled 0 = Disabled bit 1 TMR3IE: TMR3 Overflow Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 CCP2IE: ECCP2 Interrupt Enable bit 1 = Enabled 0 = Disabled Legend: DS39646B-page 128 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared Preliminary x = Bit is unknown 2004 Microchip Technology Inc. PIC18F8722 FAMILY REGISTER 10-9: PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3 R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 SSP2IE BCL2IE RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE bit 7 bit 0 bit 7 SSP2IE: MSSP2 Interrupt Enable bit 1 = Enables the MSSP2 interrupt 0 = Disables the MSSP2 interrupt bit 6 BCL2IE: MSSP2 Bus Collision Interrupt Enable bit 1 = Enabled 0 = Disabled bit 5 RC2IE: EUSART2 Receive Interrupt Enable bit 1 = Enabled 0 = Disabled bit 4 TX2IE: EUSART2 Transmit Interrupt Enable bit 1 = Enabled 0 = Disabled bit 3 TMR4IE: TMR4 to PR4 Match Interrupt Enable bit 1 = Enabled 0 = Disabled bit 2 CCP5IE: CCP5 Interrupt Enable bit 1 = Enabled 0 = Disabled bit 1 CCP4IE: CCP4 Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 CCP3IE: ECCP3 Interrupt Enable bit 1 = Enabled 0 = Disabled Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared 2004 Microchip Technology Inc. Preliminary x = Bit is unknown DS39646B-page 129 PIC18F8722 FAMILY 10.4 IPR Registers The IPR registers contain the individual priority bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Priority registers (IPR1, IPR2, IPR3). Using the priority bits requires that the Interrupt Priority Enable (IPEN) bit be set. REGISTER 10-10: IPR1: PERIPHERAL INTERRUPT PRIORITY REGISTER 1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 PSPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP bit 7 bit 0 bit 7 PSPIP: Parallel Slave Port Read/Write Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 ADIP: A/D Converter Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 RC1IP: EUSART1 Receive Interrupt Priority bit 1 = High priority 0 = Low priority bit 4 TX1IP: EUSART1 Transmit Interrupt Priority bit 1 = High priority 0 = Low priority bit 3 SSP1IP: MSSP1 Interrupt Priority bit 1 = High priority 0 = Low priority bit 2 CCP1IP: ECCP1 Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 TMR2IP: TMR2 to PR2 Match Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 TMR1IP: TMR1 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority Legend: DS39646B-page 130 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared Preliminary x = Bit is unknown 2004 Microchip Technology Inc. PIC18F8722 FAMILY REGISTER 10-11: IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2 R/W-1 R/W-1 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 OSCFIP CMIP -- EEIP BCL1IP HLVDIP TMR3IP CCP2IP bit 7 bit 0 bit 7 OSCFIP: Oscillator Fail Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 CMIP: Comparator Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 Unimplemented: Read as `0' bit 4 EEIP: Interrupt Priority bit 1 = High priority 0 = Low priority bit 3 BCL1IP: MSSP1 Bus Collision Interrupt Priority bit 1 = High priority 0 = Low priority bit 2 HLVDIP: High/Low-Voltage Detect Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 TMR3IP: TMR3 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 CCP2IP: ECCP2 Interrupt Priority bit 1 = High priority 0 = Low priority Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared 2004 Microchip Technology Inc. Preliminary x = Bit is unknown DS39646B-page 131 PIC18F8722 FAMILY REGISTER 10-12: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3 R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 SSP2IP BCL2IP RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP bit 7 bit 0 bit 7 SSP2IP: MSSP2 Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 BCL2IP: MSSP2 Bus Collision Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 RC2IP: EUSART2 Receive Interrupt Priority bit 1 = High priority 0 = Low priority bit 4 TX2IP: EUSART2 Transmit Interrupt Priority bit 1 = High priority 0 = Low priority bit 3 TMR4IP: TMR4 to PR4 Match Interrupt Priority bit 1 = High priority 0 = Low priority bit 2 CCP5IP: CCP5 Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 CCP4IP: CCP4 Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 CCP3IP: ECCP3 Interrupt Priority bit 1 = High priority 0 = Low priority Legend: DS39646B-page 132 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared Preliminary x = Bit is unknown 2004 Microchip Technology Inc. PIC18F8722 FAMILY 10.5 RCON Register The RCON register contains bits used to determine the cause of the last Reset or wake-up from Idle or Sleep modes. RCON also contains the bit that enables interrupt priorities (IPEN). REGISTER 10-13: RCON: RESET CONTROL REGISTER R/W-0 R/W-1 U-0 R/W-1 R-1 R-1 R/W-0 R/W-0 IPEN SBOREN -- RI TO PD POR BOR bit 7 bit 0 bit 7 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode) bit 6 SBOREN: Software BOR Enable bit For details of bit operation and Reset state, see Register 4-1. bit 5 Unimplemented: Read as `0' bit 4 RI: RESET Instruction Flag bit For details of bit operation, see Register 4-1. bit 3 TO: Watchdog Timer Time-out Flag bit For details of bit operation, see Register 4-1. bit 2 PD: Power-Down Detection Flag bit For details of bit operation, see Register 4-1. bit 1 POR: Power-on Reset Status bit For details of bit operation, see Register 4-1. bit 0 BOR: Brown-out Reset Status bit For details of bit operation, see Register 4-1. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared 2004 Microchip Technology Inc. Preliminary x = Bit is unknown DS39646B-page 133 PIC18F8722 FAMILY 10.6 INTn Pin Interrupts 10.7 TMR0 Interrupt External interrupts on the RB0/INT0, RB1/INT1, RB2/ INT2 and RB3/INT3 pins are edge-triggered. If the corresponding INTEDGx bit in the INTCON2 register is set (= 1), the interrupt is triggered by a rising edge; if the bit is clear, the trigger is on the falling edge. When a valid edge appears on the RBx/INTx pin, the corresponding flag bit, INTxIF, is set. This interrupt can be disabled by clearing the corresponding enable bit, INTxIE. Flag bit, INTxIF, must be cleared in software in the Interrupt Service Routine before re-enabling the interrupt. In 8-bit mode (which is the default), an overflow in the TMR0 register (FFh 00h) will set flag bit, TMR0IF. In 16-bit mode, an overflow in the TMR0H:TMR0L register pair (FFFFh 0000h) will set TMR0IF. The interrupt can be enabled/disabled by setting/clearing enable bit, TMR0IE (INTCON<5>). Interrupt priority for Timer0 is determined by the value contained in the interrupt priority bit, TMR0IP (INTCON2<2>). See Section 12.0 "Timer0 Module" for further details on the Timer0 module. All external interrupts (INT0, INT1, INT2 and INT3) can wake-up the processor from the power-managed modes if bit INTxIE was set prior to going into powermanaged modes. If the Global Interrupt Enable bit, GIE, is set, the processor will branch to the interrupt vector following wake-up. 10.8 Interrupt priority for INT1, INT2 and INT3 is determined by the value contained in the interrupt priority bits, INT1IP (INTCON3<6>), INT2IP (INTCON3<7>) and INT3IP (INTCON2<1>). There is no priority bit associated with INT0. It is always a high priority interrupt source. EXAMPLE 10-1: An input change on PORTB<7:4> sets flag bit, RBIF (INTCON<0>). The interrupt can be enabled/disabled by setting/clearing enable bit, RBIE (INTCON<3>). Interrupt priority for PORTB interrupt-on-change is determined by the value contained in the interrupt priority bit, RBIP (INTCON2<0>). 10.9 Context Saving During Interrupts During interrupts, the return PC address is saved on the stack. Additionally, the WREG, STATUS and BSR registers are saved on the fast return stack. If a fast return from interrupt is not used (see Section 5.3 "Data Memory Organization"), the user may need to save the WREG, STATUS and BSR registers on entry to the Interrupt Service Routine. Depending on the user's application, other registers may also need to be saved. Example 10-1 saves and restores the WREG, STATUS and BSR registers during an Interrupt Service Routine. SAVING STATUS, WREG AND BSR REGISTERS IN RAM MOVWF W_TEMP MOVFF STATUS, STATUS_TEMP MOVFF BSR, BSR_TEMP ; ; USER ISR CODE ; MOVFF BSR_TEMP, BSR MOVF W_TEMP, W MOVFF STATUS_TEMP, STATUS DS39646B-page 134 PORTB Interrupt-on-Change ; W_TEMP is in virtual bank ; STATUS_TEMP located anywhere ; BSR_TMEP located anywhere ; Restore BSR ; Restore WREG ; Restore STATUS Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY 11.0 I/O PORTS 11.1 Depending on the device selected and features enabled, there are up to nine ports available. Some pins of the I/O ports are multiplexed with an alternate function from the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. Each port has three registers for its operation. These registers are: The Data Latch (LAT register) is useful for read-modify-write operations on the value that the I/O pins are driving. A simplified model of a generic I/O port, without the interfaces to other peripherals, is shown in Figure 11-1. GENERIC I/O PORT OPERATION RD LAT Data Bus WR LAT or Port D Q I/O pin(1) D The RA4 pin is multiplexed with the Timer0 module clock input to become the RA4/T0CKI pin. Pins RA6 and RA7 are multiplexed with the main oscillator pins; they are enabled as oscillator or I/O pins by the selection of the main oscillator in the Configuration register (see Section 25.1 "Configuration Bits" for details). When they are not used as port pins, RA6 and RA7 and their associated TRIS and LAT bits are read as `0'. The other PORTA pins are multiplexed with the analog VREF+ and VREF- inputs. The operation of pins RA5:RA0 as A/D converter inputs is selected by clearing or setting the PCFG3:PCFG0 control bits in the ADCON1 register. Note: Q CKx TRIS Latch Input Buffer RD TRIS Q D ENEN The TRISA register controls the direction of the PORTA pins, even when they are being used as analog inputs. The user must ensure the bits in the TRISA register are maintained set when using them as analog inputs. EXAMPLE 11-1: I/O pins have diode protection to VDD and VSS. CLRF MOVLW MOVWF MOVLW MOVWF 2004 Microchip Technology Inc. On a Power-on Reset, RA5 and RA3:RA0 are configured as analog inputs and read as `0'. RA4 is configured as a digital input. The RA4/T0CKI pin is a Schmitt Trigger input and an open-drain output. All other PORTA pins have TTL input levels and full CMOS output drivers. CLRF RD Port Note 1: The Data Latch register (LATA) is also memory mapped. Read-modify-write operations on the LATA register read and write the latched output value for PORTA. CKx Data Latch WR TRIS PORTA is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISA. Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i.e., put the contents of the output latch on the selected pin). Reading the PORTA register reads the status of the pins, whereas writing to it, will write to the port latch. * TRIS register (data direction register) * Port register (reads the levels on the pins of the device) * LAT register (output latch) FIGURE 11-1: PORTA, TRISA and LATA Registers Preliminary PORTA ; ; ; LATA ; ; ; 0Fh ; ADCON1 ; 0CFh ; ; ; TRISA ; ; INITIALIZING PORTA Initialize PORTA by clearing output data latches Alternate method to clear output data latches Configure A/D for digital inputs Value used to initialize data direction Set RA<3:0> as inputs RA<5:4> as outputs DS39646B-page 135 PIC18F8722 FAMILY TABLE 11-1: PORTA FUNCTIONS Pin Name Function TRIS Setting I/O I/O Type RA0 0 O DIG LATA<0> data output; not affected by analog input. 1 I TTL PORTA<0> data input; disabled when analog input enabled. AN0 1 I ANA A/D input channel 0. Default input configuration on POR; does not affect digital output. RA1 0 O DIG LATA<1> data output; not affected by analog input. 1 I TTL PORTA<1> data input; disabled when analog input enabled. AN1 1 I ANA A/D input channel 1. Default input configuration on POR; does not affect digital output. RA2 0 O DIG LATA<2> data output; not affected by analog input. 1 I TTL PORTA<2> data input. Disabled when analog functions enabled. RA0/AN0 RA1/AN1 RA2/AN2/VREF- RA3/AN3/VREF+ RA4/T0CKI RA5/AN4/HLVDIN 1 I ANA A/D input channel 2. Default input configuration on POR. 1 I ANA Comparator voltage reference low input and A/D voltage reference low input. RA3 0 O DIG LATA<3> data output; not affected by analog input. 1 I TTL PORTA<3> data input; disabled when analog input enabled. AN3 1 I ANA A/D input channel 3. Default input configuration on POR. VREF+ 1 I ANA Comparator voltage reference high input and A/D voltage reference high input. RA4 0 O DIG LATA<4> data output. 1 I ST PORTA<4> data input; default configuration on POR. T0CKI x I ST Timer0 clock input. RA5 0 O DIG LATA<5> data output; not affected by analog input. 1 I TTL PORTA<5> data input; disabled when analog input enabled. AN4 1 I ANA A/D input channel 4. Default configuration on POR. 1 I ANA High/Low-Voltage Detect external trip point input. OSC2 x O ANA Main oscillator feedback output connection (XT, HS, HSPLL and LP modes). CLKO x O DIG System cycle clock output (FOSC/4) in all oscillator modes except RC, INTIO7 and EC. RA6 0 O DIG LATA<6> data output. Enabled in RCIO, INTIO2 and ECIO modes only. 1 I TTL PORTA<6> data input. Enabled in RCIO, INTIO2 and ECIO modes only. x I ANA Main oscillator input connection. OSC1/CLKI/RA7 OSC1 CLKI x I ANA Main clock input connection. RA7 0 O DIG LATA<7> data output. Disabled in external oscillator modes. 1 I TTL PORTA<7> data input. Disabled in external oscillator modes. PWR = Power Supply, O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST= Schmitt Buffer Input, TTL = TTL Buffer Input, x = Don't care (TRIS bit does not affect port direction or is overridden for this option). TABLE 11-2: Name AN2 VREF- HLVDIN OSC2/CLKO/RA6 Legend: Description SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Bit 6 RA7(1) RA6(1) RA5 RA4 RA3 RA2 RA1 RA0 61 LATA LATA7(1) LATA6(1) LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 60 TRISA TRISA7(1) TRISA6(1) TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 60 VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 59 PORTA ADCON1 -- -- Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page Bit 7 Legend: -- = unimplemented, read as `0'. Shaded cells are not used by PORTA. Note 1: RA7:RA6 and their associated latch and data direction bits are enabled as I/O pins based on oscillator configuration; otherwise, they are read as `0'. DS39646B-page 136 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY 11.2 PORTB, TRISB and LATB Registers PORTB is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISB. Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i.e., put the contents of the output latch on the selected pin). The Data Latch register (LATB) is also memory mapped. Read-modify-write operations on the LATB register read and write the latched output value for PORTB. EXAMPLE 11-2: CLRF PORTB CLRF LATB MOVLW 0CFh MOVWF TRISB Four of the PORTB pins (RB7:RB4) have an interrupt-on-change feature. Only pins configured as inputs can cause this interrupt to occur (i.e., any RB7:RB4 pin configured as an output is excluded from the interrupt-on-change comparison). The input pins (of RB7:RB4) are compared with the old value latched on the last read of PORTB. The "mismatch" outputs of RB7:RB4 are ORed together to generate the RB Port Change Interrupt with Flag bit, RBIF (INTCON<0>). This interrupt can wake the device from power-managed modes. The user, in the Interrupt Service Routine, can clear the interrupt in the following manner: a) INITIALIZING PORTB ; ; ; ; ; ; ; ; ; ; ; ; Initialize PORTB by clearing output data latches Alternate method to clear output data latches Value used to initialize data direction Set RB<3:0> as inputs RB<5:4> as outputs RB<7:6> as inputs b) A mismatch condition will continue to set flag bit RBIF. Reading PORTB will end the mismatch condition and allow flag bit RBIF to be cleared. The interrupt-on-change feature is recommended for wake-up on key depression operation and operations where PORTB is only used for the interrupt-on-change feature. Polling of PORTB is not recommended while using the interrupt-on-change feature. Each of the PORTB pins has a weak internal pull-up. A single control bit can turn on all the pull-ups. This is performed by clearing bit RBPU (INTCON2<7>). The weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on a Power-on Reset. 2004 Microchip Technology Inc. Any read or write of PORTB (except with the MOVSF, MOVSS, MOVFF (ANY), PORTB instruction). This will end the mismatch condition. Clear flag bit RBIF. For 80-pin devices, RB3 can be configured as the alternate peripheral pin for the ECCP2 module by clearing the CCP2MX configuration bit. This applies only when the device is in one of the operating modes other than the default Microcontroller mode. If the device is in Microcontroller mode, the alternate assignment for ECCP2 is RE7. As with other ECCP2 configurations, the user must ensure that the TRISB<3> bit is set appropriately for the intended operation. Preliminary DS39646B-page 137 PIC18F8722 FAMILY TABLE 11-3: PORTB FUNCTIONS Pin Name Function TRIS Setting I/O RB0/INT0/FLT0 RB0 0 O DIG 1 I TTL PORTB<0> data input; weak pull-up when RBPU bit is cleared. INT0 1 I ST External interrupt 0 input. FLT0 1 I ST ECCPx PWM Fault input, enabled in software. RB1 0 O DIG LATB<1> data output. 1 I TTL PORTB<1> data input; weak pull-up when RBPU bit is cleared. RB1/INT1 RB2/INT2 RB3/INT3/ ECCP2/P2A INT1 1 I ST External interrupt 1 input. RB2 0 O DIG LATB<2> data output. 1 I TTL PORTB<2> data input; weak pull-up when RBPU bit is cleared. INT2 1 I ST External interrupt 2 input. RB3 0 O DIG LATB<3> data output. 1 I TTL PORTB<3> data input; weak pull-up when RBPU bit is cleared and capture input is disabled. 1 I ST External interrupt 3 input. 0 O DIG ECCP2 compare output and ECCP2 PWM output. Takes priority over port data. 1 I ST ECCP2 capture input. P2A(1) 0 O DIG ECCP2 Enhanced PWM output, channel A. May be configured for tri-state during Enhanced PWM shutdown events. Takes priority over port data. RB4 0 O DIG LATB<4> data output. 1 I TTL PORTB<4> data input; weak pull-up when RBPU bit is cleared. KBI0 1 I TTL Interrupt-on-pin change. RB5 0 O DIG LATB<5> data output 1 I TTL PORTB<5> data input; weak pull-up when RBPU bit is cleared. KBI1 1 I TTL Interrupt-on-pin change. PGM x I ST Single-Supply Programming mode entry (ICSP). Enabled by LVP configuration bit; all other pin functions disabled. RB6 0 O DIG LATB<6> data output. RB6/KBI2/PGC RB7/KBI3/PGD 2: LATB<0> data output. INT3 RB5/KBI1/PGM Note 1: Description ECCP2(1) RB4/KBI0 Legend: I/O Type 1 I TTL PORTB<6> data input; weak pull-up when RBPU bit is cleared. KBI2 1 I TTL Interrupt-on-pin change. PGC x I ST Serial execution (ICSPTM) clock input for ICSP and ICD operation(2). RB7 0 O DIG LATB<7> data output. 1 I TTL PORTB<7> data input; weak pull-up when RBPU bit is cleared. KBI3 1 I TTL Interrupt-on-pin change. PGD x O DIG Serial execution data output for ICSP and ICD operation(2). x I ST Serial execution data input for ICSP and ICD operation(2). PWR = Power Supply, O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input, x = Don't care (TRIS bit does not affect port direction or is overridden for this option). Alternate assignment for ECCP2 when the CCP2MX configuration bit is cleared (Microprocessor, Extended Microcontroller and Microcontroller with Boot Block modes, 80-pin devices only). Default assignment is RC1. All other pin functions are disabled when ICSP or ICD operations are enabled. DS39646B-page 138 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY TABLE 11-4: Name PORTB SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 60 LATB LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 60 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 60 TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 57 INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INT3IP RBIP 57 INT2IF INT1IF 57 INTCON GIE/GIEH PEIE/GIEL INTCON2 RBPU INTCON3 INT2IP INT1IP INT3IE INT2IE INT1IE INT3IF Legend: Shaded cells are not used by PORTB. 2004 Microchip Technology Inc. Preliminary DS39646B-page 139 PIC18F8722 FAMILY 11.3 PORTC, TRISC and LATC Registers Note: PORTC is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISC. Setting a TRISC bit (= 1) will make the corresponding PORTC pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISC bit (= 0) will make the corresponding PORTC pin an output (i.e., put the contents of the output latch on the selected pin). The Data Latch register (LATC) is also memory mapped. Read-modify-write operations on the LATC register read and write the latched output value for PORTC. PORTC is multiplexed with several peripheral functions. All port pins have Schmitt Trigger input buffers. RC1 is normally configured by configuration bit CCP2MX as the default peripheral pin of the ECCP2 module (default/erased state, CCP2MX = 1). On a Power-on Reset, these pins are configured as digital inputs. The contents of the TRISC register are affected by peripheral overrides. Reading TRISC always returns the current contents, even though a peripheral device may be overriding one or more of the pins. EXAMPLE 11-3: CLRF PORTC CLRF LATC MOVLW 0CFh MOVWF TRISC INITIALIZING PORTC ; ; ; ; ; ; ; ; ; ; ; ; Initialize PORTC by clearing output data latches Alternate method to clear output data latches Value used to initialize data direction Set RC<3:0> as inputs RC<5:4> as outputs RC<7:6> as inputs When enabling peripheral functions, care should be taken in defining TRIS bits for each PORTC pin. Some peripherals override the TRIS bit to make a pin an output, while other peripherals override the TRIS bit to make a pin an input. The user should refer to the corresponding peripheral section for the correct TRIS bit settings. DS39646B-page 140 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY TABLE 11-5: PORTC FUNCTIONS Pin Name Function RC0/T1OSO/T13CKI RC0 RC1/T1OSI/ ECCP2/P2A DIG LATC<0> data output. I ST PORTC<0> data input. T1OSO x O ANA T13CKI 1 I ST Timer1/Timer3 counter input. RC1 0 O DIG LATC<1> data output. 1 I ST x I ANA Timer1 oscillator input; enabled when Timer1 oscillator enabled. Disables digital I/O. ECCP2(1) 0 O DIG ECCP2 compare output and ECCP2 PWM output. Takes priority over port data. 1 I ST ECCP2 capture input. 0 O DIG ECCP2 Enhanced PWM output, channel A. May be configured for tri-state during Enhanced PWM shutdown events. Takes priority over port data. 0 O DIG LATC<2> data output. 1 I ST PORTC<2> data input. ECCP1 0 O DIG ECCP1 compare output and ECCP1 PWM output. Takes priority over port data. 1 I ST ECCP1 capture input. P1A 0 O DIG ECCP1 Enhanced PWM output, channel A. May be configured for tri-state during Enhanced PWM shutdown events. Takes priority over port data. RC3 0 O DIG LATC<3> data output. 1 I ST PORTC<3> data input. 0 O DIG SPITM clock output (MSSP1 module). Takes priority over port data. 1 I ST SPI clock input (MSSP1 module). 0 O DIG I2CTM clock output (MSSP1 module). Takes priority over port data. 1 I I2C/SMB 0 O DIG LATC<4> data output. 1 I ST PORTC<4> data input. RC2 RC4 Note 1: PORTC<1> data input. I2C clock input (MSSP1 module); input type depends on module setting. SDI1 1 I ST SPI data input (MSSP1 module). SDA1 1 O DIG I2C data output (MSSP1 module). Takes priority over port data. 1 I 0 O DIG LATC<5> data output. 1 I ST PORTC<5> data input. 0 O DIG SPI data output (MSSP1 module). Takes priority over port data. RC5 SDO1 Legend: Timer1 oscillator output; enabled when Timer1 oscillator enabled. Disables digital I/O. T1OSI SCL1 RC5/SDO1 Description O SCK1 RC4/SDI1/SDA1 I/O Type 0 P2A RC3/SCK1/SCL1 I/O 1 (1) RC2/ECCP1/P1A TRIS Setting I2C/SMB I2C data input (MSSP1 module); input type depends on module setting. DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output; I2C/SMB = I2C/SMBus input buffer; x = Don't care (TRIS bit does not affect port direction or is overridden for this option). Default assignment for ECCP2 when CCP2MX configuration bit is set. 2004 Microchip Technology Inc. Preliminary DS39646B-page 141 PIC18F8722 FAMILY TABLE 11-5: PORTC FUNCTIONS (CONTINUED) Pin Name RC6/TX1/CK1 RC7/RX1/DT1 Legend: Note 1: PORTC TRIS Setting I/O I/O Type RC6 0 O DIG LATC<6> data output. 1 I ST PORTC<6> data input. TX1 0 O DIG Asynchronous serial transmit data output (EUSART1 module). Takes priority over port data. CK1 0 O DIG Synchronous serial clock output (EUSART1 module). Takes priority over port data. Synchronous serial clock input (EUSART1 module). Description 1 I ST 0 O DIG LATC<7> data output. 1 I ST PORTC<7> data input. RX1 1 I ST Asynchronous serial receive data input (EUSART1 module) DT1 1 O DIG Synchronous serial data output (EUSART1 module). Takes priority over port data. User must configure as input. 1 I ST Synchronous serial data input (EUSART1 module). User must configure as an input. RC7 DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output; I2C/SMB = I2C/SMBus input buffer; x = Don't care (TRIS bit does not affect port direction or is overridden for this option). Default assignment for ECCP2 when CCP2MX configuration bit is set. TABLE 11-6: Name Function SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 60 LATC LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 60 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 60 DS39646B-page 142 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY 11.4 PORTD, TRISD and LATD Registers PORTD is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISD. Setting a TRISD bit (= 1) will make the corresponding PORTD pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISD bit (= 0) will make the corresponding PORTD pin an output (i.e., put the contents of the output latch on the selected pin). The Data Latch register (LATD) is also memory mapped. Read-modify-write operations on the LATD register read and write the latched output value for PORTD. All pins on PORTD are implemented with Schmitt Trigger input buffers. Each pin is individually configurable as an input or output. Note: On a Power-on Reset, these pins are configured as digital inputs. PORTD can also be configured to function as an 8-bit wide parallel microprocessor port by setting the PSPMODE control bit (PSPCON<4>). In this mode, parallel port data takes priority over other digital I/O (but not the external memory interface). When the parallel port is active, the input buffers are TTL. For more information, refer to Section 11.10 "Parallel Slave Port". EXAMPLE 11-4: CLRF PORTD CLRF LATD MOVLW 0CFh MOVWF TRISD INITIALIZING PORTD ; ; ; ; ; ; ; ; ; ; ; ; Initialize PORTD by clearing output data latches Alternate method to clear output data latches Value used to initialize data direction Set RD<3:0> as inputs RD<5:4> as outputs RD<7:6> as inputs In 80-pin devices, PORTD is multiplexed with the system bus as part of the external memory interface. I/O port and other functions are only available when the interface is disabled by setting the EBDIS bit (MEMCON<7>). When the interface is enabled, PORTD is the low-order byte of the multiplexed address/data bus (AD7:AD0). The TRISD bits are also overridden. 2004 Microchip Technology Inc. Preliminary DS39646B-page 143 PIC18F8722 FAMILY TABLE 11-7: PORTD FUNCTIONS Pin Name Function TRIS Setting I/O I/O Type RD0/AD0/PSP0 RD0 0 O DIG LATD<0> data output. 1 I ST PORTD<0> data input. x O DIG External memory interface, address/data bit 0 output. Takes priority over PSP and port data. x I TTL External memory interface, data bit 0 input. x O DIG PSP read data output (LATD<0>). Takes priority over port data. x I TTL PSP write data input. 0 O DIG LATD<1> data output. 1 I ST PORTD<1> data input. x O DIG External memory interface, address/data bit 1 output. Takes priority over PSP and port data. x I TTL External memory interface, data bit 1 input. x O DIG PSP read data output (LATD<1>). Takes priority over port data. x I TTL PSP write data input. 0 O DIG LATD<2> data output. 1 I ST PORTD<2> data input. x O DIG External memory interface, address/data bit 2 output. Takes priority over PSP and port data. x I TTL External memory interface, data bit 2 input. x O DIG PSP read data output (LATD<2>). Takes priority over port data. x I TTL PSP write data input. 0 O DIG LATD<3> data output. 1 I ST PORTD<3> data input. x O DIG External memory interface, address/data bit 3 output. Takes priority over PSP and port data. x I TTL External memory interface, data bit 3 input. x O DIG PSP read data output (LATD<3>). Takes priority over port data. x I TTL PSP write data input. 0 O DIG LATD<4> data output. 1 I ST PORTD<4> data input. x O DIG External memory interface, address/data bit 4 output. Takes priority over PSP, MSSP and port data. x I TTL External memory interface, data bit 4 input. x O DIG PSP read data output (LATD<4>). Takes priority over port and PSP data. x I TTL PSP write data input. 0 O DIG SPITM data output (MSSP2 module). Takes priority over PSP and port data. AD0(1) PSP0 RD1/AD1/PSP1 RD1 AD1(1) PSP1 RD2/AD2/PSP2 RD2 AD2(1) PSP2 RD3/AD3/PSP3 RD3 AD3(1) PSP3 RD4/AD4/ PSP4/SDO2 RD4 AD4(1) PSP4 SDO2 Legend: Note 1: Description PWR = Power Supply, O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input, x = Don't care (TRIS bit does not affect port direction or is overridden for this option). Implemented on 80-pin devices only. DS39646B-page 144 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY TABLE 11-7: Pin Name RD5/AD5/ PSP5/SDI2 /SDA2 PORTD FUNCTIONS (CONTINUED) Function TRIS Setting I/O I/O Type RD5 0 O DIG LATD<5> data output. 1 I ST PORTD<5> data input. x O DIG External memory interface, address/data bit 5 output. Takes priority over PSP, MSSP and port data. x I TTL External memory interface, data bit 5 input. x O DIG PSP read data output (LATD<5>). Takes priority over port data. PSP write data input. AD5(1) PSP5 RD6/AD6/ PSP6/SCK2/ SCL2 x I TTL SDI2 1 I ST SPITM data input (MSSP2 module). SDA2 1 O DIG I2CTM data output (MSSP2 module). Takes priority over PSP and port data. 1 I 0 O DIG LATD<6> data output. 1 I ST PORTD<6> data input. x O DIG-3 x I TTL x O DIG PSP read data output (LATD<6>). Takes priority over port data. x I TTL PSP write data input. 0 O DIG SPI clock output (MSSP2 module). Takes priority over PSP and port data. 1 I ST SPI clock input (MSSP2 module). 0 O DIG I2C clock output (MSSP2 module). Takes priority over PSP and port data. 1 I 0 O DIG LATD<7> data output. 1 I ST PORTD<7> data input. x O DIG External memory interface, address/data bit 7 output. Takes priority over PSP and port data. x I TTL External memory interface, data bit 7 input. x O DIG PSP read data output (LATD<7>). Takes priority over port data. x I TTL PSP write data input. 1 I TTL Slave select input for SSP (MSSP2 module). RD6 AD6(1) PSP6 SCK2 SCL2 RD7 RD7/AD7/ PSP7/SS2 AD7(1) PSP7 SS2 Legend: Note 1: PORTD I2C/SMB I2C data input (MSSP2 module); input type depends on module setting. External memory interface, address/data bit 6 output. Takes priority over PSP, MSSP and port data. External memory interface, data bit 6 input. I2C/SMB I2C clock input (MSSP2 module); input type depends on module setting. PWR = Power Supply, O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input, x = Don't care (TRIS bit does not affect port direction or is overridden for this option). Implemented on 80-pin devices only. TABLE 11-8: Name Description SUMMARY OF REGISTERS ASSOCIATED WITH PORTD Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 60 LATD LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 60 TRISD TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 60 2004 Microchip Technology Inc. Preliminary DS39646B-page 145 PIC18F8722 FAMILY 11.5 PORTE, TRISE and LATE Registers PORTE is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISE. Setting a TRISE bit (= 1) will make the corresponding PORTE pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISE bit (= 0) will make the corresponding PORTE pin an output (i.e., put the contents of the output latch on the selected pin). The Data Latch register (LATE) is also memory mapped. Read-modify-write operations on the LATE register read and write the latched output value for PORTE. All pins on PORTE are implemented with Schmitt Trigger input buffers. Each pin is individually configurable as an input or output. Note: On a Power-on Reset, these pins are configured as digital inputs. When the Parallel Slave Port is active on PORTD, three of the PORTE pins (RE0/AD8/RD/P2D, RE1/AD9/WR/P2C and RE2/AD10/CS/P2B) are configured as digital control inputs for the port. The control functions are summarized in Table 11-9. The reconfiguration occurs automatically when the PSPMODE control bit (PSPCON<4>) is set. Users must still make certain the the corresponding TRISE bits are set to configure these pins as digital inputs. EXAMPLE 11-5: CLRF PORTE CLRF LATE MOVLW 03h MOVWF TRISE INITIALIZING PORTE ; ; ; ; ; ; ; ; ; ; ; Initialize PORTE by clearing output data latches Alternate method to clear output data latches Value used to initialize data direction Set RE<1:0> as inputs RE<7:2> as outputs When the device is operating in Microcontroller mode, pin RE7 can be configured as the alternate peripheral pin for the ECCP2 module. This is done by clearing the CCP2MX configuration bit. In 80-pin devices, PORTE is multiplexed with the system bus as part of the external memory interface. I/O port and other functions are only available when the interface is disabled by setting the EBDIS bit (MEMCON<7>). When the interface is enabled (80-pin devices only), PORTE is the high-order byte of the multiplexed address/data bus (AD15:AD8). The TRISE bits are also overridden. DS39646B-page 146 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY TABLE 11-9: Pin Name RE0/AD8/ RD/P2D PORTE FUNCTIONS Function TRIS Setting I/O I/O Type RE0 0 O DIG LATE<0> data output. AD8(2) RE1/AD9/ WR/P2C External memory interface, address/data bit 8 output. Takes priority over ECCP and port data. External memory interface, data bit 8 input. TTL I TTL Parallel Slave Port read enable control input. P2D 0 O DIG ECCP2 Enhanced PWM output, channel D. May be configured for tri-state during Enhanced PWM shutdown events. Takes priority over port data. RE1 0 O DIG LATE<1> data output. 1 I ST PORTE<1> data input. x O DIG External memory interface, address/data bit 9 output. Takes priority over ECCP and port data. x I TTL External memory interface, data bit 9 input. WR 1 I TTL Parallel Slave Port write enable control input. P2C 0 O DIG ECCP2 Enhanced PWM output, channel C. May be configured for tri-state during Enhanced PWM shutdown events. Takes priority over port data. RE2 0 O DIG LATE<2> data output. 1 I ST PORTE<2> data input. x O DIG External memory interface, address/data bit 10 output. Takes priority over ECCP and port data. x I TTL External memory interface, data bit 10 input. CS 1 I TTL Parallel Slave Port chip select control input. P2B 0 O DIG ECCP2 Enhanced PWM output, channel B. May be configured for tri-state during Enhanced PWM shutdown events. Takes priority over port data. RE3 0 O DIG LATE<3> data output. 1 I ST PORTE<3> data input. x O DIG External memory interface, address/data bit 11 output. Takes priority over ECCP and port data. x I TTL External memory interface, data bit 11 input. P3C 0 O DIG ECCP3 Enhanced PWM output, channel C. May be configured for tri-state during Enhanced PWM shutdown events. Takes priority over port data. RE4 0 O DIG LATE<4> data output. 1 I ST PORTE<4> data input. x O DIG External memory interface, address/data bit 12 output. Takes priority over ECCP and port data. P3B Note 1: 2: PORTE<0> data input. DIG I AD12(2) Legend: ST O 1 AD11(2) RE4/AD12/P3B I x x AD10(2) RE3/AD11/P3C 1 RD AD9(2) RE2/AD10/ CS/P2B Description x I TTL External memory interface, data bit 12 input. 0 O DIG ECCP3 Enhanced PWM output, channel B. May be configured for tri-state during Enhanced PWM shutdown events. Takes priority over port data. PWR = Power Supply, O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input, x = Don't care (TRIS bit does not affect port direction or is overridden for this option). Alternate assignment for ECCP2 when CCP2MX configuration bit is cleared (all devices in Microcontroller mode). Implemented on 80-pin devices only. 2004 Microchip Technology Inc. Preliminary DS39646B-page 147 PIC18F8722 FAMILY TABLE 11-9: Pin Name PORTE FUNCTIONS (CONTINUED) Function TRIS Setting I/O I/O Type RE5 0 O DIG LATE<5> data output. RE5/AD13/P1C AD13(2) RE6/AD14/P1B ST PORTE<5> data input. O DIG External memory interface, address/data bit 13 output. Takes priority over ECCP and port data. I TTL External memory interface, data bit 13 input. 0 O DIG ECCP1 Enhanced PWM output, channel C. May be configured for tri-state during Enhanced PWM shutdown events. Takes priority over port data. RE6 0 O DIG LATE<6> data output. 1 I ST PORTE<6> data input. x O DIG External memory interface, address/data bit 14 output. Takes priority over ECCP and port data. x I TTL External memory interface, data bit 14 input. P1B 0 O DIG ECCP1 Enhanced PWM output, channel B. May be configured for tri-state during Enhanced PWM shutdown events. Takes priority over port data. RE7 0 O DIG LATE<7> data output. 1 I ST PORTE<7> data input. x O DIG External memory interface, address/data bit 15 output. Takes priority over ECCP and port data. x I TTL External memory interface, data bit 15 input. 0 O DIG ECCP2 compare output and ECCP2 PWM output. Takes priority over port data. ECCP2(1) P2A(1) Note 1: 2: I x x AD15(2) Legend: 1 P1C AD14(2) RE7/AD15/ ECCP2/P2A Description 1 I ST ECCP2 capture input. 0 O DIG ECCP2 Enhanced PWM output, channel A. Takes priority over port and data. May be configured for tri-state during Enhanced PWM shutdown events. PWR = Power Supply, O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input, x = Don't care (TRIS bit does not affect port direction or is overridden for this option). Alternate assignment for ECCP2 when CCP2MX configuration bit is cleared (all devices in Microcontroller mode). Implemented on 80-pin devices only. TABLE 11-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE Name PORTE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page RE7 RE6 RE5 RE4 RE3 RE2 RE1 RE0 60 LATE LATE7 LATE6 LATE5 LATE4 LATE3 LATE2 LATE1 LATE0 60 TRISE TRISE7 TRISE6 TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 TRISE0 60 DS39646B-page 148 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY 11.6 PORTF, LATF and TRISF Registers PORTF is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISF. Setting a TRISF bit (= 1) will make the corresponding PORTF pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISF bit (= 0) will make the corresponding PORTF pin an output (i.e., put the contents of the output latch on the selected pin). The Data Latch register (LATF) is also memory mapped. Read-modify-write operations on the LATF register read and write the latched output value for PORTF. All pins on PORTF are implemented with Schmitt Trigger input buffers. Each pin is individually configurable as an input or output. PORTF is multiplexed with several analog peripheral functions, including the A/D converter and comparator inputs, as well as the comparator outputs. Pins RF1 through RF2 may be used as comparator inputs or outputs by setting the appropriate bits in the CMCON register. To use RF0:RF6 as digital inputs, it is necessary to turn off the A/D inputs. 2004 Microchip Technology Inc. Note 1: On a Power-on Reset, the RF6:RF0 pins are configured as analog inputs and read as `0'. 2: To configure PORTF as digital I/O, set the ADCON1 register. EXAMPLE 11-6: CLRF CLRF MOVLW MOVWF MOVLW MOVWF Preliminary PORTF ; ; ; LATF ; ; ; 0x0F ; ADCON1 ; 0xCF ; ; ; TRISF ; ; ; INITIALIZING PORTF Initialize PORTF by clearing output data latches Alternate method to clear output data latches Set PORTF as digital I/O Value used to initialize data direction Set RF3:RF0 as inputs RF5:RF4 as outputs RF7:RF6 as inputs DS39646B-page 149 PIC18F8722 FAMILY TABLE 11-11: PORTF FUNCTIONS Pin Name Function TRIS Setting I/O I/O Type RF0 0 O DIG 1 I ST AN5 1 I ANA A/D input channel 5. Default configuration on POR. RF1 0 O DIG LATF<1> data output; not affected by analog input. RF0/AN5 RF1/AN6/C2OUT LATF<0> data output; not affected by analog input. PORTF<0> data input; disabled when analog input enabled. 1 I ST 1 I ANA A/D input channel 6. Default configuration on POR. C2OUT 0 O DIG Comparator 2 output; takes priority over port data. RF2 0 O DIG LATF<2> data output; not affected by analog input. AN6 RF2/AN7/C1OUT PORTF<1> data input; disabled when analog input enabled. 1 I ST 1 I ANA C1OUT 0 O TTL Comparator 1 output; takes priority over port data. RF3 0 O DIG LATF<3> data output; not affected by analog input. AN7 RF3/AN8 AN8 RF4/AN9 RF4 PORTF<2> data input; disabled when analog input enabled. A/D input channel 7. Default configuration on POR. 1 I ST PORTF<3> data input; disabled when analog input enabled. 1 I ANA A/D input channel 8 and Comparator C2+ input. Default input configuration on POR; not affected by analog output. LATF<4> data output; not affected by analog input. 0 O DIG 1 I ST PORTF<4> data input; disabled when analog input enabled. AN9 1 I ANA A/D input channel 9 and Comparator C2- input. Default input configuration on POR; does not affect digital output. RF5 0 O DIG LATF<5> data output; not affected by analog input. Disabled when CVREF output enabled. 1 I ST PORTF<5> data input; disabled when analog input enabled. Disabled when CVREF output enabled. AN10 1 I ANA A/D input channel 10 and Comparator C1+ input. Default input configuration on POR; not affected by analog output. CVREF x O ANA Comparator voltage reference output. Enabling this feature disables digital I/O. RF6 0 O DIG LATF<6> data output; not affected by analog input. 1 I ST AN11 1 I ANA A/D input channel 11 and Comparator C1- input. Default input configuration on POR; does not affect digital output. RF7 0 O DIG LATF<7> data output. 1 I ST PORTF<7> data input. SS1 1 I TTL Slave select input for SSP (MSSP1 module). RF5/AN10/CVREF RF6/AN11 RF7/SS1 Legend: Description PORTF<6> data input; disabled when analog input enabled. PWR = Power Supply, O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input, x = Don't care (TRIS bit does not affect port direction or is overridden for this option). TABLE 11-12: SUMMARY OF REGISTERS ASSOCIATED WITH PORTF Name TRISF PORTF LATF Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0 60 RF7 RF6 RF5 RF4 RF3 RF2 RF1 RF0 60 LATF7 LATF6 LATF5 LATF4 LATF3 LATF2 LATF1 LATF0 60 ADCON1 -- -- VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 59 CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 59 Legend: -- = unimplemented, read as `0'. Shaded cells are not used by PORTF. DS39646B-page 150 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY 11.7 PORTG, TRISG and LATG Registers PORTG is a 6-bit wide, bidirectional port. The corresponding data direction register is TRISG. Setting a TRISG bit (= 1) will make the corresponding PORTG pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISG bit (= 0) will make the corresponding PORTG pin an output (i.e., put the contents of the output latch on the selected pin). The Data Latch register (LATG) is also memory mapped. Read-modify-write operations on the LATG register, read and write the latched output value for PORTG. PORTG is multiplexed with EUSART and CCP functions (Table 11-13). PORTG pins have Schmitt Trigger input buffers. When enabling peripheral functions, care should be taken in defining TRIS bits for each PORTG pin. Some peripherals override the TRIS bit to make a pin an output, while other peripherals override the TRIS bit to make a pin an input. The user should refer to the corresponding peripheral section for the correct TRIS bit settings. The pin override value is not loaded into the TRIS register. This allows read-modify-write of the TRIS register without concern due to peripheral overrides. 2004 Microchip Technology Inc. The sixth pin of PORTG (RG5/MCLR/VPP) is an input only pin. Its operation is controlled by the MCLRE configuration bit. When selected as a port pin (MCLRE = 0), it functions as a digital input only pin; as such, it does not have TRIS or LAT bits associated with its operation. Otherwise, it functions as the device's Master Clear input. In either configuration, RG5 also functions as the programming voltage input during programming. Note: On a Power-on Reset, RG5 is enabled as a digital input only if Master Clear functionality is disabled. All other 5 pins are configured as digital inputs. EXAMPLE 11-7: CLRF PORTG CLRF LATG MOVLW 0x04 MOVWF TRISG Preliminary INITIALIZING PORTG ; ; ; ; ; ; ; ; ; ; ; ; Initialize PORTG by clearing output data latches Alternate method to clear output data latches Value used to initialize data direction Set RG1:RG0 as outputs RG2 as input RG4:RG3 as inputs DS39646B-page 151 PIC18F8722 FAMILY TABLE 11-13: PORTG FUNCTIONS Pin Name Function TRIS Setting I/O I/O Type RG0/ECCP3/P3A RG0 0 O DIG 1 I ST PORTG<0> data input. 0 O DIG ECCP3 compare and ECCP3 PWM output. Takes priority over port data. ECCP3 RG1/TX2/CK2 RG2/RX2/DT2 RG3/CCP4/P3D 1 I ST ECCP3 capture input. 0 O DIG ECCP3 Enhanced PWM output, channel B. May be configured for tri-state during Enhanced PWM shutdown events. Takes priority over port data. RG1 0 O DIG LATG<1> data output. 1 I ST PORTG<1> data input. TX2 0 O DIG Asynchronous serial transmit data output (EUSART2 module). Takes priority over port data. CK2 0 O DIG Synchronous serial clock output (EUSART2 module). Takes priority over port data. 1 I ST Synchronous serial clock input (EUSART2 module). 0 O DIG LATG<2> data output. 1 I ST PORTG<2> data input. RX2 1 I ST Asynchronous serial receive data input (EUSART2 module). DT2 1 O DIG Synchronous serial data output (EUSART2 module). Takes priority over port data. User must configure as an input. 1 I ST Synchronous serial data input (EUSART2 module). User must configure as an input. 0 O DIG LATG<3> data output. 1 I ST PORTG<3> data input. 0 O DIG CCP4 compare and PWM output; takes priority over port data and P3D function. RG2 RG3 1 I ST CCP4 capture input. P3D 0 O DIG ECCP3 Enhanced PWM output, channel D. May be configured for tri-state during Enhanced PWM shutdown events. Takes priority over port data. RG4 0 O DIG LATG<4> data output. 1 I ST PORTG<4> data input. 0 O DIG CCP5 compare and PWM output. Takes priority over port data and P1D function. CCP5 RG5/MCLR/VPP Legend: Note 1: LATG<0> data output. P3A CCP4 RG4/CCP5/P1D Description 1 I ST CCP5 capture input. P1D 0 O DIG ECCP1 Enhanced PWM output, channel B. May be configured for tri-state during Enhanced PWM shutdown events. Takes priority over port data. RG5 --(1) I ST PORTG<5> data input; enabled when MCLRE configuration bit is clear. MCLR -- I ST External Master Clear input; enabled when MCLRE configuration bit is set. VPP -- I ANA High-voltage detection; used for ICSPTM mode entry detection. Always available regardless of pin mode. PWR = Power Supply, O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input, x = Don't care (TRIS bit does not affect port direction or is overridden for this option). RG5 does not have a corresponding TRISG bit. DS39646B-page 152 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY TABLE 11-14: SUMMARY OF REGISTERS ASSOCIATED WITH PORTG Name Bit 4 Bit 3 Bit 2 Bit 0 Reset Values on page RG1 RG0 60 LATG1 LATG0 60 TRISG0 60 Bit 7 Bit 6 Bit 5 Bit 1 PORTG -- -- RG5(1) RG4 RG3 RG2 LATG -- -- LATG5(1) LATG4 LATG3 LATG2 TRISG -- -- -- TRISG4 TRISG3 TRISG2 TRISG1 Legend: -- = unimplemented, read as `0'. Shaded cells are not used by PORTG. Note 1: RG5 and LATG5 are only available when MCLR is disabled (MCLRE configuration bit = 0; otherwise, RG5 and LATG5 read as `0'. 2004 Microchip Technology Inc. Preliminary DS39646B-page 153 PIC18F8722 FAMILY 11.8 Note: PORTH, LATH and TRISH Registers PORTH is available only on PIC18F8527/8622/8627/8722 devices. PORTH is an 8-bit wide, bidirectional I/O port. The corresponding data direction register is TRISH. Setting a TRISH bit (= 1) will make the corresponding PORTH pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISH bit (= 0) will make the corresponding PORTH pin an output (i.e., put the contents of the output latch on the selected pin). The Data Latch register (LATH) is also memory mapped. Read-modify-write operations on the LATH register, read and write the latched output value for PORTH. When the external memory interface is enabled, four of the PORTH pins function as the high-order address lines for the interface. The address output from the interface takes priority over other digital I/O. The corresponding TRISH bits are also overridden. EXAMPLE 11-8: CLRF PORTH CLRF LATH MOVLW 0CFh MOVWF TRISH INITIALIZING PORTH ; ; ; ; ; ; ; ; ; ; ; ; Initialize PORTH by clearing output data latches Alternate method to clear output data latches Value used to initialize data direction Set RH3:RH0 as inputs RH5:RH4 as outputs RH7:RH6 as inputs All pins on PORTH are implemented with Schmitt Trigger input buffers. Each pin is individually configurable as an input or output. Note: On a Power-on Reset, these pins are configured as digital inputs. DS39646B-page 154 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY TABLE 11-15: PORTH FUNCTIONS Pin Name RH0/A16 RH1/A17 RH2/A18 RH3/A19 RH4/AN12/ P3C RH5/AN13/ P3B RH6/AN14/ P1C RH7/AN15/ P1B Legend: Note 1: Function TRIS Setting I/O I/O Type RH0 0 O DIG LATH<0> data output. 1 I ST PORTH<0> data input. A16 x O DIG External memory interface, address line 16. Takes priority over port data. RH1 0 O DIG LATH<1> data output. PORTH<1> data input. Description 1 I ST A17 x O DIG External memory interface, address line 17. Takes priority over port data. RH2 0 O DIG LATH<2> data output. 1 I ST PORTH<2> data input. A18 x O DIG External memory interface, address line 18. Takes priority over port data. RH3 0 O DIG LATH<3> data output. 1 I ST PORTH<3> data input. A19 x O DIG External memory interface, address line 19. Takes priority over port data. RH4 0 O DIG LATH<4> data output. 1 I ST PORTH<4> data input. AN12 1 I ANA A/D input channel 12. Default configuration on POR. P3C(1) 0 O DIG ECCP3 Enhanced PWM output, channel C. May be configured for tri-state during Enhanced PWM shutdown events. Takes priority over port data. RH5 0 O DIG LATH<5> data output. 1 I ST PORTH<5> data input. AN13 1 I ANA A/D input channel 13. Default configuration on POR. P3B(1) 0 O DIG ECCP3 Enhanced PWM output, channel B. May be configured for tri-state during Enhanced PWM shutdown events. Takes priority over port data. RH6 0 O DIG LATH<6> data output. 1 I ST AN14 1 I ANA A/D input channel 14. Default configuration on POR. P1C(1) 0 O DIG ECCP1 Enhanced PWM output, channel C. May be configured for tri-state during Enhanced PWM shutdown events. Takes priority over port data. RH7 0 O DIG LATH<7> data output. 1 I ST PORTH<7> data input. PORTH<6> data input. AN15 1 I ANA A/D input channel 15. Default configuration on POR. P1B(1) 0 O DIG ECCP1 Enhanced PWM output, channel B. May be configured for tri-state during Enhanced PWM shutdown events. Takes priority over port data. PWR = Power Supply, O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input, x = Don't care (TRIS bit does not affect port direction or is overridden for this option). Alternate assignment for P1B/P1C/P3B/P3C (ECCPMX is clear). TABLE 11-16: SUMMARY OF REGISTERS ASSOCIATED WITH PORTH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page TRISH TRISH7 TRISH6 TRISH5 TRISH4 TRISH3 TRISH2 TRISH1 TRISH0 60 PORTH RH7 RH6 RH5 RH4 RH3 RH2 RH1 RH0 60 LATH7 LATH6 LATH5 LATH4 LATH3 LATH2 LATH1 LATH0 60 -- -- VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 59 Name LATH ADCON1 2004 Microchip Technology Inc. Preliminary DS39646B-page 155 PIC18F8722 FAMILY 11.9 Note: PORTJ, TRISJ and LATJ Registers PORTJ is available only on PIC18F8527/8622/8627/8722 devices. PORTJ is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISJ. Setting a TRISJ bit (= 1) will make the corresponding PORTJ pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISJ bit (= 0) will make the corresponding PORTJ pin an output (i.e., put the contents of the output latch on the selected pin). The Data Latch register (LATJ) is also memory mapped. Read-modify-write operations on the LATJ register, read and write the latched output value for PORTJ. When the external memory interface is enabled, all of the PORTJ pins function as control outputs for the interface. This occurs automatically when the interface is enabled by clearing the EBDIS control bit (MEMCON<7>). The TRISJ bits are also overridden. EXAMPLE 11-9: CLRF PORTJ CLRF LATJ MOVLW 0xCF MOVWF TRISJ All pins on PORTJ are implemented with Schmitt Trigger input buffers. Each pin is individually configurable as an input or output. Note: INITIALIZING PORTJ ; ; ; ; ; ; ; ; ; ; ; ; Initialize PORTJ by clearing output data latches Alternate method to clear output data latches Value used to initialize data direction Set RJ3:RJ0 as inputs RJ5:RJ4 as output RJ7:RJ6 as inputs On a Power-on Reset, these pins are configured as digital inputs. DS39646B-page 156 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY TABLE 11-17: PORTJ FUNCTIONS Pin Name RJ0/ALE RJ1/OE RJ2/WRL RJ3/WRH RJ4/BA0 RJ5/CE RJ6/LB RJ7/UB Function TRIS Setting I/O I/O Type RJ0 0 O DIG 1 I ST PORTJ<0> data input. ALE x O DIG External memory interface address latch enable control output. Takes priority over digital I/O. RJ1 0 O DIG LATJ<1> data output. LATJ<0> data output. 1 I ST PORTJ<1> data input. OE x O DIG External memory interface output enable control output. Takes priority over digital I/O. RJ2 0 O DIG LATJ<2> data output. 1 I ST PORTJ<2> data input. WRL x O DIG External memory bus write low byte control. Takes priority over digital I/O. RJ3 0 O DIG LATJ<3> data output. 1 I ST PORTJ<3> data input. WRH x O DIG External memory interface write high byte control output. Takes priority over digital I/O. RJ4 0 O DIG LATJ<4> data output. 1 I ST PORTJ<4> data input. BA0 x O DIG External memory interface byte address 0 control output. Takes priority over digital I/O. RJ5 0 O DIG LATJ<5> data output. 1 I ST PORTJ<5> data input. CE x O DIG External memory interface chip enable control output. Takes priority over digital I/O. RJ6 0 O DIG LATJ<6> data output. 1 I ST PORTJ<6> data input. LB x O DIG External memory interface lower byte enable control output. Takes priority over digital I/O. RJ7 0 O DIG LATJ<7> data output. UB Legend: Description 1 I ST PORTJ<7> data input. x O DIG External memory interface upper byte enable control output. Takes priority over digital I/O. PWR = Power Supply, O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input, x = Don't care (TRIS bit does not affect port direction or is overridden for this option). TABLE 11-18: SUMMARY OF REGISTERS ASSOCIATED WITH PORTJ Name PORTJ Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page RJ7 RJ6 RJ5 RJ4 RJ3 RJ2 RJ1 RJ0 60 LATJ LATJ7 LATJ6 LATJ5 LATJ4 LATJ3 LATJ2 LATJ1 LATJ0 60 TRISJ TRISJ7 TRISJ6 TRISJ5 TRISJ4 TRISJ3 TRISJ2 TRISJ1 TRISJ0 60 2004 Microchip Technology Inc. Preliminary DS39646B-page 157 PIC18F8722 FAMILY FIGURE 11-2: 11.10 Parallel Slave Port PORTD can also function as an 8-bit wide Parallel Slave Port, or microprocessor port, when control bit PSPMODE (PSPCON<4>) is set. It is asynchronously readable and writable by the external world through the RD and WR control input pins. Note: Data Bus D WR LATD or PORTD For PIC18F8527/8622/8627/8722 devices, the Parallel Slave Port is available only in Microcontroller mode. RDx pin TTL Data Latch RD PORTD D ENEN TRIS Latch RD LATD One bit of PORTD A read from the PSP occurs when both the CS and RD lines are first detected low. The data in PORTD is read out and the OBF bit is set. If the user writes new data to PORTD to set OBF, the data is immediately read out; however, the OBF bit is not set. When either the CS or RD lines are detected high, the PORTD pins return to the input state and the PSPIF bit is set. User applications should wait for PSPIF to be set before servicing the PSP; when this happens, the IBF and OBF bits can be polled and the appropriate action taken. The timing for the control signals in Write and Read modes is shown in Figure 11-3 and Figure 11-4, respectively. DS39646B-page 158 Q CKx Q The PSP can directly interface to an 8-bit microprocessor data bus. The external microprocessor can read or write the PORTD latch as an 8-bit latch. Setting bit PSPMODE enables port pin RE0/RD to be the RD input, RE1/WR to be the WR input and RE2/CS to be the CS (Chip Select) input. For this functionality, the corresponding data direction bits of the TRISE register (TRISE<2:0>) must be configured as inputs (set). A write to the PSP occurs when both the CS and WR lines are first detected low and ends when either are detected high. The PSPIF and IBF flag bits are both set when the write ends. PORTD AND PORTE BLOCK DIAGRAM (PARALLEL SLAVE PORT) Preliminary Set Interrupt Flag PSPIF (PIR1<7>) Read TTL RD Chip Select TTL CS Write TTL WR Note: I/O pin has protection diodes to VDD and VSS. 2004 Microchip Technology Inc. PIC18F8722 FAMILY REGISTER 11-1: PSPCON: PARALLEL SLAVE PORT CONTROL REGISTER R-0 R-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 IBF OBF IBOV PSPMODE -- -- -- -- bit 7 bit 0 bit 7 IBF: Input Buffer Full Status bit 1 = A word has been received and is waiting to be read by the CPU 0 = No word has been received bit 6 OBF: Output Buffer Full Status bit 1 = The output buffer still holds a previously written word 0 = The output buffer has been read bit 5 IBOV: Input Buffer Overflow Detect bit 1 = A write occurred when a previously input word has not been read (must be cleared in software) 0 = No overflow occurred bit 4 PSPMODE: Parallel Slave Port Mode Select bit 1 = Parallel Slave Port mode 0 = General Purpose I/O mode bit 3-0 Unimplemented: Read as `0' Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared 2004 Microchip Technology Inc. Preliminary x = Bit is unknown DS39646B-page 159 PIC18F8722 FAMILY FIGURE 11-3: PARALLEL SLAVE PORT WRITE WAVEFORMS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q4 Q1 Q2 Q3 Q4 CS WR RD PORTD<7:0> IBF OBF PSPIF FIGURE 11-4: PARALLEL SLAVE PORT READ WAVEFORMS Q1 Q2 Q3 Q4 Q1 Q2 Q3 CS WR RD PORTD<7:0> IBF OBF PSPIF TABLE 11-19: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT Name PORTD Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 60 LATD LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 60 TRISD TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 60 PORTE RE7 RE6 RE5 RE4 RE3 RE2 RE1 RE0 60 LATE LATE7 LATE6 LATE5 LATE4 LATE3 LATE2 LATE1 LATE0 60 TRISE TRISE7 TRISE6 TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 TRISE0 60 IBF OBF IBOV PSPMODE -- -- -- -- 59 PSPCON INTCON TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 57 PIR1 GIE/GIEH PEIE/GIEL PSPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 60 PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 60 IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 60 Legend: -- = unimplemented, read as `0'. Shaded cells are not used by the Parallel Slave Port. DS39646B-page 160 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY 12.0 TIMER0 MODULE The Timer0 module incorporates the following features: * Software selectable operation as a timer or counter in both 8-bit or 16-bit modes * Readable and writable registers * Dedicated 8-bit, software programmable prescaler * Selectable clock source (internal or external) * Edge select for external clock * Interrupt-on-overflow REGISTER 12-1: The T0CON register (Register 12-1) controls all aspects of the module's operation, including the prescale selection. It is both readable and writable. A simplified block diagram of the Timer0 module in 8-bit mode is shown in Figure 12-1. Figure 12-2 shows a simplified block diagram of the Timer0 module in 16-bit mode. T0CON: TIMER0 CONTROL REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 bit 7 bit 0 bit 7 TMR0ON: Timer0 On/Off Control bit 1 = Enables Timer0 0 = Stops Timer0 bit 6 T08BIT: Timer0 8-bit/16-bit Control bit 1 = Timer0 is configured as an 8-bit timer/counter 0 = Timer0 is configured as a 16-bit timer/counter bit 5 T0CS: Timer0 Clock Source Select bit 1 = Transition on T0CKI pin 0 = Internal instruction cycle clock (CLKO) bit 4 T0SE: Timer0 Source Edge Select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin bit 3 PSA: Timer0 Prescaler Assignment bit 1 = TImer0 prescaler is NOT assigned. Timer0 clock input bypasses prescaler. 0 = Timer0 prescaler is assigned. Timer0 clock input comes from prescaler output. bit 2-0 T0PS2:T0PS0: Timer0 Prescaler Select bits 111 = 1:256 Prescale value 110 = 1:128 Prescale value 101 = 1:64 Prescale value 100 = 1:32 Prescale value 011 = 1:16 Prescale value 010 = 1:8 Prescale value 001 = 1:4 Prescale value 000 = 1:2 Prescale value Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared 2004 Microchip Technology Inc. Preliminary x = Bit is unknown DS39646B-page 161 PIC18F8722 FAMILY 12.1 Timer0 Operation Timer0 can operate as either a timer or a counter; the mode is selected with the T0CS bit (T0CON<5>). In Timer mode (T0CS = 0), the module increments on every clock by default unless a different prescaler value is selected (see Section 12.3 "Prescaler"). If the TMR0 register is written to, the increment is inhibited for the following two instruction cycles. The user can work around this by writing an adjusted value to the TMR0 register. The Counter mode is selected by setting the T0CS bit (= 1). In this mode, Timer0 increments either on every rising or falling edge of pin RA4/T0CKI. The incrementing edge is determined by the Timer0 Source Edge Select bit, T0SE (T0CON<4>); clearing this bit selects the rising edge. Restrictions on the external clock input are discussed below. An external clock source can be used to drive Timer0; however, it must meet certain requirements to ensure that the external clock can be synchronized with the FIGURE 12-1: internal phase clock (TOSC). There is a delay between synchronization and the onset of incrementing the timer/counter. 12.2 Timer0 Reads and Writes in 16-bit Mode TMR0H is not the actual high byte of Timer0 in 16-bit mode; it is actually a buffered version of the real high byte of Timer0 which is not directly readable nor writable (refer to Figure 12-2). TMR0H is updated with the contents of the high byte of Timer0 during a read of TMR0L. This provides the ability to read all 16 bits of Timer0 without having to verify that the read of the high and low byte were valid, due to a rollover between successive reads of the high and low byte. Similarly, a write to the high byte of Timer0 must also take place through the TMR0H Buffer register. The high byte is updated with the contents of TMR0H when a write occurs to TMR0L. This allows all 16 bits of Timer0 to be updated at once. TIMER0 BLOCK DIAGRAM (8-BIT MODE) FOSC/4 0 1 1 Programmable Prescaler T0CKI pin T0SE T0CS 0 Sync with Internal Clocks Set TMR0IF on Overflow TMR0L (2 TCY Delay) 8 3 T0PS2:T0PS0 8 PSA Note: Internal Data Bus Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale. FIGURE 12-2: TIMER0 BLOCK DIAGRAM (16-BIT MODE) FOSC/4 0 1 1 T0CKI pin T0SE T0CS Programmable Prescaler 0 Sync with Internal Clocks TMR0 High Byte TMR0L 8 Set TMR0IF on Overflow (2 TCY Delay) 3 Read TMR0L T0PS2:T0PS0 Write TMR0L PSA 8 8 TMR0H 8 8 Internal Data Bus Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale. DS39646B-page 162 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY 12.3 12.3.1 Prescaler An 8-bit counter is available as a prescaler for the Timer0 module. The prescaler is not directly readable or writable; its value is set by the PSA and T0PS2:T0PS0 bits (T0CON<3:0>) which determine the prescaler assignment and prescale ratio. Clearing the PSA bit assigns the prescaler to the Timer0 module. When it is assigned, prescale values from 1:2 through 1:256 in power-of-2 increments are selectable. When assigned to the Timer0 module, all instructions writing to the TMR0 register (e.g., CLRF TMR0, MOVWF TMR0, BSF TMR0, etc.) clear the prescaler count. Note: Writing to TMR0 when the prescaler is assigned to Timer0 will clear the prescaler count, but will not change the prescaler assignment. TABLE 12-1: Name SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software control and can be changed "on-the-fly" during program execution. 12.4 Timer0 Interrupt The TMR0 interrupt is generated when the TMR0 register overflows from FFh to 00h in 8-bit mode, or from FFFFh to 0000h in 16-bit mode. This overflow sets the TMR0IF flag bit. The interrupt can be masked by clearing the TMR0IE bit (INTCON<5>). Before reenabling the interrupt, the TMR0IF bit must be cleared in software by the Interrupt Service Routine. Since Timer0 is shut down in Sleep mode, the TMR0 interrupt cannot awaken the processor from Sleep. REGISTERS ASSOCIATED WITH TIMER0 Bit 7 Bit 6 Bit 5 TMR0L Timer0 Register Low Byte TMR0H Timer0 Register High Byte INTCON GIE/GIEH PEIE/GIEL TMR0IE T0CON TMR0ON TRISA TRISA7(1) TRISA6(1) T08BIT Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page 58 58 INT0IE RBIE TMR0IF INT0IF RBIF 57 T0CS T0SE PSA T0PS2 T0PS1 T0PS0 58 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 60 Legend: Shaded cells are not used by Timer0. Note 1: PORTA<7:6> and their direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as `0'. 2004 Microchip Technology Inc. Preliminary DS39646B-page 163 PIC18F8722 FAMILY NOTES: DS39646B-page 164 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY 13.0 TIMER1 MODULE The Timer1 timer/counter module incorporates these features: * Software selectable operation as a 16-bit timer or counter * Readable and writable 8-bit registers (TMR1H and TMR1L) * Selectable clock source (internal or external) with device clock or Timer1 oscillator internal options * Interrupt-on-overflow * Reset on CCP special event trigger * Device clock status flag (T1RUN) REGISTER 13-1: A simplified block diagram of the Timer1 module is shown in Figure 13-1. A block diagram of the module's operation in Read/Write mode is shown in Figure 13-2. The module incorporates its own low-power oscillator to provide an additional clocking option. The Timer1 oscillator can also be used as a low-power clock source for the microcontroller in power-managed operation. Timer1 can also be used to provide Real-Time Clock (RTC) functionality to applications with only a minimal addition of external components and code overhead. Timer1 is controlled through the T1CON Control register (Register 13-1). It also contains the Timer1 Oscillator Enable bit (T1OSCEN). Timer1 can be enabled or disabled by setting or clearing control bit, TMR1ON (T1CON<0>). T1CON: TIMER1 CONTROL REGISTER R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON bit 7 bit 0 bit 7 RD16: 16-bit Read/Write Mode Enable bit 1 = Enables register read/write of Timer1 in one 16-bit operation 0 = Enables register read/write of Timer1 in two 8-bit operations bit 6 T1RUN: Timer1 System Clock Status bit 1 = Device clock is derived from Timer1 oscillator 0 = Device clock is derived from another source bit 5-4 T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value bit 3 T1OSCEN: Timer1 Oscillator Enable bit 1 = Timer1 oscillator is enabled 0 = Timer1 oscillator is shut off The oscillator inverter and feedback resistor are turned off to eliminate power drain. bit 2 T1SYNC: Timer1 External Clock Input Synchronization Select bit When TMR1CS = 1: 1 = Do not synchronize external clock input 0 = Synchronize external clock input When TMR1CS = 0: This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0. bit 1 TMR1CS: Timer1 Clock Source Select bit 1 = External clock from pin RC0/T1OSO/T13CKI (on the rising edge) 0 = Internal clock (FOSC/4) bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 Legend: R = Readable bit -n = Value at POR 2004 Microchip Technology Inc. W = Writable bit `1' = Bit is set Preliminary U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown DS39646B-page 165 PIC18F8722 FAMILY 13.1 Timer1 Operation cycle (Fosc/4). When the bit is set, Timer1 increments on every rising edge of the Timer1 external clock input or the Timer1 oscillator, if enabled. Timer1 can operate in one of these modes: * Timer * Synchronous Counter * Asynchronous Counter When Timer1 is enabled, the RC1/T1OSI and RC0/ T1OSO/T13CKI pins become inputs. This means the values of TRISC<1:0> are ignored and the pins are read as `0'. The operating mode is determined by the clock select bit, TMR1CS (T1CON<1>). When TMR1CS is cleared (= 0), Timer1 increments on every internal instruction FIGURE 13-1: TIMER1 BLOCK DIAGRAM Timer1 Oscillator Timer1 Clock Input 1 On/Off T1OSO/T13CKI 1 T1OSI Synchronize Prescaler 1, 2, 4, 8 FOSC/4 Internal Clock 0 Detect 0 2 T1OSCEN(1) Sleep Input Timer1 On/Off TMR1CS T1CKPS1:T1CKPS0 T1SYNC TMR1ON Clear TMR1 (CCP special event trigger) Set TMR1IF on Overflow TMR1 High Byte TMR1L Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain. FIGURE 13-2: TIMER1 BLOCK DIAGRAM (16-BIT READ/WRITE MODE) Timer1 Oscillator Timer1 Clock Input 1 T1OSO/T13CKI T1OSI 1 FOSC/4 Internal Clock Synchronize Prescaler 1, 2, 4, 8 0 Detect 0 2 Sleep Input TMR1CS T1OSCEN(1) T1CKPS1:T1CKPS0 T1SYNC TMR1ON Clear TMR1 (CCP special event trigger) Timer1 On/Off TMR1 High Byte TMR1L 8 Set TMR1IF on Overflow Read TMR1L Write TMR1L 8 8 TMR1H 8 8 Internal Data Bus Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain. DS39646B-page 166 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY 13.2 TABLE 13-1: Timer1 16-bit Read/Write Mode Timer1 can be configured for 16-bit reads and writes (see Figure 13-2). When the RD16 control bit (T1CON<7>) is set, the address for TMR1H is mapped to a buffer register for the high byte of Timer1. A read from TMR1L will load the contents of the high byte of Timer1 into the Timer1 high byte buffer. This provides the user with the ability to accurately read all 16 bits of Timer1 without having to determine whether a read of the high byte, followed by a read of the low byte, has become invalid due to a rollover between reads. Osc Type LP CAPACITOR SELECTION FOR THE TIMER OSCILLATOR(2,3,4) Freq 32 kHz C1 27 pF C2 (1) 27 pF(1) Note 1: Microchip suggests these values as a starting point in validating the oscillator circuit. 2: Higher capacitance increases the stability of the oscillator but also increases the start-up time. A write to the high byte of Timer1 must also take place through the TMR1H Buffer register. The Timer1 high byte is updated with the contents of TMR1H when a write occurs to TMR1L. This allows a user to write all 16 bits to both the high and low bytes of Timer1 at once. 3: Since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components. The high byte of Timer1 is not directly readable or writable in this mode. All reads and writes must take place through the Timer1 High Byte Buffer register. Writes to TMR1H do not clear the Timer1 prescaler. The prescaler is only cleared on writes to TMR1L. 4: Capacitor values are for design guidance only. 13.3 Timer1 Oscillator An on-chip crystal oscillator circuit is incorporated between pins T1OSI (input) and T1OSO (amplifier output). It is enabled by setting the Timer1 Oscillator Enable bit, T1OSCEN (T1CON<3>). The oscillator is a lowpower circuit rated for 32 kHz crystals. It will continue to run during all power-managed modes. The circuit for a typical LP oscillator is shown in Figure 13-3. Table 13-1 shows the capacitor selection for the Timer1 oscillator. The user must provide a software time delay to ensure proper start-up of the Timer1 oscillator. FIGURE 13-3: EXTERNAL COMPONENTS FOR THE TIMER1 LP OSCILLATOR C1 27 pF PIC18FXXXX XTAL 32.768 kHz T1OSO C2 27 pF See the Notes with Table 13-1 for additional information about capacitor selection. USING TIMER1 AS A CLOCK SOURCE The Timer1 oscillator is also available as a clock source in power-managed modes. By setting the clock select bits, SCS1:SCS0 (OSCCON<1:0>), to `01', the device switches to SEC_RUN mode; both the CPU and peripherals are clocked from the Timer1 oscillator. If the IDLEN bit (OSCCON<7>) is cleared and a SLEEP instruction is executed, the device enters SEC_IDLE mode. Additional details are available in Section 3.0 "Power-Managed Modes". Whenever the Timer1 oscillator is providing the clock source, the Timer1 system clock status flag, T1RUN (T1CON<6>), is set. This can be used to determine the controller's current clocking mode. It can also indicate the clock source being currently used by the Fail-Safe Clock Monitor. If the Clock Monitor is enabled and the Timer1 oscillator fails while providing the clock, polling the T1RUN bit will indicate whether the clock is being provided by the Timer1 oscillator or another source. 13.3.2 T1OSI Note: 13.3.1 LOW-POWER TIMER1 OPTION The Timer1 oscillator can operate at two distinct levels of power consumption based on device configuration. When the LPT1OSC configuration bit is set, the Timer1 oscillator operates in a low-power mode. When LPT1OSC is not set, Timer1 operates at a higher power level. Power consumption for a particular mode is relatively constant, regardless of the device's operating mode. The default Timer1 configuration is the higher power mode. As the low-power Timer1 mode tends to be more sensitive to interference, high noise environments may cause some oscillator instability. The low-power option is, therefore, best suited for low noise applications where power conservation is an important design consideration. 2004 Microchip Technology Inc. Preliminary DS39646B-page 167 PIC18F8722 FAMILY 13.3.3 TIMER1 OSCILLATOR LAYOUT CONSIDERATIONS The Timer1 oscillator circuit draws very little power during operation. Due to the low-power nature of the oscillator, it may also be sensitive to rapidly changing signals in close proximity. The oscillator circuit, shown in Figure 13-3, should be located as close as possible to the microcontroller. There should be no circuits passing within the oscillator circuit boundaries other than VSS or VDD. If a high-speed circuit must be located near the Timer1 oscillator, a grounded guard ring around the oscillator circuit may be helpful when used on a single-sided PCB or in addition to a ground plane. 13.4 Timer1 Interrupt The TMR1 register pair (TMR1H:TMR1L) increments from 0000h to FFFFh and rolls over to 0000h. The Timer1 interrupt, if enabled, is generated on overflow, which is latched in interrupt flag bit, TMR1IF (PIR1<0>). This interrupt can be enabled or disabled by setting or clearing the Timer1 Interrupt Enable bit, TMR1IE (PIE1<0>). 13.5 Resetting Timer1 Using the CCP Special Event Trigger If any of the CCP modules are configured to use Timer1 and generate a special event trigger in Compare mode (CCPxM3:CCPxM0, this signal will reset Timer1. The trigger from the ECCP2 module will also start an A/D conversion if the A/D module is enabled (see Section 17.3.4 "Special Event Trigger" for more information). The module must be configured as either a timer or a synchronous counter to take advantage of this feature. When used this way, the CCPRH:CCPRL register pair effectively becomes a period register for Timer1. If Timer1 is running in Asynchronous Counter mode, this Reset operation may not work. DS39646B-page 168 In the event that a write to Timer1 coincides with a special event trigger, the write operation will take precedence. Note: 13.6 The special event triggers from the CCPx module will not set the TMR1IF interrupt flag bit (PIR1<0>). Using Timer1 as a Real-Time Clock Adding an external LP oscillator to Timer1 (such as the one described in Section 13.3 "Timer1 Oscillator" above) gives users the option to include RTC functionality to their applications. This is accomplished with an inexpensive watch crystal to provide an accurate time base and several lines of application code to calculate the time. When operating in Sleep mode and using a battery or supercapacitor as a power source, it can completely eliminate the need for a separate RTC device and battery backup. The application code routine, RTCisr, shown in Example 13-1, demonstrates a simple method to increment a counter at one-second intervals using an Interrupt Service Routine. Incrementing the TMR1 register pair to overflow triggers the interrupt and calls the routine, which increments the seconds counter by one; additional counters for minutes and hours are incremented as the previous counter overflow. Since the register pair is 16 bits wide, counting up to overflow the register directly from a 32.768 kHz clock would take 2 seconds. To force the overflow at the required one-second intervals, it is necessary to preload it; the simplest method is to set the MSb of TMR1H with a BSF instruction. Note that the TMR1L register is never preloaded or altered; doing so may introduce cumulative error over many cycles. For this method to be accurate, Timer1 must operate in Asynchronous mode and the Timer1 overflow interrupt must be enabled (PIE1<0> = 1), as shown in the routine, RTCinit. The Timer1 oscillator must also be enabled and running at all times. Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY EXAMPLE 13-1: IMPLEMENTING A REAL-TIME CLOCK USING A TIMER1 INTERRUPT SERVICE RTCinit MOVLW MOVWF CLRF MOVLW MOVWF CLRF CLRF MOVLW MOVWF BSF RETURN 80h TMR1H TMR1L b'00001111' T1CON secs mins .12 hours PIE1, TMR1IE ; Preload TMR1 register pair ; for 1 second overflow BSF BCF INCF MOVLW CPFSGT RETURN CLRF INCF MOVLW CPFSGT RETURN CLRF INCF MOVLW CPFSGT RETURN CLRF RETURN TMR1H, 7 PIR1, TMR1IF secs, F .59 secs ; ; ; ; Preload for 1 sec overflow Clear interrupt flag Increment seconds 60 seconds elapsed? ; ; ; ; No, done Clear seconds Increment minutes 60 minutes elapsed? ; ; ; ; No, done clear minutes Increment hours 24 hours elapsed? ; Configure for external clock, ; Asynchronous operation, external oscillator ; Initialize timekeeping registers ; ; Enable Timer1 interrupt RTCisr TABLE 13-2: Name INTCON secs mins, F .59 mins mins hours, F .23 hours ; No, done ; Reset hours ; Done hours REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER Bit 7 Bit 6 GIE/GIEH PEIE/GIEL Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 57 PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 60 PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 60 IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 60 TMR1L Timer1 Register Low Byte 58 TMR1H Timer1 Register High Byte 58 T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 58 Legend: Shaded cells are not used by the Timer1 module. 2004 Microchip Technology Inc. Preliminary DS39646B-page 169 PIC18F8722 FAMILY NOTES: DS39646B-page 170 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY 14.0 TIMER2 MODULE 14.1 The Timer2 timer module incorporates the following features: * 8-bit timer and period registers (TMR2 and PR2, respectively) * Readable and writable (both registers) * Software programmable prescaler (1:1, 1:4 and 1:16) * Software programmable postscaler (1:1 through 1:16) * Interrupt on TMR2-to-PR2 match * Optional use as the shift clock for the MSSPx module The module is controlled through the T2CON register (Register 14-1), which enables or disables the timer and configures the prescaler and postscaler. Timer2 can be shut off by clearing control bit, TMR2ON (T2CON<2>), to minimize power consumption. A simplified block diagram of the module is shown in Figure 14-1. Timer2 Operation In normal operation, TMR2 is incremented from 00h on each clock (FOSC/4). A 4-bit counter/prescaler on the clock input gives direct input, divide-by-4 and divide-by16 prescale options; these are selected by the prescaler control bits, T2CKPS1:T2CKPS0 (T2CON<1:0>). The value of TMR2 is compared to that of the period register, PR2, on each clock cycle. When the two values match, the comparator generates a match signal as the timer output. This signal also resets the value of TMR2 to 00h on the next cycle and drives the output counter/ postscaler (see Section 14.2 "Timer2 Interrupt"). The TMR2 and PR2 registers are both directly readable and writable. The TMR2 register is cleared on any device Reset, while the PR2 register initializes at FFh. Both the prescaler and postscaler counters are cleared on the following events: * a write to the TMR2 register * a write to the T2CON register * any device Reset (Power-on Reset, MCLR Reset, Watchdog Timer Reset or Brown-out Reset) TMR2 is not cleared when T2CON is written. REGISTER 14-1: T2CON: TIMER2 CONTROL REGISTER U-0 -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 R/W-0 T2CKPS0 bit 7 bit 0 bit 7 Unimplemented: Read as `0' bit 6-3 T2OUTPS3:T2OUTPS0: Timer2 Output Postscale Select bits 0000 = 1:1 Postscale 0001 = 1:2 Postscale * * * 1111 = 1:16 Postscale bit 2 TMR2ON: Timer2 On bit 1 = Timer2 is on 0 = Timer2 is off bit 1-0 T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits 00 = Prescaler is 1 01 = Prescaler is 4 1x = Prescaler is 16 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared 2004 Microchip Technology Inc. Preliminary x = Bit is unknown DS39646B-page 171 PIC18F8722 FAMILY 14.2 Timer2 Interrupt 14.3 Timer2 also can generate an optional device interrupt. The Timer2 output signal (TMR2-to-PR2 match) provides the input for the 4-bit output counter/postscaler. This counter generates the TMR2 match interrupt flag which is latched in TMR2IF (PIR1<1>). The interrupt is enabled by setting the TMR2 Match Interrupt Enable bit, TMR2IE (PIE1<1>). Timer2 Output The unscaled output of TMR2 is available primarily to the CCP modules, where it is used as a time base for operations in PWM mode. Timer2 can be optionally used as the shift clock source for the MSSP module operating in SPI mode. Additional information is provided in Section 19.0 "Master Synchronous Serial Port (MSSP) Module". A range of 16 postscale options (from 1:1 through 1:16 inclusive) can be selected with the postscaler control bits, T2OUTPS3:T2OUTPS0 (T2CON<6:3>). FIGURE 14-1: TIMER2 BLOCK DIAGRAM 4 1:1 to 1:16 Postscaler T2OUTPS3:T2OUTPS0 Set TMR2IF 2 TMR2 Output (to PWM or MSSP) T2CKPS1:T2CKPS0 1:1, 1:4, 1:16 Prescaler FOSC/4 TMR2/PR2 Match Reset TMR2 Comparator 8 PR2 8 8 Internal Data Bus TABLE 14-1: Name REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER Bit 7 Bit 6 INTCON GIE/GIEH PEIE/GIEL Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page 57 TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 60 PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 60 IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 60 TMR2 T2CON PR2 Timer2 Register -- 58 T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 Timer2 Period Register 58 58 Legend: -- = unimplemented, read as `0'. Shaded cells are not used by the Timer2 module. DS39646B-page 172 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY 15.0 TIMER3 MODULE The Timer3 timer/counter module incorporates these features: * Software selectable operation as a 16-bit timer or counter * Readable and writable 8-bit registers (TMR3H and TMR3L) * Selectable clock source (internal or external) with device clock or Timer1 oscillator internal options * Interrupt-on-overflow * Module Reset on CCP special event trigger REGISTER 15-1: A simplified block diagram of the Timer3 module is shown in Figure 15-1. A block diagram of the module's operation in Read/Write mode is shown in Figure 15-2. The Timer3 module is controlled through the T3CON register (Register 15-1). It also selects the clock source options for the CCP modules (see Section 17.1.1 "CCP Modules and Timer Resources" for more information). T3CON: TIMER3 CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON bit 7 bit 0 bit 7 RD16: 16-bit Read/Write Mode Enable bit 1 = Enables register read/write of Timer3 in one 16-bit operation 0 = Enables register read/write of Timer3 in two 8-bit operations bit 6,3 T3CCP2:T3CCP1: Timer3 and Timer1 to CCPx Enable bits 11 = Timer3 and Timer4 are the clock sources for ECCP1, ECCP2, ECCP3, CCP4 and CCP5 10 = Timer3 and Timer4 are the clock sources for ECCP3, CCP4 and CCP5; Timer1 and Timer2 are the clock sources for ECCP1 and ECCP2 01 = Timer3 and Timer4 are the clock sources for ECCP2, ECCP3, CCP4 and CCP5; Timer1 and Timer2 are the clock sources for ECCP1 00 = Timer1 and Timer2 are the clock sources for ECCP1, ECCP2, ECCP3, CCP4 and CCP5 bit 5-4 T3CKPS1:T3CKPS0: Timer3 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value bit 2 T3SYNC: Timer3 External Clock Input Synchronization Control bit (Not usable if the device clock comes from Timer1/Timer3.) When TMR3CS = 1: 1 = Do not synchronize external clock input 0 = Synchronize external clock input When TMR3CS = 0: This bit is ignored. Timer3 uses the internal clock when TMR3CS = 0. bit 1 TMR3CS: Timer3 Clock Source Select bit 1 = External clock input from Timer1 oscillator or T13CKI (on the rising edge after the first falling edge) 0 = Internal clock (FOSC/4) bit 0 TMR3ON: Timer3 On bit 1 = Enables Timer3 0 = Stops Timer3 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared 2004 Microchip Technology Inc. Preliminary x = Bit is unknown DS39646B-page 173 PIC18F8722 FAMILY 15.1 Timer3 Operation The operating mode is determined by the clock select bit, TMR3CS (T3CON<1>). When TMR3CS is cleared (= 0), Timer3 increments on every internal instruction cycle (FOSC/4). When the bit is set, Timer3 increments on every rising edge of the Timer1 external clock input or the Timer1 oscillator, if enabled. Timer3 can operate in one of three modes: * Timer * Synchronous Counter * Asynchronous Counter As with Timer1, the RC1/T1OSI and RC0/T1OSO/ T13CKI pins become inputs when the Timer1 oscillator is enabled. This means the values of TRISC<1:0> are ignored and the pins are read as `0'. FIGURE 15-1: TIMER3 BLOCK DIAGRAM Timer1 Oscillator Timer1 Clock Input 1 T1OSO/T13CKI 1 FOSC/4 Internal Clock T1OSI Synchronize Prescaler 1, 2, 4, 8 0 Detect 0 2 T1OSCEN (1) Sleep Input Timer3 On/Off TMR3CS T3CKPS1:T3CKPS0 T3SYNC TMR3ON CCPx Special Event Trigger CCPx Select from T3CON<6,3> Clear TMR3 Set TMR3IF on Overflow TMR3 High Byte TMR3L Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain. FIGURE 15-2: TIMER3 BLOCK DIAGRAM (16-BIT READ/WRITE MODE) Timer1 Oscillator Timer1 Clock Input 1 T13CKI/T1OSO 1 FOSC/4 Internal Clock T1OSI Synchronize Prescaler 1, 2, 4, 8 0 Detect 0 2 Sleep Input TMR3CS T1OSCEN(1) T3CKPS1:T3CKPS0 Timer3 On/Off T3SYNC TMR3ON CCPx Special Event Trigger CCPx Select from T3CON<6,3> Clear TMR3 Set TMR3IF on Overflow TMR3 High Byte TMR3L 8 Read TMR1L Write TMR1L 8 8 TMR3H 8 8 Internal Data Bus Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain. DS39646B-page 174 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY 15.2 Timer3 16-bit Read/Write Mode 15.4 Timer3 Interrupt Timer3 can be configured for 16-bit reads and writes (see Figure 15-2). When the RD16 control bit (T3CON<7>) is set, the address for TMR3H is mapped to a buffer register for the high byte of Timer3. A read from TMR3L will load the contents of the high byte of Timer3 into the Timer3 High Byte Buffer register. This provides the user with the ability to accurately read all 16 bits of Timer3 without having to determine whether a read of the high byte, followed by a read of the low byte, has become invalid due to a rollover between reads. The TMR3 register pair (TMR3H:TMR3L) increments from 0000h to FFFFh and overflows to 0000h. The Timer3 interrupt, if enabled, is generated on overflow and is latched in interrupt flag bit, TMR3IF (PIR2<1>). This interrupt can be enabled or disabled by setting or clearing the Timer3 Interrupt Enable bit, TMR3IE (PIE2<1>). A write to the high byte of Timer3 must also take place through the TMR3H Buffer register. The Timer3 high byte is updated with the contents of TMR3H when a write occurs to TMR3L. This allows a user to write all 16 bits to both the high and low bytes of Timer3 at once. If any of the CCP modules are configured to use Timer3 and to generate a special event trigger in Compare mode (CCPxM3:CCPxM0 = 1011), this signal will reset Timer3. ECCP2 can also start an A/D conversion if the A/D module is enabled (see Section 17.3.4 "Special Event Trigger" for more information). The high byte of Timer3 is not directly readable or writable in this mode. All reads and writes must take place through the Timer3 High Byte Buffer register. Writes to TMR3H do not clear the Timer3 prescaler. The prescaler is only cleared on writes to TMR3L. 15.3 Using the Timer1 Oscillator as the Timer3 Clock Source The Timer1 internal oscillator may be used as the clock source for Timer3. The Timer1 oscillator is enabled by setting the T1OSCEN (T1CON<3>) bit. To use it as the Timer3 clock source, the TMR3CS bit must also be set. As previously noted, this also configures Timer3 to increment on every rising edge of the oscillator source. 15.5 Resetting Timer3 Using the CCP Special Event Trigger The module must be configured as either a timer or synchronous counter to take advantage of this feature. When used this way, the CCPRxH:CCPRxL register pair effectively becomes a period register for Timer3. If Timer3 is running in Asynchronous Counter mode, the Reset operation may not work. In the event that a write to Timer3 coincides with a special event trigger from a CCP module, the write will take precedence. Note: The special event triggers from the CCPx module will not set the TMR3IF interrupt flag bit (PIR2<1>). The Timer1 oscillator is described in Section 13.0 "Timer1 Module". TABLE 15-1: Name INTCON REGISTERS ASSOCIATED WITH TIMER3 AS A TIMER/COUNTER Bit 7 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 57 Bit 6 GIE/GIEH PEIE/GIEL PIR2 OSCFIF CMIF -- EEIF BCL1IF HLVDIF TMR3IF CCP2IF 60 PIE2 OSCFIE CMIE -- EEIE BCL1IE HLVDIE TMR3IE CCP2IE 60 IPR2 OSCFIP CMIP -- EEIP BCL1IP HLVDIP TMR3IP CCP2IP 60 TMR3L Timer3 Register Low Byte 59 TMR3H Timer3 Register High Byte 59 T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 58 T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 TMR3CS TMR3ON 59 T3CCP1 T3SYNC Legend: -- = unimplemented, read as `0'. Shaded cells are not used by the Timer3 module. 2004 Microchip Technology Inc. Preliminary DS39646B-page 175 PIC18F8722 FAMILY NOTES: DS39646B-page 176 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY 16.0 TIMER4 MODULE 16.1 The Timer4 timer module has the following features: * * * * * * 8-bit timer register (TMR4) 8-bit period register (PR4) Readable and writable (both registers) Software programmable prescaler (1:1, 1:4, 1:16) Software programmable postscaler (1:1 to 1:16) Interrupt on TMR4 match of PR4 Timer4 has a control register shown in Register 16-1. Timer4 can be shut off by clearing control bit, TMR4ON (T4CON<2>), to minimize power consumption. The prescaler and postscaler selection of Timer4 are also controlled by this register. Figure 16-1 is a simplified block diagram of the Timer4 module. Timer4 Operation Timer4 can be used as the PWM time base for the PWM mode of the CCP modules. The TMR4 register is readable and writable and is cleared on any device Reset. The input clock (FOSC/4) has a prescale option of 1:1, 1:4 or 1:16, selected by control bits T4CKPS1:T4CKPS0 (T4CON<1:0>). The match output of TMR4 goes through a 4-bit postscaler (which gives a 1:1 to 1:16 scaling inclusive) to generate a TMR4 interrupt, latched in flag bit TMR4IF (PIR3<3>). The prescaler and postscaler counters are cleared when any of the following occurs: * a write to the TMR4 register * a write to the T4CON register * any device Reset (Power-on Reset, MCLR Reset, Watchdog Timer Reset or Brown-out Reset) TMR4 is not cleared when T4CON is written. REGISTER 16-1: T4CON: TIMER4 CONTROL REGISTER U-0 -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0 bit 7 bit 0 bit 7 Unimplemented: Read as `0' bit 6-3 T4OUTPS3:T4OUTPS0: Timer4 Output Postscale Select bits 0000 = 1:1 Postscale 0001 = 1:2 Postscale * * * 1111 = 1:16 Postscale bit 2 TMR4ON: Timer4 On bit 1 = Timer4 is on 0 = Timer4 is off bit 1-0 T4CKPS1:T4CKPS0: Timer4 Clock Prescale Select bits 00 = Prescaler is 1 01 = Prescaler is 4 1x = Prescaler is 16 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared 2004 Microchip Technology Inc. Preliminary x = Bit is unknown DS39646B-page 177 PIC18F8722 FAMILY 16.2 Timer4 Interrupt 16.3 The Timer4 module has an 8-bit period register, PR4, which is both readable and writable. Timer4 increments from 00h until it matches PR4 and then resets to 00h on the next increment cycle. The PR4 register is initialized to FFh upon Reset. FIGURE 16-1: Output of TMR4 The output of TMR4 (before the postscaler) is used only as a PWM time base for the CCP modules. It is not used as a baud rate clock for the MSSP, as is the Timer2 output. TIMER4 BLOCK DIAGRAM Sets Flag bit TMR4IF TMR4 Output(1) Prescaler 1:1, 1:4, 1:16 FOSC/4 2 TMR4 Reset Comparator EQ Postscaler 1:1 to 1:16 T4CKPS1:T4CKPS0 4 PR4 T4OUTPS3:T4OUTPS0 TABLE 16-1: REGISTERS ASSOCIATED WITH TIMER4 AS A TIMER/COUNTER Name Bit 7 Bit 6 Bit 5 Bit 4 INTCON Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 57 IPR3 SSP2IP BCL2IP RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP 60 PIR3 SSP2IF BCL2IF RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF 60 SSP2IE BCL2IE RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE PIE3 TMR4 T4CON Timer4 Register -- 60 61 T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0 61 PR4 Timer4 Period Register Legend: x = unknown, u = unchanged, -- = unimplemented, read as `0'. Shaded cells are not used by the Timer4 module. DS39646B-page 178 61 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY 17.0 CAPTURE/COMPARE/PWM (CCP) MODULES The PIC18F8722 family of devices all have a total of five CCP (Capture/Compare/PWM) modules. Two of these (CCP4 and CCP5) implement standard Capture, Compare and Pulse-Width Modulation (PWM) modes and are discussed in this section. The other three modules (ECCP1, ECCP2, ECCP3) implement standard Capture and Compare modes, as well as Enhanced PWM modes. These are discussed in Section 18.0 "Enhanced Capture/Compare/PWM (ECCP) Module". Capture and Compare operations described in this chapter apply to all standard and Enhanced CCP modules. The operations of PWM mode described in Section 17.4 "PWM Mode" apply to CCP4 and CCP5 only. Note: Each CCP/ECCP module contains a 16-bit register which can operate as a 16-bit Capture register, a 16-bit Compare register or a PWM Master/Slave Duty Cycle register. For the sake of clarity, all CCP module operations in the following sections are described with respect to CCP4, but are equally applicable to CCP5. REGISTER 17-1: Throughout this section and Section 18.0 "Enhanced Capture/Compare/PWM (ECCP) Module", references to register and bit names that may be associated with a specific CCP module are referred to generically by the use of `x' or `y' in place of the specific module number. Thus, "CCPxCON" might refer to the control register for CCP4 or CCP5, or ECCP1, ECCP2 or ECCP3. "CCPxCON" is used throughout these sections to refer to the module control register, regardless of whether the CCP module is a standard or enhanced implementation. CCPxCON: CCPx CONTROL REGISTER (CCP4 AND CCP5 MODULES) U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 -- -- DCxB1 DCxB0 CCPxM3 CCPxM2 R/W-0 R/W-0 CCPxM1 CCPxM0 bit 7 bit 0 bit 7-6 Unimplemented: Read as `0' bit 5-4 DCxB1:DCxB0: PWM Duty Cycle bit 1 and bit 0 for CCP Module x Capture mode: Unused. Compare mode: Unused. PWM mode: These bits are the two Least Significant bits (bit 1 and bit 0) of the 10-bit PWM duty cycle. The eight Most Significant bits (DCx9:DCx2) of the duty cycle are found in CCPRxL. bit 3-0 CCPxM3:CCPxM0: CCP Module x Mode Select bits 0000 = Capture/Compare/PWM disabled; resets CCPx module 0001 = Reserved 0010 = Compare mode, toggle output on match; CCPxIF bit is set 0011 = Reserved 0100 = Capture mode, every falling edge 0101 = Capture mode, every rising edge 0110 = Capture mode, every 4th rising edge 0111 = Capture mode, every 16th rising edge 1000 = Compare mode, initialize CCPx pin low; on compare match, force CCPx pin high; CCPxIF bit is set 1001 = Compare mode, initialize CCPx pin high; on compare match, force CCPx pin low; CCPxIF bit is set 1010 = Compare mode, generate software interrupt on compare match; CCPxIF bit is set; CCPx pin reflects I/O state 1011 = Compare mode, trigger special event; CCPxIF bit is set, CCPx pin is unaffected (see Section 17.3.4 "Special Event Trigger" for effects of the trigger) 11xx = PWM mode Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared 2004 Microchip Technology Inc. Preliminary x = Bit is unknown DS39646B-page 179 PIC18F8722 FAMILY 17.1 CCP Module Configuration Each Capture/Compare/PWM module is associated with a control register (generically, CCPxCON) and a data register (CCPRx). The data register, in turn, is comprised of two 8-bit registers: CCPRxL (low byte) and CCPRxH (high byte). All registers are both readable and writable. 17.1.1 17.1.2 CCP MODULES AND TIMER RESOURCES The CCP/ECCP modules utilize Timers 1, 2, 3 or 4, depending on the mode selected. Timer1 and Timer3 are available to modules in Capture or Compare modes, while Timer2 and Timer4 are available for modules in PWM mode. TABLE 17-1: CCP MODE - TIMER RESOURCE CCP Mode Timer Resource Capture Compare PWM Timer1 or Timer3 Timer1 or Timer3 Timer2 or Timer4 FIGURE 17-1: ECCP2 PIN ASSIGNMENT The pin assignment for ECCP2 (Capture input, Compare and PWM output) can change, based on device configuration. The CCP2MX configuration bit determines which pin ECCP2 is multiplexed to. By default, it is assigned to RC1 (CCP2MX = 1). If the configuration bit is cleared, ECCP2 is multiplexed with RE7 in Microcontroller mode, or RE3 in all other modes. Changing the pin assignment of ECCP2 does not automatically change any requirements for configuring the port pin. Users must always verify that the appropriate TRIS register is configured correctly for ECCP2 operation regardless of where it is located. CCP AND TIMER INTERCONNECT CONFIGURATIONS T3CCP<2:1> = 00 TMR1 The assignment of a particular timer to a module is determined by the Timer-to-CCP enable bits in the T3CON register (Register 15-1). Depending on the configuration selected, up to four timers may be active at once, with modules in the same configuration (Capture/Compare or PWM) sharing timer resources. The possible configurations are shown in Figure 17-1. TMR3 ECCP1 T3CCP<2:1> = 01 TMR1 TMR3 ECCP1 T3CCP<2:1> = 10 TMR1 TMR3 T3CCP<2:1> = 11 TMR1 TMR3 ECCP1 ECCP1 ECCP2 ECCP2 ECCP2 ECCP2 ECCP3 ECCP3 ECCP3 ECCP3 CCP4 CCP4 CCP4 CCP4 CCP5 CCP5 CCP5 CCP5 TMR2 TMR4 Timer1 is used for all Capture and Compare operations for all CCP modules. Timer2 is used for PWM operations for all CCP modules. Modules may share either timer resource as a common time base. Timer3 and Timer4 are not available. DS39646B-page 180 TMR2 TMR4 Timer1 and Timer2 are used for Capture and Compare or PWM operations for ECCP1 only (depending on selected mode). All other modules use either Timer3 or Timer4. Modules may share either timer resource as a common time base if they are in Capture/ Compare or PWM modes. TMR2 TMR4 Timer1 and Timer2 are used for Capture and Compare or PWM operations for ECCP1 and ECCP2 only (depending on the mode selected for each module). Both modules may use a timer as a common time base if they are both in Capture/Compare or PWM modes. TMR2 TMR4 Timer3 is used for all Capture and Compare operations for all CCP modules. Timer4 is used for PWM operations for all CCP modules. Modules may share either timer resource as a common time base. Timer1 and Timer2 are not available. The other modules use either Timer3 or Timer4. Modules may share either timer resource as a common time base if they are in Capture/ Compare or PWM modes. Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY 17.2 17.2.3 Capture Mode In Capture mode, the CCPRxH:CCPRxL register pair captures the 16-bit value of the TMR1 or TMR3 registers when an event occurs on the corresponding CCPx pin. An event is defined as one of the following: * * * * every falling edge every rising edge every 4th rising edge every 16th rising edge 17.2.1 CCPx PIN CONFIGURATION In Capture mode, the appropriate CCPx pin should be configured as an input by setting the corresponding TRIS direction bit. Note: 17.2.2 If a CCPx pin is configured as an output, a write to the port can cause a capture condition. TIMER1/TIMER3 MODE SELECTION The timers that are to be used with the capture feature (Timer1 and/or Timer3) must be running in Timer mode or Synchronized Counter mode. In Asynchronous Counter mode, the capture operation will not work. The timer to be used with each CCP module is selected in the T3CON register (see Section 17.1.1 "CCP Modules and Timer Resources"). FIGURE 17-2: When the Capture mode is changed, a false capture interrupt may be generated. The user should keep the CCPxIE interrupt enable bit clear to avoid false interrupts. The interrupt flag bit, CCPxIF, should also be cleared following any such change in operating mode. 17.2.4 The event is selected by the mode select bits, CCPxM3:CCPxM0 (CCPxCON<3:0>). When a capture is made, the interrupt request flag bit, CCPxIF, is set; it must be cleared in software. If another capture occurs before the value in the CCPRx registers is read, the old captured value is overwritten by the new captured value. SOFTWARE INTERRUPT CCP PRESCALER There are four prescaler settings in Capture mode; they are specified as part of the operating mode selected by the mode select bits (CCPxM3:CCPxM0). Whenever the CCP module is turned off, or Capture mode is disabled, the prescaler counter is cleared. This means that any Reset will clear the prescaler counter. Switching from one capture prescaler to another may generate an interrupt. Also, the prescaler counter will not be cleared; therefore, the first capture may be from a non-zero prescaler. Example 17-1 shows the recommended method for switching between capture prescalers. This example also clears the prescaler counter and will not generate the "false" interrupt. EXAMPLE 17-1: CLRF MOVLW MOVWF CHANGING BETWEEN CAPTURE PRESCALERS (CCP5 SHOWN) CCP5CON ; Turn CCP module off NEW_CAPT_PS ; Load WREG with the ; new prescaler mode ; value and CCP ON CCP5CON ; Load CCP5CON with ; this value CAPTURE MODE OPERATION BLOCK DIAGRAM TMR3H TMR3L Set Flag bit CCP4IF T3CCP2 Prescaler / 1, 4, 16 RG3/CCP4 pin TMR3 Enable CCPR4H and Edge Detect T3CCP2 CCPR4L TMR1 Enable TMR1H TMR1L CCP1CON<3:0> Q's 2004 Microchip Technology Inc. Preliminary DS39646B-page 181 PIC18F8722 FAMILY 17.3 17.3.2 Compare Mode TIMER1/TIMER3 MODE SELECTION In Compare mode, the 16-bit value of the CCPRx registers is constantly compared against either the TMR1 or TMR3 register pair value. When a match occurs, the CCPx pin can be: Timer1 and/or Timer3 must be running in Timer mode or Synchronized Counter mode if the CCP module is using the compare feature. In Asynchronous Counter mode, the compare operation may not work. * * * * 17.3.3 driven high driven low toggled (high-to-low or low-to-high) remain unchanged (that is, reflects the state of the I/O latch) When the Generate Software Interrupt mode is chosen (CCPxM3:CCPxM0 = 1010), the corresponding CCPx pin is not affected. Only a CCP interrupt is generated, if enabled and the CCPxIE bit is set. The action on the pin is based on the value of the mode select bits (CCPxM3:CCPxM0). At the same time, the interrupt flag bit, CCPxIF, is set. 17.3.1 17.3.4 SPECIAL EVENT TRIGGER All CCP modules are equipped with a special event trigger. This is an internal hardware signal generated in Compare mode to trigger actions by other modules. The special event trigger is enabled by selecting the Compare Special Event Trigger mode (CCPxM3:CCPxM0 = 1011). CCPx PIN CONFIGURATION The user must configure the CCPx pin as an output by clearing the appropriate TRIS bit. Note: SOFTWARE INTERRUPT MODE Clearing the CCPxCON register will force the compare output latch (depending on device configuration) to the default low level. This is not the port I/O data latch. For all CCP modules, the special event trigger resets the timer register pair for whichever timer resource is currently assigned as the module's time base. This allows the CCPRx registers to serve as a programmable period register for either timer. The ECCP2 special event trigger can also start an A/D conversion. In order to do this, the A/D converter must already be enabled. FIGURE 17-3: COMPARE MODE OPERATION BLOCK DIAGRAM Special Event Trigger Set Flag bit CCP4IF CCPR4H CCPR4L Q RG3/CCP4 pin TRISG<3> Output Enable S R Output Logic Comparator Match T3CCP2 CCP4CON<3:0> Mode Select TMR1H DS39646B-page 182 Preliminary TMR1L 0 1 TMR3H TMR3L 2004 Microchip Technology Inc. PIC18F8722 FAMILY TABLE 17-2: Name INTCON REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3 Bit 7 Bit 6 Bit 5 GIE/GIEH PEIE/GIEL TMR0IE Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page INT0IE RBIE TMR0IF INT0IF RBIF 57 RCON IPEN SBOREN -- RI TO PD POR BOR 56 PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 60 PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 60 IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 60 PIR2 OSCFIF CMIF -- EEIF BCL1IF HLVDIF TMR3IF CCP2IF 60 PIE2 OSCFIE CMIE -- EEIE BCL1IE HLVDIE TMR3IE CCP2IE 60 IPR2 OSCFIP CMIP -- EEIP BCL1IP HLVDIP TMR3IP CCP2IP 60 PIR3 SSP2IF BCL2IF RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF 60 PIE3 SSP2IE BCL2IE RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE 60 IPR3 SSP2IP BCL2IP RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP 60 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 60 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 60 TRISE TRISE7 TRISE6 TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 TRISE0 60 TRISG -- -- -- TRISG4 TRISG3 TRISG2 TRISG1 TRISG0 60 TRISH7 TRISH6 TRISH5 TRISH4 TRISH3 TRISH2 TRISH1 TRISH0 60 TRISH(1) TMR1L Timer1 Register Low Byte TMR1H Timer1 Register High Byte T1CON RD16 T1RUN Timer3 Register High Byte TMR3L Timer3 Register Low Byte RD16 T3CCP2 58 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR3H T3CON 58 TMR1CS TMR1ON 58 59 59 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 59 CCPR1L Enhanced Capture/Compare/PWM Register 1 Low Byte 59 CCPR1H Enhanced Capture/Compare/PWM Register 1 High Byte 59 CCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCPR2L Enhanced Capture/Compare/PWM Register 2 Low Byte CCPR2H Enhanced Capture/Compare/PWM Register 2 High Byte DC2B0 CCP2M3 CCP1M2 CCP1M1 CCP1M0 59 59 59 CCP2CON P2M1 P2M0 DC2B1 CCP2M2 CCP2M1 CCP2M0 59 CCP3CON P3M1 P3M0 DC3B1 DC3B0 CCP3M3 CCP3M2 CCP3M1 CCP3M0 59 CCP4CON -- -- DC4B1 DC4B0 CCP4M3 CCP4M2 CCP4M1 CCP4M0 61 CCP5CON -- -- DC5B1 DC5B0 CCP5M3 CCP5M2 CCP5M1 CCP5M0 61 Legend: -- = unimplemented, read as `0'. Shaded cells are not used by Capture/Compare, Timer1 or Timer3. Note 1: Implemented on 80-pin devices only. 2004 Microchip Technology Inc. Preliminary DS39646B-page 183 PIC18F8722 FAMILY 17.4 17.4.1 PWM Mode In Pulse-Width Modulation (PWM) mode, the CCPx pin produces up to a 10-bit resolution PWM output. Since the CCP4 and CCP5 pins are multiplexed with a PORTG data latch, the appropriate TRISG bit must be cleared to make the CCP4 or CCP5 pin an output. Note: Clearing the CCP4CON or CCP5CON register will force the RG3 or RG4 output latch (depending on device configuration) to the default low level. This is not the PORTG I/O data latch. Figure 17-4 shows a simplified block diagram of the CCP module in PWM mode. For a step-by-step procedure on how to set up a CCP module for PWM operation, see Section 17.4.3 "Setup for PWM Operation". FIGURE 17-4: SIMPLIFIED PWM BLOCK DIAGRAM The PWM period is specified by writing to the PR2 (PR4) register. The PWM period can be calculated using the following formula: EQUATION 17-1: PWM Period = [(PR2) + 1] * 4 * TOSC * (TMR2 Prescale Value) PWM frequency is defined as 1/[PWM period]. When TMR2 (TMR4) is equal to PR2 (PR4), the following three events occur on the next increment cycle: * TMR2 (TMR4) is cleared * The CCPx pin is set (exception: if PWM duty cycle = 0%, the CCPx pin will not be set) * The PWM duty cycle is latched from CCPRxL into CCPRxH Note: CCPxCON<5:4> Duty Cycle Registers PWM PERIOD CCPRxL The Timer2 and Timer 4 postscalers (see Section 14.0 "Timer2 Module" and Section 16.0 "Timer4 Module") are not used in the determination of the PWM frequency. The postscaler could be used to have a servo update rate at a different frequency than the PWM output. CCPRxH (Slave) CCPx Output R Comparator TMR2 (TMR4) 17.4.2 Q The PWM duty cycle is specified by writing to the CCPRxL register and to the CCPxCON<5:4> bits. Up to 10-bit resolution is available. The CCPRxL contains the eight MSbs and the CCPxCON<5:4> contains the two LSbs. This 10-bit value is represented by CCPRxL:CCPxCON<5:4>. The following equation is used to calculate the PWM duty cycle in time: (Note 1) S Comparator Clear Timer, CCPx pin and latch D.C. PR2 (PR4) Corresponding TRIS bit Note 1: The 8-bit TMR2 or TMR4 value is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler, to create the 10-bit time base. A PWM output (Figure 17-5) has a time base (period) and a time that the output stays high (duty cycle). The frequency of the PWM is the inverse of the period (1/period). FIGURE 17-5: PWM OUTPUT PWM DUTY CYCLE EQUATION 17-2: PWM Duty Cycle = (CCPRXL:CCPXCON<5:4>) * TOSC * (TMR2 Prescale Value) CCPRxL and CCPxCON<5:4> can be written to at any time, but the duty cycle value is not latched into CCPRxH until after a match between PR2 (PR4) and TMR2 (TMR4) occurs (i.e., the period is complete). In PWM mode, CCPRxH is a read-only register. Period Duty Cycle TMR2 (TMR4) = PR2 (PR4) TMR2 (TMR4) = Duty Cycle TMR2 (TMR4) = PR2 (TMR4) DS39646B-page 184 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY The CCPRxH register and a 2-bit internal latch are used to double-buffer the PWM duty cycle. This double-buffering is essential for glitchless PWM operation. When the CCPRxH and 2-bit latch match TMR2 (TMR4), concatenated with an internal 2-bit Q clock or 2 bits of the TMR2 (TMR4) prescaler, the CCPx pin is cleared. The maximum PWM resolution (bits) for a given PWM frequency is given by the equation: 17.4.3 The following steps should be taken when configuring the CCP module for PWM operation: 1. Set the PWM period by writing to the PR2 (PR4) register. Set the PWM duty cycle by writing to the CCPRxL register and CCPxCON<5:4> bits. Make the CCPx pin an output by clearing the appropriate TRIS bit. Set the TMR2 (TMR4) prescale value, then enable Timer2 (Timer4) by writing to T2CON (T4CON). Configure the CCPx module for PWM operation. 2. 3. 4. EQUATION 17-3: F OSC log --------------- F PWM PWM Resolution (max) = -----------------------------bits log ( 2 ) Note: SETUP FOR PWM OPERATION 5. If the PWM duty cycle value is longer than the PWM period, the CCPx pin will not be cleared. TABLE 17-3: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz PWM Frequency Timer Prescaler (1, 4, 16) PR2 Value Maximum Resolution (bits) 2004 Microchip Technology Inc. 2.44 kHz 9.77 kHz 39.06 kHz 156.25 kHz 312.50 kHz 416.67 kHz 16 4 1 1 1 1 FFh FFh FFh 3Fh 1Fh 17h 10 10 10 8 7 6.58 Preliminary DS39646B-page 185 PIC18F8722 FAMILY TABLE 17-4: Name INTCON REGISTERS ASSOCIATED WITH PWM, TIMER2 AND TIMER4 Bit 7 Bit 6 GIE/GIEH PEIE/GIEL Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 57 RCON IPEN SBOREN -- RI TO PD POR BOR 56 PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 60 PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 60 IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 60 PIR3 SSP2IF BCL2IF RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF 60 PIE3 SSP2IE BCL2IF RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE 60 SSP2IP BCL2IP RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP 60 IPR3 TMR2 Timer2 Register 58 PR2 Timer2 Period Register 58 T2CON -- T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 58 TMR4 Timer4 Register 61 PR4 Timer4 Period Register 61 T4CON -- T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0 61 CCPR1L Enhanced Capture/Compare/PWM Register 1 Low Byte 59 CCPR1H Enhanced Capture/Compare/PWM Register 1 High Byte 59 CCPR2L Enhanced Capture/Compare/PWM Register 2 Low Byte 59 CCPR2H Enhanced Capture/Compare/PWM Register 2 High Byte 59 CCP4CON -- -- DC4B1 DC4B0 CCP4M3 CCP4M2 CCP4M1 CCP4M0 61 CCP5CON -- -- DC5B1 DC5B0 CCP5M3 CCP5M2 CCP5M1 CCP5M0 61 Legend: -- = unimplemented, read as `0'. Shaded cells are not used by PWM, Timer2 or Timer4. DS39646B-page 186 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY 18.0 ENHANCED CAPTURE/ COMPARE/PWM (ECCP) MODULE The control register for the Enhanced CCP modules is shown in Register 18-1. It differs from the CCPxCON registers discussed in Section 17.0 "Capture/ Compare/PWM (CCP) Modules" in that the two Most Significant bits are implemented to control PWM functionality. In addition to the expanded range of modes available through the Enhanced CCPxCON register, the ECCP modules each have two additional features associated with Enhanced PWM operation and auto-shutdown features. They are: In the PIC18F8722 family of devices, ECCP1, ECCP2 and ECCP3 are implemented as a standard CCP module with Enhanced PWM capabilities. These include the provision for 2 or 4 output channels, user selectable polarity, dead-band control and automatic shutdown and restart. The enhanced features are discussed in detail in Section 18.4 "Enhanced PWM Mode". Capture, Compare and single-output PWM functions of the ECCP module are the same as described for the standard CCP module. REGISTER 18-1: * ECCPxDEL (Dead-Band Delay) * ECCPxAS (Auto-Shutdown Configuration) CCPxCON: ENHANCED CCPx CONTROL REGISTER (ECCP1, ECCP2, ECCP3) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PxM1 PxM0 DCxB1 DCxB0 CCPxM3 CCPxM2 CCPxM1 CCPxM0 bit 7 bit 7-6 bit 5-4 bit 3-0 bit 0 PxM1:PxM0: Enhanced PWM Output Configuration bits If CCPxM3:CCPxM2 = 00, 01, 10: xx = PxA assigned as Capture/Compare input/output; PxB, PxC, PxD assigned as port pins If CCPxM3:CCPxM2 = 11: 00 = Single output: PxA modulated; PxB, PxC, PxD assigned as port pins 01 = Full-bridge output forward: P1D modulated; P1A active; P1B, P1C inactive 10 = Half-bridge output: P1A, P1B modulated with dead-band control; P1C, P1D assigned as port pins 11 = Full-bridge output reverse: P1B modulated; P1C active; P1A, P1D inactive DCxB1:DCxB0: PWM Duty Cycle bit 1 and bit 0 Capture mode: Unused. Compare mode: Unused. PWM mode: These bits are the two LSbs of the 10-bit PWM duty cycle. The eight MSbs of the duty cycle are found in CCPRxL. CCPxM3:CCPxM0: Enhanced CCP Mode Select bits 0000 = Capture/Compare/PWM off (resets ECCPx module) 0001 = Reserved 0010 = Compare mode: toggle output on match 0011 = Capture mode 0100 = Capture mode: every falling edge 0101 = Capture mode: every rising edge 0110 = Capture mode: every 4th rising edge 0111 = Capture mode: every 16th rising edge 1000 = Compare mode: initialize ECCPx pin low; set output on compare match (set CCPxIF) 1001 = Compare mode: initialize ECCPx pin high; clear output on compare match (set CCPxIF) 1010 = Compare mode: generate software interrupt only; ECCPx pin reverts to I/O state 1011 = Compare mode: trigger special event (ECCP resets TMR1 or TMR3, sets CCPxIF bit; ECCP2 trigger starts A/D conversion if A/D module is enabled) 1100 = PWM mode: PxA, PxC active-high; PxB, PxD active-high 1101 = PWM mode: PxA, PxC active-high; PxB, PxD active-low 1110 = PWM mode: PxA, PxC active-low; PxB, PxD active-high 1111 = PWM mode: PxA, PxC active-low; PxB, PxD active-low Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared 2004 Microchip Technology Inc. Preliminary x = Bit is unknown DS39646B-page 187 PIC18F8722 FAMILY 18.1 ECCP Outputs and Configuration Each of the Enhanced CCP modules may have up to four PWM outputs, depending on the selected operating mode. These outputs, designated PxA through PxD, are multiplexed with various I/O pins. Some ECCPx pin assignments are constant, while others change based on device configuration. For those pins that do change, the controlling bits are: * CCP2MX configuration bit (CONFIG3H<0>) * ECCPMX configuration bit (CONFIG3H<1>) * Program memory mode (set by configuration bits, CONFIG3L<1:0>) The pin assignments for the Enhanced CCP modules are summarized in Table 18-1, Table 18-2 and Table 18-3. To configure the I/O pins as PWM outputs, the proper PWM mode must be selected by setting the PxMx and CCPxMx bits (CCPxCON<7:6> and <3:0>, respectively). The appropriate TRIS direction bits for the corresponding port pins must also be set as outputs. 18.1.1 USE OF CCP4 AND CCP5 WITH ECCP1 AND ECCP3 Only the ECCP2 module has four dedicated output pins available for use. Assuming that the I/O ports or other multiplexed functions on those pins are not needed, they may be used whenever needed without interfering with any other CCP module. ECCP1 and ECCP3, on the other hand, only have three dedicated output pins: ECCPx/P3A, PxB and PxC. Whenever these modules are configured for Quad PWM mode, the pin used for CCP4 or CCP5 takes priority over the D output pins for ECCP3 and ECCP1, respectively. DS39646B-page 188 18.1.2 ECCP MODULE OUTPUTS, PROGRAM MEMORY MODES AND EMB ADDRESS BUS WIDTH For PIC18F8527/8622/8627/8722 devices, the program memory mode of the device (Section 7.2 "Address and Data Width" and Section 7.4 "Program Memory Modes and the External Memory Bus") impacts both pin multiplexing and the operation of the module. The ECCP2 input/output (ECCP2/P2A) can be multiplexed to one of three pins. By default, this is RC1 for all devices; in this case, the default is in effect when CCP2MX is set and the device is operating in Microcontroller mode. With PIC18F8527/8622/8627/8722 devices, three other options exist. When CCP2MX is not set (= 0) and the device is in Microcontroller mode, ECCP2/P2A is multiplexed to RE7; in all other program memory modes, it is multiplexed to RB3. Another option is for ECCPMX to be set while the device is operating in one of the three other program memory modes. In this case, ECCP1 and ECCP3 operate as compatible (i.e., single output) CCP modules. The pins used by their other outputs (PxB through PxD) are available for other multiplexed functions. ECCP2 continues to operate as an Enhanced CCP module regardless of the program memory mode. The final option is that the ABW<1:0> configuration bits can be used to select 8, 12, 16 or 20-bit EMB addressing. Pins not assigned to EMB address pins are available for peripheral or port functions. Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY TABLE 18-1: PIN CONFIGURATIONS FOR ECCP1 ECCP Mode CCP1CON Configuration RC2 Compatible CCP 00xx 11xx ECCP1 RE6 RE5 Dual PWM 10xx 11xx P1A P1B Quad PWM x1xx 11xx P1A P1B RE6 RE5 RG4 RH7 RH6 RG4/CCP5 N/A N/A RE5 RG4/CCP5 N/A N/A P1C CCP5/P1D(1) N/A N/A PIC18F6527/6622/6627/6722 Devices: PIC18F8527/8622/8627/8722 Devices, ECCPMX = 1, Microcontroller mode: Compatible CCP 00xx 11xx ECCP1 RE6 RE5 RG4/CCP5 RH7/AN15 RH6/AN14 Dual PWM 10xx 11xx P1A P1B RE5 RG4/CCP5 RH7/AN15 RH6/AN14 P1C CCP5/P1D(1) RH7/AN15 RH6/AN14 Quad PWM x1xx 11xx P1A P1B PIC18F8527/8622/8627/8722 Devices, ECCPMX = 0, Microcontroller mode: Compatible CCP 00xx 11xx ECCP1 RE6 RE5 Dual PWM 10xx 11xx P1A RE6 RE5 Quad PWM x1xx 11xx P1A RE6 RE5 RG4/CCP5 RH7/AN15 RH6/AN14 RG4/CCP5 P1B RH6/AN14 CCP5/P1D(1) P1B P1C PIC18F8527/8622/8627/8722 Devices, ECCPMX = 1, all other Program Memory modes: Compatible CCP Dual PWM 00xx 11xx 10xx 11xx Quad PWM x1xx 11xx ECCP1 AD14(2) (2) P1A P1B/AD14 P1A P1B/AD14(2) AD13(2) RG4/CCP5 RH7/AN15 RH6/AN14 AD13(2) RG4/CCP5 RH7/AN15 RH6/AN14 P1C/AD13(2) CCP5/P1D(1) RH7/AN15 RH6/AN14 PIC18F8527/8622/8627/8722 Devices, ECCPMX = 0, all other Program Memory modes: Compatible CCP 00xx 11xx ECCP1 AD14(2) AD13(2) (2) (2) Dual PWM 10xx 11xx P1A AD14 Quad PWM x1xx 11xx P1A AD14(2) Legend: Note 1: 2: AD13 AD13(2) RG4/CCP5 RH7/AN15 RH6/AN14 RG4/CCP5 P1B RH6/AN14 CCP5/P1D(1) P1B P1C x = Don't care, N/A = Not available. Shaded cells indicate pin assignments not used by ECCP1 in a given mode. With ECCP1 in Quad PWM mode, the CCP5 module's output overrides P1D. The EMB address bus width will determine whether the pin will perform an EMB or port/peripheral function. 2004 Microchip Technology Inc. Preliminary DS39646B-page 189 PIC18F8722 FAMILY TABLE 18-2: PIN CONFIGURATIONS FOR ECCP2 CCP2CON Configuration ECCP Mode RB3 RC1 RE7 RE2 RE1 RE0 RE1 RE0 PIC18F6527/6622/6627/6722 Devices, CCP2MX = 1: Compatible CCP 00xx 11xx RB3/INT3 ECCP2 RE7 Dual PWM 10xx 11xx RB3/INT3 P2A RE7 P2B RE1 RE0 Quad PWM x1xx 11xx RB3/INT3 P2A RE7 P2B P2C P2D RE2 PIC18F6527/6622/6627/6722 Devices CCP2MX = 0: Compatible CCP 00xx 11xx RB3/INT3 RC1/T1OSI ECCP2 RE2 RE1 RE0 Dual PWM 10xx 11xx RB3/INT3 RC1/T1OSI P2A P2B RE1 RE0 Quad PWM x1xx 11xx RB3/INT3 RC1/T1OSI P2A P2B P2C P2D PIC18F8527/8622/8627/8722 Devices, CCP2MX = 1, Microcontroller mode: Compatible CCP 00xx 11xx RB3/INT3 ECCP2 RE7 RE2 RE1 RE0 Dual PWM 10xx 11xx RB3/INT3 P2A RE7 P2B RE1 RE0 Quad PWM x1xx 11xx RB3/INT3 P2A RE7 P2B P2C P2D PIC18F8527/8622/8627/8722 Devices, CCP2MX = 0, Microcontroller mode: Compatible CCP 00xx 11xx RB3/INT3 RC1/T1OSI ECCP2 RE2 RE1 RE0 Dual PWM 10xx 11xx RB3/INT3 RC1/T1OSI P2A P2B RE1 RE0 x1xx 11xx RB3/INT3 RC1/T1OSI P2A P2B P2C P2D Quad PWM PIC18F8527/8622/8627/8722 Devices, CCP2MX = 1, all other Program Memory modes: Compatible CCP 00xx 11xx RB3/INT3 ECCP2 AD15(1) AD10(1) AD9(1) AD8(1) Dual PWM 10xx 11xx RB3/INT3 P2A AD15(1) AD10/P2B(1) AD9(1) AD8(1) Quad PWM x1xx 11xx RB3/INT3 P2A AD15(1) AD10/P2B(1) AD9/P2C(1) P2D/AD8(1) PIC18F8527/8622/8627/8722 Devices, CCP2MX = 0, all other Program Memory modes: Compatible CCP 00xx 11xx ECCP2 RC1/T1OSI AD15(1) AD10(1) AD9(1) AD8(1) Dual PWM 10xx 11xx P2A RC1/T1OSI AD15(1) AD10/P2B(1) AD9(1) AD8(1) Quad PWM x1xx 11xx P2A RC1/T1OSI AD15(1) AD10/P2B(1) AD9/P2C(1) P2D/AD8(1) Legend: Note 1: x = Don't care. Shaded cells indicate pin assignments not used by ECCP2 in a given mode. The EMB address bus width will determine whether the pin will perform an EMB or port/peripheral function. DS39646B-page 190 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY TABLE 18-3: PIN CONFIGURATIONS FOR ECCP3 ECCP Mode CCP3CON Configuration RG0 Compatible CCP 00xx 11xx ECCP3 RE4 RE3 Dual PWM 10xx 11xx P3A P3B Quad PWM x1xx 11xx P3A P3B RE4 RE3 RG3 RH5 RH4 RG3/CCP4 N/A N/A RE3 RG3/CCP4 N/A N/A P3C CCP4/P3D(1) N/A N/A PIC18F6527/6622/6627/6722 Devices: PIC18F8527/8622/8627/8722 Devices, ECCPMX = 1, Microcontroller mode: Compatible CCP 00xx 11xx ECCP3 RE4 RE3 RG3/CCP4 RH5/AN13 RH4/AN12 Dual PWM 10xx 11xx P3A P3B RE3 RG3/CCP4 RH5/AN13 RH4/AN12 P3C CCP4/P3D(1) RH5/AN13 RH4/AN12 Quad PWM x1xx 11xx P3A P3B PIC18F8527/8622/8627/8722 Devices, ECCPMX = 0, Microcontroller mode: Compatible CCP 00xx 11xx ECCP3 RE4 RE3 RG3/CCP4 RH5/AN13 RH4/AN12 Dual PWM 10xx 11xx P3A RE4 Quad PWM x1xx 11xx P3A RE4 RE3 RG3/CCP4 P3B RH4/AN12 RE3 CCP4/P3D(1) P3B P3C PIC18F8527/8622/8627/8722 Devices, ECCPMX = 1, all other Program Memory modes: Compatible CCP Dual PWM 00xx 11xx 10xx 11xx Quad PWM x1xx 11xx ECCP3 AD12(2) (2) P3A AD12/P3B P3A AD12/P3B(2) AD10(2) RG3/CCP4 RH5/AN13 RH4/AN12 AD10(2) RG3/CCP4 RH5/AN13 RH4/AN12 P3C/AD10(1) CCP4/P3D(1) RH5/AN13 RH4/AN12 PIC18F8527/8622/8627/8722 Devices, ECCPMX = 0, all other Program Memory modes: Compatible CCP 00xx 11xx ECCP3 AD12(2) AD10(2) (2) (2) Dual PWM 10xx 11xx P3A AD12 Quad PWM x1xx 11xx P3A AD12(2) Legend: Note 1: 2: AD10 AD10(2) RG3/CCP4 RH5/AN13 RH4/AN12 RG3/CCP4 P3B RH4/AN12 CCP4/P3D(1) P3B P3C x = Don't care, N/A = Not available. Shaded cells indicate pin assignments not used by ECCP3 in a given mode. With ECCP3 in Quad PWM mode, the CCP4 module's output overrides P3D. The EMB address bus width will determine whether the pin will perform an EMB or port/peripheral function. 2004 Microchip Technology Inc. Preliminary DS39646B-page 191 PIC18F8722 FAMILY 18.1.3 ECCP MODULES AND TIMER RESOURCES Like the standard CCP modules, the ECCP modules can utilize Timers 1, 2, 3 or 4, depending on the mode selected. Timer1 and Timer3 are available for modules in Capture or Compare modes, while Timer2 and Timer4 are available for modules in PWM mode. Additional details on timer resources are provided in Section 17.1.1 "CCP Modules and Timer Resources". 18.2 Capture and Compare Modes With the exception of the special event trigger discussed below, the Capture and Compare modes of the ECCP modules are identical in operation to that of CCP4. These are discussed in detail in Section 17.2 "Capture Mode" and Section 17.3 "Compare Mode". 18.2.1 SPECIAL EVENT TRIGGER The special event trigger output of ECCPx resets the TMR1 or TMR3 register pair, depending on which timer resource is currently selected. This allows the CCPRx registers to effectively be 16-bit programmable period registers for Timer1 or Timer3. 18.3 Standard PWM Mode When configured in Single Output mode, the ECCP module functions identically to the standard CCP module in PWM mode as described in Section 17.4 "PWM Mode". This is also sometimes referred to as "Compatible CCP" mode as in Tables 18-1 through 18-3. Note: 18.4 When setting up single output PWM operations, users are free to use either of the processes described in Section 17.4.3 "Setup for PWM Operation" or Section 18.4.9 "Setup for PWM Operation". The latter is more generic, but will work for either single or multi-output PWM. For the sake of clarity, Enhanced PWM mode operation is described generically throughout this section with respect to ECCP1 and TMR2 modules. Control register names are presented in terms of ECCP1. All three Enhanced modules, as well as the two timer resources, can be used interchangeably and function identically. TMR2 or TMR4 can be selected for PWM operation by selecting the proper bits in T3CON. Figure 18-1 shows a simplified block diagram of PWM operation. All control registers are double-buffered and are loaded at the beginning of a new PWM cycle (the period boundary when Timer2 resets) in order to prevent glitches on any of the outputs. The exception is the PWM delay register, ECCP1DEL, which is loaded at either the duty cycle boundary or the boundary period (whichever comes first). Because of the buffering, the module waits until the assigned timer resets instead of starting immediately. This means that Enhanced PWM waveforms do not exactly match the standard PWM waveforms, but are instead offset by one full instruction cycle (4 TOSC). As before, the user must manually configure the appropriate TRIS bits for output. 18.4.1 EQUATION 18-1: PWM Period = [(PR2) + 1] * 4 * TOSC * (TMR2 Prescale Value) PWM frequency is defined as 1/[PWM period]. When TMR2 is equal to PR2, the following three events occur on the next increment cycle: * TMR2 is cleared * The ECCP1 pin is set (if PWM duty cycle = 0%, the ECCP1 pin will not be set) * The PWM duty cycle is copied from CCPR1L into CCPR1H Note: Enhanced PWM Mode The Enhanced PWM mode provides additional PWM output options for a broader range of control applications. The module is a backward compatible version of the standard CCP module and offers up to four outputs, designated PxA through PxD. Users are also able to select the polarity of the signal (either active-high or active-low). The module's output mode and polarity are configured by setting the PxM1:PxM0 and CCPxM3:CCPxM0 bits of the CCPxCON register (CCPxCON<7:6> and CCPxCON<3:0>, respectively). DS39646B-page 192 PWM PERIOD The PWM period is specified by writing to the PR2 register. The PWM period can be calculated using the following equation: Preliminary The Timer2 postscaler (see Section 14.0 "Timer2 Module") is not used in the determination of the PWM frequency. The postscaler could be used to have a servo update rate at a different frequency than the PWM output. 2004 Microchip Technology Inc. PIC18F8722 FAMILY FIGURE 18-1: SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODULE CCP1CON<5:4> Duty Cycle Registers CCP1M<3:0> 4 P1M1<1:0> 2 CCPR1L ECCP1/P1A ECCP1/P1A TRISx<x> CCPR1H (Slave) P1B R Comparator Output Controller Q P1B TRISx<x> P1C (Note 1) TMR2 P1C TRISx<x> S P1D Comparator Clear Timer, set ECCP1 pin and latch D.C. PR2 P1D TRISx<x> ECCP1DEL Note: The 8-bit TMR2 register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler, to create the 10-bit time base. 18.4.2 PWM DUTY CYCLE The PWM duty cycle is specified by writing to the CCPR1L register and to the CCP1CON<5:4> bits. Up to 10-bit resolution is available. The CCPR1L contains the eight MSbs and the CCP1CON<5:4> contains the two LSbs. This 10-bit value is represented by CCPR1L:CCP1CON<5:4>. The PWM duty cycle is calculated by the equation: EQUATION 18-3: EQUATION 18-2: PWM Duty Cycle = log FOSC FPWM PWM Resolution (max) = log(2) ( (CCPR1L:CCP1CON<5:4>) * TOSC * (TMR2 Prescale Value) CCPR1L and CCP1CON<5:4> can be written to at any time but the duty cycle value is not copied into CCPR1H until a match between PR2 and TMR2 occurs (i.e., the period is complete). In PWM mode, CCPR1H is a read-only register. TABLE 18-4: The CCPR1H register and a 2-bit internal latch are used to double-buffer the PWM duty cycle. This double-buffering is essential for glitchless PWM operation. When the CCPR1H and 2-bit latch match TMR2, concatenated with an internal 2-bit Q clock or two bits of the TMR2 prescaler, the ECCP1 pin is cleared. The maximum PWM resolution (bits) for a given PWM frequency is given by the equation: Note: ) bits If the PWM duty cycle value is longer than the PWM period, the ECCP1 pin will not be cleared. EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz PWM Frequency Timer Prescaler (1, 4, 16) PR2 Value Maximum Resolution (bits) 2004 Microchip Technology Inc. 2.44 kHz 9.77 kHz 39.06 kHz 156.25 kHz 312.50 kHz 416.67 kHz 16 4 1 1 1 1 FFh FFh FFh 3Fh 1Fh 17h 10 10 10 8 7 6.58 Preliminary DS39646B-page 193 PIC18F8722 FAMILY 18.4.3 PWM OUTPUT CONFIGURATIONS The Single Output mode is the standard PWM mode discussed in Section 18.4 "Enhanced PWM Mode". The Half-Bridge and Full-Bridge Output modes are covered in detail in the sections that follow. The P1M1:P1M0 bits in the CCP1CON register allow one of four configurations: * * * * Single Output Half-Bridge Output Full-Bridge Output, Forward mode Full-Bridge Output, Reverse mode FIGURE 18-2: The general relationship of the outputs in all configurations is summarized in Figure 18-2. PWM OUTPUT RELATIONSHIPS (ACTIVE-HIGH STATE) 0 CCP1CON<7:6> PR2 + 1 Duty Cycle SIGNAL Period 00 (Single Output) P1A Modulated Delay(1) Delay(1) P1A Modulated 10 (Half-Bridge) P1B Modulated P1A Active 01 (Full-Bridge, Forward) P1B Inactive P1C Inactive P1D Modulated P1A Inactive 11 (Full-Bridge, Reverse) P1B Modulated P1C Active P1D Inactive Relationships: * Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value) * Duty Cycle = TOSC * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value) * Delay = 4 * TOSC * (ECCP1DEL<6:0>) Note 1: Dead-band delay is programmed using the ECCP1DEL register (Section 18.4.6 "Programmable Dead-Band Delay"). DS39646B-page 194 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY FIGURE 18-3: PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE) 0 CCP1CON<7:6> PR2 + 1 Duty Cycle SIGNAL Period 00 (Single Output) P1A Modulated P1A Modulated 10 (Half-Bridge) Delay(1) Delay(1) P1B Modulated P1A Active 01 (Full-Bridge, Forward) P1B Inactive P1C Inactive P1D Modulated P1A Inactive 11 (Full-Bridge, Reverse) P1B Modulated P1C Active P1D Inactive Relationships: * Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value) * Duty Cycle = TOSC * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value) * Delay = 4 * TOSC * (ECCP1DEL<6:0>) Note 1: Dead-band delay is programmed using the ECCP1DEL register (Section 18.4.6 "Programmable Dead-Band Delay"). 2004 Microchip Technology Inc. Preliminary DS39646B-page 195 PIC18F8722 FAMILY 18.4.4 HALF-BRIDGE MODE The P1A and P1B outputs are multiplexed with the PORTC<2> and PORTE<6> data latches. Alternatively, P1B can be assigned to PORTH<7> by programming the ECCPMX configuration bit to `0'. See Table 18-1, Table 18-2 and Table 18-3 for more information. The associated TRIS bit must be cleared to configure P1A and P1B as outputs. In the Half-Bridge Output mode, two pins are used as outputs to drive push-pull loads. The PWM output signal is output on the P1A pin, while the complementary PWM output signal is output on the P1B pin (Figure 18-4). This mode can be used for half-bridge applications, as shown in Figure 18-5, or for full-bridge applications, where four power switches are being modulated with two PWM signals. FIGURE 18-4: In Half-Bridge Output mode, the programmable dead-band delay can be used to prevent shoot-through current in half-bridge power devices. The value of bits, P1DC6:P1DC0 sets the number of instruction cycles before the output is driven active. If the value is greater than the duty cycle, the corresponding output remains inactive during the entire cycle. See Section 18.4.6 "Programmable Dead-Band Delay" for more details on dead-band delay operations. HALF-BRIDGE PWM OUTPUT Period Period Duty Cycle P1A(2) td td P1B(2) (1) (1) (1) td = Dead Band Delay Note 1: At this time, the TMR2 register is equal to the PR2 register. 2: Output signals are shown as active-high. FIGURE 18-5: EXAMPLES OF HALF-BRIDGE OUTPUT MODE APPLICATIONS Standard Half-Bridge Circuit ("Push-Pull") V+ PIC18F6X27/6X22/8X27/8X22 FET Driver + V - P1A Load FET Driver + V - P1B VHalf-Bridge Output Driving a Full-Bridge Circuit V+ PIC18F6X27/6X22/8X27/8X22 FET Driver FET Driver P1A FET Driver Load FET Driver P1B V- DS39646B-page 196 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY 18.4.5 FULL-BRIDGE MODE In Full-Bridge Output mode, four pins are used as outputs; however, only two outputs are active at a time. In the Forward mode, pin P1A is continuously active and pin P1D is modulated. In the Reverse mode, pin P1C is continuously active and pin P1B is modulated. These are illustrated in Figure 18-6. FIGURE 18-6: P1A, P1B, P1C and P1D outputs are multiplexed with the PORTC<2>, PORTE<6:5> and PORTG<4> data latches. Alternatively, P1B and P1C can be assigned to PORTH<7> and PORTH<6>, respectively, by programming the ECCPMX configuration bit to `0'. See Table 18-1, Table 18-2 and Table 18-3 for more information. The associated bits must be cleared to make the P1A, P1B, P1C and P1D pins outputs. FULL-BRIDGE PWM OUTPUT Forward Mode Period P1A(2) Duty Cycle P1B(2) P1C(2) P1D(2) (1) (1) Reverse Mode Period Duty Cycle P1A(2) P1B(2) P1C(2) P1D(2) (1) (1) Note 1: At this time, the TMR2 register is equal to the PR2 register. Note 2: Output signal is shown as active-high. 2004 Microchip Technology Inc. Preliminary DS39646B-page 197 PIC18F8722 FAMILY FIGURE 18-7: EXAMPLE OF FULL-BRIDGE APPLICATION V+ PIC18F6X27/6X22/8X27/8X22 FET Driver QC QA FET Driver P1A Load P1B FET Driver P1C FET Driver QD QB VP1D 18.4.5.1 Direction Change in Full-Bridge Mode In the Full-Bridge Output mode, the P1M1 bit in the CCP1CON register allows users to control the forward/ reverse direction. When the application firmware changes this direction control bit, the module will assume the new direction on the next PWM cycle. Just before the end of the current PWM period, the modulated outputs (P1B and P1D) are placed in their inactive state, while the unmodulated outputs (P1A and P1C) are switched to drive in the opposite direction. This occurs in a time interval of (4 TOSC * (Timer2 Prescale Value)) before the next PWM period begins. The Timer2 prescaler will be either 1, 4 or 16, depending on the value of the T2CKPSx bit (T2CON<1:0>). During the interval from the switch of the unmodulated outputs to the beginning of the next period, the modulated outputs (P1B and P1D) remain inactive. This relationship is shown in Figure 18-8. Note that in the Full-Bridge Output mode, the ECCP1 module does not provide any dead-band delay. In general, since only one output is modulated at all times, dead-band delay is not required. However, there is a situation where a dead-band delay might be required. This situation occurs when both of the following conditions are true: 1. 2. Figure 18-9 shows an example where the PWM direction changes from forward to reverse at a near 100% duty cycle. At time t1, the outputs P1A and P1D become inactive, while output P1C becomes active. In this example, since the turn-off time of the power devices is longer than the turn-on time, a shoot-through current may flow through power devices QC and QD (see Figure 18-7) for the duration of `t'. The same phenomenon will occur to power devices QA and QB for PWM direction change from reverse to forward. If changing PWM direction at high duty cycle is required for an application, one of the following requirements must be met: 1. 2. Reduce PWM for a PWM period before changing directions. Use switch drivers that can drive the switches off faster than they can drive them on. Other options to prevent shoot-through current may exist. The direction of the PWM output changes when the duty cycle of the output is at or near 100%. The turn-off time of the power switch, including the power device and driver circuit, is greater than the turn-on time. DS39646B-page 198 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY FIGURE 18-8: PWM DIRECTION CHANGE Period(1) SIGNAL Period P1A (Active-High) P1B (Active-High) DC P1C (Active-High) (Note 2) P1D (Active-High) DC Note 1: The direction bit in the ECCP1 Control register (CCP1CON<7>) is written any time during the PWM cycle. 2: When changing directions, the P1A and P1C signals switch before the end of the current PWM cycle at intervals of 4 TOSC, 16 TOSC or 64 TOSC, depending on the Timer2 prescaler value. The modulated P1B and P1D signals are inactive at this time. FIGURE 18-9: PWM DIRECTION CHANGE AT NEAR 100% DUTY CYCLE(1) Forward Period t1 Reverse Period P1A P1B DC P1C P1D DC tON(2) External Switch C tOFF(3) External Switch D Potential Shoot-Through Current t = tOFF - tON Note 1: All signals are shown as active-high. 2: tON is the turn-on delay of power switch QC and its driver. 3: tOFF is the turn-off delay of power switch QD and its driver. 2004 Microchip Technology Inc. Preliminary DS39646B-page 199 PIC18F8722 FAMILY 18.4.6 PROGRAMMABLE DEAD-BAND DELAY In half-bridge applications where all power switches are modulated at the PWM frequency at all times, the power switches normally require more time to turn off than to turn on. If both the upper and lower power switches are switched at the same time (one turned on and the other turned off), both switches may be on for a short period of time until one switch completely turns off. During this brief interval, a very high current (shoot-through current) may flow through both power switches, shorting the bridge supply. To avoid this potentially destructive shoot-through current from flowing during switching, turning on either of the power switches is normally delayed to allow the other switch to completely turn off. In the Half-Bridge Output mode, a digitally programmable dead-band delay is available to avoid shoot-through current from destroying the bridge power switches. The delay occurs at the signal transition from the non-active state to the active state. See Figure 18-4 for illustration. The lower seven bits of the ECCP1DEL register (Register 18-2) set the delay period in terms of microcontroller instruction cycles (TCY or 4 TOSC). 18.4.7 ENHANCED PWM AUTO-SHUTDOWN When the ECCP is programmed for any of the Enhanced PWM modes, the active output pins may be configured for auto-shutdown. Auto-shutdown immediately places the Enhanced PWM output pins into a defined shutdown state when a shutdown event occurs. REGISTER 18-2: A shutdown event can be caused by either of the two comparator modules or the FLT0 pin (or any combination of these three sources). The comparators may be used to monitor a voltage input proportional to a current being monitored in the bridge circuit. If the voltage exceeds a threshold, the comparator switches state and triggers a shutdown. Alternatively, a digital signal on the FLT0 pin can also trigger a shutdown. The auto-shutdown feature can be disabled by not selecting any auto-shutdown sources. The auto-shutdown sources to be used are selected using the ECCP1AS2:ECCP1AS0 bits (ECCP1AS<6:4>). When a shutdown occurs, the output pins are asynchronously placed in their shutdown states, specified by the PSS1AC1:PSS1AC0 and PSS1BD1:PSS1BD0 bits (ECCP1AS<3:0>). Each pin pair (P1A/P1C and P1B/P1D) may be set to drive high, drive low or be tri-stated (not driving). The ECCP1ASE bit (ECCP1AS<7>) is also set to hold the Enhanced PWM outputs in their shutdown states. The ECCP1ASE bit is set by hardware when a shutdown event occurs. If automatic restarts are not enabled, the ECCP1ASE bit is cleared by firmware when the cause of the shutdown clears. If automatic restarts are enabled, the ECCP1ASE bit is automatically cleared when the cause of the auto-shutdown has cleared. If the ECCP1ASE bit is set when a PWM period begins, the PWM outputs remain in their shutdown state for that entire PWM period. When the ECCP1ASE bit is cleared, the PWM outputs will return to normal operation at the beginning of the next PWM period. Note: Writing to the ECCP1ASE bit is disabled while a shutdown condition is active. ECCPxDEL: ENHANCED PWM CONFIGURATION REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PxRSEN PxDC6 PxDC5 PxDC4 PxDC3 PxDC2 PxDC1 PxDC0 bit 7 bit 0 bit 7 PxRSEN: PWM Restart Enable bit 1 = Upon auto-shutdown, the ECCPxASE bit clears automatically once the shutdown event goes away; the PWM restarts automatically 0 = Upon auto-shutdown, the ECCPxASE bit must be cleared in software to restart the PWM bit 6-0 PxDC6:PxDC0: PWM Delay Count bits Delay time, in number of FOSC/4 (4 * TOSC) cycles, between the scheduled and actual time for a PWM signal to transition to active. Legend: DS39646B-page 200 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared Preliminary x = Bit is unknown 2004 Microchip Technology Inc. PIC18F8722 FAMILY REGISTER 18-3: ECCPxAS: ENHANCED CCP AUTO-SHUTDOWN CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ECCPxASE ECCPxAS2 ECCPxAS1 ECCPxAS0 PSSxAC1 PSSxAC0 PSSxBD1 PSSxBD0 bit 7 bit 0 bit 7 ECCPxASE: ECCP Auto-Shutdown Event Status bit 0 = ECCP outputs are operating 1 = A shutdown event has occurred; ECCP outputs are in shutdown state bit 6-4 ECCPxAS2:ECCPxAS0: ECCP Auto-Shutdown Source Select bits 000 = Auto-shutdown is disabled 001 = Comparator 1 output 010 = Comparator 2 output 011 = Either Comparator 1 or 2 100 = FLT0 101 = FLT0 or Comparator 1 110 = FLT0 or Comparator 2 111 = FLT0 or Comparator 1 or Comparator 2 bit 3-2 PSSxAC1:PSSxAC0: Pins A and C Shutdown State Control bits 00 = Drive pins A and C to `0' 01 = Drive pins A and C to `1' 1x = Pins A and C tri-state bit 1-0 PSSxBD1:PSSxBD0: Pins B and D Shutdown State Control bits 00 = Drive pins B and D to `0' 01 = Drive pins B and D to `1' 1x = Pins B and D tri-state Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared 2004 Microchip Technology Inc. Preliminary x = Bit is unknown DS39646B-page 201 PIC18F8722 FAMILY 18.4.7.1 Auto-Shutdown and Automatic Restart 18.4.8 The Auto-Shutdown feature can be configured to allow automatic restarts of the module following a shutdown event. This is enabled by setting the P1RSEN bit of the ECCP1DEL register (ECCP1DEL<7>). In Shutdown mode with P1RSEN = 1 (Figure 18-10), the ECCP1ASE bit will remain set for as long as the cause of the shutdown continues. When the shutdown condition clears, the ECCP1ASE bit is cleared. If P1RSEN = 0 (Figure 18-11), once a shutdown condition occurs, the ECCP1ASE bit will remain set until it is cleared by firmware. Once ECCP1ASE is cleared, the Enhanced PWM will resume at the beginning of the next PWM period. Note: Writing to the ECCP1ASE bit is disabled while a shutdown condition is active. Independent of the P1RSEN bit setting, if the auto-shutdown source is one of the comparators, the shutdown condition is a level. The ECCP1ASE bit cannot be cleared as long as the cause of the shutdown persists. The Auto-Shutdown mode can be forced by writing a `1' to the ECCP1ASE bit. FIGURE 18-10: START-UP CONSIDERATIONS When the ECCP module is used in the PWM mode, the application hardware must use the proper external pull-up and/or pull-down resistors on the PWM output pins. When the microcontroller is released from Reset, all of the I/O pins are in the high-impedance state. The external circuits must keep the power switch devices in the OFF state until the microcontroller drives the I/O pins with the proper signal levels or activates the PWM output(s). The CCP1M1:CCP1M0 bits (CCP1CON<1:0>) allow the user to choose whether the PWM output signals are active-high or active-low for each pair of PWM output pins (P1A/P1C and P1B/P1D). The PWM output polarities must be selected before the PWM pins are configured as outputs. Changing the polarity configuration while the PWM pins are configured as outputs is not recommended since it may result in damage to the application circuits. The P1A, P1B, P1C and P1D output latches may not be in the proper states when the PWM module is initialized. Enabling the PWM pins for output at the same time as the ECCP1 module may cause damage to the application circuit. The ECCP1 module must be enabled in the proper output mode and complete a full PWM cycle before configuring the PWM pins as outputs. The completion of a full PWM cycle is indicated by the TMR2IF bit being set as the second PWM period begins. PWM AUTO-SHUTDOWN (P1RSEN = 1, AUTO-RESTART ENABLED) PWM Period Shutdown Event ECCP1ASE bit PWM Activity Normal PWM Start of PWM Period FIGURE 18-11: Shutdown Shutdown Event Occurs Event Clears PWM Resumes PWM AUTO-SHUTDOWN (P1RSEN = 0, AUTO-RESTART DISABLED) PWM Period Shutdown Event ECCP1ASE bit PWM Activity Normal PWM Start of PWM Period DS39646B-page 202 ECCP1ASE Cleared by Shutdown Shutdown Firmware PWM Event Occurs Event Clears Resumes Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY 18.4.9 SETUP FOR PWM OPERATION 18.4.10 The following steps should be taken when configuring the ECCP1 module for PWM operation using Timer2: 1. Configure the PWM pins, P1A and P1B (and P1C and P1D, if used), as inputs by setting the corresponding TRIS bits. 2. Set the PWM period by loading the PR2 register. 3. If auto-shutdown is required do the following: * Disable auto-shutdown (ECCP1AS = 0) * Configure source (FLT0, Comparator 1 or Comparator 2) * Wait for non-shutdown condition 4. Configure the ECCP1 module for the desired PWM mode and configuration by loading the CCP1CON register with the appropriate values: * Select one of the available output configurations and direction with the P1M1:P1M0 bits. * Select the polarities of the PWM output signals with the CCP1M3:CCP1M0 bits. 5. Set the PWM duty cycle by loading the CCPR1L register and CCP1CON<5:4> bits. 6. For Half-Bridge Output mode, set the dead-band delay by loading ECCP1DEL<6:0> with the appropriate value. 7. If auto-shutdown operation is required, load the ECCP1AS register: * Select the auto-shutdown sources using the ECCP1AS2:ECCP1AS0 bits. * Select the shutdown states of the PWM output pins using the PSS1AC1:PSS1AC0 and PSS1BD1:PSS1BD0 bits. * Set the ECCP1ASE bit (ECCP1AS<7>). * Configure the comparators using the CMCON register. * Configure the comparator inputs as analog inputs. 8. If auto-restart operation is required, set the P1RSEN bit (ECCP1DEL<7>). 9. Configure and start TMR2: * Clear the TMR2 interrupt flag bit by clearing the TMR2IF bit (PIR1<1>). * Set the TMR2 prescale value by loading the T2CKPS bits (T2CON<1:0>). * Enable Timer2 by setting the TMR2ON bit (T2CON<2>). 10. Enable PWM outputs after a new PWM cycle has started: * Wait until TMRn overflows (TMRnIF bit is set). * Enable the ECCP1/P1A, P1B, P1C and/or P1D pin outputs by clearing the respective TRIS bits. * Clear the ECCP1ASE bit (ECCP1AS<7>). 2004 Microchip Technology Inc. OPERATION IN POWER-MANAGED MODES In Sleep mode, all clock sources are disabled. Timer2 or Timer4 will not increment and the state of the module will not change. If the ECCP1 pin is driving a value, it will continue to drive that value. When the device wakes up, it will continue from this state. If Two-Speed Start-ups are enabled, the initial start-up frequency from INTOSC and the postscaler may not be stable immediately. In PRI_IDLE mode, the primary clock will continue to clock the ECCP1 module without change. In all other power-managed modes, the selected power-managed mode clock will clock Timer2 or Timer4. Other power-managed mode clocks will most likely be different than the primary clock frequency. 18.4.10.1 Operation with Fail-Safe Clock Monitor If the Fail-Safe Clock Monitor is enabled, a clock failure will force the device into the power-managed RC_RUN mode and the OSCFIF bit (PIR2<7>) will be set. The ECCP1 will then be clocked from the internal oscillator clock source, which may have a different clock frequency than the primary clock. See the previous section for additional details. 18.4.11 EFFECTS OF A RESET Both Power-on Reset and subsequent Resets will force all ports to Input mode and the CCP registers to their Reset states. This forces the Enhanced CCP module to reset to a state compatible with the standard CCP module. Preliminary DS39646B-page 203 PIC18F8722 FAMILY TABLE 18-5: Name INTCON RCON REGISTERS ASSOCIATED WITH ECCP MODULES AND TIMER1 TO TIMER4 Reset Values on page Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 57 IPEN SBOREN -- RI TO PD POR BOR 58 PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 60 PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 60 IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 60 PIR2 OSCFIF CMIF -- EEIF BCL1IF HLVDIF TMR3IF CCP2IF 60 PIE2 OSCFIE CMIE -- EEIE BCL1IE HLVDIE TMR3IE CCP2IE 60 IPR2 OSCFIP CMIP -- EEIP BCL1IP HLVDIP TMR3IP CCP2IP 60 PIR3 SSP2IF BCL2IF RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF 60 PIE3 SSP2IE BCL2IE RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE 60 IPR3 SSP2IP BCL2IP RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP 60 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 60 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 60 TRISE TRISE7 TRISE6 TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 TRISE0 60 TRISG -- -- -- TRISG4 TRISG3 TRISG2 TRISG1 TRISG0 60 TRISH7 TRISH6 TRISH5 TRISH4 TRISH3 TRISH2 TRISH1 TRISH0 60 TRISH(2) TMR1L Timer1 Register Low Byte 58 TMR1H Timer1 Register High Byte 58 T1CON RD16 TMR2 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON Timer2 Register -- T2CON 58 58 T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 58 PR2 Timer2 Period Register 58 TMR3L Timer3 Register Low Byte 59 TMR3H Timer3 Register High Byte RD16 T3CON TMR4 T3CCP2 59 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 59 T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0 61 Timer4 Register -- T4CON PR4 61 Timer4 Period Register 61 (1) CCPRxL Enhanced Capture/Compare/PWM Register x Low Byte 59, 61 CCPRxH(1) Enhanced Capture/Compare/PWM Register x High Byte 59, 61 CCPxCON(1) ECCPxAS(1) ECCPxDEL(1) Legend: Note 1: 2: PxM1 PxM0 DCxB1 DCxB0 ECCPxASE ECCPxAS2 ECCPxAS1 ECCPxAS0 PxRSEN PxDC6 PxDC5 PxDC4 CCPxM3 CCPxM2 CCPxM1 CCPxM0 PSSxAC1 PSSxAC0 PSSxBD1 PSSxBD0 PxDC3 PxDC2 PxDC1 PxDC0 59 59, 61 61 -- = unimplemented, read as `0'. Shaded cells are not used during ECCP operation. Generic term for all of the identical registers of this name for all Enhanced CCP modules, where `x' identifies the individual module (ECCP1, ECCP2 or ECCP3). Bit assignments and Reset values for all registers of the same generic name are identical. This register is not implemented on PIC18F6527/6622/6627/6722 devices. DS39646B-page 204 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY 19.0 19.1 MASTER SYNCHRONOUS SERIAL PORT (MSSP) MODULE 19.3 SPI Mode The SPI mode allows 8 bits of data to be synchronously transmitted and received simultaneously. All four modes of SPI are supported. To accomplish communication, typically three pins are used: Master SSP (MSSP) Module Overview The Master Synchronous Serial Port (MSSP) module is a serial interface, useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be serial EEPROMs, shift registers, display drivers, A/D converters, etc. The MSSP module can operate in one of two modes: * Serial Peripheral Interface (SPITM) * Inter-Integrated Circuit (I2CTM) - Full Master mode - Slave mode (with general address call) * Serial Data Out (SDOx) - RC5/SDO1 or RD4/SDO2 * Serial Data In (SDIx) - RC4/SDI1/SDA1 or RD5/SDI2/SDA2 * Serial Clock (SCKx) - RC3/SCK1/SCL1 or RD6/SCK2/SCL2 Additionally, a fourth pin may be used when in a Slave mode of operation: * Slave Select (SSx) - RF7/SS1 or RD7/SS2 Figure 19-1 shows the block diagram of the MSSP module when operating in SPI mode. The I2C interface supports the following modes in hardware: FIGURE 19-1: * Master mode * Multi-Master mode * Slave mode Internal Data Bus Read All members of the PIC18F8722 family have two MSSP modules, designated as MSSP1 and MSSP2. Each module operates independently of the other. Note: 19.2 Throughout this section, generic references to an MSSP module in any of its operating modes may be interpreted as being equally applicable to MSSP1 or MSSP2. Register names and module I/O signals use the generic designator `x' to indicate the use of a numeral to distinguish a particular module when required. Control bit names are not individuated. RC4 or RD5 SSPxSR reg RC5 or RD4 RF7 or RD7 Control Registers Additional details are provided under the individual sections. In devices with more than one MSSP module, it is very important to pay close attention to SSPCON register names. SSP1CON1 and SSP1CON2 control different operational aspects of the same module, while SSP1CON1 and SSP2CON1 control the same features for two different modules. 2004 Microchip Technology Inc. Write SSPxBUF reg Shift Clock bit 0 SSx Control Enable Edge Select Each MSSP module has three associated control registers. These include a status register (SSPxSTAT) and two control registers (SSPxCON1 and SSPxCON2). The use of these registers and their individual configuration bits differ significantly depending on whether the MSSP module is operated in SPI or I2C mode. Note: MSSP BLOCK DIAGRAM (SPITM MODE) 2 Clock Select RC3 or RD6 SSPM3:SSPM0 SMP:CKE 4 TMR2 Output 2 2 Edge Select Prescaler TOSC 4, 16, 64 ( ) Data to TXx/RXx in SSPxSR TRIS bit Note: Preliminary Only port I/O names are used in this diagram for the sake of brevity. Refer to the text for a full list of multiplexed functions. DS39646B-page 205 PIC18F8722 FAMILY 19.3.1 REGISTERS Each MSSP module has four registers for SPI mode operation. These are: SSPxSR is the shift register used for shifting data in or out. SSPxBUF is the buffer register to which data bytes are written to or read from. In receive operations, SSPxSR and SSPxBUF together create a double-buffered receiver. When SSPxSR receives a complete byte, it is transferred to SSPxBUF and the SSPxIF interrupt is set. * MSSP Control Register 1 (SSPxCON1) * MSSP Status Register (SSPxSTAT) * Serial Receive/Transmit Buffer Register (SSPxBUF) * MSSP Shift Register (SSPxSR) - Not directly accessible During transmission, the SSPxBUF is not double-buffered. A write to SSPxBUF will write to both SSPxBUF and SSPxSR. SSPxCON1 and SSPxSTAT are the control and status registers in SPI mode operation. The SSPxCON1 register is readable and writable. The lower 6 bits of the SSPxSTAT are read-only. The upper two bits of the SSPxSTAT are read/write. REGISTER 19-1: SSPxSTAT: MSSPx STATUS REGISTER (SPITM MODE) R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 SMP CKE D/A P S R/W UA BF bit 7 bit 0 bit 7 SMP: Sample bit SPI Master mode: 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time SPI Slave mode: SMP must be cleared when SPI is used in Slave mode. bit 6 CKE: SPI Clock Select bit 1 = Transmit occurs on transition from active to Idle clock state 0 = Transmit occurs on transition from Idle to active clock state Note: Polarity of clock state is set by the CKP bit (SSPxCON1<4>). bit 5 D/A: Data/Address bit Used in I2C mode only. bit 4 P: Stop bit Used in I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared. bit 3 S: Start bit Used in I2C mode only. bit 2 R/W: Read/Write Information bit Used in I2C mode only. bit 1 UA: Update Address bit Used in I2C mode only. bit 0 BF: Buffer Full Status bit (Receive mode only) 1 = Receive complete, SSPxBUF is full 0 = Receive not complete, SSPxBUF is empty Legend: DS39646B-page 206 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared Preliminary x = Bit is unknown 2004 Microchip Technology Inc. PIC18F8722 FAMILY REGISTER 19-2: SSPxCON1: MSSPx CONTROL REGISTER 1 (SPITM MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 bit 7 bit 0 bit 7 WCOL: Write Collision Detect bit 1 = The SSPxBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision bit 6 SSPOV: Receive Overflow Indicator bit SPI Slave mode: 1 = A new byte is received while the SSPxBUF register is still holding the previous data. In case of overflow, the data in SSPxSR is lost. Overflow can only occur in Slave mode. The user must read the SSPxBUF, even if only transmitting data, to avoid setting overflow (must be cleared in software). 0 = No overflow Note: bit 5 In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPxBUF register. SSPEN: Synchronous Serial Port Enable bit 1 = Enables serial port and configures SCKx, SDOx, SDIx and SSx as serial port pins 0 = Disables serial port and configures these pins as I/O port pins Note: When enabled, these pins must be properly configured as input or output. bit 4 CKP: Clock Polarity Select bit 1 = Idle state for clock is a high level 0 = Idle state for clock is a low level bit 3-0 SSPM3:SSPM0: Synchronous Serial Port Mode Select bits 0101 = SPI Slave mode, clock = SCKx pin, SSx pin control disabled, SSx can be used as I/O pin 0100 = SPI Slave mode, clock = SCKx pin, SSx pin control enabled 0011 = SPI Master mode, clock = TMR2 output/2 0010 = SPI Master mode, clock = FOSC/64 0001 = SPI Master mode, clock = FOSC/16 0000 = SPI Master mode, clock = FOSC/4 Note: Bit combinations not specifically listed here are either reserved or implemented in I2C mode only. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared 2004 Microchip Technology Inc. Preliminary x = Bit is unknown DS39646B-page 207 PIC18F8722 FAMILY 19.3.2 OPERATION When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits (SSPxCON1<5:0> and SSPxSTAT<7:6>). These control bits allow the following to be specified: * * * * Master mode (SCKx is the clock output) Slave mode (SCKx is the clock input) Clock Polarity (Idle state of SCKx) Data Input Sample Phase (middle or end of data output time) * Clock Edge (output data on rising/falling edge of SCKx) * Clock Rate (Master mode only) * Slave Select mode (Slave mode only) Each MSSP module consists of a transmit/receive shift register (SSPxSR) and a buffer register (SSPxBUF). The SSPxSR shifts the data in and out of the device, MSb first. The SSPxBUF holds the data that was written to the SSPxSR until the received data is ready. Once the 8 bits of data have been received, that byte is moved to the SSPxBUF register. Then, the Buffer Full detect bit, BF (SSPxSTAT<0>) and the interrupt flag bit, SSPxIF, are set. This double-buffering of the received data (SSPxBUF) allows the next byte to start reception EXAMPLE 19-1: LOOP before reading the data that was just received. Any write to the SSPxBUF register during transmission/reception of data will be ignored and the Write Collision Detect bit, WCOL (SSPxCON1<7>), will be set. User software must clear the WCOL bit so that it can be determined if the following write(s) to the SSPxBUF register completed successfully. When the application software is expecting to receive valid data, the SSPxBUF should be read before the next byte of data to transfer is written to the SSPxBUF. The Buffer Full bit, BF (SSPxSTAT<0>), indicates when SSPxBUF has been loaded with the received data (transmission is complete). When the SSPxBUF is read, the BF bit is cleared. This data may be irrelevant if the SPI is only a transmitter. Generally, the MSSP interrupt is used to determine when the transmission/reception has completed. If the interrupt method is not going to be used, then software polling can be done to ensure that a write collision does not occur. Example 19-1 shows the loading of the SSPxBUF (SSPxSR) for data transmission. The SSPxSR is not directly readable or writable and can only be accessed by addressing the SSPxBUF register. Additionally, the SSPxSTAT register indicates the various status conditions. LOADING THE SSP1BUF (SSP1SR) REGISTER BTFSS BRA MOVF SSP1STAT, BF LOOP SSP1BUF, W ;Has data been received (transmit complete)? ;No ;WREG reg = contents of SSP1BUF MOVWF RXDATA ;Save in user RAM, if data is meaningful MOVF MOVWF TXDATA, W SSP1BUF ;W reg = contents of TXDATA ;New data to xmit DS39646B-page 208 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY 19.3.3 ENABLING SPI I/O To enable the serial port, SSP Enable bit, SSPEN (SSPxCON1<5>), must be set. To reset or reconfigure SPI mode, clear the SSPEN bit, reinitialize the SSPxCON registers and then set the SSPEN bit. This configures the SDIx, SDOx, SCKx and SSx pins as serial port pins. For the pins to behave as the serial port function, some must have their data direction bits (in the TRIS register) appropriately programmed as follows: * SDIx is automatically controlled by the SPI module * SDOx must have the TRISC<5> or TRISD<4> bit cleared * SCKx (Master mode) must have the TRISC<3> or TRISD<6>bit cleared * SCKx (Slave mode) must have the TRISC<3> or TRISD<6> bit set * SSx must have the TRISF<7> or TRISD<7> bit set FIGURE 19-2: Any serial port function that is not desired may be overridden by programming the corresponding data direction (TRIS) register to the opposite value. 19.3.4 TYPICAL CONNECTION Figure 19-2 shows a typical connection between two microcontrollers. The master controller (Processor 1) initiates the data transfer by sending the SCKx signal. Data is shifted out of both shift registers on their programmed clock edge and latched on the opposite edge of the clock. Both processors should be programmed to the same Clock Polarity (CKP), then both controllers would send and receive data at the same time. Whether the data is meaningful (or dummy data) depends on the application software. This leads to three scenarios for data transmission: * Master sends data - Slave sends dummy data * Master sends data - Slave sends data * Master sends dummy data - Slave sends data SPITM MASTER/SLAVE CONNECTION SPITM Master SSPM3:SSPM0 = 00xxb SPITM Slave SSPM3:SSPM0 = 010xb SDOx SDIx Serial Input Buffer (SSPxBUF) SDIx Shift Register (SSPxSR) MSb Serial Input Buffer (SSPxBUF) SDOx LSb MSb SCKx Serial Clock PROCESSOR 1 2004 Microchip Technology Inc. Shift Register (SSPxSR) LSb SCKx PROCESSOR 2 Preliminary DS39646B-page 209 PIC18F8722 FAMILY 19.3.5 MASTER MODE The master can initiate the data transfer at any time because it controls the SCKx. The master determines when the slave (Processor 1, Figure 19-2) is to broadcast data by the software protocol. In Master mode, the data is transmitted/received as soon as the SSPxBUF register is written to. If the SPI is only going to receive, the SDOx output could be disabled (programmed as an input). The SSPxSR register will continue to shift in the signal present on the SDIx pin at the programmed clock rate. As each byte is received, it will be loaded into the SSPxBUF register as if a normal received byte (interrupts and status bits appropriately set). This could be useful in receiver applications as a "Line Activity Monitor" mode. The clock polarity is selected by appropriately programming the CKP bit (SSPxCON1<4>). This then, would give waveforms for SPI communication as FIGURE 19-3: shown in Figure 19-3, Figure 19-5 and Figure 19-6, where the MSB is transmitted first. In Master mode, the SPI clock rate (bit rate) is user programmable to be one of the following: * * * * FOSC/4 (or TCY) FOSC/16 (or 4 * TCY) FOSC/64 (or 16 * TCY) Timer2 output/2 This allows a maximum data rate (at 40 MHz) of 10.00 Mbps. Figure 19-3 shows the waveforms for Master mode. When the CKE bit is set, the SDOx data is valid before there is a clock edge on SCKx. The change of the input sample is shown based on the state of the SMP bit. The time when the SSPxBUF is loaded with the received data is shown. SPITM MODE WAVEFORM (MASTER MODE) Write to SSPxBUF SCKx (CKP = 0 CKE = 0) SCKx (CKP = 1 CKE = 0) 4 Clock Modes SCKx (CKP = 0 CKE = 1) SCKx (CKP = 1 CKE = 1) SDOx (CKE = 0) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDOx (CKE = 1) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDIx (SMP = 0) bit 0 bit 7 Input Sample (SMP = 0) SDIx (SMP = 1) bit 0 bit 7 Input Sample (SMP = 1) SSPxIF Next Q4 Cycle after Q2 SSPxSR to SSPxBUF DS39646B-page 210 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY 19.3.6 SLAVE MODE In Slave mode, the data is transmitted and received as the external clock pulses appear on SCKx. When the last bit is latched, the SSPxIF interrupt flag bit is set. While in Slave mode, the external clock is supplied by the external clock source on the SCKx pin. This external clock must meet the minimum high and low times as specified in the electrical specifications. While in Sleep mode, the slave can transmit/receive data. When a byte is received, the device can be configured to wake-up from Sleep. 19.3.7 SLAVE SELECT SYNCHRONIZATION The SSx pin allows a Synchronous Slave mode. The SPI must be in Slave mode with the SSx pin control enabled (SSPxCON1<3:0> = 04h). When the SSx pin is low, transmission and reception are enabled and the SDOx pin is driven. When the SSx pin goes high, the SDOx pin is no longer driven, even if in the middle of a FIGURE 19-4: transmitted byte and becomes a floating output. External pull-up/pull-down resistors may be desirable depending on the application. Note 1: When the SPI is in Slave mode control enabled with SSx pin (SSPxCON1<3:0> = 0100), the SPI module will reset if the SSx pin is set to VDD. 2: If the SPI is used in Slave mode with CKE set, then the SSx pin control must be enabled. When the SPI module resets, the bit counter is forced to `0'. This can be done by either forcing the SSx pin to a high level or clearing the SSPEN bit. To emulate two-wire communication, the SDOx pin can be connected to the SDIx pin. When the SPI needs to operate as a receiver, the SDOx pin can be configured as an input. This disables transmissions from the SDOx. The SDIx can always be left as an input (SDI function) since it cannot create a bus conflict. SLAVE SYNCHRONIZATION WAVEFORM SSx SCKx (CKP = 0 CKE = 0) SCKx (CKP = 1 CKE = 0) Write to SSPxBUF SDOx SDIx (SMP = 0) bit 7 bit 6 bit 7 bit 0 bit 0 bit 7 bit 7 Input Sample (SMP = 0) SSPxIF Interrupt Flag Next Q4 Cycle after Q2 SSPxSR to SSPxBUF 2004 Microchip Technology Inc. Preliminary DS39646B-page 211 PIC18F8722 FAMILY FIGURE 19-5: SPITM MODE WAVEFORM (SLAVE MODE WITH CKE = 0) SSx Optional SCKx (CKP = 0 CKE = 0) SCKx (CKP = 1 CKE = 0) Write to SSPxBUF SDOx SDIx (SMP = 0) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 0 bit 7 Input Sample (SMP = 0) SSPxIF Interrupt Flag Next Q4 Cycle after Q2 SSPxSR to SSPxBUF FIGURE 19-6: SPITM MODE WAVEFORM (SLAVE MODE WITH CKE = 1) SSx Not Optional SCKx (CKP = 0 CKE = 1) SCKx (CKP = 1 CKE = 1) Write to SSPxBUF SDOx SDIx (SMP = 0) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 0 bit 7 Input Sample (SMP = 0) SSPxIF Interrupt Flag Next Q4 Cycle after Q2 SSPxSR to SSPxBUF DS39646B-page 212 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY 19.3.8 OPERATION IN POWER-MANAGED MODES In SPI Master mode, module clocks may be operating at a different speed than when in full power mode; in the case of the Sleep mode, all clocks are halted. In Idle modes, a clock is provided to the peripherals. That clock can be from the primary clock source, the secondary clock (Timer1 oscillator) or the INTOSC source. See Section 2.7 "Clock Sources and Oscillator Switching" for additional information. 19.3.10 Table 19-1 shows the compatibility between the standard SPI modes and the states of the CKP and CKE control bits. TABLE 19-1: If the Sleep mode is selected, all module clocks are halted and the transmission/reception will remain in that state until the devices wakes. After the device returns to Run mode, the module will resume transmitting and receiving data. In SPI Slave mode, the SPI Transmit/Receive Shift register operates asynchronously to the device. This allows the device to be placed in any power-managed mode and data to be shifted into the SPI Transmit/Receive Shift register. When all 8 bits have been received, the MSSP interrupt flag bit will be set and if enabled, will wake the device. 19.3.9 SPITM BUS MODES Control Bits State Standard SPITM Mode Terminology CKP CKE 0, 0 0 1 0, 1 0 0 1, 0 1 1 1, 1 1 0 In most cases, the speed that the master clocks SPI data is not important; however, this should be evaluated for each system. If MSSP interrupts are enabled, they can wake the controller from Sleep mode, or one of the Idle modes, when the master completes sending data. If an exit from Sleep or Idle mode is not desired, MSSP interrupts should be disabled. BUS MODE COMPATIBILITY There is also an SMP bit which controls when the data is sampled. 19.3.11 SPI CLOCK SPEED AND MODULE INTERACTIONS Because MSSP1 and MSSP2 are independent modules, they can operate simultaneously at different data rates. Setting the SSPM3:SSPM0 bits of the SSPxCON register determines the rate for the corresponding module. An exception is when both modules use Timer2 as a time base in Master mode. In this instance, any changes to the Timer2 module's operation will affect both MSSP modules equally. If different bit rates are required for each module, the user should select one of the other three time base options for one of the modules. EFFECTS OF A RESET A Reset disables the MSSP module and terminates the current transfer. 2004 Microchip Technology Inc. Preliminary DS39646B-page 213 PIC18F8722 FAMILY TABLE 19-2: Name INTCON REGISTERS ASSOCIATED WITH SPI OPERATION Bit 7 Bit 6 Bit 5 GIE/GIEH PEIE/GIEL TMR0IE Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page INT0IE RBIE TMR0IF INT0IF RBIF 57 PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 60 PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 60 IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 60 PIR3 SSP2IF BCL2IF RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF 60 PIE3 SSP2IE BCL2IE RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE 60 IPR3 SSP2IP BCL2IP RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP 60 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 60 TRISD TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 60 TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0 60 TRISF TMR2 Timer2 Register 58 PR2 Timer2 Period Register 58 SSP1BUF MSSP1 Receive Buffer/Transmit Register 58 SSP1CON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 58 SSP1STAT SMP CKE D/A P S R/W UA BF 58 SSP2BUF MSSP2 Receive Buffer/Transmit Register 61 SSP2CON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 61 SSP2STAT SMP CKE D/A P S R/W UA BF 61 Legend: Shaded cells are not used by the MSSP module in SPITM mode. DS39646B-page 214 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY 19.4 I2C Mode 19.4.1 The MSSP module in I 2C mode fully implements all master and slave functions (including general call support) and provides interrupts on Start and Stop bits in hardware to determine a free bus (multi-master function). The MSSP module implements the standard mode specifications, as well as 7-bit and 10-bit addressing. Two pins are used for data transfer: * Serial clock (SCLx) - RC3/SCK1/SCL1 or RD6/SCK2/SCL2 * Serial data (SDAx) - RC4/SDI1/SDA1 or RD5/SDI2/SDA2 The user must configure these pins as inputs by setting the associated TRIS bits. FIGURE 19-7: MSSP BLOCK DIAGRAM (I2CTM MODE) Internal Data Bus Read SSPxBUF reg Shift Clock MSb LSb Match Detect * * * * MSSP Control Register 1 (SSPxCON1) MSSP Control Register 2 (SSPxCON2) MSSP Status Register (SSPxSTAT) Serial Receive/Transmit Buffer Register (SSPxBUF) * MSSP Shift Register (SSPxSR) - Not directly accessible * MSSP Address Register (SSPxADD) SSPxCON1, SSPxCON2 and SSPxSTAT are the control and status registers in I2C mode operation. The SSPxCON1 and SSPxCON2 registers are readable and writable. The lower 6 bits of the SSPxSTAT are read-only. The upper two bits of the SSPxSTAT are read/write. SSPxSR is the shift register used for shifting data in or out. SSPxBUF is the buffer register to which data bytes are written to or read from. In receive operations, SSPxSR and SSPxBUF together create a double-buffered receiver. When SSPxSR receives a complete byte, it is transferred to SSPxBUF and the SSPxIF interrupt is set. SSPxSR reg RC4 or RD5 The MSSP module has six registers for I2C operation. These are: SSPxADD register holds the slave device address when the MSSP is configured in I2C Slave mode. When the MSSP is configured in Master mode, the lower seven bits of SSPxADD act as the Baud Rate Generator reload value. Write RC3 or RD6 REGISTERS During transmission, the SSPxBUF is not double-buffered. A write to SSPxBUF will write to both SSPxBUF and SSPxSR. Addr Match SSPxADD reg Start and Stop bit Detect Note: Set, Reset S, P bits (SSPxSTAT reg) Only port I/O names are used in this diagram for the sake of brevity. Refer to the text for a full list of multiplexed functions. 2004 Microchip Technology Inc. Preliminary DS39646B-page 215 PIC18F8722 FAMILY REGISTER 19-3: SSPxSTAT: MSSPx STATUS REGISTER (I2CTM MODE) R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 SMP CKE D/A P S R/W UA BF bit 7 bit 0 bit 7 SMP: Slew Rate Control bit In Master or Slave mode: 1 = Slew rate control disabled for Standard Speed mode (100 kHz and 1 MHz) 0 = Slew rate control enabled for High-Speed mode (400 kHz) bit 6 CKE: SMBus Select bit In Master or Slave mode: 1 = Enable SMBus specific inputs 0 = Disable SMBus specific inputs bit 5 D/A: Data/Address bit In Master mode: Reserved. In Slave mode: 1 = Indicates that the last byte received or transmitted was data 0 = Indicates that the last byte received or transmitted was address bit 4 P: Stop bit 1 = Indicates that a Stop bit has been detected last 0 = Stop bit was not detected last Note: bit 3 S: Start bit 1 = Indicates that a Start bit has been detected last 0 = Start bit was not detected last Note: bit 2 This bit is cleared on Reset and when SSPEN is cleared. This bit is cleared on Reset and when SSPEN is cleared. R/W: Read/Write Information bit In Slave mode: 1 = Read 0 = Write Note: This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next Start bit, Stop bit or not ACK bit. In Master mode: 1 = Transmit is in progress 0 = Transmit is not in progress Note: ORing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in Active mode. bit 1 UA: Update Address bit (10-bit Slave mode only) 1 = Indicates that the user needs to update the address in the SSPxADD register 0 = Address does not need to be updated bit 0 BF: Buffer Full Status bit In Transmit mode: 1 = SSPxBUF is full 0 = SSPxBUF is empty In Receive mode: 1 = SSPxBUF is full (does not include the ACK and Stop bits) 0 = SSPxBUF is empty (does not include the ACK and Stop bits) Legend: DS39646B-page 216 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared Preliminary x = Bit is unknown 2004 Microchip Technology Inc. PIC18F8722 FAMILY REGISTER 19-4: SSPxCON1: MSSPx CONTROL REGISTER 1 (I2CTM MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 bit 7 bit 0 bit 7 WCOL: Write Collision Detect bit In Master Transmit mode: 1 = A write to the SSPxBUF register was attempted while the I2C conditions were not valid for a transmission to be started (must be cleared in software) 0 = No collision In Slave Transmit mode: 1 = The SSPxBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision In Receive mode (Master or Slave modes): This is a "don't care" bit. bit 6 SSPOV: Receive Overflow Indicator bit In Receive mode: 1 = A byte is received while the SSPxBUF register is still holding the previous byte (must be cleared in software) 0 = No overflow In Transmit mode: This is a "don't care" bit in Transmit mode. bit 5 SSPEN: Synchronous Serial Port Enable bit 1 = Enables the serial port and configures the SDAx and SCLx pins as the serial port pins 0 = Disables serial port and configures these pins as I/O port pins Note: When enabled, the SDAx and SCLx pins must be configured as input. bit 4 CKP: SCKx Release Control bit In Slave mode: 1 = Release clock 0 = Holds clock low (clock stretch), used to ensure data setup time In Master mode: Unused in this mode. bit 3-0 SSPM3:SSPM0: Synchronous Serial Port Mode Select bits 1111 = I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled 1110 = I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled 1011 = I2C Firmware Controlled Master mode (Slave Idle) 1000 = I2C Master mode, clock = FOSC/(4 * (SSPxADD + 1)) 0111 = I2C Slave mode, 10-bit address 0110 = I2C Slave mode, 7-bit address Bit combinations not specifically listed here are either reserved or implemented in SPITM mode only. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared 2004 Microchip Technology Inc. Preliminary x = Bit is unknown DS39646B-page 217 PIC18F8722 FAMILY REGISTER 19-5: SSPxCON2: MSSPx CONTROL REGISTER 2 (I2CTM MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GCEN ACKSTAT ACKDT ACKEN(1) RCEN(1) PEN(1) RSEN(1) SEN(1) bit 7 bit 0 bit 7 GCEN: General Call Enable bit (Slave mode only) 1 = Enable interrupt when a general call address (0000h) is received in the SSPxSR 0 = General call address disabled bit 6 ACKSTAT: Acknowledge Status bit (Master Transmit mode only) 1 = Acknowledge was not received from slave 0 = Acknowledge was received from slave bit 5 ACKDT: Acknowledge Data bit (Master Receive mode only) 1 = Not Acknowledge 0 = Acknowledge Note: Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive. bit 4 ACKEN: Acknowledge Sequence Enable bit (Master Receive mode only)(1) 1 = Initiate Acknowledge sequence on SDAx and SCLx pins and transmit ACKDT data bit. Automatically cleared by hardware. 0 = Acknowledge sequence Idle bit 3 RCEN: Receive Enable bit (Master mode only)(1) 1 = Enables Receive mode for I2C 0 = Receive Idle bit 2 PEN: Stop Condition Enable bit (Master mode only)(1) 1 = Initiate Stop condition on SDAx and SCLx pins. Automatically cleared by hardware. 0 = Stop condition Idle bit 1 RSEN: Repeated Start Condition Enable bit (Master mode only)(1) 1 = Initiate Repeated Start condition on SDAx and SCLx pins. Automatically cleared by hardware. 0 = Repeated Start condition Idle bit 0 SEN: Start Condition Enable/Stretch Enable bit(1) In Master mode: 1 = Initiate Start condition on SDAx and SCLx pins. Automatically cleared by hardware. 0 = Start condition Idle In Slave mode: 1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled) 0 = Clock stretching is disabled Note 1: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is active, these bits may not be set (no spooling) and the SSPxBUF may not be written (or writes to the SSPxBUF are disabled). Legend: DS39646B-page 218 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared Preliminary x = Bit is unknown 2004 Microchip Technology Inc. PIC18F8722 FAMILY 19.4.2 OPERATION 19.4.3.1 The MSSP module functions are enabled by setting MSSP Enable bit, SSPEN (SSPxCON1<5>). The SSPxCON1 register allows control of the I2C operation. Four mode selection bits (SSPxCON1<3:0>) allow one of the following I2C modes to be selected: I2C Master mode, clock I 2C Slave mode (7-bit address) I 2C Slave mode (10-bit address) I 2C Slave mode (7-bit address) with Start and Stop bit interrupts enabled * I 2C Slave mode (10-bit address) with Start and Stop bit interrupts enabled * I 2C Firmware Controlled Master mode, slave is Idle * * * * 19.4.3 Once the MSSP module has been enabled, it waits for a Start condition to occur. Following the Start condition, the 8 bits are shifted into the SSPxSR register. All incoming bits are sampled with the rising edge of the clock (SCLx) line. The value of register SSPxSR<7:1> is compared to the value of the SSPxADD register. The address is compared on the falling edge of the eighth clock (SCLx) pulse. If the addresses match and the BF and SSPOV bits are clear, the following events occur: 1. 2. 3. 4. Selection of any I 2C mode with the SSPEN bit set forces the SCLx and SDAx pins to be open-drain, provided these pins are programmed as inputs by setting the appropriate TRISC or TRISD bits. To ensure proper operation of the module, pull-up resistors must be provided externally to the SCLx and SDAx pins. SLAVE MODE In Slave mode, the SCLx and SDAx pins must be configured as inputs (TRISC<4:3> set). The MSSP module will override the input state with the output data when required (slave-transmitter). The I 2C Slave mode hardware will always generate an interrupt on an address match. Through the mode select bits, the user can also choose to interrupt on Start and Stop bits When an address is matched, or the data transfer after an address match is received, the hardware automatically will generate the Acknowledge (ACK) pulse and load the SSPxBUF register with the received value currently in the SSPxSR register. 1. 2. 3. 4. 5. 6. 7. 8. In this case, the SSPxSR register value is not loaded into the SSPxBUF, but bit SSPxIF is set. The BF bit is cleared by reading the SSPxBUF register, while bit SSPOV is cleared through software. The SSPxSR register value is loaded into the SSPxBUF register. The Buffer Full bit, BF, is set. An ACK pulse is generated. The MSSP Interrupt Flag bit, SSPxIF, is set (and interrupt is generated, if enabled) on the falling edge of the ninth SCLx pulse. In 10-bit Address mode, two address bytes need to be received by the slave. The five Most Significant bits (MSbs) of the first address byte specify if this is a 10-bit address. Bit R/W (SSPxSTAT<2>) must specify a write so the slave device will receive the second address byte. For a 10-bit address, the first byte would equal `11110 A9 A8 0', where `A9' and `A8' are the two MSbs of the address. The sequence of events for 10-bit address is as follows, with steps 7 through 9 for the slave-transmitter: Any combination of the following conditions will cause the MSSP module not to give this ACK pulse: * The Buffer Full bit, BF (SSPxSTAT<0>), was set before the transfer was received. * The overflow bit, SSPOV (SSPxCON1<6>), was set before the transfer was received. Addressing 9. Receive first (high) byte of address (bits SSPxIF, BF and UA (SSPxSTAT<1>) are set on address match). Update the SSPxADD register with second (low) byte of address (clears bit UA and releases the SCLx line). Read the SSPxBUF register (clears bit BF) and clear flag bit SSPxIF. Receive second (low) byte of address (bits SSPxIF, BF and UA are set). Update the SSPxADD register with the first (high) byte of address. If match releases SCLx line, this will clear bit UA. Read the SSPxBUF register (clears bit BF) and clear flag bit SSPxIF. Receive Repeated Start condition. Receive first (high) byte of address (bits SSPxIF and BF are set). Read the SSPxBUF register (clears bit BF) and clear flag bit SSPxIF. The SCLx clock input must have a minimum high and low for proper operation. The high and low times of the I2C specification, as well as the requirement of the MSSP module, are shown in timing parameter 100 and parameter 101. 2004 Microchip Technology Inc. Preliminary DS39646B-page 219 PIC18F8722 FAMILY 19.4.3.2 Reception 19.4.3.3 When the R/W bit of the address byte is clear and an address match occurs, the R/W bit of the SSPxSTAT register is cleared. The received address is loaded into the SSPxBUF register and the SDAx line is held low (ACK). When the address byte overflow condition exists, then the no Acknowledge (ACK) pulse is given. An overflow condition is defined as either bit BF (SSPxSTAT<0>) is set, or bit SSPOV (SSPxCON1<6>) is set. An MSSP interrupt is generated for each data transfer byte. The interrupt flag bit, SSPxIF, must be cleared in software. The SSPxSTAT register is used to determine the status of the byte. If SEN is enabled (SSPxCON2<0> = 1), SCLx will be held low (clock stretch) following each data transfer. The clock must be released by setting bit, CKP (SSPxCON1<4>). See Section 19.4.4 "Clock Stretching" for more detail. Transmission When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit of the SSPxSTAT register is set. The received address is loaded into the SSPxBUF register. The ACK pulse will be sent on the ninth bit and pin SCLx is held low regardless of SEN (see Section 19.4.4 "Clock Stretching" for more detail). By stretching the clock, the master will be unable to assert another clock pulse until the slave is done preparing the transmit data. The transmit data must be loaded into the SSPxBUF register which also loads the SSPxSR register. Then pin SCLx should be enabled by setting bit, CKP (SSPxCON1<4>). The eight data bits are shifted out on the falling edge of the SCLx input. This ensures that the SDAx signal is valid during the SCLx high time (Figure 19-9). The ACK pulse from the master-receiver is latched on the rising edge of the ninth SCLx input pulse. If the SDAx line is high (not ACK), then the data transfer is complete. In this case, when the ACK is latched by the slave, the slave logic is reset (resets SSPxSTAT register) and the slave monitors for another occurrence of the Start bit. If the SDAx line was low (ACK), the next transmit data must be loaded into the SSPxBUF register. Again, pin SCLx must be enabled by setting bit CKP. An MSSP interrupt is generated for each data transfer byte. The SSPxIF bit must be cleared in software and the SSPxSTAT register is used to determine the status of the byte. The SSPxIF bit is set on the falling edge of the ninth clock pulse. DS39646B-page 220 Preliminary 2004 Microchip Technology Inc. 2004 Microchip Technology Inc. 2 A6 Preliminary CKP 3 A5 4 A4 5 A3 6 A2 (CKP does not reset to `0' when SEN = 0) SSPOV (SSPxCON1<6>) BF (SSPxSTAT<0>) SSPxIF (PIR1<3> or PIR3<7>) 1 SCLx S A7 Receiving Address 7 A1 8 9 ACK R/W = 0 1 D7 3 D5 4 D4 Cleared in software SSPxBUF is read 2 D6 5 D3 Receiving Data 6 D2 7 D1 8 D0 9 ACK 1 D7 2 D6 3 D5 4 D4 5 D3 Receiving Data 6 D2 7 D1 8 D0 Bus master terminates transfer P SSPOV is set because SSPxBUF is still full. ACK is not sent. 9 ACK FIGURE 19-8: SDAx PIC18F8722 FAMILY I2CTM SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 7-BIT ADDRESS) DS39646B-page 221 DS39646B-page 222 2 Data in sampled 1 A6 Preliminary CKP BF (SSPxSTAT<0>) SSPxIF (PIR1<3> or PIR3<7>) S A7 3 4 A4 5 A3 6 A2 Receiving Address A5 7 A1 8 R/W = 0 9 ACK 3 D5 4 5 D3 SSPxBUF is written in software 6 D2 Transmitting Data D4 Cleared in software 2 D6 CKP is set in software SCLx held low while CPU responds to SSPxIF 1 D7 7 8 D0 9 From SSPxIF ISR D1 ACK 1 D7 4 D4 5 D3 Cleared in software 3 D5 6 D2 CKP is set in software SSPxBUF is written in software 2 D6 7 8 D0 9 ACK From SSPxIF ISR D1 Transmitting Data P FIGURE 19-9: SCLx SDAx PIC18F8722 FAMILY I2CTM SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESS) 2004 Microchip Technology Inc. 2004 Microchip Technology Inc. 2 1 3 1 Preliminary 5 0 7 A8 8 UA is set indicating that the SSPxADD needs to be updated SSPxBUF is written with contents of SSPxSR 6 A9 9 (CKP does not reset to `0' when SEN = 0) UA (SSPxSTAT<1>) SSPOV (SSPxCON1<6>) BF (SSPxSTAT<0>) CKP 4 1 Cleared in software SSPxIF (PIR1<3> or PIR3<7>) 1 SCLx S 1 ACK R/W = 0 A7 2 4 A4 5 A3 6 A2 8 9 A0 ACK UA is set indicating that SSPxADD needs to be updated Cleared by hardware when SSPxADD is updated with low byte of address 7 A1 Cleared in software 3 A5 Dummy read of SSPxBUF to clear BF flag 1 A6 Receive Second Byte of Address 1 D7 4 5 6 Cleared in software 3 D3 D2 7 8 9 1 2 4 5 6 Cleared in software 3 D3 D2 Receive Data Byte D1 D0 ACK D7 D6 D5 D4 Cleared by hardware when SSPxADD is updated with high byte of address 2 D6 D5 D4 Receive Data Byte Clock is held low until update of SSPxADD has taken place 7 8 D1 D0 9 P Bus master terminates transfer SSPOV is set because SSPxBUF is still full. ACK is not sent. ACK FIGURE 19-10: SDAx Receive First Byte of Address Clock is held low until update of SSPxADD has taken place PIC18F8722 FAMILY I2CTM SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 10-BIT ADDRESS) DS39646B-page 223 DS39646B-page 224 2 1 3 1 4 1 Preliminary CKP (SSPxCON1<4>) UA (SSPxSTAT<1>) BF (SSPxSTAT<0>) 5 0 6 7 A9 A8 8 UA is set indicating that the SSPxADD needs to be updated SSPxBUF is written with contents of SSPxSR SSPxIF (PIR1<3> or PIR3<7>) 1 SCLx S 1 9 ACK R/W = 0 1 3 4 5 Cleared in software 2 7 UA is set indicating that SSPxADD needs to be updated 8 A0 Cleared by hardware when SSPxADD is updated with low byte of address 6 A6 A5 A4 A3 A2 A1 Receive Second Byte of Address Dummy read of SSPxBUF to clear BF flag A7 9 ACK 2 3 1 4 1 Cleared in software 1 1 5 0 6 8 9 ACK R/W = 1 1 2 4 5 6 CKP is set in software 9 P Completion of data transmission clears BF flag 8 ACK Bus master terminates transfer CKP is automatically cleared in hardware, holding SCLx low 7 D4 D3 D2 D1 D0 Cleared in software 3 D7 D6 D5 Transmitting Data Byte Clock is held low until CKP is set to `1' Write of SSPxBUF BF flag is clear initiates transmit at the end of the third address sequence 7 A9 A8 Cleared by hardware when SSPxADD is updated with high byte of address. Dummy read of SSPxBUF to clear BF flag Sr 1 Receive First Byte of Address Clock is held low until update of SSPxADD has taken place FIGURE 19-11: SDAx Receive First Byte of Address Clock is held low until update of SSPxADD has taken place PIC18F8722 FAMILY I2CTM SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS) 2004 Microchip Technology Inc. PIC18F8722 FAMILY 19.4.4 CLOCK STRETCHING 19.4.4.3 Both 7-bit and 10-bit Slave modes implement automatic clock stretching during a transmit sequence. The SEN bit (SSPxCON2<0>) allows clock stretching to be enabled during receives. Setting SEN will cause the SCLx pin to be held low at the end of each data receive sequence. 19.4.4.1 Clock Stretching for 7-bit Slave Receive Mode (SEN = 1) In 7-bit Slave Receive mode, on the falling edge of the ninth clock at the end of the ACK sequence, if the BF bit is set, the CKP bit in the SSPxCON1 register is automatically cleared, forcing the SCLx output to be held low. The CKP being cleared to `0' will assert the SCLx line low. The CKP bit must be set in the user's ISR before reception is allowed to continue. By holding the SCLx line low, the user has time to service the ISR and read the contents of the SSPxBUF before the master device can initiate another receive sequence. This will prevent buffer overruns from occurring (see Figure 19-13). Note 1: If the user reads the contents of the SSPxBUF before the falling edge of the ninth clock, thus clearing the BF bit, the CKP bit will not be cleared and clock stretching will not occur. 2: The CKP bit can be set in software regardless of the state of the BF bit. The user should be careful to clear the BF bit in the ISR before the next receive sequence in order to prevent an overflow condition. 19.4.4.2 Clock Stretching for 7-bit Slave Transmit Mode The 7-bit Slave Transmit mode implements clock stretching by clearing the CKP bit after the falling edge of the ninth clock if the BF bit is clear. This occurs regardless of the state of the SEN bit. The user's ISR must set the CKP bit before transmission is allowed to continue. By holding the SCLx line low, the user has time to service the ISR and load the contents of the SSPxBUF before the master device can initiate another transmit sequence (see Figure 19-9). Note 1: If the user loads the contents of SSPxBUF, setting the BF bit before the falling edge of the ninth clock, the CKP bit will not be cleared and clock stretching will not occur. 2: The CKP bit can be set in software regardless of the state of the BF bit. 19.4.4.4 Clock Stretching for 10-bit Slave Transmit Mode In 10-bit Slave Transmit mode, clock stretching is controlled during the first two address sequences by the state of the UA bit, just as it is in 10-bit Slave Receive mode. The first two addresses are followed by a third address sequence which contains the high-order bits of the 10-bit address and the R/W bit set to `1'. After the third address sequence is performed, the UA bit is not set, the module is now configured in Transmit mode and clock stretching is controlled by the BF flag as in 7-bit Slave Transmit mode (see Figure 19-11). Clock Stretching for 10-bit Slave Receive Mode (SEN = 1) In 10-bit Slave Receive mode during the address sequence, clock stretching automatically takes place but CKP is not cleared. During this time, if the UA bit is set after the ninth clock, clock stretching is initiated. The UA bit is set after receiving the upper byte of the 10-bit address and following the receive of the second byte of the 10-bit address with the R/W bit cleared to `0'. The release of the clock line occurs upon updating SSPxADD. Clock stretching will occur on each data receive sequence as described in 7-bit mode. Note: If the user polls the UA bit and clears it by updating the SSPxADD register before the falling edge of the ninth clock occurs and if the user hasn't cleared the BF bit by reading the SSPxBUF register before that time, then the CKP bit will still NOT be asserted low. Clock stretching on the basis of the state of the BF bit only occurs during a data sequence, not an address sequence. 2004 Microchip Technology Inc. Preliminary DS39646B-page 225 PIC18F8722 FAMILY 19.4.4.5 Clock Synchronization and the CKP bit When the CKP bit is cleared, the SCLx output is forced to `0'. However, clearing the CKP bit will not assert the SCLx output low until the SCLx output is already sampled low. Therefore, the CKP bit will not assert the SCLx line until an external I2C master device has FIGURE 19-12: already asserted the SCLx line. The SCLx output will remain low until the CKP bit is set and all other devices on the I2C bus have deasserted SCLx. This ensures that a write to the CKP bit will not violate the minimum high time requirement for SCLx (see Figure 19-12). CLOCK SYNCHRONIZATION TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 SDAx DX - 1 DX SCLx CKP Master device asserts clock Master device deasserts clock WR SSPxCON1 DS39646B-page 226 Preliminary 2004 Microchip Technology Inc. 2004 Microchip Technology Inc. 2 A6 Preliminary CKP SSPOV (SSPxCON1<6>) BF (SSPxSTAT<0>) SSPxIF (PIR1<3> or PIR3<7>) 1 SCLx S A7 3 A5 4 A4 5 A3 6 A2 Receiving Address 7 A1 8 9 ACK R/W = 0 3 D5 4 D4 5 D3 Cleared in software 2 D6 If BF is cleared prior to the falling edge of the 9th clock, CKP will not be reset to `0' and no clock stretching will occur SSPxBUF is read 1 D7 Receiving Data 6 D2 7 D1 9 1 D7 BF is set after falling edge of the 9th clock, CKP is reset to `0' and clock stretching occurs 8 D0 ACK 3 4 D4 5 D3 Receiving Data D5 CKP written to `1' in software 2 D6 Clock is held low until CKP is set to `1' 6 D2 7 D1 8 D0 Bus master terminates transfer P SSPOV is set because SSPxBUF is still full. ACK is not sent. 9 ACK Clock is not held low because ACK = 1 FIGURE 19-13: SDAx Clock is not held low because buffer full bit is clear prior to falling edge of 9th clock PIC18F8722 FAMILY I2CTM SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 7-BIT ADDRESS) DS39646B-page 227 DS39646B-page 228 2 1 3 1 Preliminary UA (SSPxSTAT<1>) SSPOV (SSPxCON1<6>) BF (SSPxSTAT<0>) CKP 4 1 5 0 6 7 A9 A8 8 UA is set indicating that the SSPxADD needs to be updated SSPxBUF is written with contents of SSPxSR Cleared in software SSPxIF (PIR1<3> or PIR3<7>) 1 SCLx S 1 9 ACK R/W = 0 A7 2 4 A4 5 A3 6 A2 Cleared in software 3 A5 7 A1 8 A0 Note: An update of the SSPxADD register before the falling edge of the ninth clock will have no effect on UA and UA will remain set. UA is set indicating that SSPxADD needs to be updated Cleared by hardware when SSPxADD is updated with low byte of address after falling edge of ninth clock Dummy read of SSPxBUF to clear BF flag 1 A6 Receive Second Byte of Address 9 ACK 2 4 5 6 Cleared in software 3 D3 D2 7 8 1 4 5 6 Cleared in software 3 CKP written to `1' in software 2 D3 D2 Receive Data Byte D7 D6 D5 D4 Note: An update of the SSPxADD register before the falling edge of the ninth clock will have no effect on UA and UA will remain set. 9 ACK Clock is held low until CKP is set to `1' D1 D0 Cleared by hardware when SSPxADD is updated with high byte of address after falling edge of ninth clock Dummy read of SSPxBUF to clear BF flag 1 D7 D6 D5 D4 Receive Data Byte Clock is held low until update of SSPxADD has taken place 7 8 9 ACK Bus master terminates transfer P SSPOV is set because SSPxBUF is still full. ACK is not sent. D1 D0 Clock is not held low because ACK = 1 FIGURE 19-14: SDAx Receive First Byte of Address Clock is held low until update of SSPxADD has taken place PIC18F8722 FAMILY I2CTM SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 10-BIT ADDRESS) 2004 Microchip Technology Inc. PIC18F8722 FAMILY 19.4.5 GENERAL CALL ADDRESS SUPPORT If the general call address matches, the SSPxSR is transferred to the SSPxBUF, the BF flag bit is set (eighth bit) and on the falling edge of the ninth bit (ACK bit), the SSPxIF interrupt flag bit is set. The addressing procedure for the I2C bus is such that the first byte after the Start condition usually determines which device will be the slave addressed by the master. The exception is the general call address which can address all devices. When this address is used, all devices should, in theory, respond with an Acknowledge. When the interrupt is serviced, the source for the interrupt can be checked by reading the contents of the SSPxBUF. The value can be used to determine if the address was device specific or a general call address. In 10-bit mode, the SSPxADD is required to be updated for the second half of the address to match and the UA bit is set (SSPxSTAT<1>). If the general call address is sampled when the GCEN bit is set, while the slave is configured in 10-bit Address mode, then the second half of the address is not necessary, the UA bit will not be set and the slave will begin receiving data after the Acknowledge (Figure 19-15). The general call address is one of eight addresses reserved for specific purposes by the I2C protocol. It consists of all `0's with R/W = 0. The general call address is recognized when the General Call Enable bit, GCEN, is enabled (SSPxCON2<7> set). Following a Start bit detect, 8 bits are shifted into the SSPxSR and the address is compared against the SSPxADD. It is also compared to the general call address and fixed in hardware. FIGURE 19-15: SLAVE MODE GENERAL CALL ADDRESS SEQUENCE (7 OR 10-BIT ADDRESS MODE) Address is compared to General Call Address after ACK, set interrupt Receiving Data R/W = 0 General Call Address SDAx ACK D7 ACK D6 D5 D4 D3 D2 D1 D0 2 3 4 5 6 7 8 SCLx S 1 2 3 4 5 6 7 8 9 1 9 SSPxIF BF (SSPxSTAT<0>) Cleared in software SSPxBUF is read SSPOV (SSPxCON1<6>) `0' GCEN (SSPxCON2<7>) `1' 2004 Microchip Technology Inc. Preliminary DS39646B-page 229 PIC18F8722 FAMILY MASTER MODE Note: Master mode is enabled by setting and clearing the appropriate SSPM bits in SSPxCON1 and by setting the SSPEN bit. In Master mode, the SCLx and SDAx lines are manipulated by the MSSP hardware if the TRIS bits are set. Master mode of operation is supported by interrupt generation on the detection of the Start and Stop conditions. The Stop (P) and Start (S) bits are cleared from a Reset or when the MSSP module is disabled. Control of the I 2C bus may be taken when the P bit is set, or the bus is Idle, with both the S and P bits clear. The following events will cause the SSP Interrupt Flag bit, SSPxIF, to be set (and SSP interrupt, if enabled): In Firmware Controlled Master mode, user code conducts all I 2C bus operations based on Start and Stop bit conditions. * * * * * Once Master mode is enabled, the user has six options. 1. 2. 3. 4. 5. 6. Assert a Start condition on SDAx and SCLx. Assert a Repeated Start condition on SDAx and SCLx. Write to the SSPxBUF register initiating transmission of data/address. Configure the I2C port to receive data. Generate an Acknowledge condition at the end of a received byte of data. Generate a Stop condition on SDAx and SCLx. FIGURE 19-16: The MSSP module, when configured in I2C Master mode, does not allow queueing of events. For instance, the user is not allowed to initiate a Start condition and immediately write the SSPxBUF register to initiate transmission before the Start condition is complete. In this case, the SSPxBUF will not be written to and the WCOL bit will be set, indicating that a write to the SSPxBUF did not occur. Start condition Stop condition Data transfer byte transmitted/received Acknowledge transmit Repeated Start MSSP BLOCK DIAGRAM (I2CTM MASTER MODE) Internal Data Bus Read SSPM3:SSPM0 SSPxADD<6:0> Write SSPxBUF Baud Rate Generator Shift Clock SDAx SDAx In SCLx In Bus Collision DS39646B-page 230 LSb Start bit, Stop bit, Acknowledge Generate Start bit Detect Stop bit Detect Write Collision Detect Clock Arbitration State Counter for end of XMIT/RCV Preliminary Clock Cntl SCLx Receive Enable SSPxSR MSb Clock Arbitrate/WCOL Detect (hold off clock source) 19.4.6 Set/Reset S, P (SSPxSTAT), WCOL (SSPxCON1) Set SSPxIF, BCLxIF Reset ACKSTAT, PEN (SSPxCON2) 2004 Microchip Technology Inc. PIC18F8722 FAMILY 19.4.6.1 I2C Master Mode Operation A typical transmit sequence would go as follows: The master device generates all of the serial clock pulses and the Start and Stop conditions. A transfer is ended with a Stop condition or with a Repeated Start condition. Since the Repeated Start condition is also the beginning of the next serial transfer, the I2C bus will not be released. In Master Transmitter mode, serial data is output through SDAx, while SCLx outputs the serial clock. The first byte transmitted contains the slave address of the receiving device (7 bits) and the Read/Write (R/W) bit. In this case, the R/W bit will be logic `0'. Serial data is transmitted 8 bits at a time. After each byte is transmitted, an Acknowledge bit is received. Start and Stop conditions are output to indicate the beginning and the end of a serial transfer. In Master Receive mode, the first byte transmitted contains the slave address of the transmitting device (7 bits) and the R/W bit. In this case, the R/W bit will be logic `1'. Thus, the first byte transmitted is a 7-bit slave address, followed by a `1' to indicate the receive bit. Serial data is received via SDAx, while SCLx outputs the serial clock. Serial data is received 8 bits at a time. After each byte is received, an Acknowledge bit is transmitted. Start and Stop conditions indicate the beginning and end of transmission. The Baud Rate Generator used for the SPI mode operation is used to set the SCLx clock frequency for either 100 kHz, 400 kHz or 1 MHz I2C operation. See Section 19.4.7 "Baud Rate" for more detail. 2004 Microchip Technology Inc. 1. The user generates a Start condition by setting the Start Enable bit, SEN (SSPxCON2<0>). 2. SSPxIF is set. The MSSP module will wait the required start time before any other operation takes place. 3. The user loads the SSPxBUF with the slave address to transmit. 4. Address is shifted out the SDAx pin until all 8 bits are transmitted. 5. The MSSP module shifts in the ACK bit from the slave device and writes its value into the SSPxCON2 register (SSPxCON2<6>). 6. The MSSP module generates an interrupt at the end of the ninth clock cycle by setting the SSPxIF bit. 7. The user loads the SSPxBUF with eight bits of data. 8. Data is shifted out the SDAx pin until all 8 bits are transmitted. 9. The MSSP module shifts in the ACK bit from the slave device and writes its value into the SSPxCON2 register (SSPxCON2<6>). 10. The MSSP module generates an interrupt at the end of the ninth clock cycle by setting the SSPxIF bit. 11. The user generates a Stop condition by setting the Stop Enable bit, PEN (SSPxCON2<2>). 12. Interrupt is generated once the Stop condition is complete. Preliminary DS39646B-page 231 PIC18F8722 FAMILY 19.4.7 BAUD RATE 19.4.7.1 2 In I C Master mode, the Baud Rate Generator (BRG) reload value is placed in the lower 7 bits of the SSPxADD register (Figure 19-17). When a write occurs to SSPxBUF, the Baud Rate Generator will automatically begin counting. The BRG counts down to `0' and stops until another reload has taken place. The BRG count is decremented twice per instruction cycle (TCY) on the Q2 and Q4 clocks. In I2C Master mode, the BRG is reloaded automatically. Baud Rate and Module Interdependence Because MSSP1 and MSSP2 are independent, they can operate simultaneously in I2C Master mode at different baud rates. This is done by using different BRG reload values for each module. Because this mode derives its basic clock source from the system clock, any changes to the clock will affect both modules in the same proportion. It may be possible to change one or both baud rates back to a previous value by changing the BRG reload value. Once the given operation is complete (i.e., transmission of the last data bit is followed by ACK), the internal clock will automatically stop counting and the SCLx pin will remain in its last state. Table 19-3 demonstrates clock rates based on instruction cycles and the BRG value loaded into SSPxADD. FIGURE 19-17: BAUD RATE GENERATOR BLOCK DIAGRAM SSPM3:SSPM0 SSPM3:SSPM0 Reload SCLx Control SSPxADD<6:0> Reload BRG Down Counter CLKO TABLE 19-3: FOSC/4 I2CTM CLOCK RATE w/BRG FOSC FCY FCY*2 BRG Value FSCL (2 Rollovers of BRG) 40 MHz 10 MHz 20 MHz 18h 400 kHz(1) 40 MHz 10 MHz 20 MHz 1Fh 312.5 kHz 40 MHz 10 MHz 20 MHz 63h 100 kHz 16 MHz 4 MHz 8 MHz 09h 400 kHz(1) 16 MHz 4 MHz 8 MHz 0Ch 308 kHz 16 MHz 4 MHz 8 MHz 27h 100 kHz 4 MHz 1 MHz 2 MHz 02h 333 kHz(1) 4 MHz 1 MHz 2 MHz 09h 100 kHz 1 MHz 2 MHz 00h 1 MHz(1) 4 MHz Note 1: I2C I2C The interface does not conform to the 400 kHz specification (which applies to rates greater than 100 kHz) in all details, but may be used with care where higher rates are required by the application. DS39646B-page 232 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY 19.4.7.2 Clock Arbitration Clock arbitration occurs when the master, during any receive, transmit or Repeated Start/Stop condition, deasserts the SCLx pin (SCLx allowed to float high). When the SCLx pin is allowed to float high, the Baud Rate Generator (BRG) is suspended from counting until the SCLx pin is actually sampled high. When the FIGURE 19-18: SCLx pin is sampled high, the Baud Rate Generator is reloaded with the contents of SSPxADD<6:0> and begins counting. This ensures that the SCLx high time will always be at least one BRG rollover count in the event that the clock is held low by an external device (Figure 19-18). BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION SDAx DX DX - 1 SCLx deasserted but slave holds SCLx low (clock arbitration) SCLx allowed to transition high SCLx BRG decrements on Q2 and Q4 cycles BRG Value 03h 02h 01h 00h (hold off) 03h 02h SCLx is sampled high, reload takes place and BRG starts its count BRG Reload 2004 Microchip Technology Inc. Preliminary DS39646B-page 233 PIC18F8722 FAMILY 19.4.8 I2C MASTER MODE START CONDITION TIMING Note: To initiate a Start condition, the user sets the Start Enable bit, SEN (SSPxCON2<0>). If the SDAx and SCLx pins are sampled high, the Baud Rate Generator is reloaded with the contents of SSPxADD<6:0> and starts its count. If SCLx and SDAx are both sampled high when the Baud Rate Generator times out (TBRG), the SDAx pin is driven low. The action of the SDAx being driven low while SCLx is high is the Start condition and causes the S bit (SSPxSTAT<3>) to be set. Following this, the Baud Rate Generator is reloaded with the contents of SSPxADD<6:0> and resumes its count. When the Baud Rate Generator times out (TBRG), the SEN bit (SSPxCON2<0>) will be automatically cleared by hardware; the Baud Rate Generator is suspended, leaving the SDAx line held low and the Start condition is complete. FIGURE 19-19: 19.4.8.1 If at the beginning of the Start condition, the SDAx and SCLx pins are already sampled low, or if during the Start condition, the SCLx line is sampled low before the SDAx line is driven low, a bus collision occurs, the Bus Collision Interrupt Flag, BCLxIF, is set, the Start condition is aborted and the I2C module is reset into its Idle state. WCOL Status Flag If the user writes the SSPxBUF when a Start sequence is in progress, the WCOL bit is set and the contents of the buffer are unchanged (the write doesn't occur). Note: Because queueing of events is not allowed, writing to the lower 5 bits of SSPxCON2 is disabled until the Start condition is complete. FIRST START BIT TIMING Set S bit (SSPxSTAT<3>) Write to SEN bit occurs here SDAx = 1, SCLx = 1 TBRG At completion of Start bit, hardware clears SEN bit and sets SSPxIF bit TBRG Write to SSPxBUF occurs here 1st bit SDAx 2nd bit TBRG SCLx TBRG S DS39646B-page 234 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY 19.4.9 I2C MASTER MODE REPEATED START CONDITION TIMING Note 1: If RSEN is programmed while any other event is in progress, it will not take effect. A Repeated Start condition occurs when the RSEN bit (SSPxCON2<1>) is programmed high and the I2C logic module is in the Idle state. When the RSEN bit is set, the SCLx pin is asserted low. When the SCLx pin is sampled low, the Baud Rate Generator is loaded with the contents of SSPxADD<5:0> and begins counting. The SDAx pin is released (brought high) for one Baud Rate Generator count (TBRG). When the Baud Rate Generator times out, if SDAx is sampled high, the SCLx pin will be deasserted (brought high). When SCLx is sampled high, the Baud Rate Generator is reloaded with the contents of SSPxADD<6:0> and begins counting. SDAx and SCLx must be sampled high for one TBRG. This action is then followed by assertion of the SDAx pin (SDAx = 0) for one TBRG while SCLx is high. Following this, the RSEN bit (SSPxCON2<1>) will be automatically cleared and the Baud Rate Generator will not be reloaded, leaving the SDAx pin held low. As soon as a Start condition is detected on the SDAx and SCLx pins, the S bit (SSPxSTAT<3>) will be set. The SSPxIF bit will not be set until the Baud Rate Generator has timed out. 2: A bus collision during the Repeated Start condition occurs if: * SDAx is sampled low when SCLx goes from low-to-high. * SCLx goes low before SDAx is asserted low. This may indicate that another master is attempting to transmit a data `1'. Immediately following the SSPxIF bit getting set, the user may write the SSPxBUF with the 7-bit address in 7-bit mode or the default first address in 10-bit mode. After the first eight bits are transmitted and an ACK is received, the user may then transmit an additional eight bits of address (10-bit mode) or eight bits of data (7-bit mode). 19.4.9.1 If the user writes the SSPxBUF when a Repeated Start sequence is in progress, the WCOL is set and the contents of the buffer are unchanged (the write doesn't occur). Note: FIGURE 19-20: WCOL Status Flag Because queueing of events is not allowed, writing of the lower 5 bits of SSPxCON2 is disabled until the Repeated Start condition is complete. REPEATED START CONDITION WAVEFORM S bit set by hardware Write to SSPxCON2 occurs here: SDAx = 1, SCLx (no change). SDAx = 1, SCLx = 1 TBRG TBRG At completion of Start bit, hardware clears RSEN bit and sets SSPxIF TBRG 1st bit SDAx RSEN bit set by hardware on falling edge of ninth clock, end of Xmit Write to SSPxBUF occurs here TBRG SCLx TBRG Sr = Repeated Start 2004 Microchip Technology Inc. Preliminary DS39646B-page 235 PIC18F8722 FAMILY 19.4.10 I2C MASTER MODE TRANSMISSION Transmission of a data byte, a 7-bit address, or the other half of a 10-bit address, is accomplished by simply writing a value to the SSPxBUF register. This action will set the Buffer Full flag bit, BF and allow the Baud Rate Generator to begin counting and start the next transmission. Each bit of address/data will be shifted out onto the SDAx pin after the falling edge of SCLx is asserted (see data hold time specification parameter 106). SCLx is held low for one Baud Rate Generator rollover count (TBRG). Data should be valid before SCLx is released high (see data setup time specification parameter 107). When the SCLx pin is released high, it is held that way for TBRG. The data on the SDAx pin must remain stable for that duration and some hold time after the next falling edge of SCLx. After the eighth bit is shifted out (the falling edge of the eighth clock), the BF flag is cleared and the master releases SDAx. This allows the slave device being addressed to respond with an ACK bit during the ninth bit time if an address match occurred, or if data was received properly. The status of ACK is written into the ACKDT bit on the falling edge of the ninth clock. If the master receives an Acknowledge, the Acknowledge Status bit, ACKSTAT, is cleared. If not, the bit is set. After the ninth clock, the SSPxIF bit is set and the master clock (Baud Rate Generator) is suspended until the next data byte is loaded into the SSPxBUF, leaving SCLx low and SDAx unchanged (Figure 19-21). After the write to the SSPxBUF, each bit of the address will be shifted out on the falling edge of SCLx until all seven address bits and the R/W bit are completed. On the falling edge of the eighth clock, the master will deassert the SDAx pin, allowing the slave to respond with an Acknowledge. On the falling edge of the ninth clock, the master will sample the SDAx pin to see if the address was recognized by a slave. The status of the ACK bit is loaded into the ACKSTAT status bit (SSPxCON2<6>). Following the falling edge of the ninth clock transmission of the address, the SSPxIF is set, the BF flag is cleared and the Baud Rate Generator is turned off until another write to the SSPxBUF takes place, holding SCLx low and allowing SDAx to float. 19.4.10.1 BF Status Flag 19.4.10.3 WCOL Status Flag ACKSTAT Status Flag In Transmit mode, the ACKSTAT bit (SSPxCON2<6>) is cleared when the slave has sent an Acknowledge (ACK = 0) and is set when the slave does not Acknowledge (ACK = 1). A slave sends an Acknowledge when it has recognized its address (including a general call), or when the slave has properly received its data. 19.4.11 I2C MASTER MODE RECEPTION Master mode reception is enabled by programming the Receive Enable bit, RCEN (SSPxCON2<3>). Note: The MSSP module must be in an inactive state before the RCEN bit is set or the RCEN bit will be disregarded. The Baud Rate Generator begins counting and on each rollover, the state of the SCLx pin changes (high-to-low/low-to-high) and data is shifted into the SSPxSR. After the falling edge of the eighth clock, the receive enable flag is automatically cleared, the contents of the SSPxSR are loaded into the SSPxBUF, the BF flag bit is set, the SSPxIF flag bit is set and the Baud Rate Generator is suspended from counting, holding SCLx low. The MSSP is now in Idle state awaiting the next command. When the buffer is read by the CPU, the BF flag bit is automatically cleared. The user can then send an Acknowledge bit at the end of reception by setting the Acknowledge Sequence Enable bit, ACKEN (SSPxCON2<4>). 19.4.11.1 BF Status Flag In receive operation, the BF bit is set when an address or data byte is loaded into SSPxBUF from SSPxSR. It is cleared when the SSPxBUF register is read. 19.4.11.2 SSPOV Status Flag In receive operation, the SSPOV bit is set when 8 bits are received into the SSPxSR and the BF flag bit is already set from a previous reception. 19.4.11.3 In Transmit mode, the BF bit (SSPxSTAT<0>) is set when the CPU writes to SSPxBUF and is cleared when all 8 bits are shifted out. 19.4.10.2 The user should verify that the WCOL bit is clear after each write to SSPxBUF to ensure the transfer is correct. In all cases, WCOL must be cleared in software. WCOL Status Flag If the user writes the SSPxBUF when a receive is already in progress (i.e., SSPxSR is still shifting in a data byte), the WCOL bit is set and the contents of the buffer are unchanged (the write doesn't occur). If the user writes the SSPxBUF when a transmit is already in progress (i.e., SSPxSR is still shifting out a data byte), the WCOL bit is set and the contents of the buffer are unchanged (the write doesn't occur) after 2 TCY after the SSPxBUF write. If SSPxBUF is rewritten within 2 TCY, the WCOL bit is set and SSPxBUF is updated. This may result in a corrupted transfer. DS39646B-page 236 Preliminary 2004 Microchip Technology Inc. 2004 Microchip Technology Inc. S Preliminary R/W PEN SEN BF (SSPxSTAT<0>) SSPxIF SCLx SDAx A6 A5 A4 A3 A2 A1 3 4 5 Cleared in software 2 6 7 8 After Start condition, SEN cleared by hardware SSPxBUF written 1 9 D7 1 SCLx held low while CPU responds to SSPxIF ACK = 0 R/W = 0 SSPxBUF written with 7-bit address and R/W, start transmit A7 Transmit Address to Slave 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 SSPxBUF is written in software Cleared in software service routine from MSSP interrupt 2 D6 Transmitting Data or Second Half of 10-bit Address P ACKSTAT in SSPxCON2 = 1 Cleared in software 9 ACK From slave, clear ACKSTAT bit SSPxCON2<6> FIGURE 19-21: SEN = 0 Write SSPxCON2<0> (SEN = 1), Start condition begins PIC18F8722 FAMILY I 2CTM MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS) DS39646B-page 237 DS39646B-page 238 S Preliminary ACKEN SSPOV BF (SSPxSTAT<0>) SDAx = 0, SCLx = 1, while CPU responds to SSPxIF SSPxIF SCLx SDAx 1 A7 2 4 5 6 Cleared in software 3 A6 A5 A4 A3 A2 Transmit Address to Slave 7 A1 8 9 R/W = 0 ACK 2 3 5 6 7 8 D0 9 ACK 2 3 4 5 6 7 Cleared in software Set SSPxIF interrupt at end of Acknowledge sequence Data shifted in on falling edge of CLK 1 Cleared in software Set SSPxIF at end of receive 9 ACK is not sent ACK P Set SSPxIF interrupt at end of Acknowledge sequence Bus master terminates transfer Set P bit (SSPxSTAT<4>) and SSPxIF PEN bit = 1 written here SSPOV is set because SSPxBUF is still full 8 D0 RCEN cleared automatically Set ACKEN, start Acknowledge sequence, SDAx = ACKDT = 1 D7 D6 D5 D4 D3 D2 D1 Receiving Data from Slave RCEN = 1, start next receive ACK from master, SDAx = ACKDT = 0 Last bit is shifted into SSPxSR and contents are unloaded into SSPxBUF Cleared in software Set SSPxIF interrupt at end of receive 4 Cleared in software 1 D7 D6 D5 D4 D3 D2 D1 Receiving Data from Slave RCEN cleared automatically Master configured as a receiver by programming SSPxCON2<3> (RCEN = 1) FIGURE 19-22: SEN = 0 Write to SSPxBUF occurs here, ACK from Slave start XMIT Write to SSPxCON2<0> (SEN = 1), begin Start condition Write to SSPxCON2<4> to start Acknowledge sequence, SDAx = ACKDT (SSPxCON2<5>) = 0 PIC18F8722 FAMILY I 2CTM MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS) 2004 Microchip Technology Inc. PIC18F8722 FAMILY 19.4.12 ACKNOWLEDGE SEQUENCE TIMING 19.4.13 A Stop bit is asserted on the SDAx pin at the end of a receive/transmit by setting the Stop Sequence Enable bit, PEN (SSPxCON2<2>). At the end of a receive/transmit, the SCLx line is held low after the falling edge of the ninth clock. When the PEN bit is set, the master will assert the SDAx line low. When the SDAx line is sampled low, the Baud Rate Generator is reloaded and counts down to `0'. When the Baud Rate Generator times out, the SCLx pin will be brought high and one TBRG (Baud Rate Generator rollover count) later, the SDAx pin will be deasserted. When the SDAx pin is sampled high while SCLx is high, the P bit (SSPxSTAT<4>) is set. A TBRG later, the PEN bit is cleared and the SSPxIF bit is set (Figure 19-24). An Acknowledge sequence is enabled by setting the Acknowledge Sequence Enable bit, ACKEN (SSPxCON2<4>). When this bit is set, the SCLx pin is pulled low and the contents of the Acknowledge data bit are presented on the SDAx pin. If the user wishes to generate an Acknowledge, then the ACKDT bit should be cleared. If not, the user should set the ACKDT bit before starting an Acknowledge sequence. The Baud Rate Generator then counts for one rollover period (TBRG) and the SCLx pin is deasserted (pulled high). When the SCLx pin is sampled high (clock arbitration), the Baud Rate Generator counts for TBRG. The SCLx pin is then pulled low. Following this, the ACKEN bit is automatically cleared, the Baud Rate Generator is turned off and the MSSP module then goes into an inactive state (Figure 19-23). 19.4.12.1 19.4.13.1 WCOL Status Flag If the user writes the SSPxBUF when a Stop sequence is in progress, then the WCOL bit is set and the contents of the buffer are unchanged (the write doesn't occur). WCOL Status Flag If the user writes the SSPxBUF when an Acknowledge sequence is in progress, then WCOL is set and the contents of the buffer are unchanged (the write doesn't occur). FIGURE 19-23: STOP CONDITION TIMING ACKNOWLEDGE SEQUENCE WAVEFORM Acknowledge sequence starts here, write to SSPxCON2, ACKEN = 1, ACKDT = 0 ACKEN automatically cleared TBRG TBRG SDAx D0 SCLx 8 ACK 9 SSPxIF SSPxIF set at the end of receive Cleared in software Cleared in software SSPxIF set at the end of Acknowledge sequence Note: TBRG = one Baud Rate Generator period. FIGURE 19-24: STOP CONDITION RECEIVE OR TRANSMIT MODE SCLx = 1 for TBRG, followed by SDAx = 1 for TBRG after SDAx sampled high. P bit (SSPxSTAT<4>) is set. Write to SSPxCON2, set PEN PEN bit (SSPxCON2<2>) is cleared by hardware and the SSPxIF bit is set Falling edge of 9th clock TBRG SCLx SDAx ACK P TBRG TBRG TBRG SCLx brought high after TBRG SDAx asserted low before rising edge of clock to setup Stop condition Note: TBRG = one Baud Rate Generator period. 2004 Microchip Technology Inc. Preliminary DS39646B-page 239 PIC18F8722 FAMILY 19.4.14 SLEEP OPERATION 19.4.17 2 While in Sleep mode, the I C module can receive addresses or data and when an address match or complete byte transfer occurs, wake the processor from Sleep (if the MSSP interrupt is enabled). 19.4.15 EFFECTS OF A RESET A Reset disables the MSSP module and terminates the current transfer. 19.4.16 MULTI-MASTER MODE In Multi-Master mode, the interrupt generation on the detection of the Start and Stop conditions allows the determination of when the bus is free. The Stop (P) and Start (S) bits are cleared from a Reset or when the MSSP module is disabled. Control of the I 2C bus may be taken when the P bit (SSPxSTAT<4>) is set, or the bus is Idle, with both the S and P bits clear. When the bus is busy, enabling the MSSP interrupt will generate the interrupt when the Stop condition occurs. In multi-master operation, the SDAx line must be monitored for arbitration to see if the signal level is the expected output level. This check is performed in hardware with the result placed in the BCLxIF bit. The states where arbitration can be lost are: * * * * * Address Transfer Data Transfer A Start Condition A Repeated Start Condition An Acknowledge Condition MULTI -MASTER COMMUNICATION, BUS COLLISION AND BUS ARBITRATION Multi-Master mode support is achieved by bus arbitration. When the master outputs address/data bits onto the SDAx pin, arbitration takes place when the master outputs a `1' on SDAx, by letting SDAx float high and another master asserts a `0'. When the SCLx pin floats high, data should be stable. If the expected data on SDAx is a `1' and the data sampled on the SDAx pin = 0, then a bus collision has taken place. The master will set the Bus Collision Interrupt Flag, BCLxIF and reset the I2C port to its Idle state (Figure 19-25). If a transmit was in progress when the bus collision occurred, the transmission is halted, the BF flag is cleared, the SDAx and SCLx lines are deasserted and the SSPxBUF can be written to. When the user services the bus collision Interrupt Service Routine and if the I2C bus is free, the user can resume communication by asserting a Start condition. If a Start, Repeated Start, Stop or Acknowledge condition was in progress when the bus collision occurred, the condition is aborted, the SDAx and SCLx lines are deasserted and the respective control bits in the SSPxCON2 register are cleared. When the user services the bus collision Interrupt Service Routine and if the I2C bus is free, the user can resume communication by asserting a Start condition. The master will continue to monitor the SDAx and SCLx pins. If a Stop condition occurs, the SSPxIF bit will be set. A write to the SSPxBUF will start the transmission of data at the first data bit regardless of where the transmitter left off when the bus collision occurred. In Multi-Master mode, the interrupt generation on the detection of Start and Stop conditions allows the determination of when the bus is free. Control of the I2C bus can be taken when the P bit is set in the SSPxSTAT register, or the bus is Idle and the S and P bits are cleared. FIGURE 19-25: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE Data changes while SCLx = 0 SDAx line pulled low by another source SDAx released by master Sample SDAx. While SCLx is high, data doesn't match what is driven by the master. Bus collision has occurred. SDAx SCLx Set bus collision interrupt (BCLxIF) BCLxIF DS39646B-page 240 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY 19.4.17.1 Bus Collision During a Start Condition During a Start condition, a bus collision occurs if: a) b) SDAx or SCLx are sampled low at the beginning of the Start condition (Figure 19-26). SCLx is sampled low before SDAx is asserted low (Figure 19-27). During a Start condition, both the SDAx and the SCLx pins are monitored. If the SDAx pin is sampled low during this count, the BRG is reset and the SDAx line is asserted early (Figure 19-28). If, however, a `1' is sampled on the SDAx pin, the SDAx pin is asserted low at the end of the BRG count. The Baud Rate Generator is then reloaded and counts down to `0'. If the SCLx pin is sampled as `0' during this time, a bus collision does not occur. At the end of the BRG count, the SCLx pin is asserted low. Note: If the SDAx pin is already low, or the SCLx pin is already low, then all of the following occur: * the Start condition is aborted, * the BCLxIF flag is set and * the MSSP module is reset to its inactive state (Figure 19-26). The Start condition begins with the SDAx and SCLx pins deasserted. When the SDAx pin is sampled high, the Baud Rate Generator is loaded from SSPxADD<6:0> and counts down to `0'. If the SCLx pin is sampled low while SDAx is high, a bus collision occurs because it is assumed that another master is attempting to drive a data `1' during the Start condition. FIGURE 19-26: The reason that bus collision is not a factor during a Start condition is that no two bus masters can assert a Start condition at the exact same time. Therefore, one master will always assert SDAx before the other. This condition does not cause a bus collision because the two masters must be allowed to arbitrate the first address following the Start condition. If the address is the same, arbitration must be allowed to continue into the data portion, Repeated Start or Stop conditions. BUS COLLISION DURING START CONDITION (SDAx ONLY) SDAx goes low before the SEN bit is set. Set BCLxIF, S bit and SSPxIF set because SDAx = 0, SCLx = 1. SDAx SCLx Set SEN, enable Start condition if SDAx = 1, SCLx = 1 SEN cleared automatically because of bus collision. MSSP module reset into Idle state. SEN BCLxIF SDAx sampled low before Start condition. Set BCLxIF. S bit and SSPxIF set because SDAx = 0, SCLx = 1. SSPxIF and BCLxIF are cleared in software S SSPxIF SSPxIF and BCLxIF are cleared in software 2004 Microchip Technology Inc. Preliminary DS39646B-page 241 PIC18F8722 FAMILY FIGURE 19-27: BUS COLLISION DURING START CONDITION (SCLx = 0) SDAx = 0, SCLx = 1 TBRG TBRG SDAx Set SEN, enable Start sequence if SDAx = 1, SCLx = 1 SCLx SCLx = 0 before SDAx = 0, bus collision occurs. Set BCLxIF. SEN SCLx = 0 before BRG time-out, bus collision occurs. Set BCLxIF. BCLxIF Interrupt cleared in software S `0' `0' SSPxIF `0' `0' FIGURE 19-28: BRG RESET DUE TO SDAx ARBITRATION DURING START CONDITION SDAx = 0, SCLx = 1 Set S Less than TBRG SDAx SCLx TBRG SDAx pulled low by other master. Reset BRG and assert SDAx. S SCLx pulled low after BRG time-out SEN BCLxIF Set SSPxIF Set SEN, enable START sequence if SDAx = 1, SCLx = 1 `0' S SSPxIF SDAx = 0, SCLx = 1, set SSPxIF DS39646B-page 242 Preliminary Interrupts cleared in software 2004 Microchip Technology Inc. PIC18F8722 FAMILY 19.4.17.2 Bus Collision During a Repeated Start Condition If SDAx is low, a bus collision has occurred (i.e., another master is attempting to transmit a data `0', Figure 19-29). If SDAx is sampled high, the BRG is reloaded and begins counting. If SDAx goes from high-to-low before the BRG times out, no bus collision occurs because no two masters can assert SDAx at exactly the same time. During a Repeated Start condition, a bus collision occurs if: a) b) A low level is sampled on SDAx when SCLx goes from low level to high level. SCLx goes low before SDAx is asserted low, indicating that another master is attempting to transmit a data `1'. If SCLx goes from high-to-low before the BRG times out and SDAx has not already been asserted, a bus collision occurs. In this case, another master is attempting to transmit a data `1' during the Repeated Start condition (see Figure 19-30). When the user deasserts SDAx and the pin is allowed to float high, the BRG is loaded with SSPxADD<6:0> and counts down to `0'. The SCLx pin is then deasserted and when sampled high, the SDAx pin is sampled. FIGURE 19-29: If, at the end of the BRG time-out, both SCLx and SDAx are still high, the SDAx pin is driven low and the BRG is reloaded and begins counting. At the end of the count, regardless of the status of the SCLx pin, the SCLx pin is driven low and the Repeated Start condition is complete. BUS COLLISION DURING A REPEATED START CONDITION (CASE 1) SDAx SCLx Sample SDAx when SCLx goes high. If SDAx = 0, set BCLxIF and release SDAx and SCLx. RSEN BCLxIF Cleared in software `0' S `0' SSPxIF FIGURE 19-30: BUS COLLISION DURING REPEATED START CONDITION (CASE 2) TBRG TBRG SDAx SCLx BCLxIF SCLx goes low before SDAx, set BCLxIF. Release SDAx and SCLx. Interrupt cleared in software RSEN `0' S SSPxIF 2004 Microchip Technology Inc. Preliminary DS39646B-page 243 PIC18F8722 FAMILY 19.4.17.3 Bus Collision During a Stop Condition The Stop condition begins with SDAx asserted low. When SDAx is sampled low, the SCLx pin is allowed to float. When the pin is sampled high (clock arbitration), the Baud Rate Generator is loaded with SSPxADD<6:0> and counts down to `0'. After the BRG times out, SDAx is sampled. If SDAx is sampled low, a bus collision has occurred. This is due to another master attempting to drive a data `0' (Figure 19-31). If the SCLx pin is sampled low before SDAx is allowed to float high, a bus collision occurs. This is another case of another master attempting to drive a data `0' (Figure 19-32). Bus collision occurs during a Stop condition if: a) b) After the SDAx pin has been deasserted and allowed to float high, SDAx is sampled low after the BRG has timed out. After the SCLx pin is deasserted, SCLx is sampled low before SDAx goes high. FIGURE 19-31: BUS COLLISION DURING A STOP CONDITION (CASE 1) TBRG TBRG SDAx sampled low after TBRG, set BCLxIF TBRG SDAx SDAx asserted low SCLx PEN BCLxIF P `0' SSPxIF `0' FIGURE 19-32: BUS COLLISION DURING A STOP CONDITION (CASE 2) TBRG TBRG TBRG SDAx SCLx goes low before SDAx goes high, set BCLxIF Assert SDAx SCLx PEN BCLxIF P `0' SSPxIF `0' DS39646B-page 244 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY TABLE 19-4: Name REGISTERS ASSOCIATED WITH I2CTM OPERATION Bit 7 Bit 6 Bit 5 Bit 4 Bit 2 Bit 1 Bit 0 Reset Values on page INT0IE RBIE TMR0IF INT0IF RBIF 57 PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 60 PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 60 IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 60 INTCON GIE/GIEH PEIE/GIEL TMR0IE Bit 3 PIR2 OSCFIF CMIF -- EEIF BCL1IF HLVDIF TMR3IF CCP2IF 60 PIE2 OSCFIE CMIE -- EEIE BCL1IE HLVDIE TMR3IE CCP2IE 60 IPR2 OSCFIP CMIP -- EEIP BCL1IP HLVDIP TMR3IP CCP2IP 60 PIR3 SSP2IF BCL2IF RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF 60 PIE3 SSP2IE BCL2IE RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE 60 IPR3 SSP2IP BCL2IP RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP 60 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 60 TRISD TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 60 SSP1BUF MSSP1 Receive Buffer/Transmit Register SSP2BUF MSSP2 Receive Buffer/Transmit Register 2C 58 61 SSP1ADD MSSP1 Address Register in I Master mode. I2C 58 SSP2ADD MSSP2 Address Register in I2C Slave mode. MSSP2 Baud Rate Reload Register in I2C Master mode. 61 TMR2 Timer2 Register 58 PR2 Timer2 Period Register Slave mode. MSSP1 Baud Rate Reload Register in 58 SSP1CON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 58 SSP1CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 58 S R/W UA BF 58 61 SSP1STAT SMP CKE D/A P SSP2CON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 SSP2CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 61 SSP2STAT SMP CKE D/A P S R/W UA BF 61 Legend: -- = unimplemented, read as `0'. Shaded cells are not used by the MSSP module in I2C mode. 2004 Microchip Technology Inc. Preliminary DS39646B-page 245 PIC18F8722 FAMILY NOTES: DS39646B-page 246 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY 20.0 ENHANCED UNIVERSAL SYNCHRONOUS RECEIVER TRANSMITTER (EUSART) The Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) module is one of two serial I/O modules. (Generically, the USART is also known as a Serial Communications Interface or SCI.) The EUSART can be configured as a full-duplex asynchronous system that can communicate with peripheral devices, such as CRT terminals and personal computers. It can also be configured as a halfduplex synchronous system that can communicate with peripheral devices, such as A/D or D/A integrated circuits, serial EEPROMs, etc. The Enhanced USART module implements additional features, including automatic baud rate detection and calibration, automatic wake-up on Sync Break reception and 12-bit Break Character transmit. These make it ideally suited for use in Local Interconnect Network bus (LIN bus) systems. The EUSART can be configured in the following modes: * Asynchronous (full duplex) with: - Auto-Wake-up on Character Reception - Auto-Baud Calibration - 12-bit Break Character Transmission * Synchronous - Master (half duplex) with Selectable Clock Polarity * Synchronous - Slave (half duplex) with Selectable Clock Polarity The pins of EUSART1 and EUSART2 are multiplexed with the functions of PORTC (RC6/TX1/CK1 and RC7/ RX1/DT1) and PORTG (RG1/TX2/CK2 and RG2/RX2/ DT2), respectively. In order to configure these pins as an EUSART: * For EUSART1: - bit SPEN (RCSTA1<7>) must be set (= 1) - bit TRISC<7> must be set (= 1) - bit TRISC<6> must be cleared (= 0) for Asynchronous and Synchronous Master modes - bit TRISC<6> must be set (= 1) for Synchronous Slave mode * For EUSART2: - bit SPEN (RCSTA2<7>) must be set (= 1) - bit TRISG<2> must be set (= 1) - bit TRISG<1> must be cleared (= 0) for Asynchronous and Synchronous Master modes - bit TRISC<6> must be set (= 1) for Synchronous Slave mode Note: The operation of each Enhanced USART module is controlled through three registers: * Transmit Status and Control (TXSTAx) * Receive Status and Control (RCSTAx) * Baud Rate Control (BAUDCONx) These are detailed on the following pages in Register 20-1, Register 20-2 and Register 20-3, respectively. Note: 2004 Microchip Technology Inc. The EUSART control will automatically reconfigure the pin from input to output as needed. Preliminary Throughout this section, references to register and bit names that may be associated with a specific EUSART module are referred to generically by the use of `x' in place of the specific module number. Thus, "RCSTAx" might refer to the Receive Status register for either EUSART1 or EUSART2 DS39646B-page 247 PIC18F8722 FAMILY REGISTER 20-1: TXSTAx: TRANSMIT STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-1 R/W-0 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D bit 7 bit 0 bit 7 CSRC: Clock Source Select bit Asynchronous mode: Don't care. Synchronous mode: 1 = Master mode (clock generated internally from BRG) 0 = Slave mode (clock from external source) bit 6 TX9: 9-bit Transmit Enable bit 1 = Selects 9-bit transmission 0 = Selects 8-bit transmission bit 5 TXEN: Transmit Enable bit 1 = Transmit enabled 0 = Transmit disabled Note: SREN/CREN overrides TXEN in Sync mode. bit 4 SYNC: EUSART Mode Select bit 1 = Synchronous mode 0 = Asynchronous mode bit 3 SENDB: Send Break Character bit Asynchronous mode: 1 = Send Sync Break on next transmission (cleared by hardware upon completion) 0 = Sync Break transmission completed Synchronous mode: Don't care. bit 2 BRGH: High Baud Rate Select bit Asynchronous mode: 1 = High speed 0 = Low speed Synchronous mode: Unused in this mode. bit 1 TRMT: Transmit Shift Register Status bit 1 = TSRx empty 0 = TSRx full bit 0 TX9D: 9th bit of Transmit Data Can be address/data bit or a parity bit. Legend: DS39646B-page 248 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared Preliminary x = Bit is unknown 2004 Microchip Technology Inc. PIC18F8722 FAMILY REGISTER 20-2: RCSTAx: RECEIVE STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x SPEN RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit 0 bit 7 SPEN: Serial Port Enable bit 1 = Serial port enabled (configures RXx/DTx and TXx/CKx pins as serial port pins) 0 = Serial port disabled (held in Reset) bit 6 RX9: 9-bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception bit 5 SREN: Single Receive Enable bit Asynchronous mode: Don't care. Synchronous mode - Master: 1 = Enables single receive 0 = Disables single receive This bit is cleared after reception is complete. Synchronous mode - Slave: Don't care. bit 4 CREN: Continuous Receive Enable bit Asynchronous mode: 1 = Enables receiver 0 = Disables receiver Synchronous mode: 1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN) 0 = Disables continuous receive bit 3 ADDEN: Address Detect Enable bit Asynchronous mode 9-bit (RX9 = 1): 1 = Enables address detection, enables interrupt and loads the receive buffer when RSRx<8> is set 0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit Asynchronous mode 9-bit (RX9 = 0): Don't care. bit 2 FERR: Framing Error bit 1 = Framing error (can be updated by reading RCREGx register and receiving next valid byte) 0 = No framing error bit 1 OERR: Overrun Error bit 1 = Overrun error (can be cleared by clearing bit CREN) 0 = No overrun error bit 0 RX9D: 9th bit of Received Data This can be address/data bit or a parity bit and must be calculated by user firmware. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared 2004 Microchip Technology Inc. Preliminary x = Bit is unknown DS39646B-page 249 PIC18F8722 FAMILY REGISTER 20-3: BAUDCONx: BAUD RATE CONTROL REGISTER R/W-0 R-1 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 ABDOVF RCIDL -- SCKP BRG16 -- WUE ABDEN bit 7 bit 0 bit 7 ABDOVF: Auto-Baud Acquisition Rollover Status bit 1 = A BRG rollover has occurred during Auto-Baud Rate Detect mode (must be cleared in software) 0 = No BRG rollover has occurred bit 6 RCIDL: Receive Operation Idle Status bit 1 = Receive operation is inactive 0 = Receive operation is active bit 5 Unimplemented: Read as `0' bit 4 SCKP: Synchronous Clock Polarity Select bit Asynchronous mode: Unused in this mode. Synchronous mode: 1 = Idle state for clock (CKx) is a high level 0 = Idle state for clock (CKx) is a low level bit 3 BRG16: 16-bit Baud Rate Register Enable bit 1 = 16-bit Baud Rate Generator - SPBRGHx and SPBRGx 0 = 8-bit Baud Rate Generator - SPBRGx only (Compatible mode), SPBRGHx value ignored bit 2 Unimplemented: Read as `0' bit 1 WUE: Wake-up Enable bit Asynchronous mode: 1 = EUSART will continue to sample the RXx pin - interrupt generated on falling edge; bit cleared in hardware on following rising edge 0 = RXx pin not monitored or rising edge detected Synchronous mode: Unused in this mode. bit 0 ABDEN: Auto-Baud Detect Enable bit Asynchronous mode: 1 = Enable baud rate measurement on the next character. Requires reception of a Sync field (55h); cleared in hardware upon completion. 0 = Baud rate measurement disabled or completed Synchronous mode: Unused in this mode. Legend: DS39646B-page 250 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared Preliminary x = Bit is unknown 2004 Microchip Technology Inc. PIC18F8722 FAMILY 20.1 Baud Rate Generator (BRG) The BRG is a dedicated 8-bit or 16-bit generator that supports both the Asynchronous and Synchronous modes of the EUSART. By default, the BRG operates in 8-bit mode; setting the BRG16 bit (BAUDCONx<3>) selects 16-bit mode. The SPBRGHx:SPBRGx register pair controls the period of a free running timer. In Asynchronous mode, bits BRGH (TXSTAx<2>) and BRG16 (BAUDCONx<3>) also control the baud rate. In Synchronous mode, BRGH is ignored. Table 20-1 shows the formula for computation of the baud rate for different EUSART modes which only apply in Master mode (internally generated clock). Given the desired baud rate and FOSC, the nearest integer value for the SPBRGHx:SPBRGx registers can be calculated using the formulas in Table 20-1. From this, the error in baud rate can be determined. An example calculation is shown in Example 20-1. Typical baud rates and error values for the various Asynchronous modes are shown in Table 20-2. It may be TABLE 20-1: advantageous to use the high baud rate (BRGH = 1) or the 16-bit BRG to reduce the baud rate error, or achieve a slow baud rate for a fast oscillator frequency. Writing a new value to the SPBRGHx:SPBRGx registers causes the BRG timer to be reset (or cleared). This ensures the BRG does not wait for a timer overflow before outputting the new baud rate. 20.1.1 OPERATION IN POWER-MANAGED MODES The device clock is used to generate the desired baud rate. When one of the power-managed modes is entered, the new clock source may be operating at a different frequency. This may require an adjustment to the value in the SPBRGx register pair. 20.1.2 SAMPLING The data on the RXx pin (either RC7/RX1/DT1 or RG2/ RX2/DT2) is sampled three times by a majority detect circuit to determine if a high or a low level is present at the RXx pin. BAUD RATE FORMULAS Configuration Bits BRG/EUSART Mode Baud Rate Formula 8-bit/Asynchronous FOSC/[64 (n + 1)] SYNC BRG16 BRGH 0 0 0 0 0 1 8-bit/Asynchronous 0 1 0 16-bit/Asynchronous 0 1 1 16-bit/Asynchronous 1 0 x 8-bit/Synchronous 1 1 x 16-bit/Synchronous FOSC/[16 (n + 1)] FOSC/[4 (n + 1)] Legend: x = Don't care, n = value of SPBRGHx:SPBRGx register pair 2004 Microchip Technology Inc. Preliminary DS39646B-page 251 PIC18F8722 FAMILY EXAMPLE 20-1: CALCULATING BAUD RATE ERROR For a device with FOSC of 16 MHz, desired baud rate of 9600, Asynchronous mode, 8-bit BRG: Desired Baud Rate = FOSC/(64 ([SPBRGHx:SPBRGx] + 1)) Solving for SPBRGHx:SPBRGx: X = ((FOSC/Desired Baud Rate)/64) - 1 = ((16000000/9600)/64) - 1 = [25.042] = 25 Calculated Baud Rate = 16000000/(64 (25 + 1)) = 9615 Error = (Calculated Baud Rate - Desired Baud Rate)/Desired Baud Rate = (9615 - 9600)/9600 = 0.16% TABLE 20-2: Name TXSTAx RCSTAx BAUDCONx REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 59 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 59 ABDOVF RCIDL -- SCKP BRG16 -- WUE ABDEN 61 SPBRGHx EUSARTx Baud Rate Generator Register High Byte 59 SPBRGx EUSARTx Baud Rate Generator Register Low Byte 59 Legend: -- = unimplemented, read as `0'. Shaded cells are not used by the BRG. DS39646B-page 252 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY TABLE 20-3: BAUD RATES FOR ASYNCHRONOUS MODES SYNC = 0, BRGH = 0, BRG16 = 0 BAUD RATE (K) FOSC = 40.000 MHz FOSC = 20.000 MHz Actual Rate (K) FOSC = 10.000 MHz Actual Rate (K) FOSC = 8.000 MHz Actual Rate (K) Actual Rate (K) % Error 0.3 -- -- -- -- -- -- -- -- -- -- -- -- 1.2 -- -- -- 1.221 1.73 255 1.202 0.16 129 1201 -0.16 103 2.4 2.441 1.73 255 2.404 0.16 129 2.404 0.16 64 2403 -0.16 51 9.6 9.615 0.16 64 9.766 1.73 31 9.766 1.73 15 9615 -0.16 12 -- SPBRG value (decimal) % Error SPBRG value (decimal) % Error SPBRG value (decimal) % Error SPBRG value (decimal) 19.2 19.531 1.73 31 19.531 1.73 15 19.531 1.73 7 -- -- 57.6 56.818 -1.36 10 62.500 8.51 4 52.083 -9.58 2 -- -- -- 115.2 125.000 8.51 4 104.167 -9.58 2 78.125 -32.18 1 -- -- -- SYNC = 0, BRGH = 0, BRG16 = 0 BAUD RATE (K) FOSC = 4.000 MHz FOSC = 2.000 MHz Actual Rate (K) % Error 207 300 -0.16 51 1201 -0.16 0.16 25 2403 Actual Rate (K) % Error 0.3 0.300 0.16 1.2 1.202 0.16 2.4 2.404 SPBRG value (decimal) FOSC = 1.000 MHz Actual Rate (K) % Error 103 300 -0.16 51 25 1201 -0.16 12 -0.16 12 -- -- -- SPBRG value (decimal) SPBRG value (decimal) 9.6 8.929 -6.99 6 -- -- -- -- -- -- 19.2 20.833 8.51 2 -- -- -- -- -- -- 57.6 62.500 8.51 0 -- -- -- -- -- -- 115.2 62.500 -45.75 0 -- -- -- -- -- -- SYNC = 0, BRGH = 1, BRG16 = 0 BAUD RATE (K) FOSC = 40.000 MHz FOSC = 20.000 MHz (decimal) Actual Rate (K) % Error -- -- -- -- -- -- -- -- -- 9.6 9.766 1.73 19.2 19.231 0.16 Actual Rate (K) % Error 0.3 -- 1.2 -- 2.4 FOSC = 10.000 MHz (decimal) Actual Rate (K) % Error -- -- -- -- -- -- -- -- -- 255 9.615 0.16 129 19.231 0.16 SPBRG value FOSC = 8.000 MHz (decimal) Actual Rate (K) % Error -- -- -- -- -- -- -- -- -- 2.441 1.73 255 2403 -0.16 207 129 9.615 0.16 64 9615 -0.16 51 64 19.531 1.73 31 19230 -0.16 25 SPBRG value SPBRG value SPBRG value (decimal) -- 57.6 58.140 0.94 42 56.818 -1.36 21 56.818 -1.36 10 55555 3.55 8 115.2 113.636 -1.36 21 113.636 -1.36 10 125.000 8.51 4 -- -- -- SYNC = 0, BRGH = 1, BRG16 = 0 BAUD RATE (K) FOSC = 4.000 MHz FOSC = 2.000 MHz (decimal) Actual Rate (K) % Error -- 0.16 -- 207 -- 1201 0.16 103 Actual Rate (K) % Error 0.3 1.2 -- 1.202 2.4 2.404 SPBRG value FOSC = 1.000 MHz (decimal) Actual Rate (K) % Error -- -0.16 -- 103 300 1201 -0.16 -0.16 207 51 2403 -0.16 51 2403 -0.16 25 SPBRG value SPBRG value (decimal) 9.6 9.615 0.16 25 9615 -0.16 12 -- -- -- 19.2 19.231 0.16 12 -- -- -- -- -- -- 57.6 62.500 8.51 3 -- -- -- -- -- -- 115.2 125.000 8.51 1 -- -- -- -- -- -- 2004 Microchip Technology Inc. Preliminary DS39646B-page 253 PIC18F8722 FAMILY TABLE 20-3: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 0, BRG16 = 1 BAUD RATE (K) FOSC = 40.000 MHz FOSC = 20.000 MHz (decimal) Actual Rate (K) % Error 0.00 0.02 8332 2082 0.300 1.200 2.402 0.06 1040 Actual Rate (K) % Error 0.3 1.2 0.300 1.200 2.4 SPBRG value FOSC = 10.000 MHz (decimal) Actual Rate (K) % Error 0.02 -0.03 4165 1041 0.300 1.200 2.399 -0.03 520 SPBRG value FOSC = 8.000 MHz (decimal) Actual Rate (K) % Error 0.02 -0.03 2082 520 300 1201 -0.04 -0.16 1665 415 2.404 0.16 259 2403 -0.16 207 SPBRG value SPBRG value (decimal) 9.6 9.615 0.16 259 9.615 0.16 129 9.615 0.16 64 9615 -0.16 51 19.2 19.231 0.16 129 19.231 0.16 64 19.531 1.73 31 19230 -0.16 25 57.6 58.140 0.94 42 56.818 -1.36 21 56.818 -1.36 10 55555 3.55 8 115.2 113.636 -1.36 21 113.636 -1.36 10 125.000 8.51 4 -- -- -- SYNC = 0, BRGH = 0, BRG16 = 1 BAUD RATE (K) FOSC = 4.000 MHz (decimal) Actual Rate (K) % Error 832 300 -0.16 0.16 207 1201 0.16 103 2403 Actual Rate (K) % Error 0.300 0.04 1.2 1.202 2.4 2.404 0.3 FOSC = 2.000 MHz SPBRG value FOSC = 1.000 MHz (decimal) Actual Rate (K) % Error 415 300 -0.16 -0.16 103 1201 -0.16 51 -0.16 51 2403 -0.16 25 SPBRG value SPBRG value (decimal) 207 9.6 9.615 0.16 25 9615 -0.16 12 -- -- -- 19.2 19.231 0.16 12 -- -- -- -- -- -- 57.6 62.500 8.51 3 -- -- -- -- -- -- 115.2 125.000 8.51 1 -- -- -- -- -- -- SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD RATE (K) FOSC = 40.000 MHz FOSC = 20.000 MHz (decimal) Actual Rate (K) % Error 0.00 33332 0.300 0.00 8332 1.200 2.400 0.02 4165 9.606 0.06 1040 19.2 19.193 -0.03 520 57.6 57.803 0.35 172 115.2 114.943 -0.22 86 116.279 Actual Rate (K) % Error 0.3 0.300 1.2 1.200 2.4 9.6 SPBRG value FOSC = 10.000 MHz (decimal) Actual Rate (K) % Error 0.00 16665 0.300 0.00 0.02 4165 1.200 0.02 2.400 0.02 2082 2.402 9.596 -0.03 520 19.231 0.16 57.471 -0.22 0.94 FOSC = 8.000 MHz Actual Rate (K) % Error 8332 300 -0.01 6665 2082 1200 -0.04 1665 0.06 1040 2400 -0.04 832 9.615 0.16 259 9615 -0.16 207 259 19.231 0.16 129 19230 -0.16 103 86 58.140 0.94 42 57142 0.79 34 42 113.636 -1.36 21 117647 -2.12 16 SPBRG value SPBRG value (decimal) SPBRG value (decimal) SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD RATE (K) FOSC = 4.000 MHz Actual Rate (K) % Error 0.3 0.300 0.01 1.2 1.200 0.04 FOSC = 2.000 MHz (decimal) Actual Rate (K) % Error 3332 300 -0.04 832 1201 SPBRG value FOSC = 1.000 MHz (decimal) Actual Rate (K) % Error 1665 300 -0.04 832 -0.16 415 1201 -0.16 207 SPBRG value SPBRG value (decimal) 2.4 2.404 0.16 415 2403 -0.16 207 2403 -0.16 103 9.6 9.615 0.16 103 9615 -0.16 51 9615 -0.16 25 19.2 19.231 0.16 51 19230 -0.16 25 19230 -0.16 12 57.6 58.824 2.12 16 55555 3.55 8 -- -- -- 115.2 111.111 -3.55 8 -- -- -- -- -- -- DS39646B-page 254 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY 20.1.3 AUTO-BAUD RATE DETECT The Enhanced USART module supports the automatic detection and calibration of baud rate. This feature is active only in Asynchronous mode and while the WUE bit is clear. Note 1: If the WUE bit is set with the ABDEN bit, Auto-Baud Rate Detection will occur on the byte following the Break character. 2: It is up to the user to determine that the incoming character baud rate is within the range of the selected BRG clock source. Some combinations of oscillator frequency and EUSART baud rates are not possible due to bit error rates. Overall system timing and communication baud rates must be taken into consideration when using the Auto-Baud Rate Detection feature. The automatic baud rate measurement sequence (Figure 20-1) begins whenever a Start bit is received and the ABDEN bit is set. The calculation is self-averaging. In the Auto-Baud Rate Detect (ABD) mode, the clock to the BRG is reversed. Rather than the BRG clocking the incoming RXx signal, the RXx signal is timing the BRG. In ABD mode, the internal Baud Rate Generator is used as a counter to time the bit period of the incoming serial byte stream. Once the ABDEN bit is set, the state machine will clear the BRG and look for a Start bit. The Auto-Baud Rate Detect must receive a byte with the value 55h (ASCII "U", which is also the LIN bus Sync character) in order to calculate the proper bit rate. The measurement is taken over both a low and a high bit time in order to minimize any effects caused by asymmetry of the incoming signal. After a Start bit, the SPBRGx begins counting up, using the preselected clock source on the first rising edge of RXx. After eight bits on the RXx pin or the fifth rising edge, an accumulated value totalling the proper BRG period is left in the SPBRGHx:SPBRGx register pair. Once the 5th edge is seen (this should correspond to the Stop bit), the ABDEN bit is automatically cleared. If a rollover of the BRG occurs (an overflow from FFFFh to 0000h), the event is trapped by the ABDOVF status bit (BAUDCONx<7>). It is set in hardware by BRG rollovers and can be set or cleared by the user in software. ABD mode remains active after rollover events and the ABDEN bit remains set (Figure 20-2). TABLE 20-4: BRG16 BRGH BRG COUNTER CLOCK RATES BRG Counter Clock 0 0 FOSC/512 0 1 FOSC/128 1 0 FOSC/128 1 1 FOSC/32 Note: During the ABD sequence, SPBRGx and SPBRGHx are both used as a 16-bit counter, independent of BRG16 setting. 20.1.3.1 ABD and EUSART Transmission Since the BRG clock is reversed during ABD acquisition, the EUSART transmitter cannot be used during ABD. This means that whenever the ABDEN bit is set, TXREGx cannot be written to. Users should also ensure that ABDEN does not become set during a transmit sequence. Failing to do this may result in unpredictable EUSART operation. While calibrating the baud rate period, the BRG registers are clocked at 1/8th the preconfigured clock rate. Note that the BRG clock will be configured by the BRG16 and BRGH bits. Independent of the BRG16 bit setting, both the SPBRGx and SPBRGHx will be used as a 16-bit counter. This allows the user to verify that no carry occurred for 8-bit modes by checking for 00h in the SPBRGHx register. Refer to Table 20-4 for counter clock rates to the BRG. While the ABD sequence takes place, the EUSART state machine is held in Idle. The RCxIF interrupt is set once the fifth rising edge on RXx is detected. The value in the RCREGx needs to be read to clear the RCxIF interrupt. The contents of RCREGx should be discarded. 2004 Microchip Technology Inc. Preliminary DS39646B-page 255 PIC18F8722 FAMILY FIGURE 20-1: BRG Value AUTOMATIC BAUD RATE CALCULATION XXXXh RXx pin 0000h 001Ch Start Edge #1 Bit 1 Bit 0 Edge #2 Bit 3 Bit 2 Edge #3 Bit 5 Bit 4 Edge #4 Bit 7 Bit 6 Edge #5 Stop Bit BRG Clock Auto-Cleared Set by User ABDEN bit RCxIF bit (Interrupt) Read RCREGx SPBRGx XXXXh 1Ch SPBRGHx XXXXh 00h Note: The ABD sequence requires the EUSART module to be configured in Asynchronous mode and WUE = 0. FIGURE 20-2: BRG OVERFLOW SEQUENCE BRG Clock ABDEN bit RXx pin Start Bit 0 ABDOVF bit FFFFh BRG Value DS39646B-page 256 XXXXh 0000h 0000h Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY 20.2 EUSART Asynchronous Mode The Asynchronous mode of operation is selected by clearing the SYNC bit (TXSTAx<4>). In this mode, the EUSART uses standard Non-Return-to-Zero (NRZ) format (one Start bit, eight or nine data bits and one Stop bit). The most common data format is 8 bits. An on-chip dedicated 8-bit/16-bit Baud Rate Generator can be used to derive standard baud rate frequencies from the oscillator. The EUSART transmits and receives the LSb first. The EUSART's transmitter and receiver are functionally independent, but use the same data format and baud rate. The Baud Rate Generator produces a clock, either x16 or x64 of the bit shift rate depending on the BRGH and BRG16 bits (TXSTAx<2> and BAUDCONx<3>). Parity is not supported by the hardware, but can be implemented in software and stored as the 9th data bit. Once the TXREGx register transfers the data to the TSRx register (occurs in one TCY), the TXREGx register is empty and the TXxIF flag bit (PIR1<4>) is set. This interrupt can be enabled or disabled by setting or clearing the interrupt enable bit, TXxIE (PIE1<4>). TXxIF will be set regardless of the state of TXxIE; it cannot be cleared in software. TXxIF is also not cleared immediately upon loading TXREGx, but becomes valid in the second instruction cycle following the load instruction. Polling TXxIF immediately following a load of TXREGx will return invalid results. While TXxIF indicates the status of the TXREGx register, another bit, TRMT (TXSTAx<1>), shows the status of the TSRx register. TRMT is a read-only bit which is set when the TSRx register is empty. No interrupt logic is tied to this bit so the user has to poll this bit in order to determine if the TSRx register is empty. When operating in Asynchronous mode, the EUSART module consists of the following important elements: * * * * * * * Baud Rate Generator Sampling Circuit Asynchronous Transmitter Asynchronous Receiver Auto-Wake-up on Sync Break Character 12-bit Break Character Transmit Auto-Baud Rate Detection 20.2.1 2: Flag bit TXxIF is set when enable bit TXEN is set. To set up an Asynchronous Transmission: 1. 2. EUSART ASYNCHRONOUS TRANSMITTER The EUSART transmitter block diagram is shown in Figure 20-3. The heart of the transmitter is the Transmit (Serial) Shift Register (TSRx). The Shift register obtains its data from the Read/Write Transmit Buffer register, TXREGx. The TXREGx register is loaded with data in software. The TSRx register is not loaded until the Stop bit has been transmitted from the previous load. As soon as the Stop bit is transmitted, the TSRx is loaded with new data from the TXREGx register (if available). 2004 Microchip Technology Inc. Note 1: The TSRx register is not mapped in data memory so it is not available to the user. 3. 4. 5. 6. 7. 8. Preliminary Initialize the SPBRGHx:SPBRGx registers for the appropriate baud rate. Set or clear the BRGH and BRG16 bits, as required, to achieve the desired baud rate. Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN. If interrupts are desired, set enable bit TXxIE. If 9-bit transmission is desired, set transmit bit TX9. Can be used as address/data bit. Enable the transmission by setting bit TXEN which will also set bit TXxIF. If 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D. Load data to the TXREGx register (starts transmission). If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. DS39646B-page 257 PIC18F8722 FAMILY FIGURE 20-3: EUSART TRANSMIT BLOCK DIAGRAM Data Bus TXxIF TXREGx Register TXxIE 8 MSb LSb * * * (8) Pin Buffer and Control 0 TSRx Register TXx pin Interrupt TXEN Baud Rate CLK TRMT BRG16 SPBRGHx SPBRGx TX9 Baud Rate Generator FIGURE 20-4: SPEN TX9D ASYNCHRONOUS TRANSMISSION Write to TXREGx BRG Output (Shift Clock) Word 1 TXx (pin) Start bit FIGURE 20-5: bit 1 bit 7/8 Stop bit Word 1 TXxIF bit (Transmit Buffer Reg. Empty Flag) TRMT bit (Transmit Shift Reg. Empty Flag) bit 0 1 TCY Word 1 Transmit Shift Reg ASYNCHRONOUS TRANSMISSION (BACK TO BACK) Write to TXREGx Word 1 Word 2 BRG Output (Shift Clock) TXx (pin) TXxIF bit (Interrupt Reg. Flag) Start bit bit 0 1 TCY bit 1 Word 1 bit 7/8 Stop bit Start bit bit 0 Word 2 1 TCY TRMT bit (Transmit Shift Reg. Empty Flag) Word 1 Transmit Shift Reg. Word 2 Transmit Shift Reg. Note: This timing diagram shows two consecutive transmissions. DS39646B-page 258 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY TABLE 20-5: Name INTCON REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION Bit 7 Bit 6 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 57 PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 60 PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 60 IPR1 TRISC TRISG RCSTAx TXREGx TXSTAx GIE/GIEH PEIE/GIEL Bit 5 PSPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 60 TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 60 -- -- -- TRISG4 TRISG3 TRISG2 TRISG1 TRISG0 60 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 59 EUSARTx Transmit Register 59 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 59 BAUDCONx ABDOVF RCIDL -- SCKP BRG16 -- WUE ABDEN SPBRGHx EUSARTx Baud Rate Generator Register High Byte 61 SPBRGx EUSARTx Baud Rate Generator Register Low Byte 59 61 Legend: -- = unimplemented locations read as `0'. Shaded cells are not used for asynchronous transmission. 2004 Microchip Technology Inc. Preliminary DS39646B-page 259 PIC18F8722 FAMILY 20.2.2 EUSART ASYNCHRONOUS RECEIVER 20.2.3 The receiver block diagram is shown in Figure 20-6. The data is received on the RXx pin and drives the data recovery block. The data recovery block is actually a high-speed shifter operating at x16 times the baud rate, whereas the main receive serial shifter operates at the bit rate or at FOSC. This mode would typically be used in RS-232 systems. This mode would typically be used in RS-485 systems. To set up an Asynchronous Reception with Address Detect Enable: 1. Initialize the SPBRGHx:SPBRGx registers for the appropriate baud rate. Set or clear the BRGH and BRG16 bits, as required, to achieve the desired baud rate. 2. Enable the asynchronous serial port by clearing the SYNC bit and setting the SPEN bit. 3. If interrupts are required, set the RCEN bit and select the desired priority level with the RCxIP bit. 4. Set the RX9 bit to enable 9-bit reception. 5. Set the ADDEN bit to enable address detect. 6. Enable reception by setting the CREN bit. 7. The RCxIF bit will be set when reception is complete. The interrupt will be Acknowledged if the RCxIE and GIE bits are set. 8. Read the RCSTAx register to determine if any error occurred during reception, as well as read bit 9 of data (if applicable). 9. Read RCREGx to determine if the device is being addressed. 10. If any error occurred, clear the CREN bit. 11. If the device has been addressed, clear the ADDEN bit to allow all received data into the receive buffer and interrupt the CPU. To set up an Asynchronous Reception: 1. Initialize the SPBRGHx:SPBRGx registers for the appropriate baud rate. Set or clear the BRGH and BRG16 bits, as required, to achieve the desired baud rate. 2. Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN. 3. If interrupts are desired, set enable bit RCxIE. 4. If 9-bit reception is desired, set bit RX9. 5. Enable the reception by setting bit CREN. 6. Flag bit, RCxIF, will be set when reception is complete and an interrupt will be generated if enable bit, RCxIE, was set. 7. Read the RCSTAx register to get the 9th bit (if enabled) and determine if any error occurred during reception. 8. Read the 8-bit received data by reading the RCREGx register. 9. If any error occurred, clear the error by clearing enable bit CREN. 10. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. FIGURE 20-6: SETTING UP 9-BIT MODE WITH ADDRESS DETECT EUSART RECEIVE BLOCK DIAGRAM CREN OERR FERR x64 Baud Rate CLK BRG16 SPBRGHx SPBRGx Baud Rate Generator / 64 or / 16 or /4 RSRx Register MSb Stop (8) 7 * * * 1 LSb 0 Start RX9 Pin Buffer and Control Data Recovery RXx RX9D RCREGx Register FIFO SPEN 8 Interrupt RCxIF Data Bus RCxIE DS39646B-page 260 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY FIGURE 20-7: ASYNCHRONOUS RECEPTION Start bit RXx (pin) bit 0 bit 7/8 Stop bit bit 1 Start bit bit 0 Rcv Shift Reg Rcv Buffer Reg Stop bit Start bit bit 7/8 Stop bit Word 2 RCREGx Word 1 RCREGx Read Rcv Buffer Reg RCREGx bit 7/8 RCxIF (Interrupt Flag) OERR bit CREN Note: This timing diagram shows three words appearing on the RXx input. The RCREGx (receive buffer) is read after the third word causing the OERR (overrun) bit to be set. TABLE 20-6: Name INTCON REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION Bit 7 Bit 6 GIE/GIEH PEIE/GIEL Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 57 PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 60 PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 60 IPR1 TRISC TRISG RCSTAx RCREGx TXSTAx PSPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 60 TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 60 -- -- -- TRISG4 TRISG3 TRISG2 TRISG1 TRISG0 60 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 59 EUSARTx Receive Register CSRC BAUDCONx ABDOVF 59 TX9 TXEN SYNC SENDB BRGH TRMT TX9D 59 RCIDL -- SCKP BRG16 -- WUE ABDEN 61 SPBRGHx EUSARTx Baud Rate Generator Register High Byte 61 SPBRGx EUSARTx Baud Rate Generator Register Low Byte 59 Legend: -- = unimplemented locations read as `0'. Shaded cells are not used for asynchronous reception. 2004 Microchip Technology Inc. Preliminary DS39646B-page 261 PIC18F8722 FAMILY 20.2.4 AUTO-WAKE-UP ON SYNC BREAK CHARACTER During Sleep mode, all clocks to the EUSART are suspended. Because of this, the Baud Rate Generator is inactive and a proper byte reception cannot be performed. The auto-wake-up feature allows the controller to wake-up due to activity on the RXx/DTx line, while the EUSART is operating in Asynchronous mode. The auto-wake-up feature is enabled by setting the WUE bit (BAUDCONx<1>). Once set, the typical receive sequence on RXx/DTx is disabled and the EUSART remains in an Idle state, monitoring for a wake-up event independent of the CPU mode. A wake-up event consists of a high-to-low transition on the RXx/DTx line. (This coincides with the start of a Sync Break or a Wake-up Signal character for the LIN protocol.) Following a wake-up event, the module generates an RCxIF interrupt. The interrupt is generated synchronously to the Q clocks in normal operating modes (Figure 20-8) and asynchronously, if the device is in Sleep mode (Figure 20-9). The interrupt condition is cleared by reading the RCREGx register. The WUE bit is automatically cleared once a low-tohigh transition is observed on the RXx line following the wake-up event. At this point, the EUSART module is inactive and returns to normal operation. This signals to the user that the Sync Break event is over. 20.2.4.1 Special Considerations Using Auto-Wake-up Since auto-wake-up functions by sensing rising edge transitions on RXx/DTx, information with any state changes before the Stop bit may signal a false end-of- FIGURE 20-8: character and cause data or framing errors. To work properly, therefore, the initial character in the transmission must be all `0's. This can be 00h (8 bytes) for standard RS-232 devices or 000h (12 bits) for LIN bus. Oscillator start-up time must also be considered, especially in applications using oscillators with longer start-up intervals (i.e., XT or HS mode). The Sync Break (or Wake-up Signal) character must be of sufficient length and be followed by a sufficient interval to allow enough time for the selected oscillator to start and provide proper initialization of the EUSART. 20.2.4.2 Special Considerations Using the WUE Bit The timing of WUE and RCxIF events may cause some confusion when it comes to determining the validity of received data. As noted, setting the WUE bit places the EUSART in an inactive state. The wake-up event causes a receive interrupt by setting the RCxIF bit. The WUE bit is cleared after this when a rising edge is seen on RXx/DTx. The interrupt condition is then cleared by reading the RCREGx register. Ordinarily, the data in RCREGx will be dummy data and should be discarded. The fact that the WUE bit has been cleared (or is still set) and the RCxIF flag is set should not be used as an indicator of the integrity of the data in RCREGx. Users should consider implementing a parallel method in firmware to verify received data integrity. To assure that no actual data is lost, check the RCIDL bit to verify that a receive operation is not in process. If a receive operation is not occurring, the WUE bit may then be set just prior to entering the Sleep mode. AUTO-WAKE-UP BIT (WUE) TIMINGS DURING NORMAL OPERATION Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 Bit set by user Auto-Cleared WUE bit(1) RXx/DTx Line RCxIF Note 1: Cleared due to user read of RCREGx The EUSART remains inactive while the WUE bit is set. FIGURE 20-9: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 Bit set by user Auto-Cleared WUE bit(2) RXx/DTx Line Note 1 RCxIF Sleep Ends Sleep Command Executed Note 1: 2: Cleared due to user read of RCREGx If the wake-up event requires long oscillator warm-up time, the auto-clear of the WUE bit can occur before the oscillator is ready. This sequence should not depend on the presence of Q clocks. The EUSART remains inactive while the WUE bit is set. DS39646B-page 262 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY 20.2.5 BREAK CHARACTER SEQUENCE The EUSART module has the capability of sending the special Break character sequences that are required by the LIN bus standard. The Break character transmit consists of a Start bit, followed by twelve `0' bits and a Stop bit. The frame Break character is sent whenever the SENDB and TXEN bits (TXSTAx<3> and TXSTAx<5>) are set while the Transmit Shift register is loaded with data. Note that the value of data written to TXREGx will be ignored and all `0's will be transmitted. The SENDB bit is automatically reset by hardware after the corresponding Stop bit is sent. This allows the user to preload the transmit FIFO with the next transmit byte following the Break character (typically, the Sync character in the LIN specification). Note that the data value written to the TXREGx for the Break character is ignored. The write simply serves the purpose of initiating the proper sequence. The TRMT bit indicates when the transmit operation is active or Idle, just as it does during normal transmission. See Figure 20-10 for the timing of the Break character sequence. 20.2.5.1 Break and Sync Transmit Sequence The following sequence will send a message frame header made up of a Break, followed by an Auto-Baud Sync byte. This sequence is typical of a LIN bus master. 1. 2. 3. 4. 5. Configure the EUSART for the desired mode. Set the TXEN and SENDB bits to set up the Break character. Load the TXREGx with a dummy character to initiate transmission (the value is ignored). Write `55h' to TXREGx to load the Sync character into the transmit FIFO buffer. After the Break has been sent, the SENDB bit is reset by hardware. The Sync character now transmits in the preconfigured mode. When the TXREGx becomes empty, as indicated by the TXxIF, the next data byte can be written to TXREGx. 20.2.6 RECEIVING A BREAK CHARACTER The Enhanced USART module can receive a Break character in two ways. The first method forces configuration of the baud rate at a frequency of 9/13 the typical speed. This allows for the Stop bit transition to be at the correct sampling location (13 bits for Break versus Start bit and 8 data bits for typical data). The second method uses the auto-wake-up feature described in Section 20.2.4 "Auto-Wake-up on Sync Break Character". By enabling this feature, the EUSART will sample the next two transitions on RXx/ DTx, cause an RCxIF interrupt and receive the next data byte followed by another interrupt. Note that following a Break character, the user will typically want to enable the Auto-Baud Rate Detect feature. For both methods, the user can set the ABD bit once the TXxIF interrupt is observed. FIGURE 20-10: Write to TXREGx SEND BREAK CHARACTER SEQUENCE Dummy Write BRG Output (Shift Clock) TXx (pin) Start Bit Bit 0 Bit 1 Bit 11 Stop Bit Break TXxIF bit (Transmit Buffer Reg. Empty Flag) TRMT bit (Transmit Shift Reg. Empty Flag) SENDB sampled here Auto-Cleared SENDB (Transmit Shift Reg. Empty Flag) 2004 Microchip Technology Inc. Preliminary DS39646B-page 263 PIC18F8722 FAMILY 20.3 EUSART Synchronous Master Mode Once the TXREGx register transfers the data to the TSRx register (occurs in one TCY), the TXREGx is empty and the TXxIF flag bit is set. The interrupt can be enabled or disabled by setting or clearing the interrupt enable bit, TXxIE. TXxIF is set regardless of the state of enable bit TXxIE; it cannot be cleared in software. It will reset only when new data is loaded into the TXREGx register. The Synchronous Master mode is entered by setting the CSRC bit (TXSTAx<7>). In this mode, the data is transmitted in a half-duplex manner (i.e., transmission and reception do not occur at the same time). When transmitting data, the reception is inhibited and vice versa. Synchronous mode is entered by setting bit SYNC (TXSTAx<4>). In addition, enable bit SPEN (RCSTAx<7>) is set in order to configure the TXx and RXx pins to CKx (clock) and DTx (data) lines, respectively. While flag bit TXxIF indicates the status of the TXREGx register, another bit, TRMT (TXSTAx<1>), shows the status of the TSRx register. TRMT is a read-only bit which is set when the TSRx is empty. No interrupt logic is tied to this bit, so the user must poll this bit in order to determine if the TSRx register is empty. The TSRx is not mapped in data memory so it is not available to the user. The Master mode indicates that the processor transmits the master clock on the CKx line. Clock polarity is selected with the SCKP bit (BAUDCONx<4>); setting SCKP sets the Idle state on CKx as high, while clearing the bit sets the Idle state as low. This option is provided to support Microwire devices with this module. 20.3.1 To set up a Synchronous Master Transmission: 1. EUSART SYNCHRONOUS MASTER TRANSMISSION 2. 3. 4. 5. 6. The EUSART transmitter block diagram is shown in Figure 20-3. The heart of the transmitter is the Transmit (Serial) Shift Register (TSRx). The Shift register obtains its data from the Read/Write Transmit Buffer register, TXREGx. The TXREGx register is loaded with data in software. The TSRx register is not loaded until the last bit has been transmitted from the previous load. As soon as the last bit is transmitted, the TSRx is loaded with new data from the TXREGx (if available). FIGURE 20-11: 7. 8. Initialize the SPBRGHx:SPBRGx registers for the appropriate baud rate. Set or clear the BRG16 bit, as required, to achieve the desired baud rate. Enable the synchronous master serial port by setting bits SYNC, SPEN and CSRC. If interrupts are desired, set enable bit TXxIE. If 9-bit transmission is desired, set bit TX9. Enable the transmission by setting bit TXEN. If 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D. Start transmission by loading data to the TXREGx register. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. SYNCHRONOUS TRANSMISSION Q1 Q2 Q3Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 DTx bit 0 bit 1 bit 2 bit 7 bit 0 bit 1 bit 7 Word 2 Word 1 CKx pin (SCKP = 0) CKx pin (SCKP = 1) Write to TXREGx Reg Write Word 1 Write Word 2 TXxIF bit (Interrupt Flag) TRMT bit TXEN bit `1' Note: `1' Sync Master mode, SPBRGx = 0, continuous transmission of two 8-bit words. DS39646B-page 264 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY FIGURE 20-12: SYNCHRONOUS TRANSMISSION (THROUGH TXEN) DTx pin bit 0 bit 1 bit 2 bit 6 bit 7 CKx pin Write to TXREGx reg TXxIF bit TRMT bit TXEN bit TABLE 20-7: Name INTCON REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Bit 7 Bit 6 Bit 5 GIE/GIEH PEIE/GIEL TMR0IE Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page INT0IE RBIE TMR0IF INT0IF RBIF 57 PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 60 PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 60 IPR1 TRISC TRISG RCSTAx TXREGx TXSTAx PSPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 60 TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 60 -- -- -- TRISG4 TRISG3 TRISG2 TRISG1 TRISG0 60 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 59 EUSARTx Transmit Register CSRC BAUDCONx ABDOVF 59 TX9 TXEN SYNC SENDB BRGH TRMT TX9D RCIDL -- SCKP BRG16 -- WUE ABDEN 59 61 SPBRGHx EUSARTx Baud Rate Generator Register High Byte 61 SPBRGx EUSARTx Baud Rate Generator Register Low Byte 59 Legend: -- = unimplemented, read as `0'. Shaded cells are not used for synchronous master transmission. 2004 Microchip Technology Inc. Preliminary DS39646B-page 265 PIC18F8722 FAMILY 20.3.2 EUSART SYNCHRONOUS MASTER RECEPTION 3. 4. 5. 6. Ensure bits CREN and SREN are clear. If interrupts are desired, set enable bit RCxIE. If 9-bit reception is desired, set bit RX9. If a single reception is required, set bit SREN. For continuous reception, set bit CREN. 7. Interrupt flag bit, RCxIF, will be set when reception is complete and an interrupt will be generated if the enable bit, RCxIE, was set. 8. Read the RCSTAx register to get the 9th bit (if enabled) and determine if any error occurred during reception. 9. Read the 8-bit received data by reading the RCREGx register. 10. If any error occurred, clear the error by clearing bit CREN. 11. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. Once Synchronous mode is selected, reception is enabled by setting either the Single Receive Enable bit, SREN (RCSTAx<5>), or the Continuous Receive Enable bit, CREN (RCSTAx<4>). Data is sampled on the RXx pin on the falling edge of the clock. If enable bit SREN is set, only a single word is received. If enable bit CREN is set, the reception is continuous until CREN is cleared. If both bits are set, then CREN takes precedence. To set up a Synchronous Master Reception: 1. 2. Initialize the SPBRGHx:SPBRGx registers for the appropriate baud rate. Set or clear the BRG16 bit, as required, to achieve the desired baud rate. Enable the synchronous master serial port by setting bits SYNC, SPEN and CSRC. FIGURE 20-13: SYNCHRONOUS RECEPTION (MASTER MODE, SREN) Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 DTx pin bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 CKx pin (SCKP = 0) CKx pin (SCKP = 1) Write to bit SREN SREN bit CREN bit `0' `0' RCxIF bit (Interrupt) Read RCREGx Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0. DS39646B-page 266 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY TABLE 20-8: Name REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION Bit 7 INTCON Bit 6 GIE/GIEH PEIE/GIEL Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 57 PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 60 PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 60 PSPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 60 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 60 TRISG -- -- -- TRISG4 TRISG3 TRISG2 TRISG1 TRISG0 60 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 59 IPR1 RCSTAx RCREGx EUSARTx Receive Register TXSTAx BAUDCONx SPBRGHx SPBRGx Legend: 59 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 59 ABDOVF RCIDL -- SCKP BRG16 -- WUE ABDEN 61 EUSARTx Baud Rate Generator Register High Byte 61 EUSARTx Baud Rate Generator Register Low Byte 59 -- = unimplemented, read as `0'. Shaded cells are not used for synchronous master reception. 2004 Microchip Technology Inc. Preliminary DS39646B-page 267 PIC18F8722 FAMILY 20.4 EUSART Synchronous Slave Mode To set up a Synchronous Slave Transmission: 1. Synchronous Slave mode is entered by clearing bit, CSRC (TXSTAx<7>). This mode differs from the Synchronous Master mode in that the shift clock is supplied externally at the CKx pin (instead of being supplied internally in Master mode). This allows the device to transfer or receive data while in any low-power mode. 20.4.1 2. 3. 4. 5. 6. EUSART SYNCHRONOUS SLAVE TRANSMISSION 7. The operation of the Synchronous Master and Slave modes is identical, except in the case of Sleep mode. 8. If two words are written to the TXREGx and then the SLEEP instruction is executed, the following will occur: a) b) c) d) e) Enable the synchronous slave serial port by setting bits SYNC and SPEN and clearing bit CSRC. Clear bits CREN and SREN. If interrupts are desired, set enable bit TXxIE. If 9-bit transmission is desired, set bit TX9. Enable the transmission by setting enable bit TXEN. If 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D. Start transmission by loading data to the TXREGx register. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. The first word will immediately transfer to the TSRx register and transmit. The second word will remain in the TXREGx register. Flag bit, TXxIF, will not be set. When the first word has been shifted out of TSRx, the TXREGx register will transfer the second word to the TSRx and flag bit, TXxIF, will now be set. If enable bit TXxIE is set, the interrupt will wake the chip from Sleep. If the global interrupt is enabled, the program will branch to the interrupt vector. TABLE 20-9: Name REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION Bit 7 Bit 6 Bit 5 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page INT0IE RBIE TMR0IF INT0IF RBIF 57 PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 60 PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 60 IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 60 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 60 TRISG -- -- -- TRISG4 TRISG3 TRISG2 TRISG1 TRISG0 60 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 59 INTCON RCSTAx TXREGx TXSTAx GIE/GIEH PEIE/GIEL TMR0IE Bit 4 EUSARTx Transmit Register CSRC BAUDCONx ABDOVF 59 TX9 TXEN SYNC SENDB BRGH TRMT TX9D 59 RCIDL -- SCKP BRG16 -- WUE ABDEN 61 SPBRGHx EUSARTx Baud Rate Generator Register High Byte 61 SPBRGx EUSARTx Baud Rate Generator Register Low Byte 59 Legend: -- = unimplemented, read as `0'. Shaded cells are not used for synchronous slave transmission. DS39646B-page 268 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY 20.4.2 EUSART SYNCHRONOUS SLAVE RECEPTION To set up a Synchronous Slave Reception: 1. The operation of the Synchronous Master and Slave modes is identical, except in the case of Sleep, or any Idle mode and bit SREN, which is a "don't care" in Slave mode. If receive is enabled by setting the CREN bit prior to entering Sleep or any Idle mode, then a word may be received while in this low-power mode. Once the word is received, the RSRx register will transfer the data to the RCREGx register; if the RCxIE enable bit is set, the interrupt generated will wake the chip from the lowpower mode. If the global interrupt is enabled, the program will branch to the interrupt vector. 2. 3. 4. 5. 6. 7. 8. 9. Enable the synchronous master serial port by setting bits SYNC and SPEN and clearing bit CSRC. If interrupts are desired, set enable bit RCxIE. If 9-bit reception is desired, set bit RX9. To enable reception, set enable bit CREN. Flag bit, RCxIF, will be set when reception is complete. An interrupt will be generated if enable bit, RCxIE, was set. Read the RCSTAx register to get the 9th bit (if enabled) and determine if any error occurred during reception. Read the 8-bit received data by reading the RCREGx register. If any error occurred, clear the error by clearing bit CREN. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. TABLE 20-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION Name INTCON Bit 7 Bit 6 GIE/GIEH PEIE/GIEL Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 57 PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 60 PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 60 IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 60 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 60 TRISG -- -- -- TRISG4 TRISG3 TRISG2 TRISG1 TRISG0 60 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 59 RCSTAx RCREGx TXSTAx EUSARTx Receive Register CSRC BAUDCONx ABDOVF 59 TX9 TXEN SYNC SENDB BRGH TRMT TX9D 59 RCIDL -- SCKP BRG16 -- WUE ABDEN 61 SPBRGHx EUSARTx Baud Rate Generator Register High Byte 61 SPBRGx EUSARTx Baud Rate Generator Register Low Byte 59 Legend: -- = unimplemented, read as `0'. Shaded cells are not used for synchronous slave reception. 2004 Microchip Technology Inc. Preliminary DS39646B-page 269 PIC18F8722 FAMILY NOTES: DS39646B-page 270 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY 21.0 10-BIT ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE The ADCON0 register, shown in Register 21-1, controls the operation of the A/D module. The ADCON1 register, shown in Register 21-2, configures the functions of the port pins. The ADCON2 register, shown in Register 21-3, configures the A/D clock source, programmed acquisition time and justification. The Analog-to-Digital (A/D) converter module has 12 inputs for the 64-pin devices and 16 for the 80-pin devices. This module allows conversion of an analog input signal to a corresponding 10-bit digital number. The module has five registers: * * * * * A/D Result High Register (ADRESH) A/D Result Low Register (ADRESL) A/D Control Register 0 (ADCON0) A/D Control Register 1 (ADCON1) A/D Control Register 2 (ADCON2) REGISTER 21-1: ADCON0: A/D CONTROL REGISTER U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 -- -- CHS3 CHS2 CHS1 CHS0 GO/DONE ADON bit 7 bit 0 bit 7-6 Unimplemented: Read as `0' bit 5-2 CHS3:CHS0: Analog Channel Select bits 0000 = Channel 0 (AN0) 0001 = Channel 1 (AN1) 0010 = Channel 2 (AN2) 0011 = Channel 3 (AN3) 0100 = Channel 4 (AN4) 0101 = Channel 5 (AN5) 0110 = Channel 6 (AN6) 0111 = Channel 7 (AN7) 1000 = Channel 8 (AN8) 1001 = Channel 9 (AN9) 1010 = Channel 10 (AN10) 1011 = Channel 11 (AN11) 1100 = Channel 12 (AN12)(1) 1101 = Channel 13 (AN13)(1) 1110 = Channel 14 (AN14)(1) 1111 = Channel 15 (AN15)(1) Note 1: These channels are not implemented on 64-pin devices. bit 1 GO/DONE: A/D Conversion Status bit When ADON = 1: 1 = A/D conversion in progress 0 = A/D Idle bit 0 ADON: A/D On bit 1 = A/D converter module is enabled 0 = A/D converter module is disabled Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared 2004 Microchip Technology Inc. Preliminary x = Bit is unknown DS39646B-page 271 PIC18F8722 FAMILY REGISTER 21-2: ADCON1: A/D CONTROL REGISTER 1 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 -- -- VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 bit 7 bit 0 bit 7-6 Unimplemented: Read as `0' bit 5-4 VCFG1:VCFG0: Voltage Reference Configuration bits A/D VREF+ 00 AVDD AVSS 01 External VREF+ AVSS 10 AVDD External VREF- 11 External VREF+ External VREF- PCFG3: PCFG0 AN14(1) AN13(1) AN12(1) AN11 AN10 AN9 AN8 AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 PCFG3:PCFG0: A/D Port Configuration Control bits: AN15(1) bit 3-0 A/D VREF- 0000 0001 A A A A A A A A A A A A A A A A D D A A A A A A A A A A A A A A 0010 D D D A A A A A A A A A A A A A 0011 D D D D A A A A A A A A A A A A 0100 D D D D D A A A A A A A A A A A 0101 D D D D D D A A A A A A A A A A 0110 D D D D D D D A A A A A A A A A 0111 1000 D D D D D D D D A A A A A A A A D D D D D D D D D A A A A A A A 1001 D D D D D D D D D D A A A A A A 1010 D D D D D D D D D D D A A A A A 1011 D D D D D D D D D D D D A A A A 1100 D D D D D D D D D D D D D A A A 1101 D D D D D D D D D D D D D D A A 1110 D D D D D D D D D D D D D D D A 1111 D D D D D D D D D D D D D D D D A = Analog input D = Digital I/O Note 1: AN15 through AN12 are available only on 80-pin devices. Legend: DS39646B-page 272 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared Preliminary x = Bit is unknown 2004 Microchip Technology Inc. PIC18F8722 FAMILY REGISTER 21-3: ADCON2: A/D CONTROL REGISTER 2 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADFM -- ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 bit 7 bit 0 bit 7 ADFM: A/D Result Format Select bit 1 = Right justified 0 = Left justified bit 6 Unimplemented: Read as `0' bit 5-3 ACQT2:ACQT0: A/D Acquisition Time Select bits 111 = 20 TAD 110 = 16 TAD 101 = 12 TAD 100 = 8 TAD 011 = 6 TAD 010 = 4 TAD 001 = 2 TAD 000 = 0 TAD(1) bit 2-0 ADCS2:ADCS0: A/D Conversion Clock Select bits 111 = FRC (clock derived from A/D RC oscillator)(1) 110 = FOSC/64 101 = FOSC/16 100 = FOSC/4 011 = FRC (clock derived from A/D RC oscillator)(1) 010 = FOSC/32 001 = FOSC/8 000 = FOSC/2 Note 1: If the A/D FRC clock source is selected, a delay of one TCY (instruction cycle) is added before the A/D clock starts. This allows the SLEEP instruction to be executed before starting a conversion. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared 2004 Microchip Technology Inc. Preliminary x = Bit is unknown DS39646B-page 273 PIC18F8722 FAMILY The analog reference voltage is software selectable to either the device's positive and negative supply voltage (VDD and VSS), or the voltage level on the RA3/AN3/ VREF+ and RA2/AN2/VREF- pins. A device Reset forces all registers to their Reset state. This forces the A/D module to be turned off and any conversion in progress is aborted. Each port pin associated with the A/D converter can be configured as an analog input, or as a digital I/O. The ADRESH and ADRESL registers contain the result of the A/D conversion. When the A/D conversion is complete, the result is loaded into the ADRESH:ADRESL register pair, the GO/DONE bit (ADCON0 register) is cleared and A/D Interrupt Flag bit, ADIF (PIR1<6>), is set. The block diagram of the A/D module is shown in Figure 21-1. The A/D converter has a unique feature of being able to operate while the device is in Sleep mode. To operate in Sleep, the A/D conversion clock must be derived from the A/D's internal RC oscillator. The output of the sample and hold is the input into the converter, which generates the result via successive approximation. FIGURE 21-1: A/D BLOCK DIAGRAM CHS3:CHS0 1111 AN15(1) 1110 AN14(1) 1101 AN13(1) 1100 AN12(1) 1011 1010 1001 1000 0111 0110 0101 0100 VAIN 0011 (Input Voltage) 10-Bit Converter A/D 0010 0001 VCFG1:VCFG0 0000 AVDD Reference Voltage VREF+ X0 X1 1X VREF- 0X AN11 AN10 AN9 AN8 AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 AVSS Note 1: 2: Channels AN12 through AN15 are not available on 64-pin devices. I/O pins have diode protection to VDD and VSS. DS39646B-page 274 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY Wait for A/D conversion to complete, by either: * Polling for the GO/DONE bit to be cleared OR * Waiting for the A/D interrupt Read A/D Result registers (ADRESH:ADRESL); clear bit ADIF, if required. For next conversion, go to step 1 or step 2, as required. The A/D conversion time per bit is defined as TAD. A minimum wait of 2 TAD is required before the next acquisition starts. 6. 7. FIGURE 21-2: The following steps should be followed to perform an A/D conversion: 3FFh 1. 3FEh FIGURE 21-3: Digital Code Output 002h 001h 1023 LSB 1023.5 LSB 1022 LSB 1022.5 LSB 3 LSB Analog Input Voltage ANALOG INPUT MODEL VDD Sampling Switch VT = 0.6V Rs VAIN 2 LSB 000h 2.5 LSB 3. 4. A/D TRANSFER FUNCTION 003h 0.5 LSB 2. Configure the A/D module: * Configure analog pins, voltage reference and digital I/O (ADCON1) * Select A/D input channel (ADCON0) * Select A/D acquisition time (ADCON2) * Select A/D conversion clock (ADCON2) * Turn on A/D module (ADCON0) Configure A/D interrupt (if desired): * Clear ADIF bit * Set ADIE bit * Set GIE bit Wait the required acquisition time (if required). Start conversion: * Set GO/DONE bit (ADCON0 register) 1 LSB After the A/D module has been configured as desired, the selected channel must be acquired before the conversion is started. The analog input channels must have their corresponding TRIS bits selected as an input. To determine acquisition time, see Section 21.1 "A/D Acquisition Requirements". After this acquisition time has elapsed, the A/D conversion can be started. An acquisition time can be programmed to occur between setting the GO/DONE bit and the actual start of the conversion. 5. 1.5 LSB The value in the ADRESH:ADRESL registers is not modified for a Power-on Reset. The ADRESH:ADRESL registers will contain unknown data after a Power-on Reset. ANx RIC 1k CPIN 5 pF VT = 0.6V SS RSS ILEAKAGE 100 nA CHOLD = 25 pF VSS Legend: CPIN = input capacitance VT = threshold voltage ILEAKAGE = leakage current at the pin due to various junctions = interconnect resistance RIC = sampling switch SS = sample/hold capacitance (from DAC) CHOLD RSS = sampling switch resistance 2004 Microchip Technology Inc. Preliminary VDD 6V 5V 4V 3V 2V 1 2 3 4 Sampling Switch (k) DS39646B-page 275 PIC18F8722 FAMILY 21.1 A/D Acquisition Requirements For the A/D converter to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The analog input model is shown in Figure 21-3. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD). The source impedance affects the offset voltage at the analog input (due to pin leakage current). The maximum recommended impedance for analog sources is 2.5 k. After the analog input channel is selected (changed), the channel must be sampled for at least the minimum acquisition time before starting a conversion. Note: CHOLD Rs Conversion Error VDD Temperature = = = = 25 pF 2.5 k 1/2 LSb 5V Rss = 2 k 85C (system max.) ACQUISITION TIME = Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient = TAMP + TC + TCOFF EQUATION 21-2: VHOLD or TC Example 21-3 shows the calculation of the minimum required acquisition time TACQ. This calculation is based on the following application system assumptions: When the conversion is started, the holding capacitor is disconnected from the input pin. EQUATION 21-1: TACQ To calculate the minimum acquisition time, Equation 21-1 may be used. This equation assumes that 1/2 LSb error is used (1024 steps for the A/D). The 1/2 LSb error is the maximum error allowed for the A/D to meet its specified resolution. A/D MINIMUM CHARGING TIME = (VREF - (VREF/2048)) * (1 - e(-TC/CHOLD(RIC + RSS + RS))) = -(CHOLD)(RIC + RSS + RS) ln(1/2048) EQUATION 21-3: CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME TACQ = TAMP + TC + TCOFF TAMP = 0.2 s TCOFF = (Temp - 25C)(0.02 s/C) (85C - 25C)(0.02 s/C) 1.2 s Temperature coefficient is only required for temperatures > 25C. Below 25C, TCOFF = 0 ms. TC = -(CHOLD)(RIC + RSS + RS) ln(1/2047) s -(25 pF) (1 k + 2 k + 2.5 k) ln(0.0004883) s 1.05 s TACQ = 0.2 s + 1 s + 1.2 s 2.4 s DS39646B-page 276 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY 21.2 Selecting and Configuring Acquisition Time 21.3 Selecting the A/D Conversion Clock The ADCON2 register allows the user to select an acquisition time that occurs each time the GO/DONE bit is set. It also gives users the option to use an automatically determined acquisition time. The A/D conversion time per bit is defined as TAD. The A/D conversion requires 11 TAD per 10-bit conversion. The source of the A/D conversion clock is software selectable. There are seven possible options for TAD: Acquisition time may be set with the ACQT2:ACQT0 bits (ADCON2<5:3>) which provides a range of 2 to 20 TAD. When the GO/DONE bit is set, the A/D module continues to sample the input for the selected acquisition time, then automatically begins a conversion. Since the acquisition time is programmed, there may be no need to wait for an acquisition time between selecting a channel and setting the GO/DONE bit. * * * * * * * Manual acquisition is selected when ACQT2:ACQT0 = 000. When the GO/DONE bit is set, sampling is stopped and a conversion begins. The user is responsible for ensuring the required acquisition time has passed between selecting the desired input channel and setting the GO/DONE bit. This option is also the default Reset state of the ACQT2:ACQT0 bits and is compatible with devices that do not offer programmable acquisition times. For correct A/D conversions, the A/D conversion clock (TAD) must be as short as possible, but greater than the minimum TAD (see parameter 130, Table 28-27 for more information). 2 TOSC 4 TOSC 8 TOSC 16 TOSC 32 TOSC 64 TOSC Internal RC Oscillator Table 21-1 shows the resultant TAD times derived from the device operating frequencies and the A/D clock source selected. In either case, when the conversion is completed, the GO/DONE bit is cleared, the ADIF flag is set and the A/D begins sampling the currently selected channel again. If an acquisition time is programmed, there is nothing to indicate if the acquisition time has ended or if the conversion has begun. TABLE 21-1: TAD vs. DEVICE OPERATING FREQUENCIES AD Clock Source (TAD) Maximum Device Frequency Operation ADCS2:ADCS0 PIC18FXXXX PIC18LFXXXX(4) 2 TOSC 000 2.86 MHz 1.43 kHz 4 TOSC 100 5.71 MHz 2.86 MHz 8 TOSC 001 11.43 MHz 5.72 MHz 16 TOSC 101 22.86 MHz 11.43 MHz 32 TOSC 010 40.0 MHz 22.86 MHz 64 TOSC 110 40.0 MHz 22.86 MHz RC(3) Note 1: 2: 3: 4: x11 1.00 MHz(1) 1.00 MHz(2) The RC source has a typical TAD time of 1.2 s. The RC source has a typical TAD time of 2.5 s. For device frequencies above 1 MHz, the device must be in Sleep for the entire conversion or the A/D accuracy may be out of specification. Low-power (PIC18LFXXXX) devices only. 2004 Microchip Technology Inc. Preliminary DS39646B-page 277 PIC18F8722 FAMILY 21.4 Operation in Power-Managed Modes 21.5 The selection of the automatic acquisition time and A/D conversion clock is determined in part by the clock source and frequency while in a power-managed mode. If the A/D is expected to operate while the device is in a power-managed mode, the ACQT2:ACQT0 and ADCS2:ADCS0 bits in ADCON2 should be updated in accordance with the clock source to be used in that mode. After entering the mode, an A/D acquisition or conversion may be started. Once started, the device should continue to be clocked by the same clock source until the conversion has been completed. If desired, the device may be placed into the corresponding Idle mode during the conversion. If the device clock frequency is less than 1 MHz, the A/D RC clock source should be selected. The ADCON1, TRISA, TRISF and TRISH registers all configure the A/D port pins. The port pins needed as analog inputs must have their corresponding TRIS bits set (input). If the TRIS bit is cleared (output), the digital output level (VOH or VOL) will be converted. The A/D operation is independent of the state of the CHS3:CHS0 bits and the TRIS bits. Note 1: When reading the Port register, all pins configured as analog input channels will read as cleared (a low level). Pins configured as digital inputs will convert as analog inputs. Analog levels on a digitally configured input will be accurately converted. Operation in the Sleep mode requires the A/D FRC clock to be selected. If bits ACQT2:ACQT0 are set to `000' and a conversion is started, the conversion will be delayed one instruction cycle to allow execution of the SLEEP instruction and entry to Sleep mode. The IDLEN bit (OSCCON<7>) must have already been cleared prior to starting the conversion. DS39646B-page 278 Configuring Analog Port Pins Preliminary 2: Analog levels on any pin defined as a digital input may cause the digital input buffer to consume current out of the device's specification limits. 2004 Microchip Technology Inc. PIC18F8722 FAMILY 21.6 A/D Conversions After the A/D conversion is completed or aborted, a 2 TAD wait is required before the next acquisition can be started. After this wait, acquisition on the selected channel is automatically started. Figure 21-4 shows the operation of the A/D converter after the GO/DONE bit has been set and the ACQT2:ACQT0 bits are cleared. A conversion is started after the following instruction to allow entry into Sleep mode before the conversion begins. Note: Figure 21-5 shows the operation of the A/D converter after the GO/DONE bit has been set, the ACQT2:ACQT0 bits are set to `010' and a 4 TAD acquisition time is selected before the conversion starts. 21.7 Discharge The discharge phase is used to initialize the value of the capacitor array. The array is discharged before every sample. This feature helps to optimize the unitygain amplifier, as the circuit always needs to charge the capacitor array, rather than charge/discharge based on previous measure values. Clearing the GO/DONE bit during a conversion will abort the current conversion. The A/D Result register pair will NOT be updated with the partially completed A/D conversion sample. This means the ADRESH:ADRESL registers will continue to contain the value of the last completed conversion (or the last value written to the ADRESH:ADRESL registers). FIGURE 21-4: The GO/DONE bit should NOT be set in the same instruction that turns on the A/D. A/D CONVERSION TAD CYCLES (ACQT<2:0> = 000, TACQ = 0) TCY - TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11 TAD1 b4 b1 b0 b6 b7 b2 b9 b8 b3 b5 Conversion starts Discharge Holding capacitor is disconnected from analog input (typically 100 ns) Set GO/DONE bit On the following cycle: ADRESH:ADRESL are loaded, GO/DONE bit is cleared, ADIF bit is set, holding capacitor is connected to analog input. A/D CONVERSION TAD CYCLES (ACQT<2:0> = 010, TACQ = 4 TAD) FIGURE 21-5: TAD Cycles TACQT Cycles 1 2 3 Automatic Acquisition Time 4 1 2 3 4 5 6 7 8 9 10 11 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Conversion starts (Holding capacitor is disconnected) Set GO/DONE bit (Holding capacitor continues acquiring input) 2004 Microchip Technology Inc. TAD1 Discharge On the following cycle: ADRESH:ADRESL are loaded, GO/DONE bit is cleared, ADIF bit is set, holding capacitor is connected to analog input. Preliminary DS39646B-page 279 PIC18F8722 FAMILY 21.8 Use of the ECCP2 Trigger An A/D conversion can be started by the special event trigger of the ECCP2 module. This requires that the CCP2M3:CCP2M0 bits (CCP2CON<3:0>) be programmed as `1011' and that the A/D module is enabled (ADON bit is set). When the trigger occurs, the GO/DONE bit will be set, starting the A/D acquisition and conversion and the Timer1 (or Timer3) counter will be reset to zero. Timer1 (or Timer3) is reset to automatically repeat the A/D acquisition period with minimal TABLE 21-2: Name INTCON software overhead (moving ADRESH:ADRESL to the desired location). The appropriate analog input channel must be selected and the minimum acquisition period is either timed by the user, or an appropriate TACQ time selected before the special event trigger sets the GO/DONE bit (starts a conversion). If the A/D module is not enabled (ADON is cleared), the special event trigger will be ignored by the A/D module but will still reset the Timer1 (or Timer3) counter. REGISTERS ASSOCIATED WITH A/D OPERATION Bit 7 Bit 6 GIE/GIEH PEIE/GIEL Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 57 PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 60 PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 60 IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 60 PIR2 OSCFIF CMIF -- EEIF BCL1IF HLVDIF TMR3IF CCP2IF 60 PIE2 OSCFIE CMIE -- EEIE BCL1IE HLVDIE TMR3IE CCP2IE 60 IPR2 OSCFIP CMIP -- EEIP BCL1IP HLVDIP TMR3IP CCP2IP 60 ADRESH A/D Result Register High Byte 59 ADRESL A/D Result Register Low Byte 59 ADCON0 -- -- CHS3 CHS2 CHS1 CHS0 GO/DONE ADON 59 ADCON1 -- -- VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 59 ADFM -- ADCON2 TRISA TRISA7(1) TRISA6(1) ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 59 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 60 TRISF TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0 60 TRISH(2) TRISH7 TRISH6 TRISH5 TRISH4 TRISH3 TRISH2 TRISH1 TRISH0 60 Legend: -- = unimplemented, read as `0'. Shaded cells are not used for A/D conversion. Note 1: PORTA<7:6> and their direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as `0'. 2: These registers are not implemented on 64-pin devices. DS39646B-page 280 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY 22.0 COMPARATOR MODULE The analog comparator module contains two comparators that can be configured in a variety of ways. The inputs can be selected from the analog inputs multiplexed with pins RF3 through RF6, as well as the on-chip voltage reference (see Section 23.0 "Comparator Voltage Reference Module"). The digital outputs (normal or inverted) are available on RF1 and RF2 and can also be read through the control register. REGISTER 22-1: The CMCON register (Register 22-1) selects the comparator input and output configuration. Block diagrams of the various comparator configurations are shown in Figure 22-1. CMCON: COMPARATOR MODULE CONTROL REGISTER R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 bit 7 bit 0 bit 7 C2OUT: Comparator 2 Output bit When C2INV = 0: 1 = C2 VIN+ > C2 VIN0 = C2 VIN+ < C2 VINWhen C2INV = 1: 1 = C2 VIN+ < C2 VIN0 = C2 VIN+ > C2 VIN- bit 6 C1OUT: Comparator 1 Output bit When C1INV = 0: 1 = C1 VIN+ > C1 VIN0 = C1 VIN+ < C1 VINWhen C1INV = 1: 1 = C1 VIN+ < C1 VIN0 = C1 VIN+ > C1 VIN- bit 5 C2INV: Comparator 2 Output Inversion bit 1 = C2 output inverted 0 = C2 output not inverted bit 4 C1INV: Comparator 1 Output Inversion bit 1 = C1 output inverted 0 = C1 output not inverted bit 3 CIS: Comparator Input Switch bit When CM2:CM0 = 110: 1 = C1 VIN- connects to RF5/AN10/CVREF C2 VIN- connects to RF3/AN8 0 = C1 VIN- connects to RF6/AN11 C2 VIN- connects to RF4/AN9 bit 2-0 CM2:CM0: Comparator mode bits Figure 22-1 shows the Comparator modes and the CM2:CM0 bit settings. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared 2004 Microchip Technology Inc. Preliminary x = Bit is unknown DS39646B-page 281 PIC18F8722 FAMILY 22.1 Comparator Configuration There are eight modes of operation for the comparators, shown in Figure 22-1. Bits CM2:CM0 of the CMCON register are used to select these modes. The TRISF register controls the data direction of the comparator pins for each mode. If the Comparator FIGURE 22-1: RF5/AN10/ CVREF RF4/AN9 RF3/AN8 A VIN- A VIN+ A VIN- A VIN+ A VIN- A VIN+ RF4/AN9 A VIN- RF3/AN8 A VIN+ RF5/AN10/ CVREF Comparator interrupts should be disabled during a Comparator mode change; otherwise, a false interrupt may occur. Comparators Off (POR Default Value) CM2:CM0 = 111 RF6/AN11 D VINC1 Off (Read as `0') C2 Off (Read as `0') Two Independent Comparators CM2:CM0 = 010 RF6/AN11 Note: COMPARATOR I/O OPERATING MODES Comparators Reset CM2:CM0 = 000 RF6/AN11 mode is changed, the comparator output level may not be valid for the specified mode change delay shown in Section 28.0 "Electrical Characteristics". RF5/AN10/ CVREF D VIN+ RF4/AN9 D VIN- RF3/AN8 D VIN+ Off (Read as `0') C2 Off (Read as `0') Two Independent Comparators with Outputs CM2:CM0 = 011 RF6/AN11 C1 C1 C1OUT RF5/AN10 A VIN- A VIN+ C1 C1OUT C2 C2OUT RF2/AN7/C1OUT* C2 C2OUT RF4/AN9 A VIN- RF3/AN8 A VIN+ RF1/AN6/C2OUT* Two Common Reference Comparators CM2:CM0 = 100 RF6/AN11 A VIN- RF5/AN10/ A CVREF VIN+ RF4/AN9 A VIN- RF3/AN8 D VIN+ C1 Two Common Reference Comparators with Outputs CM2:CM0 = 101 RF6/AN11 A VINC1OUT A VIN+ RF4/AN9 A VIN- RF3/AN8 D VIN+ RF5/AN10/ CVREF C1 C1OUT C2 C2OUT RF2/AN7/ C1OUT* C2 C2OUT RF1/AN6/C2OUT* Four Inputs Multiplexed to Two Comparators CM2:CM0 = 110 One Independent Comparator with Output CM2:CM0 = 001 RF6/AN11 A VIN- RF5/AN10/ A CVREF VIN+ RF6/AN11 C1 C1OUT RF5/AN10/ A CVREF RF2/AN7/ C1OUT* RF4/AN9 D VIN- RF3/AN8 D VIN+ C2 A RF4/AN9 A RF3/AN8 A CIS = 0 CIS = 1 VINVIN+ CIS = 0 CIS = 1 C1 C1OUT C2 C2OUT VINVIN+ Off (Read as `0') CVREF From VREF Module A = Analog Input, port reads zeros always D = Digital Input CIS (CMCON<3>) is the Comparator Input Switch * Setting the TRISF<2:1> bits will disable the comparator outputs by configuring the pins as inputs. DS39646B-page 282 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY 22.2 22.3.2 Comparator Operation A single comparator is shown in Figure 22-2, along with the relationship between the analog input levels and the digital output. When the analog input at VIN+ is less than the analog input VIN-, the output of the comparator is a digital low level. When the analog input at VIN+ is greater than the analog input VIN-, the output of the comparator is a digital high level. The shaded areas of the output of the comparator in Figure 22-2 represent the uncertainty, due to input offsets and response time. 22.3 Comparator Reference Depending on the comparator operating mode, either an external or internal voltage reference may be used. The analog signal present at VIN- is compared to the signal at VIN+ and the digital output of the comparator is adjusted accordingly (Figure 22-2). FIGURE 22-2: SINGLE COMPARATOR VIN+ + VIN- - The internal reference is only available in the mode where four inputs are multiplexed to two comparators (CM2:CM0 = 110). In this mode, the internal voltage reference is applied to the VIN+ pin of both comparators. 22.4 Comparator Response Time Response time is the minimum time, after selecting a new reference voltage or input source, before the comparator output has a valid level. If the internal reference is changed, the maximum delay of the internal voltage reference must be considered when using the comparator outputs. Otherwise, the maximum delay of the comparators should be used (see Section 28.0 "Electrical Characteristics"). Comparator Outputs The comparator outputs are read through the CMCON register. These bits are read-only. The comparator outputs may also be directly output to the RF1 and RF2 I/O pins. When enabled, multiplexors in the output path of the RF1 and RF2 pins will switch and the output of each pin will be the unsynchronized output of the comparator. The uncertainty of each of the comparators is related to the input offset voltage and the response time given in the specifications. Figure 22-3 shows the comparator output block diagram. VINVIN+ Output 22.3.1 The comparator module also allows the selection of an internally generated voltage reference from the comparator voltage reference module. This module is described in more detail in Section 23.0 "Comparator Voltage Reference Module". 22.5 Output INTERNAL REFERENCE SIGNAL The TRISF bits will still function as an output enable/ disable for the RF1 and RF2 pins while in this mode. EXTERNAL REFERENCE SIGNAL When external voltage references are used, the comparator module can be configured to have the comparators operate from the same or different reference sources. However, threshold detector applications may require the same reference. The reference signal must be between VSS and VDD and can be applied to either pin of the comparator(s). 2004 Microchip Technology Inc. The polarity of the comparator outputs can be changed using the C2INV and C1INV bits (CMCON<5:4>). Note 1: When reading the Port register, all pins configured as analog inputs will read as a `0'. Pins configured as digital inputs will convert an analog input according to the Schmitt Trigger input specification. Preliminary 2: Analog levels on any pin defined as a digital input may cause the input buffer to consume more current than is specified. DS39646B-page 283 PIC18F8722 FAMILY + CxOUT - Port pins COMPARATOR OUTPUT BLOCK DIAGRAM MULTIPLEX FIGURE 22-3: D Q Bus Data CxINV EN Read CMCON D Q EN CL From other Comparator Reset 22.6 Comparator Interrupts 22.7 The comparator interrupt flag is set whenever there is a change in the output value of either comparator. Software will need to maintain information about the status of the output bits, as read from CMCON<7:6>, to determine the actual change that occurred. The CMIF bit (PIR2<6>) is the Comparator Interrupt Flag. The CMIF bit must be reset by clearing it. Since it is also possible to write a `1' to this register, a simulated interrupt may be initiated. Both the CMIE bit (PIE2<6>) and the PEIE bit (INTCON<6>) must be set to enable the interrupt. In addition, the GIE bit (INTCON<7>) must also be set. If any of these bits are clear, the interrupt is not enabled, though the CMIF bit will still be set if an interrupt condition occurs. Note: If a change in the CMCON register (C1OUT or C2OUT) should occur when a read operation is being executed (start of the Q2 cycle), then the CMIF (PIR2 register) interrupt flag may not get set. The user, in the Interrupt Service Routine, can clear the interrupt in the following manner: a) b) Set CMIF bit Comparator Operation During Sleep When a comparator is active and the device is placed in Sleep mode, the comparator remains active and the interrupt is functional if enabled. This interrupt will wake-up the device from Sleep mode, when enabled. Each operational comparator will consume additional current, as shown in the comparator specifications. To minimize power consumption while in Sleep mode, turn off the comparators (CM2:CM0 = 111) before entering Sleep. If the device wakes up from Sleep, the contents of the CMCON register are not affected. 22.8 Effects of a Reset A device Reset forces the CMCON register to its Reset state, causing the comparator modules to be turned off (CM2:CM0 = 111). However, the input pins (RF3 through RF6) are configured as analog inputs by default on device Reset. The I/O configuration for these pins is also determined by the setting of the PCFG3:PCFG0 bits (ADCON1<3:0>). Therefore, device current is minimized when analog inputs are present at Reset time. Any read or write of CMCON will end the mismatch condition. Clear flag bit CMIF. A mismatch condition will continue to set flag bit CMIF. Reading CMCON will end the mismatch condition and allow flag bit CMIF to be cleared. DS39646B-page 284 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY 22.9 Analog Input Connection Considerations range by more than 0.6V in either direction, one of the diodes is forward biased and a latch-up condition may occur. A maximum source impedance of 10 k is recommended for the analog sources. Any external component connected to an analog input pin, such as a capacitor or a Zener diode, should have very little leakage current. A simplified circuit for an analog input is shown in Figure 22-4. Since the analog pins are connected to a digital output, they have reverse biased diodes to VDD and VSS. The analog input, therefore, must be between VSS and VDD. If the input voltage deviates from this FIGURE 22-4: COMPARATOR ANALOG INPUT MODEL VDD VT = 0.6V RS < 10k RIC Comparator Input AIN CPIN 5 pF VA VT = 0.6V ILEAKAGE 500 nA VSS Legend: TABLE 22-1: Name CMCON CVRCON INTCON CPIN VT ILEAKAGE RIC RS VA = = = = = = Input Capacitance Threshold Voltage Leakage Current at the pin due to various junctions Interconnect Resistance Source Impedance Analog Voltage REGISTERS ASSOCIATED WITH COMPARATOR MODULE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 59 CVREN CVROE GIE/GIEH PEIE/GIEL CVRR CVRSS CVR3 CVR2 CVR1 CVR0 59 TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 60 PIR2 OSCFIF CMIF -- EEIF BCL1IF HLVDIF TMR3IF CCP2IF 60 PIE2 OSCFIE CMIE -- EEIE BCL1IE HLVDIE TMR3IE CCP2IE 60 IPR2 OSCFIP CMIP -- EEIP BCL1IP HLVDIP TMR3IP CCP2IP 60 TRISF TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0 60 Legend: -- = unimplemented, read as `0'. Shaded cells are unused by the comparator module. 2004 Microchip Technology Inc. Preliminary DS39646B-page 285 PIC18F8722 FAMILY NOTES: DS39646B-page 286 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY 23.0 COMPARATOR VOLTAGE REFERENCE MODULE The comparator voltage reference is a 16-tap resistor ladder network that provides a selectable reference voltage. Although its primary purpose is to provide a reference for the analog comparators, it may also be used independently of them. A block diagram of the module is shown in Figure 23-1. The resistor ladder is segmented to provide two ranges of CVREF values and has a power-down function to conserve power when the reference is not being used. The module's supply reference can be provided from either device VDD/VSS or an external voltage reference. 23.1 Configuring the Comparator Voltage Reference The voltage reference module is controlled through the CVRCON register (Register 23-1). The comparator voltage reference provides two ranges of output voltage, each with 16 distinct levels. The range to be REGISTER 23-1: used is selected by the CVRR bit (CVRCON<5>). The primary difference between the ranges is the size of the steps selected by the CVREF Selection bits (CVR3:CVR0), with one range offering finer resolution. The equations used to calculate the output of the comparator voltage reference are as follows: If CVRR = 1: CVREF = ((CVR3:CVR0)/24) x (CVRSRC) If CVRR = 0: CVREF = (CVRSRC/4) + ((CVR3:CVR0)/32) x (CVRSRC) The comparator reference supply voltage can come from either VDD and VSS, or the external VREF+ and VREF- that are multiplexed with RA2 and RA3. The voltage source is selected by the CVRSS bit (CVRCON<4>). The settling time of the comparator voltage reference must be considered when changing the CVREF output (see Table 28-3 in Section 28.0 "Electrical Characteristics"). CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CVREN CVROE(1) CVRR CVRSS CVR3 CVR2 CVR1 CVR0 bit 7 bit 0 bit 7 CVREN: Comparator Voltage Reference Enable bit 1 = CVREF circuit powered on 0 = CVREF circuit powered down bit 6 CVROE: Comparator VREF Output Enable bit(1) 1 = CVREF voltage level is also output on the RF5/AN10/CVREF pin 0 = CVREF voltage is disconnected from the RF5/AN10/CVREF pin Note 1: CVROE overrides the TRISF<5> bit setting. bit 5 CVRR: Comparator VREF Range Selection bit 1 = 0 to 0.667 CVRSRC, with CVRSRC/24 step size (low range) 0 = 0.25 CVRSRC to 0.75 CVRSRC, with CVRSRC/32 step size (high range) bit 4 CVRSS: Comparator VREF Source Selection bit 1 = Comparator reference source, CVRSRC = (VREF+) - (VREF-) 0 = Comparator reference source, CVRSRC = AVDD - AVSS bit 3-0 CVR3:CVR0: Comparator VREF Value Selection bits (0 (CVR3:CVR0) 15) When CVRR = 1: CVREF = ((CVR3:CVR0)/24) x (CVRSRC) When CVRR = 0: CVREF = (CVRSRC/4) + ((CVR3:CVR0)/32) x (CVRSRC) Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared 2004 Microchip Technology Inc. Preliminary x = Bit is unknown DS39646B-page 287 PIC18F8722 FAMILY FIGURE 23-1: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM VREF+ AVDD CVRSS = 1 8R CVRSS = 0 CVR3:CVR0 R CVREN R 16-to-1 MUX R R 16 Steps CVREF R R R CVRR VREF- 8R CVRSS = 1 CVRSS = 0 AVSS 23.2 Voltage Reference Accuracy/Error The full range of voltage reference cannot be realized due to the construction of the module. The transistors on the top and bottom of the resistor ladder network (Figure 23-1) keep CVREF from approaching the reference source rails. The voltage reference is derived from the reference source; therefore, the CVREF output changes with fluctuations in that source. The tested absolute accuracy of the voltage reference can be found in Section 28.0 "Electrical Characteristics". 23.3 Operation During Sleep When the device wakes up from Sleep through an interrupt or a Watchdog Timer time-out, the contents of the CVRCON register are not affected. To minimize current consumption in Sleep mode, the voltage reference should be disabled. 23.4 Effects of a Reset A device Reset disables the voltage reference by clearing bit, CVREN (CVRCON<7>). This Reset also disconnects the reference from the RF5 pin by clearing bit, CVROE (CVRCON<6>) and selects the high-voltage range by clearing bit, CVRR (CVRCON<5>). The CVR value select bits are also cleared. 23.5 Connection Considerations The voltage reference module operates independently of the comparator module. The output of the reference generator may be connected to the RF5 pin if the CVROE bit is set. Enabling the voltage reference output onto RF5 when it is configured as a digital input will increase current consumption. Connecting RF5 as a digital output with CVRSS enabled will also increase current consumption. The RF5 pin can be used as a simple D/A output with limited drive capability. Due to the limited current drive capability, a buffer must be used on the voltage reference output for external connections to VREF. Figure 23-2 shows an example buffering technique. DS39646B-page 288 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY FIGURE 23-2: COMPARATOR VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE PIC18FXXXX CVREF Module R(1) Voltage Reference Output Impedance Note 1: TABLE 23-1: Name + - RF5 CVREF Output R is dependent upon the voltage reference configuration bits, CVRCON<3:0> and CVRCON<5>. REGISTERS ASSOCIATED WITH COMPARATOR VOLTAGE REFERENCE Bit 7 Bit 6 CVRCON CVREN CMCON C2OUT TRISF TRISF7 Reset Values on page Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 59 C1OUT C2INV C1INV CIS CM2 CM1 CM0 59 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0 60 Legend: Shaded cells are not used with the comparator voltage reference. 2004 Microchip Technology Inc. Preliminary DS39646B-page 289 PIC18F8722 FAMILY NOTES: DS39646B-page 290 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY 24.0 HIGH/LOW-VOLTAGE DETECT (HLVD) The PIC18F8722 family of devices have a High/Low-Voltage Detect module (HLVD). This is a programmable circuit that allows the user to specify both a device voltage trip point and the direction of change from that point. If the device experiences an excursion past the trip point in that direction, an interrupt flag is set. If the interrupt is enabled, the program execution will branch to the interrupt vector address and the software can then respond to the interrupt. REGISTER 24-1: The High/Low-Voltage Detect Control register (Register 24-1) completely controls the operation of the HLVD module. This allows the circuitry to be "turned off" by the user under software control, which minimizes the current consumption for the device. The block diagram for the HLVD module is shown in Figure 24-1. HLVDCON: HIGH/LOW-VOLTAGE DETECT CONTROL REGISTER R/W-0 VDIRMAG U-0 -- R-0 IRVST R/W-0 R/W-0 R/W-1 R/W-0 R/W-1 HLVDEN HLVDL3(1) HLVDL2(1) HLVDL1(1) HLVDL0(1) bit 7 bit 0 bit 7 VDIRMAG: Voltage Direction Magnitude Select bit 1 = Event occurs when voltage equals or exceeds trip point (HLVDL3:HLDVL0) 0 = Event occurs when voltage equals or falls below trip point (HLVDL3:HLVDL0) bit 6 Unimplemented: Read as `0' bit 5 IRVST: Internal Reference Voltage Stable Flag bit 1 = Indicates that the voltage detect logic will generate the interrupt flag at the specified voltage range 0 = Indicates that the voltage detect logic will not generate the interrupt flag at the specified voltage range and the HLVD interrupt should not be enabled bit 4 HLVDEN: High/Low-Voltage Detect Power Enable bit 1 = HLVD enabled 0 = HLVD disabled bit 3-0 HLVDL3:HLVDL0: Voltage Detection Limit bits(1) 1111 = External analog input is used (input comes from the HLVDIN pin) 1110 = Maximum setting . . . 0000 = Minimum setting Note 1: See Table 28-4 for specifications. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared 2004 Microchip Technology Inc. Preliminary x = Bit is unknown DS39646B-page 291 PIC18F8722 FAMILY The module is enabled by setting the HLVDEN bit. Each time that the HLVD module is enabled, the circuitry requires some time to stabilize. The IRVST bit is a read-only bit and is used to indicate when the circuit is stable. The module can only generate an interrupt after the circuit is stable and IRVST is set. event, depending on the configuration of the module. When the supply voltage is equal to the trip point, the voltage tapped off of the resistor array is equal to the internal reference voltage generated by the voltage reference module. The comparator then generates an interrupt signal by setting the HLVDIF bit. The VDIRMAG bit determines the overall operation of the module. When VDIRMAG is cleared, the module monitors for drops in VDD below a predetermined set point. When the bit is set, the module monitors for rises in VDD above the set point. The trip point voltage is software programmable to any one of 16 values. The trip point is selected by programming the HLVDL3:HLVDL0 bits (HLVDCON<3:0>). 24.1 The HLVD module has an additional feature that allows the user to supply the trip voltage to the module from an external source. This mode is enabled when bits HLVDL3:HLVDL0 are set to `1111'. In this state, the comparator input is multiplexed from the external input pin, HLVDIN. This gives users flexibility because it allows them to configure the High/Low-Voltage Detect interrupt to occur at any voltage in the valid operating range. Operation When the HLVD module is enabled, a comparator uses an internally generated reference voltage as the set point. The set point is compared with the trip point, where each node in the resistor divider represents a trip point voltage. The "trip point" voltage is the voltage level at which the device detects a high or low-voltage FIGURE 24-1: HLVD MODULE BLOCK DIAGRAM (WITH EXTERNAL INPUT) Externally Generated Trip Point VDD VDD HLVDL3:HLVDL0 HLVDCON Register HLVDEN 16-to-1 MUX HLVDIN VDIRMAG Set HLVDIF HLVDEN BOREN DS39646B-page 292 Internal Voltage Reference 1.2V Typical Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY 24.2 HLVD Setup The following steps are needed to set up the HLVD module: 1. 2. 3. 4. 5. Write the value to the HLVDL3:HLVDL0 bits that selects the desired HLVD trip point. Set the VDIRMAG bit to detect high voltage (VDIRMAG = 1) or low voltage (VDIRMAG = 0). Enable the HLVD module by setting the HLVDEN bit. Clear the HLVD interrupt flag (PIR2<2>), which may have been set from a previous interrupt. Enable the HLVD interrupt if interrupts are desired by setting the HLVDIE and GIE bits (PIE2<2> and INTCON<7>). An interrupt will not be generated until the IRVST bit is set. 24.3 24.4 Current Consumption When the module is enabled, the HLVD comparator and voltage divider are enabled and will consume static current. The total current consumption, when enabled, is specified in electrical specification parameter D022B (Section 28.2 "DC Characteristics"). FIGURE 24-2: Depending on the application, the HLVD module does not need to be operating constantly. To decrease the current requirements, the HLVD circuitry may only need to be enabled for short periods where the voltage is checked. After doing the check, the HLVD module may be disabled. HLVD Start-up Time The internal reference voltage of the HLVD module, specified in electrical specification parameter D420 (Section 28.2 "DC Characteristics"), may be used by other internal circuitry, such as the Programmable Brown-out Reset. If the HLVD or other circuits using the voltage reference are disabled to lower the device's current consumption, the reference voltage circuit will require time to become stable before a low or high-voltage condition can be reliably detected. This start-up time, TIRVST, is an interval that is independent of device clock speed. It is specified in electrical specification parameter 36 (Table 28-12). The HLVD interrupt flag is not enabled until TIRVST has expired and a stable reference voltage is reached. For this reason, brief excursions beyond the set point may not be detected during this interval. Refer to Figure 24-2 or Figure 24-3. LOW-VOLTAGE DETECT OPERATION (VDIRMAG = 0) CASE 1: HLVDIF may not be set VDD VHLVD HLVDIF Enable HLVD TIRVST IRVST Internal Reference is stable HLVDIF cleared in software CASE 2: VDD VHLVD HLVDIF Enable HLVD TIRVST IRVST Internal Reference is stable HLVDIF cleared in software HLVDIF cleared in software, HLVDIF remains set since HLVD condition still exists 2004 Microchip Technology Inc. Preliminary DS39646B-page 293 PIC18F8722 FAMILY FIGURE 24-3: HIGH-VOLTAGE DETECT OPERATION (VDIRMAG = 1) CASE 1: HLVDIF may not be set VHLVD VDD HLVDIF Enable HLVD TIRVST IRVST HLVDIF cleared in software Internal Reference is stable CASE 2: VHLVD VDD HLVDIF Enable HLVD TIRVST IRVST Internal Reference is stable HLVDIF cleared in software HLVDIF cleared in software, HLVDIF remains set since HLVD condition still exists FIGURE 24-4: Applications In many applications, the ability to detect a drop below or rise above a particular threshold is desirable. For example, the HLVD module could be periodically enabled to detect Universal Serial Bus (USB) attach or detach. This assumes the device is powered by a lower voltage source than the USB when detached. An attach would indicate a high-voltage detect from, for example, 3.3V to 5V (the voltage on USB) and vice versa for a detach. This feature could save a design a few extra components and an attach signal (input pin). VA VB For general battery applications, Figure 24-4 shows a possible voltage curve. Over time, the device voltage decreases. When the device voltage reaches voltage VA, the HLVD logic generates an interrupt at time TA. The interrupt could cause the execution of an ISR, which would allow the application to perform "housekeeping tasks" and perform a controlled shutdown before the device voltage exits the valid operating range at TB. The HLVD, thus, would give the application a time window, represented by the difference between TA and TB, to safely exit. DS39646B-page 294 TYPICAL LOW-VOLTAGE DETECT APPLICATION Voltage 24.5 Preliminary Time TA TB Legend: VA = HLVD trip point VB = Minimum valid device operating voltage 2004 Microchip Technology Inc. PIC18F8722 FAMILY 24.6 Operation During Sleep 24.7 When enabled, the HLVD circuitry continues to operate during Sleep. If the device voltage crosses the trip point, the HLVDIF bit will be set and the device will wake-up from Sleep. Device execution will continue from the interrupt vector address if interrupts have been globally enabled. TABLE 24-1: Effects of a Reset A device Reset forces all registers to their Reset state. This forces the HLVD module to be turned off. REGISTERS ASSOCIATED WITH HIGH/LOW-VOLTAGE DETECT MODULE Name Bit 7 Bit 6 HLVDCON VDIRMAG -- INTCON GIE/GIEH PEIE/GIEL Reset Values on page Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 IRVST HLVDEN HLVDL3 HLVDL2 HLVDL1 HLVDL0 58 TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 57 PIR2 OSCFIF CMIF -- EEIF BCL1IF HLVDIF TMR3IF CCP2IF 60 PIE2 OSCFIE CMIE -- EEIE BCL1IE HLVDIE TMR3IE CCP2IE 60 IPR2 TRISA OSCFIP CMIP -- EEIP BCL1IP HLVDIP TMR3IP CCP2IP 60 TRISA7(1) TRISA6(1) TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 60 Legend: -- = unimplemented, read as `0'. Shaded cells are unused by the HLVD module. Note 1: PORTA<7:6> and their direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as `0'. 2004 Microchip Technology Inc. Preliminary DS39646B-page 295 PIC18F8722 FAMILY NOTES: DS39646B-page 296 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY 25.0 SPECIAL FEATURES OF THE CPU The PIC18F8722 family of devices include several features intended to maximize reliability and minimize cost through elimination of external components. These are: 25.1 Configuration Bits The configuration bits can be programmed (read as `0') or left unprogrammed (read as `1') to select various device configurations. These bits are mapped starting at program memory location 300000h. The user will note that address 300000h is beyond the user program memory space. In fact, it belongs to the configuration memory space (300000h-3FFFFFh), which can only be accessed using table reads and table writes. * Oscillator Selection * Resets: - Power-on Reset (POR) - Power-up Timer (PWRT) - Oscillator Start-up Timer (OST) - Brown-out Reset (BOR) * Interrupts * Watchdog Timer (WDT) * Fail-Safe Clock Monitor * Two-Speed Start-up * Code Protection * ID Locations * In-Circuit Serial Programming The oscillator can be configured for the application depending on frequency, power, accuracy and cost. All of the options are discussed in detail in Section 2.0 "Oscillator Configurations". Programming the Configuration registers is done in a manner similar to programming the Flash memory. The WR bit in the EECON1 register starts a self-timed write to the Configuration register. In normal operation mode, a TBLWT instruction with the TBLPTR pointing to the Configuration register sets up the address and the data for the Configuration register write. Setting the WR bit starts a long write to the Configuration register. The Configuration registers are written a byte at a time. To write or erase a configuration cell, a TBLWT instruction can write a `1' or a `0' into the cell. For additional details on Flash programming, refer to Section 6.5 "Writing to Flash Program Memory". A complete discussion of device Resets and interrupts is available in previous sections of this data sheet. In addition to their Power-up and Oscillator Start-up Timers provided for Resets, the PIC18F8722 family of devices has a Watchdog Timer, which is either permanently enabled via the configuration bits or software controlled (if configured as disabled). The inclusion of an internal RC oscillator also provides the additional benefits of a Fail-Safe Clock Monitor (FSCM) and Two-Speed Start-up. FSCM provides for background monitoring of the peripheral clock and automatic switchover in the event of its failure. TwoSpeed Start-up enables code to be executed almost immediately on start-up, while the primary clock source completes its start-up delays. All of these features are enabled and configured by setting the appropriate Configuration register bits. 2004 Microchip Technology Inc. Preliminary DS39646B-page 297 PIC18F8722 FAMILY TABLE 25-1: CONFIGURATION BITS AND DEVICE IDs Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default/ Unprogrammed Value 300001h CONFIG1H IESO FCMEN -- -- FOSC3 FOSC2 FOSC1 FOSC0 00-- 0111 300002h CONFIG2L -- -- -- BORV1 BORV0 300003h CONFIG2H -- -- -- File Name 300004h CONFIG3L(5) WDTPS3 WDTPS2 BOREN1 BOREN0 PWRTEN ---1 1111 WDTPS1 WDTPS0 WDTEN ---1 1111 -- PM1 PM0 1111 --11 WAIT BW ABW1 ABW0 -- 300005h CONFIG3H MCLRE -- -- -- -- 300006h CONFIG4L DEBUG XINST BBSIZ1 BBSIZ0 -- LVP -- STVREN 300008h CONFIG5L CP7(1) CP6(1) CP5(2) CP4(2) CP3(3) CP2 CP1 CP0 1111 1111 300009h CONFIG5H CPD CPB -- -- -- -- -- -- 11-- ---- WRT3(3) WRT2 WRT1 WRT0 1111 1111 -- -- -- -- 111- ---- EBTR2 EBTR1 EBTR0 1111 1111 -- -- -- -1-- ---- 30000Ah CONFIG6L 30000Bh CONFIG6H 30000Ch CONFIG7L 30000Dh CONFIG7H (4) WRT7(1) WRT6(1) WRT5(2) WRT4(2) WRTD WRTB WRTC -- EBRT7(1) EBRT6(1) EBTR5(2) EBTR4(2) EBTR3(3) -- EBTRB -- -- -- LPT1OSC ECCPMX(5) CCP2MX 1--- -011 1000 -1-1 3FFFFEh DEVID1 DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 xxxx xxxx 3FFFFFh DEVID2(4) DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 xxxx xxxx Legend: Note 1: 2: 3: 4: 5: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Shaded cells are unimplemented, read as `0'. Unimplemented in PIC18F6527/6622/6627/8527/8622/8627 devices. Unimplemented in PIC18F6527/6622/8527/8622 devices. Unimplemented in PIC18F6527/8527 devices. See Register 25-13 for DEVID1 values. DEVID registers are read-only and cannot be programmed by the user. Unimplemented in PIC18F6527/6622/6627/6722 devices. DS39646B-page 298 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY REGISTER 25-1: CONFIG1H: CONFIGURATION REGISTER 1 HIGH (BYTE ADDRESS 300001h) R/P-0 R/P-0 U-0 U-0 R/P-0 R/P-1 R/P-1 R/P-1 IESO FCMEN -- -- FOSC3 FOSC2 FOSC1 FOSC0 bit 7 bit 0 bit 7 IESO: Internal/External Oscillator Switchover bit 1 = Two-Speed Start-up enabled 0 = Two-Speed Start-up disabled bit 6 FCMEN: Fail-Safe Clock Monitor Enable bit 1 = Fail-Safe Clock Monitor enabled 0 = Fail-Safe Clock Monitor disabled bit 5-4 Unimplemented: Read as `0' bit 3-0 FOSC3:FOSC0: Oscillator Selection bits 11xx = External RC oscillator, CLKO function on RA6 101x = External RC oscillator, CLKO function on RA6 1001 = Internal oscillator block, CLKO function on RA6, port function on RA7 1000 = Internal oscillator block, port function on RA6 and RA7 0111 = External RC oscillator, port function on RA6 0110 = HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) 0101 = EC oscillator, port function on RA6 0100 = EC oscillator, CLKO function on RA6 0011 = External RC oscillator, CLKO function on RA6 0010 = HS oscillator 0001 = XT oscillator 0000 = LP oscillator Legend: R = Readable bit P = Programmable bit -n = Value when device is unprogrammed 2004 Microchip Technology Inc. Preliminary U = Unimplemented bit, read as `0' u = Unchanged from programmed state DS39646B-page 299 PIC18F8722 FAMILY REGISTER 25-2: CONFIG2L: CONFIGURATION REGISTER 2 LOW (BYTE ADDRESS 300002h) U-0 U-0 -- -- U-0 -- R/P-1 BORV1 (1) R/P-1 BORV0 (1) R/P-1 R/P-1 (2) BOREN1 R/P-1 (2) BOREN0 PWRTEN(2) bit 7 bit 0 bit 7-5 Unimplemented: Read as `0' bit 4-3 BORV1:BORV0: Brown-out Reset Voltage bits(1) 11 = Minimum setting . . . 00 = Maximum setting bit 2-1 BOREN1:BOREN0: Brown-out Reset Enable bits(2) 11 = Brown-out Reset enabled in hardware only (SBOREN is disabled) 10 = Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) 01 = Brown-out Reset enabled and controlled by software (SBOREN is enabled) 00 = Brown-out Reset disabled in hardware and software bit 0 PWRTEN: Power-up Timer Enable bit(2) 1 = PWRT disabled 0 = PWRT enabled Note 1: See Section 28.1 "DC Characteristics: Supply Voltage" for specifications. 2: The Power-up Timer is decoupled from Brown-out Reset, allowing these features to be independently controlled. Legend: R = Readable bit P = Programmable bit -n = Value when device is unprogrammed DS39646B-page 300 Preliminary U = Unimplemented bit, read as `0' u = Unchanged from programmed state 2004 Microchip Technology Inc. PIC18F8722 FAMILY REGISTER 25-3: CONFIG2H: CONFIGURATION REGISTER 2 HIGH (BYTE ADDRESS 300003h) U-0 U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 -- -- -- WDTPS3 WDTPS2 WDTPS1 WDTPS0 WDTEN bit 7 bit 0 bit 7-5 Unimplemented: Read as `0' bit 4-1 WDTPS3:WDTPS0: Watchdog Timer Postscale Select bits 1111 = 1:32,768 1110 = 1:16,384 1101 = 1:8,192 1100 = 1:4,096 1011 = 1:2,048 1010 = 1:1,024 1001 = 1:512 1000 = 1:256 0111 = 1:128 0110 = 1:64 0101 = 1:32 0100 = 1:16 0011 = 1:8 0010 = 1:4 0001 = 1:2 0000 = 1:1 bit 0 WDTEN: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled (control is placed on the SWDTEN bit) Legend: R = Readable bit P = Programmable bit -n = Value when device is unprogrammed 2004 Microchip Technology Inc. Preliminary U = Unimplemented bit, read as `0' u = Unchanged from programmed state DS39646B-page 301 PIC18F8722 FAMILY REGISTER 25-4: CONFIG3L: CONFIGURATION REGISTER 3 LOW (BYTE ADDRESS 300004h)(1) R/P-1 R/P-1 R/P-1 R/P-1 U-0 U-0 R/P-1 R/P-1 WAIT BW ABW1 ABW0 -- -- PM1 PM0 bit 7 bit 0 bit 7 WAIT: External Bus Data Wait Enable bit 1 = Wait selections are unavailable for table reads and table writes 0 = Wait selections for table reads and table writes are determined by the WAIT1:WAIT0 bits bit 6 BW: Data Bus Width Select bit 1 = 16-bit External Bus mode 0 = 8-bit External Bus mode bit 5-4 ABW<1:0>: Address Bus Width Select bits 11 = 20-bit address bus 10 = 16-bit address bus 01 = 12-bit address bus 00 = 8-bit address bus bit 3-2 Unimplemented: Read as `0' bit 1-0 PM<1:0>: Processor Data Memory Mode Select bits 11 = Microcontroller mode 10 = Microprocessor mode 01 = Microprocessor with Boot Block mode 00 = Extended Microcontroller mode Note 1: This register is unimplemented in PIC18F6527/6622/6627/6722 devices. Legend: R = Readable bit P = Programmable bit -n = Value when device is unprogrammed DS39646B-page 302 Preliminary U = Unimplemented bit, read as `0' u = Unchanged from programmed state 2004 Microchip Technology Inc. PIC18F8722 FAMILY REGISTER 25-5: CONFIG3H: CONFIGURATION REGISTER 3 HIGH (BYTE ADDRESS 300005h) R/P-1 U-0 U-0 U-0 U-0 MCLRE -- -- -- -- R/P-0 R/P-1 R/P-1 LPT1OSC ECCPMX(1) CCP2MX bit 7 bit 0 bit 7 MCLRE: MCLR Pin Enable bit 1 = MCLR pin enabled; RG5 input pin disabled 0 = RG5 input pin enabled; MCLR disabled bit 6-3 Unimplemented: Read as `0' bit 2 LPT1OSC: Low-Power Timer1 Oscillator Enable bit 1 = Timer1 configured for low-power operation 0 = Timer1 configured for higher power operation bit 1 ECCPMX: ECCP Mux bit(1) 1 = ECCP1/3 (P1B/P1C/P3B/P3C) are multiplexed onto RE6, RE5, RE4 and RE3 respectively 0 = ECCP1/3 (P1B/P1C/P3B/P3C) are multiplexed onto RH7, RH6, RH5 and RH4 respectively bit 0 CCP2MX: CCP2 Mux bit 1 = ECCP2 input/output is multiplexed with RC1 0 = ECCP2 input/output is multiplexed with RB3 in Extended Microcontroller, Microprocessor or Microprocessor with Boot Block mode(1). ECCP2 is multiplexed with RE7 in Microcontroller mode. Note 1: This feature is only available on PIC18F8527/8622/8627/8722 devices. Legend: R = Readable bit P = Programmable bit -n = Value when device is unprogrammed 2004 Microchip Technology Inc. Preliminary U = Unimplemented bit, read as `0' u = Unchanged from programmed state DS39646B-page 303 PIC18F8722 FAMILY REGISTER 25-6: CONFIG4L: CONFIGURATION REGISTER 4 LOW (BYTE ADDRESS 300006h) R/P-1 R/P-0 R/P-0 R/P-0 U-0 R/P-1 U-0 R/P-1 DEBUG XINST BBSIZ1 BBSIZ0 -- LVP -- STVREN bit 7 bit 0 bit 7 DEBUG: Background Debugger Enable bit 1 = Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins 0 = Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug bit 6 XINST: Extended Instruction Set Enable bit 1 = Instruction set extension and Indexed Addressing mode enabled 0 = Instruction set extension and Indexed Addressing mode disabled (Legacy mode) bit 5-4 BBSIZ<1:0>: Boot Block Size Select bits 11 = 4K words (8 Kbytes) Boot Block size 10 = 4K words (8 Kbytes) Boot Block size 01 = 2K words (4 Kbytes) Boot Block size 00 = 1K word (2 Kbytes) Boot Block size bit 3 Unimplemented: Read as `0' bit 2 LVP: Single-Supply ICSPTM Enable bit 1 = Single-Supply ICSP enabled 0 = Single-Supply ICSP disabled bit 1 Unimplemented: Read as `0' bit 0 STVREN: Stack Full/Underflow Reset Enable bit 1 = Stack full/underflow will cause Reset 0 = Stack full/underflow will not cause Reset Legend: R = Readable bit C = Clearable bit -n = Value when device is unprogrammed DS39646B-page 304 Preliminary U = Unimplemented bit, read as `0' u = Unchanged from programmed state 2004 Microchip Technology Inc. PIC18F8722 FAMILY REGISTER 25-7: CONFIG5L: CONFIGURATION REGISTER 5 LOW (BYTE ADDRESS 300008h) R/C-1 R/C-1 R/C-1 R/C-1 R/C-1 R/C-1 R/C-1 R/C-1 CP7(1) CP6(1) CP5(2) CP5(2) CP3(3) CP2 CP1 CP0 bit 7 bit 0 bit 7 CP7: Code Protection bit(1) 1 = Block 7 (01C000-01FFFFh) not code-protected 0 = Block 7 (01C000-01FFFFh) code-protected bit 6 CP6: Code Protection bit(1) 1 = Block 6 (01BFFF-018000h) not code-protected 0 = Block 6 (01BFFF-018000h) code-protected bit 5 CP5: Code Protection bit(2) 1 = Block 5 (014000-017FFFh) not code-protected 0 = Block 5 (014000-017FFFh) code-protected bit 4 CP4: Code Protection bit(2) 1 = Block 4 (010000-013FFFh) not code-protected 0 = Block 4 (010000-013FFFh) code-protected bit 3 CP3: Code Protection bit(3) 1 = Block 3 (00C000-00FFFFh) not code-protected 0 = Block 3 (00C000-00FFFFh) code-protected bit 2 CP2: Code Protection bit 1 = Block 2 (008000-00BFFFh) not code-protected 0 = Block 2 (008000-00BFFFh) code-protected bit 1 CP1: Code Protection bit 1 = Block 1 (004000-007FFFh) not code-protected 0 = Block 1 (004000-007FFFh) code-protected bit 0 CP0: Code Protection bit 1 = Block 0 (000800, 001000 or 002000(4)-003FFFh) not code-protected 0 = Block 0 (000800, 001000 or 002000(4)-003FFFh) code-protected Note 1: Unimplemented in PIC18F6527/6622/6627/8527/8622/8627 devices; maintain this bit set. 2: Unimplemented in PIC18F6527/6622/8527/8622 devices; maintain this bit set. 3: Unimplemented in PIC18F6527/8527 devices; maintain this bit set. 4: Boot Block size is determined by the BBSIZ<1:0> bits in CONFIG4L. Legend: R = Readable bit C = Clearable bit -n = Value when device is unprogrammed 2004 Microchip Technology Inc. Preliminary U = Unimplemented bit, read as `0' u = Unchanged from programmed state DS39646B-page 305 PIC18F8722 FAMILY REGISTER 25-8: CONFIG5H: CONFIGURATION REGISTER 5 HIGH (BYTE ADDRESS 300009h) R/C-1 R/C-1 U-0 U-0 U-0 U-0 U-0 U-0 CPD CPB -- -- -- -- -- -- bit 7 bit 0 bit 7 CPD: Data EEPROM Code Protection bit 1 = Data EEPROM not code-protected 0 = Data EEPROM code-protected bit 6 CPB: Boot Block Code Protection bit 1 = Boot Block (000000-0007FFh) not code-protected 0 = Boot Block (000000-0007FFh) code-protected bit 5-0 Unimplemented: Read as `0' Legend: R = Readable bit C = Clearable bit -n = Value when device is unprogrammed DS39646B-page 306 Preliminary U = Unimplemented bit, read as `0' u = Unchanged from programmed state 2004 Microchip Technology Inc. PIC18F8722 FAMILY REGISTER 25-9: CONFIG6L: CONFIGURATION REGISTER 6 LOW (BYTE ADDRESS 30000Ah) R/C-1 R/C-1 R/C-1 R/C-1 R/C-1 R/C-1 R/C-1 R/C-1 WRT7 WRT6 WRT5(2) WRT4(2) WRT3(3) WRT2 WRT1 WRT0 bit 7 bit 0 bit 7 WRT7: Write Protection bit(1) 1 = Block 7 (01C000-01FFFFh) not write-protected 0 = Block 7 (01C000-01FFFFh) write-protected bit 6 WRT6: Write Protection bit(1) 1 = Block 6 (01BFFF-018000h) not write-protected 0 = Block 6 (01BFFF-018000h) write-protected bit 5 WRT5: Write Protection bit(2) 1 = Block 5 (014000-017FFFh) not write-protected 0 = Block 5 (014000-017FFFh) write-protected bit 4 WRT4: Write Protection bit(2) 1 = Block 4 (010000-013FFFh) not write-protected 0 = Block 4 (010000-013FFFh) write-protected bit 3 WRT3: Write Protection bit(3) 1 = Block 3 (00C000-00FFFFh) not write-protected 0 = Block 3 (00C000-00FFFFh) write-protected bit 2 WRT2: Write Protection bit 1 = Block 2 (008000-00BFFFh) not write-protected 0 = Block 2 (008000-00BFFFh) write-protected bit 1 WRT1: Write Protection bit 1 = Block 1 (004000-007FFFh) not write-protected 0 = Block 1 (004000-007FFFh) write-protected bit 0 WRT0: Write Protection bit 1 = Block 0 (000800, 001000 or 002000(4)-003FFFh) not write-protected 0 = Block 0 (000800, 001000 or 002000(4)-003FFFh) write-protected Note 1: Unimplemented in PIC18F6527/6622/6627/8527/8622/8627 devices; maintain this bit set. 2: Unimplemented in PIC18F6527/6622/8527/8622 devices; maintain this bit set. 3: Unimplemented in PIC18F6527/8527 devices; maintain this bit set. 4: Boot Block size is determined by the BBSIZ<1:0> bits in CONFIG4L. Legend: R = Readable bit C = Clearable bit -n = Value when device is unprogrammed 2004 Microchip Technology Inc. Preliminary U = Unimplemented bit, read as `0' u = Unchanged from programmed state DS39646B-page 307 PIC18F8722 FAMILY REGISTER 25-10: CONFIG6H: CONFIGURATION REGISTER 6 HIGH (BYTE ADDRESS 30000Bh) R/C-1 R/C-1 R-1 U-0 U-0 U-0 U-0 U-0 WRTD WRTB WRTC(1) -- -- -- -- -- bit 7 bit 0 bit 7 WRTD: Data EEPROM Write Protection bit 1 = Data EEPROM not write-protected 0 = Data EEPROM write-protected bit 6 WRTB: Boot Block Write Protection bit 1 = Boot Block (000000-007FFF, 000FFF or 001FFFh(1)) not write-protected 0 = Boot Block (000000-007FFF, 000FFF or 001FFFh(1)) write-protected bit 5 WRTC: Configuration Register Write Protection bit(2) 1 = Configuration registers (300000-3000FFh) not write-protected 0 = Configuration registers (300000-3000FFh) write-protected bit 4-0 Unimplemented: Read as `0' Note 1: Boot Block size is determined by the BBSIZ<1:0> bits in CONFIG4L. 2: This bit is read-only in normal execution mode; it can be written only in Program mode. Legend: R = Readable bit C = Clearable bit -n = Value when device is unprogrammed DS39646B-page 308 Preliminary U = Unimplemented bit, read as `0' u = Unchanged from programmed state 2004 Microchip Technology Inc. PIC18F8722 FAMILY REGISTER 25-11: CONFIG7L: CONFIGURATION REGISTER 7 LOW (BYTE ADDRESS 30000Ch) R/C-1 R/C-1 R/C-1 R/C-1 EBTR7(1) EBTR6(1) EBTR5(2) EBTR4(2) R/C-1 R/C-1 R/C-1 R/C-1 EBTR3(3) EBTR2 EBTR1 EBTR0 bit 7 bit 0 bit 7 EBTR7: Table Read Protection bit(1) 1 = Block 7 (01C000-01FFFFh) not protected from table reads executed in other blocks 0 = Block 7 (01C000-01FFFFh) protected from table reads executed in other blocks bit 6 EBTR6: Table Read Protection bit(1) 1 = Block 6 (018000-01BFFFh) not protected from table reads executed in other blocks 0 = Block 6 (018000-01BFFFh) protected from table reads executed in other blocks bit 5 EBTR5: Table Read Protection bit(2) 1 = Block 5 (014000-017FFFh) not protected from table reads executed in other blocks 0 = Block 5 (014000-017FFFh) protected from table reads executed in other blocks bit 4 EBTR4: Table Read Protection bit(2) 1 = Block 4 (010000-013FFFh) not protected from table reads executed in other blocks 0 = Block 4 (010000-013FFFh) protected from table reads executed in other blocks bit 3 EBTR3: Table Read Protection bit(3) 1 = Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks 0 = Block 3 (00C000-00FFFFh) protected from table reads executed in other blocks bit 2 EBTR2: Table Read Protection bit 1 = Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks 0 = Block 2 (008000-00BFFFh) protected from table reads executed in other blocks bit 1 EBTR1: Table Read Protection bit 1 = Block 1 (004000-007FFFh) not protected from table reads executed in other blocks 0 = Block 1 (004000-007FFFh) protected from table reads executed in other blocks bit 0 EBTR0: Table Read Protection bit 1 = Block 0 (000800, 001000 or 002000(4)-003FFFh) not protected from table reads executed in other blocks 0 = Block 0 (000800, 001000 or 002000(4)-003FFFh) protected from table reads executed in other blocks Note 1: Unimplemented in PIC18F6527/6622/6627/8527/8622/8627 devices; maintain this bit set. 2: Unimplemented in PIC18F6527/6622/8527/8622 devices; maintain this bit set. 3: Unimplemented in PIC18F6527/8527 devices; maintain this bit set. 4: Boot Block size is determined by the BBSIZ<1:0> bit in CONFIG4L. Legend: R = Readable bit C = Clearable bit -n = Value when device is unprogrammed 2004 Microchip Technology Inc. Preliminary U = Unimplemented bit, read as `0' u = Unchanged from programmed state DS39646B-page 309 PIC18F8722 FAMILY REGISTER 25-12: CONFIG7H: CONFIGURATION REGISTER 7 HIGH (BYTE ADDRESS 30000Dh) U-0 R/C-1 U-0 U-0 U-0 U-0 U-0 U-0 -- EBTRB -- -- -- -- -- -- bit 7 bit 0 bit 7 Unimplemented: Read as `0' bit 6 EBTRB: Boot Block Table Read Protection bit 1 = Boot Block (000000-007FFF, 000FFF or 001FFFh(1)) not protected from table reads executed in other blocks 0 = Boot Block (000000-007FFF, 000FFF or 001FFFh(1)) protected from table reads executed in other blocks bit 5-0 Unimplemented: Read as `0' Note 1: Boot Block size is determined by the BBSIZ<1:0> bits in CONFIG4L. Legend: R = Readable bit C = Clearable bit -n = Value when device is unprogrammed DS39646B-page 310 Preliminary U = Unimplemented bit, read as `0' u = Unchanged from programmed state 2004 Microchip Technology Inc. PIC18F8722 FAMILY REGISTER 25-13: DEVID1: DEVICE ID REGISTER 1 FOR THE PIC18F8722 FAMILY R R R R R R R R DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 bit 7 bit 0 bit 7-5 DEV2:DEV0: Device ID bits 001 = PIC18F8722 111 = PIC18F8627 101 = PIC18F8622 011 = PIC18F8527 000 = PIC18F6722 110 = PIC18F6627 100 = PIC18F6622 010 = PIC18F6527 bit 4-0 REV4:REV0: Revision ID bits These bits are used to indicate the device revision. Legend: R = Read-only bit P = Programmable bit -n = Value when device is unprogrammed U = Unimplemented bit, read as `0' u = Unchanged from programmed state REGISTER 25-14: DEVID2: DEVICE ID REGISTER 2 FOR THE PIC18F8722 FAMILY R R R R R R R R DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 bit 7 bit 7-0 bit 0 DEV10:DEV3: Device ID bits These bits are used with the DEV2:DEV0 bits in the Device ID Register 1 to identify the part number. 0001 0100 = PIC18F6722/8722 devices 0001 0011 = PIC18F6527/6622/6627/8527/8622/8627 devices Note: These values for DEV10:DEV3 may be shared with other devices. The specific device is always identified by using the entire DEV10:DEV0 bit sequence. Legend: R = Read-only bit P = Programmable bit -n = Value when device is unprogrammed 2004 Microchip Technology Inc. Preliminary U = Unimplemented bit, read as `0' u = Unchanged from programmed state DS39646B-page 311 PIC18F8722 FAMILY 25.2 Watchdog Timer (WDT) For the PIC18F8722 family of devices, the WDT is driven by the INTRC source. When the WDT is enabled, the clock source is also enabled. The nominal WDT period is 4 ms and has the same stability as the INTRC oscillator. The 4 ms period of the WDT is multiplied by a 16-bit postscaler. Any output of the WDT postscaler is selected by a multiplexor, controlled by bits in Configuration Register 2H. Available periods range from 4 ms to 131.072 seconds (2.18 minutes). The WDT and postscaler are cleared when any of the following events occur: a SLEEP or CLRWDT instruction is executed, the IRCF bits (OSCCON<6:4>) are changed or a clock failure has occurred. FIGURE 25-1: SWDTEN WDTEN Note 1: The CLRWDT and SLEEP instructions clear the WDT and postscaler counts when executed. 2: Changing the setting of the IRCF bits (OSCCON<6:4>) clears the WDT and postscaler counts. 3: When a CLRWDT instruction is executed, the postscaler count will be cleared. 25.2.1 CONTROL REGISTER Register 25-15 shows the WDTCON register. This is a readable and writable register which contains a control bit that allows software to override the WDT enable configuration bit, but only if the configuration bit has disabled the WDT. WDT BLOCK DIAGRAM Enable WDT WDT Counter INTRC Source /128 Wake-up from Power-Managed Modes Change on IRCF bits Programmable Postscaler 1:1 to 1:32,768 CLRWDT Reset WDT Reset All Device Resets WDTPS<4:1> 4 Sleep DS39646B-page 312 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY REGISTER 25-15: WDTCON: WATCHDOG TIMER CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 -- -- -- -- -- -- -- SWDTEN(1) bit 7 bit 0 bit 7-1 Unimplemented: Read as `0' bit 0 SWDTEN: Software Controlled Watchdog Timer Enable bit(1) 1 = Watchdog Timer is on 0 = Watchdog Timer is off Note 1: This bit has no effect if the configuration bit, WDTEN, is enabled. Legend: TABLE 25-2: Name RCON WDTCON R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR SUMMARY OF WATCHDOG TIMER REGISTERS Bit 0 Reset Values on page Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 IPEN SBOREN -- RI TO PD POR BOR 56 -- -- -- -- -- -- -- SWDTEN 58 Legend: -- = unimplemented, read as `0'. Shaded cells are not used by the Watchdog Timer. 2004 Microchip Technology Inc. Preliminary DS39646B-page 313 PIC18F8722 FAMILY 25.3 Two-Speed Start-up In all other power-managed modes, Two-Speed Startup is not used. The device will be clocked by the currently selected clock source until the primary clock source becomes available. The setting of the IESO bit is ignored. The Two-Speed Start-up feature helps to minimize the latency period from oscillator start-up to code execution by allowing the microcontroller to use the INTOSC oscillator as a clock source until the primary clock source is available. It is enabled by setting the IESO configuration bit. 25.3.1 Two-Speed Start-up should be enabled only if the primary oscillator mode is LP, XT, HS or HSPLL (crystal-based modes). Other sources do not require an OST start-up delay; for these, Two-Speed Start-up should be disabled. While using the INTOSC oscillator in Two-Speed Startup, the device still obeys the normal command sequences for entering power-managed modes, including multiple SLEEP instructions (refer to Section 3.1.4 "Multiple Sleep Commands"). In practice, this means that user code can change the SCS1:SCS0 bit settings or issue SLEEP instructions before the OST times out. This would allow an application to briefly wake-up, perform routine "housekeeping" tasks and return to Sleep before the device starts to operate from the primary oscillator. When enabled, Resets and wake-ups from Sleep mode cause the device to configure itself to run from the internal oscillator block as the clock source, following the time-out of the Power-up Timer after a Power-on Reset is enabled. This allows almost immediate code execution while the primary oscillator starts and the OST is running. Once the OST times out, the device automatically switches to PRI_RUN mode. User code can also check if the primary clock source is currently providing the device clocking by checking the status of the OSTS bit (OSCCON<3>). If the bit is set, the primary oscillator is providing the clock. Otherwise, the internal oscillator block is providing the clock during wake-up from Reset or Sleep mode. To use a higher clock speed on wake-up, the INTOSC or postscaler clock sources can be selected to provide a higher clock speed by setting bits IRCF2:IRCF0 immediately after Reset. For wake-ups from Sleep, the INTOSC or postscaler clock sources can be selected by setting the IRCF2:IRCF0 bits prior to entering Sleep mode. FIGURE 25-2: SPECIAL CONSIDERATIONS FOR USING TWO-SPEED START-UP TIMING TRANSITION FOR TWO-SPEED START-UP (INTOSC TO HSPLL) Q1 Q3 Q2 Q4 Q2 Q3 Q4 Q1 Q2 Q3 Q1 INTOSC Multiplexor OSC1 TOST(1) TPLL(1) 1 PLL Clock Output 2 n-1 n Clock Transition(2) CPU Clock Peripheral Clock Program Counter PC Wake from Interrupt Event Note 1: 2: DS39646B-page 314 PC + 4 PC + 2 PC + 6 OSTS bit Set TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale. Clock transition typically occurs within 2-4 TOSC. Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY 25.4 Fail-Safe Clock Monitor The Fail-Safe Clock Monitor (FSCM) allows the microcontroller to continue operation in the event of an external oscillator failure by automatically switching the device clock to the internal oscillator block. The FSCM function is enabled by setting the FCMEN configuration bit. When FSCM is enabled, the INTRC oscillator runs at all times to monitor clocks to peripherals and provide a backup clock in the event of a clock failure. Clock monitoring (shown in Figure 25-3) is accomplished by creating a sample clock signal, which is the INTRC output divided by 64. This allows ample time between FSCM sample clocks for a peripheral clock edge to occur. The peripheral device clock and the sample clock are presented as inputs to the Clock Monitor latch (CM). The CM is set on the falling edge of the device clock source, but cleared on the rising edge of the sample clock. FIGURE 25-3: FSCM BLOCK DIAGRAM Clock Monitor Latch (CM) (edge-triggered) Peripheral Clock INTRC Source (32 s) / 64 S Q C Q To use a higher clock speed on wake-up, the INTOSC or postscaler clock sources can be selected to provide a higher clock speed by setting bits, IRCF2:IRCF0, immediately after Reset. For wake-ups from Sleep, the INTOSC or postscaler clock sources can be selected by setting the IRCF2:IRCF0 bits prior to entering Sleep mode. The FSCM will detect failures of the primary or secondary clock sources only. If the internal oscillator block fails, no failure would be detected, nor would any action be possible. 25.4.1 Both the FSCM and the WDT are clocked by the INTRC oscillator. Since the WDT operates with a separate divider and counter, disabling the WDT has no effect on the operation of the INTRC oscillator when the FSCM is enabled. As already noted, the clock source is switched to the INTOSC clock when a clock failure is detected. Depending on the frequency selected by the IRCF2:IRCF0 bits, this may mean a substantial change in the speed of code execution. If the WDT is enabled with a small prescale value, a decrease in clock speed allows a WDT time-out to occur and a subsequent device Reset. For this reason, fail-safe clock events also reset the WDT and postscaler, allowing it to start timing from when execution speed was changed and decreasing the likelihood of an erroneous time-out. 25.4.2 488 Hz (2.048 ms) Clock Failure Detected Clock failure is tested for on the falling edge of the sample clock. If a sample clock falling edge occurs while CM is still set, a clock failure has been detected (Figure 25-4). This causes the following: * the FSCM generates an oscillator fail interrupt by setting bit, OSCFIF (PIR2<7>); * the device clock source is switched to the internal oscillator block (OSCCON is not updated to show the current clock source - this is the fail-safe condition) and * the WDT is reset. FSCM AND THE WATCHDOG TIMER EXITING FAIL-SAFE OPERATION The fail-safe condition is terminated by either a device Reset or by entering a power-managed mode. On Reset, the controller starts the primary clock source specified in Configuration Register 1H (with any required start-up delays that are required for the oscillator mode, such as OST or PLL timer). The INTOSC multiplexor provides the device clock until the primary clock source becomes ready (similar to a TwoSpeed Start-up). The clock source is then switched to the primary clock (indicated by the OSTS bit in the OSCCON register becoming set). The Fail-Safe Clock Monitor then resumes monitoring the peripheral clock. The primary clock source may never become ready during start-up. In this case, operation is clocked by the INTOSC multiplexor. The OSCCON register will remain in its Reset state until a power-managed mode is entered. During switchover, the postscaler frequency from the internal oscillator block may not be sufficiently stable for timing sensitive applications. In these cases, it may be desirable to select another clock configuration and enter an alternate power-managed mode. This can be done to attempt a partial recovery or execute a controlled shutdown. See Section 3.1.4 "Multiple Sleep Commands" and Section 25.3.1 "Special Considerations for Using Two-Speed Start-up" for more details. 2004 Microchip Technology Inc. Preliminary DS39646B-page 315 PIC18F8722 FAMILY FIGURE 25-4: FSCM TIMING DIAGRAM Sample Clock Oscillator Failure Device Clock Output CM Output (Q) Failure Detected OSCFIF CM Test Note: 25.4.3 CM Test FSCM INTERRUPTS IN POWER-MANAGED MODES By entering a power-managed mode, the clock multiplexor selects the clock source selected by the OSCCON register. Fail-Safe Monitoring of the powermanaged clock source resumes in the power-managed mode. If an oscillator failure occurs during power-managed operation, the subsequent events depend on whether or not the oscillator failure interrupt is enabled. If enabled (OSCFIF = 1), code execution will be clocked by the INTOSC multiplexer. An automatic transition back to the failed clock source will not occur. For oscillator modes involving a crystal or resonator (HS, HSPLL, LP or XT), the situation is somewhat different. Since the oscillator may require a start-up time considerably longer than the FCSM sample clock time, a false clock failure may be detected. To prevent this, the internal oscillator block is automatically configured as the device clock and functions until the primary clock is stable (the OST and PLL timers have timed out). This is identical to Two-Speed Start-up mode. Once the primary clock is stable, the INTRC returns to its role as the FSCM source. Note: If the interrupt is disabled, subsequent interrupts while in Idle mode will cause the CPU to begin executing instructions while being clocked by the INTOSC source. 25.4.4 CM Test The device clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity. POR OR WAKE FROM SLEEP The FSCM is designed to detect oscillator failure at any point after the device has exited Power-on Reset (POR) or low-power Sleep mode. When the primary device clock is EC, RC or INTRC modes, monitoring can begin immediately following these events. DS39646B-page 316 The same logic that prevents false oscillator failure interrupts on POR, or wake from Sleep, will also prevent the detection of the oscillator's failure to start at all following these events. This can be avoided by monitoring the OSTS bit and using a timing routine to determine if the oscillator is taking too long to start. Even so, no oscillator failure interrupt will be flagged. As noted in Section 25.3.1 "Special Considerations for Using Two-Speed Start-up", it is also possible to select another clock configuration and enter an alternate power-managed mode while waiting for the primary clock to become stable. When the new powermanaged mode is selected, the primary clock is disabled. Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY 25.5 Program Verification and Code Protection Each of the blocks has three code protection bits associated with them. They are: The user program memory is divided into four blocks for PIC18F6527/8527 devices, five blocks for PIC18F6622/8622 devices, six blocks for PIC18F6627/ 8627 devices and eight blocks for PIC18F6722/8722 devices. One of these is a Boot Block of 2, 4 or 8 Kbytes. The remainder of the memory is divided into blocks on binary boundaries. FIGURE 25-5: * Code-Protect bit (CPn) * Write-Protect bit (WRTn) * External Block Table Read bit (EBTRn) Figure 25-5 shows the program memory organization for 48, 64, 96 and 128-Kbyte devices and the specific code protection bit associated with each block. The actual locations of the bits are summarized in Table 25-3. CODE-PROTECTED PROGRAM MEMORY FOR THE PIC18F8722 FAMILY 000000h MEMORY SIZE/DEVICE Code Memory 01FFFFh 128 Kbytes (PIC18FX722) 96 Kbytes (PIC18FX627) 64 Kbytes (PIC18FX622) 48 Kbytes (PIC18FX527) Address Range 000000h Boot Block Boot Block Boot Block Boot Block Unimplemented Read as `0' Block 0 Block 0 Block 0 0007FFh* or 000FFFh* or 001FFFh* 000800h* or 001000h* or 002000h* Block 0 003FFFh 004000h Block 1 Block 1 Block 1 Block 1 007FFFh 008000h 200000h Block 2 Block 2 Block 2 Block 2 00BFFFh 00C000h Configuration and ID Space Block 3 Block 3 Block 3 00FFFFh 010000h Block 4 Block 4 013FFFh 014000h Block 5 Unimplemented Read `0's Block 5 3FFFFFh Unimplemented Read `0's 017FFFh 018000h Block 6 Unimplemented Read `0's 01BFFFh 01C000h Block 7 01FFFFh Note: * Sizes of memory areas are not to scale. Boot Block size is determined by the BBSIZ<1:0> bits in CONFIG4L. 2004 Microchip Technology Inc. Preliminary DS39646B-page 317 PIC18F8722 FAMILY TABLE 25-3: SUMMARY OF CODE PROTECTION REGISTERS File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 300008h CONFIG5L CP7(1) CP6(1) CP5(2) CP4(2) CP3(3) CP2 CP1 CP0 300009h CONFIG5H CPD CPB -- -- -- -- -- -- WRT2 WRT1 WRT0 -- -- -- EBTR2 EBTR1 EBTR0 -- -- -- 30000Ah CONFIG6L WRT7 (1) 30000Bh CONFIG6H WRTD 30000Ch CONFIG7L EBRT7(1) 30000Dh CONFIG7H -- Legend: Note 1: 2: 3: 25.5.1 (1) WRT6 WRTB EBRT6 (1) EBTRB WRT5 (2) WRT4 EBTR5 WRT3 -- WRTC (2) (2) -- (2) EBTR4 -- (3) (3) EBTR3 -- -- Shaded cells are unimplemented. Unimplemented in PIC18F6527/6622/6627/8527/8622/8627 devices; maintain this bit set. Unimplemented in PIC18F6527/6622/8527/8622 devices; maintain this bit set. Unimplemented in PIC18F6527/8527 devices; maintain this bit set. PROGRAM MEMORY CODE PROTECTION The program memory may be read to or written from any location using the table read and table write instructions. The device ID may be read with table reads. The Configuration registers may be read and written with the table read and table write instructions. not allowed to read and will result in reading `0's. Figures 25-6 through 25-8 illustrate table write and table read protection. Note: In normal execution mode, the CPn bits have no direct effect. CPn bits inhibit external reads and writes. A block of user memory may be protected from table writes if the WRTn configuration bit is `0'. The EBTRn bits control table reads. For a block of user memory with the EBTRn bit set to `0', a table read instruction that executes from within that block is allowed to read. A table read instruction that executes from a location outside of that block is FIGURE 25-6: Code protection bits may only be written to a `0' from a `1' state. It is not possible to write a `1' to a bit in the `0' state. Code protection bits are only set to `1' by a full chip erase or block erase function. The full chip erase and block erase functions can only be initiated via ICSP or an external programmer. Refer to the device programming specification for more information. TABLE WRITE (WRTn) DISALLOWED Register Values Program Memory Configuration Bit Settings 000000h 0007FFh 000800h WRTB, EBTRB = 11 TBLPTR = 0008FFh WRT0, EBTR0 = 01 PC = 003FFEh TBLWT* 003FFFh 004000h WRT1, EBTR1 = 11 007FFFh 008000h PC = 00BFFEh WRT2, EBTR2 = 11 TBLWT* 00BFFFh 00C000h WRT3, EBTR3 = 11 00FFFFh Results: All table writes disabled to Blockn whenever WRTn = 0. DS39646B-page 318 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY FIGURE 25-7: EXTERNAL BLOCK TABLE READ (EBTRn) DISALLOWED Register Values Program Memory Configuration Bit Settings 000000h 0007FFh 000800h WRTB, EBTRB = 11 TBLPTR = 0008FFh WRT0, EBTR0 = 10 003FFFh 004000h PC = 007FFEh TBLRD* WRT1, EBTR1 = 11 007FFFh 008000h WRT2, EBTR2 = 11 00BFFFh 00C000h WRT3, EBTR3 = 11 00FFFFh Results: All table reads from external blocks to Blockn are disabled whenever EBTRn = 0. TABLAT register returns a value of `0'. FIGURE 25-8: EXTERNAL BLOCK TABLE READ (EBTRn) ALLOWED Register Values Program Memory Configuration Bit Settings 000000h WRTB, EBTRB = 11 0007FFh 000800h TBLPTR = 0008FFh PC = 003FFEh WRT0, EBTR0 = 10 TBLRD* 003FFFh 004000h WRT1, EBTR1 = 11 007FFFh 008000h WRT2, EBTR2 = 11 00BFFFh 00C000h WRT3, EBTR3 = 11 00FFFFh Results: Table reads permitted within Blockn, even when EBTRBn = 0. TABLAT register returns the value of the data at the location TBLPTR. 2004 Microchip Technology Inc. Preliminary DS39646B-page 319 PIC18F8722 FAMILY 25.5.2 DATA EEPROM CODE PROTECTION The entire data EEPROM is protected from external reads and writes by two bits: CPD and WRTD. CPD inhibits external reads and writes of data EEPROM. WRTD inhibits internal and external writes to data EEPROM. The CPU can always read data EEPROM under normal operation, regardless of the protection bit settings. 25.5.3 CONFIGURATION REGISTER PROTECTION The Configuration registers can be write-protected. The WRTC bit controls protection of the Configuration registers. In normal execution mode, the WRTC bit is readable only. WRTC can only be written via ICSP or an external programmer. 25.6 ID Locations Eight memory locations (200000h-200007h) are designated as ID locations, where the user can store checksum or other code identification numbers. These locations are both readable and writable during normal execution through the TBLRD and TBLWT instructions or during program/verify. The ID locations can be read when the device is code-protected. 25.7 25.9 In-Circuit Debugger When the DEBUG configuration bit is programmed to a `0', the In-Circuit Debugger functionality is enabled. This function allows simple debugging functions when used with MPLAB(R) IDE. When the microcontroller has this feature enabled, some resources are not available for general use. Table 25-4 shows which resources are required by the background debugger. TABLE 25-4: DEBUGGER RESOURCES I/O pins: RB6, RB7 Stack: 2 levels Program Memory: 512 bytes Data Memory: 10 bytes DS39646B-page 320 Single-Supply ICSP Programming The LVP configuration bit enables Single-Supply ICSP Programming (formerly known as Low-Voltage ICSP Programming or LVP). When Single-Supply Programming is enabled, the microcontroller can be programmed without requiring high voltage being applied to the RG5/MCLR/VPP pin, but the RB5/KBI1/PGM pin is then dedicated to controlling Program mode entry and is not available as a general purpose I/O pin. While programming, using single-supply programming mode, VDD is applied to the RG5/MCLR/VPP pin as in normal execution mode. To enter Programming mode, VDD is applied to the PGM pin. Note 1: High-voltage programming is always available, regardless of the state of the LVP bit or the PGM pin, by applying VIHH to the MCLR pin. 2: By default, Single-Supply ICSP is enabled in unprogrammed devices (as supplied from Microchip) and erased devices. In-Circuit Serial Programming The PIC18F8722 family of devices can be serially programmed while in the end application circuit. This is simply done with two lines for clock and data and three other lines for power, ground and the programming voltage. This allows customers to manufacture boards with unprogrammed devices and then program the microcontroller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed. 25.8 To use the In-Circuit Debugger function of the microcontroller, the design must implement In-Circuit Serial Programming connections to RG5/MCLR/VPP, VDD, VSS, RB7 and RB6. This will interface to the In-Circuit Debugger module available from Microchip or one of the third party development tool companies. 3: When Single-Supply Programming is enabled, the RB5 pin can no longer be used as a general purpose I/O pin. 4: When LVP is enabled, externally pull the PGM pin to VSS to allow normal program execution. If Single-Supply ICSP Programming mode will not be used, the LVP bit can be cleared. RB5/KBI1/PGM then becomes available as the digital I/O pin, RB5. The LVP bit may be set or cleared only when using standard high-voltage programming (VIHH applied to the RG5/ MCLR/VPP pin). Once LVP has been disabled, only the standard high-voltage programming is available and must be used to program the device. Memory that is not code-protected can be erased using a block erase, or erased row by row, then written at any specified VDD. If code-protected memory is to be erased, a block erase is required. If a block erase is to be performed when using Low-Voltage Programming, the device must be supplied with VDD of 4.5V to 5.5V. Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY 26.0 INSTRUCTION SET SUMMARY The PIC18F8722 family of devices incorporates the standard set of 75 PIC18 core instructions, as well as an extended set of 8 new instructions for the optimization of code that is recursive or that utilizes a software stack. The extended set is discussed later in this section. 26.1 Standard Instruction Set The standard PIC18 instruction set adds many enhancements to the previous PICmicro(R) instruction sets, while maintaining an easy migration from these PICmicro instruction sets. Most instructions are a single program memory word (16 bits), but there are four instructions that require two program memory locations. Each single-word instruction is a 16-bit word divided into an opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction. The instruction set is highly orthogonal and is grouped into four basic categories: * * * * Byte-oriented operations Bit-oriented operations Literal operations Control operations The PIC18 instruction set summary in Table 26-2 lists byte-oriented, bit-oriented, literal and control operations. Table 26-1 shows the opcode field descriptions. Most byte-oriented instructions have three operands: 1. 2. 3. The file register (specified by `f') The destination of the result (specified by `d') The accessed memory (specified by `a') The file register designator `f' specifies which file register is to be used by the instruction. The destination designator `d' specifies where the result of the operation is to be placed. If `d' is zero, the result is placed in the WREG register. If `d' is one, the result is placed in the file register specified in the instruction. All bit-oriented instructions have three operands: 1. 2. 3. The file register (specified by `f') The bit in the file register (specified by `b') The accessed memory (specified by `a') The literal instructions may use some of the following operands: * A literal value to be loaded into a file register (specified by `k') * The desired FSR register to load the literal value into (specified by `f') * No operand required (specified by `--') The control instructions may use some of the following operands: * A program memory address (specified by `n') * The mode of the CALL or RETURN instructions (specified by `s') * The mode of the table read and table write instructions (specified by `m') * No operand required (specified by `--') All instructions are a single word, except for four double-word instructions. These instructions were made double-word to contain the required information in 32 bits. In the second word, the 4 MSbs are 1's. If this second word is executed as an instruction (by itself), it will execute as a NOP. All single-word instructions are executed in a single instruction cycle, unless a conditional test is true or the program counter is changed as a result of the instruction. In these cases, the execution takes two instruction cycles with the additional instruction cycle(s) executed as a NOP. The double word instructions execute in two instruction cycles. One instruction cycle consists of four oscillator periods. Thus, for an oscillator frequency of 4 MHz, the normal instruction execution time is 1 s. If a conditional test is true, or the program counter is changed as a result of an instruction, the instruction execution time is 2 s. Two-word branch instructions (if true) would take 3 s. Figure 26-1 shows the general formats that the instructions can have. All examples use the convention `nnh' to represent a hexadecimal number. The Instruction Set Summary, shown in Table 26-2, lists the standard instructions recognized by the Microchip MPASMTM Assembler. Section 26.1.1 "Standard Instruction Set" provides a description of each instruction. The bit field designator `b' selects the number of the bit affected by the operation, while the file register designator `f' represents the number of the file in which the bit is located. 2004 Microchip Technology Inc. DS39646B-page 321 PIC18F8722 FAMILY TABLE 26-1: OPCODE FIELD DESCRIPTIONS Field Description a RAM access bit: a = 0: RAM location in Access RAM (BSR register is ignored) a = 1: RAM bank is specified by BSR register bbb Bit address within an 8-bit file register (0 to 7). BSR Bank Select Register. Used to select the current RAM bank. C, DC, Z, OV, N ALU status bits: Carry, Digit Carry, Zero, Overflow, Negative. d Destination select bit: d = 0: store result in WREG d = 1: store result in file register f dest Destination: either the WREG register or the specified register file location. f 8-bit Register file address (00h to FFh), or 2-bit FSR designator (0h to 3h). fs 12-bit Register file address (000h to FFFh). This is the source address. fd 12-bit Register file address (000h to FFFh). This is the destination address. GIE Global Interrupt Enable bit. k Literal field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value). label Label name. mm The mode of the TBLPTR register for the table read and table write instructions. Only used with table read and table write instructions: * No Change to register (such as TBLPTR with table reads and writes) *+ Post-Increment register (such as TBLPTR with table reads and writes) *- Post-Decrement register (such as TBLPTR with table reads and writes) Pre-Increment register (such as TBLPTR with table reads and writes) +* n The relative address (2's complement number) for relative branch instructions or the direct address for Call/Branch and Return instructions. PC Program Counter. PCL Program Counter Low Byte. PCH Program Counter High Byte. PCLATH Program Counter High Byte Latch. PCLATU Program Counter Upper Byte Latch. PD Power-Down bit. PRODH Product of Multiply High Byte. PRODL Product of Multiply Low Byte. s Fast Call/Return mode select bit: s = 0: do not update into/from shadow registers s = 1: certain registers loaded into/from shadow registers (Fast mode) TBLPTR 21-bit Table Pointer (points to a Program Memory location). TABLAT 8-bit Table Latch. TO Time-out bit. TOS Top-of-Stack. u Unused or Unchanged. WDT Watchdog Timer. WREG Working register (accumulator). x Don't care (`0' or `1'). The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. zs 7-bit offset value for indirect addressing of register files (source). 7-bit offset value for indirect addressing of register files (destination). zd { } Optional argument. [text] Indicates an indexed address. (text) The contents of text. [expr]<n> Specifies bit n of the register indicated by the pointer expr. Assigned to. < > Register bit field. In the set of. italics User-defined term (font is Courier). DS39646B-page 322 2004 Microchip Technology Inc. PIC18F8722 FAMILY FIGURE 26-1: GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations 15 10 9 8 7 OPCODE d a Example Instruction 0 f (FILE #) ADDWF MYREG, W, B d = 0 for result destination to be WREG register d = 1 for result destination to be file register (f) a = 0 to force Access Bank a = 1 for BSR to select bank f = 8-bit file register address Byte to Byte move operations (2-word) 15 12 11 OPCODE 15 0 f (Source FILE #) 12 11 MOVFF MYREG1, MYREG2 0 f (Destination FILE #) 1111 f = 12-bit file register address Bit-oriented file register operations 15 12 11 9 8 7 OPCODE b (BIT #) a 0 f (FILE #) BSF MYREG, bit, B b = 3-bit position of bit in file register (f) a = 0 to force Access Bank a = 1 for BSR to select bank f = 8-bit file register address Literal operations 15 8 7 OPCODE 0 k (literal) MOVLW 7Fh k = 8-bit immediate value Control operations CALL, GOTO and Branch operations 15 8 7 OPCODE 15 0 n<7:0> (literal) 12 11 GOTO Label 0 n<19:8> (literal) 1111 n = 20-bit immediate value 15 8 7 OPCODE 15 S 0 CALL MYFUNC n<7:0> (literal) 12 11 0 n<19:8> (literal) 1111 S = Fast bit 15 OPCODE 15 OPCODE 2004 Microchip Technology Inc. 11 10 0 BRA MYFUNC n<10:0> (literal) 8 7 n<7:0> (literal) 0 BC MYFUNC DS39646B-page 323 PIC18F8722 FAMILY TABLE 26-2: PIC18FXXXX INSTRUCTION SET Mnemonic, Operands 16-Bit Instruction Word Description Cycles MSb LSb Status Affected Notes BYTE-ORIENTED OPERATIONS ADDWF ADDWFC ANDWF CLRF COMF CPFSEQ CPFSGT CPFSLT DECF DECFSZ DCFSNZ INCF INCFSZ INFSNZ IORWF MOVF MOVFF f, d, a f, d, a f, d, a f, a f, d, a f, a f, a f, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a fs, fd MOVWF MULWF NEGF RLCF RLNCF RRCF RRNCF SETF SUBFWB f, a f, a f, a f, d, a f, d, a f, d, a f, d, a f, a f, d, a SUBWF SUBWFB f, d, a f, d, a SWAPF TSTFSZ XORWF f, d, a f, a f, d, a Note 1: 2: 3: 4: Add WREG and f Add WREG and Carry bit to f AND WREG with f Clear f Complement f Compare f with WREG, skip = Compare f with WREG, skip > Compare f with WREG, skip < Decrement f Decrement f, Skip if 0 Decrement f, Skip if Not 0 Increment f Increment f, Skip if 0 Increment f, Skip if Not 0 Inclusive OR WREG with f Move f Move fs (source) to 1st word fd (destination) 2nd word Move WREG to f Multiply WREG with f Negate f Rotate Left f through Carry Rotate Left f (No Carry) Rotate Right f through Carry Rotate Right f (No Carry) Set f Subtract f from WREG with borrow Subtract WREG from f Subtract WREG from f with borrow Swap nibbles in f Test f, skip if 0 Exclusive OR WREG with f 1 1 1 1 1 1 (2 or 3) 1 (2 or 3) 1 (2 or 3) 1 1 (2 or 3) 1 (2 or 3) 1 1 (2 or 3) 1 (2 or 3) 1 1 2 C, DC, Z, OV, N C, DC, Z, OV, N Z, N Z Z, N None None None C, DC, Z, OV, N None None C, DC, Z, OV, N None None Z, N Z, N None 1, 2 1, 2 1,2 2 1, 2 4 4 1, 2 1, 2, 3, 4 1, 2, 3, 4 1, 2 1, 2, 3, 4 4 1, 2 1, 2 1 1 1 1 1 1 1 1 1 1 0010 0010 0001 0110 0001 0110 0110 0110 0000 0010 0100 0010 0011 0100 0001 0101 1100 1111 0110 0000 0110 0011 0100 0011 0100 0110 0101 01da 00da 01da 101a 11da 001a 010a 000a 01da 11da 11da 10da 11da 10da 00da 00da ffff ffff 111a 001a 110a 01da 01da 00da 00da 100a 01da ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff 1 1 0101 11da 0101 10da ffff ffff ffff C, DC, Z, OV, N 1, 2 ffff C, DC, Z, OV, N 1 0011 10da 1 (2 or 3) 0110 011a 1 0001 10da ffff ffff ffff ffff None ffff None ffff Z, N None None 1, 2 C, DC, Z, OV, N C, Z, N 1, 2 Z, N C, Z, N Z, N None 1, 2 C, DC, Z, OV, N 4 1, 2 When a Port register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is `1' for a pin configured as input and is driven low by an external device, the data will be written back with a `0'. If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if assigned. If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction. DS39646B-page 324 2004 Microchip Technology Inc. PIC18F8722 FAMILY TABLE 26-2: PIC18FXXXX INSTRUCTION SET (CONTINUED) 16-Bit Instruction Word Mnemonic, Operands Description Cycles MSb LSb Status Affected Notes BIT-ORIENTED OPERATIONS BCF BSF BTFSC BTFSS BTG f, b, a f, b, a f, b, a f, b, a f, b, a Bit Clear f Bit Set f Bit Test f, Skip if Clear Bit Test f, Skip if Set Bit Toggle f 1 1 1 (2 or 3) 1 (2 or 3) 1 1001 1000 1011 1010 0111 bbba bbba bbba bbba bbba ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff None None None None None 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 2 1 (2) 2 0010 0110 0011 0111 0101 0001 0100 0nnn 0000 110s kkkk 0000 0000 1111 kkkk 0000 xxxx 0000 0000 1nnn 0000 0000 nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn kkkk kkkk 0000 0000 kkkk kkkk 0000 xxxx 0000 0000 nnnn 1111 0001 nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn kkkk kkkk 0100 0111 kkkk kkkk 0000 xxxx 0110 0101 nnnn 1111 000s None None None None None None None None None None 1 1 1 1 2 1 2 1110 1110 1110 1110 1110 1110 1110 1101 1110 1110 1111 0000 0000 1110 1111 0000 1111 0000 0000 1101 0000 0000 2 2 1 0000 1100 0000 0000 0000 0000 kkkk 0001 0000 1, 2 1, 2 3, 4 3, 4 1, 2 CONTROL OPERATIONS BC BN BNC BNN BNOV BNZ BOV BRA BZ CALL n n n n n n n n n n, s CLRWDT DAW GOTO -- -- n NOP NOP POP PUSH RCALL RESET RETFIE -- -- -- -- n s Branch if Carry Branch if Negative Branch if Not Carry Branch if Not Negative Branch if Not Overflow Branch if Not Zero Branch if Overflow Branch Unconditionally Branch if Zero Call subroutine 1st word 2nd word Clear Watchdog Timer Decimal Adjust WREG Go to address 1st word 2nd word No Operation No Operation Pop top of return stack (TOS) Push top of return stack (TOS) Relative Call Software device Reset Return from interrupt enable RETLW RETURN SLEEP k s -- Return with literal in WREG Return from Subroutine Go into Standby mode Note 1: 2: 3: 4: 1 1 2 TO, PD C None None None None None None All GIE/GIEH, PEIE/GIEL kkkk None 001s None 0011 TO, PD 4 When a Port register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is `1' for a pin configured as input and is driven low by an external device, the data will be written back with a `0'. If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if assigned. If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction. 2004 Microchip Technology Inc. DS39646B-page 325 PIC18F8722 FAMILY TABLE 26-2: PIC18FXXXX INSTRUCTION SET (CONTINUED) 16-Bit Instruction Word Mnemonic, Operands Description Cycles MSb LSb Status Affected Notes LITERAL OPERATIONS ADDLW ANDLW IORLW LFSR k k k f, k MOVLB MOVLW MULLW RETLW SUBLW XORLW k k k k k k Add literal and WREG AND literal with WREG Inclusive OR literal with WREG Move literal (12-bit) 2nd word to FSR(f) 1st word Move literal to BSR<3:0> Move literal to WREG Multiply literal with WREG Return with literal in WREG Subtract WREG from literal Exclusive OR literal with WREG 1 1 1 2 1 1 1 2 1 1 0000 0000 0000 1110 1111 0000 0000 0000 0000 0000 0000 1111 1011 1001 1110 0000 0001 1110 1101 1100 1000 1010 kkkk kkkk kkkk 00ff kkkk 0000 kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk C, DC, Z, OV, N Z, N Z, N None 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1000 1001 1010 1011 1100 1101 1110 1111 None None None None None None None None None None None None C, DC, Z, OV, N Z, N DATA MEMORY PROGRAM MEMORY OPERATIONS TBLRD* TBLRD*+ TBLRD*TBLRD+* TBLWT* TBLWT*+ TBLWT*TBLWT+* Note 1: 2: 3: 4: Table Read 2 Table Read with post-increment Table Read with post-decrement Table Read with pre-increment Table Write 2 Table Write with post-increment Table Write with post-decrement Table Write with pre-increment 5 5 5 5 When a Port register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is `1' for a pin configured as input and is driven low by an external device, the data will be written back with a `0'. If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if assigned. If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction. DS39646B-page 326 2004 Microchip Technology Inc. PIC18F8722 FAMILY 26.1.1 STANDARD INSTRUCTION SET ADDLW ADD Literal to W ADDWF ADD W to f Syntax: ADDLW Syntax: ADDWF Operands: 0 f 255 d [0,1] a [0,1] Operation: (W) + (f) dest Status Affected: N, OV, C, DC, Z k Operands: 0 k 255 Operation: (W) + k W Status Affected: N, OV, C, DC, Z Encoding: 0000 1111 kkkk kkkk Description: The contents of W are added to the 8-bit literal `k' and the result is placed in W. Words: 1 Cycles: 1 Encoding: 0010 Description: Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal `k' Process Data Write to W Example: ADDLW 01da ffff ffff Add W to register `f'. If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f' (default). If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 26.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 15h Before Instruction W = 10h After Instruction W = 25h f {,d {,a}} Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write to destination Example: ADDWF Before Instruction W = REG = After Instruction W = REG = Note: REG, 0, 0 17h 0C2h 0D9h 0C2h All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in symbolic addressing. If a label is used, the instruction format then becomes: {label} instruction argument(s). 2004 Microchip Technology Inc. DS39646B-page 327 PIC18F8722 FAMILY ADDWFC ADD W and Carry bit to f ANDLW AND Literal with W Syntax: ADDWFC Syntax: ANDLW Operands: 0 f 255 d [0,1] a [0,1] f {,d {,a}} (W) + (f) + (C) dest Operation: Status Affected: Encoding: 0010 Description: 00da ffff ffff Add W, the Carry flag and data memory location `f'. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed in data memory location `f'. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 26.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. Words: 1 Cycles: 1 Operands: 0 k 255 Operation: (W) .AND. k W Status Affected: N, Z Encoding: N,OV, C, DC, Z k 0000 1011 kkkk kkkk Description: The contents of W are ANDed with the 8-bit literal `k'. The result is placed in W. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal `k' Process Data Write to W Example: ANDLW Before Instruction W = After Instruction W = 05Fh A3h 03h Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write to destination Example: ADDWFC Before Instruction Carry bit = REG = W = After Instruction Carry bit = REG = W = DS39646B-page 328 REG, 0, 1 1 02h 4Dh 0 02h 50h 2004 Microchip Technology Inc. PIC18F8722 FAMILY ANDWF AND W with f BC Branch if Carry Syntax: ANDWF Syntax: BC Operands: 0 f 255 d [0,1] a [0,1] f {,d {,a}} Operation: (W) .AND. (f) dest Status Affected: N, Z Encoding: 0001 Description: Operands: -128 n 127 Operation: if Carry bit is `1' (PC) + 2 + 2n PC Status Affected: None Encoding: 01da ffff ffff 1110 Description: The contents of W are ANDed with register `f'. If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f' (default). Words: 1 Cycles: 1 Q Cycle Activity: nnnn nnnn Words: 1 Cycles: 1(2) Q Cycle Activity: If Jump: Q1 Q2 Q3 Q4 Decode Read literal `n' Process Data Write to PC No operation No operation No operation No operation If No Jump: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write to destination Example: 0010 If the Carry bit is '1', then the program will branch. The 2's complement number `2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 26.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. n ANDWF Before Instruction W = REG = After Instruction W = REG = REG, 0, 0 17h C2h 02h C2h 2004 Microchip Technology Inc. Q1 Q2 Q3 Q4 Decode Read literal `n' Process Data No operation Example: HERE Before Instruction PC After Instruction If Carry PC If Carry PC BC 5 = address (HERE) = = = = 1; address (HERE + 12) 0; address (HERE + 2) DS39646B-page 329 PIC18F8722 FAMILY BCF Bit Clear f BN Branch if Negative Syntax: BCF Syntax: BN Operands: 0 f 255 0b7 a [0,1] f, b {,a} Operation: 0 f<b> Status Affected: None Encoding: 1001 Description: Operands: -128 n 127 Operation: if Negative bit is `1' (PC) + 2 + 2n PC Status Affected: None Encoding: bbba ffff ffff 1110 Description: Bit `b' in register `f' is cleared. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 26.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. Words: 1 Cycles: 1 Q1 Q2 Q3 Q4 Read register `f' Process Data Write register `f' Example: BCF Before Instruction FLAG_REG = C7h After Instruction FLAG_REG = 47h DS39646B-page 330 FLAG_REG, 7, 0 0110 nnnn nnnn If the Negative bit is `1', then the program will branch. The 2's complement number `2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. Words: 1 Cycles: 1(2) Q Cycle Activity: If Jump: Q1 Q2 Q3 Q4 Decode Read literal `n' Process Data Write to PC No operation No operation No operation No operation Q Cycle Activity: Decode n If No Jump: Q1 Q2 Q3 Q4 Decode Read literal `n' Process Data No operation Example: HERE Before Instruction PC After Instruction If Negative PC If Negative PC BN Jump = address (HERE) = = = = 1; address (Jump) 0; address (HERE + 2) 2004 Microchip Technology Inc. PIC18F8722 FAMILY BNC Branch if Not Carry BNN Branch if Not Negative Syntax: BNC Syntax: BNN n n Operands: -128 n 127 Operands: -128 n 127 Operation: if Carry bit is `0' (PC) + 2 + 2n PC Operation: if Negative bit is `0' (PC) + 2 + 2n PC Status Affected: None Status Affected: None Encoding: 1110 Description: 0011 nnnn nnnn If the Carry bit is `0', then the program will branch. Encoding: 1110 Description: The 2's complement number `2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. nnnn nnnn The 2's complement number `2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. Words: 1 Words: 1 Cycles: 1(2) Cycles: 1(2) Q Cycle Activity: If Jump: 0111 If the Negative bit is `0', then the program will branch. Q Cycle Activity: If Jump: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read literal `n' Process Data Write to PC Decode Read literal `n' Process Data Write to PC No operation No operation No operation No operation No operation No operation No operation No operation Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read literal `n' Process Data No operation Decode Read literal `n' Process Data No operation If No Jump: Example: If No Jump: HERE Before Instruction PC After Instruction If Carry PC If Carry PC BNC Jump = address (HERE) = = = = 0; address (Jump) 1; address (HERE + 2) 2004 Microchip Technology Inc. Example: HERE Before Instruction PC After Instruction If Negative PC If Negative PC BNN Jump = address (HERE) = = = = 0; address (Jump) 1; address (HERE + 2) DS39646B-page 331 PIC18F8722 FAMILY BNOV Branch if Not Overflow BNZ Branch if Not Zero Syntax: BNOV Syntax: BNZ n n Operands: -128 n 127 Operands: -128 n 127 Operation: if Overflow bit is `0' (PC) + 2 + 2n PC Operation: if Zero bit is `0' (PC) + 2 + 2n PC Status Affected: None Status Affected: None Encoding: 1110 Description: 0101 nnnn nnnn If the Overflow bit is `0', then the program will branch. Encoding: 1110 Description: The 2's complement number `2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. nnnn nnnn The 2's complement number `2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. Words: 1 Words: 1 Cycles: 1(2) Cycles: 1(2) Q Cycle Activity: If Jump: 0001 If the Zero bit is `0', then the program will branch. Q Cycle Activity: If Jump: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read literal `n' Process Data Write to PC Decode Read literal `n' Process Data Write to PC No operation No operation No operation No operation No operation No operation No operation No operation Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read literal `n' Process Data No operation Decode Read literal `n' Process Data No operation If No Jump: If No Jump: Example: HERE Before Instruction PC After Instruction If Overflow PC If Overflow PC DS39646B-page 332 BNOV Jump = address (HERE) = = = = 0; address (Jump) 1; address (HERE + 2) Example: HERE Before Instruction PC After Instruction If Zero PC If Zero PC BNZ Jump = address (HERE) = = = = 0; address (Jump) 1; address (HERE + 2) 2004 Microchip Technology Inc. PIC18F8722 FAMILY BRA Unconditional Branch BSF Bit Set f Syntax: BRA Syntax: BSF Operands: 0 f 255 0b7 a [0,1] Operation: 1 f<b> Status Affected: None n Operands: -1024 n 1023 Operation: (PC) + 2 + 2n PC Status Affected: None Encoding: 1101 Description: 0nnn nnnn nnnn Add the 2's complement number `2n' to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is a two-cycle instruction. Words: 1 Cycles: 2 Encoding: 1000 Description: Q1 Q2 Q3 Q4 Read literal `n' Process Data Write to PC No operation No operation No operation No operation bbba ffff ffff Bit `b' in register `f' is set. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 26.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. Q Cycle Activity: Decode f, b {,a} Words: 1 Cycles: 1 Q Cycle Activity: Example: HERE Before Instruction PC After Instruction PC BRA Jump = address (HERE) = address (Jump) Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write register `f' Example: BSF Before Instruction FLAG_REG After Instruction FLAG_REG 2004 Microchip Technology Inc. FLAG_REG, 7, 1 = 0Ah = 8Ah DS39646B-page 333 PIC18F8722 FAMILY BTFSC Bit Test File, Skip if Clear BTFSS Bit Test File, Skip if Set Syntax: BTFSC f, b {,a} Syntax: BTFSS f, b {,a} Operands: 0 f 255 0b7 a [0,1] Operands: 0 f 255 0b<7 a [0,1] Operation: skip if (f<b>) = 0 Operation: skip if (f<b>) = 1 Status Affected: None Status Affected: None Encoding: 1011 Description: bbba ffff ffff If bit `b' in register `f' is `0', then the next instruction is skipped. If bit `b' is `0', then the next instruction fetched during the current instruction execution is discarded and a NOP is executed instead, making this a two-cycle instruction. Encoding: 1010 Description: bbba ffff ffff If bit `b' in register `f' is `1', then the next instruction is skipped. If bit `b' is `1', then the next instruction fetched during the current instruction execution is discarded and a NOP is executed instead, making this a two-cycle instruction. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 26.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 26.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. Words: 1 Words: 1 Cycles: 1(2) Note: Cycles: 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q Cycle Activity: 3 cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read register `f' Process Data No operation Decode Read register `f' Process Data No operation Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No operation No operation No operation No operation No operation No operation No operation No operation If skip: If skip: If skip and followed by 2-word instruction: If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation Example: HERE FALSE TRUE Before Instruction PC After Instruction If FLAG<1> PC If FLAG<1> PC DS39646B-page 334 BTFSC : : FLAG, 1, 0 = address (HERE) = = = = 0; address (TRUE) 1; address (FALSE) Example: HERE FALSE TRUE Before Instruction PC After Instruction If FLAG<1> PC If FLAG<1> PC BTFSS : : FLAG, 1, 0 = address (HERE) = = = = 0; address (FALSE) 1; address (TRUE) 2004 Microchip Technology Inc. PIC18F8722 FAMILY BTG Bit Toggle f BOV Branch if Overflow Syntax: BTG f, b {,a} Syntax: BOV Operands: 0 f 255 0b<7 a [0,1] Operands: -128 n 127 Operation: if Overflow bit is `1' (PC) + 2 + 2n PC Status Affected: None Operation: (f<b>) f<b> Status Affected: None Encoding: 0111 Description: Encoding: bbba ffff ffff 1110 Description: Bit `b' in data memory location `f' is inverted. Words: Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write register `f' Example: BTG PORTC, 1(2) 2004 Microchip Technology Inc. nnnn Q1 Q2 Q3 Q4 Decode Read literal `n' Process Data Write to PC No operation No operation No operation No operation If No Jump: Q1 Q2 Q3 Q4 Decode Read literal `n' Process Data No operation 4, 0 Before Instruction: PORTC = 0111 0101 [75h] After Instruction: PORTC = 0110 0101 [65h] nnnn Q Cycle Activity: If Jump: 1 Cycles: 0100 If the Overflow bit is `1', then the program will branch. The 2's complement number `2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 26.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. n Example: HERE Before Instruction PC After Instruction If Overflow PC If Overflow PC BOV Jump = address (HERE) = = = = 1; address (Jump) 0; address (HERE + 2) DS39646B-page 335 PIC18F8722 FAMILY BZ Branch if Zero CALL Subroutine Call Syntax: BZ Syntax: CALL k {,s} n Operands: -128 n 127 Operands: Operation: if Zero bit is `1' (PC) + 2 + 2n PC 0 k 1048575 s [0,1] Operation: Status Affected: None (PC) + 4 TOS, k PC<20:1>, if s = 1 (W) WS, (STATUS) STATUSS, (BSR) BSRS Status Affected: None Encoding: 1110 Description: 0000 nnnn nnnn If the Zero bit is `1', then the program will branch. The 2's complement number `2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. Words: 1 Cycles: 1(2) Encoding: 1st word (k<7:0>) 2nd word(k<19:8>) Q1 Q2 Q3 Q4 Read literal `n' Process Data Write to PC No operation No operation No operation No operation Q1 Q2 Q3 Q4 Decode Read literal `n' Process Data No operation If No Jump: Example: HERE Before Instruction PC After Instruction If Zero PC If Zero PC DS39646B-page 336 BZ Jump = address (HERE) = = = = 1; address (Jump) 0; address (HERE + 2) 110s k19kkk k7kkk kkkk kkkk0 kkkk8 Description: Subroutine call of entire 2-Mbyte memory range. First, return address (PC + 4) is pushed onto the return stack. If `s' = 1, the W, STATUS and BSR registers are also pushed into their respective shadow registers, WS, STATUSS and BSRS. If `s' = 0, no update occurs (default). Then, the 20-bit value `k' is loaded into PC<20:1>. CALL is a two-cycle instruction. Words: 2 Cycles: 2 Q Cycle Activity: If Jump: Decode 1110 1111 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal `k'<7:0>, Push PC to stack Read literal 'k'<19:8>, Write to PC No operation No operation No operation No operation Example: HERE Before Instruction PC = After Instruction PC = TOS = WS = BSRS = STATUSS = CALL THERE,1 address (HERE) address (THERE) address (HERE + 4) W BSR STATUS 2004 Microchip Technology Inc. PIC18F8722 FAMILY CLRF Clear f Syntax: CLRF Operands: 0 f 255 a [0,1] f {,a} Operation: 000h f 1Z Status Affected: Z Encoding: 0110 Description: 101a ffff ffff Clears the contents of the specified register. CLRWDT Clear Watchdog Timer Syntax: CLRWDT Operands: None Operation: 000h WDT, 000h WDT postscaler, 1 TO, 1 PD Status Affected: TO, PD Encoding: 0000 Words: 1 Cycles: 1 Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write register `f' Example: CLRF Before Instruction FLAG_REG After Instruction FLAG_REG FLAG_REG,1 = 5Ah = 00h 2004 Microchip Technology Inc. 0100 Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode No operation Process Data No operation Example: Q Cycle Activity: 0000 CLRWDT instruction resets the Watchdog Timer. It also resets the postscaler of the WDT. Status bits, TO and PD, are set. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 26.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 0000 Description: CLRWDT Before Instruction WDT Counter After Instruction WDT Counter WDT Postscaler TO PD = ? = = = = 00h 0 1 1 DS39646B-page 337 PIC18F8722 FAMILY COMF Complement f CPFSEQ Compare f with W, Skip if f = W Syntax: COMF Syntax: CPFSEQ Operands: 0 f 255 a [0,1] Operation: (f) - (W), skip if (f) = (W) (unsigned comparison) Status Affected: None f {,d {,a}} Operands: 0 f 255 d [0,1] a [0,1] Operation: ( f ) dest Status Affected: N, Z Encoding: 0001 Description: 11da ffff ffff The contents of register `f' are complemented. If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f' (default). Encoding: Description: If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 26.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 1 Cycles: 1 Decode Q2 Read register `f' Example: COMF Before Instruction REG = After Instruction REG = W = 13h 13h ECh Q3 Process Data REG, 0, 0 ffff If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 26.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. Q4 Words: 1 Write to destination Cycles: 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Q1 Decode Q2 Read register `f' Q3 Process Data Q4 No operation If skip: Q1 Q2 Q3 No No No operation operation operation If skip and followed by 2-word instruction: Q1 Q2 Q3 No No No operation operation operation No No No operation operation operation Example: HERE NEQUAL EQUAL Before Instruction PC Address W REG After Instruction If REG PC If REG PC DS39646B-page 338 ffff If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). Q Cycle Activity: Q1 001a Compares the contents of data memory location `f' to the contents of W by performing an unsigned subtraction. If `f' = W, then the fetched instruction is discarded and a NOP is executed instead, making this a two-cycle instruction. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). Words: 0110 f {,a} Q4 No operation Q4 No operation No operation CPFSEQ REG, 0 : : = = = HERE ? ? = = = W; Address (EQUAL) W; Address (NEQUAL) 2004 Microchip Technology Inc. PIC18F8722 FAMILY CPFSGT Compare f with W, Skip if f > W CPFSLT Compare f with W, Skip if f < W Syntax: CPFSGT Syntax: CPFSLT Operands: 0 f 255 a [0,1] Operands: Operation: (f) - (W), skip if (f) > (W) (unsigned comparison) 0 f 255 a [0,1] Operation: (f) - (W), skip if (f) < (W) (unsigned comparison) Status Affected: None Status Affected: None Encoding: Description: 0110 f {,a} 010a ffff ffff Compares the contents of data memory location `f' to the contents of the W by performing an unsigned subtraction. Encoding: 0110 Description: If the contents of `f' are greater than the contents of WREG, then the fetched instruction is discarded and a NOP is executed instead, making this a two-cycle instruction. Words: 1 Cycles: 1(2) Note: Q Cycle Activity: Q1 Decode 3 cycles if skip and followed by a 2-word instruction. Q2 Read register `f' Q3 Process Data Q4 No operation Example: HERE NGREATER GREATER Before Instruction PC W After Instruction If REG PC If REG PC Q4 No operation Q4 No operation No operation CPFSGT REG, 0 : : = = Address (HERE) ? > = = W; Address (GREATER) W; Address (NGREATER) 2004 Microchip Technology Inc. ffff ffff Compares the contents of data memory location `f' to the contents of W by performing an unsigned subtraction. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). Words: 1 Cycles: 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data No operation If skip: Q1 Q2 Q3 Q4 No operation No operation No operation No operation If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 No operation No operation No operation No operation No operation No operation No operation No operation If skip: Q1 Q2 Q3 No No No operation operation operation If skip and followed by 2-word instruction: Q1 Q2 Q3 No No No operation operation operation No No No operation operation operation 000a If the contents of `f' are less than the contents of W, then the fetched instruction is discarded and a NOP is executed instead, making this a two-cycle instruction. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 26.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. f {,a} Example: HERE NLESS LESS Before Instruction PC W After Instruction If REG PC If REG PC CPFSLT REG, 1 : : = = Address (HERE) ? < = = W; Address (LESS) W; Address (NLESS) DS39646B-page 339 PIC18F8722 FAMILY DAW Decimal Adjust W Register DECF Decrement f Syntax: DAW Syntax: DECF f {,d {,a}} Operands: None Operands: Operation: If [W<3:0> > 9] or [DC = 1] then (W<3:0>) + 6 W<3:0>; else (W<3:0>) W<3:0> 0 f 255 d [0,1] a [0,1] Operation: (f) - 1 dest Status Affected: C, DC, N, OV, Z Encoding: If [W<7:4> > 9] or [C = 1] then (W<7:4>) + 6 W<7:4>; C = 1; else (W<7:4>) W<7:4> Status Affected: 0000 Description: C Encoding: 0000 Description: 0000 0000 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register W Process Data Write W Example 1: DAW Before Instruction W = C = DC = After Instruction W = C = DC = A5h 0 0 05h 1 0 Example 2: Before Instruction W = C = DC = After Instruction W = C = DC = DS39646B-page 340 ffff ffff Decrement register `f'. If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f' (default). If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). 0111 DAW adjusts the eight-bit value in W, resulting from the earlier addition of two variables (each in packed BCD format) and produces a correct packed BCD result. Words: 01da If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 26.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write to destination Example: DECF Before Instruction CNT = Z = After Instruction CNT = Z = CNT, 1, 0 01h 0 00h 1 CEh 0 0 34h 1 0 2004 Microchip Technology Inc. PIC18F8722 FAMILY DECFSZ Decrement f, Skip if 0 DCFSNZ Decrement f, Skip if not 0 Syntax: DECFSZ f {,d {,a}} Syntax: DCFSNZ Operands: 0 f 255 d [0,1] a [0,1] Operands: 0 f 255 d [0,1] a [0,1] Operation: (f) - 1 dest, skip if result = 0 Operation: (f) - 1 dest, skip if result 0 Status Affected: None Status Affected: None Encoding: 0010 Description: 11da ffff ffff The contents of register `f' are decremented. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f' (default). Encoding: 0100 Description: If the result is `0', the next instruction which is already fetched is discarded and a NOP is executed instead, making it a two-cycle instruction. Cycles: 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q1 Q2 Q3 Q4 Read register `f' Process Data Write to destination Q1 Q2 Q3 Q4 No operation No operation No operation No operation Words: 1 Cycles: 1(2) Note: Q1 Q2 Q3 Q4 No operation No operation No operation No operation No operation No operation No operation No operation DECFSZ GOTO CNT, 1, 1 LOOP Example: HERE CONTINUE Before Instruction PC = After Instruction CNT = If CNT = PC = If CNT PC = Address (HERE) CNT - 1 0; Address (CONTINUE) 0; Address (HERE + 2) 2004 Microchip Technology Inc. 3 cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write to destination If skip: If skip and followed by 2-word instruction: ffff If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 26.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. Q Cycle Activity: Decode ffff If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 26.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 1 11da The contents of register `f' are decremented. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f' (default). If the result is not `0', the next instruction which is already fetched is discarded and a NOP is executed instead, making it a two-cycle instruction. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). Words: f {,d {,a}} If skip: Q1 Q2 Q3 Q4 No operation No operation No operation No operation If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 No operation No operation No operation No operation No operation No operation No operation No operation Example: HERE ZERO NZERO Before Instruction TEMP After Instruction TEMP If TEMP PC If TEMP PC DCFSNZ : : TEMP, 1, 0 = ? = = = = TEMP - 1, 0; Address (ZERO) 0; Address (NZERO) DS39646B-page 341 PIC18F8722 FAMILY GOTO Unconditional Branch INCF Increment f Syntax: GOTO k Syntax: INCF Operands: 0 k 1048575 Operands: Operation: k PC<20:1> Status Affected: None 0 f 255 d [0,1] a [0,1] Operation: (f) + 1 dest Status Affected: C, DC, N, OV, Z Encoding: 1st word (k<7:0>) 2nd word(k<19:8>) 1110 1111 1111 k19kkk k7kkk kkkk kkkk0 kkkk8 Description: GOTO allows an unconditional branch anywhere within entire 2-Mbyte memory range. The 20-bit value `k' is loaded into PC<20:1>. GOTO is always a two-cycle instruction. Words: 2 Cycles: 2 Encoding: 0010 Description: Q1 Q2 Q3 Q4 Read literal `k'<7:0>, No operation Read literal `k'<19:8>, Write to PC No operation No operation No operation No operation Example: ffff ffff The contents of register `f' are incremented. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f' (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 26.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. Words: 1 Cycles: 1 GOTO THERE After Instruction PC = Address (THERE) Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write to destination Example: INCF Before Instruction CNT = Z = C = DC = After Instruction CNT = Z = C = DC = DS39646B-page 342 10da If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). Q Cycle Activity: Decode f {,d {,a}} CNT, 1, 0 FFh 0 ? ? 00h 1 1 1 2004 Microchip Technology Inc. PIC18F8722 FAMILY INCFSZ Increment f, Skip if 0 INFSNZ Syntax: INCFSZ Syntax: INFSNZ 0 f 255 d [0,1] a [0,1] f {,d {,a}} Increment f, Skip if not 0 f {,d {,a}} Operands: 0 f 255 d [0,1] a [0,1] Operands: Operation: (f) + 1 dest, skip if result = 0 Operation: (f) + 1 dest, skip if result 0 Status Affected: None Status Affected: None Encoding: 0011 Description: 11da ffff ffff The contents of register `f' are incremented. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f'. (default) Encoding: 0100 Description: 10da ffff ffff The contents of register `f' are incremented. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f' (default). If the result is `0', the next instruction which is already fetched is discarded and a NOP is executed instead, making it a two-cycle instruction. If the result is not `0', the next instruction which is already fetched is discarded and a NOP is executed instead, making it a two-cycle instruction. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 26.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 26.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. Words: 1 Words: 1 Cycles: 1(2) Note: Cycles: 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. 3 cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Q Cycle Activity: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write to destination Decode Read register `f' Process Data Write to destination Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No operation No operation No operation No operation No operation No operation No operation No operation If skip: If skip: If skip and followed by 2-word instruction: If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation Example: HERE NZERO ZERO Before Instruction PC = After Instruction CNT = If CNT = PC = If CNT PC = INCFSZ : : Address (HERE) CNT + 1 0; Address (ZERO) 0; Address (NZERO) 2004 Microchip Technology Inc. CNT, 1, 0 Example: HERE ZERO NZERO Before Instruction PC = After Instruction REG = If REG PC = If REG = PC = INFSNZ REG, 1, 0 Address (HERE) REG + 1 0; Address (NZERO) 0; Address (ZERO) DS39646B-page 343 PIC18F8722 FAMILY IORLW Inclusive OR Literal with W IORWF Inclusive OR W with f Syntax: IORLW k Syntax: IORWF Operands: 0 k 255 Operands: Operation: (W) .OR. k W Status Affected: N, Z 0 f 255 d [0,1] a [0,1] Operation: (W) .OR. (f) dest Status Affected: N, Z Encoding: 0000 1001 kkkk kkkk Description: The contents of W are ORed with the eight-bit literal `k'. The result is placed in W. Words: 1 Cycles: 1 Encoding: 0001 Description: Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal `k' Process Data Write to W Example: IORLW Before Instruction W = After Instruction W = 00da ffff ffff Inclusive OR W with register `f'. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f' (default). If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 26.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 35h 9Ah BFh f {,d {,a}} Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write to destination Example: IORWF Before Instruction RESULT = W = After Instruction RESULT = W = DS39646B-page 344 RESULT, 0, 1 13h 91h 13h 93h 2004 Microchip Technology Inc. PIC18F8722 FAMILY LFSR Load FSR MOVF Move f Syntax: LFSR f, k Syntax: MOVF Operands: 0f2 0 k 4095 Operands: Operation: k FSRf 0 f 255 d [0,1] a [0,1] Status Affected: None Operation: f dest Status Affected: N, Z Encoding: 1110 1111 1110 0000 00ff k7kkk k11kkk kkkk Description: The 12-bit literal `k' is loaded into the file select register pointed to by `f'. Words: 2 Cycles: 2 Encoding: 0101 Description: Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal `k' MSB Process Data Write literal `k' MSB to FSRfH Decode Read literal `k' LSB Process Data Write literal `k' to FSRfL Example: After Instruction FSR2H FSR2L 03h ABh 00da ffff ffff The contents of register `f' are moved to a destination dependent upon the status of `d'. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f' (default). Location `f' can be anywhere in the 256-byte bank. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 26.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. LFSR 2, 3ABh = = f {,d {,a}} Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write W Example: MOVF Before Instruction REG W After Instruction REG W 2004 Microchip Technology Inc. REG, 0, 0 = = 22h FFh = = 22h 22h DS39646B-page 345 PIC18F8722 FAMILY MOVFF Move f to f MOVLB Move Literal to Low Nibble in BSR Syntax: MOVFF fs,fd Syntax: MOVLW k Operands: 0 fs 4095 0 fd 4095 Operands: 0 k 255 Operation: k BSR Status Affected: None Operation: (fs) fd Status Affected: None Encoding: 1st word (source) 2nd word (destin.) Encoding: 1100 1111 Description: ffff ffff ffff ffff ffffs ffffd The contents of source register `fs' are moved to destination register `fd'. Location of source `fs' can be anywhere in the 4096-byte data space (000h to FFFh) and location of destination `fd' can also be anywhere from 000h to FFFh. The MOVFF instruction cannot use the PCL, TOSU, TOSH or TOSL as the destination register Words: 2 Cycles: 2 (3) 0001 kkkk kkkk Description: The eight-bit literal `k' is loaded into the Bank Select Register (BSR). The value of BSR<7:4> always remains `0' regardless of the value of k7:k4. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal `k' Process Data Write literal `k' to BSR MOVLB 5 Either source or destination can be W (a useful special situation). MOVFF is particularly useful for transferring a data memory location to a peripheral register (such as the transmit buffer or an I/O port). 0000 Example: Before Instruction BSR Register = After Instruction BSR Register = 02h 05h Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' (src) Process Data No operation Decode No operation No operation Write register `f' (dest) No dummy read Example: MOVFF Before Instruction REG1 REG2 After Instruction REG1 REG2 DS39646B-page 346 REG1, REG2 = = 33h 11h = = 33h 33h 2004 Microchip Technology Inc. PIC18F8722 FAMILY MOVLW Move Literal to W MOVWF Move W to f Syntax: MOVLW k Syntax: MOVWF Operands: 0 k 255 Operands: Operation: kW 0 f 255 a [0,1] Status Affected: None Encoding: 0000 Description: 1110 kkkk kkkk The eight-bit literal `k' is loaded into W. Words: 1 Cycles: 1 Operation: (W) f Status Affected: None Encoding: 0110 Description: Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal `k' Process Data Write to W Example: After Instruction W = MOVLW f {,a} 111a ffff ffff Move data from W to register `f'. Location `f' can be anywhere in the 256-byte bank. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 26.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 5Ah 5Ah Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write register `f' Example: MOVWF Before Instruction W = REG = After Instruction W = REG = 2004 Microchip Technology Inc. REG, 0 4Fh FFh 4Fh 4Fh DS39646B-page 347 PIC18F8722 FAMILY MULLW Multiply Literal with W MULWF Syntax: MULLW Syntax: MULWF Operands: 0 k 255 Operands: Operation: (W) x k PRODH:PRODL 0 f 255 a [0,1] Status Affected: None Operation: (W) x (f) PRODH:PRODL Status Affected: None Encoding: 0000 Description: k 1101 kkkk kkkk An unsigned multiplication is carried out between the contents of W and the 8-bit literal `k'. The 16-bit result is placed in PRODH:PRODL register pair. PRODH contains the high byte. Multiply W with f Encoding: 0000 Description: W is unchanged. None of the status flags are affected. 1 Cycles: 1 Q1 Q2 Q3 Q4 Read literal `k' Process Data Write registers PRODH: PRODL MULLW If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 26.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 0C4h = = = E2h ? ? = = = E2h ADh 08h Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write registers PRODH: PRODL Example: Before Instruction W REG PRODH PRODL After Instruction W REG PRODH PRODL DS39646B-page 348 ffff If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). Decode Before Instruction W PRODH PRODL After Instruction W PRODH PRODL ffff Note that neither Overflow nor Carry is possible in this operation. A Zero result is possible but not detected. Q Cycle Activity: Example: 001a An unsigned multiplication is carried out between the contents of W and the register file location `f'. The 16-bit result is stored in the PRODH:PRODL register pair. PRODH contains the high byte. Both W and `f' are unchanged. None of the status flags are affected. Note that neither Overflow nor Carry is possible in this operation. A Zero result is possible but not detected. Words: f {,a} MULWF REG, 1 = = = = C4h B5h ? ? = = = = C4h B5h 8Ah 94h 2004 Microchip Technology Inc. PIC18F8722 FAMILY NEGF Negate f Syntax: NEGF Operands: 0 f 255 a [0,1] f {,a} Operation: (f)+1f Status Affected: N, OV, C, DC, Z Encoding: 0110 Description: 110a ffff If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 26.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 1 1 Syntax: NOP Operands: None Operation: No operation Status Affected: None 0000 1111 ffff If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). Cycles: No Operation Encoding: Location `f' is negated using two's complement. The result is placed in the data memory location `f'. Words: NOP 0000 xxxx Description: No operation. Words: 1 Cycles: 1 0000 xxxx 0000 xxxx Q Cycle Activity: Q1 Q2 Q3 Q4 Decode No operation No operation No operation Example: None. Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write register `f' Example: NEGF Before Instruction REG = After Instruction REG = REG, 1 0011 1010 [3Ah] 1100 0110 [C6h] 2004 Microchip Technology Inc. DS39646B-page 349 PIC18F8722 FAMILY POP Pop Top of Return Stack PUSH Push Top of Return Stack Syntax: POP Syntax: PUSH Operands: None Operands: None Operation: (TOS) bit bucket Operation: (PC + 2) TOS Status Affected: None Status Affected: None Encoding: 0000 0000 0000 0110 Description: The TOS value is pulled off the return stack and is discarded. The TOS value then becomes the previous value that was pushed onto the return stack. This instruction is provided to enable the user to properly manage the return stack to incorporate a software stack. Words: 1 Cycles: 1 Encoding: Q2 Q3 Q4 Decode No operation POP TOS value No operation POP GOTO NEW Before Instruction TOS Stack (1 level down) DS39646B-page 350 0000 0101 The PC + 2 is pushed onto the top of the return stack. The previous TOS value is pushed down on the stack. This instruction allows implementing a software stack by modifying TOS and then pushing it onto the return stack. Words: 1 Cycles: 1 Q Cycle Activity: Q1 After Instruction TOS PC 0000 Description: Q Cycle Activity: Example: 0000 Q1 Q2 Q3 Q4 Decode PUSH PC + 2 onto return stack No operation No operation Example: = = = = 0031A2h 014332h 014332h NEW PUSH Before Instruction TOS PC = = 345Ah 0124h After Instruction PC TOS Stack (1 level down) = = = 0126h 0126h 345Ah 2004 Microchip Technology Inc. PIC18F8722 FAMILY RCALL Relative Call RESET Reset Syntax: RCALL Syntax: RESET n Operands: -1024 n 1023 Operands: None Operation: (PC) + 2 TOS, (PC) + 2 + 2n PC Operation: Reset all registers and flags that are affected by a MCLR Reset. Status Affected: None Status Affected: All Encoding: 1101 Description: 1nnn nnnn nnnn Subroutine call with a jump up to 1K from the current location. First, return address (PC + 2) is pushed onto the stack. Then, add the 2's complement number `2n' to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is a two-cycle instruction. Words: 1 Cycles: 2 Encoding: 0000 Q1 Q2 Q3 Q4 Decode Read literal `n' Process Data Write to PC No operation No operation 1111 1111 This instruction provides a way to execute a MCLR Reset in software. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Start reset No operation No operation Example: Q Cycle Activity: 0000 Description: After Instruction Registers = Flags* = RESET Reset Value Reset Value PUSH PC to stack No operation Example: No operation HERE RCALL Jump Before Instruction PC = Address (HERE) After Instruction PC = Address (Jump) TOS = Address (HERE + 2) 2004 Microchip Technology Inc. DS39646B-page 351 PIC18F8722 FAMILY RETFIE Return from Interrupt RETLW Return Literal to W Syntax: RETFIE {s} Syntax: RETLW k Operands: s [0,1] Operands: 0 k 255 Operation: (TOS) PC, 1 GIE/GIEH or PEIE/GIEL, if s = 1 (WS) W, (STATUSS) STATUS, (BSRS) BSR, PCLATU, PCLATH are unchanged Operation: k W, (TOS) PC, PCLATU, PCLATH are unchanged Status Affected: None Status Affected: 0000 0000 Description: 0000 0001 Words: 1 Cycles: 2 Q Cycle Activity: kkkk kkkk W is loaded with the eight-bit literal `k'. The program counter is loaded from the top of the stack (the return address). The high address latch (PCLATH) remains unchanged. Words: 1 Cycles: 2 000s Return from interrupt. Stack is popped and Top-of-Stack (TOS) is loaded into the PC. Interrupts are enabled by setting either the high or low priority global interrupt enable bit. If `s' = 1, the contents of the shadow registers WS, STATUSS and BSRS are loaded into their corresponding registers W, STATUS and BSR. If `s' = 0, no update of these registers occurs (default). 1100 Description: GIE/GIEH, PEIE/GIEL. Encoding: Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal `k' Process Data POP PC from stack, write to W No operation No operation No operation No operation Example: Q1 Q2 Q3 Q4 Decode No operation No operation POP PC from stack Set GIEH or GIEL No operation Encoding: No operation Example: RETFIE After Interrupt PC W BSR STATUS GIE/GIEH, PEIE/GIEL DS39646B-page 352 No operation No operation 1 = = = = = TOS WS BSRS STATUSS 1 CALL TABLE ; ; ; ; : TABLE ADDWF PCL ; RETLW k0 ; RETLW k1 ; : : RETLW kn ; Before Instruction W = After Instruction W = W contains table offset value W now has table value W = offset Begin table End of table 07h value of kn 2004 Microchip Technology Inc. PIC18F8722 FAMILY RETURN Return from Subroutine RLCF Rotate Left f through Carry Syntax: RETURN {s} Syntax: RLCF Operands: s [0,1] Operands: Operation: (TOS) PC, if s = 1 (WS) W, (STATUSS) STATUS, (BSRS) BSR, PCLATU, PCLATH are unchanged 0 f 255 d [0,1] a [0,1] Operation: (f<n>) dest<n + 1>, (f<7>) C, (C) dest<0> Status Affected: C, N, Z Status Affected: None Encoding: 0000 Description: Encoding: 0000 0001 001s 0011 Description: Return from subroutine. The stack is popped and the top of the stack (TOS) is loaded into the program counter. If `s'= 1, the contents of the shadow registers WS, STATUSS and BSRS are loaded into their corresponding registers W, STATUS and BSR. If `s' = 0, no update of these registers occurs (default). Words: 1 Cycles: 2 Q1 Q2 Q3 Q4 No operation Process Data POP PC from stack No operation No operation No operation No operation 01da ffff ffff The contents of register `f' are rotated one bit to the left through the Carry flag. If `d' is `0', the result is placed in W. If `d' is `1', the result is stored back in register `f' (default). If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 26.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. Q Cycle Activity: Decode f {,d {,a}} register f C Words: 1 Cycles: 1 Q Cycle Activity: Example: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write to destination RETURN After Instruction: PC = TOS Example: Before Instruction REG = C = After Instruction REG = W = C = 2004 Microchip Technology Inc. RLCF REG, 0, 0 1110 0110 0 1110 0110 1100 1100 1 DS39646B-page 353 PIC18F8722 FAMILY RLNCF Rotate Left f (no carry) RRCF Rotate Right f through Carry Syntax: RLNCF Syntax: RRCF Operands: 0 f 255 d [0,1] a [0,1] Operands: 0 f 255 d [0,1] a [0,1] Operation: (f<n>) dest<n + 1>, (f<7>) dest<0> Operation: Status Affected: N, Z (f<n>) dest<n - 1>, (f<0>) C, (C) dest<7> Status Affected: C, N, Z Encoding: 0100 Description: f {,d {,a}} 01da ffff ffff The contents of register `f' are rotated one bit to the left. If `d' is `0', the result is placed in W. If `d' is `1', the result is stored back in register `f' (default). Encoding: 0011 Description: If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). 1 1 Q1 Decode Q2 Read register `f' Example: Before Instruction REG = After Instruction REG = DS39646B-page 354 RLNCF Q3 Process Data Q4 Write to destination Words: 1 Cycles: register f 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write to destination REG, 1, 0 1010 1011 0101 0111 ffff The contents of register `f' are rotated one bit to the right through the Carry flag. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f' (default). C Q Cycle Activity: ffff If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 26.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. register f Cycles: 00da If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 26.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. Words: f {,d {,a}} Example: RRCF Before Instruction REG = C = After Instruction REG = W = C = REG, 0, 0 1110 0110 0 1110 0110 0111 0011 0 2004 Microchip Technology Inc. PIC18F8722 FAMILY RRNCF Rotate Right f (no carry) SETF Set f Syntax: RRNCF Syntax: SETF Operands: 0 f 255 d [0,1] a [0,1] Operands: 0 f 255 a [0,1] Operation: (f<n>) dest<n - 1>, (f<0>) dest<7> Status Affected: N, Z Encoding: 0100 Description: f {,d {,a}} 00da Operation: FFh f Status Affected: None Encoding: ffff ffff 0110 Description: The contents of register `f' are rotated one bit to the right. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f' (default). register f Words: 1 Cycles: 1 Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write to destination Example 1: RRNCF Before Instruction REG = After Instruction REG = Example 2: ffff Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write register `f' SETF Before Instruction REG After Instruction REG REG,1 = 5Ah = FFh REG, 1, 0 1101 0111 1110 1011 RRNCF Before Instruction W = REG = After Instruction W = REG = ffff If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 26.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. Example: Q Cycle Activity: 100a The contents of the specified register are set to FFh. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' is `1', then the bank will be selected as per the BSR value (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 26.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. f {,a} REG, 0, 0 ? 1101 0111 1110 1011 1101 0111 2004 Microchip Technology Inc. DS39646B-page 355 PIC18F8722 FAMILY SLEEP Enter Sleep Mode SUBFWB Subtract f from W with Borrow Syntax: SLEEP Syntax: SUBFWB Operands: None Operands: Operation: 00h WDT, 0 WDT postscaler, 1 TO, 0 PD 0 f 255 d [0,1] a [0,1] Operation: (W) - (f) - (C) dest Status Affected: N, OV, C, DC, Z Status Affected: TO, PD Encoding: 0000 Description: Encoding: 0000 0000 0011 0101 Description: The Power-Down status bit (PD) is cleared. The Time-out status bit (TO) is set. The Watchdog Timer and its postscaler are cleared. The processor is put into Sleep mode with the oscillator stopped. Words: 1 Cycles: 1 Q1 Q2 Q3 Q4 No operation Process Data Go to Sleep Example: SLEEP Before Instruction TO = ? ? PD = After Instruction 1 TO = PD = 0 If WDT causes wake-up, this bit is cleared. DS39646B-page 356 01da ffff ffff Subtract register `f' and Carry flag (borrow) from W (2's complement method). If `d' is `0', the result is stored in W. If `d' is `1', the result is stored in register `f' (default). If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 26.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. Q Cycle Activity: Decode f {,d {,a}} Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write to destination SUBFWB REG, 1, 0 Example 1: Before Instruction REG = 3 W = 2 C = 1 After Instruction REG = FF W = 2 C = 0 Z = 0 N = 1 ; result is negative SUBFWB REG, 0, 0 Example 2: Before Instruction REG = 2 W = 5 C = 1 After Instruction REG = 2 W = 3 C = 1 Z = 0 N = 0 ; result is positive SUBFWB REG, 1, 0 Example 3: Before Instruction REG = 1 W = 2 C = 0 After Instruction REG = 0 W = 2 C = 1 Z = 1 ; result is zero N = 0 2004 Microchip Technology Inc. PIC18F8722 FAMILY SUBLW Subtract W from literal SUBWF Subtract W from f Syntax: SUBLW k Syntax: SUBWF Operands: 0 k 255 Operands: Operation: k - (W) W Status Affected: N, OV, C, DC, Z 0 f 255 d [0,1] a [0,1] Operation: (f) - (W) dest Status Affected: N, OV, C, DC, Z Encoding: 0000 1000 kkkk kkkk Description: W is subtracted from the eight-bit literal `k'. The result is placed in W. Words: 1 Cycles: 1 Encoding: 0101 Description: Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal `k' Process Data Write to W Example 1: Before Instruction W = C = After Instruction W = C = Z = N = Example 2: Before Instruction W = C = After Instruction W = C = Z = N = Example 3: Before Instruction W = C = After Instruction W = C = Z = N = SUBLW SUBLW 11da ffff ffff Subtract W from register `f' (2's complement method). If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f' (default). If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 26.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 02h 01h ? 01h 1 0 0 f {,d {,a}} ; result is positive Words: 1 Cycles: 1 02h Q Cycle Activity: 02h ? 00h 1 1 0 SUBLW ; result is zero 02h 03h ? FFh 0 0 1 ; (2's complement) ; result is negative Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write to destination SUBWF REG, 1, 0 Example 1: Before Instruction REG = W = C = After Instruction REG = W = C = Z = N = Example 2: Before Instruction REG = W = C = After Instruction REG = W = C = Z = N = Example 3: Before Instruction REG = W = C = After Instruction REG = W = C = Z = N = 2004 Microchip Technology Inc. 3 2 ? 1 2 1 0 0 ; result is positive SUBWF REG, 0, 0 2 2 ? 2 0 1 1 0 SUBWF ; result is zero REG, 1, 0 1 2 ? FFh ;(2's complement) 2 0 ; result is negative 0 1 DS39646B-page 357 PIC18F8722 FAMILY SUBWFB Subtract W from f with Borrow SWAPF Swap f Syntax: SUBWFB Syntax: SWAPF f {,d {,a}} Operands: 0 f 255 d [0,1] a [0,1] Operands: Operation: (f) - (W) - (C) dest 0 f 255 d [0,1] a [0,1] Operation: Status Affected: N, OV, C, DC, Z (f<3:0>) dest<7:4>, (f<7:4>) dest<3:0> Status Affected: None Encoding: 0101 Description: f {,d {,a}} 10da ffff ffff Subtract W and the Carry flag (borrow) from register `f' (2's complement method). If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f' (default). Encoding: 0011 Description: If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). 1 Cycles: 1 Q Cycle Activity: Q1 Decode Q2 Read register `f' Example 1: SUBWFB Before Instruction REG = W = C = After Instruction REG = W = C = Z = N = Example 2: Q4 Write to destination If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 26.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write to destination REG, 1, 0 19h 0Dh 1 (0001 1001) (0000 1101) 0Ch 0Dh 1 0 0 (0000 1011) (0000 1101) ffff Example: SWAPF Before Instruction REG = After Instruction REG = REG, 1, 0 53h 35h ; result is positive SUBWFB REG, 0, 0 Before Instruction REG = W = C = After Instruction REG = W = C = Z = N = Example 3: 1Bh 1Ah 0 (0001 1011) (0001 1010) 1Bh 00h 1 1 0 (0001 1011) SUBWFB Before Instruction REG = W = C = After Instruction REG = W C Z N Q3 Process Data ffff If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 26.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. Words: 10da The upper and lower nibbles of register `f' are exchanged. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed in register `f' (default). = = = = DS39646B-page 358 ; result is zero REG, 1, 0 03h 0Eh 1 (0000 0011) (0000 1101) F5h (1111 0100) ; [2's comp] (0000 1101) 0Eh 0 0 1 ; result is negative 2004 Microchip Technology Inc. PIC18F8722 FAMILY TBLRD Table Read TBLRD Table Read (Continued) Syntax: TBLRD ( *; *+; *-; +*) Example 1: TBLRD Operands: None Operation: if TBLRD *, (Prog Mem (TBLPTR)) TABLAT; TBLPTR - No Change if TBLRD *+, (Prog Mem (TBLPTR)) TABLAT; (TBLPTR) + 1 TBLPTR if TBLRD *-, (Prog Mem (TBLPTR)) TABLAT; (TBLPTR) - 1 TBLPTR if TBLRD +*, (TBLPTR) + 1 TBLPTR; (Prog Mem (TBLPTR)) TABLAT Before Instruction TABLAT TBLPTR MEMORY(00A356h) After Instruction TABLAT TBLPTR Example 2: Status Affected: None Encoding: Description: 0000 0000 0000 TBLRD Before Instruction TABLAT TBLPTR MEMORY(01A357h) MEMORY(01A358h) After Instruction TABLAT TBLPTR *+ ; = = = 55h 00A356h 34h = = 34h 00A357h +* ; = = = = AAh 01A357h 12h 34h = = 34h 01A358h 10nn nn=0 * =1 *+ =2 *=3 +* This instruction is used to read the contents of Program Memory (P.M.). To address the program memory, a pointer called Table Pointer (TBLPTR) is used. The TBLPTR (a 21-bit pointer) points to each byte in the program memory. TBLPTR has a 2-Mbyte address range. TBLPTR[0] = 0: Least Significant Byte of Program Memory Word TBLPTR[0] = 1: Most Significant Byte of Program Memory Word The TBLRD instruction can modify the value of TBLPTR as follows: * no change * post-increment * post-decrement * pre-increment Words: 1 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode No operation No operation No operation No operation No operation (Read Program Memory) No operation No operation (Write TABLAT) 2004 Microchip Technology Inc. DS39646B-page 359 PIC18F8722 FAMILY TBLWT Table Write TBLWT Table Write (Continued) Syntax: TBLWT ( *; *+; *-; +*) Example 1: TBLWT Operands: None Operation: if TBLWT*, (TABLAT) Holding Register; TBLPTR - No Change if TBLWT*+, (TABLAT) Holding Register; (TBLPTR) + 1 TBLPTR if TBLWT*-, (TABLAT) Holding Register; (TBLPTR) - 1 TBLPTR if TBLWT+*, (TBLPTR) + 1 TBLPTR; (TABLAT) Holding Register Status Affected: Description: Before Instruction TABLAT = 55h TBLPTR = 00A356h HOLDING REGISTER (00A356h) = FFh After Instructions (table write completion) TABLAT = 55h TBLPTR = 00A357h HOLDING REGISTER (00A356h) = 55h Example 2: None Encoding: 0000 0000 0000 *+; 11nn nn=0 * =1 *+ =2 *=3 +* This instruction uses the 3 LSBs of TBLPTR to determine which of the 8 holding registers the TABLAT is written to. The holding registers are used to program the contents of Program Memory (P.M.). (Refer to Section 5.0 "Memory Organization" for additional details on programming Flash memory.) TBLWT +*; Before Instruction TABLAT = 34h TBLPTR = 01389Ah HOLDING REGISTER (01389Ah) = FFh HOLDING REGISTER (01389Bh) = FFh After Instruction (table write completion) TABLAT = 34h TBLPTR = 01389Bh HOLDING REGISTER (01389Ah) = FFh HOLDING REGISTER (01389Bh) = 34h The TBLPTR (a 21-bit pointer) points to each byte in the program memory. TBLPTR has a 2-Mbyte address range. The LSb of the TBLPTR selects which byte of the program memory location to access. TBLPTR[0] = 0: Least Significant Byte of Program Memory Word TBLPTR[0] = 1: Most Significant Byte of Program Memory Word The TBLWT instruction can modify the value of TBLPTR as follows: * * * * no change post-increment post-decrement pre-increment Words: 1 Cycles: 2 Q Cycle Activity: Q1 Decode Q2 Q3 Q4 No No No operation operation operation No No No No operation operation operation operation (Read (Write to TABLAT) Holding Register) DS39646B-page 360 2004 Microchip Technology Inc. PIC18F8722 FAMILY TSTFSZ Test f, Skip if 0 XORLW Exclusive OR Literal with W Syntax: TSTFSZ f {,a} Syntax: XORLW k Operands: 0 f 255 a [0,1] Operands: 0 k 255 Operation: (W) .XOR. k W Operation: skip if f = 0 Status Affected: N, Z Status Affected: None Encoding: Encoding: 0110 Description: 011a ffff ffff If `f' = 0, the next instruction fetched during the current instruction execution is discarded and a NOP is executed, making this a two-cycle instruction. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 26.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. Words: 1 Cycles: 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. 0000 1010 kkkk kkkk Description: The contents of W are XORed with the 8-bit literal `k'. The result is placed in W. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal `k' Process Data Write to W Example: Before Instruction W = After Instruction W = XORLW 0AFh B5h 1Ah Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data No operation If skip: Q1 Q2 Q3 Q4 No operation No operation No operation No operation If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 No operation No operation No operation No operation No operation No operation No operation No operation Example: HERE NZERO ZERO Before Instruction PC After Instruction If CNT PC If CNT PC TSTFSZ : : CNT, 1 = Address (HERE) = = = 00h, Address (ZERO) 00h, Address (NZERO) 2004 Microchip Technology Inc. DS39646B-page 361 PIC18F8722 FAMILY XORWF Exclusive OR W with f Syntax: XORWF Operands: 0 f 255 d [0,1] a [0,1] Operation: (W) .XOR. (f) dest Status Affected: N, Z Encoding: 0001 Description: f {,d {,a}} 10da ffff ffff Exclusive OR the contents of W with register `f'. If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in the register `f' (default). If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 26.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write to destination Example: XORWF Before Instruction REG = W = After Instruction REG = W = DS39646B-page 362 REG, 1, 0 AFh B5h 1Ah B5h 2004 Microchip Technology Inc. PIC18F8722 FAMILY 26.2 Extended Instruction Set A summary of the instructions in the extended instruction set is provided in Table 26-3. Detailed descriptions are provided in Section 26.2.2 "Extended Instruction Set". The opcode field descriptions in Table 26-1 (page 322) apply to both the standard and extended PIC18 instruction sets. In addition to the standard 75 instructions of the PIC18 instruction set, the PIC18F8722 family of devices also provide an optional extension to the core CPU functionality. The added features include eight additional instructions that augment indirect and indexed addressing operations and the implementation of Indexed Literal Offset Addressing for many of the standard PIC18 instructions. Note: The additional features of the extended instruction set are enabled by default. To enable them, users must set the XINST configuration bit. The instructions in the extended set can all be classified as literal operations, which either manipulate the File Select Registers, or use them for indexed addressing. Two of the instructions, ADDFSR and SUBFSR, each have an additional special instantiation for using FSR2. These versions (ADDULNK and SUBULNK) allow for automatic return after execution. 26.2.1 EXTENDED INSTRUCTION SYNTAX Most of the extended instructions use indexed arguments, using one of the File Select Registers and some offset to specify a source or destination register. When an argument for an instruction serves as part of indexed addressing, it is enclosed in square brackets ("[ ]"). This is done to indicate that the argument is used as an index or offset. The MPASMTM Assembler will flag an error if it determines that an index or offset value is not bracketed. The extended instructions are specifically implemented to optimize re-entrant program code (that is, code that is recursive or that uses a software stack) written in high-level languages, particularly C. Among other things, they allow users working in high-level languages to perform certain operations on data structures more efficiently. These include: When the extended instruction set is enabled, brackets are also used to indicate index arguments in byte-oriented and bit-oriented instructions. This is in addition to other changes in their syntax. For more details, see Section 26.2.3.1 "Extended Instruction Syntax with Standard PIC18 Commands". * dynamic allocation and deallocation of software stack space when entering and leaving subroutines * function pointer invocation * software stack pointer manipulation * manipulation of variables located in a software stack TABLE 26-3: The instruction set extension and the Indexed Literal Offset Addressing mode were designed for optimizing applications written in C; the user may likely never use these instructions directly in assembler. The syntax for these commands is provided as a reference for users who may be reviewing code that has been generated by a compiler. Note: In the past, square brackets have been used to denote optional arguments in the PIC18 and earlier instruction sets. In this text and going forward, optional arguments are denoted by braces ("{ }"). EXTENSIONS TO THE PIC18 INSTRUCTION SET 16-Bit Instruction Word Mnemonic, Operands ADDFSR ADDULNK CALLW MOVSF f, k k MOVSS zs, zd PUSHL k SUBFSR SUBULNK f, k k zs, fd Description Cycles MSb Add literal to FSR Add literal to FSR2 and return Call subroutine using WREG Move zs (source) to 1st word fd (destination) 2nd word Move zs (source) to 1st word zd (destination) 2nd word Store literal at FSR2, decrement FSR2 Subtract literal from FSR Subtract literal from FSR2 and return 2004 Microchip Technology Inc. 1 2 2 2 LSb Status Affected 1000 1000 0000 1011 ffff 1011 xxxx 1010 ffkk 11kk 0001 0zzz ffff 1zzz xzzz kkkk kkkk kkkk 0100 zzzz ffff zzzz zzzz kkkk None None None None 1 1110 1110 0000 1110 1111 1110 1111 1110 1 2 1110 1110 1001 1001 ffkk 11kk kkkk kkkk None None 2 None None DS39646B-page 363 PIC18F8722 FAMILY 26.2.2 EXTENDED INSTRUCTION SET ADDFSR Add Literal to FSR ADDULNK Add Literal to FSR2 and Return Syntax: ADDFSR f, k Syntax: ADDULNK k Operands: 0 k 63 f [ 0, 1, 2 ] Operands: 0 k 63 Operation: FSR(f) + k FSR(f) Status Affected: None Encoding: 1110 FSR2 + k FSR2, Operation: (TOS) PC Status Affected: 1000 ffkk kkkk Description: The 6-bit literal `k' is added to the contents of the FSR specified by `f'. Words: 1 Cycles: 1 None Encoding: 1110 Description: Q2 Q3 Q4 Decode Read literal `k' Process Data Write to FSR Example: ADDFSR Before Instruction FSR2 = After Instruction FSR2 = 03FFh kkkk This may be thought of as a special case of the ADDFSR instruction, where f = 3 (binary `11'); it operates only on FSR2. 2, 23h Words: 1 Cycles: 2 Q Cycle Activity: 0422h Q1 Q2 Q3 Q4 Decode Read literal `k' Process Data Write to FSR No Operation No Operation No Operation No Operation Example: Note: 11kk The instruction takes two cycles to execute; a NOP is performed during the second cycle. Q Cycle Activity: Q1 1000 The 6-bit literal `k' is added to the contents of FSR2. A RETURN is then executed by loading the PC with the TOS. ADDULNK 23h Before Instruction FSR2 = PC = 03FFh 0100h After Instruction FSR2 = PC = 0422h (TOS) All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in symbolic addressing. If a label is used, the instruction format then becomes: {label} instruction argument(s). DS39646B-page 364 2004 Microchip Technology Inc. PIC18F8722 FAMILY CALLW Subroutine Call using WREG MOVSF Move Indexed to f Syntax: CALLW Syntax: MOVSF [zs], fd Operands: None Operands: Operation: (PC + 2) TOS, (W) PCL, (PCLATH) PCH, (PCLATU) PCU 0 zs 127 0 fd 4095 Operation: ((FSR2) + zs) fd Status Affected: None Status Affected: None Encoding: 0000 Description 0000 0001 0100 First, the return address (PC + 2) is pushed onto the return stack. Next, the contents of W are written to PCL; the existing value is discarded. Then, the contents of PCLATH and PCLATU are latched into PCH and PCU, respectively. The second cycle is executed as a NOP instruction while the new next instruction is fetched. Encoding: 1st word (source) 2nd word (destin.) Description: Unlike CALL, there is no option to update W, STATUS or BSR. Words: 1 Cycles: 2 Q1 Q2 Q3 Q4 Read WREG Push PC to stack No operation No operation No operation No operation No operation Before Instruction PC = PCLATH = PCLATU = W = After Instruction PC = TOS = PCLATH = PCLATU = W = Words: 2 Cycles: 2 Q Cycle Activity: CALLW Decode address (HERE) 10h 00h 06h 001006h address (HERE + 2) 10h 00h 06h 2004 Microchip Technology Inc. zzzzs ffffd The contents of the source register are moved to destination register `fd'. The actual address of the source register is determined by adding the 7-bit literal offset `zs', in the first word, to the value of FSR2. The address of the destination register is specified by the 12-bit literal `fd' in the second word. Both addresses can be anywhere in the 4096-byte data space (000h to FFFh). Q1 HERE 0zzz ffff If the resultant source address points to an indirect addressing register, the value returned will be 00h. Decode Example: 1011 ffff The MOVSF instruction cannot use the PCL, TOSU, TOSH or TOSL as the destination register. Q Cycle Activity: Decode 1110 1111 Q2 Q3 Determine Determine source addr source addr No operation No operation No dummy read Example: MOVSF Before Instruction FSR2 Contents of 85h REG2 After Instruction FSR2 Contents of 85h REG2 Q4 Read source reg Write register `f' (dest) [05h], REG2 = 80h = = 33h 11h = 80h = = 33h 33h DS39646B-page 365 PIC18F8722 FAMILY MOVSS Move Indexed to Indexed PUSHL Store Literal at FSR2, Decrement FSR2 Syntax: MOVSS [zs], [zd] Syntax: PUSHL k Operands: 0 zs 127 0 zd 127 Operands: 0 k 255 Operation: k (FSR2), FSR2 - 1 FSR2 Status Affected: None Operation: ((FSR2) + zs) ((FSR2) + zd) Status Affected: None Encoding: 1st word (source) 2nd word (dest.) 1110 1111 Description 1011 xxxx 1zzz xzzz zzzzs zzzzd The contents of the source register are moved to the destination register. The addresses of the source and destination registers are determined by adding the 7-bit literal offsets `zs' or `zd', respectively, to the value of FSR2. Both registers can be located anywhere in the 4096-byte data memory space (000h to FFFh). The MOVSS instruction cannot use the PCL, TOSU, TOSH or TOSL as the destination register. If the resultant source address points to an indirect addressing register, the value returned will be 00h. If the resultant destination address points to an indirect addressing register, the instruction will execute as a NOP. Words: 2 Cycles: 2 Q Cycle Activity: Q1 Decode Decode Q2 Q3 Determine Determine source addr source addr Determine dest addr Example: MOVSS Before Instruction FSR2 Contents of 85h Contents of 86h After Instruction FSR2 Contents of 85h Contents of 86h DS39646B-page 366 Determine dest addr Encoding: 1111 Description: 1010 kkkk kkkk The 8-bit literal `k' is written to the data memory address specified by FSR2. FSR2 is decremented by 1 after the operation. This instruction allows users to push values onto a software stack. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read `k' Process data Write to destination Example: PUSHL 08h Before Instruction FSR2H:FSR2L Memory (01ECh) = = 01ECh 00h After Instruction FSR2H:FSR2L Memory (01ECh) = = 01EBh 08h Q4 Read source reg Write to dest reg [05h], [06h] = 80h = 33h = 11h = 80h = 33h = 33h 2004 Microchip Technology Inc. PIC18F8722 FAMILY SUBFSR Subtract Literal from FSR SUBULNK Syntax: SUBFSR f, k Syntax: SUBULNK k Operands: 0 k 63 Operands: 0 k 63 f [ 0, 1, 2 ] Operation: FSR2 - k FSR2 Operation: FSRf - k FSRf Status Affected: None Encoding: 1110 (TOS) PC Status Affected: 1001 ffkk kkkk Description: The 6-bit literal `k' is subtracted from the contents of the FSR specified by `f'. Words: 1 Cycles: 1 Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write to destination Before Instruction FSR2 = After Instruction FSR2 = SUBFSR 2, 23h None Encoding: 1110 Description: 1001 11kk kkkk The 6-bit literal `k' is subtracted from the contents of the FSR2. A RETURN is then executed by loading the PC with the TOS. The instruction takes two cycles to execute; a NOP is performed during the second cycle. Q Cycle Activity: Example: Subtract Literal from FSR2 and Return This may be thought of as a special case of the SUBFSR instruction, where f = 3 (binary `11'); it operates only on FSR2. Words: 1 Cycles: 2 Q Cycle Activity: 03FFh 03DCh Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write to destination No Operation No Operation No Operation No Operation Example: 2004 Microchip Technology Inc. SUBULNK 23h Before Instruction FSR2 = PC = 03FFh 0100h After Instruction FSR2 = PC = 03DCh (TOS) DS39646B-page 367 PIC18F8722 FAMILY 26.2.3 Note: BYTE-ORIENTED AND BIT-ORIENTED INSTRUCTIONS IN INDEXED LITERAL OFFSET MODE Enabling the PIC18 instruction set extension may cause legacy applications to behave erratically or fail entirely. In addition to eight new commands in the extended set, enabling the extended instruction set also enables Indexed Literal Offset Addressing (Section 5.5.1 "Indexed Addressing with Literal Offset"). This has a significant impact on the way that many commands of the standard PIC18 instruction set are interpreted. When the extended set is disabled, addresses embedded in opcodes are treated as literal memory locations: either as a location in the Access Bank (a = 0) or in a GPR bank designated by the BSR (a = 1). When the extended instruction set is enabled and a = 0, however, a file register argument of 5Fh or less is interpreted as an offset from the pointer value in FSR2 and not as a literal address. For practical purposes, this means that all instructions that use the Access RAM bit as an argument - that is, all byte-oriented and bit-oriented instructions, or almost half of the core PIC18 instructions - may behave differently when the extended instruction set is enabled. When the content of FSR2 is 00h, the boundaries of the Access RAM are essentially remapped to their original values. This may be useful in creating backward-compatible code. If this technique is used, it may be necessary to save the value of FSR2 and restore it when moving back and forth between C and assembly routines in order to preserve the Stack Pointer. Users must also keep in mind the syntax requirements of the extended instruction set (see Section 26.2.3.1 "Extended Instruction Syntax with Standard PIC18 Commands"). Although the Indexed Literal Offset Addressing mode can be very useful for dynamic stack and pointer manipulation, it can also be very annoying if a simple arithmetic operation is carried out on the wrong register. Users who are accustomed to the PIC18 programming must keep in mind that, when the extended instruction set is enabled, register addresses of 5Fh or less are used for Indexed Literal Offset Addressing. Representative examples of typical byte-oriented and bit-oriented instructions in the Indexed Literal Offset Addressing mode are provided on the following page to show how execution is affected. The operand conditions shown in the examples are applicable to all instructions of these types. DS39646B-page 368 26.2.3.1 Extended Instruction Syntax with Standard PIC18 Commands When the extended instruction set is enabled, the file register argument `f' in the standard byte-oriented and bit-oriented commands is replaced with the literal offset value `k'. As already noted, this occurs only when `f' is less than or equal to 5Fh. When an offset value is used, it must be indicated by square brackets ("[ ]"). As with the extended instructions, the use of brackets indicates to the compiler that the value is to be interpreted as an index or an offset. Omitting the brackets, or using a value greater than 5Fh within the brackets, will generate an error in the MPASM Assembler. If the index argument is properly bracketed for Indexed Literal Offset Addressing, the Access RAM argument is never specified; it will automatically be assumed to be `0'. This is in contrast to standard operation (extended instruction set disabled), when `a' is set on the basis of the target address. Declaring the Access RAM bit in this mode will also generate an error in the MPASM Assembler. The destination argument `d' functions as before. In the latest versions of the MPASM Assembler, language support for the extended instruction set must be explicitly invoked. This is done with either the command line option, /y, or the PE directive in the source listing. 26.2.4 CONSIDERATIONS WHEN ENABLING THE EXTENDED INSTRUCTION SET It is important to note that the extensions to the instruction set may not be beneficial to all users. In particular, users who are not writing code that uses a software stack may not benefit from using the extensions to the instruction set. Additionally, the Indexed Literal Offset Addressing mode may create issues with legacy applications written to the PIC18 assembler. This is because instructions in the legacy code may attempt to address registers in the Access Bank below 5Fh. Since these addresses are interpreted as literal offsets to FSR2 when the instruction set extension is enabled, the application may read or write to the wrong data addresses. When porting an application to the PIC18F8722 family, it is very important to consider the type of code. A large, re-entrant application that is written in C and would benefit from efficient compilation will do well when using the instruction set extensions. Legacy applications that heavily use the Access Bank will most likely not benefit from using the extended instruction set. 2004 Microchip Technology Inc. PIC18F8722 FAMILY ADD W to Indexed (Indexed Literal Offset mode) BSF Bit Set Indexed (Indexed Literal Offset mode) Syntax: ADDWF Syntax: BSF [k], b Operands: 0 k 95 d [0,1] Operands: 0 f 95 0b7 Operation: (W) + ((FSR2) + k) dest Operation: 1 ((FSR2) + k)<b> Status Affected: N, OV, C, DC, Z Status Affected: None ADDWF Encoding: [k] {,d} 0010 Description: 01d0 kkkk kkkk The contents of W are added to the contents of the register indicated by FSR2, offset by the value `k'. If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f' (default). Words: Encoding: bbb0 kkkk kkkk Description: Bit `b' of the register indicated by FSR2, offset by the value `k', is set. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write to destination 1 Cycles: 1000 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read `k' Process Data Write to destination Example: ADDWF Before Instruction W OFST FSR2 Contents of 0A2Ch After Instruction W Contents of 0A2Ch [OFST] ,0 = = = 17h 2Ch 0A00h = 20h = 37h = 20h Example: BSF Before Instruction FLAG_OFST FSR2 Contents of 0A0Ah After Instruction Contents of 0A0Ah [FLAG_OFST], 7 = = 0Ah 0A00h = 55h = D5h SETF Set Indexed (Indexed Literal Offset mode) Syntax: SETF [k] Operands: 0 k 95 Operation: FFh ((FSR2) + k) Status Affected: None Encoding: 0110 1000 kkkk kkkk Description: The contents of the register indicated by FSR2, offset by `k', are set to FFh. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read `k' Process Data Write register Example: SETF Before Instruction OFST FSR2 Contents of 0A2Ch After Instruction Contents of 0A2Ch 2004 Microchip Technology Inc. [OFST] = = 2Ch 0A00h = 00h = FFh DS39646B-page 369 PIC18F8722 FAMILY 26.2.5 SPECIAL CONSIDERATIONS WITH MICROCHIP MPLAB(R) IDE TOOLS The latest versions of Microchip's software tools have been designed to fully support the extended instruction set for the PIC18F8722 family. This includes the MPLAB C18 C Compiler, MPASM assembly language and MPLAB Integrated Development Environment (IDE). When selecting a target device for software development, MPLAB IDE will automatically set default configuration bits for that device. The default setting for the XINST configuration is `0', disabling the extended instruction set and Indexed Literal Offset Addressing mode. For proper execution of applications developed to take advantage of the extended instruction set, XINST must be set during programming. DS39646B-page 370 To develop software for the extended instruction set, the user must enable support for the instructions and the Indexed Addressing mode in their language tool(s). Depending on the environment being used, this may be done in several ways: * A menu option or dialog box within the environment that allows the user to configure the language tool and its settings for the project * A command line option * A directive in the source code These options vary between different compilers, assemblers and development environments. Users are encouraged to review the documentation accompanying their development systems for the appropriate information. 2004 Microchip Technology Inc. PIC18F8722 FAMILY 27.0 DEVELOPMENT SUPPORT 27.1 The PICmicro(R) microcontrollers are supported with a full range of hardware and software development tools: * Integrated Development Environment - MPLAB(R) IDE Software * Assemblers/Compilers/Linkers - MPASMTM Assembler - MPLAB C17 and MPLAB C18 C Compilers - MPLINKTM Object Linker/ MPLIBTM Object Librarian - MPLAB C30 C Compiler - MPLAB ASM30 Assembler/Linker/Library * Simulators - MPLAB SIM Software Simulator - MPLAB dsPIC30 Software Simulator * Emulators - MPLAB ICE 2000 In-Circuit Emulator - MPLAB ICE 4000 In-Circuit Emulator * In-Circuit Debugger - MPLAB ICD 2 * Device Programmers - PRO MATE(R) II Universal Device Programmer - PICSTART(R) Plus Development Programmer - MPLAB PM3 Device Programmer * Low-Cost Demonstration Boards - PICDEMTM 1 Demonstration Board - PICDEM.netTM Demonstration Board - PICDEM 2 Plus Demonstration Board - PICDEM 3 Demonstration Board - PICDEM 4 Demonstration Board - PICDEM 17 Demonstration Board - PICDEM 18R Demonstration Board - PICDEM LIN Demonstration Board - PICDEM USB Demonstration Board * Evaluation Kits - KEELOQ(R) Evaluation and Programming Tools - PICDEM MSC - microID(R) Developer Kits - CAN - PowerSmart(R) Developer Kits - Analog MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit microcontroller market. The MPLAB IDE is a Windows(R) based application that contains: * An interface to debugging tools - simulator - programmer (sold separately) - emulator (sold separately) - in-circuit debugger (sold separately) * A full-featured editor with color coded context * A multiple project manager * Customizable data windows with direct edit of contents * High-level source code debugging * Mouse over variable inspection * Extensive on-line help The MPLAB IDE allows you to: * Edit your source files (either assembly or C) * One touch assemble (or compile) and download to PICmicro emulator and simulator tools (automatically updates all project information) * Debug using: - source files (assembly or C) - mixed assembly and C - machine code MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increasing flexibility and power. 27.2 MPASM Assembler The MPASM assembler is a full-featured, universal macro assembler for all PICmicro MCUs. The MPASM assembler generates relocatable object files for the MPLINK object linker, Intel(R) standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging. The MPASM assembler features include: * Integration into MPLAB IDE projects * User defined macros to streamline assembly code * Conditional assembly for multi-purpose source files * Directives that allow complete control over the assembly process 2004 Microchip Technology Inc. Preliminary DS39646B-page 371 PIC18F8722 FAMILY 27.3 MPLAB C17 and MPLAB C18 C Compilers 27.6 The MPLAB C17 and MPLAB C18 Code Development Systems are complete ANSI C compilers for Microchip's PIC17CXXX and PIC18CXXX family of microcontrollers. These compilers provide powerful integration capabilities, superior code optimization and ease of use not found with other compilers. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. 27.4 MPLINK Object Linker/ MPLIB Object Librarian The MPLINK object linker combines relocatable objects created by the MPASM assembler and the MPLAB C17 and MPLAB C18 C compilers. It can link relocatable objects from precompiled libraries, using directives from a linker script. The MPLIB object librarian manages the creation and modification of library files of precompiled code. When a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The object linker/library features include: * Efficient linking of single libraries instead of many smaller files * Enhanced code maintainability by grouping related modules together * Flexible creation of libraries with easy module listing, replacement, deletion and extraction 27.5 MPLAB C30 C Compiler MPLAB C30 is distributed with a complete ANSI C standard library. All library functions have been validated and conform to the ANSI C library standard. The library includes functions for string manipulation, dynamic memory allocation, data conversion, timekeeping and math functions (trigonometric, exponential and hyperbolic). The compiler provides symbolic information for high-level source debugging with the MPLAB IDE. DS39646B-page 372 MPLAB ASM30 assembler produces relocatable machine code from symbolic assembly language for dsPIC30F devices. MPLAB C30 compiler uses the assembler to produce it's object file. The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. Notable features of the assembler include: * * * * * * Support for the entire dsPIC30F instruction set Support for fixed-point and floating-point data Command line interface Rich directive set Flexible macro language MPLAB IDE compatibility 27.7 MPLAB SIM Software Simulator The MPLAB SIM software simulator allows code development in a PC hosted environment by simulating the PICmicro series microcontrollers on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a file, or user defined key press, to any pin. The execution can be performed in Single-Step, Execute Until Break or Trace mode. The MPLAB SIM simulator fully supports symbolic debugging using the MPLAB C17 and MPLAB C18 C Compilers, as well as the MPASM assembler. The software simulator offers the flexibility to develop and debug code outside of the laboratory environment, making it an excellent, economical software development tool. 27.8 The MPLAB C30 C compiler is a full-featured, ANSI compliant, optimizing compiler that translates standard ANSI C programs into dsPIC30F assembly language source. The compiler also supports many command line options and language extensions to take full advantage of the dsPIC30F device hardware capabilities and afford fine control of the compiler code generator. MPLAB ASM30 Assembler, Linker and Librarian MPLAB SIM30 Software Simulator The MPLAB SIM30 software simulator allows code development in a PC hosted environment by simulating the dsPIC30F series microcontrollers on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a file, or user defined key press, to any of the pins. The MPLAB SIM30 simulator fully supports symbolic debugging using the MPLAB C30 C Compiler and MPLAB ASM30 assembler. The simulator runs in either a Command Line mode for automated tasks, or from MPLAB IDE. This high-speed simulator is designed to debug, analyze and optimize time intensive DSP routines. Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY 27.9 MPLAB ICE 2000 High-Performance Universal In-Circuit Emulator 27.11 MPLAB ICD 2 In-Circuit Debugger The MPLAB ICE 2000 universal in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PICmicro microcontrollers. Software control of the MPLAB ICE 2000 in-circuit emulator is advanced by the MPLAB Integrated Development Environment, which allows editing, building, downloading and source debugging from a single environment. The MPLAB ICE 2000 is a full-featured emulator system with enhanced trace, trigger and data monitoring features. Interchangeable processor modules allow the system to be easily reconfigured for emulation of different processors. The universal architecture of the MPLAB ICE in-circuit emulator allows expansion to support new PICmicro microcontrollers. The MPLAB ICE 2000 in-circuit emulator system has been designed as a real-time emulation system with advanced features that are typically found on more expensive development tools. The PC platform and Microsoft(R) Windows 32-bit operating system were chosen to best make these features available in a simple, unified application. 27.10 MPLAB ICE 4000 High-Performance Universal In-Circuit Emulator The MPLAB ICE 4000 universal in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for highend PICmicro microcontrollers. Software control of the MPLAB ICE in-circuit emulator is provided by the MPLAB Integrated Development Environment, which allows editing, building, downloading and source debugging from a single environment. The MPLAB ICD 4000 is a premium emulator system, providing the features of MPLAB ICE 2000, but with increased emulation memory and high-speed performance for dsPIC30F and PIC18XXXX devices. Its advanced emulator features include complex triggering and timing, up to 2 Mb of emulation memory and the ability to view variables in real-time. The MPLAB ICE 4000 in-circuit emulator system has been designed as a real-time emulation system with advanced features that are typically found on more expensive development tools. The PC platform and Microsoft Windows 32-bit operating system were chosen to best make these features available in a simple, unified application. 2004 Microchip Technology Inc. Microchip's In-Circuit Debugger, MPLAB ICD 2, is a powerful, low-cost, run-time development tool, connecting to the host PC via an RS-232 or high-speed USB interface. This tool is based on the Flash PICmicro MCUs and can be used to develop for these and other PICmicro microcontrollers. The MPLAB ICD 2 utilizes the in-circuit debugging capability built into the Flash devices. This feature, along with Microchip's In-Circuit Serial ProgrammingTM (ICSPTM) protocol, offers cost effective in-circuit Flash debugging from the graphical user interface of the MPLAB Integrated Development Environment. This enables a designer to develop and debug source code by setting breakpoints, single-stepping and watching variables, CPU status and peripheral registers. Running at full speed enables testing hardware and applications in real-time. MPLAB ICD 2 also serves as a development programmer for selected PICmicro devices. 27.12 PRO MATE II Universal Device Programmer The PRO MATE II is a universal, CE compliant device programmer with programmable voltage verification at VDDMIN and VDDMAX for maximum reliability. It features an LCD display for instructions and error messages and a modular detachable socket assembly to support various package types. In Stand-Alone mode, the PRO MATE II device programmer can read, verify and program PICmicro devices without a PC connection. It can also set code protection in this mode. 27.13 MPLAB PM3 Device Programmer The MPLAB PM3 is a universal, CE compliant device programmer with programmable voltage verification at VDDMIN and VDDMAX for maximum reliability. It features a large LCD display (128 x 64) for menus and error messages and a modular detachable socket assembly to support various package types. The ICSPTM cable assembly is included as a standard item. In StandAlone mode, the MPLAB PM3 device programmer can read, verify and program PICmicro devices without a PC connection. It can also set code protection in this mode. MPLAB PM3 connects to the host PC via an RS232 or USB cable. MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an SD/MMC card for file storage and secure data applications. Preliminary DS39646B-page 373 PIC18F8722 FAMILY 27.14 PICSTART Plus Development Programmer 27.17 PICDEM 2 Plus Demonstration Board The PICSTART Plus development programmer is an easy-to-use, low-cost, prototype programmer. It connects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus development programmer supports most PICmicro devices up to 40 pins. Larger pin count devices, such as the PIC16C92X and PIC17C76X, may be supported with an adapter socket. The PICSTART Plus development programmer is CE compliant. The PICDEM 2 Plus demonstration board supports many 18, 28 and 40-pin microcontrollers, including PIC16F87X and PIC18FXX2 devices. All the necessary hardware and software is included to run the demonstration programs. The sample microcontrollers provided with the PICDEM 2 demonstration board can be programmed with a PRO MATE II device programmer, PICSTART Plus development programmer, or MPLAB ICD 2 with a Universal Programmer Adapter. The MPLAB ICD 2 and MPLAB ICE in-circuit emulators may also be used with the PICDEM 2 demonstration board to test firmware. A prototype area extends the circuitry for additional application components. Some of the features include an RS-232 interface, a 2 x 16 LCD display, a piezo speaker, an on-board temperature sensor, four LEDs and sample PIC18F452 and PIC16F877 Flash microcontrollers. 27.15 PICDEM 1 PICmicro Demonstration Board The PICDEM 1 demonstration board demonstrates the capabilities of the PIC16C5X (PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X, PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and PIC17C44. All necessary hardware and software is included to run basic demo programs. The sample microcontrollers provided with the PICDEM 1 demonstration board can be programmed with a PRO MATE II device programmer or a PICSTART Plus development programmer. The PICDEM 1 demonstration board can be connected to the MPLAB ICE in-circuit emulator for testing. A prototype area extends the circuitry for additional application components. Features include an RS-232 interface, a potentiometer for simulated analog input, push button switches and eight LEDs. 27.16 PICDEM.net Internet/Ethernet Demonstration Board The PICDEM.net demonstration board is an Internet/ Ethernet demonstration board using the PIC18F452 microcontroller and TCP/IP firmware. The board supports any 40-pin DIP device that conforms to the standard pinout used by the PIC16F877 or PIC18C452. This kit features a user friendly TCP/IP stack, web server with HTML, a 24L256 Serial EEPROM for Xmodem download to web pages into Serial EEPROM, ICSP/MPLAB ICD 2 interface connector, an Ethernet interface, RS-232 interface and a 16 x 2 LCD display. Also included is the book and CD-ROM "TCP/IP Lean, Web Servers for Embedded Systems," by Jeremy Bentham DS39646B-page 374 27.18 PICDEM 3 PIC16C92X Demonstration Board The PICDEM 3 demonstration board supports the PIC16C923 and PIC16C924 in the PLCC package. All the necessary hardware and software is included to run the demonstration programs. 27.19 PICDEM 4 8/14/18-Pin Demonstration Board The PICDEM 4 can be used to demonstrate the capabilities of the 8, 14 and 18-pin PIC16XXXX and PIC18XXXX MCUs, including the PIC16F818/819, PIC16F87/88, PIC16F62XA and the PIC18F1320 family of microcontrollers. PICDEM 4 is intended to showcase the many features of these low pin count parts, including LIN and Motor Control using ECCP. Special provisions are made for low-power operation with the supercapacitor circuit and jumpers allow onboard hardware to be disabled to eliminate current draw in this mode. Included on the demo board are provisions for Crystal, RC or Canned Oscillator modes, a five volt regulator for use with a nine volt wall adapter or battery, DB-9 RS-232 interface, ICD connector for programming via ICSP and development with MPLAB ICD 2, 2 x 16 liquid crystal display, PCB footprints for H-Bridge motor driver, LIN transceiver and EEPROM. Also included are: header for expansion, eight LEDs, four potentiometers, three push buttons and a prototyping area. Included with the kit is a PIC16F627A and a PIC18F1320. Tutorial firmware is included along with the User's Guide. Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY 27.20 PICDEM 17 Demonstration Board The PICDEM 17 demonstration board is an evaluation board that demonstrates the capabilities of several Microchip microcontrollers, including PIC17C752, PIC17C756A, PIC17C762 and PIC17C766. A programmed sample is included. The PRO MATE II device programmer, or the PICSTART Plus development programmer, can be used to reprogram the device for user tailored application development. The PICDEM 17 demonstration board supports program download and execution from external on-board Flash memory. A generous prototype area is available for user hardware expansion. 27.21 PICDEM 18R PIC18C601/801 Demonstration Board The PICDEM 18R demonstration board serves to assist development of the PIC18C601/801 family of Microchip microcontrollers. It provides hardware implementation of both 8-bit Multiplexed/Demultiplexed and 16-bit Memory modes. The board includes 2 Mb external Flash memory and 128 Kb SRAM memory, as well as serial EEPROM, allowing access to the wide range of memory types supported by the PIC18C601/801. 27.22 PICDEM LIN PIC16C43X Demonstration Board The powerful LIN hardware and software kit includes a series of boards and three PICmicro microcontrollers. The small footprint PIC16C432 and PIC16C433 are used as slaves in the LIN communication and feature on-board LIN transceivers. A PIC16F874 Flash microcontroller serves as the master. All three microcontrollers are programmed with firmware to provide LIN bus communication. 27.24 PICDEM USB PIC16C7X5 Demonstration Board The PICDEM USB Demonstration Board shows off the capabilities of the PIC16C745 and PIC16C765 USB microcontrollers. This board provides the basis for future USB products. 27.25 Evaluation and Programming Tools In addition to the PICDEM series of circuits, Microchip has a line of evaluation kits and demonstration software for these products. * KEELOQ evaluation and programming tools for Microchip's HCS Secure Data Products * CAN developers kit for automotive network applications * Analog design boards and filter design software * PowerSmart battery charging evaluation/ calibration kits * IrDA(R) development kit * microID development and rfLabTM development software * SEEVAL(R) designer kit for memory evaluation and endurance calculations * PICDEM MSC demo boards for Switching mode power supply, high-power IR driver, delta sigma ADC and flow rate sensor Check the Microchip web page and the latest Product Selector Guide for the complete list of demonstration and evaluation kits. 27.23 PICkitTM 1 Flash Starter Kit A complete "development system in a box", the PICkitTM Flash Starter Kit includes a convenient multi-section board for programming, evaluation and development of 8/14-pin Flash PIC(R) microcontrollers. Powered via USB, the board operates under a simple Windows GUI. The PICkit 1 Starter Kit includes the User's Guide (on CD ROM), PICkit 1 tutorial software and code for various applications. Also included are MPLAB(R) IDE (Integrated Development Environment) software, software and hardware "Tips 'n Tricks for 8-pin Flash PIC(R) Microcontrollers" Handbook and a USB interface cable. Supports all current 8/14-pin Flash PIC microcontrollers, as well as many future planned devices. 2004 Microchip Technology Inc. Preliminary DS39646B-page 375 PIC18F8722 FAMILY NOTES: DS39646B-page 376 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY 28.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings() Ambient temperature under bias.............................................................................................................-40C to +125C Storage temperature .............................................................................................................................. -65C to +150C Voltage on any pin with respect to VSS (except VDD and MCLR) ................................................... -0.3V to (VDD + 0.3V) Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +7.5V Voltage on MCLR with respect to VSS (Note 2) ......................................................................................... 0V to +13.25V Total power dissipation (Note 1) ...............................................................................................................................1.0W Maximum current out of VSS pin ...........................................................................................................................300 mA Maximum current into VDD pin ..............................................................................................................................250 mA Input clamp current, IIK (VI < 0 or VI > VDD)...................................................................................................................... 20 mA Output clamp current, IOK (VO < 0 or VO > VDD) .............................................................................................................. 20 mA Maximum output current sunk by any I/O pin..........................................................................................................25 mA Maximum output current sourced by any I/O pin ....................................................................................................25 mA Maximum current sunk by all ports .......................................................................................................................200 mA Maximum current sourced by all ports ..................................................................................................................200 mA Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - IOH} + {(VDD - VOH) x IOH} + (VOL x IOL) 2: Voltage spikes below VSS at the RG5/MCLR/VPP pin, inducing currents greater than 80 mA, may cause latch-up. Thus, a series resistor of 50-100 should be used when applying a "low" level to the RG5/MCLR/ VPP pin, rather than pulling this pin directly to VSS. NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2004 Microchip Technology Inc. Preliminary DS39646B-page 377 PIC18F8722 FAMILY FIGURE 28-1: PIC18F8722 DEVICE FAMILY VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) 6.0V 5.5V Voltage 5.0V 4.5V PIC18F6627/6622/6627/6722 PIC18F8527/8622/8627/8722 4.2V 4.0V 3.5V 3.0V 2.5V 2.0V FMAX Frequency FMAX = 20 MHz in 8-bit External Memory mode. FMAX = 40 MHz in all other modes. PIC18F8722 DEVICE FAMILY VOLTAGE-FREQUENCY GRAPH (EXTENDED) FIGURE 28-2: 6.0V 5.5V Voltage 5.0V 4.5V PIC18F6627/6622/6627/6722 PIC18F8527/8622/8627/8722 4.2V 4.0V 3.5V 3.0V 2.5V 2.0V FMAX Frequency FMAX = 20 MHz in 8-bit External Memory mode. FMAX = 25 MHz in all other modes. DS39646B-page 378 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY FIGURE 28-3: PIC18LF8722 DEVICE FAMILY VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) 6.0V 5.5V PIC18LF6627/6622/6627/6722 PIC18LF8527/8622/8627/8722 Voltage 5.0V 4.5V 4.2V 4.0V 3.5V 3.0V 2.5V 2.0V FMAX 4 MHz Frequency In 8-bit External Memory mode: FMAX = (9.55 MHz/V) (VDDAPPMIN - 2.0V) + 4 MHz, if VDDAPPMIN 4.2V; FMAX = 25 MHz, if VDDAPPMIN > 4.2V. In all other modes: FMAX = (16.36 MHz/V) (VDDAPPMIN - 2.0V) + 4 MHz; FMAX = 40 MHz, if VDDAPPMIN > 4.2V. Note: VDDAPPMIN is the minimum voltage of the PICmicro(R) device in the application. 2004 Microchip Technology Inc. Preliminary DS39646B-page 379 PIC18F8722 FAMILY 28.1 DC Characteristics: Supply Voltage PIC18F6X27/6X22/8X27/8X22 (Industrial, Extended) PIC18LF6X27/6X22/8X27/8X22 (Industrial) PIC18LF6X27/6X22/8X27/8X22 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial PIC18F6X27/6X22/8X27/8X22 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Param No. D001 Symbol VDD Characteristic Min Typ Max Units Conditions Supply Voltage PIC18LF6X27/6X22/8X27/8X22 2.0 -- 5.5 V PIC18F6X27/6X22/8X27/8X22 4.2 -- 5.5 V D002 VDR RAM Data Retention Voltage(1) 1.5 -- -- V D003 VPOR VDD Start Voltage to ensure internal Power-on Reset signal -- -- 0.7 V D004 SVDD VDD Rise Rate to ensure internal Power-on Reset signal 0.05 -- -- D005 VBOR Brown-out Reset Voltage BORV1:BORV0 = 11 2.00 2.05 2.16 V PIC18LF6627/6722/8627/8722 BORV1:BORV0 = 11 2.00 2.11 2.22 V PIC18LF6527/6622/8527/8622 BORV1:BORV0 = 10 2.65 2.79 2.93 V PIC18LF6X27/6X22/8X27/8X22 BORV1:BORV0 = 01 4.11 4.33 4.55 V All devices BORV1:BORV0 = 00 4.36 4.59 4.82 V All devices Legend: Note 1: See Section 4.3 "Power-on Reset (POR)" for details V/ms See Section 4.3 "Power-on Reset (POR)" for details Shading of rows is to assist in readability of the table. This is the limit to which VDD can be lowered in Sleep mode, or during a device Reset, without losing RAM data. DS39646B-page 380 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY 28.2 DC Characteristics: Power-Down and Supply Current PIC18F6X27/6X22/8X27/8X22 (Industrial, Extended) PIC18LF6X27/6X22/8X27/8X22 (Industrial) PIC18LF6X27/6X22/8X27/8X22 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial PIC18F6X27/6X22/8X27/8X22 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Param No. Device Typ Max Units Conditions Power-Down Current (IPD)(1) PIC18LF6X27/6X22/8X27/8X22 PIC18LF6X27/6X22/8X27/8X22 All devices Extended devices only Legend: Note 1: 2: 3: 4: 0.12 1.2 A -40C 0.12 1.2 A +25C 0.24 6.0 A +85C 0.12 1.7 A -40C 0.12 2.4 A +25C 0.36 9.6 A +85C 0.12 2.4 A -40C 0.12 2.5 A +25C 0.48 18.0 A +85C 12 150 A +125C VDD = 2.0V, (Sleep mode) VDD = 3.0V, (Sleep mode) VDD = 5.0V, (Sleep mode) Shading of rows is to assist in readability of the table. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD OR VSS; MCLR = VDD; WDT enabled/disabled as specified. Low-power Timer1 oscillator selected. BOR and HLVD enable internal band gap reference. With both modules enabled, current consumption will be less than the sum of both specifications. 2004 Microchip Technology Inc. Preliminary DS39646B-page 381 PIC18F8722 FAMILY 28.2 DC Characteristics: Power-Down and Supply Current PIC18F6X27/6X22/8X27/8X22 (Industrial, Extended) PIC18LF6X27/6X22/8X27/8X22 (Industrial) (Continued) PIC18LF6X27/6X22/8X27/8X22 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial PIC18F6X27/6X22/8X27/8X22 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Param No. Device Typ Max Units Conditions Supply Current (IDD)(2) PIC18LF6X27/6X22/8X27/8X22 PIC18LF6X27/6X22/8X27/8X22 All devices Extended devices only PIC18LF6X27/6X22/8X27/8X22 PIC18LF6X27/6X22/8X27/8X22 All devices Extended devices only Legend: Note 1: 2: 3: 4: 18 39 A -40C 18 36 A +25C 18 42 A +85C 48 75 A -40C 42 72 A +25C 36 69 A +85C 126 202 A -40C 108 192 A +25C 96 182 A +85C 96 300 A +125C 0.38 1.2 mA -40C 0.38 1.2 mA +25C 0.38 1.2 mA +85C 0.72 1.6 mA -40C 0.7 1.5 mA +25C +85C 0.72 1.4 mA 1.3 2.8 mA -40C 1.3 2.8 mA +25C 1.2 2.7 mA +85C 1.2 4.0 mA +125C VDD = 2.0V VDD = 3.0V FOSC = 31 kHz (RC_RUN mode, Internal oscillator source) VDD = 5.0V VDD = 2.0V VDD = 3.0V FOSC = 1 MHz (RC_RUN mode, Internal oscillator source) VDD = 5.0V Shading of rows is to assist in readability of the table. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD OR VSS; MCLR = VDD; WDT enabled/disabled as specified. Low-power Timer1 oscillator selected. BOR and HLVD enable internal band gap reference. With both modules enabled, current consumption will be less than the sum of both specifications. DS39646B-page 382 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY 28.2 DC Characteristics: Power-Down and Supply Current PIC18F6X27/6X22/8X27/8X22 (Industrial, Extended) PIC18LF6X27/6X22/8X27/8X22 (Industrial) (Continued) PIC18LF6X27/6X22/8X27/8X22 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial PIC18F6X27/6X22/8X27/8X22 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Param No. Device Typ Max Units 1.0 2.5 mA Conditions Supply Current (IDD)(2) PIC18LF6X27/6X22/8X27/8X22 PIC18LF6X27/6X22/8X27/8X22 All devices mA +25C 2.3 mA +85C 1.6 3.6 mA -40C 1.6 3.6 mA +25C +85C 1.6 3.6 mA 3.0 6.3 mA -40C 3.0 6.0 mA +25C 3.0 5.8 mA +85C +125C 3.0 12 mA 3.5 9.6 A -40C 3.7 9.6 A +25C 4.3 32 A +85C Extended devices only 3: 4: 2.4 1.0 Extended devices only All devices 2: 1.0 PIC18LF6X27/6X22/8X27/8X22 PIC18LF6X27/6X22/8X27/8X22 Legend: Note 1: -40C 5.4 13 A -40C 5.7 13 A +25C 7.0 38 A +85C 11 19 A -40C 11.8 19 A +25C 13.5 43 A +85C 25 216 A +125C VDD = 2.0V VDD = 3.0V FOSC = 4 MHz (RC_RUN mode, Internal oscillator source) VDD = 5.0V VDD = 2.0V VDD = 3.0V FOSC = 31 kHz (RC_IDLE mode, Internal oscillator source) VDD = 5.0V Shading of rows is to assist in readability of the table. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD OR VSS; MCLR = VDD; WDT enabled/disabled as specified. Low-power Timer1 oscillator selected. BOR and HLVD enable internal band gap reference. With both modules enabled, current consumption will be less than the sum of both specifications. 2004 Microchip Technology Inc. Preliminary DS39646B-page 383 PIC18F8722 FAMILY 28.2 DC Characteristics: Power-Down and Supply Current PIC18F6X27/6X22/8X27/8X22 (Industrial, Extended) PIC18LF6X27/6X22/8X27/8X22 (Industrial) (Continued) PIC18LF6X27/6X22/8X27/8X22 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial PIC18F6X27/6X22/8X27/8X22 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Param No. Device Typ Max Units Conditions 200 420 A -40C 210 420 A +25C 228 420 A +85C Supply Current (IDD)(2) PIC18LF6X27/6X22/8X27/8X22 PIC18LF6X27/6X22/8X27/8X22 All devices -40C +25C 350 600 A +85C 0.6 1.2 mA -40C 0.62 1.2 mA +25C 0.67 1.2 mA +85C +125C 0.72 3.5 mA 410 600 A -40C 420 600 A +25C 430 600 A +85C Extended devices only 3: 4: A A Extended devices only All devices 2: 600 600 PIC18LF6X27/6X22/8X27/8X22 PIC18LF6X27/6X22/8X27/8X22 Legend: Note 1: 300 324 0.63 1.1 mA -40C 0.65 1.1 mA +25C 0.69 1.1 mA +85C 1.2 1.9 mA -40C 1.3 1.8 mA +25C 1.2 1.7 mA +85C 1.2 6.0 mA +125C VDD = 2.0V VDD = 3.0V FOSC = 1 MHz (RC_IDLE mode, Internal oscillator source) VDD = 5.0V VDD = 2.0V VDD = 3.0V FOSC = 4 MHz (RC_IDLE mode, Internal oscillator source) VDD = 5.0V Shading of rows is to assist in readability of the table. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD OR VSS; MCLR = VDD; WDT enabled/disabled as specified. Low-power Timer1 oscillator selected. BOR and HLVD enable internal band gap reference. With both modules enabled, current consumption will be less than the sum of both specifications. DS39646B-page 384 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY 28.2 DC Characteristics: Power-Down and Supply Current PIC18F6X27/6X22/8X27/8X22 (Industrial, Extended) PIC18LF6X27/6X22/8X27/8X22 (Industrial) (Continued) PIC18LF6X27/6X22/8X27/8X22 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial PIC18F6X27/6X22/8X27/8X22 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Param No. Device Typ Max Units Conditions 300 600 A -40C 310 600 A +25C 300 600 A +85C Supply Current (IDD)(2) PIC18LF6X27/6X22/8X27/8X22 PIC18LF6X27/6X22/8X27/8X22 All devices -40C +25C 550 780 A +85C 1.5 1.9 mA -40C 1.4 1.8 mA +25C 1.3 1.7 mA +85C +125C 1.3 4.2 mA 0.86 2.4 mA -40C 0.88 2.4 mA +25C 0.88 2.4 mA +85C 1.6 3.6 mA -40C 1.6 3.6 mA +25C Extended devices only 3: 4: A A Extended devices only All devices 2: 855 780 PIC18LF6X27/6X22/8X27/8X22 PIC18LF6X27/6X22/8X27/8X22 Legend: Note 1: 660 580 1.6 3.6 mA +85C 3.2 7.2 mA -40C 3.1 7.2 mA +25C 3.0 7.2 mA +85C 3.1 8.4 mA +125C VDD = 2.0V VDD = 3.0V FOSC = 1 MHZ (PRI_RUN mode, EC oscillator) VDD = 5.0V VDD = 2.0V VDD = 3.0V FOSC = 4 MHz (PRI_RUN mode, EC oscillator) VDD = 5.0V Shading of rows is to assist in readability of the table. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD OR VSS; MCLR = VDD; WDT enabled/disabled as specified. Low-power Timer1 oscillator selected. BOR and HLVD enable internal band gap reference. With both modules enabled, current consumption will be less than the sum of both specifications. 2004 Microchip Technology Inc. Preliminary DS39646B-page 385 PIC18F8722 FAMILY 28.2 DC Characteristics: Power-Down and Supply Current PIC18F6X27/6X22/8X27/8X22 (Industrial, Extended) PIC18LF6X27/6X22/8X27/8X22 (Industrial) (Continued) PIC18LF6X27/6X22/8X27/8X22 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial PIC18F6X27/6X22/8X27/8X22 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Param No. Device Typ Max Units Conditions 10 25 mA +125C VDD = 4.2V 13 33 mA +125C VDD = 5.0V 18 42 mA -40C 19 42 mA +25C 19 42 mA +85C 25 48 mA -40C Supply Current (IDD)(2) Extended devices only All devices All devices Legend: Note 1: 2: 3: 4: 25 48 mA +25C 25 48 mA +85C FOSC = 25 MHz (PRI_RUN mode, EC oscillator) VDD = 4.2V FOSC = 40 MHZ (PRI_RUN mode, EC oscillator) VDD = 5.0V Shading of rows is to assist in readability of the table. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD OR VSS; MCLR = VDD; WDT enabled/disabled as specified. Low-power Timer1 oscillator selected. BOR and HLVD enable internal band gap reference. With both modules enabled, current consumption will be less than the sum of both specifications. DS39646B-page 386 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY 28.2 DC Characteristics: Power-Down and Supply Current PIC18F6X27/6X22/8X27/8X22 (Industrial, Extended) PIC18LF6X27/6X22/8X27/8X22 (Industrial) (Continued) PIC18LF6X27/6X22/8X27/8X22 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial PIC18F6X27/6X22/8X27/8X22 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Param No. Device Typ Max Units Conditions Supply Current (IDD)(2) All devices 2: 3: 4: 19 mA -40C 18 mA +25C 9.0 17 mA +85C Extended devices only 9.6 30 mA +125C All devices 12 25 mA -40C 12 24 mA +25C 12 23 mA +85C Extended devices only 12 42 mA +125C All devices 20 42 mA -40C 20 42 mA +25C +85C All devices Legend: Note 1: 9.0 9.0 20 42 mA 28 48 mA -40C 28 48 mA +25C 28 48 mA +85C VDD = 4.2V FOSC = 4 MHZ. 16 MHz internal (PRI_RUN HS+PLL) VDD = 5.0V FOSC = 4 MHZ, 16 MHz internal (PRI_RUN HS+PLL) VDD = 4.2V FOSC = 10 MHZ, 40 MHz internal (PRI_RUN HS+PLL) VDD = 5.0V FOSC = 10 MHZ, 40 MHz internal (PRI_RUN HS+PLL) Shading of rows is to assist in readability of the table. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD OR VSS; MCLR = VDD; WDT enabled/disabled as specified. Low-power Timer1 oscillator selected. BOR and HLVD enable internal band gap reference. With both modules enabled, current consumption will be less than the sum of both specifications. 2004 Microchip Technology Inc. Preliminary DS39646B-page 387 PIC18F8722 FAMILY 28.2 DC Characteristics: Power-Down and Supply Current PIC18F6X27/6X22/8X27/8X22 (Industrial, Extended) PIC18LF6X27/6X22/8X27/8X22 (Industrial) (Continued) PIC18LF6X27/6X22/8X27/8X22 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial PIC18F6X27/6X22/8X27/8X22 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Param No. Device Typ Max Units 78 215 A Conditions Supply Current (IDD)(2) PIC18LF6X27/6X22/8X27/8X22 PIC18LF6X27/6X22/8X27/8X22 All devices A +25C A +85C 144 325 A -40C 144 300 A +25C 144 288 A +85C 360 575 A -40C 290 540 A +25C 360 515 A +85C +125C 0.38 1.1 mA 312 570 A -40C 305 540 A +25C 324 515 A +85C 0.5 1.1 mA -40C 0.6 1.0 mA +25C Extended devices only 3: 4: 210 205 Extended devices only All devices 2: 78 84 PIC18LF6X27/6X22/8X27/8X22 PIC18LF6X27/6X22/8X27/8X22 Legend: Note 1: -40C 0.6 0.9 mA +85C 1.1 1.8 mA -40C 1.1 1.7 mA +25C 1.1 1.6 mA +85C 1.2 3.1 mA +125C VDD = 2.0V VDD = 3.0V FOSC = 1 MHz (PRI_IDLE mode, EC oscillator) VDD = 5.0V VDD = 2.0V VDD = 3.0V FOSC = 4 MHz (PRI_IDLE mode, EC oscillator) VDD = 5.0V Shading of rows is to assist in readability of the table. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD OR VSS; MCLR = VDD; WDT enabled/disabled as specified. Low-power Timer1 oscillator selected. BOR and HLVD enable internal band gap reference. With both modules enabled, current consumption will be less than the sum of both specifications. DS39646B-page 388 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY 28.2 DC Characteristics: Power-Down and Supply Current PIC18F6X27/6X22/8X27/8X22 (Industrial, Extended) PIC18LF6X27/6X22/8X27/8X22 (Industrial) (Continued) PIC18LF6X27/6X22/8X27/8X22 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial PIC18F6X27/6X22/8X27/8X22 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Param No. Device Typ Max Units Conditions Supply Current (IDD)(2) Extended devices only All devices All devices Legend: Note 1: 2: 3: 4: 3.4 8.4 mA +125C VDD = 4.2V 5.2 13 mA +125C VDD = 5.0V 7.2 19 mA -40C 7.4 19 mA +25C 7.8 19 mA +85C 9.7 21 mA -40C 11 21 mA +25C 10 21 mA +85C FOSC = 25 MHz (PRI_IDLE mode, EC oscillator) VDD = 4.2 V FOSC = 40 MHz (PRI_IDLE mode, EC oscillator) VDD = 5.0V Shading of rows is to assist in readability of the table. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD OR VSS; MCLR = VDD; WDT enabled/disabled as specified. Low-power Timer1 oscillator selected. BOR and HLVD enable internal band gap reference. With both modules enabled, current consumption will be less than the sum of both specifications. 2004 Microchip Technology Inc. Preliminary DS39646B-page 389 PIC18F8722 FAMILY 28.2 DC Characteristics: Power-Down and Supply Current PIC18F6X27/6X22/8X27/8X22 (Industrial, Extended) PIC18LF6X27/6X22/8X27/8X22 (Industrial) (Continued) PIC18LF6X27/6X22/8X27/8X22 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial PIC18F6X27/6X22/8X27/8X22 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Param No. Device Typ Max Units 17 48 A Conditions Supply Current (IDD)(2) PIC18LF6X27/6X22/8X27/8X22 PIC18LF6X27/6X22/8X27/8X22 All devices PIC18LF6X27/6X22/8X27/8X22 PIC18LF6X27/6X22/8X27/8X22 All devices Legend: Note 1: 2: 3: 4: -40C 18 48 A +25C 19 48 A +70C 48 89 A -40C 42 84 A +25C +70C 37 80 A 120 180 A -40C 97 180 A +25C 90 180 A +70C 3.0 14 A -40C 4.4 14 A +25C 5.4 14 A +70C 6.0 18 A -40C 6.5 18 A +25C 7.6 18 A +70C 10.0 30 A -40C 10.5 30 A +25C 11.0 43 A +70C VDD = 2.0V VDD = 3.0V FOSC = 32 kHz(3) (SEC_RUN mode, Timer1 as clock) VDD = 5.0V VDD = 2.0V VDD = 3.0V FOSC = 32 kHz(3) (SEC_IDLE mode, Timer1 as clock) VDD = 5.0V Shading of rows is to assist in readability of the table. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD OR VSS; MCLR = VDD; WDT enabled/disabled as specified. Low-power Timer1 oscillator selected. BOR and HLVD enable internal band gap reference. With both modules enabled, current consumption will be less than the sum of both specifications. DS39646B-page 390 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY 28.2 DC Characteristics: Power-Down and Supply Current PIC18F6X27/6X22/8X27/8X22 (Industrial, Extended) PIC18LF6X27/6X22/8X27/8X22 (Industrial) (Continued) PIC18LF6X27/6X22/8X27/8X22 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial PIC18F6X27/6X22/8X27/8X22 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Param No. D022 (IWDT) D022A (IBOR) Device D025 (IOSCB) Legend: Note 1: 2: 3: 4: Max Units Conditions Module Differential Currents (IWDT, IBOR, ILVD, IOSCB, IAD) Watchdog Timer 1.5 5.7 A -40C Brown-out Reset(4) High/Low-Voltage Detect(4) D022B (ILVD) Typ Timer1 Oscillator 1.6 2.4 2.3 2.4 6.3 6.3 6.6 7.2 A A A A +25C +85C -40C +25C 3.4 4.8 6.0 6.1 10 4.2 48 7.2 12 12 12 16 48 54 A A A A A A A +85C -40C +25C +85C +125C -40C to +85C -40C to +85C 66 0 0 2.7 30 35 54 2.4 6.0 47 48 54 A A A A A A -40C to +125C -40C to +85C -40C to +125C -40C to +85C -40C to +85C -40C to +85C 36 2.5 54 8.1 A A -40C to +125C -40C 2.2 2.5 2.6 8.7 8.7 9.1 A A A +25C +85C -40C VDD = 2.0V 32 kHz on Timer1(3) 3.1 3.5 3.6 3.8 9.7 9.7 9.6 9.6 A A A A +25C +85C -40C +25C VDD = 3.0V 32 kHz on Timer1(3) VDD = 5.0V 32 kHz on Timer1(3) 4.0 9.6 A +85C VDD = 2.0V VDD = 3.0V VDD = 5.0V VDD = 3.0V VDD = 5.0V Sleep mode, BOREN1:BOREN0 = 10 VDD = 2.0V VDD = 3.0V VDD = 5.0V Shading of rows is to assist in readability of the table. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD OR VSS; MCLR = VDD; WDT enabled/disabled as specified. Low-power Timer1 oscillator selected. BOR and HLVD enable internal band gap reference. With both modules enabled, current consumption will be less than the sum of both specifications. 2004 Microchip Technology Inc. Preliminary DS39646B-page 391 PIC18F8722 FAMILY 28.2 DC Characteristics: Power-Down and Supply Current PIC18F6X27/6X22/8X27/8X22 (Industrial, Extended) PIC18LF6X27/6X22/8X27/8X22 (Industrial) (Continued) PIC18LF6X27/6X22/8X27/8X22 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial PIC18F6X27/6X22/8X27/8X22 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Param No. Device A/D Converter D026 (IAD) Legend: Note 1: 2: 3: 4: Typ Max Units Conditions 1.2 2.4 A -40C to +85C VDD = 2.0V 1.2 1.2 2.4 2.4 A A -40C to +85C -40C to +85C VDD = 3.0V A/D on, not converting, Sleep mode VDD = 5.0V 2.4 9.6 A -40C to +125C Shading of rows is to assist in readability of the table. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD OR VSS; MCLR = VDD; WDT enabled/disabled as specified. Low-power Timer1 oscillator selected. BOR and HLVD enable internal band gap reference. With both modules enabled, current consumption will be less than the sum of both specifications. DS39646B-page 392 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY 28.3 DC Characteristics: PIC18F8722 (Industrial, Extended) PIC18LF6X27/6X22/8X27/8X22 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial DC CHARACTERISTICS Param Symbol No. VIL Characteristic Min Max Units Conditions VSS 0.15 VDD V VDD < 4.5V -- 0.8 V 4.5V VDD 5.5V VSS 0.2 VDD V 0.2 VDD V Input Low Voltage I/O ports: D030 with TTL buffer D030A D031 with Schmitt Trigger buffer D032 MCLR VSS D033 OSC1 VSS 0.3 VDD V HS, HSPLL modes D033A D033B D034 OSC1 OSC1 T13CKI VSS VSS VSS 0.2 VDD 0.3 0.3 V V V RC, EC modes(1) XT, LP modes 0.25 VDD + 0.8V VDD V VDD < 4.5V 2.0 VDD V 4.5V VDD 5.5V 0.8 VDD VDD V VIH Input High Voltage I/O ports: D040 with TTL buffer D040A D041 with Schmitt Trigger buffer D042 MCLR 0.8 VDD VDD V D043 OSC1 0.7 VDD VDD V HS, HSPLL modes D043A D043B D043C D044 OSC1 OSC1 OSC1 T13CKI 0.8 VDD 0.9 VDD 1.6 1.6 VDD VDD VDD VDD V V V V EC mode RC mode(1) XT, LP modes IIL Input Leakage Current(2,3) D060 I/O ports -- 1 A VSS VPIN VDD, Pin at high-impedance D061 MCLR -- 5 A Vss VPIN VDD D063 OSC1 -- 5 A Vss VPIN VDD 50 400 A VDD = 5V, VPIN = VSS D070 Note 1: 2: 3: IPU Weak Pull-up Current IPURB PORTB weak pull-up current In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the PICmicro(R) device be driven with an external clock while in RC mode. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. Negative current is defined as current sourced by the pin. 2004 Microchip Technology Inc. Preliminary DS39646B-page 393 PIC18F8722 FAMILY 28.3 DC Characteristics: PIC18F8722 (Industrial, Extended) PIC18LF6X27/6X22/8X27/8X22 (Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial DC CHARACTERISTICS Param Symbol No. VOL Characteristic Min Max Units Conditions Output Low Voltage D080 I/O ports -- 0.6 V IOL = 8.5 mA, VDD = 4.5V, -40C to +85C D083 OSC2/CLKO (RC, RCIO, EC, ECIO modes) -- 0.6 V IOL = 1.6 mA, VDD = 4.5V, -40C to +85C VOH Output High Voltage(3) D090 I/O ports VDD - 0.7 -- V IOH = -3.0 mA, VDD = 4.5V, -40C to +85C D092 OSC2/CLKO (RC, RCIO, EC, ECIO modes) VDD - 0.7 -- V IOH = -1.3 mA, VDD = 4.5V, -40C to +85C Capacitive Loading Specs on Output Pins D100 COSC2 OSC2 pin -- 15 pF In XT, HS and LP modes when external clock is used to drive OSC1 D101 CIO All I/O pins and OSC2 (in RC mode) -- 50 pF To meet the AC Timing Specifications D102 CB SCLx, SDAx -- 400 pF I2CTM Specification Note 1: 2: 3: In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the PICmicro(R) device be driven with an external clock while in RC mode. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. Negative current is defined as current sourced by the pin. DS39646B-page 394 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY TABLE 28-1: MEMORY PROGRAMMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial DC CHARACTERISTICS Param No. Sym Characteristic Min Typ Max Units Conditions Data EEPROM Memory D120 ED Byte Endurance 100K 1M -- D121 VDRW VDD for Read/Write VMIN -- 5.5 E/W -40C to +85C V Using EECON to read/write VMIN = Minimum operating voltage D122 TDEW Erase/Write Cycle Time -- 4 -- D123 TRETD Characteristic Retention 40 -- -- Year Provided no other specifications are violated ms D124 TREF Number of Total Erase/Write Cycles before Refresh(1) 1M 10M -- E/W -40C to +85C D125 IDDP Supply Current during Programming -- 10 -- mA D130 EP Cell Endurance 10K 100K -- E/W -40C to +85C D131 VPR VDD for Read VMIN -- 5.5 V VMIN = Minimum operating voltage D132B VPEW VDD for Self-Timed Write and Row Erase VMIN -- 5.5 V VMIN = Minimum operating voltage D133A TIW Self-Timed Write Cycle Time -- 2 -- ms 40 100 -- Year Provided no other specifications are violated -- 10 -- mA Program Flash Memory D134 TRETD Characteristic Retention D135 IDDP Supply Current during Programming Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Refer to Section 8.8 "Using the Data EEPROM" for a more detailed discussion on data EEPROM endurance. 2004 Microchip Technology Inc. Preliminary DS39646B-page 395 PIC18F8722 FAMILY TABLE 28-2: COMPARATOR SPECIFICATIONS Operating Conditions: 3.0V < VDD < 5.5V, -40C < TA < +85C (unless otherwise stated) Param No. Sym Characteristics Min Typ Max Units D300 VIOFF Input Offset Voltage -- 5.0 10 mV D301 VICM Input Common Mode Voltage 0 -- VDD - 1.5 V Comments D302 CMRR Common Mode Rejection Ratio 55 -- -- dB 300 TRESP Response Time(1) -- 150 400 ns PIC18FXXXX -- 150 600 ns PIC18LFXXXX, VDD = 2.0V -- -- 10 s 300A 301 Note 1: TMC2OV Comparator Mode Change to Output Valid Response time measured with one comparator input at (VDD - 1.5)/2, while the other input transitions from VSS to VDD. TABLE 28-3: COMPARATOR VOLTAGE REFERENCE SPECIFICATIONS Operating Conditions: 3.0V < VDD < 5.5V, -40C < TA < +85C (unless otherwise stated) Param No. Sym Characteristics Min Typ Max Units D310 VRES Resolution VDD/24 -- VDD/32 LSb D311 VRAA Absolute Accuracy -- -- 1/2 LSb D312 VRUR Unit Resistor Value (R) -- 2k -- TSET Time(1) -- -- 10 s 310 Note 1: Settling Comments Settling time measured while CVRR = 1 and CVR3:CVR0 transitions from `0000' to `1111'. DS39646B-page 396 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY FIGURE 28-4: HIGH/LOW-VOLTAGE DETECT CHARACTERISTICS For VDIRMAG = 1: VDD VHLVD (HLVDIF set by hardware) (HLVDIF can be cleared in software) VHLVD For VDIRMAG = 0: VDD HLVDIF TABLE 28-4: HIGH/LOW-VOLTAGE DETECT CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Param Symbol No. D420 Characteristic Min Typ Max Units HLVD Voltage on VDD HLVDL = 0000 Transition High-to-Low HLVDL = 0001 2.06 2.17 2.28 V 2.12 2.23 2.34 V HLVDL = 0010 2.24 2.36 2.48 V HLVDL = 0011 2.32 2.44 2.56 V HLVDL = 0100 2.47 2.60 2.73 V HLVDL = 0101 2.65 2.79 2.93 V HLVDL = 0110 2.74 2.89 3.04 V HLVDL = 0111 2.96 3.12 3.28 V HLVDL = 1000 3.22 3.39 3.56 V HLVDL = 1001 3.37 3.55 3.73 V HLVDL = 1010 3.52 3.71 3.90 V HLVDL = 1011 3.70 3.90 4.10 V HLVDL = 1100 3.90 4.11 4.32 V 2004 Microchip Technology Inc. HLVDL = 1101 4.11 4.33 4.55 V HLVDL = 1110 4.36 4.59 4.82 V Preliminary Conditions DS39646B-page 397 PIC18F8722 FAMILY 28.4 28.4.1 AC (Timing) Characteristics TIMING PARAMETER SYMBOLOGY The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 2. TppS T F Frequency Lowercase letters (pp) and their meanings: pp cc CCP1 ck CLKO cs CS di SDI do SDO dt Data in io I/O port mc MCLR Uppercase letters and their meanings: S F Fall H High I Invalid (High-Impedance) L Low I2C only AA output access BUF Bus free TCC:ST (I2C specifications only) CC HD Hold ST DAT DATA input hold STA Start condition DS39646B-page 398 3. TCC:ST 4. Ts (I2CTM specifications only) (I2C specifications only) T Time osc rd rw sc ss t0 t1 wr OSC1 RD RD or WR SCK SS T0CKI T13CKI WR P R V Z Period Rise Valid High-Impedance High Low High Low SU Setup STO Stop condition Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY 28.4.2 TIMING CONDITIONS Note: The temperature and voltages specified in Table 28-5 apply to all timing specifications unless otherwise noted. Figure 28-5 specifies the load conditions for the timing specifications. TABLE 28-5: Because of space limitations, the generic terms "PIC18FXXXX" and "PIC18LFXXXX" are used throughout this section to refer to the PIC18F6X27/6X22/8X27/8X22 and PIC18LF6X27/6X22/8X27/8X22 families of devices specifically and only those devices. TEMPERATURE AND VOLTAGE SPECIFICATIONS - AC AC CHARACTERISTICS FIGURE 28-5: Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Operating voltage VDD range as described in the DC specifications in Section 28.1 and Section 28.3. LF parts operate for industrial temperatures only. LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load Condition 1 Load Condition 2 VDD/2 RL CL Pin VSS CL Pin RL = 464 VSS 2004 Microchip Technology Inc. CL = 50 pF for all pins except OSC2/CLKO and including D and E outputs as ports Preliminary DS39646B-page 399 PIC18F8722 FAMILY 28.4.3 TIMING DIAGRAMS AND SPECIFICATIONS FIGURE 28-6: EXTERNAL CLOCK TIMING (ALL MODES EXCEPT PLL) Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 4 3 4 2 CLKO TABLE 28-6: Param. No. 1A EXTERNAL CLOCK TIMING REQUIREMENTS Symbol FOSC Characteristic Min External CLKI Frequency(1) DC 1 MHz XT, RC Oscillator mode DC 25 MHz HS Oscillator mode DC 31.25 kHz LP Oscillator mode DC 40 MHz EC Oscillator mode DC 4 MHz RC Oscillator mode 0.1 4 MHz XT Oscillator mode 4 25 MHz HS Oscillator mode 4 10 MHz HS + PLL Oscillator mode LP Oscillator mode Oscillator Frequency 1 TOSC External CLKI Period(1) Oscillator 2 3 4 Note 1: TCY (1) Period(1) Instruction Cycle Time(1) TOSL, TOSH External Clock in (OSC1) High or Low Time TOSR, TOSF External Clock in (OSC1) Rise or Fall Time Max Units Conditions 5 200 kHz 1000 -- ns XT, RC Oscillator mode 40 -- ns HS Oscillator mode 32 -- s LP Oscillator mode 25 -- ns EC Oscillator mode 250 -- ns RC Oscillator mode 250 1 s XT Oscillator mode 40 250 ns HS Oscillator mode 100 250 ns HS + PLL Oscillator mode 5 -- s LP Oscillator mode 100 -- ns TCY = 4/FOSC, Industrial 160 -- ns TCY = 4/FOSC, Extended 30 -- ns XT Oscillator mode 2.5 -- s LP Oscillator mode 10 -- ns HS Oscillator mode -- 20 ns XT Oscillator mode -- 50 ns LP Oscillator mode -- 7.5 ns HS Oscillator mode Instruction cycle period (TCY) equals four times the input oscillator time base period for all configurations except PLL. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKI pin. When an external clock input is used, the "max." cycle time limit is "DC" (no clock) for all devices. DS39646B-page 400 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY TABLE 28-7: Param No. PLL CLOCK TIMING SPECIFICATIONS (VDD = 4.2V TO 5.5V) Sym Characteristic Min Typ Max 4 16 -- -- 10 40 Units F10 F11 FOSC Oscillator Frequency Range FSYS On-Chip VCO System Frequency F12 trc PLL Start-up Time (Lock Time) -- -- 2 ms CLK CLKO Stability (Jitter) -2 -- +2 % F13 Conditions MHz HS mode only MHz HS mode only Data in "Typ" column is at 5V, 25C, unless otherwise stated. These parameters are for design guidance only and are not tested. TABLE 28-8: AC CHARACTERISTICS:INTERNAL RC ACCURACY PIC18F6X27/6X22/8X27/8X22 (INDUSTRIAL, EXTENDED) PIC18LF6X27/6X22/8X27/8X22 (INDUSTRIAL) PIC18LF6X27/6X22/8X27/8X22 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial PIC18F6X27/6X22/8X27/8X22 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Param No. Device Min Typ Max Units Conditions INTOSC Accuracy @ Freq = 8 MHz, 4 MHz, 2 MHz, 1 MHz, 500 kHz, 250 kHz, 125 kHz(1) PIC18LF6X27/6X22/8X27/8X22 PIC18F6X27/6X22/8X27/8X22 -2 +/-1 2 % +25C VDD = 2.7-3.3V -5 -- 5 % -10C to +85C VDD = 2.7-3.3V -10 +/-1 10 % -40C to +85C VDD = 2.7-3.3V -2 +/-1 2 % +25C VDD = 4.5-5.5V -5 -- 5 % -10C to +85C VDD = 4.5-5.5V -10 +/-1 10 % -40C to +85C VDD = 4.5-5.5V INTRC Accuracy @ Freq = 31 kHz(2) Legend: Note 1: 2: PIC18LF6X27/6X22/8X27/8X22 -15 -- 15 % -40C to +85C VDD = 2.7-3.3V PIC18F6X27/6X22/8X27/8X22 -15 +/-8 15 % -40C to +85C VDD = 4.5-5.5V Shading of rows is to assist in readability of the table. Frequency calibrated at 25C. OSCTUNE register can be used to compensate for temperature drift. INTRC frequency after calibration. 2004 Microchip Technology Inc. Preliminary DS39646B-page 401 PIC18F8722 FAMILY FIGURE 28-7: CLKO AND I/O TIMING Q1 Q4 Q2 Q3 OSC1 11 10 CLKO 13 19 14 12 18 16 I/O pin (Input) 15 17 I/O pin (Output) Note: 20, 21 Refer to Figure 28-5 for load conditions. TABLE 28-9: Param No. New Value Old Value CLKO AND I/O TIMING REQUIREMENTS Symbol Characteristic Min Typ Max Units Conditions 10 TOSH2CKL OSC1 to CLKO -- 75 200 ns (Note 1) 11 TOSH2CKH OSC1 to CLKO -- 75 200 ns (Note 1) 12 TCKR CLKO Rise Time -- 35 100 ns (Note 1) 13 TCKF CLKO Fall Time -- 35 100 ns (Note 1) 14 TCKL2IOV CLKO to Port Out Valid -- -- 0.5 TCY + 20 ns (Note 1) 15 TIOV2CKH Port In Valid before CLKO 16 TCKH2IOI 17 TOSH2IOV OSC1 (Q1 cycle) to Port Out Valid 18 TOSH2IOI 18A 0.25 TCY + 25 -- -- ns (Note 1) 0 -- -- ns (Note 1) Port In Hold after CLKO OSC1 (Q2 cycle) to Port Input Invalid (I/O in hold time) -- 50 150 ns PIC18FXXXX 100 -- -- ns PIC18LFXXXX 200 -- -- ns 19 TIOV2OSH Port Input Valid to OSC1 (I/O in setup time) 0 -- -- ns 20 TIOR PIC18FXXXX -- 10 25 ns PIC18LFXXXX -- -- 60 ns PIC18FXXXX -- 10 25 ns PIC18LFXXXX -- -- 60 ns Port Output Rise Time 20A 21 TIOF Port Output Fall Time 21A 22 TINP INT pin High or Low Time TCY -- -- ns 23 TRBP RB7:RB4 Change INT High or Low Time TCY -- -- ns VDD = 2.0V VDD = 2.0V VDD = 2.0V These parameters are asynchronous events not related to any internal clock edges. Note 1: Measurements are taken in RC mode, where CLKO output is 4 x TOSC. DS39646B-page 402 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY FIGURE 28-8: PROGRAM MEMORY READ TIMING DIAGRAM Q1 Q2 Q3 Q4 Q1 Q2 OSC1 A<19:16> BA0 Address Address Address AD<15:0> Data from External 150 151 Address 163 160 162 161 155 166 167 168 ALE 164 169 171 CE 171A OE 165 Operating Conditions: 2.0V < VCC < 5.5V, -40C < TA < +125C unless otherwise stated. TABLE 28-10: CLKO AND I/O TIMING REQUIREMENTS Param. No Symbol Characteristics Min Typ Max Units 0.25 TCY - 10 -- -- ns 150 TadV2alL Address Out Valid to ALE (address setup time) 151 TalL2adl ALE to Address Out Invalid (address hold time) 5 -- -- ns 155 TalL2oeL ALE to OE 10 0.125 TCY -- ns 160 TadZ2oeL AD high-Z to OE (bus release to OE) 0 -- -- ns 0.125 TCY - 5 -- -- ns 20 -- -- ns 0 -- -- ns 161 ToeH2adD OE to AD Driven 162 TadV2oeH LS Data Valid before OE (data setup time) 163 ToeH2adl OE to Data In Invalid (data hold time) 164 TalH2alL ALE Pulse Width 165 ToeL2oeH OE Pulse Width -- TCY -- ns 0.5 TCY - 5 0.5 TCY -- ns 166 TalH2alH ALE to ALE (cycle time) -- 0.25 TCY -- ns 167 Tacc Address Valid to Data Valid 0.75 TCY - 25 -- -- ns 168 Toe OE to Data Valid -- 0.5 TCY - 25 ns 169 TalL2oeH ALE to OE 0.625 TCY - 10 -- 0.625 TCY + 10 ns 171 TalH2csL Chip Enable Active to ALE 0.25 TCY - 20 -- -- ns 171A TubL2oeH AD Valid to Chip Enable Active -- -- 10 ns 2004 Microchip Technology Inc. Preliminary DS39646B-page 403 PIC18F8722 FAMILY FIGURE 28-9: PROGRAM MEMORY WRITE TIMING DIAGRAM Q1 Q2 Q3 Q4 Q1 Q2 OSC1 A<19:16> BA0 Address Address 166 AD<15:0> Data Address Address 153 150 156 151 ALE 171 CE 171A 154 WRH or WRL 157A 157 UB or LB Operating Conditions: 2.0V < VCC < 5.5V, -40C < TA < +125C unless otherwise stated. TABLE 28-11: PROGRAM MEMORY WRITE TIMING REQUIREMENTS Param. No Symbol Characteristics Min Typ Max Units 0.25 TCY - 10 -- -- ns 150 TadV2alL Address Out Valid to ALE (address setup time) 151 TalL2adl ALE to Address Out Invalid (address hold time) 5 -- -- ns 153 TwrH2adl WRn to Data Out Invalid (data hold time) 5 -- -- ns 154 TwrL WRn Pulse Width 0.5 TCY - 5 0.5 TCY -- ns 156 TadV2wrH Data Valid before WRn (data setup time) 0.5 TCY - 10 -- -- ns 157 TbsV2wrL Byte Select Valid before WRn (byte select setup time) 0.25 TCY -- -- ns 157A TwrH2bsI WRn to Byte Select Invalid (byte select hold time) 0.125 TCY - 5 -- -- ns 166 TalH2alH ALE to ALE (cycle time) -- 0.25 TCY -- ns 171 TalH2csL Chip Enable Active to ALE 0.25 TCY - 20 -- -- ns 171A TubL2oeH AD Valid to Chip Enable Active -- -- 10 ns DS39646B-page 404 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY FIGURE 28-10: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 Oscillator Time-out Internal Reset Watchdog Timer Reset 31 34 34 I/O pins Note: Refer to Figure 28-5 for load conditions. FIGURE 28-11: BROWN-OUT RESET TIMING BVDD VDD 35 VBGAP = 1.2V VIRVST Enable Internal Reference Voltage Internal Reference Voltage Stable 36 TABLE 28-12: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET REQUIREMENTS Param. Symbol No. Characteristic Min Typ Max Units 30 TmcL MCLR Pulse Width (low) 2 -- -- s 31 TWDT Watchdog Timer Time-out Period (no postscaler) 3.4 4.0 4.6 ms 32 TOST Oscillation Start-up Timer Period 1024 TOSC -- 1024 TOSC -- 33 TPWRT Power-up Timer Period 55.6 64 75 ms 34 TIOZ I/O High-Impedance from MCLR Low or Watchdog Timer Reset -- 2 -- s 35 TBOR Brown-out Reset Pulse Width 36 TIRVST Time for Internal Reference Voltage to become Stable 37 TLVD High/Low-Voltage Detect Pulse Width 38 TCSD CPU Start-up Time 39 TIOBST Time for INTOSC to Stabilize 2004 Microchip Technology Inc. 200 -- -- s -- 20 50 s 200 -- -- s -- 10 -- s -- 1 -- s Preliminary Conditions TOSC = OSC1 period VDD BVDD (see D005) VDD VHLVD DS39646B-page 405 PIC18F8722 FAMILY FIGURE 28-12: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI 41 40 42 T1OSO/T13CKI 46 45 47 48 TMR0 or TMR1 Note: Refer to Figure 28-5 for load conditions. TABLE 28-13: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param No. Symbol Characteristic 40 TT0H T0CKI High Pulse Width 41 TT0L T0CKI Low Pulse Width 42 TT0P T0CKI Period No prescaler With prescaler No prescaler With prescaler 45 TT1H ns 10 -- ns 0.5 TCY + 20 -- ns ns ns With prescaler Greater of: 20 ns or (TCY + 40)/N -- ns T13CKI Synchronous, no prescaler High Time Synchronous, PIC18FXXXX with prescaler PIC18LFXXXX 0.5 TCY + 20 -- ns 10 -- ns 25 -- ns 30 -- ns PIC18FXXXX T13CKI Low Time Synchronous, no prescaler Synchronous, with prescaler 50 -- ns 0.5 TCY + 5 -- ns PIC18FXXXX 10 -- ns PIC18LFXXXX 25 -- ns Conditions N = prescale value (1, 2, 4,..., 256) VDD = 2.0V VDD = 2.0V VDD = 2.0V PIC18FXXXX 30 -- ns PIC18LFXXXX 50 -- ns VDD = 2.0V Greater of: 20 ns or (TCY + 40)/N -- ns N = prescale value (1, 2, 4, 8) TT1P T13CKI Input Period FT 1 T13CKI Oscillator Input Frequency Range Synchronous TCKE2TMRI Delay from External T13CKI Clock Edge to Timer Increment DS39646B-page 406 -- -- Asynchronous 48 0.5 TCY + 20 -- Asynchronous 47 Units 10 No prescaler PIC18LFXXXX TT1L Max TCY + 10 Asynchronous 46 Min Preliminary 60 -- ns DC 50 kHz 2 TOSC 7 TOSC -- 2004 Microchip Technology Inc. PIC18F8722 FAMILY FIGURE 28-13: CAPTURE/COMPARE/PWM TIMINGS (ALL ECCP/CCP MODULES) CCPx (Capture Mode) 50 51 52 CCPx (Compare or PWM Mode) 54 53 Note: Refer to Figure 28-5 for load conditions. TABLE 28-14: CAPTURE/COMPARE/PWM REQUIREMENTS (ALL ECCP/CCP MODULES) Param Symbol No. 50 51 TCCL TCCH Characteristic Min Max Units CCPx Input Low No prescaler Time With PIC18FXXXX prescaler PIC18LFXXXX 0.5 TCY + 20 -- ns 10 -- ns 20 -- ns CCPx Input High Time 0.5 TCY + 20 -- ns No prescaler With prescaler 52 TCCP CCPx Input Period 53 TCCR CCPx Output Fall Time 54 TCCF CCPx Output Fall Time 2004 Microchip Technology Inc. Conditions VDD = 2.0V PIC18FXXXX 10 -- ns PIC18LFXXXX 20 -- ns VDD = 2.0V 3 TCY + 40 N -- ns N = prescale value (1, 4 or 16) -- 25 ns PIC18FXXXX PIC18LFXXXX -- 45 ns PIC18FXXXX -- 25 ns PIC18LFXXXX -- 45 ns Preliminary VDD = 2.0V VDD = 2.0V DS39646B-page 407 PIC18F8722 FAMILY FIGURE 28-14: PARALLEL SLAVE PORT TIMING (PIC18F8527/8622/8627/8722) RE2/CS RE0/RD RE1/WR 65 RD7:RD0 62 64 63 Note: Refer to Figure 28-5 for load conditions. TABLE 28-15: PARALLEL SLAVE PORT REQUIREMENTS (PIC18F8527/8622/8627/8722) Param. No. Symbol Characteristic Min Max Units 62 TdtV2wrH Data In Valid before WR or CS (setup time) 20 -- ns 63 TwrH2dtI WR or CS to Data-In Invalid (hold time) PIC18FXXXX 20 -- ns PIC18LFXXXX 35 -- ns 64 TrdL2dtV RD and CS to Data-Out Valid -- 80 ns 65 TrdH2dtI RD or CS to Data-Out Invalid 10 30 ns 66 TibfINH Inhibit of the IBF Flag bit being Cleared from WR or CS -- 3 TCY DS39646B-page 408 Preliminary Conditions VDD = 2.0V 2004 Microchip Technology Inc. PIC18F8722 FAMILY FIGURE 28-15: EXAMPLE SPITM MASTER MODE TIMING (CKE = 0) SSx 70 SCKx (CKP = 0) 71 72 78 79 79 78 SCKx (CKP = 1) 80 bit 6 - - - - - - 1 MSb SDOx LSb 75, 76 SDIx MSb In bit 6 - - - - 1 LSb In 74 73 Note: Refer to Figure 28-5 for load conditions. TABLE 28-16: EXAMPLE SPITM MODE REQUIREMENTS (MASTER MODE, CKE = 0) Param No. Symbol Characteristic 70 TSSL2SCH, TSSL2SCL SSx to SCKx or SCKx Input 71 TSCH SCKx Input High Time (Slave mode) SCKx Input Low Time (Slave mode) 71A 72 TSCL 72A Min Max Units TCY -- ns Continuous 1.25 TCY + 30 -- ns Single Byte 40 -- ns Continuous 1.25 TCY + 30 -- ns Single Byte 40 -- ns 100 -- ns 1.5 TCY + 40 -- ns 73 TDIV2SCH, TDIV2SCL Setup Time of SDIx Data Input to SCKx Edge 73A TB2B Last Clock Edge of Byte 1 to the 1st Clock Edge of Byte 2 74 TSCH2DIL, TSCL2DIL Hold Time of SDIx Data Input to SCKx Edge 100 -- ns 75 TDOR SDOx Data Output Rise Time PIC18FXXXX -- 25 ns -- 45 ns 76 TDOF SDOx Data Output Fall Time -- 25 ns 78 TSCR SCKx Output Rise Time (Master mode) PIC18LFXXXX PIC18FXXXX -- 25 ns PIC18LFXXXX -- 45 ns -- 25 ns -- 50 ns -- 100 ns 79 TSCF 80 TSCH2DOV, SDOx Data Output Valid after PIC18FXXXX TSCL2DOV SCKx Edge PIC18LFXXXX Note 1: 2: SCKx Output Fall Time (Master mode) Conditions (Note 1) (Note 1) (Note 2) VDD = 2.0V VDD = 2.0V VDD = 2.0V Requires the use of Parameter #73A. Only if Parameter #71A and #72A are used. 2004 Microchip Technology Inc. Preliminary DS39646B-page 409 PIC18F8722 FAMILY FIGURE 28-16: EXAMPLE SPITM MASTER MODE TIMING (CKE = 1) SSx 81 SCKx (CKP = 0) 71 72 79 73 SCKx (CKP = 1) 80 78 MSb SDOx bit 6 - - - - - - 1 LSb bit 6 - - - - 1 LSb In 75, 76 SDIx MSb In 74 Note: Refer to Figure 28-5 for load conditions. TABLE 28-17: EXAMPLE SPITM MODE REQUIREMENTS (MASTER MODE, CKE = 1) Param. No. 71 Symbol TSCH 71A 72 TSCL 72A Characteristic Min Max Units SCKx Input High Time (Slave mode) Continuous 1.25 TCY + 30 -- ns Single Byte 40 -- ns SCKx Input Low Time (Slave mode) Continuous 1.25 TCY + 30 -- ns Single Byte 40 -- ns 100 -- ns 1.5 TCY + 40 -- ns 73 TDIV2SCH, TDIV2SCL Setup Time of SDIx Data Input to SCKx Edge 73A TB2B Last Clock Edge of Byte 1 to the 1st Clock Edge of Byte 2 74 TSCH2DIL, TSCL2DIL Hold Time of SDIx Data Input to SCKx Edge 100 -- ns 75 TDOR SDOx Data Output Rise Time PIC18FXXXX -- 25 ns 76 TDOF SDOx Data Output Fall Time 78 TSCR SCKx Output Rise Time (Master mode) PIC18LFXXXX 45 ns 25 ns PIC18FXXXX -- 25 ns PIC18LFXXXX -- 45 ns -- 25 ns -- 50 ns -- 100 ns TCY -- ns 79 TSCF 80 TSCH2DOV, SDOx Data Output Valid after PIC18FXXXX TSCL2DOV SCKx Edge PIC18LFXXXX 81 TDOV2SCH, SDOx Data Output Setup to SCKx Edge TDOV2SCL Note 1: 2: -- -- SCKx Output Fall Time (Master mode) Conditions (Note 1) (Note 1) (Note 2) VDD = 2.0V VDD = 2.0V VDD = 2.0V Requires the use of Parameter #73A. Only if Parameter #71A and #72A are used. DS39646B-page 410 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY FIGURE 28-17: EXAMPLE SPITM SLAVE MODE TIMING (CKE = 0) SSx 70 SCKx (CKP = 0) 83 71 72 78 79 79 78 SCKx (CKP = 1) 80 MSb SDOx bit 6 - - - - - - 1 LSb 75, 76 MSb In SDIx SDI 77 bit 6 - - - - 1 LSb In 74 73 Note: Refer to Figure 28-5 for load conditions. TABLE 28-18: EXAMPLE SPITM MODE REQUIREMENTS (SLAVE MODE TIMING, CKE = 0) Param No. Symbol Characteristic 70 TSSL2SCH, SSx to SCKx or SCKx Input TSSL2SCL 71 TSCH SCKx Input High Time (Slave mode) TSCL SCKx Input Low Time (Slave mode) 71A 72 72A Min Continuous Max Units Conditions TCY -- ns 1.25 TCY + 30 -- ns Single Byte 40 -- ns Continuous 1.25 TCY + 30 -- ns 40 -- ns 100 -- ns -- ns 100 -- ns PIC18FXXXX -- 25 ns PIC18LFXXXX Single Byte 73 TDIV2SCH, Setup Time of SDIx Data Input to SCKx Edge TDIV2SCL 73A TB2B 74 TSCH2DIL, Hold Time of SDIx Data Input to SCKx Edge TSCL2DIL 75 TDOR SDOx Data Output Rise Time -- 45 ns 76 TDOF SDOx Data Output Fall Time -- 25 ns Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40 77 TSSH2DOZ SSx to SDOx Output High-impedance 10 50 ns 78 TSCR SCKx Output Rise Time (Master mode) PIC18FXXXX -- 25 ns -- 45 ns 79 TSCF SCKx Output Fall Time (Master mode) -- 25 ns 80 TSCH2DOV, SDOx Data Output Valid after SCKx TSCL2DOV Edge PIC18LFXXXX 83 Note 1: 2: PIC18FXXXX -- 50 ns PIC18LFXXXX -- 100 ns 1.5 TCY + 40 -- ns TSCH2SSH, SSx after SCKx Edge TSCL2SSH (Note 1) (Note 1) (Note 2) VDD = 2.0V VDD = 2.0V VDD = 2.0V Requires the use of Parameter #73A. Only if Parameter #71A and #72A are used. 2004 Microchip Technology Inc. Preliminary DS39646B-page 411 PIC18F8722 FAMILY FIGURE 28-18: EXAMPLE SPITM SLAVE MODE TIMING (CKE = 1) 82 SSx SCKx (CKP = 0) 70 83 71 72 SCKx (CKP = 1) 80 MSb SDOx bit 6 - - - - - - 1 LSb 75, 76 SDIx SDI Note: MSb In 77 bit 6 - - - - 1 LSb In 74 Refer to Figure 28-5 for load conditions. TABLE 28-19: EXAMPLE SPITM SLAVE MODE REQUIREMENTS (CKE = 1) Param No. Symbol Characteristic Min Max Units Conditions 70 TSSL2SCH, SSx to SCKx or SCKx Input TSSL2SCL 71 TSCH SCKx Input High Time (Slave mode) TSCL SCKx Input Low Time (Slave mode) 73A TB2B Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40 74 TSCH2DIL, Hold Time of SDIx Data Input to SCKx Edge TSCL2DIL 75 TDOR SDOx Data Output Rise Time 76 TDOF SDOx Data Output Fall Time 71A 72 72A TCY -- ns 1.25 TCY + 30 -- ns Single Byte 40 -- ns Continuous 1.25 TCY + 30 -- ns Single Byte 40 -- ns (Note 1) -- ns (Note 2) 100 -- ns -- 25 ns Continuous PIC18FXXXX PIC18LFXXXX -- 45 ns -- 25 ns 77 TSSH2DOZ SSx to SDOx Output High-Impedance 10 50 ns 78 TSCR SCKx Output Rise Time (Master mode) PIC18FXXXX -- 25 ns PIC18LFXXXX -- 45 ns 79 TSCF SCKx Output Fall Time (Master mode) -- 25 ns 80 TSCH2DOV, SDOx Data Output Valid after SCKx TSCL2DOV Edge 82 TSSL2DOV SDOx Data Output Valid after SSx Edge 83 TSCH2SSH, SSx after SCKx Edge TSCL2SSH Note 1: 2: PIC18FXXXX -- 50 ns PIC18LFXXXX -- 100 ns PIC18FXXXX -- 50 ns -- 100 ns 1.5 TCY + 40 -- ns PIC18LFXXXX (Note 1) VDD = 2.0V VDD = 2.0V VDD = 2.0V VDD = 2.0V Requires the use of Parameter #73A. Only if Parameter #71A and #72A are used. DS39646B-page 412 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY FIGURE 28-19: I2CTM BUS START/STOP BITS TIMING SCLx 91 93 90 92 SDAx Stop Condition Start Condition Note: Refer to Figure 28-5 for load conditions. TABLE 28-20: I2CTM BUS START/STOP BITS REQUIREMENTS (SLAVE MODE) Param. Symbol No. 90 91 92 93 TSU:STA THD:STA TSU:STO Characteristic Max Units Conditions ns Only relevant for Repeated Start condition ns After this period, the first clock pulse is generated Start Condition 100 kHz mode 4700 -- Setup Time 400 kHz mode 600 -- Start Condition 100 kHz mode 4000 -- Hold Time 400 kHz mode 600 -- Stop Condition 100 kHz mode 4700 -- Setup Time 400 kHz mode 600 -- 100 kHz mode 4000 -- 400 kHz mode 600 -- THD:STO Stop Condition Hold Time FIGURE 28-20: Min ns ns I2CTM BUS DATA TIMING 103 102 100 101 SCLx 90 106 107 91 92 SDAx In 110 109 109 SDAx Out Note: Refer to Figure 28-5 for load conditions. 2004 Microchip Technology Inc. Preliminary DS39646B-page 413 PIC18F8722 FAMILY TABLE 28-21: I2CTM BUS DATA REQUIREMENTS (SLAVE MODE) Param. No. 100 Symbol THIGH Characteristic Clock High Time Min Max Units Conditions 100 kHz mode 4.0 -- s PIC18FXXXX must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 -- s PIC18FXXXX must operate at a minimum of 10 MHz 1.5 TCY -- 100 kHz mode 4.7 -- s PIC18FXXXX must operate at a minimum of 1.5 MHz 400 kHz mode 1.3 -- s PIC18FXXXX must operate at a minimum of 10 MHz SSP Module 101 TLOW Clock Low Time SSP Module 102 TR SDAx and SCLx Rise Time 100 kHz mode 400 kHz mode 103 TF SDAx and SCLx Fall Time 100 kHz mode TSU:STA THD:STA 91 THD:DAT 106 TSU:DAT 107 TSU:STO 92 109 TAA 110 TBUF D102 CB Note 1: 2: -- -- 1000 ns 20 + 0.1 CB 300 ns CB is specified to be from 10 to 400 pF -- 300 ns 20 + 0.1 CB 300 ns CB is specified to be from 10 to 400 pF Start Condition Setup Time 100 kHz mode 4.7 -- s 400 kHz mode 0.6 -- s Only relevant for Repeated Start condition 400 kHz mode 90 1.5 TCY Start Condition Hold Time Data Input Hold Time Data Input Setup Time 100 kHz mode 4.0 -- s 400 kHz mode 0.6 -- s 100 kHz mode 0 -- ns 400 kHz mode 0 0.9 s 100 kHz mode 250 -- ns 400 kHz mode 100 -- ns Stop Condition Setup Time 100 kHz mode 4.7 -- s 400 kHz mode 0.6 -- s Output Valid from Clock Bus Free Time Bus Capacitive Loading 100 kHz mode -- 3500 ns 400 kHz mode -- -- ns 100 kHz mode 4.7 -- s 400 kHz mode 1.3 -- s -- 400 pF After this period, the first clock pulse is generated (Note 2) (Note 1) Time the bus must be free before a new transmission can start As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCLx to avoid unintended generation of Start or Stop conditions. A Fast mode I2CTM bus device can be used in a Standard mode I2C bus system, but the requirement, TSU:DAT 250 ns, must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCLx signal. If such a device does stretch the LOW period of the SCLx signal, it must output the next data bit to the SDAx line, TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification), before the SCLx line is released. DS39646B-page 414 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY FIGURE 28-21: MASTER SSP I2CTM BUS START/STOP BITS TIMING WAVEFORMS SCLx 93 91 90 92 SDAx Stop Condition Start Condition Note: Refer to Figure 28-5 for load conditions. TABLE 28-22: MASTER SSP I2CTM BUS START/STOP BITS REQUIREMENTS Param. Symbol No. 90 TSU:STA Characteristic After this period, the first clock pulse is generated 400 kHz mode 2(TOSC)(BRG + 1) -- mode(1) 2(TOSC)(BRG + 1) -- 100 kHz mode 2(TOSC)(BRG + 1) -- 400 kHz mode 2(TOSC)(BRG + 1) -- 1 MHz mode(1) 2(TOSC)(BRG + 1) -- Stop Condition 100 kHz mode 2(TOSC)(BRG + 1) -- Setup Time 400 kHz mode THD:STO Stop Condition 2(TOSC)(BRG + 1) -- mode(1) 2(TOSC)(BRG + 1) -- 100 kHz mode 2(TOSC)(BRG + 1) -- 400 kHz mode 2(TOSC)(BRG + 1) -- 1 MHz mode(1) 2(TOSC)(BRG + 1) -- 2CTM Maximum pin capacitance = 10 pF for all I FIGURE 28-22: ns Setup Time Hold Time Note 1: Only relevant for Repeated Start condition -- 1 MHz 93 ns 2(TOSC)(BRG + 1) Hold Time 92 Units 100 kHz mode THD:STA Start Condition TSU:STO Max Start Condition 1 MHz 91 Min Conditions ns ns pins. MASTER SSP I2CTM BUS DATA TIMING 103 102 100 101 SCLx 90 106 91 107 92 SDAx In 109 109 110 SDAx Out Note: Refer to Figure 28-5 for load conditions. 2004 Microchip Technology Inc. Preliminary DS39646B-page 415 PIC18F8722 FAMILY TABLE 28-23: MASTER SSP I2CTM BUS DATA REQUIREMENTS Param. Symbol No. 100 101 THIGH TLOW Characteristic Min Max Units 2(TOSC)(BRG + 1) -- ms 400 kHz mode 2(TOSC)(BRG + 1) -- ms 1 MHz mode(1) 2(TOSC)(BRG + 1) -- ms Clock Low Time 100 kHz mode 2(TOSC)(BRG + 1) -- ms 400 kHz mode 2(TOSC)(BRG + 1) -- ms (1) 2(TOSC)(BRG + 1) -- ms -- 1000 ns 20 + 0.1 CB 300 ns -- 300 ns Clock High Time 100 kHz mode 1 MHz mode 102 TR SDAx and SCLx 100 kHz mode Rise Time 400 kHz mode 1 MHz mode(1) 103 90 91 106 107 92 109 110 D102 TF TSU:STA SDAx and SCLx 100 kHz mode Fall Time 400 kHz mode Start Condition Setup Time THD:STA Start Condition Hold Time THD:DAT Data Input Hold Time TSU:DAT Data Input Setup Time TSU:STO Stop Condition Setup Time TAA TBUF CB Output Valid from Clock Bus Free Time -- 300 ns 20 + 0.1 CB 300 ns 1 MHz mode(1) -- 100 ns 100 kHz mode 2(TOSC)(BRG + 1) -- ms 400 kHz mode 2(TOSC)(BRG + 1) -- ms 1 MHz mode(1) 2(TOSC)(BRG + 1) -- ms 100 kHz mode 2(TOSC)(BRG + 1) -- ms 400 kHz mode 2(TOSC)(BRG + 1) -- ms 1 MHz mode(1) 2(TOSC)(BRG + 1) -- ms 100 kHz mode 0 -- ns 400 kHz mode 0 0.9 ms 1 MHz mode(1) TBD -- ns 100 kHz mode 250 -- ns 400 kHz mode 100 -- ns 1 MHz mode(1) TBD -- ns 100 kHz mode 2(TOSC)(BRG + 1) -- ms 400 kHz mode 2(TOSC)(BRG + 1) -- ms 1 MHz mode(1) 2(TOSC)(BRG + 1) -- ms 100 kHz mode -- 3500 ns 400 kHz mode -- 1000 ns (1) 1 MHz mode -- -- ns 100 kHz mode 4.7 -- ms 400 kHz mode 1.3 -- ms 1 MHz mode(1) TBD -- ms -- 400 pF Bus Capacitive Loading Conditions CB is specified to be from 10 to 400 pF CB is specified to be from 10 to 400 pF Only relevant for Repeated Start condition After this period, the first clock pulse is generated (Note 2) Time the bus must be free before a new transmission can start Legend: TBD = To Be Determined Note 1: Maximum pin capacitance = 10 pF for all I2CTM pins. 2: A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but parameter #107 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCLx signal. If such a device does stretch the LOW period of the SCLx signal, it must output the next data bit to the SDAx line, parameter #102 + parameter #107 = 1000 + 250 = 1250 ns (for 100 kHz mode,) before the SCLx line is released. DS39646B-page 416 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY FIGURE 28-23: EUSART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING CKx/TXx pin 121 121 DTx/RXx pin 122 120 Note: Refer to Figure 28-5 for load conditions. TABLE 28-24: EUSART SYNCHRONOUS TRANSMISSION REQUIREMENTS Param No. 120 Symbol Characteristic TCKH2DTV SYNC XMIT (MASTER and SLAVE) Clock High to Data Out Valid PIC18FXXXX Min Max Units -- 40 ns PIC18LFXXXX -- 100 ns 121 TCKRF Clock Out Rise Time and Fall Time (Master mode) PIC18FXXXX -- 20 ns PIC18LFXXXX -- 50 ns 122 TDTRF Data Out Rise Time and Fall Time PIC18FXXXX -- 20 ns PIC18LFXXXX -- 50 ns FIGURE 28-24: Conditions VDD = 2.0V VDD = 2.0V VDD = 2.0V EUSART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING CKx/TXx pin 125 DTx/RXx pin 126 Note: Refer to Figure 28-5 for load conditions. TABLE 28-25: EUSART SYNCHRONOUS RECEIVE REQUIREMENTS Param. No. 125 126 Symbol Characteristic TDTV2CKL SYNC RCV (MASTER and SLAVE) Data Hold before CKx (DTx hold time) TCKL2DTL Data Hold after CKx (DTx hold time) 2004 Microchip Technology Inc. Preliminary Min Max Units 10 -- ns 15 -- ns Conditions DS39646B-page 417 PIC18F8722 FAMILY TABLE 28-26: A/D CONVERTER CHARACTERISTICS: PIC18F6X27/6X22/8X27/8X22 (INDUSTRIAL) PIC18LF6X27/6X22/8X27/8X22 (INDUSTRIAL) Param Symbol No. Characteristic Min Typ Max Units -- -- 10 bit Conditions VREF 3.0V A01 NR Resolution A03 EIL Integral Linearity Error -- -- <1 LSb VREF 3.0V A04 EDL Differential Linearity Error -- -- <1 LSb VREF 3.0V A06 EOFF Offset Error -- -- <1.5 LSb VREF 3.0V A07 EGN Gain Error -- -- <1 LSb VREF 3.0V A10 -- Monotonicity -- VSS VAIN VREF A20 VREF Reference Voltage Range (VREFH - VREFL) 1.8 3 -- -- -- -- V V VDD < 3.0V VDD 3.0V A21 VREFH Reference Voltage High VSS -- VREFH V A22 VREFL Reference Voltage Low VSS - 0.3V -- VDD - 3.0V V A25 VAIN Analog Input Voltage VREFL -- VREFH V A30 ZAIN Recommended Impedance of Analog Voltage Source -- -- 2.5 k A40 IAD A/D Current from VDD PIC18FXXXX -- 180 -- A PIC18LFXXXX -- 90 -- A A50 IREF VREF Input Current(2) -- -- -- -- 5 150 A A Note 1: 2: Guaranteed(1) Average current during conversion During VAIN acquisition. During A/D conversion cycle. The A/D conversion result never decreases with an increase in the input voltage and has no missing codes. VREFH current is from RA3/AN3/VREF+ pin or VDD, whichever is selected as the VREFH source. VREFL current is from RA2/AN2/VREF- pin or VSS, whichever is selected as the VREFL source. FIGURE 28-25: A/D CONVERSION TIMING BSF ADCON0, GO (Note 1, 2) 131 Q4 130 A/D CLK 132 9 A/D DATA 8 7 ... ... 2 1 OLD_DATA ADRES 0 NEW_DATA TCY ADIF GO DONE SAMPLING STOPPED SAMPLE Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. 2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input. DS39646B-page 418 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY TABLE 28-27: A/D CONVERSION REQUIREMENTS Param Symbol No. 130 TAD Characteristic A/D Clock Period Min Max Units 0.7 25.0(1) s TOSC based, VREF 3.0V 1.4 25.0 (1) s VDD = 2.0V; TOSC based, VREF full range PIC18FXXXX TBD 1 s A/D RC mode PIC18LFXXXX TBD 3 s VDD = 2.0V; A/D RC mode 11 12 TAD 1.4 TBD -- -- s s PIC18FXXXX PIC18LFXXXX 131 TCNV Conversion Time (not including acquisition time) (Note 2) 132 TACQ Acquisition Time (Note 3) 135 TSWC Switching Time from Convert Sample -- (Note 4) 137 TDIS Discharge Time 0.2 -- Legend: Note 1: 2: 3: 4: Conditions -40C to +85C 0C to +85C s TBD = To Be Determined The time of the A/D clock period is dependent on the device frequency and the TAD clock divider. ADRES register may be read on the following TCY cycle. The time for the holding capacitor to acquire the "New" input voltage when the voltage changes full scale after the conversion (VDD to VSS or VSS to VDD). The source impedance (RS) on the input channels is 50. On the following cycle of the device clock. 2004 Microchip Technology Inc. Preliminary DS39646B-page 419 PIC18F8722 FAMILY NOTES: DS39646B-page 420 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY 29.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES Graphs and tables are not available at this time. 2004 Microchip Technology Inc. Preliminary DS39646B-page 421 PIC18F8722 FAMILY NOTES: DS39646B-page 422 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY 30.0 PACKAGING INFORMATION 30.1 Package Marking Information 64-Lead TQFP Example XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN PIC18F6722 -I/PT 0410017 80-Lead TQFP Example XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN Legend: XX...X Y YY WW NNN Note: * PIC18F8722-E /PT 0410017 Customer specific information* Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. Standard PICmicro device marking consists of Microchip part number, year code, week code, and traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. 2004 Microchip Technology Inc. Preliminary DS39646B-page 423 PIC18F8722 FAMILY 30.2 Package Details The following sections give the technical details of the packages. 64-Lead Plastic Thin Quad Flatpack (PT) 10x10x1 mm Body, 1.0/0.10 mm Lead Form (TQFP) E E1 #leads=n1 p D1 D 2 1 B n CH x 45 A c L A2 A1 (F) Units Dimension Limits n p MIN INCHES NOM 64 .020 16 .043 .039 .006 .024 .039 3.5 .472 .472 .394 .394 .007 .009 .035 10 10 MAX MILLIMETERS* NOM 64 0.50 16 1.00 1.10 0.95 1.00 0.05 0.15 0.45 0.60 1.00 0 3.5 11.75 12.00 11.75 12.00 9.90 10.00 9.90 10.00 0.13 0.18 0.17 0.22 0.64 0.89 5 10 5 10 MIN Number of Pins Pitch Pins per Side n1 Overall Height A .039 .047 Molded Package Thickness A2 .037 .041 Standoff A1 .002 .010 Foot Length L .018 .030 (F) Footprint (Reference) Foot Angle 0 7 Overall Width E .463 .482 Overall Length D .463 .482 Molded Package Width E1 .390 .398 Molded Package Length D1 .390 .398 c Lead Thickness .005 .009 Lead Width B .007 .011 Pin 1 Corner Chamfer CH .025 .045 Mold Draft Angle Top 5 15 Mold Draft Angle Bottom 5 15 *Controlling Parameter Notes: Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. MAX 1.20 1.05 0.25 0.75 7 12.25 12.25 10.10 10.10 0.23 0.27 1.14 15 15 JEDEC Equivalent: MS-026 Drawing No. C04-085 DS39646B-page 424 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY 80-Lead Plastic Thin Quad Flatpack (PT) 12x12x1 mm Body, 1.0/0.10 mm Lead Form (TQFP) E E1 #leads=n1 p D1 D 2 1 B n CH x 45 A c L A2 A1 (F) Units Dimension Limits n p MIN INCHES NOM 80 .020 20 .043 .039 .004 .024 .039 3.5 .551 .551 .472 .472 .006 .009 .035 10 10 MAX MILLIMETERS* NOM 80 0.50 20 1.00 1.10 0.95 1.00 0.05 0.10 0.45 0.60 1.00 0 3.5 13.75 14.00 13.75 14.00 11.75 12.00 11.75 12.00 0.09 0.15 0.17 0.22 0.64 0.89 5 10 5 10 MIN Number of Pins Pitch Pins per Side n1 Overall Height A .047 .039 Molded Package Thickness A2 .037 .041 Standoff A1 .002 .006 Foot Length L .018 .030 (F) Footprint (Reference) Foot Angle 0 7 Overall Width E .541 .561 Overall Length D .541 .561 Molded Package Width E1 .463 .482 Molded Package Length D1 .463 .482 c Lead Thickness .004 .008 Lead Width B .007 .011 Pin 1 Corner Chamfer CH .025 .045 Mold Draft Angle Top 5 15 Mold Draft Angle Bottom 5 15 *Controlling Parameter Notes: Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. MAX 1.20 1.05 0.15 0.75 7 14.25 14.25 12.25 12.25 0.20 0.27 1.14 15 15 JEDEC Equivalent: MS-026 Drawing No. C04-092 2004 Microchip Technology Inc. Preliminary DS39646B-page 425 PIC18F8722 FAMILY NOTES: DS39646B-page 426 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY APPENDIX A: REVISION HISTORY APPENDIX B: Revision A (September 2004) Original data sheet for the PIC18F8722 family of devices. DEVICE DIFFERENCES The differences between the devices listed in this data sheet are shown in Table B-1. Revision B (December 2004) This revision includes updates to the Electrical Specifications in Section 28.0 "Electrical Characteristics", minor corrections to the data sheet text and information to support the following devices has been added: * PIC18F6527 * PIC18LF6527 * PIC18F6622 * PIC18LF6622 * PIC18F8527 * PIC18LF8527 * PIC18F8622 * PIC18LF8622 TABLE B-1: DEVICE DIFFERENCES (PIC18F6527/6622/6627/6722) Features Program Memory (Bytes) Program Memory (Instructions) Interrupt Sources PIC18F6527 PIC18F6622 PIC18F6627 PIC18F6722 48K 64K 96K 128K 24576 32768 49152 65536 28 28 28 28 Ports A, B, C, D, E, F, G Ports A, B, C, D, E, F, G Ports A, B, C, D, E, F, G Ports A, B, C, D, E, F, G Capture/Compare/PWM Modules 2 2 2 2 Enhanced Capture/Compare/PWM Modules 3 3 3 3 Yes Yes Yes Yes I/O Ports Parallel Communications (PSP) External Memory Bus 10-bit Analog-to-Digital Module Packages TABLE B-2: No No No No 12 input channels 12 input channels 12 input channels 12 input channels 64-pin TQFP 64-pin TQFP 64-pin TQFP 64-pin TQFP DEVICE DIFFERENCES (PIC18F8527/8622/8627/8722) Features PIC18F8527 PIC18F8622 PIC18F8627 PIC18F8722 48K 64K 96K 128K 24576 32768 49152 65536 29 29 29 29 Ports A, B, C, D, E, F, G, H, J Ports A, B, C, D, E, F, G, H, J Ports A, B, C, D, E, F, G, H, J Ports A, B, C, D, E, F, G, H, J Capture/Compare/PWM Modules 2 2 2 2 Enhanced Capture/Compare/PWM Modules 3 3 3 3 Program Memory (Bytes) Program Memory (Instructions) Interrupt Sources I/O Ports Parallel Communications (PSP) Yes Yes Yes Yes External Memory Bus Yes Yes Yes Yes 16 input channels 16 input channels 16 input channels 16 input channels 80-pin TQFP 80-pin TQFP 80-pin TQFP 80-pin TQFP 10-bit Analog-to-Digital Module Packages 2004 Microchip Technology Inc. Preliminary DS39646B-page 427 PIC18F8722 FAMILY APPENDIX C: CONVERSION CONSIDERATIONS APPENDIX D: This appendix discusses the considerations for converting from previous versions of a device to the ones listed in this data sheet. Typically, these changes are due to the differences in the process technology used. An example of this type of conversion is from a PIC16C74A to a PIC16C74B. Not Applicable DS39646B-page 428 MIGRATION FROM BASELINE TO ENHANCED DEVICES This section discusses how to migrate from a Baseline device (i.e., PIC16C5X) to an Enhanced MCU device (i.e., PIC18FXXX). The following are the list of modifications over the PIC16C5X microcontroller family: Not Currently Available Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY APPENDIX E: MIGRATION FROM MID-RANGE TO ENHANCED DEVICES A detailed discussion of the differences between the mid-range MCU devices (i.e., PIC16CXXX) and the enhanced devices (i.e., PIC18FXXX) is provided in AN716, "Migrating Designs from PIC16C74A/74B to PIC18C442". The changes discussed, while device specific, are generally applicable to all mid-range to enhanced device migrations. APPENDIX F: MIGRATION FROM HIGH-END TO ENHANCED DEVICES A detailed discussion of the migration pathway and differences between the high-end MCU devices (i.e., PIC17CXXX) and the enhanced devices (i.e., PIC18FXXX) is provided in AN726, "PIC17CXXX to PIC18CXXX Migration". This Application Note is available on our web site, www.microchip.com, as Literature Number DS00726. This Application Note is available on our web site, www.microchip.com, as Literature Number DS00716. 2004 Microchip Technology Inc. Preliminary DS39646B-page 429 PIC18F8722 FAMILY NOTES: DS39646B-page 430 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY INDEX A A/D ................................................................................... 271 A/D Converter Interrupt, Configuring ....................... 275 Acquisition Requirements ........................................ 276 ADCON0 Register .................................................... 271 ADCON1 Register .................................................... 271 ADCON2 Register .................................................... 271 ADRESH Register ............................................ 271, 274 ADRESL Register .................................................... 271 Analog Port Pins ...................................................... 158 Analog Port Pins, Configuring .................................. 278 Associated Registers ............................................... 280 Configuring the Module ............................................ 275 Conversion Clock (TAD) ........................................... 277 Conversion Status (GO/DONE Bit) .......................... 274 Conversions ............................................................. 279 Converter Characteristics ........................................ 418 Discharge ................................................................. 279 Operation in Power-Managed Modes ...................... 278 Selecting and Configuring Acquisition Time .............................................. 277 Special Event Trigger (ECCP) ................................. 192 Special Event Trigger (ECCP2) ............................... 280 Use of the ECCP2 Trigger ....................................... 280 Absolute Maximum Ratings ............................................. 377 AC (Timing) Characteristics ............................................. 398 Load Conditions for Device Timing Specifications ....................................... 399 Parameter Symbology ............................................. 398 Temperature and Voltage Specifications ................. 399 Timing Conditions .................................................... 399 Access Bank Mapping in Indexed Literal Offset Mode .................... 85 ACKSTAT ........................................................................ 236 ACKSTAT Status Flag ..................................................... 236 ADCON0 Register ............................................................ 271 GO/DONE Bit ........................................................... 274 ADCON1 Register ............................................................ 271 ADCON2 Register ............................................................ 271 ADDFSR .......................................................................... 364 ADDLW ............................................................................ 327 ADDULNK ........................................................................ 364 ADDWF ............................................................................ 327 ADDWFC ......................................................................... 328 ADRESH Register ............................................................ 271 ADRESL Register .................................................... 271, 274 Analog-to-Digital Converter. See A/D. ANDLW ............................................................................ 328 ANDWF ............................................................................ 329 Assembler MPASM Assembler .................................................. 371 Auto-Wake-up on Sync Break Character ......................... 262 B Bank Select Register (BSR) ............................................... 72 Baud Rate Generator ....................................................... 232 BC .................................................................................... 329 BCF .................................................................................. 330 BF .................................................................................... 236 BF Status Flag ................................................................. 236 2004 Microchip Technology Inc. Block Diagrams 16-Bit Byte Select Mode .......................................... 103 16-Bit Byte Write Mode ............................................ 101 16-Bit Word Write Mode .......................................... 102 A/D ........................................................................... 274 Analog Input Model .................................................. 275 Baud Rate Generator .............................................. 232 Capture Mode Operation ......................................... 181 Comparator Analog Input Model .............................. 285 Comparator I/O Operating Modes ........................... 282 Comparator Output .................................................. 284 Comparator Voltage Reference ............................... 288 Comparator Voltage Reference Output Buffer Example .................................... 289 Compare Mode Operation ....................................... 182 Device Clock .............................................................. 37 Enhanced PWM ....................................................... 193 EUSART Receive .................................................... 260 EUSART Transmit ................................................... 258 External Power-on Reset Circuit (Slow VDD Power-up) ........................................ 51 Fail-Safe Clock Monitor (FSCM) .............................. 315 Generic I/O Port Operation ...................................... 135 High/Low-Voltage Detect with External Input .................................................. 292 HSPLL ....................................................................... 33 Interrupt Logic .......................................................... 120 INTOSC and PLL ....................................................... 34 MSSP (I2C Master Mode) ........................................ 230 MSSP (I2C Mode) .................................................... 215 MSSP (SPI Mode) ................................................... 205 On-Chip Reset Circuit ................................................ 49 PIC18F6527/6622/6627/6722 ................................... 11 PIC18F8527/8622/8627/8722 ................................... 12 PORTD and PORTE (Parallel Slave Port) ............... 158 PWM Operation (Simplified) .................................... 184 Reads from Flash Program Memory ......................... 91 Single Comparator ................................................... 283 Table Read Operation ............................................... 87 Table Write Operation ............................................... 88 Table Writes to Flash Program Memory .................... 93 Timer0 in 16-Bit Mode ............................................. 162 Timer0 in 8-Bit Mode ............................................... 162 Timer1 ..................................................................... 166 Timer1 (16-Bit Read/Write Mode) ............................ 166 Timer2 ..................................................................... 172 Timer3 ..................................................................... 174 Timer3 (16-Bit Read/Write Mode) ............................ 174 Timer4 ..................................................................... 178 Watchdog Timer ...................................................... 312 BN .................................................................................... 330 BNC ................................................................................. 331 BNN ................................................................................. 331 BNOV .............................................................................. 332 BNZ ................................................................................. 332 BOR. See Brown-out Reset. BOV ................................................................................. 335 BRA ................................................................................. 333 Break Character (12-Bit) Transmit and Receive .............. 263 BRG. See Baud Rate Generator. Preliminary DS39646B-page 431 PIC18F8722 FAMILY Brown-out Reset (BOR) ..................................................... 52 Detecting .................................................................... 52 Disabling in Sleep Mode ............................................ 52 Software Enabled ....................................................... 52 BSF .................................................................................. 333 BTFSC ............................................................................. 334 BTFSS .............................................................................. 334 BTG .................................................................................. 335 BZ ..................................................................................... 336 C C Compilers MPLAB C17 ............................................................. 372 MPLAB C18 ............................................................. 372 MPLAB C30 ............................................................. 372 CALL ................................................................................ 336 CALLW ............................................................................. 365 Capture (CCP Module) ..................................................... 181 Associated Registers ............................................... 183 CCPRxH:CCPRxL Registers ................................... 181 CCPx Pin Configuration ........................................... 181 Prescaler .................................................................. 181 Software Interrupt .................................................... 181 Timer1/Timer3 Mode Selection ................................ 181 Capture (ECCP Module) .................................................. 192 Capture/Compare/PWM (CCP) ........................................ 179 Capture Mode. See Capture. CCP Mode and Timer Resources ............................ 180 CCPRxH Register .................................................... 180 CCPRxL Register ..................................................... 180 Compare Mode. See Compare. Interconnect Configurations ..................................... 180 Module Configuration ............................................... 180 Clock Sources .................................................................... 37 Selecting the 31 kHz Source ...................................... 38 Selection Using OSCCON Register ........................... 38 CLRF ................................................................................ 337 CLRWDT .......................................................................... 337 Code Examples 16 x 16 Signed Multiply Routine .............................. 118 16 x 16 Unsigned Multiply Routine .......................... 118 8 x 8 Signed Multiply Routine .................................. 117 8 x 8 Unsigned Multiply Routine .............................. 117 Changing Between Capture Prescalers ................... 181 Computed GOTO Using an Offset Value ................... 68 Data EEPROM Read ............................................... 113 Data EEPROM Refresh Routine .............................. 114 Data EEPROM Write ............................................... 113 Erasing a Flash Program Memory Row ..................... 92 Fast Register Stack .................................................... 68 How to Clear RAM (Bank 1) Using Indirect Addressing .................................. 81 Implementing a Real-Time Clock Using a Timer1 Interrupt Service ..................... 169 Initializing PORTA .................................................... 135 Initializing PORTB .................................................... 137 Initializing PORTC .................................................... 140 Initializing PORTD .................................................... 143 Initializing PORTE .................................................... 146 Initializing PORTF .................................................... 149 Initializing PORTG ................................................... 151 Initializing PORTH .................................................... 154 Initializing PORTJ .................................................... 156 Loading the SSP1BUF (SSP1SR) Register .......................................... 208 DS39646B-page 432 Reading a Flash Program Memory Word .................. 91 Saving STATUS, WREG and BSR Registers in RAM .................................... 134 Writing to Flash Program Memory ....................... 94-95 Code Protection ............................................................... 297 COMF .............................................................................. 338 Comparator ...................................................................... 281 Analog Input Connection Considerations ................ 285 Associated Registers ............................................... 285 Configuration ........................................................... 282 Effects of a Reset .................................................... 284 Interrupts ................................................................. 284 Operation ................................................................. 283 Operation During Sleep ........................................... 284 Outputs .................................................................... 283 Reference ................................................................ 283 External Signal ................................................ 283 Internal Signal .................................................. 283 Response Time ........................................................ 283 Comparator Specifications ............................................... 396 Comparator Voltage Reference ....................................... 287 Accuracy and Error .................................................. 288 Associated Registers ............................................... 289 Configuring .............................................................. 287 Connection Considerations ...................................... 288 Effects of a Reset .................................................... 288 Operation During Sleep ........................................... 288 Comparator Voltage Reference Specifications ......................................... 396 Compare (CCP Module) .................................................. 182 Associated Registers ............................................... 183 CCPRx Registers ..................................................... 182 Pin Configuration ..................................................... 182 Software Interrupt .................................................... 182 Special Event Trigger .............................................. 182 Timer1/Timer3 Mode Selection ................................ 182 Compare (CCP Modules) Special Event Trigger .............................................. 175 Compare (ECCP Module) ................................................ 192 Special Event Trigger .............................................. 192 Compare (ECCP2 Module) Special Event Trigger .............................................. 280 Computed GOTO ............................................................... 68 Configuration Bits ............................................................ 297 Configuration Register Protection .................................... 320 Context Saving During Interrupts ..................................... 134 Conversion Considerations .............................................. 428 CPFSEQ .......................................................................... 338 CPFSGT .......................................................................... 339 CPFSLT ........................................................................... 339 Crystal Oscillator/Ceramic Resonator ................................ 31 D Data Addressing Modes .................................................... 81 Comparing Addressing Modes with the Extended Instruction Set Enabled ............... 84 Direct ......................................................................... 81 Indexed Literal Offset ................................................ 83 Instructions Affected .......................................... 83 Indirect ....................................................................... 81 Inherent and Literal .................................................... 81 Data EEPROM Code Protection ....................................................... 320 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY Data EEPROM Memory ................................................... 111 Associated Registers ............................................... 115 EEADR and EEADRH Registers ............................. 111 EECON1 and EECON2 Registers ........................... 111 Operation During Code-Protect ............................... 114 Protection Against Spurious Write ........................... 114 Reading .................................................................... 113 Using ........................................................................ 114 Write Verify .............................................................. 113 Writing ...................................................................... 113 Data Memory ..................................................................... 72 Access Bank .............................................................. 74 and the Extended Instruction Set ............................... 83 Bank Select Register (BSR) ....................................... 72 General Purpose Registers ........................................ 74 Map for PIC18F8722 Family ...................................... 73 Special Function Registers ........................................ 75 DAW ................................................................................. 340 DC and AC Characteristics Graphs and Tables .................................................. 421 DC Characteristics ........................................................... 393 Power-Down and Supply Current ............................ 381 Supply Voltage ......................................................... 380 DCFSNZ .......................................................................... 341 DECF ............................................................................... 340 DECFSZ ........................................................................... 341 Demonstration Boards PICDEM 1 ................................................................ 374 PICDEM 17 .............................................................. 375 PICDEM 18R ........................................................... 375 PICDEM 2 Plus ........................................................ 374 PICDEM 3 ................................................................ 374 PICDEM 4 ................................................................ 374 PICDEM LIN ............................................................ 375 PICDEM USB ........................................................... 375 PICDEM.net Internet/Ethernet ................................. 374 Development Support ...................................................... 371 Device Differences ........................................................... 427 Device Overview .................................................................. 7 Details on Individual Family Members ......................... 9 Features (table) ...................................................... 9, 10 New Core Features ...................................................... 7 Device Reset Timers .......................................................... 53 Oscillator Start-up Timer (OST) ................................. 53 PLL Lock Time-out ..................................................... 53 Power-up Timer (PWRT) ........................................... 53 Time-out Sequence .................................................... 53 Direct Addressing ............................................................... 82 E ECCP Capture and Compare Modes .................................. 192 Standard PWM Mode ............................................... 192 Effect on Standard PIC Instructions ................................. 368 Effects of Power-Managed Modes on Various Clock Sources ............................................... 40 Electrical Characteristics .................................................. 377 Enhanced Capture/Compare/PWM (ECCP) .................... 187 and Program Memory Modes .................................. 188 Capture Mode. See Capture (ECCP Module). Outputs and Configuration ....................................... 188 Pin Configurations for ECCP1 ................................. 189 Pin Configurations for ECCP2 ................................. 190 Pin Configurations for ECCP3 ................................. 191 PWM Mode. See PWM (ECCP Module). Timer Resources ...................................................... 192 2004 Microchip Technology Inc. Enhanced PWM Mode. See PWM (ECCP Module). ....... 192 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART). See EUSART. Equations A/D Acquisition Time ............................................... 276 A/D Minimum Charging Time .................................. 276 A/D, Calculating the Minimum Required Acquisition Time ............................... 276 Errata ................................................................................... 5 EUSART Asynchronous Mode ................................................ 257 12-Bit Break Transmit and Receive ................. 263 Associated Registers, Receive ........................ 261 Associated Registers, Transmit ....................... 259 Auto-Wake-up on Sync Break ......................... 262 Receiver .......................................................... 260 Setting up 9-Bit Mode with Address Detect ........................................ 260 Transmitter ...................................................... 257 Baud Rate Generator Operation in Power-Managed Modes ...................................................... 251 Baud Rate Generator (BRG) ................................... 251 Associated Registers ....................................... 252 Auto-Baud Rate Detect .................................... 255 Baud Rate Error, Calculating ........................... 252 Baud Rates, Asynchronous Modes ................. 253 High Baud Rate Select (BRGH Bit) ................. 251 Sampling ......................................................... 251 Synchronous Master Mode ...................................... 264 Associated Registers, Receive ........................ 267 Associated Registers, Transmit ....................... 265 Reception ........................................................ 266 Transmission ................................................... 264 Synchronous Slave Mode ........................................ 268 Associated Registers, Receive ........................ 269 Associated Registers, Transmit ....................... 268 Reception ........................................................ 269 Transmission ................................................... 268 Evaluation and Programming Tools ................................. 375 Extended Instruction Set ADDFSR .................................................................. 364 ADDULNK ............................................................... 364 CALLW .................................................................... 365 MOVSF .................................................................... 365 MOVSS .................................................................... 366 PUSHL ..................................................................... 366 SUBFSR .................................................................. 367 SUBULNK ................................................................ 367 Extended Microcontroller Mode ....................................... 100 External Clock Input ........................................................... 32 External Memory Bus ........................................................ 97 16-Bit Byte Select Mode .......................................... 103 16-Bit Byte Write Mode ............................................ 101 16-Bit Data Width Modes ......................................... 100 16-Bit Mode Timing ................................................. 104 16-Bit Word Write Mode .......................................... 102 8-Bit Data Width Modes ........................................... 106 8-Bit Mode Timing ................................................... 107 I/O Port Functions ...................................................... 97 Operation in Power-Managed Modes .............................................................. 109 Preliminary DS39646B-page 433 PIC18F8722 FAMILY F Fail-Safe Clock Monitor ............................................ 297, 315 Exiting Operation ..................................................... 315 Interrupts in Power-Managed Modes ....................... 316 POR or Wake from Sleep ........................................ 316 WDT During Oscillator Failure ................................. 315 Fast Register Stack ............................................................ 68 Firmware Instructions ....................................................... 321 Flash Program Memory ...................................................... 87 Associated Registers ................................................. 95 Control Registers ....................................................... 88 EECON1 and EECON2 ..................................... 88 TABLAT (Table Latch) Register ......................... 90 TBLPTR (Table Pointer) Register ...................... 90 Erase Sequence ........................................................ 92 Erasing ....................................................................... 92 Operation During Code-Protect ................................. 95 Reading ...................................................................... 91 Table Pointer Boundaries Based on Operation ........................ 90 Table Pointer Boundaries .......................................... 90 Table Reads and Table Writes .................................. 87 Write Sequence ......................................................... 93 Writing To ................................................................... 93 Protection Against Spurious Writes ................... 95 Unexpected Termination .................................... 95 Write Verify ........................................................ 95 FSCM. See Fail-Safe Clock Monitor. G General Call Address Support ......................................... 229 GOTO ............................................................................... 342 H Hardware Multiplier .......................................................... 117 Introduction .............................................................. 117 Operation ................................................................. 117 Performance Comparison ........................................ 117 High/Low-Voltage Detect ................................................. 291 Applications .............................................................. 294 Associated Registers ............................................... 295 Characteristics ......................................................... 397 Current Consumption ............................................... 293 Effects of a Reset ..................................................... 295 Operation ................................................................. 292 During Sleep .................................................... 295 Setup ........................................................................ 293 Start-up Time ........................................................... 293 Typical Application ................................................... 294 HLVD. See High/Low-Voltage Detect. I I/O Ports ........................................................................... 135 I2C Mode (MSSP) Acknowledge Sequence Timing ............................... 239 Associated Registers ............................................... 245 Baud Rate Generator ............................................... 232 Bus Collision During a Repeated Start Condition .................. 243 During a Stop Condition ................................... 244 Clock Arbitration ....................................................... 233 DS39646B-page 434 Clock Stretching ....................................................... 225 10-Bit Slave Receive Mode (SEN = 1) ............ 225 10-Bit Slave Transmit Mode ............................ 225 7-Bit Slave Receive Mode (SEN = 1) .............. 225 7-Bit Slave Transmit Mode .............................. 225 Clock Synchronization and the CKP bit ................... 226 Effects of a Reset .................................................... 240 General Call Address Support ................................. 229 I2C Clock Rate w/BRG ............................................. 232 Master Mode ............................................................ 230 Operation ......................................................... 231 Reception ........................................................ 236 Repeated Start Condition Timing .................... 235 Start Condition Timing ..................................... 234 Transmission ................................................... 236 Multi-Master Communication, Bus Collision and Arbitration ................................................. 240 Multi-Master Mode ................................................... 240 Operation ................................................................. 219 Read/Write Bit Information (R/W Bit) ............... 219, 220 Registers ................................................................. 215 Serial Clock (RC3/SCKx/SCLx) ............................... 220 Slave Mode .............................................................. 219 Addressing ....................................................... 219 Reception ........................................................ 220 Transmission ................................................... 220 Sleep Operation ....................................................... 240 Stop Condition Timing ............................................. 239 ID Locations ............................................................. 297, 320 INCF ................................................................................ 342 INCFSZ ............................................................................ 343 In-Circuit Debugger .......................................................... 320 In-Circuit Serial Programming (ICSP) ...................... 297, 320 Indexed Literal Offset Addressing and Standard PIC18 Instructions ............................. 368 Indexed Literal Offset Mode ............................................. 368 Indirect Addressing ............................................................ 82 INFSNZ ............................................................................ 343 Initialization Conditions for all Registers ...................... 57-61 Instruction Cycle ................................................................ 69 Clocking Scheme ....................................................... 69 Instruction Flow/Pipelining ................................................. 69 Instruction Set .................................................................. 321 ADDLW .................................................................... 327 ADDWF .................................................................... 327 ADDWF (Indexed Literal Offset Mode) .................... 369 ADDWFC ................................................................. 328 ANDLW .................................................................... 328 ANDWF .................................................................... 329 BC ............................................................................ 329 BCF ......................................................................... 330 BN ............................................................................ 330 BNC ......................................................................... 331 BNN ......................................................................... 331 BNOV ...................................................................... 332 BNZ ......................................................................... 332 BOV ......................................................................... 335 BRA ......................................................................... 333 BSF .......................................................................... 333 BSF (Indexed Literal Offset Mode) .......................... 369 BTFSC ..................................................................... 334 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY BTFSS ..................................................................... 334 BTG .......................................................................... 335 BZ ............................................................................ 336 CALL ........................................................................ 336 CLRF ........................................................................ 337 CLRWDT .................................................................. 337 COMF ...................................................................... 338 CPFSEQ .................................................................. 338 CPFSGT .................................................................. 339 CPFSLT ................................................................... 339 DAW ......................................................................... 340 DCFSNZ .................................................................. 341 DECF ....................................................................... 340 DECFSZ ................................................................... 341 Extended Instructions .............................................. 363 Considerations when Enabling ........................ 368 Syntax .............................................................. 363 Use with MPLAB IDE Tools ............................. 370 General Format ........................................................ 323 GOTO ...................................................................... 342 INCF ......................................................................... 342 INCFSZ .................................................................... 343 INFSNZ .................................................................... 343 IORLW ..................................................................... 344 IORWF ..................................................................... 344 LFSR ........................................................................ 345 MOVF ....................................................................... 345 MOVFF .................................................................... 346 MOVLB .................................................................... 346 MOVLW ................................................................... 347 MOVWF ................................................................... 347 MULLW .................................................................... 348 MULWF .................................................................... 348 NEGF ....................................................................... 349 NOP ......................................................................... 349 POP ......................................................................... 350 PUSH ....................................................................... 350 RCALL ..................................................................... 351 RESET ..................................................................... 351 RETFIE .................................................................... 352 RETLW .................................................................... 352 RETURN .................................................................. 353 RLCF ........................................................................ 353 RLNCF ..................................................................... 354 RRCF ....................................................................... 354 RRNCF .................................................................... 355 SETF ........................................................................ 355 SETF (Indexed Literal Offset Mode) ........................ 369 SLEEP ..................................................................... 356 Standard Instructions ............................................... 321 SUBFWB .................................................................. 356 SUBLW .................................................................... 357 SUBWF .................................................................... 357 SUBWFB .................................................................. 358 SWAPF .................................................................... 358 TBLRD ..................................................................... 359 TBLWT ..................................................................... 360 TSTFSZ ................................................................... 361 XORLW .................................................................... 361 XORWF .................................................................... 362 INTCON Register RBIF Bit .................................................................... 137 INTCON Registers ........................................................... 121 Inter-Integrated Circuit. See I2C. 2004 Microchip Technology Inc. Internal Oscillator Block ..................................................... 34 Adjustment ................................................................. 34 INTIO Modes ............................................................. 34 INTOSC Frequency Drift ........................................... 35 INTOSC Output Frequency ....................................... 34 OSCTUNE Register ................................................... 34 PLL in INTOSC Modes .............................................. 35 Internal RC Oscillator Use with WDT .......................................................... 312 Interrupt Sources ............................................................. 297 A/D Conversion Complete ....................................... 275 Capture Complete (CCP) ........................................ 181 Compare Complete (CCP) ...................................... 182 Interrupt-on-Change (RB7:RB4) .............................. 137 INTn Pin ................................................................... 134 PORTB, Interrupt-on-Change .................................. 134 TMR0 ....................................................................... 134 TMR0 Overflow ........................................................ 163 TMR1 Overflow ........................................................ 165 TMR2 to PR2 Match (PWM) ............................ 184, 192 TMR3 Overflow ................................................ 173, 175 TMR4 to PR4 Match ................................................ 178 TMR4 to PR4 Match (PWM) .................................... 177 Interrupts ......................................................................... 119 Interrupts, Flag Bits Interrupt-on-Change (RB7:RB4) Flag (RBIF Bit) ................................................. 137 INTOSC, INTRC. See Internal Oscillator Block. IORLW ............................................................................. 344 IORWF ............................................................................. 344 IPR Registers ................................................................... 130 K Key Features Easy Migration ............................................................. 8 Expanded Memory ...................................................... 7 External Memory Interface .......................................... 8 L LFSR ............................................................................... 345 Low-Voltage ICSP Programming. See Single-Supply ICSP Programming. M Master Clear (MCLR) ......................................................... 51 Master Synchronous Serial Port (MSSP). See MSSP. Memory Mode Memory Access ............................................... 64 Memory Maps for PIC18F8722 Family Program Memory Modes ........................................... 65 Memory Organization ........................................................ 63 Data Memory ............................................................. 72 Program Memory ....................................................... 63 Modes ................................................................ 63 Memory Programming Requirements .............................. 395 Microcontroller Mode ....................................................... 100 Microprocessor Mode ...................................................... 100 Microprocessor with Boot Block Mode ............................. 100 Migration from Baseline to Enhanced Devices ................................................... 428 Migration from High-End to Enhanced Devices ................................................... 429 Migration from Mid-Range to Enhanced Devices ................................................... 429 Preliminary DS39646B-page 435 PIC18F8722 FAMILY MOVF ............................................................................... 345 MOVFF ............................................................................. 346 MOVLB ............................................................................. 346 MOVLW ............................................................................ 347 MOVSF ............................................................................ 365 MOVSS ............................................................................ 366 MOVWF ........................................................................... 347 MPLAB ASM30 Assembler, Linker, Librarian .................. 372 MPLAB ICD 2 In-Circuit Debugger ................................... 373 MPLAB ICE 2000 High-Performance Universal In-Circuit Emulator ................................... 373 MPLAB ICE 4000 High-Performance Universal In-Circuit Emulator ................................... 373 MPLAB Integrated Development Environment Software .............................................. 371 MPLAB PM3 Device Programmer .................................... 373 MPLINK Object Linker/MPLIB Object Librarian ............... 372 MSSP ACK Pulse ........................................................ 219, 220 Control Registers (general) ...................................... 205 I2C Mode. See I2C Mode. Module Overview ..................................................... 205 SPI Master/Slave Connection .................................. 209 TMR4 Output for Clock Shift .................................... 178 MULLW ............................................................................ 348 MULWF ............................................................................ 348 N NEGF ............................................................................... 349 NOP ................................................................................. 349 O Opcode Field Descriptions ............................................... 322 Oscillator Configuration ...................................................... 31 EC .............................................................................. 31 ECIO .......................................................................... 31 HS .............................................................................. 31 HSPLL ........................................................................ 31 Internal Oscillator Block ............................................. 34 INTIO1 ....................................................................... 31 INTIO2 ....................................................................... 31 LP ............................................................................... 31 RC .............................................................................. 31 RCIO .......................................................................... 31 XT .............................................................................. 31 Oscillator Selection .......................................................... 297 Oscillator Start-up Timer (OST) ................................... 40, 53 Oscillator Switching ............................................................ 37 Oscillator Transitions .......................................................... 38 Oscillator, Timer1 ..................................................... 165, 175 Oscillator, Timer3 ............................................................. 173 P Packaging ........................................................................ 423 Details ...................................................................... 424 Marking .................................................................... 423 Parallel Slave Port (PSP) ................................................. 158 Associated Registers ............................................... 160 RE0/RD Pin .............................................................. 158 RE1/WR Pin ............................................................. 158 RE2/CS Pin .............................................................. 158 Select (PSPMODE Bit) ............................................ 158 PICkit 1 Flash Starter Kit .................................................. 375 PICSTART Plus Development Programmer .................... 374 PIE Registers ................................................................... 127 DS39646B-page 436 Pin Functions AVDD .......................................................................... 30 AVDD .......................................................................... 20 AVSS .......................................................................... 30 AVSS .......................................................................... 20 OSC1/CLKI/RA7 .................................................. 13, 21 OSC2/CLKO/RA6 ................................................ 13, 21 RA0/AN0 .............................................................. 14, 22 RA1/AN1 .............................................................. 14, 22 RA2/AN2/VREF- ................................................... 14, 22 RA3/AN3/VREF+ .................................................. 14, 22 RA4/T0CKI .......................................................... 14, 22 RA5/AN4/HLVDIN ................................................ 14, 22 RB0/INT0/FLT0 .................................................... 15, 23 RB1/INT1 ............................................................. 15, 23 RB2/INT2 ............................................................. 15, 23 RB3/INT3 ................................................................... 15 RB3/INT3/ECCP2/P2A .............................................. 23 RB4/KBI0 ............................................................. 15, 23 RB5/KBI1/PGM .................................................... 15, 23 RB6/KBI2/PGC .................................................... 15, 23 RB7/KBI3/PGD .................................................... 15, 23 RC0/T1OSO/T13CKI ........................................... 16, 24 RC1/T1OSI/ECCP2/P2A ..................................... 16, 24 RC2/ECCP1/P1A ................................................. 16, 24 RC3/SCK1/SCL1 ................................................. 16, 24 RC4/SDI1/SDA1 .................................................. 16, 24 RC5/SDO1 ........................................................... 16, 24 RC6/TX1/CK1 ...................................................... 16, 24 RC7/RX1/DT1 ...................................................... 16, 24 RD0/AD0/PSP0 ......................................................... 25 RD0/PSP0 ................................................................. 17 RD1/AD1/PSP1 ......................................................... 25 RD1/PSP1 ................................................................. 17 RD2/AD2/PSP2 ......................................................... 25 RD2/PSP2 ................................................................. 17 RD3/AD3/PSP3 ......................................................... 25 RD3/PSP3 ................................................................. 17 RD4/AD4/PSP4/SDO2 ............................................... 25 RD4/PSP4/SDO2 ....................................................... 17 RD5/AD5/PSP5/SDI2/SDA2 ...................................... 25 RD5/PSP5/SDI2/SDA2 .............................................. 17 RD6/AD6/PSP6/SCK2/SCL2 ..................................... 25 RD6/PSP6/SCK2/SCL2 ............................................. 17 RD7/AD7/PSP7/SS2 .................................................. 25 RD7/PSP7/SS2 ......................................................... 17 RE0/AD8/RD/P2D ...................................................... 26 RE0/RD/P2D .............................................................. 18 RE1/AD9/WR/P2C ..................................................... 26 RE1/WR/P2C ............................................................. 18 RE2/AD10/CS/P2B .................................................... 26 RE2/CS/P2D .............................................................. 18 RE3/AD11/P3C .......................................................... 26 RE3/P3C .................................................................... 18 RE4/AD12/P3B .......................................................... 26 RE4/P3B .................................................................... 18 RE5/AD13/P1C .......................................................... 26 RE5/P1C .................................................................... 18 RE6/AD14/P1B .......................................................... 26 RE6/P1B .................................................................... 18 RE7/AD15/ECCP2/P2A ............................................. 26 RE7/ECCP2/P2A ....................................................... 18 RF0/AN5 .............................................................. 19, 27 RF1/AN6/C2OUT ................................................. 19, 27 RF2/AN7/C1OUT ................................................. 19, 27 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY RF3/AN8 .............................................................. 19, 27 RF4/AN9 .............................................................. 19, 27 RF5/AN10/CVREF ................................................ 19, 27 RF6/AN11 ............................................................ 19, 27 RF7/SS1 .............................................................. 19, 27 RG0/ECCP3/P3A ................................................. 20, 28 RG1/TX2/CK2 ...................................................... 20, 28 RG2/RX2/DT2 ...................................................... 20, 28 RG3/CCP4/P3D ................................................... 20, 28 RG4/CCP5/P1D ................................................... 20, 28 RG5 ...................................................................... 20, 28 RG5/MCLR/VPP ................................................... 13, 21 RH0/A16 .................................................................... 29 RH1/A17 .................................................................... 29 RH2/A18 .................................................................... 29 RH3/A19 .................................................................... 29 RH4/AN12/P3C .......................................................... 29 RH5/AN13/P3B .......................................................... 29 RH6/AN14/P1C .......................................................... 29 RH7/AN15/P1B .......................................................... 29 RJ0/ALE ..................................................................... 30 RJ1/OE ...................................................................... 30 RJ2/WRL .................................................................... 30 RJ3/WRH ................................................................... 30 RJ4/BA0 ..................................................................... 30 RJ5/CE ....................................................................... 30 RJ6/LB ....................................................................... 30 RJ7/UB ....................................................................... 30 VDD ............................................................................ 30 VDD ............................................................................ 20 VSS ............................................................................. 30 VSS ............................................................................. 20 Pinout I/O Descriptions PIC18F6527/6622/6627/6722 .................................... 13 PIC18F8527/8622/8627/8722 .................................... 21 PIR Registers ................................................................... 124 PLL Frequency Multiplier ................................................... 33 HSPLL Oscillator Mode .............................................. 33 Use with INTOSC ....................................................... 33 POP ................................................................................. 350 POR. See Power-on Reset. PORTA Associated Registers ............................................... 136 Functions ................................................................. 136 LATA Register .......................................................... 135 PORTA Register ...................................................... 135 TRISA Register ........................................................ 135 PORTB Associated Registers ............................................... 139 Functions ................................................................. 138 LATB Register .......................................................... 137 PORTB Register ...................................................... 137 RB7:RB4 Interrupt-on-Change Flag (RBIF Bit) ................................................. 137 TRISB Register ........................................................ 137 PORTC Associated Registers ............................................... 142 Functions ................................................................. 141 LATC Register ......................................................... 140 PORTC Register ...................................................... 140 RC3/SCKx/SCLx Pin ................................................ 220 TRISC Register ........................................................ 140 2004 Microchip Technology Inc. PORTD ............................................................................ 158 Associated Registers ............................................... 145 Functions ................................................................. 144 LATD Register ......................................................... 143 PORTD Register ...................................................... 143 TRISD Register ....................................................... 143 PORTE Analog Port Pins ...................................................... 158 Associated Registers ............................................... 148 Functions ................................................................. 147 LATE Register ......................................................... 146 PORTE Register ...................................................... 146 PSP Mode Select (PSPMODE Bit) .......................... 158 RE0/RD Pin ............................................................. 158 RE1/WR Pin ............................................................ 158 RE2/CS Pin ............................................................. 158 TRISE Register ........................................................ 146 PORTF Associated Registers ............................................... 150 Functions ................................................................. 150 LATF Register ......................................................... 149 PORTF Register ...................................................... 149 TRISF Register ........................................................ 149 PORTG Associated Registers ............................................... 153 Functions ................................................................. 152 LATG Register ......................................................... 151 PORTG Register ..................................................... 151 TRISG Register ....................................................... 151 PORTH Associated Registers ............................................... 155 Functions ................................................................. 155 LATH Register ......................................................... 154 PORTH Register ...................................................... 154 TRISH Register ....................................................... 154 PORTJ Associated Registers ............................................... 157 Functions ................................................................. 157 LATJ Register .......................................................... 156 PORTJ Register ...................................................... 156 TRISJ Register ........................................................ 156 Power-Managed Modes ..................................................... 41 and A/D Operation ................................................... 278 and EUSART Operation .......................................... 251 and Multiple Sleep Commands .................................. 42 and PWM Operation ................................................ 203 and SPI Operation ................................................... 213 Associated Registers ............................................... 109 Clock Transitions and Status Indicators .................... 42 Effects on Clock Sources .......................................... 40 Entering ..................................................................... 41 Exiting Idle and Sleep Modes .................................... 47 by Interrupt ........................................................ 47 by Reset ............................................................ 47 by WDT Time-out .............................................. 47 Without a Start-up Delay ................................... 48 Idle Modes ................................................................. 45 PRI_IDLE .......................................................... 46 RC_IDLE ........................................................... 47 SEC_IDLE ......................................................... 46 Preliminary DS39646B-page 437 PIC18F8722 FAMILY Run Modes ................................................................. 42 PRI_RUN ........................................................... 42 RC_RUN ............................................................ 43 SEC_RUN .......................................................... 42 Selecting .................................................................... 41 Sleep Mode ................................................................ 45 Summary (table) ........................................................ 41 Power-on Reset (POR) ...................................................... 51 Power-up Timer (PWRT) ........................................... 53 Time-out Sequence .................................................... 53 Power-up Delays ................................................................ 40 Power-up Timer (PWRT) .................................................... 40 Prescaler Timer2 ...................................................................... 193 Prescaler, Timer0 ............................................................. 163 Prescaler, Timer2 ............................................................. 185 PRI_IDLE Mode ................................................................. 46 PRI_RUN Mode ................................................................. 42 PRO MATE II Universal Device Programmer .................. 373 Program Counter ................................................................ 66 PCL, PCH and PCU Registers ................................... 66 PCLATH and PCLATU Registers .............................. 66 Program Memory and Extended Instruction Set ..................................... 85 Code Protection ....................................................... 318 Extended Microcontroller Mode ................................. 63 Instructions ................................................................. 70 Two-Word .......................................................... 71 Interrupt Vector .......................................................... 63 Look-up Tables .......................................................... 68 Map and Stack (diagram) ........................................... 64 Microcontroller Mode ................................................. 63 Microprocessor Mode ................................................ 63 Microprocessor with Boot Block Mode ....................... 63 Reset Vector .............................................................. 63 Program Verification and Code Protection ....................... 317 Associated Registers ............................................... 318 Programming, Device Instructions ................................... 321 PSP.See Parallel Slave Port. Pulse-Width Modulation. See PWM (CCP Module) and PWM (ECCP Module). PUSH ............................................................................... 350 PUSH and POP Instructions .............................................. 67 PUSHL ............................................................................. 366 PWM (CCP Module) Associated Registers ............................................... 186 Duty Cycle ................................................................ 184 Example Frequencies/Resolutions .......................... 185 Period ....................................................................... 184 Setup for PWM Operation ........................................ 185 TMR2 to PR2 Match ................................................ 184 TMR4 to PR4 Match ................................................ 177 PWM (ECCP Module) ...................................................... 192 Associated Registers ............................................... 204 CCPR1H:CCPR1L Registers ................................... 192 Direction Change in Full-Bridge Output Mode .................................................... 198 Duty Cycle ................................................................ 193 Effects of a Reset ..................................................... 203 Enhanced PWM Auto-Shutdown ............................. 200 Example Frequencies/Resolutions .......................... 193 Full-Bridge Application Example .............................. 198 Full-Bridge Mode ...................................................... 197 Half-Bridge Mode ..................................................... 196 DS39646B-page 438 Half-Bridge Output Mode Applications Example ...................................... 196 Operation in Power-Managed Modes ...................... 203 Operation with Fail-Safe Clock Monitor ................... 203 Output Configurations .............................................. 194 Output Relationships (Active-High) .......................... 194 Output Relationships (Active-Low) .......................... 195 Period ...................................................................... 192 Programmable Dead-Band Delay ............................ 200 Setup for PWM Operation ........................................ 203 Start-up Considerations ........................................... 202 TMR2 to PR2 Match ................................................ 192 Q Q Clock .................................................................... 185, 193 R RAM. See Data Memory. RC Oscillator ...................................................................... 33 RCIO Oscillator Mode ................................................ 33 RC_IDLE Mode .................................................................. 47 RC_RUN Mode .................................................................. 43 RCALL ............................................................................. 351 RCON Register Bit Status During Initialization .................................... 56 Register File ....................................................................... 74 Registers ADCON0 (A/D Control 0) ......................................... 271 ADCON1 (A/D Control 1) ......................................... 272 ADCON2 (A/D Control 2) ......................................... 273 BAUDCONx (Baud Rate Control) ............................ 250 CCPxCON (Capture/Compare/PWM Control) ................... 179 CCPxCON (Enhanced Capture/Compare/PWM Control) .................... 187 CMCON (Comparator Control) ................................ 281 CONFIG1H (Configuration 1 High) .......................... 299 CONFIG2H (Configuration 2 High) .......................... 301 CONFIG2L (Configuration 2 Low) ........................... 300 CONFIG3H (Configuration 3 High) .......................... 303 CONFIG3L (Configuration 3 Low) ........................... 302 CONFIG4L (Configuration 4 Low) ........................... 304 CONFIG5H (Configuration 5 High) .......................... 306 CONFIG5L (Configuration 5 Low) ........................... 305 CONFIG6H (Configuration 6 High) .......................... 308 CONFIG6L (Configuration 6 Low) ........................... 307 CONFIG7H (Configuration 7 High) .......................... 310 CONFIG7L (Configuration 7 Low) ........................... 309 CVRCON (Comparator Voltage Reference Control) .......................................... 287 DEVID1 (Device ID 1) .............................................. 311 DEVID2 (Device ID 2) .............................................. 311 ECCPxAS (ECCP Auto-Shutdown Control) .................................. 201 ECCPxDEL (Enhanced PWM Configuration) ........................................ 200 EECON1 (Data EEPROM Control 1) ....................... 112 EECON1 (EEPROM Control 1) ................................. 89 HLVDCON (High/Low-Voltage Detect Control) ................................................ 291 INTCON (Interrupt Control) ...................................... 121 INTCON2 (Interrupt Control 2) ................................. 122 INTCON3 (Interrupt Control 3) ................................. 123 IPR1 (Peripheral Interrupt Priority 1) ....................... 130 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY IPR2 (Peripheral Interrupt Priority 2) ........................ 131 IPR3 (Peripheral Interrupt Priority 3) ........................ 132 MEMCON (External Memory Bus Control) ....................................................... 98 OSCCON (Oscillator Control) .................................... 39 OSCTUNE (Oscillator Tuning) ................................... 35 PIE1 (Peripheral Interrupt Enable 1) ........................ 127 PIE2 (Peripheral Interrupt Enable 2) ........................ 128 PIE3 (Peripheral Interrupt Enable 3) ........................ 129 PIR1 (Peripheral Interrupt Request (Flag) 1) ............................................. 124 PIR2 (Peripheral Interrupt Request (Flag) 2) ............................................. 125 PIR3 (Peripheral Interrupt Request (Flag) 3) ............................................. 126 PSPCON (Parallel Slave Port Control) .................................................... 159 RCON (Reset Control) ....................................... 50, 133 RCSTAx (Receive Status and Control) .................... 249 SSPxCON1 (MSSPx Control 1, I2C Mode) ........................................................ 217 SSPxCON1 (MSSPx Control 1, SPI Mode) ........................................................ 207 SSPxCON2 (MSSPx Control 2, I2C Mode) ........................................................ 218 SSPxSTAT (MSSPx Status, I2C Mode) ....................................................... 216 SSPxSTAT (MSSPx Status, SPI Mode) ........................................................ 206 STATUS ..................................................................... 80 STKPTR (Stack Pointer) ............................................ 67 T0CON (Timer0 Control) .......................................... 161 T1CON (Timer1 Control) .......................................... 165 T2CON (Timer2 Control) .......................................... 171 T3CON (Timer3 Control) .......................................... 173 T4CON (Timer 4 Control) ......................................... 177 TXSTAx (Transmit Status and Control) ................... 248 WDTCON (Watchdog Timer Control) ...................... 313 RESET ............................................................................. 351 Reset State of Registers .................................................... 56 Resets ........................................................................ 49, 297 Brown-out Reset (BOR) ........................................... 297 Oscillator Start-up Timer (OST) ............................... 297 Power-on Reset (POR) ............................................ 297 Power-up Timer (PWRT) ......................................... 297 RETFIE ............................................................................ 352 RETLW ............................................................................ 352 RETURN .......................................................................... 353 Return Address Stack ........................................................ 66 Return Stack Pointer (STKPTR) ........................................ 67 Revision History ............................................................... 427 RLCF ................................................................................ 353 RLNCF ............................................................................. 354 RRCF ............................................................................... 354 RRNCF ............................................................................ 355 S SCKx ................................................................................ 205 SDIx ................................................................................. 205 SDOx ............................................................................... 205 SEC_IDLE Mode ................................................................ 46 SEC_RUN Mode ................................................................ 42 Serial Clock, SCKx ........................................................... 205 Serial Data In (SDIx) ........................................................ 205 2004 Microchip Technology Inc. Serial Data Out (SDOx) ................................................... 205 Serial Peripheral Interface. See SPI Mode. SETF ............................................................................... 355 Slave Select (SSx) ........................................................... 205 Slave Select Synchronization .......................................... 211 SLEEP ............................................................................. 356 Sleep OSC1 and OSC2 Pin States ...................................... 40 Sleep Mode ....................................................................... 45 Software Simulator (MPLAB SIM) ................................... 372 Software Simulator (MPLAB SIM30) ....................................................... 372 Special Event Trigger. See Compare (CCP Mode). Special Event Trigger. See Compare (ECCP Module). Special Features of the CPU ........................................... 297 Special Function Registers ................................................ 75 Map ............................................................................ 75 SPI Mode (MSSP) ........................................................... 205 Associated Registers ............................................... 214 Bus Mode Compatibility ........................................... 213 Clock Speed, Interactions ........................................ 213 Effects of a Reset .................................................... 213 Enabling SPI I/O ...................................................... 209 Master Mode ............................................................ 210 Master/Slave Connection ........................................ 209 Operation ................................................................. 208 Operation in Power-Managed Modes .................................. 213 Serial Clock ............................................................. 205 Serial Data In ........................................................... 205 Serial Data Out ........................................................ 205 Slave Mode .............................................................. 211 Slave Select ............................................................. 205 Slave Select Synchronization .................................. 211 SPI Clock ................................................................. 210 SSPxBUF Register .................................................. 210 SSPxSR Register .................................................... 210 Typical Connection .................................................. 209 SSPOV ............................................................................ 236 SSPOV Status Flag ......................................................... 236 SSPxSTAT Register R/W Bit ............................................................ 219, 220 SSx .................................................................................. 205 Stack Full/Underflow Resets .............................................. 68 SUBFSR .......................................................................... 367 SUBFWB ......................................................................... 356 SUBLW ............................................................................ 357 SUBULNK ........................................................................ 367 SUBWF ............................................................................ 357 SUBWFB ......................................................................... 358 SWAPF ............................................................................ 358 T Table Pointer Operations (table) ........................................ 90 Table Reads/Table Writes ................................................. 68 TBLRD ............................................................................. 359 TBLWT ............................................................................ 360 Time-out in Various Situations (table) ................................ 53 Preliminary DS39646B-page 439 PIC18F8722 FAMILY Timer0 .............................................................................. 161 Associated Registers ............................................... 163 Operation ................................................................. 162 Overflow Interrupt .................................................... 163 Prescaler .................................................................. 163 Prescaler Assignment (PSA Bit) .............................. 163 Prescaler Select (T0PS2:T0PS0 Bits) ..................... 163 Prescaler. See Prescaler, Timer0. Reads and Writes in 16-Bit Mode ............................ 162 Source Edge Select (T0SE Bit) ................................ 162 Source Select (T0CS Bit) ......................................... 162 Switching Prescaler Assignment .............................. 163 Timer1 .............................................................................. 165 16-Bit Read/Write Mode ........................................... 167 Associated Registers ............................................... 169 Interrupt .................................................................... 168 Operation ................................................................. 166 Oscillator .......................................................... 165, 167 Layout Considerations ..................................... 168 Overflow Interrupt .................................................... 165 Resetting, Using the CCP Special Event Trigger ....................................... 168 Special Event Trigger (ECCP) ................................. 192 TMR1H Register ...................................................... 165 TMR1L Register ....................................................... 165 Use as a Real-Time Clock ....................................... 168 Timer2 .............................................................................. 171 Associated Registers ............................................... 172 Interrupt .................................................................... 172 Operation ................................................................. 171 Output ...................................................................... 172 PR2 Register .................................................... 184, 192 TMR2 to PR2 Match Interrupt .......................... 184, 192 Timer3 .............................................................................. 173 16-Bit Read/Write Mode ........................................... 175 Associated Registers ............................................... 175 Operation ................................................................. 174 Oscillator .......................................................... 173, 175 Overflow Interrupt ............................................ 173, 175 Special Event Trigger (CCP) .................................... 175 TMR3H Register ...................................................... 173 TMR3L Register ....................................................... 173 Timer4 .............................................................................. 177 Associated Registers ............................................... 178 MSSP Clock Shift ..................................................... 178 Operation ................................................................. 177 Postscaler. See Postscaler, Timer4. PR4 Register ............................................................ 177 Prescaler. See Prescaler, Timer4. TMR4 Register ......................................................... 177 TMR4 to PR4 Match Interrupt .......................... 177, 178 Timing Diagrams A/D Conversion ........................................................ 418 Asynchronous Reception ......................................... 261 Asynchronous Transmission .................................... 258 Asynchronous Transmission (Back to Back) .................................................. 258 Automatic Baud Rate Calculation ............................ 256 Auto-Wake-up Bit (WUE) During Normal Operation ............................................. 262 Auto-Wake-up Bit (WUE) During Sleep ................... 262 Baud Rate Generator with Clock Arbitration ............................................... 233 BRG Overflow Sequence ......................................... 256 BRG Reset Due to SDAx Arbitration During Start Condition ...................................... 242 DS39646B-page 440 Preliminary Brown-out Reset (BOR) ........................................... 405 Bus Collision During a Repeated Start Condition (Case 1) .................................. 243 Bus Collision During a Repeated Start Condition (Case 2) .................................. 243 Bus Collision During a Start Condition (SCLx = 0) ....................................................... 242 Bus Collision During a Stop Condition (Case 1) ........................................................... 244 Bus Collision During a Stop Condition (Case 2) ........................................................... 244 Bus Collision During Start Condition (SDAx Only) ..................................................... 241 Bus Collision for Transmit and Acknowledge ................................................... 240 Capture/Compare/PWM (All ECCP/CCP Modules) ................................ 407 CLKO and I/O .......................................................... 402 Clock Synchronization ............................................. 226 Clock/Instruction Cycle .............................................. 69 EUSART Synchronous Receive (Master/Slave) ................................................. 417 EUSART Synchronous Transmission (Master/Slave) ................................................. 417 Example SPI Master Mode (CKE = 0) ..................... 409 Example SPI Master Mode (CKE = 1) ..................... 410 Example SPI Slave Mode (CKE = 0) ....................... 411 Example SPI Slave Mode (CKE = 1) ....................... 412 External Clock (All Modes Except PLL) ................... 400 External Memory Bus for Sleep (Microprocessor Mode) ............................ 105, 108 External Memory Bus for TBLRD (Extended Microcontroller Mode) ............ 104, 107 External Memory Bus for TBLRD (Microprocessor Mode) .................................... 107 External Memory Bus for TBLRD with 1 TCY Wait State (Microprocessor Mode) .................. 104 Fail-Safe Clock Monitor (FSCM) .............................. 316 First Start Bit Timing ................................................ 234 Full-Bridge PWM Output .......................................... 197 Half-Bridge PWM Output ......................................... 196 High/Low-Voltage Detect Characteristics ................ 397 High-Voltage Detect Operation (VDIRMAG = 1) ............................................... 294 I2C Acknowledge Sequence .................................... 239 I2C Bus Data ............................................................ 413 I2C Bus Start/Stop Bits ............................................ 413 I2C Master Mode (7 or 10-Bit Transmission) ........................................ 237 I2C Master Mode (7-Bit Reception) .......................... 238 I2C Slave Mode (10-Bit Reception, SEN = 0) .......................................................... 223 I2C Slave Mode (10-Bit Reception, SEN = 1) .......................................................... 228 I2C Slave Mode (10-Bit Transmission) .................... 224 I2C Slave Mode (7-bit Reception, SEN = 0) ............ 221 I2C Slave Mode (7-Bit Reception, SEN = 1) ............ 227 I2C Slave Mode (7-Bit Transmission) ...................... 222 I2C Slave Mode General Call Address Sequence (7 or 10-Bit Address Mode) ............ 229 I2C Stop Condition Receive or Transmit Mode ................................................. 239 Low-Voltage Detect Operation (VDIRMAG = 0) ............................................... 293 Master SSP I2C Bus Data ........................................ 415 Master SSP I2C Bus Start/Stop Bits ........................ 415 2004 Microchip Technology Inc. PIC18F8722 FAMILY Parallel Slave Port (PIC18F8527/8622/8627/8722) ....................... 408 Parallel Slave Port (PSP) Read ............................... 160 Parallel Slave Port (PSP) Write ............................... 160 Program Memory Read ............................................ 403 Program Memory Write ............................................ 404 PWM Auto-Shutdown (P1RSEN = 0, Auto-Restart Disabled) .................................... 202 PWM Auto-Shutdown (P1RSEN = 1, Auto-Restart Enabled) ..................................... 202 PWM Direction Change ........................................... 199 PWM Direction Change at Near 100% Duty Cycle .................................... 199 PWM Output ............................................................ 184 Repeated Start Condition ......................................... 235 Reset, Watchdog Timer (WDT), Oscillator Start-up Timer (OST) and Power-up Timer (PWRT) ................................. 405 Send Break Character Sequence ............................ 263 Slave Synchronization ............................................. 211 Slow Rise Time (MCLR Tied to VDD, VDD Rise > TPWRT) ............................................ 55 SPI Mode (Master Mode) ......................................... 210 SPI Mode (Slave Mode, CKE = 0) ........................... 212 SPI Mode (Slave Mode, CKE = 1) ........................... 212 Synchronous Reception (Master Mode, SREN) ..................................... 266 Synchronous Transmission ...................................... 264 Synchronous Transmission (Through TXEN) .............................................. 265 Time-out Sequence on POR w/PLL Enabled (MCLR Tied to VDD) ............................. 55 Time-out Sequence on Power-up (MCLR Not Tied to VDD, Case 1) ....................... 54 Time-out Sequence on Power-up (MCLR Not Tied to VDD, Case 2) ....................... 54 Time-out Sequence on Power-up (MCLR Tied to VDD, VDD Rise < TPWRT) ........................ 54 Timer0 and Timer1 External Clock .......................... 406 Transition for Entry to Idle Mode ................................ 46 Transition for Entry to SEC_RUN Mode .................... 43 Transition for Entry to Sleep Mode ............................ 45 Transition for Two-Speed Start-up (INTOSC to HSPLL) ........................................ 314 Transition for Wake from Idle to Run Mode ............... 46 Transition for Wake from Sleep (HSPLL) ................... 45 Transition from RC_RUN Mode to PRI_RUN Mode ................................................. 44 Transition from SEC_RUN Mode to PRI_RUN Mode (HSPLL) .................................. 43 Transition to RC_RUN Mode ..................................... 44 Typical Opcode Fetch, 8-bit Mode ........................... 108 Timing Diagrams and Specifications A/D Conversion Requirements ................................ 419 AC Characteristics Internal RC Accuracy ....................................... 401 Capture/Compare/PWM Requirements (All ECCP/CCP Modules) ................................ 407 2004 Microchip Technology Inc. CLKO and I/O Requirements ........................... 402, 403 EUSART Synchronous Receive Requirements .................................................. 417 EUSART Synchronous Transmission Requirements .................................................. 417 Example SPI Mode Requirements (Master Mode, CKE = 0) .................................. 409 Example SPI Mode Requirements (Master Mode, CKE = 1) .................................. 410 Example SPI Mode Requirements (Slave Mode, CKE = 0) .................................... 411 Example SPI Slave Mode Requirements (CKE = 1) ................................. 412 External Clock Requirements .................................. 400 I2C Bus Data Requirements (Slave Mode) .............. 414 I2C Bus Start/Stop Bits Requirements (Slave Mode) ................................................... 413 Master SSP I2C Bus Data Requirements ................ 416 Master SSP I2C Bus Start/Stop Bits Requirements .................................................. 415 Parallel Slave Port Requirements (PIC18F8527/8622/8627/8722) ....................... 408 PLL Clock ................................................................ 401 Program Memory Write Requirements .................... 404 Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer and Brown-out Reset Requirements ...................... 405 Timer0 and Timer1 External Clock Requirements ........................................ 406 Top-of-Stack Access .......................................................... 66 TRISE Register PSPMODE Bit ......................................................... 158 TSTFSZ ........................................................................... 361 Two-Speed Start-up ................................................. 297, 314 IESO (CONFIG1H<7>), Internal/External Oscillator Switchover Bit................................... 299 Two-Word Instructions Example Cases ......................................................... 71 TXSTAx Register BRGH Bit ................................................................. 251 W Watchdog Timer (WDT) ........................................... 297, 312 Associated Registers ............................................... 313 Control Register ....................................................... 312 During Oscillator Failure .......................................... 315 Programming Considerations .................................. 312 WCOL ...................................................... 234, 235, 236, 239 WCOL Status Flag ................................... 234, 235, 236, 239 WWW, On-Line Support ...................................................... 5 X XORLW ........................................................................... 361 XORWF ........................................................................... 362 Preliminary DS39646B-page 441 PIC18F8722 FAMILY NOTES: DS39646B-page 442 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY ON-LINE SUPPORT Microchip provides on-line support on the Microchip World Wide Web site. The web site is used by Microchip as a means to make files and information easily available to customers. To view the site, the user must have access to the Internet and a web browser, such as Netscape(R) or Microsoft(R) Internet Explorer. Files are also available for FTP download from our FTP site. SYSTEMS INFORMATION AND UPGRADE HOT LINE The Systems Information and Upgrade Line provides system users a listing of the latest versions of all of Microchip's development systems software products. Plus, this line provides information on how customers can receive the most current upgrade kits. The Hot Line Numbers are: 1-800-755-2345 for U.S. and most of Canada, and 1-480-792-7302 for the rest of the world. Connecting to the Microchip Internet Web Site 042003 The Microchip web site is available at the following URL: www.microchip.com The file transfer site is available by using an FTP service to connect to: ftp://ftp.microchip.com The web site and file transfer site provide a variety of services. Users may download files for the latest Development Tools, Data Sheets, Application Notes, User's Guides, Articles and Sample Programs. A variety of Microchip specific business information is also available, including listings of Microchip sales offices, distributors and factory representatives. Other data available for consideration is: * Latest Microchip Press Releases * Technical Support Section with Frequently Asked Questions * Design Tips * Device Errata * Job Postings * Microchip Consultant Program Member Listing * Links to other useful web sites related to Microchip Products * Conferences for products, Development Systems, technical information and more * Listing of seminars and events 2004 Microchip Technology Inc. Preliminary DS39646B-page 443 PIC18F8722 FAMILY READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: Technical Publications Manager RE: Reader Response Total Pages Sent ________ From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Y N Device: PIC18F6527/6622/6627/6722 PIC18F8527/8622/8627/8722 Questions: Literature Number: DS39646B 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS39646B-page 444 Preliminary 2004 Microchip Technology Inc. PIC18F8722 FAMILY PIC18F8722 FAMILY PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX XXX Device Temperature Range Package Pattern Examples: a) b) Device PIC18F6527/6622/6627/6722(1), PIC18F8527/8622/8627/8722(1), PIC18F6527/6622/6627/6722T(2), PIC18F8527/8622/8627/8722T(2); VDD range 4.2V to 5.5V PIC18LF6627/6722(1), PIC18LF8627/8722(1), PIC18LF6627/6722T(2), PIC18LF8627/8722T(2); VDD range 2.0V to 5.5V Temperature Range I E = = -40C to +85C (Industrial) -40C to +125C (Extended) Package PT = TQFP (Thin Quad Flatpack) Pattern QTP, SQTP, Code or Special Requirements (blank otherwise) 2004 Microchip Technology Inc. PIC18LF6622-I/PT 301 = Industrial temp., TQFP package, Extended VDD limits, QTP pattern #301. PIC18LF6722-E/PT = Extended temp., TQFP package, standard VDD limits. Note 1: 2: Preliminary F = Standard Voltage Range LF = Wide Voltage Range T = in tape and reel TQFP packages only. DS39646B-page 445 Worldwide Sales and Service AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.com Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 India - Bangalore Tel: 91-80-2229-0061 Fax: 91-80-2229-0062 China - Beijing Tel: 86-10-8528-2100 Fax: 86-10-8528-2104 India - New Delhi Tel: 91-11-5160-8631 Fax: 91-11-5160-8632 Austria - Weis Tel: 43-7242-2244-399 Fax: 43-7242-2244-393 Denmark - Ballerup Tel: 45-4450-2828 Fax: 45-4485-2829 China - Chengdu Tel: 86-28-8676-6200 Fax: 86-28-8676-6599 Japan - Kanagawa Tel: 81-45-471- 6166 Fax: 81-45-471-6122 France - Massy Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 China - Fuzhou Tel: 86-591-8750-3506 Fax: 86-591-8750-3521 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 Germany - Ismaning Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Atlanta Alpharetta, GA Tel: 770-640-0034 Fax: 770-640-0307 Boston Westford, MA Tel: 978-692-3848 Fax: 978-692-3821 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Kokomo Kokomo, IN Tel: 765-864-8360 Fax: 765-864-8387 China - Hong Kong SAR Tel: 852-2401-1200 Fax: 852-2401-3431 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 China - Shenzhen Tel: 86-755-8203-2660 Fax: 86-755-8203-1760 China - Shunde Tel: 86-757-2839-5507 Fax: 86-757-2839-5571 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 England - Berkshire Tel: 44-118-921-5869 Fax: 44-118-921-5820 Taiwan - Hsinchu Tel: 886-3-572-9526 Fax: 886-3-572-6459 China - Qingdao Tel: 86-532-502-7355 Fax: 86-532-502-7205 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 San Jose Mountain View, CA Tel: 650-215-1444 Fax: 650-961-0286 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509 10/20/04 DS39646B-page 446 Preliminary 2004 Microchip Technology Inc.