ADSP-21367KSZ-X - Analog Devices, Inc.

Preliminary Technical Data

SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.

SHARC

Processor

ADSP-21367

Rev. PrD

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SUMMARY

High performance 32-bit/40-bit floating point processor

optimized for high performance audio processing

Audio decoder and post processor-algorithm support with

32-bit floating-point implementations

Non-volatile memory may be configured to support audio

decoders and post processor-algorithms like PCM, Dolby

Digital EX, Dolby Prologic IIx, Dolby Digital Plus, Dolby

headphone, DTS 96/24, Neo:6, DTS ES, DTS Lossless,

MPEG2 AAC, MPEG2 2channel, MP3, WMAPro, and multi-

channel encoder. Functions like bass management, delay,

speaker equalization, graphic equalization, decoder/post-

processor algorithm combination support will vary

depending upon the chip version and the system configu-

rations. Please visit www.analog.com

Single-instruction multiple-data (SIMD) computational

architecture

On-chip memory—2M bit of on-chip SRAM and a dedicated

6M bit of on-chip mask-programmable ROM

Code compatible with all other members of the SHARC family

The ADSP-21367 is available with a 333 MHz core instruction

rate with unique audio centric peripherals such as the digi-

tal audio interface, S/PDIF transceiver, serial ports,

8-channel asynchronous sample rate converter, precision

clock generators, and more. For complete ordering infor-

mation, see Ordering Guide on Page 49.

Figure 1. Functional Block Diagram

PWM

SDRAM

CO NTRO LLE R

ASYNCHRONOUS

MEM O RY

INTERFACE

CONTROLPINS

ADDRESS

DATA

CONTROL

EXTERNAL PORT

FLAGS4-15

SPI PORT (2)

TIMERS (3)

TWO WIRE

INTERFACE

UART (2)

DPIROUTINGUNIT

DIGITAL PERIP HERAL INTE R FAC E

GPIO FLAGS/

IRQ/TIMEX P

SERIAL PORTS (8)

INPUT DATA PORT/

PDAP

DAIROUTINGUNIT

SPDIF (Rx/Tx)

DIGITAL AUDIO INTERFACE

IOD(32)

ADDR DATA

IOA(24)

4BLOCKSOF

ON-CHIP MEMORY

2M BIT RAM, 6M BIT ROM

PM DATA BUS

DM DATA BUS

P M A D D RE SS BU S

DM ADDRESS BUS

PX REGISTER

PROCESS ING

ELEMENT

(P EY)

PROCESS ING

ELEMENT

(P EX)

TI MER

INSTRUCTION

CACHE

32-BIT ⫻48 -BIT

DAG1

8⫻4⫻32

CORE PROCESSOR

PROGRAM

SEQUENCER

DMA

CONTROLLER

34 CHANNELS

MEMORY-TO-

MEMORY DMA (2)

IOP RE GIS TE R (MEMORY MAPPED)

CONTROL, STATUS, & DATA BUFFERS

JTAG TEST & EMULATION

DAG2

8⫻4⫻32

I/O PROCESSOR

DAI PINS DPI PINS

SRC (8 CHANNELS)

PRECISION CLO CK

GENERATORS (4)

Rev. PrD | Page 2 of 52 | April 2006

ADSP-21367 Preliminary Technical Data

KEY FEATURES — PROCESSOR CORE

At 333 MHz (3 ns) core instruction rate, the ADSP-21367 per-

forms 2 GFLOPS/666 MMACs

2M bit on-chip, SRAM (0.75M Bit in blocks 0 and 1, and

0.25M Bit in blocks 2 and 3) for simultaneous access by the

core processor and DMA

6M bit on-chip, mask-programmable, ROM (3M bit in block 0

and 3M bit in block 1)

Dual data address generators (DAGs) with modulo and bit-

reverse addressing

Zero-overhead looping with single-cycle loop setup, provid-

ing efficient program sequencing

Single instruction multiple data (SIMD) architecture

provides:

Two computational processing elements

Concurrent execution

Code compatibility with other SHARC family members at

the assembly level

Parallelism in buses and computational units allows: Sin-

gle cycle executions (with or without SIMD) of a multiply

operation, an ALU operation, a dual memory read or

write, and an instruction fetch

Transfers between memory and core at a sustained

6.4G bytes/s bandwidth at 333 MHz core instruction rate

INPUT/OUTPUT FEATURES

DMA controller supports:

34 zero-overhead DMA channels for transfers between

ADSP-21367 internal memory and a variety of

peripherals

32-bit DMA transfers at peripheral clock speed, in parallel

with full-speed processor execution

32-Bit wide external port provides glueless connection to

both synchronous (SDRAM) and asynchronous memory

devices

Programmable wait state options: 2 SCLK to 31 SCLK cycles

Delay-line DMA engine maintains circular buffers in exter-

nal memory with tap/offset based reads

SDRAM accesses at 133 MHz and asynchronous accesses at

66 MHz

Four memory select lines allows multiple external memory

devices

Digital audio interface (DAI) includes eight serial ports, four

precision clock generators, an input data port, an S/PDIF

transceiver, an 8-channel asynchronous sample rate con-

verter, and a signal routing unit

Digital peripheral interface (DPI) includes three timers, two

UARTs, two SPI ports, and an I

C compatible two wire inter-

face port (TWI)

Eight dual data line serial ports that operate at up to

50M bits/s on each data line — each has a clock, frame sync

and two data lines that can be configured as either a

receiver or transmitter pair

TDM support for telecommunications interfaces including

128 TDM channel support for newer telephony interfaces

such as H.100/H.110

Up to 16 TDM stream support, each with 128 channels per

frame

Companding selection on a per channel basis in TDM mode

Input data port, configurable as eight channels of serial data

or seven channels of serial data and up to a 20-bit wide

parallel data channel

Signal routing unit provides configurable and flexible con-

nections between all DAI/DPI components

2 Muxed Flag/IRQ lines

1 Muxed Flag/Timer expired line /MS pin

1 Muxed Flag/IRQ /MS pin

DEDICATED AUDIO COMPONENTS

S/PDIF compatible digital audio receiver/transmitter sup-

ports EIAJ CP-340 (CP-1201), IEC-958, AES/EBU standards

Left-justified, I

S, or right-justified serial data input with

16, 18, 20 or 24-bit word widths (transmitter)

Four independent asynchronous sample rate converters

(SRC). Each converter has separate serial input and output

ports, a deemphasis filter providing up to -128 dB SNR per-

formance, stereo sample rate converter (SRC) and supports

left-justified, I

S, TDM and right-justified modes and 24,

20, 18 and 16 audio data word lengths.

Pulse width modulation provides:

16 PWM outputs configured as four groups of four outputs

supports center-aligned or edge-aligned PWM waveforms

ROM based security features include:

JTAG access to memory permitted with a 64-bit key

Protected memory regions that can be assigned to limit

access under program control to sensitive code

PLL has a wide variety of software and hardware multi-

plier/divider ratios

Dual voltage: 3.3 V I/O, 1.3 V core

Available in 256-ball SBGA and 208-lead MQFP packages (see

Ordering Guide on Page 49)

ADSP-21367Preliminary Technical Data

Rev. PrD | Page 3 of 52 | April 2006

TABLE OF CONTENTS

Summary ................................................................1

Key Features — Processor Core .................................2

Input/Output Features ............................................2

Dedicated Audio Components ..................................2

General Description ..................................................4

ADSP-21367 Family Core Architecture .......................4

ADSP-21367 Memory .............................................5

External Memory ...................................................5

ADSP-21367 Input/Output Features ...........................7

System Design .......................................................9

Development Tools ..............................................10

Additional Information .........................................11

Pin Function Descriptions ........................................12

Data Modes ........................................................ 14

Boot Modes ........................................................ 14

Core Instruction Rate to CLKIN Ratio Modes .............14

ADSP-21367 Specifications ....................................... 15

Operating Conditions ........................................... 15

Electrical Characteristics ........................................15

Package Information ............................................16

Maximum Power Dissipation ................................. 16

ESD Sensitivity .................................................... 16

Absolute Maximum Ratings ................................... 16

Timing Specifications ........................................... 17

Output Drive Currents .......................................... 41

Test Conditions ...................................................41

Capacitive Loading ............................................... 41

Thermal Characteristics ........................................42

256-Ball SBGA Pinout .............................................. 43

208-Lead MQFP Pinout ............................................ 46

Package Dimensions ................................................ 47

Surface Mount Design .......................................... 48

Ordering Guide ......................................................49

REVISION HISTORY

5/06–Rev PrD

Updated ordering guide with X-Grade model numbers. See

Ordering Guide on Page 49

Rev. PrD | Page 4 of 52 | April 2006

ADSP-21367 Preliminary Technical Data

GENERAL DESCRIPTION

The ADSP-21367 SHARC processor is a members of the SIMD

SHARC family of DSPs that feature Analog Devices' Super Har-

vard Architecture. The ADSP-21367 is source code compatible

with the ADSP-2126x and ADSP-2116x DSPs as well as with

first generation ADSP-2106x SHARC processors in SISD

(single-instruction, single-data) mode. The ADSP-21367 is a

32-bit/40-bit floating point processors optimized for high per-

formance automotive audio applications with its large on-chip

SRAM and mask-programmable ROM, multiple internal buses

to eliminate I/O bottlenecks, and an innovative digital audio

interface (DAI).

As shown in the functional block diagram on Page 1, the

ADSP-21367 uses two computational units to deliver a signifi-

cant performance increase over the previous SHARC processors

on a range of DSP algorithms. Fabricated in a state-of-the-art,

high speed, CMOS process, the ADSP-21367 processor achieves

an instruction cycle time of 3.0 ns at 333 MHz. With its SIMD

computational hardware, the ADSP-21367 can perform

two GFLOPS running at 333 MHz.

Table 1 shows performance benchmarks for the ADSP-21367.

The ADSP-21367 continues SHARC’s industry leading stan-

dards of integration for DSPs, combining a high performance

32-bit DSP core with integrated, on-chip system features.

The block diagram of the ADSP-21367 on Page 1, illustrates the

following architectural features:

• Two processing elements, each of which comprises an

ALU, multiplier, shifter, and data register file

• Data address generators (DAG1, DAG2)

• Program sequencer with instruction cache

• PM and DM buses capable of supporting four 32-bit data

transfers between memory and the core at every core pro-

cessor cycle

• Three programmable interval timers with PWM genera-

tion, PWM capture/pulse width measurement, and

external event counter capabilities

•On-chip SRAM (2M bit)

•On-chip mask-programmable ROM (6M bit)

• JTAG test access port

The block diagram of the ADSP-21367 on Page 1 also illustrates

the following architectural features:

• DMA controller

• Eight full duplex serial ports

• Digital audio interface that includes four precision clock

generators (PCG), an input data port (IDP), an S/PDIF

receiver/transmitter, eight channels asynchronous sample

rate converters, eight serial ports, eight serial interfaces, a

16-bit parallel input port (PDAP), a flexible signal routing

unit (DAI SRU).

• Digital peripheral interface that includes three timers, an

-compatible interface, two UARTs, two serial periph-

eral interfaces (SPI), and a flexible signal routing unit (DPI

SRU).

ADSP-21367 FAMILY CORE ARCHITECTURE

The ADSP-21367 is code compatible at the assembly level with

the ADSP-2126x, ADSP-21160, and ADSP-21161, and with the

first generation ADSP-2106x SHARC processors. The

ADSP-21367 shares architectural features with the ADSP-2126x

and ADSP-2116x SIMD SHARC processors, as detailed in the

following sections.

SIMD Computational Engine

The ADSP-21367 contains two computational processing ele-

ments that operate as a single-instruction multiple-data (SIMD)

engine. The processing elements are referred to as PEX and PEY

and each contains an ALU, multiplier, shifter, and register file.

PEX is always active, and PEY may be enabled by setting the

PEYEN mode bit in the MODE1 register. When this mode is

enabled, the same instruction is executed in both processing ele-

ments, but each processing element operates on different data.

This architecture is efficient at executing math intensive DSP

algorithms.

Entering SIMD mode also has an effect on the way data is trans-

ferred between memory and the processing elements. When in

SIMD mode, twice the data bandwidth is required to sustain

computational operation in the processing elements. Because of

this requirement, entering SIMD mode also doubles the band-

width between memory and the processing elements. When

using the DAGs to transfer data in SIMD mode, two data values

are transferred with each access of memory or the register file.

Independent, Parallel Computation Units

Within each processing element is a set of computational units.

The computational units consist of an arithmetic/logic unit

(ALU), multiplier, and shifter. These units perform all opera-

tions in a single cycle. The three units within each processing

element are arranged in parallel, maximizing computational

throughput. Single multifunction instructions execute parallel

ALU and multiplier operations. In SIMD mode, the parallel

Table 1. ADSP-21367 Benchmarks (at 333 MHz)

Benchmark Algorithm

Speed

(at 333 MHz)

1024 Point Complex FFT (Radix 4, with reversal) 27.9 μs

FIR Filter (per tap)

Assumes two files in multichannel SIMD mode

1.5 ns

IIR Filter (per biquad)

6.0 ns

Matrix Multiply (pipelined)

[3x3] × [3x1]

[4x4] × [4x1]

13.5 ns

23.9 ns

Divide (y/×) 10.5 ns

Inverse Square Root 16.3 ns

ADSP-21367Preliminary Technical Data

Rev. PrD | Page 5 of 52 | April 2006

ALU and multiplier operations occur in both processing ele-

ments. These computation units support IEEE 32-bit single-

precision floating-point, 40-bit extended precision floating-

point, and 32-bit fixed-point data formats.

Data Register File

A general-purpose data register file is contained in each pro-

cessing element. The register files transfer data between the

computation units and the data buses, and store intermediate

results. These 10-port, 32-register (16 primary, 16 secondary)

vard architecture, allow unconstrained data flow between

computation units and internal memory. The registers in PEX

are referred to as R0–R15 and in PEY as S0–S15.

Single-Cycle Fetch of Instruction and Four Operands

The ADSP-21367 features an enhanced Harvard architecture in

which the data memory (DM) bus transfers data and the pro-

gram memory (PM) bus transfers both instructions and data

(see Figure 1 on page 1). With the ADSP-21367’s separate pro-

gram and data memory buses and on-chip instruction cache,

the processor can simultaneously fetch four operands (two over

each data bus) and one instruction (from the cache), all in a

single cycle.

Instruction Cache

The ADSP-21367 includes an on-chip instruction cache that

enables three-bus operation for fetching an instruction and four

data values. The cache is selective—only the instructions whose

fetches conflict with PM bus data accesses are cached. This

cache allows full-speed execution of core, looped operations

such as digital filter multiply-accumulates, and FFT butterfly

processing.

Data Address Generators With Zero-Overhead Hardware

Circular Buffer Support

The ADSP-21367’s two data address generators (DAGs) are

used for indirect addressing and implementing circular data

buffers in hardware. Circular buffers allow efficient program-

ming of delay lines and other data structures required in digital

signal processing, and are commonly used in digital filters and

Fourier transforms. The two DAGs of the ADSP-21367 contain

sufficient registers to allow the creation of up to 32 circular buff-

ers (16 primary register sets, 16 secondary). The DAGs

automatically handle address pointer wraparound, reduce over-

head, increase performance, and simplify implementation.

Circular buffers can start and end at any memory location.

Flexible Instruction Set

The 48-bit instruction word accommodates a variety of parallel

operations, for concise programming. For example, the

ADSP-21367 can conditionally execute a multiply, an add, and a

subtract in both processing elements while branching and fetch-

ing up to four 32-bit values from memory—all in a single

instruction.

ADSP-21367 MEMORY

The ADSP-21367 adds the following architectural features to

the SIMD SHARC family core.

On-Chip Memory

The ADSP-21367 contains two megabits of internal RAM and

six megabits of internal mask-programmable ROM. Each block

can be configured for different combinations of code and data

storage (see Table 2 on Page 6). Each memory block supports

single-cycle, independent accesses by the core processor and I/O

processor. The ADSP-21367 memory architecture, in combina-

tion with its separate on-chip buses, allow two data transfers

from the core and one from the I/O processor, in a single cycle.

The ADSP-21367’s, SRAM can be configured as a maximum of

64K words of 32-bit data, 128K words of 16-bit data, 42K words

of 48-bit instructions (or 40-bit data), or combinations of differ-

ent word sizes up to two megabits. All of the memory can be

accessed as 16-bit, 32-bit, 48-bit, or 64-bit words. A 16-bit float-

ing-point storage format is supported that effectively doubles

the amount of data that may be stored on-chip. Conversion

between the 32-bit floating-point and 16-bit floating-point for-

mats is performed in a single instruction. While each memory

block can store combinations of code and data, accesses are

most efficient when one block stores data using the DM bus for

transfers, and the other block stores instructions and data using

the PM bus for transfers.

Using the DM bus and PM buses, with one bus dedicated to

each memory block, assures single-cycle execution with two

data transfers. In this case, the instruction must be available in

the cache.

EXTERNAL MEMORY

The external port on the ADSP-21367 SHARC provides a high

performance, glueless interface to a wide variety of industry-

standard memory devices. The 32-bit wide bus may be used to

interface to synchronous and/or asynchronous memory devices

through the use of its separate internal memory controllers: the

first is an SDRAM controller for connection of industry-stan-

dard synchronous DRAM devices and DIMMs (Dual Inline

Memory Module), while the second is an asynchronous mem-

ory controller intended to interface to a variety of memory

devices. Four memory select pins enable up to four separate

devices to coexist, supporting any desired combination of syn-

chronous and asynchronous device types. NonSDRAM external

memory address space is shown in Table 3.

SDRAM Controller

The SDRAM controller provides an interface to up to four sepa-

rate banks of industry-standard SDRAM devices or DIMMs, at

speeds up to f

SCLK

. Fully compliant with the SDRAM standard,

each bank can has its own memory select line (MS0–MS3), and

can be configured to contain between 16M bytes and

128M bytes of memory. SDRAM external memory address

space is shown in Table 4.

The controller maintains all of the banks as a contiguous

address space so that the processor sees this as a single address

space, even if different size devices are used in the different

banks.

Rev. PrD | Page 6 of 52 | April 2006

ADSP-21367 Preliminary Technical Data

A set of programmable timing parameters is available to config-

ure the SDRAM banks to support slower memory devices. The

memory banks can be configured as either 32 bits wide for max-

imum performance and bandwidth or 16 bits wide for

minimum device count and lower system cost.

The SDRAM controller address, data, clock, and command pins

can drive loads up to 30 pF. For larger memory systems, the

SDRAM controller external buffer timing should be selected

and external buffering should be provided so that the load on

the SDRAM controller pins does not exceed 30 pF.

Asynchronous Controller

The asynchronous memory controller provides a configurable

interface for up to four separate banks of memory or I/O

devices. Each bank can be independently programmed with dif-

ferent timing parameters, enabling connection to a wide variety

of memory devices including SRAM, ROM, flash, and EPROM,

as well as I/O devices that interface with standard memory con-

trol lines. Bank 0 occupies a 14.7M word window and banks 1, 2,

and 3 occupy a 16M word window in the processor’s address

space but, if not fully populated, these windows are not made

contiguous by the memory controller logic. The banks can also

be configured as 8-bit, 16-bit, or 32-bit wide buses for ease of

interfacing to a range of memories and I/O devices tailored

either to high performance or to low cost and power.

The asynchronous memory controller is capable of a maximum

throughput of 267 M bytes/sec using a 66 MHz external bus

speed. Other features include 8-bit to 32-bit and 16-bit to 32-bit

packing and unpacking, booting from Bank Select 1, and sup-

port for delay line DMA.

Table 2. ADSP-21367 Internal Memory Space

IOP Registers 0x0000 0000–0x0003 FFFF

Long Word (64 Bits)

Extended Precision Normal or

Instruction Word (48 Bits) Normal Word (32 Bits) Short Word (16 Bits)

BLOCK 0 ROM

0x0004 0000–0x0004 BFFF

BLOCK 0 ROM

0x0008 0000–0x0008 FFFF

BLOCK 0 ROM

0x0008 0000–0x0009 7FFF

BLOCK 0 ROM

0x0010 0000–0x0012 FFFF

Reserved

0x0004 F000–0x0004 FFFF

Reserved

0x0009 4000–0x0009 FFFF

Reserved

0x0009 E0000–0x0009 FFFF

Reserved

0x0013 C000–0x0013 FFFF

BLOCK 0 RAM

0x0004 C000–0x0004 EFFF

BLOCK 0 RAM

0x0009 0000–0x0009 3FFF

BLOCK 0 RAM

0x0009 8000–0x0009 DFFF

BLOCK 0 RAM

0x0013 0000–0x0013 BFFF

BLOCK 1 ROM

0x0005 0000–0x0005 BFFF

BLOCK 1 ROM

0x000A 0000–0x000A FFFF

BLOCK 1 ROM

0x000A 0000–0x000B 7FFF

BLOCK 1 ROM

0x0014 0000–0x0016 FFFF

Reserved

0x0005 F000–0x0005 FFFF

Reserved

0x000B 4000–0x000B FFFF

Reserved

0x000B E000–0x000B FFFF

Reserved

0x0017 C000–0x0017 FFFF

BLOCK 1 RAM

0x0005 C000–0x0005 EFFF

BLOCK 1 RAM

0x000B 0000–0x000B 3FFF

BLOCK 1 RAM

0x000B 8000–0x000B DFFF

BLOCK 1 RAM

0x0017 0000–0x0017 BFFF

BLOCK 2 RAM

0x0006 0000–0x0006 0FFF

BLOCK 2 RAM

0x000C 0000–0x000C 1554

BLOCK 2 RAM

0x000C 0000–0x000C 1FFF

BLOCK 2 RAM

0x0018 0000–0x0018 3FFF

Reserved

0x0006 1000–0x0006 FFFF

Reserved

0x000C 1555–0x000D FFFF

Reserved

0x000C 2000–0x000D FFFF

Reserved

0x0018 4000–0x001B FFFF

BLOCK 3 RAM

0x0007 0000–0x0007 0FFF

BLOCK 3 RAM

0x000E 0000–0x000E 1554

BLOCK 3 RAM

0x000E 0000–0x000E 1FFF

BLOCK 3 RAM

0x001C 0000–0x001C 3FFF

Reserved

0x0007 1000–0x0007 FFFF

Reserved

0x000E 1555–0x000F FFFF

Reserved

0x000E 2000–0x000F FFFF

Reserved

0x001C 4000–0x001F FFFF

Table 3. External Memory for Non SDRAM Addresses

Bank

Size in

Words Address Range

Bank 0 14M 0x0020 0000 – 0x00FF FFFF

Bank 1 16M 0x0400 0000 – 0x04FF FFFF

Bank 2 16M 0x0800 0000 – 0x08FF FFFF

Bank 3 16M 0x0C00 0000 – 0x0CFF FFFF

Table 4. External Memory for SDRAM Addresses

Bank

Size in

Words Address Range

Bank 0 62M 0x0020 0000 – 0x03FF FFFF

Bank 1 64M 0x0400 0000 – 0x07FF FFFF

Bank 2 64M 0x0800 0000 – 0x0BFF FFFF

Bank 3 64M 0x0C00 0000 – 0x0FFF FFFF

ADSP-21367Preliminary Technical Data

Rev. PrD | Page 7 of 52 | April 2006

ADSP-21367 INPUT/OUTPUT FEATURES

The ADSP-21367 I/O processor provides 34 channels of DMA,

as well as an extensive set of peripherals. These include a 20 pin

digital audio interface which controls:

• Eight serial ports

• S/PDIF receiver/transmitter

• Four precision clock generators

• Four stereo sample rate converters

• Internal data port/parallel data acquisition port

The ADSP-21367 processor also contains a 14 pin digital

peripheral interface which controls:

• Three general-purpose timers

• Two serial peripheral Interfaces

•Two universal asynchronous receiver/transmitters

(UARTs)

• A two wire interface/I

DMA Controller

The ADSP-21367’s on-chip DMA controller allows data trans-

fers without processor intervention. The DMA controller

operates independently and invisibly to the processor core,

allowing DMA operations to occur while the core is simulta-

neously executing its program instructions. DMA transfers can

occur between the ADSP-21367’s internal memory and its serial

ports, the SPI-compatible (serial peripheral interface) ports, the

IDP (input data port), the parallel data acquisition port (PDAP),

or the UART. Thirty-four channels of DMA are available on the

ADSP-21367—sixteen via the serial ports, eight via the input

data port, four for the UARTs, two for the SPI interface, two for

the external port, and two for memory-to-memory transfers.

Programs can be downloaded to the ADSP-21367 using DMA

transfers. Other DMA features include interrupt generation

upon completion of DMA transfers, and DMA chaining for

automatic linked DMA transfers.

Delay Line DMA

The ADSP-21367 processor provides delay line DMA function-

ality. This allows processor reads and writes to external delay

line buffers (and hence to external memory) with limited core

interaction.

Digital Audio and Digital Peripheral Interfaces (DAI/DPI)

The digital audio and digital periphal interfaces (DAI and DPI)

provide the ability to connect various peripherals to any of the

DSPs DAI or DPI pins (DAI_P20–1 and DPI_P14–1).

Programs make these connections using the signal routing units

(SRU1 and SRU2), shown in Figure 1.

The SRUs are matrix routing units (or group of multiplexers)

that enables the peripherals provided by the DAI and DPI to be

interconnected under software control. This allows easy use of

the associated peripherals for a much wider variety of applica-

tions by using a larger set of algorithms than is possible with

non configurable signal paths.

The DAI and DPI also includes eight serial ports, an S/PDIF

receiver/transmitter, four precision clock generators (PCG),

eight channels of synchronous sample rate converters, and an

input data port (IDP). The IDP provides an additional input

path to the ADSP-21367 core, configurable as either eight chan-

nels of I

S serial data or as seven channels plus a single 20-bit

wide synchronous parallel data acquisition port. Each data

channel has its own DMA channel that is independent from the

ADSP-21367's serial ports.

For complete information on using the DAI and DPI, see the

ADSP-2136x SHARC Processor Hardware Reference for the

ADSP-21367/8/9 Processors.

Serial Ports

The ADSP-21367 features eight synchronous serial ports that

provide an inexpensive interface to a wide variety of digital and

mixed-signal peripheral devices such as the Analog Devices

AD183x family of audio codecs, ADCs, and DACs. The serial

ports are made up of two data lines, a clock, and frame sync. The

data lines can be programmed to either transmit or receive and

each data line has a dedicated DMA channel.

Serial ports are enabled via 16 programmable and simultaneous

receive or transmit pins that support up to 32 transmit or

32 receive channels of audio data when all eight SPORTS are

enabled, or eight full duplex TDM streams of 128 channels

per frame.

The serial ports operate at a maximum data rate of 50M bits/s.

Serial port data can be automatically transferred to and from

on-chip memory via dedicated DMA channels. Each of the

serial ports can work in conjunction with another serial port to

provide TDM support. One SPORT provides two transmit sig-

nals while the other SPORT provides the two receive signals.

The frame sync and clock are shared.

Serial ports operate in five modes:

• Standard DSP serial mode

• Multichannel (TDM) mode with support for packed I

mode

•I

S mode

•Packed I

S mode

• Left-justified sample pair mode

Left-justified sample pair mode is a mode where in each frame

sync cycle two samples of data are transmitted/received—one

sample on the high segment of the frame sync, the other on the

low segment of the frame sync. Programs have control over var-

ious attributes of this mode.

Each of the serial ports supports the left-justified sample pair

and I

S protocols (I

S is an industry standard interface com-

monly used by audio codecs, ADCs, and DACs such as the

Analog Devices AD183x family), with two data pins, allowing

four left-justified sample pair or I

S channels (using two stereo

devices) per serial port, with a maximum of up to 32 I

S chan-

nels. The serial ports permit little-endian or big-endian

transmission formats and word lengths selectable from 3 bits to

32 bits. For the left-justified sample pair and I

S modes, data-

Rev. PrD | Page 8 of 52 | April 2006

ADSP-21367 Preliminary Technical Data

word lengths are selectable between 8 bits and 32 bits. Serial

ports offer selectable synchronization and transmit modes as

well as optional μ-law or A-law companding selection on a per

channel basis. Serial port clocks and frame syncs can be inter-

nally or externally generated.

The serial ports also contain frame sync error detection logic

where the serial ports detect frame syncs that arrive early (for

example frame syncs that arrive while the transmission/recep-

tion of the previous word is occurring). All the serial ports also

share one dedicated error interrupt.

S/PDIF Compatible Digital Audio Receiver/Transmitter

and Synchronous/Asynchronous Sample Rate Converter

The S/PDIF receiver/transmitter has no separate DMA chan-

nels. It receives audio data in serial format and converts it into a

biphase encoded signal. The serial data input to the

receiver/transmitter can be formatted as left justified, I

S or

right justified with word widths of 16, 18, 20, or 24 bits.

The serial data, clock, and frame sync inputs to the S/PDIF

receiver/transmitter are routed through the signal routing unit

(SRU). They can come from a variety of sources such as the

SPORTs, external pins, the precision clock generators (PCGs),

or the sample rate converters (SRC), and are controlled by the

SRU control registers.

The sample rate converter contains four SRC blocks and is the

same core as that used in the AD1896 192 kHz stereo asynchro-

nous sample rate converter and provides up to 128 dB SNR. The

SRC block is used to perform synchronous or asynchronous

sample rate conversion across independent stereo channels,

without using internal processor resources. The four SRC blocks

can also be configured to operate together to convert multi-

channel audio data without phase mismatches. Finally, the SRC

is used to clean up audio data from jittery clock sources such as

the S/PDIF receiver.

Digital Peripheral Interface (DPI)

The digital peripheral interface provides connections to two

serial peripheral interface ports (SPI), two universal asynchro-

nous receiver-transmitters (UARTs), a two wire interface

(TWI), 12 Flags, and three general-purpose timers.

Serial Peripheral (Compatible) Interface

The ADSP-21367 SHARC processor contains two serial periph-

eral interface ports (SPIs). The SPI is an industry standard

synchronous serial link, enabling the ADSP-21367 SPI compati-

ble port to communicate with other SPI compatible devices. The

SPI consists of two data pins, one device select pin, and one

clock pin. It is a full-duplex synchronous serial interface, sup-

porting both master and slave modes. The SPI port can operate

in a multimaster environment by interfacing with up to four

other SPI compatible devices, either acting as a master or slave

device. The ADSP-21367 SPI compatible peripheral implemen-

tation also features programmable baud rate and clock phase

and polarities. The ADSP-21367 SPI compatible port uses open

drain drivers to support a multimaster configuration and to

avoid data contention.

UART Port

The ADSP-21367 processor provides a full-duplex universal

asynchronous receiver/transmitter (UART) port, which is fully

compatible with PC-standard UARTs. The UART port provides

a simplified UART interface to other peripherals or hosts, sup-

porting full-duplex, DMA-supported, asynchronous transfers of

serial data. The UART also has multiprocessor communication

capability using 9-bit address detection. This allows it to be used

in multidrop networks through the RS-485 data interface stan-

dard. The UART port also includes support for 5 data bits to

8 data bits, 1 or 2 stop bits, and none, even, or odd parity. The

UART port supports two modes of operation:

• PIO (programmed I/O) – The processor sends or receives

data by writing or reading I/O-mapped UART registers.

The data is double-buffered on both transmit and receive.

• DMA (direct memory access) – The DMA controller trans-

fers both transmit and receive data. This reduces the

number and frequency of interrupts required to transfer

data to and from memory. The UART has two dedicated

DMA channels, one for transmit and one for receive. These

DMA channels have lower default priority than most DMA

channels because of their relatively low service rates.

The UART port's baud rate, serial data format, error code gen-

eration and status, and interrupts are programmable:

• Supporting bit rates ranging from (f

SCLK

/ 1,048,576) to

SCLK

/16) bits per second.

• Supporting data formats from 7 bits to12 bits per frame.

• Both transmit and receive operations can be configured to

generate maskable interrupts to the processor.

Where the 16-bit UART_Divisor comes from the DLH register

(most significant 8 bits) and DLL register (least significant

8bits).

In conjunction with the general-purpose timer functions, auto-

baud detection is supported.

Timers

The ADSP-21367 has a total of four timers: a core timer that can

generate periodic software interrupts and three general purpose

timers that can generate periodic interrupts and be indepen-

dently set to operate in one of three modes:

•Pulse waveform generation mode

•Pulse width count/capture mode

• External event watchdog mode

The core timer can be configured to use FLAG3 as a timer

expired signal, and each general purpose timer has one bidirec-

tional pin and four registers that implement its mode of

operation: a 6-bit configuration register, a 32-bit count register,

a 32-bit period register, and a 32-bit pulse width register. A sin-

gle control and status register enables or disables all three

general purpose timers independently.

ADSP-21367Preliminary Technical Data

Rev. PrD | Page 9 of 52 | April 2006

Two Wire Interface Port (TWI)

The TWI is a bi-directional 2-wire, serial bus used to move 8-bit

data while maintaining compliance with the I

C bus protocol.

The TWI Master incorporates the following features:

• Simultaneous master and slave operation on multiple

device systems with support for multi master data

arbitration

• Digital filtering and timed event processing

• 7-bit and 10-bit addressing

• 100K bits/s and 400K bits/s data rates

• Low interrupt rate

Pulse Width Modulation

The PWM module is a flexible, programmable, PWM waveform

generator that can be programmed to generate the required

switching patterns for various applications related to motor and

engine control or audio power control. The PWM generator can

generate either center-aligned or edge-aligned PWM wave-

forms. In addition, it can generate complementary signals on

two outputs in paired mode or independent signals in non

paired mode (applicable to a single group of four PWM

waveforms).

The entire PWM module has four groups of four PWM outputs

each. Therefore, this module generates 16 PWM outputs in

total. Each PWM group produces two pairs of PWM signals on

the four PWM outputs.

The PWM generator is capable of operating in two distinct

modes while generating center-aligned PWM waveforms: single

update mode or double update mode. In single update mode the

duty cycle values are programmable only once per PWM period.

This results in PWM patterns that are symmetrical about the

mid-point of the PWM period. In double update mode, a sec-

ond updating of the PWM registers is implemented at the mid-

point of the PWM period. In this mode, it is possible to produce

asymmetrical PWM patterns that produce lower harmonic dis-

tortion in three-phase PWM inverters.

ROM Based Security

The ADSP-21367 has a ROM security feature that provides

hardware support for securing user software code by preventing

unauthorized reading from the internal code when enabled.

When using this feature, the processor does not boot-load any

external code, executing exclusively from internal SRAM/ROM.

Additionally, the processor is not freely accessible via the JTAG

port. Instead, a unique 64-bit key, which must be scanned in

through the JTAG or test access port will be assigned to each

customer. The device will ignore a wrong key. Emulation fea-

tures and external boot modes are only available after the

correct key is scanned.

SYSTEM DESIGN

The following sections provide an introduction to system design

options and power supply issues.

Program Booting

The internal memory of the ADSP-21367 boots at system

power-up from an 8-bit EPROM via the external port, an SPI

master, an SPI slave, or an internal boot. Booting is determined

by the Boot Configuration (BOOTCFG1–0) pins (see Table 7 on

Page 14). Selection of the boot source is controlled via the SPI as

either a master or slave device, or it can immediately begin exe-

cuting from ROM.

Power Supplies

The ADSP-21367 has separate power supply connections for the

internal (V

DDINT

), external (V

DDEXT

), and analog (A

VDD

VSS

)

power supplies. The internal and analog supplies must meet the

1.3 V requirement. The external supply must meet the 3.3 V

requirement. All external supply pins must be connected to the

same power supply.

Note that the analog supply pin (A

VDD

) powers the ADSP-

21367’s internal clock generator PLL. To produce a stable clock,

it is recommended that PCB designs use an external filter circuit

for the A

VDD

pin. Place the filter components as close as possible

to the A

VDD

VSS

pins. For an example circuit, see Figure 2. (A

recommended ferrite chip is the muRata BLM18AG102SN1D).

To reduce noise coupling, the PCB should use a parallel pair of

power and ground planes for V

DDINT

and GND. Use wide traces

to connect the bypass capacitors to the analog power (A

VDD

) and

ground (A

VSS

) pins. Note that the A

VDD

and A

VSS

pins specified in

Figure 2 are inputs to the processor and not the analog ground

plane on the board—the A

VSS

pin should connect directly to dig-

ital ground (GND) at the chip.

Target Board JTAG Emulator Connector

Analog Devices DSP Tools product line of JTAG emulators uses

the IEEE 1149.1 JTAG test access port of the ADSP-21367 pro-

cessor to monitor and control the target board processor during

emulation. Analog Devices DSP Tools product line of JTAG

emulators provides emulation at full processor speed, allowing

inspection and modification of memory, registers, and proces-

sor stacks. The processor's JTAG interface ensures that the

emulator will not affect target system loading or timing.

For complete information on Analog Devices’ SHARC DSP

Tools product line of JTAG emulator operation, see the appro-

priate “Emulator Hardware User's Guide”.

Figure 2. Analog Power (A

VDD

) Filter Circuit

HI Z FERRITE

BEAD CHIP

LOCATE ALL COMPONENTS

CLOSE TO AVDD AND AVSS PINS

AVDD

AVSS

100nF 10nF 1nF ADSP-213xx

VDDINT

Rev. PrD | Page 10 of 52 | April 2006

ADSP-21367 Preliminary Technical Data

DEVELOPMENT TOOLS

The ADSP-21367 is supported with a complete set of

CROSSCORE

software and hardware development tools,

including Analog Devices emulators and VisualDSP++

devel-

opment environment. The same emulator hardware that

supports other SHARC processors also fully emulates the

ADSP-21367.

The VisualDSP++ project management environment lets pro-

grammers develop and debug an application. This environment

includes an easy to use assembler (which is based on an alge-

braic syntax), an archiver (librarian/library builder), a linker, a

loader, a cycle-accurate instruction-level simulator, a C/C++

compiler, and a C/C++ runtime library that includes DSP and

mathematical functions. A key point for these tools is C/C++

code efficiency. The compiler has been developed for efficient

translation of C/C++ code to DSP assembly. The SHARC has

architectural features that improve the efficiency of compiled

C/C++ code.

The VisualDSP++ debugger has a number of important fea-

tures. Data visualization is enhanced by a plotting package that

offers a significant level of flexibility. This graphical representa-

tion of user data enables the programmer to quickly determine

the performance of an algorithm. As algorithms grow in com-

plexity, this capability can have increasing significance on the

designer’s development schedule, increasing productivity. Sta-

tistical profiling enables the programmer to non intrusively poll

the processor as it is running the program. This feature, unique

to VisualDSP++, enables the software developer to passively

gather important code execution metrics without interrupting

the real-time characteristics of the program. Essentially, the

developer can identify bottlenecks in software quickly and effi-

ciently. By using the profiler, the programmer can focus on

those areas in the program that impact performance and take

corrective action.

Debugging both C/C++ and assembly programs with the

VisualDSP++ debugger, programmers can:

• View mixed C/C++ and assembly code (interleaved source

and object information)

• Insert breakpoints

• Set conditional breakpoints on registers, memory,

and stacks

• Trace instruction execution

• Perform linear or statistical profiling of program execution

• Fill, dump, and graphically plot the contents of memory

• Perform source level debugging

• Create custom debugger windows

The VisualDSP++ IDDE lets programmers define and manage

DSP software development. Its dialog boxes and property pages

let programmers configure and manage all of the SHARC devel-

opment tools, including the color syntax highlighting in the

VisualDSP++ editor. This capability permits programmers to:

• Control how the development tools process inputs and

generate outputs

• Maintain a one-to-one correspondence with the tool’s

command line switches

The VisualDSP++ Kernel (VDK) incorporates scheduling and

resource management tailored specifically to address the mem-

ory and timing constraints of DSP programming. These

capabilities enable engineers to develop code more effectively,

eliminating the need to start from the very beginning, when

developing new application code. The VDK features include

threads, critical and unscheduled regions, semaphores, events,

and device flags. The VDK also supports priority-based, pre-

emptive, cooperative, and time-sliced scheduling approaches. In

addition, the VDK was designed to be scalable. If the application

does not use a specific feature, the support code for that feature

is excluded from the target system.

Because the VDK is a library, a developer can decide whether to

use it or not. The VDK is integrated into the VisualDSP++

development environment, but can also be used via standard

command line tools. When the VDK is used, the development

environment assists the developer with many error-prone tasks

and assists in managing system resources, automating the gen-

eration of various VDK based objects, and visualizing the

system state, when debugging an application that uses the VDK.

VisualDSP++ Component Software Engineering (VCSE) is

Analog Devices’ technology for creating, using, and reusing

software components (independent modules of substantial

functionality) to quickly and reliably assemble software applica-

tions. Download components from the Web and drop them into

the application. Publish component archives from within

VisualDSP++. VCSE supports component implementation in

C/C++ or assembly language.

Use the Expert Linker to visually manipulate the placement of

code and data on the embedded system. View memory utiliza-

tion in a color-coded graphical form, easily move code and data

to different areas of the processor or external memory with the

drag of the mouse, examine run time stack and heap usage. The

Expert Linker is fully compatible with the existing Linker Defi-

nition File (LDF), allowing the developer to move between the

graphical and textual environments.

In addition to the software and hardware development tools

available from Analog Devices, third parties provide a wide

range of tools supporting the SHARC processor family. Hard-

ware tools include SHARC processor PC plug-in cards. Third

party software tools include DSP libraries, real-time operating

systems, and block diagram design tools.

ADSP-21367Preliminary Technical Data

Rev. PrD | Page 11 of 52 | April 2006

Designing an Emulator-Compatible DSP Board (Target)

The Analog Devices family of emulators are tools that every

DSP developer needs in order to test and debug hardware and

software systems. Analog Devices has supplied an IEEE 1149.1

JTAG Test Access Port (TAP) on each JTAG DSP. Nonintrusive

in-circuit emulation is assured by the use of the processor’s

JTAG interface—the emulator does not affect target system

loading or timing. The emulator uses the TAP to access the

internal features of the processor, allowing the developer to load

code, set breakpoints, observe variables, observe memory, and

examine registers. The processor must be halted to send data

and commands, but once an operation has been completed by

the emulator, the DSP system is set running at full speed with no

impact on system timing.

To use these emulators, the target board must include a header

that connects the DSP’s JTAG port to the emulator.

For details on target board design issues including mechanical

layout, single processor connections, signal buffering, signal ter-

mination, and emulator pod logic, see the EE-68: Analog Devices

JTAG Emulation Technical Reference on the Analog Devices

website (www.analog.com)—use site search on “EE-68.” This

document is updated regularly to keep pace with improvements

to emulator support.

Evaluation Kit

Analog Devices offers a range of EZ-KIT Lite

evaluation plat-

forms to use as a cost effective method to learn more about

developing or prototyping applications with Analog Devices

processors, platforms, and software tools. Each EZ-KIT Lite

includes an evaluation board along with an evaluation suite of

the VisualDSP++ development and debugging environment

with the C/C++ compiler, assembler, and linker. Also included

are sample application programs, power supply, and a USB

cable. All evaluation versions of the software tools are limited

for use only with the EZ-KIT Lite product.

The USB controller on the EZ-KIT Lite board connects the

board to the USB port of the user’s PC, enabling the

VisualDSP++ evaluation suite to emulate the on-board proces-

sor in-circuit. This permits the customer to download, execute,

and debug programs for the EZ-KIT Lite system. It also allows

in-circuit programming of the on-board Flash device to store

user-specific boot code, enabling the board to run as a standal-

one unit without being connected to the PC.

With a full version of VisualDSP++ installed (sold separately),

engineers can develop software for the EZ-KIT Lite or any cus-

tom defined system. Connecting one of Analog Devices JTAG

emulators to the EZ-KIT Lite board enables high-speed, non-

intrusive emulation.

ADDITIONAL INFORMATION

This data sheet provides a general overview of the ADSP-21367

architecture and functionality. For detailed information on the

ADSP-2136x Family core architecture and instruction set, refer

to the ADSP-2136x SHARC Processor Hardware Reference for

the ADSP-21367/8/9 Processors and the ADSP-2136x SHARC

Processor Programming Reference.

Rev. PrD | Page 12 of 52 | April 2006

ADSP-21367 Preliminary Technical Data

PIN FUNCTION DESCRIPTIONS

The following symbols appear in the Type column of Table 5:

A = Asynchronous, G = Ground, I = Input, O = Output,

P = Power Supply, S = Synchronous, (A/D) = Active Drive,

(O/D) = Open Drain, and T = Three-State, (pd) = pull-down

resistor, (pu) = pull-up resistor.

Table 5. Pin List

Name Type

State During

/After Reset Description

ADDR

23–0

O/T (pu) Pulled

high/driven low

External Address.

The ADSP-21367 outputs addresses for external memory and

peripherals on these pins.

DATA

31–0

I/O (pu) Pulled

high/pulled

high

External Data.

Data pins can be multiplexed to support external memory interface data

(I/O), the PDAP (I), FLAGS (I/O), and PWM (O). After reset, all DATA pins are in EMIF mode

and FLAG(0-3) pins are in FLAGS mode (default).

When configured using the

IDP_PDAP_CTL register, IDP Channel 0 scans the DATA

31–8

pins for parallel input

data.

DAI _P

20–1

I/O with program-

mable pu

Pulled high/

pulled high

Digital Audio Interface Pins

. These pins provide the physical interface to the DAI SRU.

The DAI SRU configuration registers define the combination of on-chip audio centric

peripheral inputs or outputs connected to the pin, and to the pin’s output enable. The

configuration registers then determines the exact behavior of the pin. Any input or

output signal present in the DAI SRU may be routed to any of these pins. The DAI SRU

provides the connection from the serial ports (8), the SRC module, the PWM module,

the S/PDIF module, input data ports (2), and the precision clock generators (4), to the

DAI_P20–1 pins. Pull-ups can be disabled via the DAI_PIN_PULLUP register.

DPI _P

14–1

I/O with program-

mable pu

Pulled high/

pulled high

Digital Peripheral Interface.

These pins provide the physical interface to the DPI SRU.

The DPI SRU configuration registers define the combination of on-chip peripheral inputs

or outputs connected to the pin and to the pin’s output enable. The configuration

registers of these peripherals then determines the exact behavior of the pin. Any input

or output signal present in the DPI SRU may be routed to any of these pins. The DPI SRU

provides the connection from the timers (3), SPIs (2), UARTs (2), flags (12) TWI (1), and

general-purpose I/O (9) to the DPI_P14–1 pins. The TWI output is an open-drain

output—so the pins used for I

C data and clock should be connected to logic level 0.

Pull-ups can be disabled via the DPI_PIN_PULLUP register.

ACK I (pu)

Memory Acknowledge.

External devices can deassert ACK (low) to add wait states to

an external memory access. ACK is used by I/O devices, memory controllers, or other

peripherals to hold off completion of an external memory access.

RD O/T (pu) Pulled high/

driven high

External Port Read Enable.

RD is asserted whenever the ADSP-21367 reads a word

from external memory.

WR O/T (pu) Pulled high/

driven high

External Port Write Enable.

WR is asserted when the ADSP-21367 writes a word to

external memory.

SDRAS O/T (pu) Pulled high/

driven high

SDRAM Row Address Strobe.

Connect to SDRAM’s RAS pin. In conjunction with other

SDRAM command pins, defines the operation for the SDRAM to perform.

SDCAS O/T (pu) Pulled high/

driven high

SDRAM Column Address Select.

Connect to SDRAM's CAS pin. In conjunction with

other SDRAM command pins, defines the operation for the SDRAM to perform.

SDWE O/T (pu) Pulled high/

driven high

SDRAM Write Enable.

Connect to SDRAM’s WE or W buffer pin.

ADSP-21367Preliminary Technical Data

Rev. PrD | Page 13 of 52 | April 2006

SDCKE O/T (pu) Pulled high/

driven high

SDRAM Clock Enable.

Connect to SDRAM’s CKE pin. Enables and disables the CLK

signal. For details, see the data sheet supplied with the SDRAM device.

SDA10 O/T (pu) Pulled high/

driven low

SDRAM A10 Pin.

Enables applications to refresh an SDRAM in parallel with non-

SDRAM accesses. This pin replaces the DSP’s A10 pin only during SDRAM accesses.

SDCLK0 O/T High-Z/driving

SDRAM Clock Output 0.

0–1

O/T (pu) Pulled high/

driven high

Memory Select Lines 0–1.

These lines are asserted (low) as chip selects for the corre-

sponding banks of external memory. The MS

3-0

lines are decoded memory address lines

that change at the same time as the other address lines. When no external memory

access is occurring, the MS

3-0

lines are inactive; they are active, however, when a condi-

tional memory access instruction is executed, whether or not the condition is true.

The MS1 pin can be used in EPORT/FLASH boot mode. See the hardware reference for

more information.

FLAG[0]/IRQ0 I/O High-Z/high-Z

FLAG0/Interrupt Request0.

FLAG[1]/IRQ1 I/O High-Z/high-Z

FLAG1/Interrupt Request1.

FLAG[2]/IRQ2/

MS2

I/O with program-

mable pu (for MS

mode)

High-Z/high-Z

FLAG2/Interrupt Request/Memory Select2.

FLAG[3]/TIMEXP/

MS3

I/O with program-

mable pu (for MS

mode)

High-Z/high-Z

FLAG3/Timer Expired/Memory Select3.

TDI I (pu)

Test Data Input (JTAG).

Provides serial data for the boundary scan logic.

TDO O/T

Test Data Output (JTAG).

Serial scan output of the boundary scan path.

TMS I (pu)

Test Mode Select (JTAG).

Used to control the test state machine.

TCK I

Test Clock (JTAG).

Provides a clock for JTAG boundary scan. TCK must be asserted

(pulsed low) after power-up, or held low for proper operation of the ADSP-21367.

TRST I (pu)

Test Reset (JTAG).

Resets the test state machine. TRST must be asserted (pulsed low)

after power-up or held low for proper operation of the ADSP-21367.

EMU O/T (pu)

Emulation Status.

Must be connected to the ADSP-21367 Analog Devices DSP Tools

product line of JTAG emulator target board connectors only.

CLK_CFG

1–0

Core/CLKIN Ratio Control.

These pins set the start up clock frequency. See Table 8 for

a description of the clock configuration modes.

Note that the operating frequency can be changed by programming the PLL multiplier

and divider in the PMCTL register at any time after the core comes out of reset.

BOOT_CFG

1–0

Boot Configuration Select.

These pins select the boot mode for the processor. The

BOOTCFG pins must be valid before reset is asserted. See Table 7 for a description of the

boot modes.

RESET I

Processor Reset.

Resets the ADSP-21367 to a known state. Upon deassertion, there is

a 4096 CLKIN cycle latency for the PLL to lock. After this time, the core begins program

execution from the hardware reset vector address. The RESET input must be asserted

(low) at power-up.

Table 5. Pin List

Name Type

State During

/After Reset Description

Rev. PrD | Page 14 of 52 | April 2006

ADSP-21367 Preliminary Technical Data

DATA MODES

The upper 32 data pins of the external memory interface are

muxed (using bits in the SYSCTL register) to support the exter-

nal memory interface data (input/output), the PDAP (input

only), the FLAGS (input/output), and the PWM channels (out-

put). Table 6 provides the pin settings.

BOOT MODES CORE INSTRUCTION RATE TO CLKIN RATIO MODES

For details on processor timing, see Timing Specifications and

Figure 4 on Page 17.

XTAL O

Crystal Oscillator Terminal.

Us ed in conju nct ion w ith C LKIN to dr ive an ex te rn al cr yst al.

CLKIN I

Local Clock In.

Used with XTAL. CLKIN is the processor’s clock input. It configures the

ADSP-21367 to use either its internal clock generator or an external clock source. Con-

necting the necessary components to CLKIN and XTAL enables the internal clock

generator. Connecting the external clock to CLKIN while leaving XTAL unconnected

configures the ADSP-21367 to use an external clock such as an external clock oscillator.

CLKIN may not be halted, changed, or operated below the specified frequency.

CLKOUT O/T Driven low/

driven high

Local Clock Out.

CLKOUT can also be configured as a reset out pin.The functionality

can be switched between the PLL output clock and reset out by setting bit 12 of the

PMCTREG register. The default is reset out.

Pull-up can be enabled/disabled, value of pull-up cannot be programmed.

Table 5. Pin List

Name Type

State During

/After Reset Description

Table 6. Function of Data Pins

DATA PIN MODE DATA31–16 DATA15–8 DATA7–0

000 EPDATA32–0

001 FLAGS/PWM15–0

EPDATA15–0

010 FLAGS/PWM15–0

FLAGS15–8 EPDATA7–0

011 FLAGS/PWM15–0

FLAGS15–0

100 PDAP (DATA + CTRL) EPDATA7–0

101 PDAP (DATA + CTRL) FLAGS7–0

110 Reserved

111 Three-state all pins

These signals can be FLAGS or PWM or a mix of both. However, they can be selected only in groups of four. Their function is determined by the control

signals FLAGS/PWM_SEL. For more information, see the ADSP-2136x SHARC Processor Hardware Reference for the ADSP-21367/8/9 Processors.

Table 7. Boot Mode Selection

BOOTCFG1–0 Booting Mode

00 SPI Slave Boot

01 SPI Master Boot

10 EPROM/FLASH Boot

Table 8. Core Instruction Rate/ CLKIN Ratio Selection

CLKCFG1–0 Core to CLKIN Ratio

00 6:1

01 32:1

10 16:1

ADSP-21367Preliminary Technical Data

Rev. PrD | Page 15 of 52 | April 2006

ADSP-21367 SPECIFICATIONS

OPERATING CONDITIONS

ELECTRICAL CHARACTERISTICS

Parameter

Specifications subject to change without notice.

Min Max Unit

DDINT

Internal (Core) Supply Voltage 1.235 1.365 V

VDD

Analog (PLL) Supply Voltage 1.235 1.365 V

DDEXT

External (I/O) Supply Voltage 3.13 3.47 V

Applies to input and bidirectional pins: ACK, DATA31–0, FLAG3–0, DAI_Px, DPI_Px, BOOTCFGx, CLKCFGx, RESET, TCK, TMS, TDI, TRST.

High Level Input Voltage @ V

DDEXT

= max 2.0 V

DDEXT

+ 0.5 V

Low Level Input Voltage @ V

DDEXT

= min –0.5 +0.8 V

CLKIN

Applies to input pin CLKIN.

High Level Input Voltage @ V

DDEXT

= max 1.74 V

DDEXT

+ 0.5 V

CLKIN

Low Level Input Voltage @ V

DDEXT

= min –0.5 +1.19 V

Parameter

Test Conditions Min Typ Max Unit

High Level Output Voltage @ V

DDEXT

= min, I

= –1.0 mA

2.4 V

Low Level Output Voltage @ V

DDEXT

= min, I

= 1.0 mA

0.4 V

4, 5

High Level Input Current @ V

DDEXT

= max, V

= V

DDEXT

max 10 μA

Low Level Input Current @ V

DDEXT

= max, V

= 0 V 10 μA

ILPU

Low Level Input Current Pull-up @ V

DDEXT

= max, V

= 0 V 200 μA

OZH

6, 7

Three-State Leakage Current @ V

DDEXT

= max, V

= V

DDEXT

max 10 μA

OZL

Three-State Leakage Current @ V

DDEXT

= max, V

= 0 V 10 μA

OZLPU

Three-State Leakage Current Pull-up @ V

DDEXT

= max, V

= 0 V 200 μA

INTYP

8, 9

Supply Current (Internal) t

CCLK

= 3.0 ns, V

DDINT

= 1.3 900 mA

Supply Current (Analog) A

VDD

= max 10 mA

11,

Input Capacitance f

=1 MHz, T

CASE

=25°C, V

=1.3 V 4.7 pF

Specifications subject to change without notice.

Applies to output and bidirectional pins: ADDR23-0, DATA31-0, RD, WR, FLAG3–0, DAI_Px, DPI_Px, SDRAS, SDCAS, SDWE, SDCKE, SDA10, SDCLK0, MS0-1, EMU,

TDO, CLKOUT.

See Output Drive Currents on Page 41 for typical drive current capabilities.

Applies to input pins: BOOTCFGx, CLKCFGx, TCK, RESET, CLKIN.

Applies to input pins with internal pull-ups: ACK, TRST, TMS, TDI.

Applies to three-statable pins without pull-ups and those with pull-ups disabled: FLAG3:0, DAI_Px (pull-ups disabled), DPI_Px (pull-ups disabled), SDCLK0, and TDO.

Applies to three-statable pins with pull-ups: ADDR23-0, DATA31-0, RD, WR, DAI_Px, DPI_Px, SDRAS, SDCAS, SDWE, SDCKE, SDA10, MS0-1, EMU.

Typical internal current data reflects nominal operating conditions.

See Engineer-to-Engineer Note (No. TBD) for further information.

Characterized, but not tested.

Applies to all signal pins.

Guaranteed, but not tested.

Rev. PrD | Page 16 of 52 | April 2006

ADSP-21367 Preliminary Technical Data

PACKAGE INFORMATION

The information presented in Figure 3 provide details about the

package branding for the ADSP-21367 processor. For a com-

plete listing of product availability, see Ordering Guide on

Page 49.

MAXIMUM POWER DISSIPATION

See Engineer-to-Engineer Note (EE-TBD) for detailed thermal

and power information regarding maximum power dissipation.

For information on package thermal specifications, see Thermal

Characteristics on Page 42.

ABSOLUTE MAXIMUM RATINGS

Stresses greater than those listed in Table 10 may cause perma-

nent damage to the device. These are stress ratings only;

functional operation of the device at these or any other condi-

tions greater than those indicated in the operational sections of

this specification is not implied. Exposure to absolute maximum

rating conditions for extended periods may affect device

reliability.

ESD SENSITIVITY

Figure 3. Typical Package Brand

Table 9. Package Brand Information

Brand Key Field Description

t Temperature Range

pp Package Type

Z Lead Free Option (optional)

ccc See Ordering Guide

vvvvvv.x Assembly Lot Code

n.n Silicon Revision

yyww Date Code

vvvvvv.x n.n

tppZccc

ADSP-2136x

yyww country_of_origin

Table 10. Absolute Maximum Ratings

Parameter Rating

Internal (Core) Supply Voltage (V

DDINT

)–0.3 V to +1.5 V

Analog (PLL) Supply Voltage (A

VDD

)–0.3 V to +1.5 V

External (I/O) Supply Voltage (V

DDEXT

)–0.3 V to +4.6 V

Input Voltage –0.5 V to V

DDEXT

+0.5 V

Output Voltage Swing –0.5 V to V

DDEXT

+0.5 V

Load Capacitance 200 pF

Storage Temperature Range –65°C to +150°C

Junction Temperature under Bias 125°C

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection.

Although the ADSP-21367 features proprietary ESD protection circuitry, permanent damage may

occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD

precautions are recommended to avoid performance degradation or loss of functionality.

ADSP-21367Preliminary Technical Data

Rev. PrD | Page 17 of 52 | April 2006

TIMING SPECIFICATIONS

The ADSP-21367’s internal clock (a multiple of CLKIN) pro-

vides the clock signal for timing internal memory, processor

core, and serial ports. During reset, program the ratio between

the processor’s internal clock frequency and external (CLKIN)

clock frequency with the CLKCFG1–0 pins (see Table 8 on

Page 14). To determine switching frequencies for the serial

ports, divide down the internal clock, using the programmable

divider control of each port (DIVx for the serial ports).

The ADSP-21367’s internal clock switches at higher frequencies

than the system input clock (CLKIN). To generate the internal

clock, the processor uses an internal phase-locked loop (PLL).

This PLL-based clocking minimizes the skew between the sys-

tem clock (CLKIN) signal and the processor’s internal clock.

Figure 4 shows Core to CLKIN ratios of 6:1, 16:1, and 32:1 with

external oscillator or crystal. Note that more ratios are possible

and can be set through software using the power management

control register (PMCTL). For more information, see the ADSP-

2136x SHARC Processor Programming Reference.

Note the definitions of various clock periods shown in Table 12

which are a function of CLKIN and the appropriate ratio con-

trol shown in Table 11.

Use the exact timing information given. Do not attempt to

derive parameters from the addition or subtraction of others.

While addition or subtraction would yield meaningful results

for an individual device, the values given in this data sheet

reflect statistical variations and worst cases. Consequently, it is

not meaningful to add parameters to derive longer times. See

Figure 36 on page 41 under Test Conditions for voltage refer-

ence levels.

Switching Characteristics specify how the processor changes its

signals. Circuitry external to the processor must be designed for

compatibility with these signal characteristics. Switching char-

acteristics describe what the processor will do in a given

circumstance. Use switching characteristics to ensure that any

timing requirement of a device connected to the processor (such

as memory) is satisfied.

Timing Requirements apply to signals that are controlled by cir-

cuitry external to the processor, such as the data input for a read

operation. Timing requirements guarantee that the processor

operates correctly with other devices.

Figure 4. Core Clock and System Clock Relationship to CLKIN

PLLM

CLKIN

CCLK

(CORE CLOCK)

PLLICLK

XTAL

OSC

CLKOUT

CLK-CFG [1:0]

(6:1, 16:1, 32:1)

PCLK

(PERIPHERAL CLOCK)

INDIV

÷1, 2

DIVEN

÷2,4,8,16

SDCLK

(SDRAM CLOCK)

Table 11. ADSP-21367 CLKOUT and CCLK Clock

Generation Operation

Timing

Requirements Description Calculation

CLKIN Input Clock 1/t

CCLK Core Clock 1/t

CCLK

Table 12. Clock Periods

Timing

Requirements Description

where:

SR = serial port-to-core clock ratio (wide range, determined by SPORT CLKDIV

bits in DIVx register)

SPIR = SPI-to-core clock ratio (wide range, determined by SPIBAUD register

setting)

SPICLK = SPI clock

SDR = SDRAM-to-core clock ratio (values determined by bit 20 to bit 18 of the

PMCTL register)

CLKIN Clock Period

CCLK

(Processor) Core Clock Period

PCLK

(Peripheral) Clock Period = 2 × t

CCLK

SCLK

Serial Port Clock Period = (t

PCLK

) × SR

SDCLK

SDRAM Clock Period = (t

CCLK

) × SDR

SPICLK

SPI Clock Period = (t

PCLK

) × SPIR

Rev. PrD | Page 18 of 52 | April 2006

ADSP-21367 Preliminary Technical Data

Power-Up Sequencing

The timing requirements for processor startup are given in

Table 13.

Table 13. Power Up Sequencing Timing Requirements (Processor Startup)

Parameter Min Max Unit

Timing Requirements

RSTVDD

RESET Low Before V

DDINT

DDEXT

On 0 ns

IVDDEVDD

DDINT

On Before V

DDEXT

–50 +200 ms

CLKVDD

CLKIN Valid After V

DDINT

DDEXT

Valid 0 +200 ms

CLKRST

CLKIN Valid Before RESET Deasserted 10

μs

PLLRST

PLL Control Setup Before RESET Deasserted 20 μs

Switching Characteristic

CORERST

Core Reset Deasserted After RESET Deasserted 4096t

+ 2 t

CCLK

Valid V

DDINT

DDEXT

assumes that the supplies are fully ramped to their 1.3 volt rails and 3.3 volt rails. Voltage ramp rates can vary from microseconds to hundreds of

milliseconds depending on the design of the power supply subsystem.

Assumes a stable CLKIN signal, after meeting worst-case start-up timing of crystal oscillators. Refer to your crystal oscillator manufacturer’s data sheet for start-up time.

Assume a 25 ms maximum oscillator start-up time if using the XTAL pin and internal oscillator circuit in conjunction with an external crystal.

Applies after the power-up sequence is complete. Subsequent resets require a minimum of 4 CLKIN cycles for RESET to be held low in order to properly initialize and

propagate default states at all I/O pins.

The 4096 cycle count depends on t

SRST

specification in Table 15. If setup time is not met, 1 additional CLKIN cycle may be added to the core reset time, resulting in 4097

cycles maximum.

Figure 5. Power-Up Sequencing

CLKIN

RESET

tRSTVDD

RSTOUT

VDDEXT

VDDINT

tPLLRST

tCLKRST

tCLKVDD

tIVDDEVDD

CLK_CFG1-0

tCORERST

ADSP-21367Preliminary Technical Data

Rev. PrD | Page 19 of 52 | April 2006

Clock Input

Clock Signals

The ADSP-21367 can use an external clock or a crystal. See the

CLKIN pin description in Table 5. The programmer can config-

ure the ADSP-21367 to use its internal clock generator by

connecting the necessary components to CLKIN and XTAL.

Figure 7 shows the component connections used for a crystal

operating in fundamental mode. Note that the clock rate is

achieved using a 16.67 MHz crystal and a PLL multiplier ratio

16:1 (CCLK:CLKIN achieves a clock speed of 333 MHz). To

achieve the full core clock rate, programs need to configure the

multiplier bits in the PMCTL register.

Table 14. Clock Input

Parameter

333 MHz Unit

Min Max

Timing Requirements

CLKIN Period 18

Applies only for CLKCFG1–0 = 00 and default values for PLL control bits in PMCTL.

100

Applies only for CLKCFG1–0 = 10 and default values for PLL control bits in PMCTL.

CKL

CLKIN Width Low 8

CKH

CLKIN Width High 8

CKRF

CLKIN Rise/Fall (0.4 V to 2.0 V) 3 ns

CCLK

Any changes to PLL control bits in the PMCTL register must meet core clock timing specification t

CCLK

CCLK Period 3.0

10 ns

CKJ

4, 5

Actual input jitter should be combined with ac specifications for accurate timing analysis.

Jitter specification is maximum peak-to-peak time interval error (TIE) jitter.

CLKIN Jitter Tolerance –250 +250 ps

Figure 6. Clock Input

CLKIN

tCK

tCKH tCKL

Figure 7. 333 MHz Operation (Fundamental Mode Crystal)

22pF Y1

1M⍀(TYPICAL) XTAL

CLKIN

22pF

24.576MHz

47⍀(TYPICAL)

ADSP-2136X

R2 SHOULD BE CHOSEN TO LIMIT CRYSTAL DRIVE POWER.

Rev. PrD | Page 20 of 52 | April 2006

ADSP-21367 Preliminary Technical Data

Reset

Interrupts

The following timing specification applies to the FLAG0,

FLAG1, and FLAG2 pins when they are configured as IRQ0,

IRQ1, and IRQ2 interrupts.

Table 15. Reset

Parameter Min Max Unit

Timing Requirements

WRST

RESET Pulse Width Low 4t

SRST

RESET Setup Before CLKIN Low 8 ns

Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 100 μs while RESET is low, assuming

stable V

and CLKIN (not including start-up time of external clock oscillator).

Figure 8. Reset

CLKIN

RESET

tWRST tSRST

Table 16. Interrupts

Parameter Min Max Unit

Timing Requirement

IPW

IRQx Pulse Width 2 × t

PCLK

+2 ns

Figure 9. Interrupts

DAI_P20-1

DPI_14-1

FLAG2-0

(IRQ2-0) tIPW

ADSP-21367Preliminary Technical Data

Rev. PrD | Page 21 of 52 | April 2006

Core Timer

The following timing specification applies to FLAG3 when it is

configured as the core timer (CTIMER).

Timer PWM_OUT Cycle Timing

The following timing specification applies to Timer0, Timer1,

and Timer2 in PWM_OUT (pulse width modulation) mode.

Timer signals are routed to the DPI_P14–1 pins through the

SRU. Therefore, the timing specifications provided below are

valid at the DPI_P14–1 pins.

Table 17. Core Timer

Parameter Min Max Unit

Switching Characteristic

WCTIM

CTIMER Pulse width 4 × t

PCLK

– 1 ns

Figure 10. Core Timer

FLAG3

(CTIMER)

tWCTIM

Table 18. Timer PWM_OUT Timing

Parameter Min Max Unit

Switching Characteristic

PWMO

Timer Pulse Width Output 2 × t

PCLK

– 1 2 × (2

– 1) × t

PCLK

Figure 11. Timer PWM_OUT Timing

DPI14-1

(TIMER2-0)

tPWMO

Rev. PrD | Page 22 of 52 | April 2006

ADSP-21367 Preliminary Technical Data

Timer WDTH_CAP Timing

The following timing specification applies to Timer0, Timer1,

and Timer2 in WDTH_CAP (pulse width count and capture)

mode. Timer signals are routed to the DPI_P14–1 pins through

the SRU. Therefore, the timing specification provided below are

valid at the DPI_P14–1 pins.

Pin to Pin Direct Routing (DAI and DPI)

For direct pin connections only (for example DAI_PB01_I to

DAI_PB02_O).

Table 19. Timer Width Capture Timing

Parameter Min Max Unit

Timing Requirement

PWI

Timer Pulse Width 2 × t

PCLK

2 × (2

– 1) × t

PCLK

Figure 12. Timer Width Capture Timing

DPI_14-1

(TIMER2-0)

tPWI

Table 20. DAI Pin to Pin Routing

Parameter Min Max Unit

Timing Requirement

DPIO

Delay DAI/DPI Pin Input Valid to DAI Output Valid 1.5 10 ns

Figure 13. DAI Pin to Pin Direct Routing

DAI_Pn

DPI_Pn

tDPIO

DAI_Pm

DPI_Pm

ADSP-21367Preliminary Technical Data

Rev. PrD | Page 23 of 52 | April 2006

Precision Clock Generator (Direct Pin Routing)

This timing is only valid when the SRU is configured such that

the precision clock generator (PCG) takes its inputs directly

from the DAI pins (via pin buffers) and sends its outputs

directly to the DAI pins. For the other cases, where the PCG’s

inputs and outputs are not directly routed to/from DAI pins (via

pin buffers) there is no timing data available. All timing param-

eters and switching characteristics apply to external DAI pins

(DAI_P01 – DAI_P20).

Table 21. Precision Clock Generator (Direct Pin Routing)

Parameter Min Max Unit

Timing Requirements

PCGIP

Input Clock Period 24 ns

STRIG

PCG Trigger Setup Before Falling

Edge of PCG Input Clock

4.5 ns

HTRIG

PCG Trigger Hold After Falling

Edge of PCG Input Clock

3ns

Switching Characteristics

DPCGIO

PCG Output Clock and Frame Sync Active Edge Delay

After PCG Input Clock 2.5 10 ns

DTRIGCLK

PCG Output Clock Delay After PCG Trigger 2.5 + ((2.5 + D) × t

PCGIP

) 10 + ((2.5 + D) × t

PCGIP

)ns

DTRIGFS

PCG Frame Sync Delay After PCG Trigger 2.5 + ((2.5 + D – PH) × t

PCGIP

) 10 + ((2.5 + D – PH) × t

PCGIP

)ns

PCGOW

Output Clock Period 2 × t

PCGIP

– 1 ns

D = FSxDIV, PH = FSxPHASE. For more information, see the ADSP-2136x SHARC Processor Hardware Reference for the ADSP-21367/8/9 Processors,

“Precision Clock Generators” chapter.

In normal mode.

Figure 14. Precision Clock Generator (Direct Pin Routing)

DAI_Pn

DPI_Pn

PCG_TRIGx_I

tSTRIG

DAI_Pm

DPI_Pm

PCG_EXTx_I

(CLKIN)

DAI_Py

DPI_Py

PCG_CLKx_O

DAI_Pz

DPI_Pz

PCG_FSx_O

tHTRIG

tDPCGIO

tDTRIGFS

tPCGIP

tPCGOW

tDTRIGCLK tDPCGIO

Rev. PrD | Page 24 of 52 | April 2006

ADSP-21367 Preliminary Technical Data

Flags

The timing specifications provided below apply to the FLAG3–0

and DPI_P14–1 pins, and the serial peripheral interface (SPI).

See Table 5 for more information on flag use.

Table 22. Flags

Parameter Min Max Unit

Timing Requirement

FIPW

FLAG3–0 IN Pulse Width 2 × t

PCLK

+ 3 ns

Switching Characteristic

FOPW

FLAG3–0 OUT Pulse Width 2 × t

PCLK

– 1.5 ns

Figure 15. Flags

DPI_P14-1

(FLAG3-0IN)

(DATA31-0)

tFIPW

DPI_P14-1

(FLAG3-0OUT)

(DATA31-0)

tFOPW

ADSP-21367Preliminary Technical Data

Rev. PrD | Page 25 of 52 | April 2006

SDRAM Interface Timing (133 MHz SDCLK)

Table 23. SDRAM Interface Timing

For F

CCLK

= 333 MHz (SDCLK ratio = 1:2.5).

Parameter Min Max Unit

Timing Requirement

SSDAT

DATA Setup Before SDCLK 0.58 ns

HSDAT

DATA Hold After SDCLK 1.23 ns

Switching Characteristic

SCLK

SDCLK Period 7.5 ns

SCLKH

SDCLK Width High 3.65 ns

SCLKL

SDCLK Width Low 3.65 ns

DCAD

Command, ADDR, Data Delay After SDCLK

Command pins include: SDCAS, SDRAS, SDWE, MSx, SDA10, SDCKE.

4.8 ns

HCAD

Command, ADDR, Data Hold After SDCLK

1.5 ns

DSDAT

Data Disable After SDCLK 5.3 ns

ENSDAT

Data Enable After SDCLK 1.6 ns

Figure 16. SDRAM Interface Timing

tHCAD

tDSDAT

tSSDAT

tDCAD

tENSDAT

tHSDAT

tSCLKL

tSCLKH

tSCLK

SDCLK

DATA (IN)

DATA(OUT)

CMND ADDR

(OUT)

tDCAD

Rev. PrD | Page 26 of 52 | April 2006

ADSP-21367 Preliminary Technical Data

Memory Read—Bus Master

Use these specifications for asynchronous interfacing to memo-

ries. These specifications apply when the ADSP-21367 is the bus

master accessing external memory space in asynchronous access

mode. Note that timing for ACK, DATA, RD, WR, and strobe

timing parameters only apply to asynchronous access mode.

Table 24. Memory Read—Bus Master

Parameter Min Max Unit

Timing Requirements

DAD

Address, Selects Delay to Data Valid

1, 2

W+t

SDCLK

–5.12 ns

DRLD

RD Low to Data Valid

W– 2.9 ns

SDS

Data Setup to RD High 2.2 ns

HDRH

Data Hold from RD High

0ns

DAAK

ACK Delay from Address, Selects

2, 5

SDCLK

–9.5+ W ns

DSAK

ACK Delay from RD Low

W– 7.0 ns

Switching Characteristics

DRHA

Address Selects Hold After RD High RH + 0.38 ns

DARL

Address Selects to RD Low

SDCLK

–3.3 ns

RD Pulsewidth W – 1.1 ns

RWR

RD High to WR, RD, Low HI +t

SDCLK

– 0.8 ns

W = (number of wait states specified in AMICTLx register) × t

SDCLK

HI =RHC + IC (RHC = (number of Read Hold Cycles specified in AMICTLx register) × t

SDCLK

IC = (number of Idle Cycles specified in AMICTLx register) × t

SDCLK

H = (number of Hold Cycles specified in AMICTLx register) × t

SDCLK

Data Delay/Setup: System must meet t

DAD

, t

DRLD

, or t

SDS.

The falling edge of MSx, is referenced.

Note that timing for ACK, DATA, RD, WR, and strobe timing parameters only apply to asynchronous access mode.

Data Hold: User must meet t

HDA

or t

HDRH

in asynchronous access mode. See Test Conditions on Page 41 for the calculation of hold times given capacitive and dc loads.

ACK Delay/Setup: User must meet t

DAAK

, or t

DSAK

, for deassertion of ACK (Low). For asynchronous assertion of ACK (High) user must meet t

DAAK

or t

DSAK

Figure 17. Memory Read—Bus Master

ACK

DATA

tDARL tRW

tDAD

tDAAK

tHDRH

tRWR

tDRLD

tDRHA

tDSAK

tSDS

ADDRESS

MSx

ADSP-21367Preliminary Technical Data

Rev. PrD | Page 27 of 52 | April 2006

Memory Write— Bus Master

Use these specifications for asynchronous interfacing to memo-

ries. These specifications apply when the ADSP-21367 is the bus

master accessing external memory space in asynchronous access

mode. Note that timing for ACK, DATA, RD, WR, and strobe

timing parameters only apply to asynchronous access mode.

Table 25. Memory Write—Bus Master

Parameter Min Max Unit

Timing Requirements

DAAK

ACK Delay from Address, Selects

1, 2

SDCLK

– 9.7 + W ns

DSAK

ACK Delay from WR Low

1, 3

W – 4.9 ns

Switching Characteristics

DAWH

Address, Selects to WR Deasserted

SDCLK

–3.1+ W ns

DAWL

Address, Selects to WR Low

SDCLK

–2.7 ns

WR Pulsewidth W – 0.8 ns

DDWH

Data Setup Before WR High t

SDCLK

–3.0+ W ns

DWHA

Address Hold After WR Deasserted H + 0.15 ns

DWHD

Data Hold After WR Deasserted H + 0.02 ns

WWR

WR High to WR, RD Low t

SDCLK

–1.5+ H ns

DDWR

Data Disable Before RD Low 2t

SDCLK

– 4.11 ns

WDE

WR Low to Data Enabled t

SDCLK

– 3.5 ns

W = (number of wait states specified in AMICTLx register) × t

SDCLK

H = (number of hold cycles specified in AMICTLx register) × t

SDCLK

ACK Delay/Setup: System must meet t

DAAK

, or t

DSAK

, for deassertion of ACK (Low). For asynchronous assertion of ACK (High) user must meet t

DAAK

or t

DSAK

The falling edge of MSx is referenced.

Note that timing for ACK, DATA, RD, WR, and strobe timing parameters only applies to asynchronous access mode.

Figure 18. Memory Write—Bus Master

ACK

DATA

tDAWL tWW

tDAAK

tWWR

tWDE

tDDWR

tDWHA

tDAWH

tDSAK

tDDWH

tDWHD

ADDRESS

MSx

Rev. PrD | Page 28 of 52 | April 2006

ADSP-21367 Preliminary Technical Data

Serial Ports

To determine whether communication is possible between two

devices at clock speed n, the following specifications must be

confirmed: 1) frame sync delay and frame sync setup and hold,

2) data delay and data setup and hold, and 3) SCLK width.

Serial port signals (SCLK, FS, data channel A, data channel B)

are routed to the DAI_P20–1 pins using the SRU. Therefore, the

timing specifications provided below are valid at the

DAI_P20–1 pins.

Table 26. Serial Ports—External Clock

Parameter Min Max Unit

Timing Requirements

SFSE

FS Setup Before SCLK

(Externally Generated FS in either Transmit or Receive Mode) 2.5 ns

HFSE

FS Hold After SCLK

(Externally Generated FS in either Transmit or Receive Mode) 2.5 ns

SDRE

Receive Data Setup Before Receive SCLK 2.5 ns

HDRE

Receive Data Hold After SCLK 2.5 ns

SCLKW

SCLK Width 10 ns

SCLK

SCLK Period 20 ns

Switching Characteristics

DFSE

FS Delay After SCLK

(Internally Generated FS in either Transmit or Receive Mode) 9.5 ns

HOFSE

FS Hold After SCLK

(Internally Generated FS in either Transmit or Receive Mode) 2 ns

DDTE

Transmit Data Delay After Transmit SCLK 9.6 ns

HDTE

Transmit Data Hold After Transmit SCLK 2 ns

Referenced to sample edge.

Referenced to drive edge.

Table 27. Serial Ports—Internal Clock

Parameter Min Max Unit

Timing Requirements

SFSI

FS Setup Before SCLK

(Externally Generated FS in either Transmit or Receive Mode) 7 ns

HFSI

FS Hold After SCLK

(Externally Generated FS in either Transmit or Receive Mode) 2.5 ns

SDRI

Receive Data Setup Before SCLK 7 ns

HDRI

Receive Data Hold After SCLK 2.5 ns

Switching Characteristics

DFSI

FS Delay After SCLK (Internally Generated FS in Transmit Mode) 4 ns

HOFSI

FS Hold After SCLK (Internally Generated FS in Transmit Mode) –1.0 ns

DFSI

FS Delay After SCLK (Internally Generated FS in Receive Mode) 9 ns

HOFSI

FS Hold After SCLK (Internally Generated FS in Receive Mode) –1.0 ns

DDTI

Transmit Data Delay After SCLK 3 ns

HDTI

Transmit Data Hold After SCLK –1.0 ns

SCLKIW

Transmit or Receive SCLK Width 2 × t

PCLK

– 1.5 2 × t

PCLK

Referenced to the sample edge.

Referenced to drive edge.

Minimum SPORT divisor register value.

ADSP-21367Preliminary Technical Data

Rev. PrD | Page 29 of 52 | April 2006

Table 28. Serial Ports—Enable and Three-State

Parameter Min Max Unit

Switching Characteristics

DDTEN

Data Enable from External Transmit SCLK 2 ns

DDTTE

Data Disable from External Transmit SCLK 10 ns

DDTIN

Data Enable from Internal Transmit SCLK –1 ns

Referenced to drive edge.

Table 29. Serial Ports—External Late Frame Sync

Parameter Min Max Unit

Switching Characteristics

DDTLFSE

Data Delay from Late External Transmit FS or External Receive FS

with MCE = 1, MFD = 0 7.75 ns

DDTENFS

Data Enable for MCE = 1, MFD = 0 0.5 ns

The t

DDTLFSE

and t

DDTENFS

parameters apply to left-justified sample pair as well as DSP serial mode, and MCE = 1, MFD = 0.

Figure 19. External Late Frame Sync

This figure reflects changes made to support left-justified sample pair mode.

DRIVE SAMPLE DRIVE

DAI_P20-1

(SCLK)

DAI_P20-1

(FS)

DAI_P20-1

(DATA CHANNEL A/B)

DRIVE SAMPLE DRIVE

LATE EXTERNAL TRANSMIT FS

EXTERNAL RECEIVE FS WITH MCE = 1, MFD = 0

1ST BIT 2ND BIT

DAI_P20-1

(SCLK)

DAI_P20-1

(FS)

1ST BIT 2ND BIT

tHFSE/I

tSFSE/I

tDDTE/I

tDDTENFS

tDDTLFSE

tHDTE/I

tSFSE/I

tDDTE/I

tDDTENFS

tDDTLFSE

tHDTE/I

DAI_P20-1

(DATA CHANNEL A/B)

NOTE: SERIAL PORT SIGNALS (SCLK, FS, DATA CHANNEL A/B) ARE ROUTED TO THE DAI_P20-1 PINS

USING THE SRU. THE TIMING SPECIFICATIONS PROVIDED HERE ARE VALID AT THE DAI_P20-1 PINS.

tHFSE/I

Rev. PrD | Page 30 of 52 | April 2006

ADSP-21367 Preliminary Technical Data

Figure 20. Serial Ports

DAI_P20-1

(SCLK)

DAI_P20-1

(FS)

DRIVE EDGE SAMPLE EDGE

DATA RECEIVE— INTERNAL CLOCK DATA RECEIVE

—

TERNAL CLOCK

DRIVE EDGE SAMPLE EDGE

NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF SCLK (EXTERNAL), SCLK (INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE.

tSDRI tHDRI

tSFSI tHFSI

tDFSI

tHOFSI

tSCLKIW

tSDRE tHDRE

tSFSE tHFSE

tDFSE

tSCLKW

tHOFSE

DAI_P20-1

(DATA CHANNEL A/B)

tDDTI

DRIVE EDGE SAMPLE EDGE

DATA TRANSMIT — INTERNAL CLOCK

tSFSI tHFSI

tDFSI

tHOFSI

tSCLKIW

tHDTI

NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF SCLK (EXTERNAL), SCLK (INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE.

tDDTE

DRIVE EDGE SAMPLE EDGE

DATA TRANSMIT — EXTERNAL CLOCK

tSFSE tHFSE

tDFSE

tHOFSE

tSCLKW

tHDTE

DAI_P20-1

(SCLK)

DAI_P20-1

(FS)

DAI_P20-1

(DATA CHANNEL A/B)

DAI_P20-1

(SCLK)

DAI_P20-1

(FS)

DAI_P20-1

(DATA CHANNEL A/B)

DAI_P20-1

(SCLK)

DAI_P20-1

(FS)

DAI_P20-1

(DATA CHANNEL A/B)

DRIVE EDGE

DAI_P20-1

SCLK (INT)

DRIVE EDGE DRIVE EDGE

SCLKDAI_P20-1

SCLK (EXT)

tDDTTE

tDDTEN

tDDTIN

DAI_P20-1

(DATA CHANNEL A/B)

DAI_P20-1

(DATA CHANNEL A/B)

ADSP-21367Preliminary Technical Data

Rev. PrD | Page 31 of 52 | April 2006

Input Data Port

The timing requirements for the IDP are given in Table 30.

IDP Signals (SCLK, FS, SDATA) are routed to the DAI_P20–1

pins using the SRU. Therefore, the timing specifications pro-

vided below are valid at the DAI_P20–1 pins.

Table 30. IDP

Parameter Min Max Unit

Timing Requirements

SISFS

FS Setup Before SCLK Rising Edge 3.8 ns

SIHFS

FS Hold After SCLK Rising Edge 2.5 ns

SISD

SData Setup Before SCLK Rising Edge 2.5 ns

SIHD

SData Hold After SCLK Rising Edge 2.5 ns

IDPCLKW

Clock Width 9 ns

IDPCLK

Clock Period 24 ns

DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG's input can be either CLKIN or any of the DAI pins.

Figure 21. IDP Master Timing

DAI_P20-1

(SCLK)

DAI_P20-1

(FS)

SAMPLE EDGE

tSISFS tSIHFS

tIDPCLK

DAI_P20-1

(SDATA)

tIDPCLKW

tSISD tSIHD

Rev. PrD | Page 32 of 52 | April 2006

ADSP-21367 Preliminary Technical Data

Parallel Data Acquisition Port (PDAP)

The timing requirements for the PDAP are provided in

Table 31. PDAP is the parallel mode operation of channel 0 of

the IDP. For details on the operation of the IDP, see the IDP

chapter of the ADSP-2136x SHARC Processor Hardware

Reference for the ADSP-21367/8/9 Processors. Note that the most

significant 16 bits of external PDAP data can be provided

through the DATA31–16 pins. The remaining 4 bits can only be

sourced through DAI_P4–1. The timing below is valid at the

DATA31–16 pins.

Table 31. Parallel Data Acquisition Port (PDAP)

Parameter Min Max Unit

Timing Requirements

SPCLKEN

PDAP_CLKEN Setup Before PDAP_CLK Sample Edge 2.5 ns

HPCLKEN

PDAP_CLKEN Hold After PDAP_CLK Sample Edge 2.5 ns

PDSD

PDAP_DAT Setup Before SCLK PDAP_CLK Sample Edge 3.85 ns

PDHD

PDAP_DAT Hold After SCLK PDAP_CLK Sample Edge 2.5 ns

PDCLKW

Clock Width 7.0 ns

PDCLK

Clock Period 24 ns

Switching Characteristics

PDHLDD

Delay of PDAP Strobe After Last PDAP_CLK Capture Edge for a Word 2 × t

PCLK

+ 3 ns

PDSTRB

PDAP Strobe Pulse Width 2 × t

PCLK

– 1 ns

Source pins of DATA are ADDR7–0, DATA7–0, or DAI pins. Source pins for SCLK and FS are: 1) DAI pins, 2) CLKIN through PCG, or 3) DAI pins through PCG.

Figure 22. PDAP Timing

DAI_P20-1

(PDAP_CLK)

SAMPLE EDGE

tPDSD tPDHD

tSPCLKEN tHPCLKEN

tPDCLKW

DATA

DAI_P20-1

(PDAP_CLKEN)

tPDSTRB

tPDHLDD

DAI_P20-1

(PDAP_STROBE)

tPDCLK

ADSP-21367Preliminary Technical Data

Rev. PrD | Page 33 of 52 | April 2006

Pulse Width Modulation Generators

Sample Rate Converter—Serial Input Port

The SRC input signals (SCLK, FS, and SDATA) are routed from

the DAI_P20–1 pins using the SRU. Therefore, the timing spec-

ifications provided in Table 33 are valid at the DAI_P20–1 pins.

Table 32. PWM Timing

Parameter Min Max Unit

Switching Characteristics

PWMW

PWM Output Pulse Width t

PCLK

– 2 (2

– 2) × t

PCLK

– 2 ns

PWMP

PWM Output Period 2 × t

PCLK

– 1.5 (2

– 1) × t

PCLK

– 1.5 ns

Figure 23. PWM Timing

PWM

OUTPUTS

tPWMW

tPWMP

Table 33. SRC, Serial Input Port

Parameter Min Max Unit

Timing Requirements

SRCSFS

FS Setup Before SCLK Rising Edge 4 ns

SRCHFS

FS Hold After SCLK Rising Edge 5.5 ns

SRCSD

SDATA Setup Before SCLK Rising Edge 4 ns

SRCHD

SDATA Hold After SCLK Rising Edge 5.5 ns

SRCCLKW

Clock Width 9 ns

SRCCLK

Clock Period 24 ns

DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins.

Figure 24. SRC Serial Input Port Timing

DAI_P20-1

(SCLK)

DAI_P20-1

(FS)

SAMPLE EDGE

tSRCSFS tSRCHFS

tSRCCLK

DAI_P20-1

(SDATA)

tSRCCLKW

tSRCSD tSRCHD

Rev. PrD | Page 34 of 52 | April 2006

ADSP-21367 Preliminary Technical Data

Sample Rate Converter—Serial Output Port

For the serial output port, the frame-sync is an input and it

should meet setup and hold times with regard to SCLK on the

output port. The serial data output, SDATA, has a hold time

and delay specification with regard to SCLK. Note that SCLK

rising edge is the sampling edge and the falling edge is the drive

edge.

Table 34. SRC, Serial Output Port

Parameter Min Max Unit

Timing Requirements

SRCSFS

FS Setup Before SCLK Rising Edge 4 ns

SRCHFS

FS Hold Before SCLK Rising Edge 5.5 ns

SRCCLKW

Clock Width 9 ns

SRCCLK

Clock Period 24 ns

Switching Characteristics

SRCTDD

Transmit Data Delay After SCLK Falling Edge 8.9 ns

SRCTDH

Transmit Data Hold After SCLK Falling Edge 1 ns

SDATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG's input can be either CLKIN or any of the DAI pins.

Figure 25. SRC Serial Output Port Timing

DAI_P20-1

(SCLK)

DAI_P20-1

(FS)

tSRCSFS tSRCHFS

DAI_P20-1

(SDATA)

tSRCTDD

tSRCTDH

SAMPLE EDGE

tSRCCLK

tSRCCLKW

ADSP-21367Preliminary Technical Data

Rev. PrD | Page 35 of 52 | April 2006

SPDIF Transmitter

Serial data input to the SPDIF transmitter can be formatted as

left justified, I

S or right justified with word widths of 16, 18, 20,

or 24 bits. The following sections provide timing for the

transmitter.

SPDIF Transmitter—Serial Input Waveforms

Figure 26 shows the right-justified mode. LRCLK is HI for the

left channel and LO for the right channel. Data is valid on the

rising edge of SCLK. The MSB is delayed 12-bit clock periods

(in 20-bit output mode) or 16-bit clock periods (in 16-bit output

mode) from an LRCLK transition, so that when there are 64

SCLK periods per LRCLK period, the LSB of the data will be

right-justified to the next LRCLK transition.

Figure 27 shows the default I

S-justified mode. LRCLK is LO for

the left channel and HI for the right channel. Data is valid on the

rising edge of SCLK. The MSB is left-justified to an LRCLK

transition but with a single SCLK period delay.

Figure 28 shows the left-justified mode. LRCLK is HI for the left

channel and LO for the right channel. Data is valid on the rising

edge of SCLK. The MSB is left-justified to an LRCLK transition

with no MSB delay.

Figure 26. Right-Justified Mode

DAI

-1

LRCLK

DAI_P20-1

SCLK

DAI_P20-1

SDATA

LEFT CHANNEL RIGHT CHANNEL

MSB-1 MSB-2 LSB+2 LSB+1 LSB MSB MSB-1 MSB-2 LSB+2 LSB+1 LSB

LSB MSB

Figure 27. I

S-Justified Mode

MSB-1 MSB-2 LSB+2 LSB+1 LSB

LEFT CHANNEL

RIGHT CHANNEL

MSB MSB-1 MSB-2 LSB+2 LSB+1 LSB MSBMSB

DAI_P20-1

LRCLK

DAI_P20-1

SCLK

DAI_P20-1

SDATA

Figure 28. Left-Justified Mode

LEFT CHANNEL RIGHT CHANNEL

MSB-1 MSB-2 LSB+2 LSB+1 LSB MSB MSB-1 MSB-2 LSB+2 LSB +1 LSB MSB MSB+1

MSB

DAI_P20-1

LRCLK

DAI_P20-1

SCLK

DAI_P20-1

SDATA

Rev. PrD | Page 36 of 52 | April 2006

ADSP-21367 Preliminary Technical Data

SPDIF Transmitter Input Data Timing

The timing requirements for the Input port are given in

Table 35. Input Signals (SCLK, FS, SDATA) are routed to the

DAI_P20–1 pins using the SRU. Therefore, the timing specifica-

tions provided below are valid at the DAI_P20–1 pins.

Over Sampling Clock (TxCLK) Switching Characteristics

The SPDIF transmitter has an over sampling clock. This TxCLK

input is divided down to generate the biphase clock.

Table 35. SPDIF Transmitter Input Data Timing

Parameter Min Max Unit

Timing Requirements

SIFS

FS Setup Before SCLK Rising Edge 3 ns

SIHFS

FS Hold After SCLK Rising Edge 3 ns

SISD

SData Setup Before SCLK Rising Edge 3 ns

SIHD

SData Hold After SCLK Rising Edge 3 ns

SITXCLKW

Transmit Clock Width 9 ns

SITXCLK

Transmit Clock Period 20 ns

DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG's input can be either CLKIN or any of the DAI pins.

Figure 29. SPDIF Transmitter Input Timing

DAI_P20-1

(SCLK)

DAI_P20-1

(FS)

SAMPLE EDGE

tSISD

tSISFS

tSISCLKW

DAI_P20-1

(SDATA)

DAI_P20-1

(TXCLK)

tSIHD

tSIHFS

tSITXCLKW tSITXCLK

Table 36. Over Sampling Clock (TxCLK) Switching Characteristics

Parameter Min Max Unit

TxCLK Frequency for TxCLK = 768 × FS 147.5 MHz

TxCLK Frequency for TxCLK = 512 × FS 98.4 MHz

TxCLK Frequency for TxCLK = 384 × FS 73.8 MHz

TxCLK Frequency for TxCLK = 256 × FS 49.2 MHz

Frame Rate 192.0 kHz

ADSP-21367Preliminary Technical Data

Rev. PrD | Page 37 of 52 | April 2006

SPDIF Receiver

The following section describes timing as it relates to the SPDIF

receiver.

Internal Digital PLL Mode

In the internal digital phase-locked loop mode the internal PLL

(digital PLL) generates the 512 × FS clock.

Table 37. SPDIF Receiver Internal Digital PLL Mode Timing

Parameter Min Max Unit

Switching Characteristics

DFSI

LRCLK Delay After SCLK 5 ns

HOFSI

LRCLK Hold After SCLK –2 ns

DDTI

Transmit Data Delay After SCLK 5 ns

HDTI

Transmit Data Hold After SCLK –2 ns

SCLKIW

Transmit SCLK Width 38 ns

SCLK frequency is 64 × FS where FS = the frequency of LRCLK.

Figure 30. SPDIF Receiver Internal Digital PLL Mode Timing

DRIVE EDGE SAMPLE EDGE

DAI_P20-1

(SCLK)

DAI_P20-1

(FS)

DAI_P20-1

(DATA CHANNEL A/B)

tSCLKIW

tDFSI

tDDTI

tHOFSI

tHDTI

Rev. PrD | Page 38 of 52 | April 2006

ADSP-21367 Preliminary Technical Data

SPI Interface—Master

The ADSP-21367 contains two SPI ports. The primary has dedi-

cated pins and the secondary is available through the DPI. The

timing provided in Table 38 and Table 39 applies to both.

Table 38. SPI Interface Protocol — Master Switching and Timing Specifications

Parameter Min Max Unit

Timing Requirements

SSPIDM

Data Input Valid to SPICLK Edge (Data Input Set-up Time) 8 ns

HSPIDM

SPICLK Last Sampling Edge to Data Input Not Valid 2 ns

Switching Characteristics

SPICLKM

Serial Clock Cycle 8 × t

PCLK

– 1.5 ns

SPICHM

SErial Clock High Period 4 × t

PCLK

– 1.5 ns

SPICLM

Serial Clock Low Period 4 × t

PCLK

– 1.5 ns

DDSPIDM

SPICLK Edge to Data Out Valid (Data Out Delay Time) 2.5 ns

HDSPIDM

SPICLK Edge to Data Out Not Valid (Data Out Hold Time) 2 ns

SDSCIM

FLAG3–0IN (SPI Device Select) Low to First SPICLK Edge 4 × t

PCLK

– 2 ns

HDSM

Last SPICLK Edge to FLAG3–0IN High 4 × t

PCLK

– 2 ns

SPITDM

Sequential Transfer Delay 4 × t

PCLK

– 1 ns

Figure 31. SPI Master Timing

LSB

VALID

MSB

VALID

tSSPIDM tHSPIDM

tHDSPIDM

LSBMSB

tHSPIDM

tDDSPIDM

MOSI

(OUTPUT)

MISO

(INPUT)

FLAG3-0

(OUTPUT)

SPICLK

(CP = 0)

(OUTPUT)

SPICLK

(CP = 1)

(OUTPUT)

tSPICHM tSPICLM

tSPICLM

tSPICLKM

tSPICHM

tHDSM tSPITDM

tHDSPIDM

LSB

VALID

LSBMSB

MSB

VALID

tHSPIDM

tDDSPIDM

MOSI

(OUTPUT)

MISO

(INPUT)

tSSPIDM

CPHASE = 1

tSDSCIM

CPHASE = 0

tSSPIDM

ADSP-21367Preliminary Technical Data

Rev. PrD | Page 39 of 52 | April 2006

SPI Interface—Slave

Table 39. SPI Interface Protocol —Slave Switching and Timing Specifications

Parameter Min Max Unit

Timing Requirements

SPICLKS

Serial Clock Cycle 4 × t

PCLK

– 2 ns

SPICHS

Serial Clock High Period 2 × t

PCLK

– 2 ns

SPICLS

Serial Clock Low Period 2 × t

PCLK

– 2 ns

SDSCO

SPIDS Assertion to First SPICLK Edge

CPHASE = 0

CPHASE = 1

2 × t

PCLK

2 × t

PCLK

HDS

Last SPICLK Edge to SPIDS Not Asserted, CPHASE = 0 2 × t

PCLK

SSPIDS

Data Input Valid to SPICLK Edge (Data Input Set-up Time) 2 ns

HSPIDS

SPICLK Last Sampling Edge to Data Input Not Valid 2 ns

SDPPW

SPIDS Deassertion Pulse Width (CPHASE = 0) 2 × t

PCLK

Switching Characteristics

DSOE

SPIDS Assertion to Data Out Active 0 6.8 ns

DSDHI

SPIDS Deassertion to Data High Impedance 0 6.8 ns

DDSPIDS

SPICLK Edge to Data Out Valid (Data Out Delay Time) 9.4 ns

HDSPIDS

SPICLK Edge to Data Out Not Valid (Data Out Hold Time) 2 × t

PCLK

DSOV

SPIDS Assertion to Data Out Valid (CPHASE = 0) 5 × t

PCLK

Figure 32. SPI Slave Timing

tHSPIDS

tDDSPIDS

tDSDHI

LSBMSB

MSB VALID

tDSOE tDDSPIDS

tHDSPIDS

MISO

(OUTPUT)

MOSI

(INPUT)

tSSPIDS

SPIDS

(INPUT)

SPICLK

(CP = 0)

(INPUT)

SPICLK

(CP = 1)

(INPUT)

tSDSCO

tSPICHS tSPICLS

tSPICLS

tSPICLKS tHDS

tSPICHS

tSSPIDS tHSPIDS

tDSDHI

LSB VALID

MSB

MSB VALID

tDSOE

tDDSPIDS

MISO

(OUTPUT)

MOSI

(INPUT)

tSSPIDS

LSB VALID

LSB

CPHASE = 1

CPHASE = 0

tSDPPW

tDSOV tHDSPIDS

Rev. PrD | Page 40 of 52 | April 2006

ADSP-21367 Preliminary Technical Data

JTAG Test Access Port and Emulation

Table 40. JTAG Test Access Port and Emulation

Parameter Min Max Unit

Timing Requirements

TCK

TCK Period t

STAP

TDI, TMS Setup Before TCK High 5 ns

HTAP

TDI, TMS Hold After TCK High 6 ns

SSYS

System Inputs Setup Before TCK High 7 ns

HSYS

System Inputs Hold After TCK High 18 ns

TRSTW

TRST Pulse Width 4t

Switching Characteristics

DTDO

TDO Delay from TCK Low 7 ns

DSYS

System Outputs Delay After TCK Low t

÷ 2 + 7 ns

System Inputs = AD15–0, SPIDS, CLKCFG1–0, RESET, BOOTCFG1–0, MISO, MOSI, SPICLK, DAI_Px, FLAG3–0.

System Outputs = MISO, MOSI, SPICLK, DAI_Px, AD15–0, RD, WR, FLAG3–0, CLKOUT, EMU.

Figure 33. IEEE 1149.1 JTAG Test Access Port

TCK

TMS

TDI

TDO

SYSTEM

INPUTS

SYSTEM

OUTPUTS

tSTAP

tTCK

tHTAP

tDTDO

tSSYS tHSYS

tDSYS

ADSP-21367Preliminary Technical Data

Rev. PrD | Page 41 of 52 | April 2006

OUTPUT DRIVE CURRENTS

Figure 34 shows typical I-V characteristics for the output driv-

ers of the ADSP-21367. The curves represent the current drive

capability of the output drivers as a function of output voltage.

TEST CONDITIONS

The ac signal specifications (timing parameters) appear

Table 15 on Page 20 through Table 40 on Page 40. These include

output disable time, output enable time, and capacitive loading.

The timing specifications for the SHARC apply for the voltage

reference levels in Figure 35.

Timing is measured on signals when they cross the 1.5 V level as

described in Figure 36. All delays (in nanoseconds) are mea-

sured between the point that the first signal reaches 1.5 V and

the point that the second signal reaches 1.5 V.

CAPACITIVE LOADING

Output delays and holds are based on standard capacitive loads:

30 pF on all pins (see Figure 35). Figure 39 shows graphically

how output delays and holds vary with load capacitance. The

graphs of Figure 37, Figure 38, and Figure 39 may not be linear

outside the ranges shown for typical output delay vs. load capac-

itance and typical output rise time (20% to 80%, v = min) vs.

load capacitance.

Figure 34. ADSP-21367 Typical Drive

Figure 35. Equivalent Device Loading for AC Measurements

(Includes All Fixtures)

Figure 36. Voltage Reference Levels for AC Measurements

SWEEP (VDDEXT) VOLTAGE (V)

03.50.5 1.0 1.5 2.0 2.5 3.0

SOURCE(V

DDEXT

)CURRENT(mA)

VOL

3.11V, 125° C

3.3V, 25° C

3.47V,

45° C

VOH

3.11V, 125° C

3.3V, 25° C

3.47V,

45° C

1.5V

30pF

OUTPUT

50⍀

INPUT

OUTPUT

1.5V 1.5V

Figure 37. Typical Output Rise/Fall Time (20% to 80%,

DDEXT

= Max)

Figure 38. Typical Output Rise/Fall Time (20% to 80%,

DDEXT

= Min)

LOAD CAPACITANCE (pF)

0100 250

RISEANDFALLTIMES(ns)

20015050

FALL

y = 0.0467x + 1.6323

y = 0.045x + 1.524

RISE

LOAD CAPACITANCE (pF)

0 50 100 150 200 250

RISEANDFALLTIMES(ns)

RISE

FALL

y = 0.049x + 1.5105

y = 0.0482x + 1.4604

Rev. PrD | Page 42 of 52 | April 2006

ADSP-21367 Preliminary Technical Data

THERMAL CHARACTERISTICS

The ADSP-21367 processor is rated for performance over the

temperature range specified in Operating Conditions on

Page 15.

Table 41 and Table 42 airflow measurements comply with

JEDEC standards JESD51-2 and JESD51-6 and the junction-to-

board measurement complies with JESD51-8. Test board design

complies with JEDEC standards JESD51-9 (SBGA). The junc-

tion-to-case measurement complies with MIL- STD-883. All

measurements use a 2S2P JEDEC test board.

To determine the junction temperature of the device while on

the application PCB, use:

where:

= junction temperature (°C)

= case temperature (°C) measured at the top center of the

package

= junction-to-top (of package) characterization parameter is

the typical value from Table 41 and Table 42.

= power dissipation (see EE Note No. EE-277 for more

information).

Values of θ

are provided for package comparison and PCB

design considerations. θ

can be used for a first order approxi-

mation of T

by the equation:

where:

= Ambient Temperature °C

Values of θ

are provided for package comparison and PCB

design considerations when an external heatsink is required.

Values of θ

are provided for package comparison and PCB

design considerations. Note that the thermal characteristics val-

ues provided in Table 41 and Table 42 are modeled values.

Figure 39. Typical Output Delay or Hold vs. Load Capacitance

(at Ambient Temperature)

LOAD CAPACITANCE (pF)

0 20050 100 150

OUTPUTDELAYORHOLD(ns)

-4

-2

Y = 0.0488x - 1.5923

TJTTΨJT PD

×()+=

TJTA

JA PD

×()+=

Table 41. Thermal Characteristics for 256 Ball SBGA (No

thermal vias in PCB)

Parameter Condition Typical Unit

Airflow = 0 m/s 12.5 °C/W

JMA

Airflow = 1 m/s 10.6 °C/W

JMA

Airflow = 2 m/s 9.9 °C/W

0.7 °C/W

5.3 °C/W

Airflow = 0 m/s 0.3 °C/W

JMT

Airflow = 1 m/s 0.3 °C/W

JMT

Airflow = 2 m/s 0.3 °C/W

Table 42. Thermal Characteristics for 208-Lead MQFP

Parameter Condition Typical Unit

Airflow = 0 m/s 25.0 °C/W

JMA

Airflow = 1 m/s 22.5 °C/W

JMA

Airflow = 2 m/s 21.6 °C/W

9.6 °C/W

Airflow = 0 m/s 0.7 °C/W

JMT

Airflow = 1 m/s 0.8 °C/W

JMT

Airflow = 2 m/s 0.9 °C/W

ADSP-21367Preliminary Technical Data

Rev. PrD | Page 43 of 52 | April 2006

256-BALL SBGA PINOUT

Table 43. 256-Ball SBGA Pin Assignment (Numerically by Ball Number)

Ball No. Signal Ball No. Signal Ball No. Signal Ball No. Signal

A01 NC B01 DAI5 C01 DAI9 D01 DAI10

A02 TDI B02 NC C02 DAI7 D02 DAI6

A03 TMS B03 TRST C03 GND D03 GND

A04 CLK_CFG0 B04 TCK C04 V

DDEXT

D04 V

DDEXT

A05 CLK_CFG1 B05 BOOTCFG_0 C05 GND D05 GND

A06 EMU B06 BOOTCFG_1 C06 GND D06 V

DDEXT

A07 DAI4 B07 TDO C07 V

DDINT

D07 V

DDINT

A08 DAI1 B08 DAI3 C08 GND D08 GND

A09 DPI14 B09 DAI2 C09 GND D09 V

DDEXT

A10 DPI12 B10 DPI13 C10 V

DDINT

D10 V

DDINT

A11 DPI10 B11 DPI11 C11 GND D11 GND

A12 DPI9 B12 DPI8 C12 GND D12 V

DDEXT

A13 DPI7 B13 DPI5 C13 V

DDINT

D13 V

DDINT

A14 DPI6 B14 DPI4 C14 GND D14 GND

A15 DPI3 B15 DPI1 C15 GND D15 V

DDEXT

A16 DPI2 B16 RESET C16 V

DDINT

D16 GND

A17 CLKOUT B17 DATA30 C17 V

DDINT

D17 V

DDEXT

A18 DATA31 B18 DATA29 C18 V

DDINT

D18 GND

A19 NC B19 DATA28 C19 DATA27 D19 DATA26

A20 NC B20 NC C20 NC D20 DATA24

E01 DAI11 F01 DAI14 G01 DAI15 H01 DAI17

E02 DAI8 F02 DAI12 G02 DAI13 H02 DAI16

E03 V

DDINT

F03 GND G03 GND H03 V

DDINT

E04 V

DDINT

F04 GND G04 V

DDEXT

H04 V

DDINT

E17 GND F17 V

DDEXT

G17 V

DDINT

H17 V

DDEXT

E18 GND F18 GND G18 V

DDINT

H18 GND

E19 DATA25 F19 GND G19 DATA22 H19 DATA19

E20 DATA23 F20 DATA21 G20 DATA20 H20 DATA18

J01DAI19 K01FLAG0 L01FLAG2 M01ACK

J02 DAI18 K02 DAI20 L02 FLAG1 M02 FLAG3

J03GND K03GND L03V

DDINT

M03 GND

J04GND K04V

DDEXT

L04 V

DDINT

M04 GND

Rev. PrD | Page 44 of 52 | April 2006

ADSP-21367 Preliminary Technical Data

J17GND K17V

DDINT

L17 V

DDINT

M17 V

DDEXT

J18GND K18V

DDINT

L18 V

DDINT

M18 GND

J19GND K19GND L19DATA15 M19DATA12

J20 DATA17 K20 DATA16 L20 DATA14 M20 DATA13

N01 RD P01 SDA10 R01 SDWE T01 SDCKE

N02 SDCLK0 P02 WR R02 SDRAS T02 SDCAS

N03 GND P03 V

DDINT

R03 GND T03 GND

N04 V

DDEXT

P04 V

DDINT

R04 GND T04 V

DDEXT

N17 GND P17 V

DDINT

R17 V

DDEXT

T17 GND

N18 GND P18 V

DDINT

R18 GND T18 GND

N19 DATA11 P19 DATA8 R19 DATA6 T19 DATA5

N20 DATA10 P20 DATA9 R20 DATA7 T20 DATA4

U01 MS0 V01 ADDR22 W01 GND Y01 GND

U02 MS1 V02 ADDR23 W02 ADDR21 Y02 NC

U03 V

DDINT

V03 V

DDINT

W03 ADDR19 Y03 NC

U04 GND V04 GND W04 ADDR20 Y04 ADDR18

U05 V

DDEXT

V05 GND W05 ADDR17 Y05 NC

U06 GND V06 GND W06 ADDR16 Y06 NC

U07 V

DDEXT

V07 GND W07 ADDR15 Y07 XTAL2

U08 V

DDINT

V08 V

DDINT

W08 ADDR14 Y08 CLKIN

U09 V

DDEXT

V09 GND W09 A

VDD

Y09 NC

U10 GND V10 GND W10 A

VSS

Y10 NC

U11 V

DDEXT

V11 GND W11 ADDR13 Y11 NC

U12 V

DDINT

V12 V

DDINT

W12 ADDR12 Y12 NC

U13 V

DDEXT

V13 V

DDEXT

W13 ADDR10 Y13 ADDR11

U14 V

DDEXT

V14 GND W14 ADDR8 Y14 ADDR9

U15 V

DDINT

V15 V

DDINT

W15 ADDR5 Y15 ADDR7

U16 V

DDEXT

V16 GND W16 ADDR4 Y16 ADDR6

U17 V

DDINT

V17 GND W17 ADDR1 Y17 ADDR3

U18 V

DDINT

V18 GND W18 ADDR2 Y18 GND

U19 DATA0 V19 DATA1 W19 ADDR0 Y19 GND

U20 DATA2 V20 DATA3 W20 NC Y20 NC

Table 43. 256-Ball SBGA Pin Assignment (Numerically by Ball Number) (Continued)

Ball No. Signal Ball No. Signal Ball No. Signal Ball No. Signal

ADSP-21367Preliminary Technical Data

Rev. PrD | Page 45 of 52 | April 2006

Figure 40 shows the top view of the SBGA ball configuration.

Figure 41 shows the bottom view of the SBGA ball

configuration.

Figure 40. 256-Ball SBGA Ball Configuration (Bottom View)

1214

15 13

1719

20 18

NO CONNECT

VDDINT

I/O SIGNALS GND

KEY

VDDEXT AVSS

AVDD

BOTTOM

VIEW

Figure 41. 256-Ball SBGA Ball Configuration (Top View)

12345678910 11 12 14 1513 16 17 19 2018

NO CONNECT

VDDINT

I/O SIGNALS GND

KEY

VDDEXT AVSS

AVDD

TOP

VIEW

Rev. PrD | Page 46 of 52 | April 2006

ADSP-21367 Preliminary Technical Data

208-LEAD MQFP PINOUT

Table 44. 208-Lead MQFP Pin Assignment (Numerically by Lead Number)

Pin No. Signal Pin No. Signal Pin No. Signal Pin No. Signal

1 VDD 53 VDD 105 VDD 157 VDD

2 DATA28 54 GND 106 GND 158 VDD

3 DATA27 55 IOVDD 107 IOVDD 159 GND

4 GND 56 ADDR0 108 SDCAS 160 VDD

5 IOVDD 57 ADDR2 109 SDRAS 161 VDD

6 DATA26 58 ADDR1 110 SDCKE 162 VDD

7 DATA25 59 ADDR4 111 SDWE 163 TDI

8DATA24 60ADDR3 112WR 164 TRST

9 DATA23 61 ADDR5 113 SDA10 165 TCK

10 GND 62 GND 114 GND 166 GND

11 VDD 63 VDD 115 IOVDD 167 VDD

12 DATA22 64 GND 116 SDCLK0 168 TMS

13 DATA21 65 IOVDD 117 GND 169 CLK_CFG0

14 DATA20 66 ADDR6 118 VDD 170 BOOTCFG0

15 IOVDD 67 ADDR7 119 RD 171 CLK_CFG1

16 GND 68 ADDR8 120 ACK 172 EMU

17 DATA19 69 ADDR9 121 FLAG3 173 BOOTCFG1

18 DATA18 70 ADDR10 122 FLAG2 174 TDO

19 VDD 71 GND 123 FLAG1 175 DAI4

20 GND 72 VDD 124 FLAG0 176 DAI2

21 DATA17 73 GND 125 DAI20 177 DAI3

22 VDD 74 IOVDD 126 GND 178 DAI1

23 GND 75 ADDR11 127 VDD 179 IOVDD

24 VDD 76 ADDR12 128 GND 180 GND

25 GND 77 ADDR13 129 IOVDD 181 VDD

26 DATA16 78 GND 130 DAI19 182 GND

27 DATA15 79 VDD 131 DAI18 183 DPI14

28 DATA14 80 AVSS 132 DAI17 184 DPI13

29 DATA13 81 AVDD 133 DAI16 185 DPI12

30 DATA12 82 GND 134 DAI15 186 DPI11

31 IOVDD 83 CLKIN 135 DAI14 187 DPI10

32 GND 84 XTAL2 136 DAI13 188 DPI9

33 VDD 85 IOVDD 137 DAI12 189 DPI8

34 GND 86 GND 138 VDD 190 DPI7

35 DATA11 87 VDD 139 IOVDD 191 IOVDD

36 DATA10 88 ADDR14 140 GND 192 GND

37 DATA9 89 GND 141 VDD 193 VDD

38 DATA8 90 IOVDD 142 GND 194 GND

39 DATA7 91 ADDR15 143 DAI11 195 DPI6

40 DATA6 92 ADDR16 144 DAI10 196 DPI5

41 IOVDD 93 ADDR17 145 DAI8 197 DPI4

42 GND 94 ADDR18 146 DAI9 198 DPI3

43 VDD 95 GND 147 DAI6 199 DPI1

44 DATA4 96 IOVDD 148 DAI7 200 DPI2

ADSP-21367Preliminary Technical Data

Rev. PrD | Page 47 of 52 | April 2006

PACKAGE DIMENSIONS

Figure 42 shows the package dimensions of the 256-ball SBGA

and Figure 43 the dimensions of the 208-lead MQFP. All

dimensions are in millimeters.

45 DATA5 97 ADDR19 149 DAI5 201 CLKOUT

46 DATA2 98 ADDR20 150 IOVDD 202 RESET

47 DATA3 99 ADDR21 151 GND 203 IOVDD

48 DATA0 100 ADDR23 152 VDD 204 GND

49 DATA1 101 ADDR22 153 GND 205 DATA30

50 IOVDD 102 MS1 154 VDD 206 DATA31

51 GND 103 MS0 155 GND 207 DATA29

52 VDD 104 VDD 156 VDD 208 VDD

Table 44. 208-Lead MQFP Pin Assignment (Numerically by Lead Number) (Continued)

Pin No. Signal Pin No. Signal Pin No. Signal Pin No. Signal

Figure 42. 256-Ball SBGA, Thermally Enhanced (BP-256)

1.27

NOM

1.70 MAX

0.90

0.75

0.60

BALL

DIAMETER

TOP VIEW

A1 BALL

INDICATOR

DIMENSIONS ARE IN MILLIMETERS AND COMPLY

WITH JEDEC STANDARD MO-192-BAL-2.

1214

15 13

1719

20 18

BOTTOM

VIEW

27.00

BSC SQ

24.13

REF SQ

A1 CORNER

INDEX AREA

0.70

0.60

0.50

1.00

0.80

0.60

0.10

MIN

SEATING

PLANE

0.20

COPLANARITY

0.25 MIN 4X

Rev. PrD | Page 48 of 52 | April 2006

ADSP-21367 Preliminary Technical Data

SURFACE MOUNT DESIGN

Table 45 is provided as an aide to PCB design. For industry-

standard design recommendations, refer to IPC-7351, Generic

Requirements for Surface Mount Design and Land Pattern

Standard.

Figure 43. 208-Lead MQFP (S-208-2)

0.20

0.09

3.60

3.40

3.20

0.50

0.25 0.08 MAX

(LEAD COPLANARITY)

VIEW A

ROTATED 90° CCW

208 157

156

105

10453

TOP VIEW

(PINS DOWN)

0.50

BSC

28.20

28.00 SQ

27.80

0.27

0.17

(LEAD PITCH) (LEAD WIDTH)

SEATING

PLANE

4.10

MAX

0.75

0.60

0.45

NOTES:

1.THEACTUALPOSITIONOFEACHLEADISWITHIN0.08FROMITSIDEAL

POSITION WHEN MEASURED IN THE LATERAL DIRECTION.

2. CENTER DIMENSIONS ARE TYPICAL UNLESS OTHERWISE NOTED.

3. DIMENSIONS ARE IN MILLIMETERS AND COMPLY WITH JEDEC

STANDARD MS-029, FA-1.

30.85

30.60 SQ

30.35

VIEW A

PIN 1 INDICATOR

Table 45. BGA Data for Use with Surface Mount Design

Package Ball Attach Type

Solder Mask

Opening Ball Pad Size

256-Lead Ball Grid

Array BGA (BP-256)

Solder Mask Defined

(SMD)

0.63 mm 0.73 mm

ADSP-21367Preliminary Technical Data

Rev. PrD | Page 49 of 52 | April 2006

ORDERING GUIDE

Analog Devices offers a wide variety of audio algorithms and

combinations to run on the ADSP-21367 processor. These

products are sold as part of a chip set, bundled with necessary

application software under special part numbers. For a complete

list, visit our web site at www.analog.com/SHARC.

These product also may contain third party IPs that may require

users to have authorization from the respective IP holders to

receive them. Royalty for use of the 3rd party IPs may also be

payable by users.

Part Number

Temperature

Range

Instruction

Rate

On-Chip

SRAM ROM

Operating

Voltage

Internal/External

Package

Description

Package

Option

ADSP-21367KSZ-X

0°C to +70°C 266 MHz 2M bit 6M bit 1.2 V/3.3 V 208-Lead MQFP S-208-2

ADSP-21367KBP-X 0°C to +70°C 333 MHz 2M bit 6M bit 1.3 V/3.3 V 256-Ball SBGA BP-256

ADSP-21367KBPZ-X

0°C to +70°C 333 MHz 2M bit 6M bit 1.3 V/3.3 V 256-Ball SBGA BP-256

Referenced temperature is ambient temperature.

Z = Pb-free part.

Rev. PrD | Page 50 of 52 | April 2006

ADSP-21367 Preliminary Technical Data

ADSP-21367Preliminary Technical Data

Rev. PrD | Page 51 of 52 | April 2006

Rev. PrD | Page 52 of 52 | April 2006

ADSP-21367 Preliminary Technical Data

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