© Semiconductor Components Industries, LLC, 2011
May, 2011 − Rev. 13
1Publication Order Number:
MC74HC595A/D
MC74HC595A
8-Bit Serial-Input/Serial or
Parallel-Output Shift
Register with Latched
3-State Outputs
High−Performance Silicon−Gate CMOS
The MC74HC595A consists of an 8−bit shift register and an 8−bit
D−type latch with three−state parallel outputs. The shift register
accepts serial data and provides a serial output. The shift register also
provides parallel data to the 8−bit latch. The shift register and latch
have independent clock inputs. This device also has an asynchronous
reset for the shift register.
The HC595A directly interfaces with the SPI serial data port on
CMOS MPUs and MCUs.
Features
•Output Drive Capability: 15 LSTTL Loads
•Outputs Directly Interface to CMOS, NMOS, and TTL
•Operating Voltage Range: 2.0 to 6.0 V
•Low Input Current: 1.0 mA
•High Noise Immunity Characteristic of CMOS Devices
•In Compliance with the Requirements Defined by JEDEC
Standard No. 7 A
•Chip Complexity: 328 FETs or 82 Equivalent Gates
•Improvements over HC595
−Improved Propagation Delays
−50% Lower Quiescent Power
−Improved Input Noise and Latchup Immunity
•These Devices are Pb−Free, Halogen Free and are RoHS Compliant
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MARKING
DIAGRAMS
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G, G= Pb−Free Package
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
ORDERING INFORMATION
SOIC−16
D SUFFIX
CASE 751B
TSSOP−16
DT SUFFIX
CASE 948F
1
16
PDIP−16
N SUFFIX
CASE 648
1
16
1
16
1
16
MC74HC595AN
AWLYYWWG
1
16
HC595AG
AWLYWW
HC
595A
ALYWG
G
1
16
(Note: Microdot may be in either location)
MC74HC595A
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2
LOGIC DIAGRAM
SERIAL
DATA
INPUT
14
11
10
12
13
SHIFT
CLOCK
RESET
LATCH
CLOCK
OUTPUT
ENABLE
SHIFT
REGISTER LATCH
15
1
2
3
4
5
6
7
9
QA
QB
QC
QD
QE
QF
QG
QH
SQH
A
VCC = PIN 16
GND = PIN 8
PARALLEL
DATA
OUTPUTS
SERIAL
DATA
OUTPUT
PIN ASSIGNMENT
13
14
15
16
9
10
11
125
4
3
2
1
8
7
6
LATCH CLOCK
OUTPUT ENABLE
A
QA
VCC
SQH
RESET
SHIFT CLOCK
QE
QD
QC
QB
GND
QH
QG
QF
ORDERING INFORMATION
Device Package Shipping†
MC74HC595ANG PDIP−16
(Pb−Free)
500 Units / Rail
MC74HC595ADG SOIC−16
(Pb−Free)
48 Units / Rail
MC74HC595ADR2G SOIC−16
(Pb−Free)
2500 Tape & Reel
MC74HC595ADTR2G TSSOP−16*
(Pb−Free)
2500 Tape & Reel
MC74HC595AFELG SOEIAJ−16
(Pb−Free)
2000 Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
MC74HC595A
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3
MAXIMUM RATINGS
Symbol Parameter Value Unit
VCC DC Supply Voltage (Referenced to GND) –0.5 to +7.0 V
Vin DC Input Voltage (Referenced to GND) –0.5 to VCC+0.5 V
Vout DC Output Voltage (Referenced to GND) –0.5 to VCC+0.5 V
Iin DC Input Current, per Pin ±20 mA
Iout DC Output Current, per Pin ±35 mA
ICC DC Supply Current, VCC and GND Pins ±75 mA
PDPower Dissipation in Still Air, Plastic DIP†
SOIC Package†
TSSOP Package†
750
500
450
mW
Tstg Storage Temperature –65 to +150 _C
TLLead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP, SOIC or TSSOP Package) 260
_C
VESD ESD Withstand Voltage Human Body Model (Note 1)
Machine Model (Note 2)
Charged Device Model (Note 3)
>3000
>400
N/A
V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress
ratings only. Functional operation above the Recommended Operating Conditions is not implied.
Extended exposure to stresses above the Recommended Operating Conditions may affect device
reliability.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: − 6.1 mW/_C from 65_ to 125_C
1. Tested to EIA/JESD22−A114−A.
2. Tested to EIA/JESD22−A115−A.
3. Tested to JESD22−C101−A.
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
VCC DC Supply Voltage (Referenced to GND) 2.0 6.0 V
Vin, Vout DC Input Voltage, Output Voltage
(Referenced to GND)
0 VCC V
TAOperating Temperature, All Package Types – 55 + 125 _C
tr, tfInput Rise and Fall Time VCC = 2.0 V
(Figure 1) VCC = 4.5 V
VCC = 6.0 V
0
0
0
1000
500
400
ns
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Symbol Parameter Test Conditions
VCC
V
Guaranteed Limit
Unit
– 55 to 25_Cv 85_Cv 125_C
VIH Minimum High−Level Input
Voltage
Vout = 0.1 V or VCC – 0.1 V
|Iout| v 20 mA
2.0
3.0
4.5
6.0
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
V
VIL Maximum Low−Level Input
Voltage
Vout = 0.1 V or VCC – 0.1 V
|Iout| v 20 mA
2.0
3.0
4.5
6.0
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
V
VOH Minimum High−Level Output
Voltage, QA − QH
Vin = VIH or VIL
|Iout| v 20 mA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
Vin = VIH or VIL |Iout| v 2.4 mA
|Iout| v 6.0 mA
|Iout| v 7.8 mA
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.2
3.7
5.2
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
cuit. For proper operation, Vin and
Vout should be constrained to the
range GND v (Vin or Vout) v VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
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4
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Symbol Unit
Guaranteed Limit
VCC
V
Test ConditionsParameter
Symbol Unit
v 125_Cv 85_C– 55 to 25_C
VCC
V
Test ConditionsParameter
VOL Maximum Low−Level Output
Voltage, QA − QH
Vin = VIH or VIL
|Iout| v 20 mA
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
Vin = VIH or VIL |Iout| v 2.4 mA
|Iout| v 6.0 mA
|Iout| v 7.8 mA
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.4
0.4
0.4
VOH Minimum High−Level Output
Voltage, SQH
Vin = VIH or VIL
IIoutI v 20 mA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
Vin = VIH or VIL |Iout| v 2.4 mA
IIoutI v 4.0 mA
IIoutIv 5.2 mA
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.2
3.7
5.2
VOL Maximum Low−Level Output
Voltage, SQH
Vin = VIH or VIL
IIoutI v 20 mA
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
Vin = VIH or VIL |Iout| v 2.4 mA
IIoutI v 4.0 mA
IIoutIv 5.2 mA
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.4
0.4
0.4
Iin Maximum Input Leakage
Current
Vin = VCC or GND 6.0 ±0.1 ±1.0 ±1.0 mA
IOZ Maximum Three−State
Leakage
Current, QA − QH
Output in High−Impedance State
Vin = VIL or VIH
Vout = VCC or GND
6.0 ±0.5 ±5.0 ±10 mA
ICC Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
lout = 0 mA
6.0 4.0 40 160 mA
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)
Symbol Parameter
VCC
V
Guaranteed Limit
Unit
– 55 to 25_Cv 85_Cv 125_C
fmax Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 7)
2.0
3.0
4.5
6.0
6.0
15
30
35
4.8
10
24
28
4.0
8.0
20
24
MHz
tPLH,
tPHL
Maximum Propagation Delay, Shift Clock to SQH
(Figures 1 and 7)
2.0
3.0
4.5
6.0
140
100
28
24
175
125
35
30
210
150
42
36
ns
tPHL Maximum Propagation Delay, Reset to SQH
(Figures 2 and 7)
2.0
3.0
4.5
6.0
145
100
29
25
180
125
36
31
220
150
44
38
ns
tPLH,
tPHL
Maximum Propagation Delay, Latch Clock to QA − QH
(Figures 3 and 7)
2.0
3.0
4.5
6.0
140
100
28
24
175
125
35
30
210
150
42
36
ns
tPLZ,
tPHZ
Maximum Propagation Delay, Output Enable to QA − QH
(Figures 4 and 8)
2.0
3.0
4.5
6.0
150
100
30
26
190
125
38
33
225
150
45
38
ns
tPZL,
tPZH
Maximum Propagation Delay, Output Enable to QA − QH
(Figures 4 and 8)
2.0
3.0
4.5
6.0
135
90
27
23
170
110
34
29
205
130
41
35
ns
MC74HC595A
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5
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)
Symbol Unit
Guaranteed Limit
VCC
V
Parameter
Symbol Unit
v 125_Cv 85_C– 55 to 25_C
VCC
V
Parameter
tTLH,
tTHL
Maximum Output Transition Time, QA − QH
(Figures 3 and 7)
2.0
3.0
4.5
6.0
60
23
12
10
75
27
15
13
90
31
18
15
ns
tTLH,
tTHL
Maximum Output Transition Time, SQH
(Figures 1 and 7)
2.0
3.0
4.5
6.0
75
27
15
13
95
32
19
16
110
36
22
19
ns
Cin Maximum Input Capacitance — 10 10 10 pF
Cout Maximum Three−State Output Capacitance (Output in
High−Impedance State), QA − QH
— 15 15 15 pF
CPD Power Dissipation Capacitance (Per Package)*
Typical @ 25°C, VCC = 5.0 V
pF
300
TIMING REQUIREMENTS (Input tr = tf = 6.0 ns)
Symbol Parameter
VCC
V
Guaranteed Limit
Unit
25_C to –55_Cv 85_Cv 125_C
tsu Minimum Setup Time, Serial Data Input A to Shift Clock
(Figure 5)
2.0
3.0
4.5
6.0
50
40
10
9.0
65
50
13
11
75
60
15
13
ns
tsu Minimum Setup Time, Shift Clock to Latch Clock
(Figure 6)
2.0
3.0
4.5
6.0
75
60
15
13
95
70
19
16
110
80
22
19
ns
thMinimum Hold Time, Shift Clock to Serial Data Input A
(Figure 5)
2.0
3.0
4.5
6.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
ns
trec Minimum Recovery Time, Reset Inactive to Shift Clock
(Figure 2)
2.0
3.0
4.5
6.0
50
40
10
9.0
65
50
13
11
75
60
15
13
ns
twMinimum Pulse Width, Reset
(Figure 2)
2.0
3.0
4.5
6.0
60
45
12
10
75
60
15
13
90
70
18
15
ns
twMinimum Pulse Width, Shift Clock
(Figure 1)
2.0
3.0
4.5
6.0
50
40
10
9.0
65
50
13
11
75
60
15
13
ns
twMinimum Pulse Width, Latch Clock
(Figure 6)
2.0
3.0
4.5
6.0
50
40
10
9.0
65
50
13
11
75
60
15
13
ns
tr, tfMaximum Input Rise and Fall Times
(Figure 1)
2.0
3.0
4.5
6.0
1000
800
500
400
1000
800
500
400
1000
800
500
400
ns
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6
FUNCTION TABLE
Operation
Inputs Resulting Function
Reset
Serial
Input
A
Shift
Clock
Latch
Clock
Output
Enable
Shift
Register
Contents
Latch
Register
Contents
Serial
Output
SQH
Parallel
Outputs
QA − QH
Reset shift register L X X L, H, ↓L L U L U
Shift data into shift
register
H D ↑L, H, ↓L D →SRA;
SRN →SRN+1
U SRG →SRHU
Shift register remains
unchanged
H X L, H, ↓L, H, ↓L U U U U
Transfer shift register
contents to latch
register
H X L, H, ↓ ↑ L U SRN →LRNU SRN
Latch register remains
unchanged
X X X L, H, ↓L * U * U
Enable parallel outputs X X X X L * ** * Enabled
Force outputs into high
impedance state
X X X X H * ** * Z
SR = shift register contents D = data (L, H) logic level ↑ = Low−to−High * = depends on Reset and Shift Clock inputs
LR = latch register contents U = remains unchanged ↓ = High−to−Low ** = depends on Latch Clock input
PIN DESCRIPTIONS
INPUTS
A (Pin 14)
Serial Data Input. The data on this pin is shifted into the
8−bit serial shift register.
CONTROL INPUTS
Shift Clock (Pin 11)
Shift Register Clock Input. A low− to−high transition on
this input causes the data at the Serial Input pin to be shifted
into the 8−bit shift register.
Reset (Pin 10)
Active−low, Asynchronous, Shift Register Reset Input. A
low on this pin resets the shift register portion of this device
only. The 8−bit latch is not affected.
Latch Clock (Pin 12)
Storage Latch Clock Input. A low−to−high transition on
this input latches the shift register data.
Output Enable (Pin 13)
Active−low Output Enable. A low on this input allows the
data from the latches to be presented at the outputs. A high
on this input forces the outputs (QA−QH) into the
high−impedance state. The serial output is not affected by
this control unit.
OUTPUTS
QA − QH (Pins 15, 1, 2, 3, 4, 5, 6, 7)
Noninverted, 3−state, latch outputs.
SQH (Pin 9)
Noninverted, Serial Data Output. This is the output of the
eighth stage of the 8−bit shift register. This output does not
have three−state capability.
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7
SWITCHING WAVEFORMS
SERIAL
INPUT A 50%
50%
SWITCH
CLOCK
VCC
GND
VALID
tsu th
Figure 5.
SHIFT
CLOCK
OUTPUT
SQH
trtf
VCC
GND
90%
50%
10%
90%
50%
10%
tPLH tPHL
tTLH tTHL
tw
1/fmax
RESET
OUTPUT
SQH
SHIFT
CLOCK
tw
50%
50%
50%
VCC
GND
VCC
GND
tPHL
trec
tsu
50%
50%
VCC
GND
LATCH
CLOCK
QA-QH
OUTPUTS
50%
tPLH tPHL
tTLH tTHL
90%
50%
10%
VCC
GND
VCC
GND
SHIFT
CLOCK
LATCH
CLOCK
Figure 3.
VCC
GND tw
Figure 1. Figure 2.
Figure 4.
Figure 6.
OUTPUT Q
OUTPUT Q
50%
50%
90%
10%
tPZL tPLZ
tPZH tPHZ
VCC
GND
HIGH
IMPEDANCE
VOL
VOH
HIGH
IMPEDANCE
OUTPUT
ENABLE
50%
TEST CIRCUITS
*Includes all probe and jig capacitance
CL*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
*Includes all probe and jig capacitance
CL*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
CONNECT TO VCC WHEN
TESTING tPLZ AND tPZL.
CONNECT TO GND WHEN
TESTING tPHZ AND tPZH.
1 kW
Figure 7. Figure 8.
MC74HC595A
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8
D
R
Q
SRA
DQ
LRA
DQ
SRB
DQ
LRB
R
DQ
SRC
DQ
LRC
R
DQ
SRD
DQ
LRD
R
DQ
SRE
DQ
LRE
R
DQ
SRF
DQ
LRF
R
DQ
SRG
DQ
LRG
R
DQ
SRH
DQ
LRH
R
EXPANDED LOGIC DIAGRAM
OUTPUT
ENABLE
LATCH
CLOCK
SERIAL
DATA
INPUT A
SHIFT
CLOCK
RESET
13
12
14
11
10
15
1
2
3
4
5
6
7
9
QA
QB
QC
QD
QE
QF
QG
QH
SERIAL
DATA
OUTPUT SQH
PARALLEL
DATA
OUTPUTS
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9
TIMING DIAGRAM
SHIFT
CLOCK
SERIAL DATA
INPUT A
RESET
LATCH
CLOCK
OUTPUT
ENABLE
QA
QB
QC
QD
QE
QF
QG
QH
SERIAL DATA
OUTPUT SQH
NOTE: implies that the output is in a high−impedance
state.
MC74HC595A
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10
PACKAGE DIMENSIONS
PDIP−16
N SUFFIX
CASE 648−08
ISSUE T NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS
WHEN FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE
MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
−A−
B
FC
S
H
GD
J
L
M
16 PL
SEATING
18
916
K
PLANE
−T−
M
A
M
0.25 (0.010) T
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A0.740 0.770 18.80 19.55
B0.250 0.270 6.35 6.85
C0.145 0.175 3.69 4.44
D0.015 0.021 0.39 0.53
F0.040 0.70 1.02 1.77
G0.100 BSC 2.54 BSC
H0.050 BSC 1.27 BSC
J0.008 0.015 0.21 0.38
K0.110 0.130 2.80 3.30
L0.295 0.305 7.50 7.74
M0 10 0 10
S0.020 0.040 0.51 1.01
____
0.25 (0.010) T B A
MS S
MIN MINMAX MAX
MILLIMETERS INCHES
DIM
A
B
C
D
F
G
J
K
M
P
R
9.80
3.80
1.35
0.35
0.40
0.19
0.10
0°
5.80
0.25
10.00
4.00
1.75
0.49
1.25
0.25
0.25
7°
6.20
0.50
0.386
0.150
0.054
0.014
0.016
0.008
0.004
0°
0.229
0.010
0.393
0.157
0.068
0.019
0.049
0.009
0.009
7°
0.244
0.019
1.27 BSC 0.050 BSC
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
18
916
−A
−
−B
−
D16PL
K
C
G
−T
−
SEATING
PLANE
R X 45°
MJ
F
P 8 PL
0.25 (0.010) B
M M
SOIC−16
D SUFFIX
CASE 751B−05
ISSUE K
6.40
16X
0.58
16X 1.12
1.27
DIMENSIONS: MILLIMETERS
1
PITCH
SOLDERING FOOTPRINT
16
89
8X
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11
PACKAGE DIMENSIONS
TSSOP−16
DT SUFFIX
CASE 948F−01
ISSUE B
ÇÇÇ
ÇÇÇ
ÇÇÇ
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A4.90 5.10 0.193 0.200
B4.30 4.50 0.169 0.177
C−−− 1.20 −−− 0.047
D0.05 0.15 0.002 0.006
F0.50 0.75 0.020 0.030
G0.65 BSC 0.026 BSC
H0.18 0.28 0.007 0.011
J0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
K0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L6.40 BSC 0.252 BSC
M0 8 0 8
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
____
SECTION N−N
SEATING
PLANE
IDENT.
PIN 1
18
16 9
DETAIL E
J
J1
B
C
D
A
K
K1
H
G
ÉÉ
ÉÉ
DETAIL E
F
M
L
2X L/2
−U−
S
U0.15 (0.006) T
S
U0.15 (0.006) T
S
U
M
0.10 (0.004) V S
T
0.10 (0.004)
−T−
−V−
−W−
0.25 (0.010)
16X REFK
N
N
7.06
16X
0.36 16X
1.26
0.65
DIMENSIONS: MILLIMETERS
1
PITCH
SOLDERING FOOTPRINT
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MC74HC595A/D
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