AD7172-4 Data Sheet
Rev. B | Page 42 of 61
INTEGRATED FUNCTIONS
The AD7172-4 has integrated functions that improve the
usefulness of a number of applications as well as serve
diagnostic purposes in safety conscious applications.
GENERAL-PURPOSE INPUT/OUTPUT
The AD7172-4 has two digital GPIO pins (GPIO0 and GPIO1)
and two general-purpose digital output pins (GPO2 and
GPO3). As the naming convention suggests, the GPIO0 and
GPIO1 pins can be configured as inputs or outputs, but GPO2
and GPO3 are outputs only. The GPIOx and GPOx pins are
enabled using the following bits in the GPIOCON register:
IP_EN0, IP_EN1 (or OP_EN0, OP_EN1) for GPIO0 and
GPIO1, and OP_EN2_3 for GPO2 and GPO3.
When the GPIO0 pin or the GPIO1 pin is enabled as an input,
the logic level at the pin is contained in the GP_DATA0 or
GP_DATA1 bit, respectively. When the GPIO0, GPIO1, GPO2,
or GPO3 pin is enabled as an output, the GP_DATA0, GP_DATA1,
GP_DATA2, or GP_DATA3 bit, respectively, determine the logic
level output at the pin. The logic levels for these pins are referenced
to AVDD1 and AVSS.
The ERROR pin can also be used as a general-purpose output.
When the ERR_EN bits in the GPIOCON register are set to 11,
the ERROR pin operates as a general-purpose output. In this
configuration, the ERR_DAT bit in the GPIOCON register
determines the logic level output at the pin. The logic level for
the pin is referenced to IOVDD and DGND.
All general-purpose outputs have an active pull-up.
EXTERNAL MULTIPLEXER CONTROL
If an external multiplexer is used to increase the channel count,
the multiplexer logic pins can be controlled via the AD7172-4
GPIOx pins. With the MUX_IO bit, the GPIOx timing is controlled
by the ADC; therefore, the channel change is synchronized with
the ADC, eliminating any need for external synchronization.
DELAY
It is possible to insert a programmable delay before the AD7172-4
begins to take samples. This delay allows an external amplifier
or multiplexer to settle and can also alleviate the specification
requirements for the external amplifier or multiplexer. Eight
programmable settings, ranging from 0 μs to 8 ms, can be set using
the delay bits in the ADC mode register (Register 0x01, Bits[10:8]).
If a delay greater than 0 μs is selected and the HIDE_DELAY bit
in the ADC mode register is set to 0, this delay is added to the
conversion time, regardless of the selected output data rate.
When using the sinc5 + sinc1 filter, it is possible to hide this
delay such that the output data rate remains the same as the output
data rate without the delay enabled. If the HIDE_DELAY bit is
set to 1 and the selected delay is less than half of the conversion
time, the delay can be absorbed by reducing the number of
averages the digital filter performs, which keeps the conversion
time the same but can affect the noise performance.
The effect on the noise performance depends on the delay time
compared to the conversion time. It is possible to absorb the
delay only for output data rates less than 2.6 kSPS with the
exception of the following four rates, which cannot absorb any
delay: 381 SPS, 59.52 SPS, 49.68 SPS, and 16.66 SPS.
16-BIT/24-BIT CONVERSIONS
By default, the AD7172-4 generates 24-bit conversions.
However, the width of the conversions can be reduced to 16 bits.
Setting the WL16 bit in the interface mode register to 1 rounds
all data conversions to 16 bits. Clearing this bit sets the width of
the data conversions to 24 bits.
DOUT_RESET
The serial interface uses a shared DOUT/RDY pin. By default,
this pin outputs the RDY signal. During a data read, this pin
outputs the data from the register being read. After the read is
complete, the pin reverts to outputting the RDY signal after a short
fixed period of time (t7). However, this time may be too short for
some microcontrollers and can be extended until the CS pin is
brought high by setting the DOUT_RESET bit in the interface
mode register to 1. This setting means that CS must frame each
read operation and compete the serial interface transaction.
SYNCHRONIZATION
Normal Synchronization
When the SYNC_EN bit in the GPIOCON register is set to 1,
the SYNC pin functions as a synchronization input. The SYNC
input allows the user to reset the modulator and the digital filter
without affecting any of the setup conditions on the device. This
feature allows the user to start to gather samples of the analog
input from a known point, the rising edge of the SYNC input.
The SYNC input must be low for at least one master clock cycle
to ensure that synchronization occurs.
If multiple AD7172-4 devices are operated from a common master
clock, they can be synchronized so that their analog inputs are
sampled simultaneously. This synchronization is typically
completed after each AD7172-4 device has performed its own
calibration or has calibration coefficients loaded into its
calibration registers. A falling edge on the SYNC input resets the
digital filter and the analog modulator and places the AD7172-4
into a consistent known state. While the SYNC input is low, the
AD7172-4 is maintained in this known state. On the SYNC
input rising edge, the modulator and filter are taken out of this
reset state, and on the next master clock edge, the device starts to
gather input samples again.
The device is taken out of reset on the master clock falling edge
following the SYNC input low to high transition. Therefore, when
multiple devices are being synchronized, take the SYNC input
high on the master clock rising edge to ensure that all devices
are released on the master clock falling edge. If the SYNC input
is not taken high in sufficient time, a difference of one master