74ABT573ADB@118 - NXP SEMICONDUCTORS

This is information on a product in full production.

February 2015 DocID14733 Rev 13 1/117

STM8S207xx STM8S208xx

Performance line, 24 MHz STM8S 8-bit MCU, up to 128 KB Flash,

integrated EEPROM, 10-bit ADC, timers, 2 UARTs, SPI, I²C, CAN

Datasheet - production data

Features

Core

–Max f

CPU: up to 24 MHz, 0 wait states @

fCPU 16 MHz

– Advanced STM8 core with Harvard

architecture and 3-stage pipeline

– Extended instruction set

– Max 20 MIPS @ 24 MHz

Memories

– Program: up to 128 Kbytes Flash; data

retention 20 years at 55 °C after 10 kcycles

–Data: up to 2 Kbytes true data EEPROM;

endurance 300 kcycles

– RAM: up to 6 Kbytes

Clock, reset and supply management

– 2.95 to 5.5 V operating voltage

– Low power crystal resonator oscillator

– External clock input

– Internal, user-trimmable 16 MHz RC

– Internal low power 128 kHz RC

– Clock security system with clock monitor

– Wait, active-halt, & halt low power modes

– Peripheral clocks switched off individually

– Permanently active, low consumption

power-on and power-down reset

Interrupt management

– Nested interrupt controller with 32

interrupts

– Up to 37 external interrupts on 6 vectors

Timers

– 2x 16-bit general purpose timers, with 2+3

CAPCOM channels (IC, OC or PWM)

– Advanced control timer: 16-bit, 4 CAPCOM

channels, 3 complementary outputs, dead-

time insertion and flexible synchronization

– 8-bit basic timer with 8- bit presca ler

– Auto wakeup timer

– Window watchdog, independent watchdog

Communications interfaces

– High speed 1 Mbit/s active beCAN 2.0B

– UART with clock output for synchron ous

operation - LIN master mode

– UART with LIN 2.1 compliant, master/slave

modes and automatic resynchronization

– SPI interface up to 10 Mbit/s

–I

2C interface up to 400 Kbit/s

10-bit ADC with up to 16 channels

I/Os

– Up to 68 I/Os on an 80-pin package

including 18 high sink outputs

– Highly robust I/O design, immune against

current injection

– Development support

– Single wire interface module (SWIM) and

debug module (DM)

96-bit unique ID key for each device

Table 1. Device summary

Reference Part number

STM8S207xx

STM8S207MB, STM8S207M8, STM8S207RB,

STM8S207R8, STM8S207R6, STM8S207CB,

STM8S207C8, STM8S207C6, STM8S207SB,

STM8S207S8, STM8S207S6, STM8S 207K8,

STM8S207K6

STM8S208xx

STM8S208MB, STM8S208RB, STM8S208R8,

STM8S208R6, STM8S208CB, STM8S208C8,

STM8S208C6, STM8S208SB, STM8S208S8,

STM8S208S6

LQFP80 LQFP64

LQFP32

LQFP44

LQFP64

LQFP48

7 x 7 mm 10 x 10mm 7 x 7 mm

14 x 14 mm 14 x 14 mm 10 x 10 mm

www.st.com

Contents STM8S207xx STM8S208xx
2/117 DocID14733 Rev 13
Contents
Introduction  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Block diagram  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Product overview   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1 Central processing unit STM8  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  13
2 Single wire interface module (SWIM) and debug module (DM) . . . . . . . .  14
3 Interrupt controller  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  14
4 Flash program and data EEPROM memory . . . . . . . . . . . . . . . . . . . . . . .  14
5 Clock controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  16
6 Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  17
7 Watchdog timers   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  17
8 Auto wakeup counter  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  18
9 Beeper  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  18
10 TIM1 - 16-bit advanced control timer  . . . . . . . . . . . . . . . . . . . . . . . . . . . .  18
11 TIM2, TIM3 - 16-bit general purpose timers . . . . . . . . . . . . . . . . . . . . . . .  18
12 TIM4 - 8-bit basic timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  19
13 Analog-to-digital converter (ADC2)   . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  19
14 Communication interfaces  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  19
14.1 UART1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
14.2 UART3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
14.3 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
14.4 I2C  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
14.5 beCAN  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1 Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  23
2 Alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  32
Memory and register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
1 Memory map   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  34

DocID14733 Rev 13 3/117
STM8S207xx STM8S208xx Contents
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2 Register map  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  35
Interrupt vector mapping  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Option bytes   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Unique ID  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Electrical characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
1 Parameter conditions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  52
1.1 Minimum and maximum values  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
1.2 Typical values   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
1.3 Typical curves  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
1.4 Typical current consumption  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
1.5 Pin loading conditions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
1.6 Loading capacitor   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
1.7 Pin input voltage  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  54
3 Operating conditions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  56
3.1 VCAP external capacitor  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
3.2 Supply current characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
3.3 External clock sources and timing characteristics . . . . . . . . . . . . . . . . . 65
3.4 Internal clock sources and timing characteristics   . . . . . . . . . . . . . . . . . 67
3.5 Memory characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
3.6 I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
3.7 Reset pin characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
3.8 SPI serial peripheral interface  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
3.9 I2C interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
3.10 10-bit ADC characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
3.11 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Package characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
1 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  92
1.1 LQFP80 package information  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
1.2 LQFP64 package information  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
1.3 LQFP48 package information  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
1.4 LQFP44 package information  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Contents STM8S207xx STM8S208xx
4/117 DocID14733 Rev 13
1.5 LQFP32 package information  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
2 Thermal characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  108
2.1 Reference document  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
2.2 Selecting the product temperature range   . . . . . . . . . . . . . . . . . . . . . . 109
STM8 development tools  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
1 Emulation and in-circuit debugging tools  . . . . . . . . . . . . . . . . . . . . . . . . .110
2 Software tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
2.1 STM8 toolset  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
2.2 C and assembly toolchains  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
3 Programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
Ordering information   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Revision history   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

DocID14733 Rev 13 5/117
STM8S207xx STM8S208xx List of tables
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List of tables
Table 1. Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. STM8S20xxx performance line features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 3. Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers. . . . . . . . . . . . . . . 16
Table 4. TIM timer features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 5. Legend/abbreviations for pinout table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 6. Pin description  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 7. Flash, Data EEPROM and RAM boundary addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 8. I/O port hardware register map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 9. General hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 10. CPU/SWIM/debug module/interrupt controller registers. . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 11. Interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 12. Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 13. Option byte description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 14. Unique ID registers (96 bits). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 15. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 16. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 17. Thermal characte ris t ics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 18. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 19. Operating conditions at power-up/power-down  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 20. Total current consumption with code execution in run mode at VDD = 5 V. . . . . . . . . . . . . 58
Table 21. Total current consumption with code execution in run mode at VDD = 3.3 V . . . . . . . . . . . 59
Table 22. Total current consumption in wait mode at VDD = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 23. Total current consumption in wait mode at VDD = 3.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 24. Total current consumption in active halt mode at VDD = 5 V, TA -40 to 85° C . . . . . . . . . . 61
Table 25. Total current consumption in active halt mode at VDD = 3.3 V . . . . . . . . . . . . . . . . . . . . . . 61
Table 26. Total current consumption in halt mode at VDD = 5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 27. Total current consumption in halt mode at VDD = 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 28. Wakeup times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 29. Total current consumption and timing in forced reset state . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 30. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 31. HSE user external clock charact er i stics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 32. HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 33. HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 34. L SI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 35. RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 36. Flash program memory/data EEPROM memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 37. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 38. Output driving current (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 39. Output driving current (true open drain ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 40. Output driving current (high sink ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 41. NRST pin characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 42. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 43. I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 44. ADC characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 45. ADC ac cu ra cy with  R AIN < 10 k, VDDA = 5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 46. ADC ac cu ra cy with  R AIN < 10 kRAIN, VDDA = 3.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 47. EMS data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 48. EMI data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

List of tables STM8S207xx STM8S208xx
6/117 DocID14733 Rev 13
Table 49. ESD ab so lut e ma xim u m ra tings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Table 50. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 51. LQFP80 - 80-pin, 14 x 14 mm low-profile quad flat package mechanical
 data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Table 52. LQFP64 - 64-pin, 14 x 14 mm low-profile quad flat package mechanical
 data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Table 53. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package mechanical
 data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Table 54. LQFP48 - 48-pin, 7x 7 mm low-profile quad flat package mechanical . . . . . . . . . . . . . . . . 99
Table 55. LQFP44 - 44-pin, 10 x 10 mm low-profile quad flat package mechanical
 data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Table 56. LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package mechanical
 data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Table 57. T he rm a l  chara c te ris tics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Table 58. Document revision history  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

DocID14733 Rev 13 7/117
STM8S207xx STM8S208xx List of figures
8
List of figures
Figure 1. STM8S20xxx block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 2. Flash memory organization  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 3. LQFP 80-pin pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 4. LQFP 64-pin pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 5. LQFP 48-pin pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 6. LQFP 44-pin pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 7. LQFP 32-pin pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 8. Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 9. Supply current measurement conditions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 10. Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 11. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 12. fCPUmax versus VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Figure 13. External capacitor CEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 14. Typ. IDD(RUN) vs VDD, HSI RC osc, fCPU = 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 15. Typ. IDD(WFI) vs VDD, HSI RC osc, fCPU = 16 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 16. HSE external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 17. HSE oscillator circuit diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 18. Typical HSI frequency variation vs VDD at 4 temperatures. . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 19. Typical LSI frequency variation vs VDD @ 25 °C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 20. Typical VIL and VIH vs VDD @ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 21. Typical pull-up resistance vs VDD @ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 22. Typical pull-up current vs VDD @ 4 temperatures  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 23. Typ. VOL @ VDD = 5 V (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 24. Typ. VOL @ VDD = 3.3 V (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 25. Typ. VOL @ VDD = 5 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 26. Typ. VOL @ VDD = 3.3 V (true open drain ports)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 27. Typ. VOL @ VDD = 5 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 28. Typ. VOL @ VDD = 3.3 V (high sink ports)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 29. Typ. VDD - VOH @ VDD = 5 V (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 30. Typ. VDD - VOH @ VDD = 3.3 V (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 31. Typ. VDD - VOH @ VDD = 5 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 32. Typ. VDD - VOH @ VDD = 3.3 V (high sink ports)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 33. Typical NRST VIL and VIH vs VDD @ 4 temperatures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 34. Typical NRST pull-up resistance vs VDD @ 4 temperatures. . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 35. Typical NRST pull-up current vs VDD @ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 36. Recommended reset pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 37. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 38. SPI timing diagram - slave mode and CPHA = 1(1)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 39. SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 40. Typical application with I2C bus and timing diagram  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 41. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 42. Typical application with ADC  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 43. LQFP80 - 80-pin, 14 x 14 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . . 92
Figure 44. LQFP80 reco mmended footprint  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 45. LQFP80 mar kin g example (package top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Figure 46. LQFP64 - 64-pin 14 mm x 14 mm low-profile quad flat package outline . . . . . . . . . . . . . . 95
Figure 47. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . . 96
Figure 48. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat recommended footprint  . . . . . . . . . . . 97

List of figures STM8S207xx STM8S208xx
8/117 DocID14733 Rev 13
Figure 49. LQFP64 mar kin g example (package top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Figure 50. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . 99
Figure 51. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat recommended footprint  . . . . . . . . . . . . 100
Figure 52. LQFP48 mar kin g example (package top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Figure 53. LQFP44 - 44-pin, 10 x 10 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . 102
Figure 54. LQFP44 - 44-pin, 10 x 10 mm low-profile quad flat recommended footprint  . . . . . . . . . . 104
Figure 55. LQFP44 mar kin g example (package top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Figure 56. LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . . . 105
Figure 57. LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat recommended footprint  . . . . . . . . . . . . 106
Figure 58. LQFP32 mar kin g example (package top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Figure 59. STM8S207xx/208xx performance line ordering information scheme(1) . . . . . . . . . . . . . . 112

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STM8S207xx STM8S208xx Introduction

116

1 Introduction

This datasheet contains the descr ipt ion of the STM8S20xxx features, pinout, electrical

characteristics, mechanical data and ordering information.

For complete information on the STM8S microcontroller memory, registers and

peripherals, please refer to the STM8S microcontroller family reference manual

(RM0016).

For information on programming, erasing and protection of the internal Flash memory

please refer to the STM8 S Flash programming manual (PM0051).

For information on the debug and SWIM (single wire interface module) refer to the

STM8 SWIM communication protocol and debug module user manual (UM0470).

For information on the STM8 cor e, please refer to the STM8 CPU programming ma nual

(PM0044).

Description STM8S207xx STM8S208xx

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2 Description

The STM8S20xxx performance line 8-bit microcontrollers offe r from 32 to 128 Kbytes Flash

program memory. They are referred to as high-density devices in the STM8S

microcontroller family reference manual.

All STM8S20xxx devices provide the following benefits: reduced system cost, performance

robustness, short development cycles, and product longevity.

The system cost is reduced thanks to an integrated true data EEPROM for up to 300 k

write/erase cycles and a high system integration level with internal clock oscillators,

watchdog, and brown-out reset.

Device performance is ensure d by 20 MIPS at 24 MHz CPU clock frequ ency and e nhanced

characteristics which include robust I/O, independent watchdogs (with a sepa rate clock

source), and a clock security system.

Short development cycles are guaranteed due to application scalability across a common

family product architecture with compatible pinout, memory map and modular peripherals.

Full documentation is offered with a wide choice of development tools.

Product longevity is ensured in the STM8S family thanks to their advanced core which is

made in a state-of-the art te ch no log y fo r applic atio n s w ith 2. 95 V to 5.5 V oper atin g supp ly.

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STM8S207xx STM8S208xx Description

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Table 2. STM8S20xxx performance line features

Device

Pin count

Max. number of GPIOs

(I/O)

Ext. interrupt pins

Timer CAPCOM channels

Timer complementary outputs

A/D converter channels

High sink I/Os

High density Flash program memory

(bytes)

Data EEPROM

(bytes

RAM (bytes)

beCAN interface

STM8S207MB

STM8S207M8

STM8S207RB

STM8S207R8

STM8S207R6

STM8S207CB

STM8S207C8

STM8S207C6

STM8S207SB

STM8S207S8

STM8S207S6

STM8S207K8

STM8S207K6

128 K

64 K

128 K

64 K

32 K

128 K

64 K

32 K

128 K

64 K

32 K

64 K

32 K

2048

1536

1024

2048

1536

1024

1536

1024

6 K

STM8S208MB

STM8S208RB

STM8S208R8

STM8S208R6

STM8S208CB

STM8S208C8

STM8S208C6

STM8S208SB

STM8S208S8

STM8S208S6

128 K

64 K

32 K

128 K

64 K

32 K

128 K

64 K

32 K

2048

1536

6 K

Yes

Block diagram STM8S207xx STM8S208xx

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3 Block diagram

Figure 1. STM8S20xxx block dia gram

1. Legend:

ADC: Analog-to-digital converter

beCAN: Controller area network

BOR: Brownout reset

I²C: Inter-integrated circuit multimaster interface

Independent WDG: Independent watchdog

POR/PDR: Power on reset / power down reset

SPI: Serial peripheral interface

SWIM: Single wire interface module

UART: Universal asynchronous receiver transmitter

Window WDG: Window watchdog

XTAL 1-24 MHz

RC int. 16 MHz

RC int. 128 kHz

STM8 core

Debug/SWIM

I2C

SPI

UART1

UART3

AW U timer

Reset block

Reset

Clock controller

Detector

Clock to peripherals and core

10 Mbit/s

LIN master

16 channels

Address and data bus

Window WDG

Up to 128 Kbytes

Up to 2 Kbytes

Up to 6 Kbytes

Boot ROM

ADC2

beCAN

Reset

400 Kbit/s

1 Mbit/s

Master/slave

Single wire

autosynchro

debug interf.

SPI emul.

high density program

Flash

data EE PROM

RAM

16-bit general purpose

16-bit advanced contr ol

timer (TIM1)

timers (TIM2, TIM3)

8-bit basic timer

(TIM4)

Beeper

1/2/4 kHz

beep

Independent WDG

4 CAPCOM

channels

Up to

5 CAPCOM

channels

Up to

+ 3 complementary

outputs

POR/PDR

BOR

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4 Product overview

The following section intends to give an overview of the basic features of the STM8S20xxx

functional modules and peripherals.

For more detailed information please refer to the corresponding family refere nce manual

(RM0016).

4.1 Central processing unit STM8

The 8-bit STM8 core is designed for code ef ficiency and performance.

It contains 6 internal registers which are directly addressable in each execution context, 20

addressing modes including indexed indirect and relative addressing an d 80 instructions.

Architecture and registers

Harvard arch ite ctu re

3-stage pipeline

32-bit wide program memory bus - single cycle fetching for most instructions

X and Y 16-bit index registers - enablin g indexed addressing modes with or without

offset and read-modify-write type data manipulations

8-bit accumulator

24-bit progra m counter - 16-Mbyte linear memo ry space

16-bit stack pointer - access to a 64 K-level stack

8-bit condition code register - 7 condition flags for the result of the last instruction

Addressing

20 addressing modes

Indexed indirect addressing mode for look-up tables located anywhere in the address

space

Stack pointer relative addressing mode for local variables and parameter passing

Instruction set

80 instructions with 2-byte average instruction size

Standard data movement and logic/arithmetic functions

8-bit by 8-bit multiplication

16-bit by 8-bit and 16-bit by 16-bit division

Bit manipulation

Data transfer between stack and accumulator (push/pop) with direct stack access

Data transfer using the X and Y registers or direct mem ory-to-memory transfers

Product overview STM8S207xx STM8S208xx

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4.2 Single wire interface module (SWIM) and debug module (DM)

The single wire interface module and debug module permits non-intrusive, real-time in-

circuit debugging and fast memory programming.

SWIM

Single wire interface module for direct access to the debug module and memory

programming. The interface can be activated in all device operation modes. The maximum

data transmission speed is 145 bytes/ms.

Debug module

The non-intrusive debu gging module features a performance close to a full-featured

emulator. Beside memory and peripherals, also CPU operation can be monitored in real-

time by means of shadow registers.

R/W to RAM and peripheral registers in real-time

R/W access to all resources by stalling the CPU

Breakpoints on all pr ogram-memory instructions (software breakpoints)

Two advanced breakpoints, 23 predefined configurations

4.3 Interrupt controller

Nested interrupts with three software priority levels

32 interrupt vectors with hardware priority

Up to 37 external interrupts on six vectors including TLI

Trap and reset interrupts

4.4 Flash program and data EEPROM memory

Up to 128 Kbytes of high density Flash program single voltage Flash memory

Up to 2K bytes true data EEPROM

Read while write: Writing in data memory possible while executing code in program

memory.

User option byte area

Write protection (WP)

Write protection of Flash program memory and data EEPROM is provided to avoid

unintentional overwriting of memory that could result from a user sof tware malfunction.

There are two levels of write protection. The first level is known as MASS (memory access

security system). MASS is always enabled and protects the main Flash program memory,

data EEPROM and option bytes.

To perform in-application programming (IAP), this write protection can be removed by

writing a MASS key sequence in a control register. This allows the application to write to

data EEPROM, modify the contents of main program memory or the device option bytes.

A second level of write prot ect ion , ca n be enabled to further protect a specific area of

memory known as UBC (u se r boot co de ). Refe r to Figure 2.

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The size of the UBC is programmable th rough the UBC option byte (Table 13.), in

increments of 1 page ( 512 bytes) by programming the UBC option byte in ICP mode.

This divides the program memory into two areas:

Main program memory: Up to 128 Kbytes minus UBC

User-specific boot code (UBC): Configurable up to 128 Kbytes

The UBC area remains write-protected during in-application programming. This means that

the MASS keys do not unlock the UBC area. It protects the memor y u sed to store the boot

program, specific code libraries, reset and interrupt vectors, the reset routine and usually

the IAP and communication routines.

Figure 2. Flash memory organization

Read-out protection (ROP)

The read-out protection blocks reading and writing the Flash program memory and data

EEPROM memory in ICP mode (and debug mode). Once the read-out protection is

activated, any attempt to toggle its status triggers a global erase of the program and data

memory. Even if no protection can be considered as tot ally unbreakable, the feature

provides a very high level of protection for a general purpose microcontroller.

Programmable area fro m 1 Kb yte

Data

UBC area

Program memory area

Data memory area (2 Kbytes)

(2 first pages) up to 128 Kbytes

EEPROM

Remains write protected during IAP

memory

128 Kbytes

Flash

Up to

Write access possible for IAP

program

memory

(1 page steps)

Option bytes

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4.5 Clock controller

The clock controller distributes the system clock (fMASTER) coming from different oscillators

to the core and the peripherals. It also manages clock gating for low power modes and

ensures clock robustness.

Features

Clock prescaler: To get the best compromise between speed and current

consumption the clock frequency to the CPU an d peripherals can be adjusted by a

programmable prescaler.

Safe clock switching: Clock sources can be changed safely on the fly in run mode

through a configuration register. The clock signal is not switched until the new clock

source is ready. The design guarantees glitch-free switching.

Clock management: To reduce power consumption, the clock controller can stop the

clock to the core, individual peripherals or memory.

Master clock sources: Four different clock sources can be used to drive the master

clock:

– 1-24 MHz high-speed external crystal (HSE)

– Up to 24 MHz high-speed user-external clock (HSE user-ext)

– 16 MHz high-speed internal RC oscillator (HSI)

– 128 kHz low-speed internal RC (LSI)

S tartup clock: After reset, the microcontroller restarts by default with an internal 2

MHz clock (HSI/8). The prescaler ratio and clock source can be cha ng e d by th e

application program as soon as the code execution starts .

Clock security system (CSS): This feature can be enab led by software. If an HSE

clock failure occurs, the internal RC (16 MHz/8) is automatically selected by the CSS

and an interrupt can op tionally be generated.

Configurable main clock output (CCO): This outputs an external clock for use by the

application.

Table 3. Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers

Bit Peripheral

clock Bit Peripheral

clock

PCKEN17 TIM1 PCKEN13 UART3 PCKEN27 beCAN PCKEN23 ADC

PCKEN16 TIM3 PCKEN12 UART1 PCKEN26 Reserved PCKEN22 AWU

PCKEN15 TIM2 PCKEN11 SPI PCKEN25 Reserved PCKEN21 Reserved

PCKEN14 TIM4 PCKEN10 I2C PCKEN24 Reserved PCKEN20 Reserved

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4.6 Power management

For efficient power management, the application can be put in one of four different low-

power modes. You can configu re each mode to obt ain the best compromi se between lowest

power consumption, fastest start-up time and available wakeup sources.

Wait mode: In this mode, the CPU is stopped, but peripherals are kept running. The

wakeup is performed by an internal or external inter rupt or reset.

Active halt mode with regulator on: In this mod e, the CPU and peripheral clocks are

stopped. An internal wakeup is generated at programmable inter vals by the auto wake

up unit (AWU). The main voltage r egulator is kept powered on, so cur rent consumption

is higher than in active halt mode with regulator off, but the wakeup time is faster.

Wakeup is triggered by the internal AWU interrupt, external interrupt or reset.

Active halt mode with regulator off: This mode is the same as active halt with

regulator on, ex cept that the main volt age regula tor is powered off, so the wake up time

is slower.

Halt mode: In this mode the microcontroller uses the least power. The CPU and

peripheral clocks are stopped, the main voltage regulator is powered off. Wakeup is

triggered by external event or reset.

4.7 Watchdog timers

The watchdog system is based on two independent timers providing maximum security to

the application s.

Activation of the watchdog timers is controlled by option bytes or by software. Once

activated, the watchdogs cannot be disabled by the user program without performing a

reset.

Window watchdog timer

The window watchdog is used to detect the occurrence of a software fault, usually

generated by external interferences or by unexpected logical conditions, which cause the

application program to abandon its normal sequence.

The window function can be used to trim the watchdog behavior to match the application

perfectly.

The application soft ware must refresh the counter before time-o ut and during a limited time

window.

A reset is generated in two situations:

1. Timeout: At 16 MHz CPU clock the time-out period can be adjusted between 75 µs up

to 64 ms.

2. Refresh out of window: The downcounter is refreshed before its value is lower than the

one stored in the window register.

Product overview STM8S207xx STM8S208xx

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Independent watchdog timer

The independent watchdog periph eral can be used to resolve processor malfunctions due to

hardware or software failures.

It is clocked by the 128 kHz LSI internal RC clock source, and th us stays active even in case

of a CPU clock failure

The IWDG time base spans from 60 µs to 1 s.

4.8 Auto wakeup counter

Used for auto wakeup from active halt mode

Clock source: Internal 128 kHz internal low frequency RC oscillator or external clock

LSI clock can be internally co nnected to TIM3 input capture channel 1 for calibration

4.9 Beeper

The beeper function outputs a signal on the BEEP pin for sound generation. The signal is in

the range of 1, 2 or 4 kHz.

4.10 TIM1 - 16-bit advanced control timer

This is a high-end timer designed for a wide range of control applications. With its

complementary outputs, dead-time control and center-aligned PWM capability, the field of

applications is extended to motor control, lighting and half-bridge driver

16-bit up, down and up/down autoreload counter with 16-bit prescaler

Four independent captur e/compare channels (CAPCOM) configurable as input

capture, output compa re, PWM gen eration ( ed ge and cente r a ligne d mode ) a nd single

pulse mode output

Synchronization module to control the timer with external signals

Break input to force the timer outputs into a defined state

Three complementary outputs with adjustable dead time

Encoder mode

Interrupt sources: 3 x input capture/output compare, 1 x overflow/update, 1 x break

4.11 TIM2, TIM3 - 16-bit general purpose timers

16-bit autore load (AR) up-counter

15-bit prescaler adjustable to fixed power of 2 ratios 1…32768

Timers with 3 or 2 individually configurable capture/compare channels

PWM mode

Interrupt sources: 2 or 3 x input capture/output compare, 1 x overflow/update

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4.12 TIM4 - 8-bit basic timer

8-bit autoreload, adjustable prescaler ratio to any power of 2 from 1 to 128

Clock source: CPU clock

Interrupt source: 1 x overflow/update

4.13 Analog-to-digital converter (ADC2)

STM8S20xxx performance line products contain a 10-bit successive approximation A/D

converter (ADC2) with up to 16 multiplexed input channels and the following main features:

Input voltage range: 0 to VDDA

Dedicated voltage reference (VREF) pins available on 80 and 64-pin devices

Conversion time: 14 clock cycles

Single and continuous modes

External trigger input

Trigger from TIM1 TRGO

End of conversion (EOC) interrupt

4.14 Communication interfaces

The following communication interfaces are implemented:

UART1: Full feature UART, SPI emulation, LIN2.1 master capability, Smartcard mode,

IrDA mode, single wire mode.

UART3: Full feature UART, LIN2.1 master/slave capability

SPI: Full and half-duplex, 10 Mbit/s

I²C: Up to 400 Kbit/s

beCAN (rev. 2.0A,B) - 3 Tx mailboxes - up to 1 Mbit/s

Table 4. TIM timer features

Timer Counter

size

(bits) Prescaler Counting

mode CAPCOM

channels Complem.

outputs Ext.

trigger

Timer

synchr-

onization/

chaining

TIM1 16 Any integer from 1 to 65536 Up/down 4 3 Yes

TIM2 16 Any power of 2 from 1 to 32768 Up 3 0 No

TIM3 16 Any power of 2 from 1 to 32768 Up 2 0 No

TIM4 8 Any power of 2 from 1 to 128 Up 0 0 No

Product overview STM8S207xx STM8S208xx

20/117 DocID14733 Rev 13

4.14.1 UART1

Main features

One Mbit/s full duplex SCI

SPI emulation

High precision baud rate generator

Smartcard em u lat ion

IrDA SIR encoder deco d er

LIN master mode

Single wire half duplex mode

Asynchronous communication (UART mode)

Full duplex communication - NRZ standard format (mark/space )

Programmable transmit and receive baud rates up to 1 Mbit/s (fCPU/1 6) an d ca p able of

following any standard baud rate regardless of the input frequency

Separate enable bits for tr ansmitter and receiver

Two receiver wakeup modes:

– Address bit (MSB)

– Idle line (interrupt)

Transmission error detection with interrupt generation

Parity control

Synchronous communication

Full duplex synchronous transfers

SPI master operation

8-bit data communication

Maximum speed: 1 Mbit/s at 16 MHz (fCPU/16)

LIN master mode

Emission: Generates 13-bit sync break frame

Reception: Detects 11-bit break frame

4.14.2 UART3

Main features

1 Mbit/s full duplex SCI

LIN master capable

High precision baud rate generator

DocID14733 Rev 13 21/117

STM8S207xx STM8S208xx Product overview

116

Asynchronous communication (UART mode)

Full duplex communication - NRZ standard format (mark/space )

Programmable transmit and receive baud rates up to 1 Mbit/s (fCPU/1 6) an d ca p able of

following any standard baud rate regardless of the input frequency

Separate enable bits for tr ansmitter and receiver

Two receiver wakeup modes:

– Address bit (MSB)

– Idle line (interrupt)

Transmission error detection with interrupt generation

Parity control

LIN master capability

Emission: Generates 13-bit sync break frame

Reception: Detects 11-bit break frame

LIN slave mode

Autonomous header handling - one single interrupt per valid message header

Automatic baud rate synchronization - maximum tolerated initial clock deviation ±15%

Sync delimiter checking

11-bit LIN sync break detection - break detection always active

Parity check on the LIN identifier field

LIN error management

Hot plugging support

4.14.3 SPI

Maximum speed: 1 0 Mbit/s (fMASTER/2) both for master and slave

Full duplex synchronous transfers

Simplex synchronous transfers on two lines with a possible bidirectional data line

Master or slave operation - selectable by hardware or software

CRC calculation

1 byte Tx and Rx buffer

Slave/master selection input pin

Product overview STM8S207xx STM8S208xx

22/117 DocID14733 Rev 13

4.14.4 I2C

I2C master features:

– Clock generation

– Start and stop generation

I2C slave features:

– Programmable I2C address detection

– Stop bit detection

Generation and detection of 7-bit/10-bit addressing and general call

Supports different communication speeds:

– Standard speed (up to 100 kHz)

– Fast speed (up to 400 kHz)

4.14.5 beCAN

The beCAN controller (basic en hanced CAN), inter faces the CAN netwo rk and support s the

CAN protocol version 2.0A and B. It has been designed to manage a high number of

incoming messages efficiently with a minimum CPU load.

For safety-critical applications the beCAN controller provides all hardware functions to

support the CAN time triggered communication option (TTCAN).

The maximum transmission speed is 1 Mbit.

Transmission

Three transmit mailboxes

Configurable transmit priority by identifier or order request

Time stamp on SOF transmission

Reception

8-, 11- and 29-bit ID

One receive FIFO (3 messages deep)

Software-efficient mailbox mapping at a unique address space

FMI (filter match index) stored with message

Configurab le FIF O ove r ru n

Time stamp on SOF reception

Six filter banks, 2 x 32 bytes (scalable to 4 x 16-bit) each, enabling various masking

configurations, such as 12 filters for 29-bit ID or 48 filters for 11-bit ID

Filtering modes:

– Mask mode permitting ID range filtering

– ID list mode

Time triggered communication option

– Disable automatic retransmission mode

– 16-bit free running timer

– Configurable timer resolution

– Time stamp sent in last two data by tes

DocID14733 Rev 13 23/117

STM8S207xx STM8S208xx Pinouts and pin description

116

5 Pinouts and pin description

5.1 Package pinouts

Figure 3. LQ FP 80 -p i n pi n ou t

1. (HS) high sink capability.

2. (T) True open drain (P-buffer and prote ct i on diode to VDD not implemented).

3. [ ] alternate fun ction remap ping opt ion (If t he sa me altern ate f uncti on is shown twice, it in dicates an e xclusive choice no t a

duplication of the function).

4. CAN_RX and CAN_TX is available on STM8S208xx devices only.

PD4 (HS)/TIM2_CH1 [BEEP]

PI4

PI3

PI2

PI1

PC4 (HS)/TIM1_CH4

PC3 (HS)/TIM1_CH3

PC2 (HS)/TIM1_CH2

PC1 (HS)/TIM1_CH1

PG6

PG5

PI5

PI0

PG4

PG3

PG2

PC7 (HS)/SPI_MISO

VSSIO_2

VDDIO_1

[TIM3_CH1] TIM2_CH3/PA3

UART1_RX/ (HS) PA4

UART1_TX/ (HS) PA5

AIN12/PF4

VSSIO_1

VSS

VCAP

VDD

UART1_CK/ (HS) PA6

(HS) PH0

(HS) PH1

PH2

PH3

AIN15/PF7

AIN14/PF6

AIN13/PF5

NRST

OSCIN/PA1

OSCOUT/PA2

[I2C_SDA] AIN5/PB5

[I2C_SCL] AIN4/PB4

[TIM1_CH2N] AIN1/PB1

[TIM1_CH1N] AIN0/PB0

AIN8/PE7

VREF-

AIN10/PF0

AIN7/PB7

AIN6/PB6

TIM1_ETR/PH4

TIM1_CH3N/PH5

TIM1_CH2N/PH6

AIN9/PE6

AIN11/PF3

VREF+

VDDA

VSSA

PD0 (HS)/TIM3_CH2 [TIM1_BKIN] [CLK_CCO]

PE2 (T]/I 2C_SDA

PE3/TIM1_BKIN

PE4

PG7

PD7/TLI

PD6/UART3_RX

PD5/UART3_TX

PI7

PI6

PD2 (HS)/TIM3_CH1 [TIM2_CH3]

PD1 (HS)/SWIM

PC5 (HS)/SPI_SCK

PC6 (HS)/SPI_MOSI

PG0/CAN_TX

PG1/CAN_RX

PE0 (HS)/CLK_CCO

PD3 (HS)/TIM2_CH2 [ADC_ETR]

[TIM1_ETR] AIN3/PB3

[TIM1_CH3N] AIN2/PB2

PC0/ADC_ETR

PE5/SPI_NSS

TIM1_CH1N/PH7

VDDIO_2

PE1(T)/I2C_SCL

Pinouts and pin description STM8S207xx STM8S208xx

24/117 DocID14733 Rev 13

Figure 4. LQ FP 64 -p i n pi n ou t

1. (HS) high sink capability.

2. (T) True open drain (P-buffer and prote ct i on diode to VDD not implemented).

3. [ ] alternate fun ction remap ping opt ion (If t he sa me altern ate f uncti on is shown twice, it in dicates an e xclusive choice no t a

duplication of the function).

4. CAN_RX and CAN_TX is available on STM8S208xx devices only.

VREF-

AIN10/PF0

AIN7/PB7

AIN6/PB6

[I2C_SDA] AIN5/PB5

[I2C_SCL] AIN4/PB4

[TIM1_ETR] AIN3/PB3

[TIM1_CH3N] AIN2/PB2

[TIM1_CH2N] AIN1/PB1

[TIM1_CH1N] AIN0/PB0

AIN8/PE7

AIN9/PE6

AIN11/PF3

VREF+

VDDA

VSSA

64636261605958575655545352515049

1718192021222324 2930313225262728

VSS

VCAP

VDD

VDDIO_1

[TIM3_CH1] TIM2_CH3/PA3

UART1_RX/ (HS) PA4

UART1_TX/ (HS) PA5

UART1_CK/ (HS) PA6

AIN15/PF7

AIN14/PF6

AIN13/PF5

AIN12/PF4

NRST

OSCIN/PA1

OSCOUT/PA2

VSSIO_1 PG1/CAN_RX

PG0/CAN_TX

PC7 (HS)/SPI_MISO

PC6 (HS)/SPI_MOSI

VDDIO_2

VSSIO_2

PC5 (HS)/SPI_SCK

PC4 (HS)/TIM1_CH4

PC3 (HS)/TIM1_CH3

PC2 (HS)/TIM1_CH2

PC1 (HS)/TIM1_CH1

PE5/SPI_NSS

PI0

PG4

PG3

PG2

PD3 (HS)/TIM2_CH2[ADC_ETR]

PD2 (HS)/T IM 3 _ CH1[ T IM 2_ CH3 ]

PD1 (HS)/SWIM

PD0 (HS)/T IM 3 _ CH2 [TI M 1_B K IN] [CLK _ CCO]

PE0 (HS)/CLK_CCO

PE1 (T)/I2C_SCL

PE2 (T)/I2C_SDA

PE3/TIM1_BKIN

PE4

PG7

PG6

PG5

PD7/TLI

PD6/UART3_RX

PD5/UART3_TX

PD4 (HS)/TIM2_CH1 [BE EP ]

DocID14733 Rev 13 25/117

STM8S207xx STM8S208xx Pinouts and pin description

116

Figure 5. LQ FP 48 -p i n pi n ou t

1. (HS) high sink capability.

2. (T) True open drain (P-buffer and prote ct i on diode to VDD not implemented).

3. [ ] alternate fun ction remap ping opt ion (If t he sa me altern ate f uncti on is shown twice, it in dicates an e xclusive choice no t a

duplication of the function).

4. CAN_RX and CAN_TX is available on STM8S208xx devices only.

4443424140393837

13141516171819202122

48474645

UART1_CK/(HS) PA6

AIN8/PE7

PC1 (HS)/TIM1_CH1

PE5/SPI_NSS

PG1/CAN_RX

AIN9/PE6

PD3 (HS)/TIM2_CH2 [ADC_ETR]

PD2 (HS)/TIM3_CH1 [TIM2_CH3]

PE0 (HS)/CLK_CCO

PE1 (T)/I2C_SCL

PE2 (T)/I2C_SDA

PE3/TIM1_BKIN

PD7/TLI

PD6/UART3_RX

PD5/UART3_TX

PD4 (HS)/TIM2_CH1 [BEEP]

PD1 (HS)/SWIM

PD0 (HS)/TIM3_CH2 [TIM1_BKIN] [CLK_CCO]

VSSIO_2

PC5 (HS)/SPI_SCK

PC4 (HS)/TIM1_CH4

PC3 (HS)/TIM1_CH3

PC2 (HS)/TIM1_CH2

PG0/CAN_TX

PC7 (HS)/SPI_MISO

PC6 (HS)/SPI_MOSI

VDDIO_2

AIN7/PB7

AIN6/PB6

[I2C_SDA] AIN5/PB5

[I2C_SCL] AIN4/PB4

[TIM1_ETR/AIN3/PB3

[TIM1_CH3N] AIN2/PB2

[TIM1_CH2N] AIN1/PB1

[TIM1_CH1N] AIN0/PB0

VDDA

VSSA

VSS

VCAP

VDD

VDDIO_1

[TIM3_CH1] TIM2_CH3/PA3

UART1_RX/(HS) PA4

UART1_TX/(HS) PA5

NRST

OSCIN/PA1

OSCOUT/PA2

VSSIO_1

Pinouts and pin description STM8S207xx STM8S208xx

26/117 DocID14733 Rev 13

Figure 6. LQ FP 44 -p i n pi n ou t

1. (HS) high sink capability.

2. (T) True open drain (P-buffer and prote ct i on diode to VDD not implemented).

3. [ ] alternate fun ction remap ping opt ion (If t he sa me altern ate f uncti on is shown twice, it in dicates an e xclusive choice no t a

duplication of the function).

4. CAN_RX and CAN_TX is available on STM8S208xx devices only.

AIN6/PB6

[I2C_SDA] AIN5/PB5

[I2C_SCL] AIN4/PB4

[TIM1_ETR] AIN3/PB3

[TIM1_CH3N] AIN2/PB2

[TIM1_CH2N] AIN1/PB1

(TIM1_CH1N] AIN0/PB0

AIN9/PE6

VDDA

VSSA

AIN7/PB7

4443424140393837363534

1213141516171819202122

VSS

VCAP

VDD

VDDIO_1

UART1_RX

UART1_TX/

UART1_CK

NRST

OSCIN/PA1

OSCOUT/PA2

VSSIO_1 VDDIO_2

VSSIO_2

PC5 (HS)/SPI_SCK

PC3 (HS)/TIM1_CH3

PC2 (HS)/TIM1_CH2

PC1 (HS)/TIM1_CH1

PE5/SPI_NSS

PG1/CAN_RX

PG0/CAN_TX

PC7 (HS)/SPI_MISO

PC6 (HS)/SPI_MOSI

PD3 (HS)/TIM2_CH2 [ADC_ETR]

PD2 (HS)/TIM3_CH1 [TIM2_CH3]

PD1 (HS)/SWIM

PE1 (T)/I2C_SCL

PE2 (T)/I2C_SDA

PD7/TLI [TIM1_CH4]

PD6/UART3_RX

PD5/UART3_TX

PD4 (HS)/TIM2_CH1[BEEP]

PE0 (HS)/CLK_CCO

PD0 (HS)/TIM3_CH2 [TIM1_BKIN] [CLK_CCO]

DocID14733 Rev 13 27/117

STM8S207xx STM8S208xx Pinouts and pin description

116

Figure 7. LQ FP 32 -p i n pinout

1. (HS) high sink capability.

2. [ ] alternate fun ction remap ping opt ion (If t he sa me altern ate f uncti on is shown twice, it in dicates an e xclusive choice no t a

duplication of the function).

[I2C_SCL] AI N4 /P B4

[TIM1_ETR] AI N3 /P B3

[TIM1_CH3N] AIN2/PB2

[TIM1_CH2N] AIN1/PB1

[TIM1_CH1N] AIN0/PB0

VDDA

VSSA

[I2C_SDA] AI N5 /P B5

3231302928272625

9 10111213141516

VCAP

VDD

VDDIO

AIN12/PF4

NRST

OSCIN/PA1

OSCOUT/PA2

VSS PC3 (HS)/TIM1_CH3

PC2 (HS)/TIM1_CH2

PC1 (HS)/TIM1_CH1

PE5/SPI_NSS

PC7 (HS)/SPI_MISO

PC6 (HS)/SPI_MOSI

PC5 (HS)/SPI_SCK

PC4 (HS)/TIM1_CH4

PD3 (HS)/TIM2_CH2 [ADC_ETR]

PD2 (HS)/TIM3_CH1[TIM2_CH3]

PD1 (HS)/SWIM

PD0 (HS)/TIM3_CH2 [TIM1_BKIN] [CLK _CCO]

PD7/TLI

PD6/UART3_RX

PD5/UART3_TX

PD4 (HS)/TIM2_CH1 [BEEP]

Pinouts and pin description STM8S207xx STM8S208xx

28/117 DocID14733 Rev 13

Table 5. Legend/abbreviations for pinout table

Type I= Input, O = Output, S = Power supp ly

Level Input CM = CMOS

Output HS = High sink

Output speed O1 = Slow (up to 2 MHz) 

O2 = Fast (up to 10 MHz)

O3 = Fast/slow programmability with slow as default state after reset 

O4 = Fast/slow programmability with fast as default state after reset

Port and control

configuration Input float = floating, wpu = weak pull-up

Output T = True open drain, OD = Open drain, PP = Push pull

Reset state Bold X (pin state after internal reset release)

Unless otherwise specified, the pin state is the same during the reset phase and

after the internal reset release.

Table 6. Pin description

Pin number

Pin name

Type

Input Output

Main function

(after reset)

Default

alternate

function

Alternate

function

after remap

[option bit]

LQFP80

LQFP64

LQFP48

LQFP44

LQFP32

floating

wpu

Ext. interrupt

High sink

Speed

11111NRST I/O XReset

2 2 2 2 2 PA1/OSCIN I/O XXO1XXPort A1 Resonator/

crystal in

3 3 3 3 3 PA2/OSCOUT I/O XXX O1XXPort A2 Resonator/

crystal out

4444-V

SSIO_1 S I/O ground

55554V

SS S Digital ground

6 6 6 6 5 VCAP S 1.8 V regulator capacitor

77776V

DD S Digital power supply

88887V

DDIO_1 S I/O power supply

9 9 9 - - PA3/TIM2_CH3 I/O XXX O1XXPort A3 Timer 2 -

channel3 TIM3_CH1

[AFR1]

10 10 10 9 - PA4/UART1_RX

(1) I/O XXXHSO3XXPort A4 UART1

receive

11 11 11 10 - PA5/UART1_TX I/O XXXHSO3XXPort A5 UART1

transmit

DocID14733 Rev 13 29/117

STM8S207xx STM8S208xx Pinouts and pin description

116

12 12 12 11 - PA6/UART1_CK I/O XXXHSO3XXPort A6 UART1

synchronous

clock

13----PH0 I/OXXHSO3XXPort H0

14----PH1 I/OXXHSO3XXPort H1

15----PH2 I/OXXO1XXPort H2

16----PH3 I/OXXO1XXPort H3

17 13 - - - PF7/AIN15 I/O XXO1XXPort F7 Analog 

input 15

18 14 - - - PF6/AIN14 I/O XXO1XXPort F6 Analog 

input 14

19 15 - - - PF5/AIN13 I/O XXO1XXPort F5 Analog 

input 13

20 16 - - 8 PF4/AIN12 I/O XXO1XXPort F4 Analog 

input 12

21 17 - - - PF3/AIN11 I/O XXO1XXPort F3 Analog 

input 11

22 18 - - - VREF+ SADC positive reference

voltage

23 19 13 12 9 VDDA S Analog power supply

24 20 14 13 10 VSSA S Analog ground

25 21 - - - VREF- SADC negative reference

voltage

26 22 - - - PF0/AIN10 I/O XXO1XXPort F0 Analog 

input 10

27 23 15 14 - PB7/AIN7 I/O XXX O1XXPort B7 Analog 

input 7

28 24 16 15 - PB6/AIN6 I/O XXX O1XXPort B6 Analog 

input 6

29 25 17 16 11 PB5/AIN5 I/O XXX O1XXPort B5 Analog 

input 5 I2C_SDA

[AFR6]

30 26 18 17 12 PB4/AIN4 I/O XXX O1XXPort B4 Analog 

input 4 I2C_SCL

[AFR6]

Table 6. Pin description (continued)

Pin number

Pin name

Type

Input Output

Main function

(after reset)

Default

alternate

function

Alternate

function

after remap

[option bit]

LQFP80

LQFP64

LQFP48

LQFP44

LQFP32

floating

wpu

Ext. interrupt

High sink

Speed

Pinouts and pin description STM8S207xx STM8S208xx

30/117 DocID14733 Rev 13

31 27 19 18 13 PB3/AIN3 I/O XXX O1XXPort B3 Analog 

input 3 TIM1_ETR

[AFR5]

32 28 20 19 14 PB2/AIN2 I/O XXX O1XXPort B2 Analog 

input 2

TIM1_

CH3N

[AFR5]

33 29 21 20 15 PB1/AIN1 I/O XXX O1XXPort B1 Analog 

input 1

TIM1_

CH2N

[AFR5]

34 30 22 21 16 PB0/AIN0 I/O XXX O1XXPort B0 Analog 

input 0

TIM1_

CH1N

[AFR5]

35 - - - - PH4/TIM1_ETR I/O XXO1XXPort H4 Timer 1 -

trigger input

36 - - - - PH5/ TIM1_CH3N I/O XXO1XXPort H5 Timer 1 -

inverted

channel 3

37 - - - - PH6/ TIM1_CH2N I/O XXO1XXPort H6 Timer 1 -

inverted

channel 2

38 - - - - PH7/ TIM1_CH1N I/O XXO1XXPort H7 Timer 1 -

inverted

channel 2

39 31 23 - - PE7/AIN8 I/O XXX O1XXPort E7 Analog input 8

40 32 24 22 - PE6/AIN9 I/O XXX O1XXPort E6 Analog input 9

41 33 25 23 17 PE5/SPI_NSS I/O XXX O1XXPort E5 SPI

master/slave

select

42 - - - - PC0/ADC_ETR I/O XXX O1XXPort C0 ADC trigger

input

43 34 26 24 18 PC1/TIM1_CH1 I/O XXXHSO3XXPort C1 Timer 1 -

channel 1

44 35 27 25 19 PC2/TIM1_CH2 I/O XXXHSO3XXPort C2 Timer 1-

channel 2

45 36 28 26 20 PC3/TIM1_CH3 I/O XXXHSO3XXPort C3 Timer 1 -

channel 3

Table 6. Pin description (continued)

Pin number

Pin name

Type

Input Output

Main function

(after reset)

Default

alternate

function

Alternate

function

after remap

[option bit]

LQFP80

LQFP64

LQFP48

LQFP44

LQFP32

floating

wpu

Ext. interrupt

High sink

Speed

DocID14733 Rev 13 31/117

STM8S207xx STM8S208xx Pinouts and pin description

116

46 37 29 - 21 PC4/TIM1_CH4 I/O XXXHSO3XXPort C4 Ti mer 1 -

channel 4

47 38 30 27 22 PC5/SPI_SCK I/O XXXHSO3XXPort C5 SPI clock

48 39 31 28 - VSSIO_2 S I/O ground

49 40 32 29 - VDDIO_2 S I/O power supply

50 41 33 30 23 PC6/SPI_MOSI I/O XXXHSO3XXPort C6 SPI master

out/

slave in

51 42 34 31 24 PC7/SPI_MISO I/O XXXHSO3XXPort C7 SPI master in/

slave out

52 43 35 32 - PG0/CAN_TX(2) I/O XXO1XXPort G0 beCAN

transmit

53 44 36 33 - PG1/CAN_RX(2) I/O XXO1XXPort G1 beCAN

receive

54 45 - - - PG2 I/O XXO1XXPort G2

55 46 - - - PG3 I/O XXO1XXPort G3

56 47 - - - PG4 I/O XXO1XXPort G4

57 48 - - - PI0 I/O XXO1XXPort I0

58----PI1 I/OXXO1XXPort I1

59----PI2 I/OXXO1XXPort I2

60----PI3 I/OXXO1XXPort I3

61----PI4 I/OXXO1XXPort I4

62----PI5 I/OXXO1XXPort I5

63 49 - - - PG5 I/O XXO1XXPort G5

64 50 - - - PG6 I/O XXO1XXPort G6

65 51 - - - PG7 I/O XXO1XXPort G7

66 52 - - - PE4 I/O XXX O1XXPort E4

67 53 37 - - PE3/TIM1_BKIN I/O XXX O1XXPort E3 Timer 1 - 

break input

68 54 38 34 - PE2/I2C_SDA I/O XXO1T

(3) Port E2 I2C data

Table 6. Pin description (continued)

Pin number

Pin name

Type

Input Output

Main function

(after reset)

Default

alternate

function

Alternate

function

after remap

[option bit]

LQFP80

LQFP64

LQFP48

LQFP44

LQFP32

floating

wpu

Ext. interrupt

High sink

Speed

Pinouts and pin description STM8S207xx STM8S208xx

32/117 DocID14733 Rev 13

5.2 Alternate function remapping

As shown in the rightmost column of the pin description t ab le, so me alternate functions can

be remapped at different I/O ports by programming one of eight AFR (alternate function

69 55 39 35 - PE1/I2C_SCL I/O XXO1T

(3) Port E1 I2C clock

70 56 40 36 - PE0/CLK_CCO I/O XXXHSO3XXPort E0 Configurable

clock output

71----PI6 I/OXXO1XXPort I6

72----PI7 I/OXXO1XXPort I7

73 57 41 37 25 PD0/TIM3_CH2 I/O XXXHSO3XXPort D0 Timer 3 -

channel 2

TIM1_BKIN

[AFR3]/

CLK_CCO

[AFR2]

74 58 42 38 26 PD1/SWIM(4) I/O X XXHSO4XXPort D1 SWIM data

interface

75 59 43 39 27 PD2/TIM3_CH1 I/O XXXHSO3XXPort D2 Timer 3 -

channel 1 TIM2_CH3

[AFR1]

76 60 44 40 28 PD3/TIM2_CH2 I/O XXXHSO3XXPort D3 Timer 2 -

channel 2 ADC_ETR

[AFR0]

77 61 45 41 29 PD4/TIM2_CH1/B

EEP I/O XXXHSO3XXPort D4 Timer 2 -

channel 1 BEEP output

[AFR7]

78 62 46 42 30 PD5/ UART3_TX I/O XXX O1XXPort D5 UART3 data

transmit

79 63 47 43 31 PD6/

UART3_RX(1) I/O XXX O1XXPort D6 UART3 data

receive

80 64 48 44 32 PD7/TLI I/O XXX O1XXPort D7 Top level

interrupt TIM1_CH4

[AFR4](5)

1. The default state of UART1_RX and UART3_RX pins is controlled by the ROM bootloader . These pins are pulled up as part

of the bootloader activation process and returned to the floating state before a return from the bootloader.

2. The beCAN interface is available on STM8S208xx devices only

3. In the open-drain output column, ‘T’ defines a true open-drain I/O (P-buffer, weak pull-up, and protection diode to VDD are

not implemented).

4. The PD1 pin is in input pull-up during the reset phase and after the internal reset release.

5. Available in 44-pin package only. On other packages, the AFR4 bit is reserved and must be kept at 0.

Table 6. Pin description (continued)

Pin number

Pin name

Type

Input Output

Main function

(after reset)

Default

alternate

function

Alternate

function

after remap

[option bit]

LQFP80

LQFP64

LQFP48

LQFP44

LQFP32

floating

wpu

Ext. interrupt

High sink

Speed

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STM8S207xx STM8S208xx Pinouts and pin description

116

remap) option bits. Refer to Section 8: Option bytes on page 47. When the remapping

option is active, the default alternate function is no longer available.

To use an alternate function, the corr esponding peripheral must be enabled in the peripheral

registers.

Alternate function remapping does not effect GPIO capabilities of the I/O ports (see the

GPIO section of the family reference manual, RM0016 ).

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6 Memory and register map

6.1 Memory map

Figure 8. Memory map

GPIO and peripheral registers

0x00 0000

Reserved

Flash program memory

(64 to 128 Kbytes)

32 interrupt vectors

0x00 4000

0x00 47FF

RAM

0x00 17FF

(up to 6 Kbytes)

1024 bytes stack

Up to 2 Kbytes data EEPROM

0x00 4800

0x00 487F Option bytes

0x00 5000

0x00 57FF

0x00 5800

0x00 7FFF

0x00 8000

0x02 7FFF

(see Table 8 and Table 9)

0x00 1800

0x00 3FFF

0x00 4900

0x00 4FFF

2 Kbytes boot ROM

0x00 6000

0x00 67FF

0x00 6800

0x00 7EFF

0x00 8080

0x00 807F

CPU/SWIM/debug/ITC

(see Table 10)

registers

0x00 7F00

0x00 5FFF

Reserved

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STM8S207xx STM8S208xx Memory and register map

116

Table 7 lists the boundary addresses for each memory size. The top of the stack is at the

RAM end address in each case.

6.2 Register map

Table 7. Flash, Data EEPROM and RAM boundary addresses

Memory area Size (bytes) Start address End address

Flash progra m m emory

128 K 0x00 8000 0x02 7FFF

64 K 0x00 8000 0x01 7FFF

32 K 0x00 8000 0x00 FFFF

RAM

6 K 0x00 0000 0x00 17FF

4 K 0x00 0000 0x00 1000

2 K 0x00 0000 0x00 07FF

Data EEPROM

2048 0x00 4000 0x00 47FF

1536 0x00 4000 0x00 45FF

1024 0x00 4000 0x00 43FF

Table 8. I/O port hardware register map

Address Block Register label Register name Reset

status

0x00 5000

Port A

PA_ODR Port A data output latch register 0x00

0x00 5001 PA_IDR Port A input pin value register 0x00

0x00 5002 PA_DDR Port A data direction register 0x00

0x00 5003 PA_CR1 Port A control register 1 0x00

0x00 5004 PA_CR2 Port A control register 2 0x00

0x00 5005

Port B

PB_ODR Port B data output latch register 0x00

0x00 5006 PB_IDR Port B input pin value register 0x00

0x00 5007 PB_DDR Port B data direction register 0x00

0x00 5008 PB_CR1 Port B control register 1 0x00

0x00 5009 PB_CR2 Port B control register 2 0x00

0x00 500A

Port C

PC_ODR Port C data output latch register 0x00

0x00 500B PB_IDR Port C input pin value register 0x00

0x00 500C PC_DDR Port C data direction register 0x00

0x00 500D PC_CR1 Port C control register 1 0x00

0x00 500E PC_CR2 Port C control register 2 0x00

Memory and register map STM8S207xx STM8S208xx

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0x00 500F

Port D

PD_ODR Port D data output latch register 0x00

0x00 5010 PD_ IDR Port D input pin value register 0x00

0x00 5011 PD_DDR Port D data direction register 0x00

0x00 5012 PD_CR1 Port D control register 1 0x02

0x00 5013 PD_CR2 Port D control register 2 0x00

0x00 5014

Port E

PE_ODR Port E data output latch register 0x00

0x00 5015 PE_IDR Port E input pin value register 0x00

0x00 5016 PE_DDR Port E data direction register 0x00

0x00 5017 PE_CR1 Port E control register 1 0x00

0x00 5018 PE_CR2 Port E control register 2 0x00

0x00 5019

Port F

PF_ODR Port F data output latch register 0x00

0x00 501A PF_IDR Port F input pin value register 0x00

0x00 501B PF_DDR Port F data directi on register 0x00

0x00 501C PF_CR1 Port F control register 1 0x00

0x00 501D PF_CR2 Port F control register 2 0x00

0x00 501E

Port G

PG_ODR Port G data output latch register 0x00

0x00 501F PG_IDR Port G input pin value register 0x00

0x00 5020 PG_DDR Port G data direction register 0x00

0x00 5021 PG_CR1 Port G control register 1 0x00

0x00 5022 PG_CR2 Port G control register 2 0x00

0x00 5023

Port H

PH_ODR Port H data output latch register 0x00

0x00 5024 PH_ IDR Port H input pin value register 0x00

0x00 5025 PH_DDR Port H data direction register 0x00

0x00 5026 PH_CR1 Port H control register 1 0x00

0x00 5027 PH_CR2 Port H control register 2 0x00

0x00 5028

Port I

PI_ODR Port I data output latch register 0x00

0x00 5029 PI_IDR Port I input pin value register 0x00

0x00 502A PI_DDR Port I data direction register 0x00

0x00 502B PI_CR1 Port I control register 1 0x00

0x00 502C PI_CR2 Port I control register 2 0x00

Table 8. I/O port hardware register map (continued)

Address Block Register label Register name Reset

status

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116

Ta bl e 9. General hardware register map

Address Bloc k Register label Register name Reset

status

0x00 5050 to

0x00 5059 Reserved area (10 bytes)

0x00 505A

Flash

FLASH_CR1 Flash control register 1 0x00

0x00 505B FLASH_CR2 Flash control register 2 0x00

0x00 505C FLASH_NCR2 Flash complementary control register 2 0xFF

0x00 505D FLASH _FPR Flash protection register 0x00

0x00 505E FLASH _NFPR Flash complementary protection register 0xFF

0x00 505F FLASH _IAPSR Flash in-application programming status

0x00 5060 to

0x00 5061 Reserved area (2 bytes)

0x00 5062 Flash FLASH _PUKR Flash Program memory unprotection

0x00 5063 Reserved area (1 byt e)

0x00 5064 Flash FLASH _DUKR Data EEPROM unprotection register 0x00

0x00 5065 to

0x00 509F Reserved area (59 bytes)

0x00 50A0 ITC EXTI_CR1 External interrupt control register 1 0x00

0x00 50A1 EXTI_CR2 External interrupt control register 2 0x00

0x00 50A2 to

0x00 50B2 Reserved area (17 bytes)

0x00 50B3 RST RST_SR Reset st atus register 0xXX(1)

0x00 50B4 to

0x00 50BF Reserved area (12 bytes)

0x00 50C0 CLK CLK_ICKR Internal clock control register 0x01

0x00 50C1 CLK_ECKR External clock control register 0x00

0x00 50C2 Reserved area (1 byte)

0x00 50C3

CLK

CLK_CMSR Clock master status register 0xE1

0x00 50C4 CLK_SWR Clock master switch register 0xE1

0x00 50C5 CLK_SWCR Clock switch control register 0xXX

0x00 50C6 CLK_CKDIVR Clock divider register 0x18

0x00 50C7 CLK_PCKENR1 P eripheral clock gating register 1 0xFF

0x00 50C8 CLK_CSSR Clock security system register 0x00

0x00 50C9 CLK_CCOR Configurable clock control register 0x00

0x00 50CA CLK_PCKENR2 Peripheral clock gating register 2 0xFF

0x00 50CB CLK_CANCCR CAN clock control register 0x00

Memory and register map STM8S207xx STM8S208xx

38/117 DocID14733 Rev 13

0x00 50CC CLK CLK_HSITRIMR HSI clock calibration trimming register 0x00

0x00 50CD CLK_SWIMCCR SW IM clock control register 0bXXXX

XXX0

0x00 50CE to

0x00 50D0 Reserved area (3 bytes)

0x00 50D1 WWDG WWDG_CR WWDG control register 0x7F

0x00 50D2 WWDG_WR WWDR window register 0x7 F

0x00 50D3 to

0x00 50DF Reserved area (13 bytes)

0x00 50E0

IWDG

IWDG_KR IWDG key register 0xXX(2)

0x00 50E1 IWDG_PR IWDG prescaler register 0x00

0x00 50E2 IWDG_RLR IWDG reload register 0xFF

0x00 50E3 to

0x00 50EF Reserved area (13 bytes)

0x00 50F0

AWU

AWU_CSR1 AWU control/status register 1 0x00

0x00 50F1 A WU_APR A WU asynchronous prescaler buffer register 0x3F

0x00 50F2 A W U_TBR AWU timebase selection register 0x00

0x00 50F3 BEEP BEEP_CSR BEEP control/status register 0x1F

0x00 50F4 to

0x00 50FF Reserved area (12 bytes)

0x00 5200

SPI

SPI_CR1 SPI control register 1 0x00

0x00 5201 SPI_CR2 SPI control register 2 0x00

0x00 5202 SPI_ICR SPI interrupt control register 0x00

0x00 5203 SPI_SR SPI status register 0x02

0x00 5204 SPI_DR SPI data register 0x00

0x00 5205 SPI_CRCPR SPI CRC polynomial register 0x07

0x00 5206 SPI_RXCRCR SPI Rx CRC register 0xFF

0x00 5207 SPI_TXCRCR SPI Tx CRC register 0xFF

0x00 5208 to

0x00 520F Reserved area (8 bytes)

0x00 5210

I2C

I2C_CR1 I2C control register 1 0x00

0x00 5211 I2C_CR2 I2C control register 2 0x00

0x00 5212 I2C_FREQR I2C frequency register 0x00

0x00 5213 I2C_OARL I2C own address register low 0x00

0x00 5214 I2C_OARH I2C own address regist er hi g h 0x00

0x00 5215 Reserved

Table 9. General hardware register map (continued)

Address Bloc k Register label Register name Reset

status

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STM8S207xx STM8S208xx Memory and register map

116

0x00 5216

I2C

I2C_DR I2C data register 0x00

0x00 5217 I2C_SR1 I2C status register 1 0x00

0x00 5218 I2C_SR2 I2C status register 2 0x00

0x00 5219 I2C_SR3 I2C status register 3 0x00

0x00 521A I2C_ITR I2C interrupt control register 0x00

0x00 521B I2C_CCRL I2C clock control register low 0x00

0x00 521C I2C_CCRH I2C clock control register high 0x00

0x00 521D I2C_TRISER I2C TRISE register 0x02

0x00 521E to

0x00 522F Reserved area (18 bytes)

0x00 5230

UART1

UART1_SR UART1 status register 0xC0

0x00 5231 UART1_DR UART1 data register 0xXX

0x00 5232 UART1_BRR1 UART1 baud rate register 1 0x00

0x00 5233 UART1_BRR2 UART1 baud rate register 2 0x00

0x00 5234 UART1_ C R 1 UART1 cont ro l re gi ste r 1 0x00

0x00 5235 UART1_ C R 2 UART1 cont ro l re gi ste r 2 0x00

0x00 5236 UART1_ C R 3 UART1 cont ro l re gi ste r 3 0x00

0x00 5237 UART1_ C R 4 UART1 cont ro l re gi ste r 4 0x00

0x00 5238 UART1_ C R 5 UART1 cont ro l re gi ste r 5 0x00

0x00 5239 UART1_GTR UART1 guard time register 0x00

0x00 523A UART1_PSCR UART1 prescaler register 0x00

0x00 523B to

0x00 523F Reserved area (5 bytes)

0x00 5240

UART3

UART3_SR UART3 status register C0h

0x00 5241 UART3_DR UART3 data register 0xXX

0x00 5242 UART3_BRR1 UART3 baud rate register 1 0x00

0x00 5243 UART3_BRR2 UART3 baud rate register 2 0x00

0x00 5244 UART3_ C R 1 UART3 cont ro l re gi ste r 1 0x00

0x00 5245 UART3_ C R 2 UART3 cont ro l re gi ste r 2 0x00

0x00 5246 UART3_ C R 3 UART3 cont ro l re gi ste r 3 0x00

0x00 5247 UART3_ C R 4 UART3 cont ro l re gi ste r 4 0x00

0x00 5248 Reserved

0x00 5249 UART3_ C R 6 UART3 cont ro l re gi ste r 6 0x00

0x00 524A to

0x00 524F Reserved area (6 bytes)

Table 9. General hardware register map (continued)

Address Bloc k Register label Register name Reset

status

Memory and register map STM8S207xx STM8S208xx

40/117 DocID14733 Rev 13

0x00 5250

TIM1

TIM1_CR1 TIM1 control register 1 0x00

0x00 5251 TIM1_CR2 TIM1 control register 2 0x00

0x00 5252 TIM1_SMCR TIM1 slave mode control register 0x00

0x00 5253 TIM1_ETR TIM1 external trigger register 0x00

0x00 5254 TIM1_IER TIM1 Interrupt enable register 0x00

0x00 5255 TIM1_SR1 TIM1 status register 1 0x00

0x00 5256 TIM1_SR2 TIM1 status register 2 0x00

0x00 5257 TIM1_EGR TIM1 event generation register 0x00

0x00 5258 TIM1_CCMR1 TIM1 capture/compare mode register 1 0x00

0x00 5259 TIM1_CCMR2 TIM1 capture/compare mode register 2 0x00

0x00 525A TIM1_CCMR3 TIM1 capture/compare mode register 3 0x00

0x00 525B TIM1_CCMR4 TIM1 capture/compare mode register 4 0x00

0x00 525C TIM1_CCER1 TIM1 capture/compare enable register 1 0 x00

0x00 525D TIM1_CCER2 TIM1 capture/compare enable register 2 0 x00

0x00 525E TIM1_CNTRH TIM1 counter high 0x00

0x00 525F TIM1_CNTRL TIM1 counter low 0x00

0x00 5260 TIM1_PSCRH TIM1 prescaler register high 0x00

0x00 5261 TIM1_PSCRL TIM1 prescaler register low 0x00

0x00 5262 TIM1_ARRH TIM1 auto-reload register high 0xFF

0x00 5263 TIM1_ARRL TIM1 auto-reload register lo w 0xFF

0x00 5264 TIM1_RCR TIM1 repetition counter register 0x00

0x00 5265 TIM1_CCR1H TIM1 capture/compare register 1 high 0x00

0x00 5266 TIM1_CCR1L TIM1 capture/compare register 1 low 0x00

0x00 5267 TIM1_CCR2H TIM1 capture/compare register 2 high 0x00

0x00 5268 TIM1_CCR2L TIM1 capture/compare register 2 low 0x00

0x00 5269 TIM1_CCR3H TIM1 capture/compare register 3 high 0x00

0x00 526A TIM1_CCR3L TIM1 capture/compare register 3 low 0x00

0x00 526B TIM1_CCR4H TIM1 capture/compare register 4 high 0x00

0x00 526C TIM1_CCR4L TIM1 capture/co mpare register 4 low 0x00

0x00 526D TIM1_BKR TIM1 break register 0x00

0x00 526E TIM1_DTR TIM1 dead-time register 0x00

0x00 526F TIM1_OISR TIM1 output idle state register 0x 00

0x00 5270 to

0x00 52FF Reserved area (147 bytes)

Table 9. General hardware register map (continued)

Address Bloc k Register label Register name Reset

status

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STM8S207xx STM8S208xx Memory and register map

116

0x00 5300

TIM2

TIM2_CR1 TIM2 control register 1 0x00

0x00 5301 TIM2_IER TIM2 interrupt enable register 0x00

0x00 5302 TIM2_SR1 TIM2 status register 1 0x00

0x00 5303 TIM2_SR2 TIM2 status register 2 0x00

0x00 5304 TIM2_EGR TIM2 event generation register 0x00

0x00 5305 TIM2_CCMR1 TIM2 capture/compare mode register 1 0x00

0x00 5306 TIM2_CCMR2 TIM2 capture/compare mode register 2 0x00

0x00 5307 TIM2_CCMR3 TIM2 capture/compare mode register 3 0x00

0x00 5308 TIM2_CCER1 TIM2 capture/compare enable register 1 0x00

0x00 5309 TIM2_CCER2 TIM2 capture/compare enable register 2 0x00

0x00 530A TIM2_CNTRH TIM2 counter high 0x00

0x00 530B TIM2_CNTRL TIM2 counter low 0x00

00 530C0x TIM2_PSCR TIM2 prescaler register 0x00

0x00 530D TIM2_ARRH TIM2 auto-reload register high 0xFF

0x00 530E TIM2_ARRL TIM2 auto-reload registe r low 0xFF

0x00 530F TIM2_CCR1H TIM2 capture/compare register 1 high 0x00

0x00 5310 TIM2_CCR1L TIM2 capture/compare register 1 low 0x00

0x00 5311 TIM2_CCR2H TIM2 capture/compare reg. 2 high 0 x 00

0x00 5312 TIM2_CCR2L TIM2 capture/compare register 2 low 0x00

0x00 5313 TIM2_CCR3H TIM2 capture/compare register 3 high 0x00

0x00 5314 TIM2_CCR3L TIM2 capture/compare register 3 low 0x00

0x00 5315 to

0x00 531F Reserved area (11 bytes)

0x00 5320

TIM3

TIM3_CR1 TIM3 control register 1 0x00

0x00 5321 TIM3_IER TIM3 interrupt enable register 0x00

0x00 5322 TIM3_SR1 TIM3 status register 1 0x00

0x00 5323 TIM3_SR2 TIM3 status register 2 0x00

0x00 5324 TIM3_EGR TIM3 event generation register 0x00

0x00 5325 TIM3_CCMR1 TIM3 capture/compare mode register 1 0x00

0x00 5326 TIM3_CCMR2 TIM3 capture/compare mode register 2 0x00

0x00 5327 TIM3_CCER1 TIM3 capture/compare enable register 1 0x00

0x00 5328 TIM3_CNTRH TIM3 counter high 0x00

0x00 5329 TIM3_CNTRL TIM3 counter low 0x00

0x00 532A TIM3_PSCR TIM3 prescaler register 0x00

Table 9. General hardware register map (continued)

Address Bloc k Register label Register name Reset

status

Memory and register map STM8S207xx STM8S208xx

42/117 DocID14733 Rev 13

0x00 532B

TIM3

TIM3_ARRH TIM3 auto-reload register high 0xFF

0x00 532C TIM3_ARRL TIM3 auto-reload register low 0xFF

0x00 532D TIM3_CCR1H T IM3 capture /compare register 1 high 0x00

0x00 532E TIM3_CCR1L TIM3 capture/compare register 1 low 0x00

0x00 532F TIM3_CCR2H TIM3 capture/compare register 2 high 0x00

0x00 5330 TIM3_CCR2L TIM3 capture/compare register 2 low 0x00

0x00 5331 to

0x00 533F Reserved area (15 bytes)

0x00 5340

TIM4

TIM4_CR1 TIM4 control register 1 0x00

0x00 5341 TIM4_IER TIM4 interrupt enable register 0x00

0x00 5342 TIM4_SR TIM4 status regi st er 0x00

0x00 5343 TIM4_EGR TIM4 event generation register 0x00

0x00 5344 TIM4_CNTR TIM4 counter 0x00

0x00 5345 TIM4_PSCR TIM4 prescaler register 0x00

0x00 5346 TIM4_ARR TIM4 auto-reload register 0xFF

0x00 5347 to

0x00 53FF Reserved area (185 bytes)

0x00 5400

ADC2

ADC _CSR ADC control/status register 0x00

0x00 5401 ADC_CR1 ADC configuration register 1 0x00

0x00 5402 ADC_CR2 ADC configuration register 2 0x00

0x00 5403 ADC_CR3 ADC configuration register 3 0x00

0x00 5404 ADC_DRH ADC data register high 0xXX

0x00 5405 ADC_DRL ADC data register low 0xXX

0x00 5406 ADC_TDRH ADC Schmitt trigger disable register high 0x00

0x00 5407 ADC_TDRL ADC Schmitt trigger disable register low 0x00

0x00 5408 to

0x00 541F Reserved area (24 bytes)

0x00 5420

beCAN

CAN_MCR CAN master control register 0x02

0x00 5421 CAN_MSR CAN master status register 0x02

0x00 5422 CAN_TSR CAN transmit status register 0x00

0x00 5423 CAN_TPR CAN transmit priority register 0x0C

0x00 5424 CAN_RFR CAN receive FIFO register 0x00

0x00 5425 CAN_IER CAN interrupt enable register 0x00

0x00 5426 CAN_DGR CAN diagnosis register 0x0C

0x00 5427 CAN_FPSR CAN page selection register 0x00

Table 9. General hardware register map (continued)

Address Bloc k Register label Register name Reset

status

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116

0x00 5428

beCAN

CAN_P0 CAN paged register 0 0xXX(3)

0x00 5429 CAN_P1 CAN paged register 1 0xXX(3)

0x00 542A CAN_P2 CAN paged register 2 0xXX(3)

0x00 542B CAN_P3 CAN paged register 3 0xXX(3)

0x00 542C CAN_P4 CAN paged register 4 0xXX(3)

0x00 542D CAN_P5 CAN paged register 5 0xXX(3)

0x00 542E CAN_P6 CAN paged register 6 0xXX(3)

0x00 542F CAN_P7 CAN paged register 7 0xXX(3)

0x00 5430 CAN_P8 CAN paged register 8 0xXX(3)

0x00 5431 CAN_P9 CAN paged register 9 0xXX(3)

0x00 5432 CAN_PA CAN paged register A 0xXX(3)

0x00 5433 CAN_PB CAN paged register B 0xXX(3)

0x00 5434 CAN_PC CAN paged register C 0xXX(3)

0x00 5435 CAN_PD CAN paged register D 0xXX(3)

0x00 5436 CAN_PE CAN paged register E 0xXX(3)

0x00 5437 CAN_PF CAN paged register F 0xXX(3)

0x00 5438 to

0x00 57FF Reserved area (968 bytes)

1. Depends on the previous reset source.

2. Write only register.

3. If the bootloader is enabled, it is initialized to 0x00.

Table 9. General hardware register map (continued)

Address Bloc k Register label Register name Reset

status

Memory and register map STM8S207xx STM8S208xx

44/117 DocID14733 Rev 13

Table 10. CPU/SWIM/debug module/interrupt controller registers

Address Block Reg ister Label Register Name Reset

Status

0x00 7F00

CPU(1)

A Accumulator 0x00

0x00 7F01 PCE Program counter extended 0x00

0x00 7F02 PCH Program counter high 0x00

0x00 7F03 PCL Program counter low 0x00

0x00 7F04 XH X index register high 0x00

0x00 7F05 XL X index register low 0x00

0x00 7F06 YH Y index register high 0x00

0x00 7F07 YL Y index register low 0x00

0x00 7F08 SPH Stack pointer high 0x17(2)

0x00 7F09 SPL Stack pointer low 0xFF

0x00 7F0A CCR Condition code register 0x28

0x00 7F0B to

0x00 7F5F Reserve d area (85 bytes)

0x00 7F60 CPU CFG_GCR Global configuration register 0x00

0x00 7F70

ITC

ITC_SPR1 Interrupt software priority register 1 0xFF

0x00 7F71 ITC_SPR2 Interrupt software priority register 2 0xFF

0x00 7F72 ITC_SPR3 Interrupt software priority register 3 0xFF

0x00 7F73 ITC_SPR4 Interrupt software priority register 4 0xFF

0x00 7F74 ITC_SPR5 Interrupt software priority register 5 0xFF

0x00 7F75 ITC_SPR6 Interrupt software priority register 6 0xFF

0x00 7F76 ITC_SPR7 Interrupt software priority register 7 0xFF

0x00 7F77 ITC_SPR8 Interrupt software priority register 8 0xFF

0x00 7F78 to

0x00 7F79 Reserved area (2 byt es)

0x00 7F80 SWIM SWIM_CSR SWIM control status register 0x00

0x00 7F81 to

0x00 7F8F Reserve d area (15 bytes)

0x00 7F90

DM_BK1RE DM breakpoint 1 register extended byte 0xFF

0x00 7F91 DM_BK1RH DM breakpoint 1 register high byte 0xFF

0x00 7F92 DM_BK1RL DM breakpoin t 1 regi ster low byte 0xFF

0x00 7F93 DM_BK2RE DM breakpoint 2 register extended byte 0xFF

0x00 7F94 DM_BK2RH DM breakpoint 2 register high byte 0xFF

0x00 7F95 DM_BK2RL DM breakpoin t 2 regi ster low byte 0xFF

0x00 7F96 DM_CR1 DM debug module control register 1 0x00

0x00 7F97 DM_CR2 DM debug module control register 2 0x00

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0x00 7F98

DM_CSR1 DM debug module control/status register 1 0x10

0x00 7F99 DM_CSR2 DM debug module control/status register 2 0x00

0x00 7F9A DM_ENFCTR DM enable function register 0xFF

0x00 7F9B to

0x00 7F9F Reserved area (5 bytes)

1. Accessible by debug mo dule only

2. Product dependent value, see Figure 8: Memory map.

Table 10. CPU/SWIM/debug module/interrupt controller registers (continued)

Address Block Reg ister Label Register Name Reset

Status

Interrupt vector mapp ing STM8S207xx STM8S208xx

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7 Interrupt vector mapping

Table 11. Interrupt mapping

IRQ

no. Source

block Description Wakeup from

Halt mode Wakeup from

Active-halt mode Vec tor address

RESET Reset Yes Yes 0x00 8000

TRAP Software interrupt - - 0x00 8004

0 TLI External top level interrupt - - 0x00 8008

1 AWU Auto wake up from halt - Yes 0x00 800C

2 CLK Clock controller - - 0x00 8010

3 EXTI0 Port A external interrupts Yes(1) Yes(1) 0x00 8014

4 EXTI1 Port B external interrupts Yes Yes 0x00 8018

5 EXTI2 Port C external interrupts Yes Yes 0x00 801C

6 EXTI3 Port D external interrupts Yes Yes 0x00 8020

7 EXTI4 Port E external interrupts Yes Yes 0x00 8024

8 beCAN beCAN RX interrupt Yes Yes 0x00 8028

9 beCAN beCAN TX/ER/SC interrupt - - 0x00 802C

10 SPI End of transfer Yes Yes 0x00 8030

11 TIM1 TIM1 update/overflow/underflow/

trigger/break - - 0x00 8034

12 TIM1 TIM1 capture/compare - - 0x00 8038

13 TIM2 TIM2 update /overflow - - 0x00 803C

14 TIM2 TIM2 capture/compare - - 0x00 8040

15 TIM3 Update/overflow - - 0x00 8044

16 TIM3 Capture/compare - - 0x00 8048

17 UAR T1 Tx complete - - 0x00 804C

18 UART1 Receive register DATA FULL - - 0x00 8050

19 I2CI

2C interrupt Yes Yes 0x00 8054

20 UAR T3 Tx complete - - 0x00 8058

21 UART3 Receive register DATA FULL - - 0x00 805C

22 ADC2 ADC2 end of conversion - - 0x00 8060

23 TIM4 TIM4 update/overflow - - 0x00 8064

24 Flash EOP/WR_PG_DIS - - 0x00 8068

Reserved 0x00 806C to

0x00 807C

1. Except PA1

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STM8S207xx STM8S208xx Option bytes

116

8 Option bytes

Option bytes contain configurations for device hardware features as well as the memory

protection of the device. They are stored in a dedicated block of the memory. Except for the

ROP (read-out protection) byte, each option byte has to be stored twice, in a regular form

(OPTx) and a complemented one (NOPTx) for redundancy.

Option bytes can be modified in ICP mode (via SWIM) by accessing the EEPROM address

shown in Table 12: Option bytes below. Option bytes can also be modified ‘on the fly’ by the

application in IAP mode, except the ROP option that can only be modified in ICP mode (via

SWIM).

Refer to the STM8S Flash programming manual (PM0051) and STM8 SWIM

communication pro tocol and debug module user manual (UM0470) for infor mation on SWIM

programming procedures.

Table 12. Option bytes

Addr. Option

name Option

byte no.

Option bits Factory

default

setting

76543 2 1 0

4800h Read-out

protection

(ROP) OPT0 ROP[7:0] 00h

4801h User boot

code (UBC) OPT1 UBC[7:0] 00h

4802h NOPT1 NUBC[7:0] FFh

4803h Alternate

function

remapping

(AFR)

OPT2 AFR7 AFR6 AFR5 AFR4 AFR3 AFR2 AFR1 AFR0 00h

4804h NOPT2 NAFR7 NAFR6 NAFR5 NAFR4 NAFR3 NAFR2 NAFR1 NAFR0 FFh

4805h Watchdog

option

OPT3 Reserved LSI

_EN IWDG

_HW WWDG

_HALT 00h

4806h NOPT3 Reserved NLSI

_EN NIWDG

_HW NWWDG

_HALT FFh

4807h Clock option OPT4 Reserved EXT

CLK CKAWU

SEL PRS

C1 PRS

C0 00h

4808h NOPT4 Reserved NEXT

CLK NCKAWU

SEL NPR

SC1 NPR

SC0 FFh

4809h HSE clock

startup OPT5 HSECNT[7:0] 00h

480Ah NOPT5 NHSECNT[7:0] FFh

480Bh Reserved OPT6 Reserved 00h

480Ch NOPT6 Reserved FFh

480Dh Flash wait

states OPT7 Reserved Wait state 00h

480Eh NOPT7 Reserved Nwait state FFh

487Eh Bootloader OPTBL BL[7:0] 00h

487Fh NOPTBL NBL[7:0] FFh

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Ta ble 13. Option by te de sc rip tion

Option byte no. Description

OPT0

ROP[7:0] Memory readout protecti on (ROP)

0xAA: Enable readout protection (write access via SWIM protocol) 

Note: Refer to the family reference manual (RM0016) section on

Flash/EEPROM memory readout protection for details.

OPT1

UBC[7:0] User boot code area

0x00: no UBC, no write-protection

0x01: Pages 0 to 1 defined as UBC, memory write-protected

0x02: Pages 0 to 3 defined as UBC, memory write-protected

0x03: Pages 0 to 4 defined as UBC, memory write-protected

...

0xFE: Pages 0 to 255 defined as UBC, memory write-protected

0xFF: Reserved

Note: Refer to the family reference manual (RM0016) section on

Flash/EEPROM write protection for more details.

OPT2

AFR7Alternate function remapping option 7

0: Port D4 alternate function = TIM2_CH1

1: Port D4 alternate function = BEEP

AFR6 Alternate function remapping option 6

0: Port B5 alternate function = AIN5, port B4 alternate function = AIN4

1: Port B5 alternate function = I2C_SDA, port B4 alternate function =

I2C_SCL

AFR5 Alternate function remapping option 5

0: Port B3 alternate function = AIN3, port B2 alternate function = AIN2, 

port B1 alternate function = AIN1, port B0 alternate function = AIN 0

1: Port B3 alternate function = TIM1_ETR, port B2 alternate function =

TIM1_CH3N, port B1 alternate function = TIM1_CH2N, port B0 alternate

function = TIM1_CH1N

AFR4 Alternate function remapping option 4

0: Port D7 alternate function = TLI

1: Port D7 alternate function = TIM1_CH4

AFR3 Alternate function remapping option 3

0: Port D0 alternate function = TIM3_CH2

1: Port D0 alternate function = TIM1_BKIN

AFR2 Alternate function remapping option 2

0: Port D0 alternate function = TIM3_CH2

1: Port D0 alternate function = CLK_CCO

Note: AFR2 option has priority over AFR3 if both are activated

AFR1 Alternate function remapping option 1

0: Port A3 alternate function = TIM2_CH3, port D2 alternate function

TIM3_CH1

1: Port A3 alternate function = TIM3_CH1, port D2 alternate function

TIM2_CH3

AFR0 Alternate function remapping option 0

0: Port D3 alternate function = TIM2_CH2

1: Port D3 alternate function = ADC_ETR

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STM8S207xx STM8S208xx Option bytes

116

OPT3

LSI_EN: Low speed internal clock enable

0: LSI clock is not available as CPU clock source

1: LSI clock is available as CPU clock source

IWDG_HW: Independent watchdog

0: IWDG Independent watchdog activated by software

1: IWDG Independent watchdog activated by hardware

WWDG_HW: Window watchdog activation

0: WWDG window watchdog activated by software

1: WWDG window watchdog activated by hardware

WWDG_HALT: Window watchdog reset on halt

0: No reset generated on halt if WWDG active

1: Reset generated on halt if WWDG active

OPT4

EXTCLK: External clock selection

0: External crystal connected to OSCIN/OSCOUT

1: External clock signal on OSCIN

CKAWUSEL: Auto wakeup unit/clock

0: LSI clock source selected for AWU

1: HSE clock with prescaler selected as clock source for AWU

PRSC[1:0] AWU clock prescaler

00: 24 MHz to 128 kHz prescaler

01: 16 MHz to 128 kHz prescaler

10: 8 MHz to 128 kHz prescaler

11: 4 MHz to 128 kHz prescaler

OPT5

HSECNT[7:0]: HSE crystal oscillator stabilization time

This configures the stabilization time.

0x00: 2048 HSE cycles

0xB4: 128 HSE cycles

0xD2: 8 HSE cycles

0xE1: 0.5 HSE cycles

OPT6 Reserved

OPT7

WAITSTATE Wait state configuration

This option configures the number of wait states inserted when reading

from the Flash/data EEPROM memory. 

1 wait state is required if fCPU > 16 MHz.

0: No wait state

1: 1 wait state

Table 13. Option byte description (continued)

Option byte no. Description

Option bytes STM8S207xx STM8S208xx

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OPTBL

BL[7:0] Bootloader option byte

For STM8S products, this option is checked by the boot ROM code

after reset. Depending on the content of addresses 0x487E, 0x487F,

and 0x8000 (reset vector), the CPU jumps to the bootloader or to

the reset vector. Refer to the UM0560 (STM8L/S bootloader manual)

for more details.

For STM8L products, the bootloader option bytes are on addresses

0xXXXX and 0xXXXX+1 (2 bytes). These option bytes control

whether the bootloader is active or not. For more details, refer to the

UM0560 (STM8L/S bootloader manual) for more details.

Table 13. Option byte description (continued)

Option byte no. Description

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116

9 Unique ID

The devices feature a 96-bit unique device identifier which provides a reference number that

is unique for any device and in any context. The 96 bit s of the identifier can never b e altered

by the user.

The unique device identifier can be read in single bytes and may then be concatenated

using a custom algorithm.

The unique device identifier is ideally suited:

For use as serial numbers

For use as security keys to increase th e code security in the program memory while

using and combining this unique ID with software cryptographic primitives and

protocols before programming the internal memory.

To activate secure boot processes

Table 14. Unique ID registers (96 bits)

Address Content

description

Unique ID bits

76543 2 1 0

0x48CD X co-ordinate on the

wafer U_ID[7:0]

0x48CE U_ID[15:8]

0x48CF Y co-ordinate on the

wafer U_ID[23:16]

0x48D0 U_ID[31:24]

0x48D1 Wafer number U_ID[39:32]

0x48D2

Lot number

U_ID[47:40]

0x48D3 U_ID[55:48]

0x48D4 U_ID[63:56]

0x48D5 U_ID[71:64]

0x48D6 U_ID[79:72]

0x48D7 U_ID[87:80]

0x48D8 U_ID[95:88]

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10 Electrical characteristics

10.1 Parameter conditions

Unless otherwise specified, all voltages are referred to VSS.

10.1.1 Minimum and maximum values

Unless otherwise specified the minimum and maximum values are guaranteed in the worst

conditions of ambient temperature , supply voltage and fre quencies by tests in productio n on

100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by

the selected tem p er at ur e range).

Data base d on chara cte rization re su lts, design simulation a nd/or techno log y characteristics

are indicated in the table footn otes and are not tested in productio n. Based on

characterization, th e minimum and maximu m values refer to sample test s and represent the

mean value plus or minus three times the standard deviation (mean ± 3 ).

10.1.2 Typical values

Unless otherwise specified , typical d ata are based o n TA = 25 °C, VDD = 5 V. They are given

only as design guidelines and are not tested.

T ypi cal ADC accuracy values are d etermined by characterization of a batch of samples fr om

a standard diffusion lot over the full temperature range, where 95% of the devices have an

error less than or equal to the value indicated (mean ± 2 ).

10.1.3 Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are

not tested.

10.1.4 Typical current consumption

For typical current consumption measurements, VDD, VDDIO and VDDA are connected

together in the configuration shown in Figure 9.

Figure 9. Supply current measurement conditions

VDD

VDDA

VDDIO

VSS

VSSA

VSSIO

5 V or 3.3 V

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10.1.5 Pin loading conditions

10.1.6 Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 10.

Figure 10. Pin loading conditions

10.1.7 Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 11.

Figure 11. Pin input voltage

50 pF

STM8 pin

VIN

STM8 pin

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10.2 Absolute maximum ratings

Stresses above those listed as ‘absolute maximum ratings’ may cause permanent damage

to the device. This is a stress rating only and functional operation of the device under these

conditions is not implied. Exposure to maximum rating conditions for extended per iods m ay

affect device reliability.

Table 15. Voltage characteristics

Symbol Ratings Min Max Unit

VDDx - VSS Supply voltage (including VDDA and VDDIO)(1)

1. All power (VDD, VDDIO, VDDA) and ground (VSS, VSSIO, VSSA) pins must always be connected to the

external power supply

-0.3 6.5

VIN Input voltage on true open drain pins (PE1, PE2)(2)

2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum

cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive

injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. For true open-drain pads,

there is no positive injection current, and the corresponding VIN maximum must always be respected

VSS - 0.3 6.5

Input voltage on any other pin(2) VSS - 0.3 VDD + 0.3

|VDDx - VDD| Variations between different power pins 50 mV

|VSSx - VSS| Variations between all the different ground pins 50

VESD Electrostatic discharge voltage see Absolute maximum

ratings (electrical

sensitivity) on page 89

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Table 16. Current characteristics

Symbol Ratings Max.(1)

1. Data based on characterization results, not tested in production.

Unit

IVDD Total current into VDD power lines (source)(2)

2. All power (VDD, VDDIO, VDDA) and ground (VSS, VSSIO, VSSA) pins must always be connected to the

external supply.

IVSS Tot al current out of VSS ground lines (sink)(2) 60

IIO Output current sunk by any I/O and control pin 20

Output current source by any I/Os and control pin 20

IIO

Total output current sourced (sum of all I/O and control pins)

for devices with two VDDIO pi n s (3)

3. I/O pins used simultaneously for high current source/sink must be uniformly spaced around the package

between the VDDIO/VSSIO pins.

200

Total output current sourced (sum of all I/O and control pins)

for devices with one VDDIO pin(3) 100

Total output current sunk (sum of all I/O and control pins) for

devices with two VSSIO pins(3) 160

Total output current sunk (sum of all I/O and control pins) for

devices with one VSSIO pin(3) 80

IINJ(PIN)(4)(5)

4. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum

cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive

injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. For true open-drain pads,

there is no positive injection current, and the corresponding VIN maximum must always be respected

5. Ne gative injection disturbs the analog performance of the device. See note in Section 10.3.10: 10-bit ADC

characteristics on page 85.

Injected current on NRST pin ±4

Injected current on OSCIN pin ±4

Injected current on any other pin(6)

6. When several inputs are submitted to a current injection, the maximum IINJ(PIN) is the absolute sum of the

positive and negative injected currents (instant aneous values). These results are based on characterization

with IINJ(PIN) maximum current injection on four I/O port pins of the device.

±4

IINJ(PIN)(4) Total injected current (sum of all I/O and control pins)(6) ±20

Table 17. The rma l ch a racteristics

Symbol Ratings Value Unit

TSTG Storag e temperature range - 65 to 150 °C

TJMaximum junction temperature 150

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10.3 Operating conditions

The device must be use d in operating cond itions that re spect the p arameters in Table 18. In

addition, full account must be taken of all physical capacitor characteristics and tolerances.

Table 18. General operat ing conditions

Symbol Parameter Conditions Min M ax Unit

fCPU Internal CPU clock frequency TA  105 °C 0 24 MHz

0 16 MHz

VDD/VDD_IO Standard operating voltage 2.95 5.5 V

VCAP(1)

1. Care should be taken when selecting the capacitor, due to its tolerance, as well as the parameter

dependency on temperature, DC bias and frequency in addition to other factors. The parameter maximum

value must be respected for the full application range.

CEXT: capacitance of external

capacitor 470 3300 nF

ESR of external capacitor at 1 MHz(2)

2. This frequency of 1 MHz as a condition for VCAP parameters is given by design of internal regulator.

-0.3Ω

ESL of external capacitor - 15 nH

PD(3)

3. To calculate PDmax(TA), use the formula PDmax = (TJmax - TA)/JA (see Section 11.2: Thermal

characteristics on page 108) with the value for TJmax given in Table 18 above and the value for JA given in

Table 57: Thermal characteristics.

Power dissipation at 

TA = 85° C for suffix 6

or TA = 125° C for suffix 3

44, 48, 64, and 80-pin

devices, with output on 8

standard ports, 2 high sink

ports and 2 open drain ports

simultaneously(4)

4. Refer to Section 11.2: Thermal characteristics on page 108 for the calculation method.

443

32-pin package, with output

on 8 standard ports and 2

high sink ports

simultaneously(4) 360

Ambient temperature for 6

suffix version Maximum power dissipation -40 85

°C

Ambient temperature for 3

suffix version Maximum power dissipation -40 125

TJJunction temperature range 6 suffix version -40 105

3 suffix version -40 130(5)

5. TJmax is given by the test limit. Above this value the product behavior is not guaranteed.

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Figure 12. fCPUmax versus VDD

10.3.1 VCAP external capacitor

Stabilization for the main regulator is achieved connecting an external capacitor CEXT to the

VCAP pin. CEXT is specified in Table 18. Care shou ld be taken to limit the series inductance

to less than 15 nH.

Figure 13. External capacitor CEXT

1. Legend: ESR is the equivalent series resistance and ESL is the equivalent inductance.

Table 19. Operating conditions at power-up/power-down

Symbol Parameter Conditions Min Typ Max Unit

tVDD VDD rise time rate 2(1)

1. Guaranteed by design, not tested in production.

µs/V

VDD fall time rate 2(1) 

tTEMP Reset release

delay VDD rising 1.7(1) ms

VIT+ Power-o n reset

threshold 2.65 2.8 2.95 V

VIT- Brown-out reset

threshold 2.58 2.73 2.88 V

VHYS(BOR) Brown-out reset

hysteresis 70 mV

fCPU [MHz]

SUPPLY VOLTAGE [V]

02.95 4.0 5.0

FUNCTIONALITY

GUARANTEED

@ TA -40 to 125 °C

NOT GUARANTEED

IN THIS AREA 16

5.5

FUNCTIONALITY GUARANTEED

@ TA -40 to 105 °C

Rleak

ESR ESL

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10.3.2 Supply current characteristics

The current consumption is measured as described in Figure 9 on page 52.

Total current consumption in run mode

The MCU is placed under the following conditions:

All I/O pins in input mode with a static value at VDD or VSS (no load)

All peripherals are disab led (clo ck sto ppe d by Peripheral Clock Gating registers)

except if explicitly mentioned.

When the MCU is clocked at 24 MHz, TA  105 °C and the WAITSTATE option bit is set.

Subject to general operating conditions for VDD and TA.

Table 20. Total current consumption with code execution in run mode at VDD = 5 V

Symbol Parameter Conditions Typ Max Unit

IDD(RUN)

Supply

current in

run mode,

code

executed

from RAM

fCPU = fMASTER = 24 MHz, 

TA  105 °C HSE crystal osc. (24 MHz) 4.4

HSE user ext. clock (24 MHz) 3.7 7.3(1)

fCPU = fMASTER = 16 MHz

HSE crystal osc. (16 MHz) 3.3

HSE user ext. clock (16 MHz) 2.7 5.8

HSI RC osc. (16 MHz) 2.5 3.4

fCPU = fMASTER/128 = 125 kHz HSE user ext. clock (16 MHz) 1.2 4.1(1)

HSI RC osc. (16 MHz) 1.0 1.3(1)

fCPU = fMASTER/128 = 15.625

kHz HSI RC osc. (16 MHz/8) 0.55

fCPU = fMASTER = 128 kHz LSI RC osc. (128 kHz) 0.4 5

Supply

current in

run mode,

code

executed

from Flash

fCPU = fMASTER = 24 MHz,

TA  105 °C HSE crystal osc. (24 MHz) 11.4

HSE user ext. clock (24 MHz) 10.8 18(1)

fCPU = fMASTER = 16 MHz

HSE crystal osc. (16 MHz) 9.0

HSE user ext. clock (16 MHz) 8.2 15.2(1)

HSI RC osc.(16 MHz) 8.1 13.2(1)

fCPU = fMASTER = 2 MHz. HSI RC osc. (16 MHz/8)(2) 1.5

fCPU = fMASTER/128 = 125 kHz HSI RC osc. (16 MHz) 1.1

fCPU = fMASTER/128 = 15.625

kHz HSI RC osc. (16 MHz/8) 0.6

fCPU = fMASTER = 128 kHz LSI RC osc. (128 kHz) 0.5 5

1. Data based on characterization results, not tested in production.

2. Default clock configuration measured with all peripherals off.

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Table 21. Total current consumption with code execution in run mode at VDD = 3.3 V

Symbol Parameter Conditions Typ Max(1) Unit

IDD(RUN)

Supply

current in

run mode,

code

executed

from RAM

fCPU = fMASTER = 24 MHz, 

TA  105 °C HSE crystal osc. (24 MHz) 4.0

HSE user ext. clock (24 MHz) 3.7 7.3

fCPU = fMASTER = 16 MHz

HSE crystal osc. (16 MHz) 2.9

HSE user ext. clock (16 MHz) 2.7 5.8

HSI RC osc. (16 MHz) 2.5 3.4

fCPU = fMASTER/128 = 125 kHz HSE user ext. clock (16 MHz) 1.2 4.1

HSI RC osc. (16 MHz) 1.0 1.3

fCPU = fMASTER/128 = 15.625

kHz HSI RC osc. (16MHz/8) 0.55

fCPU = fMASTER = 128 kHz LSI RC osc. (128 kHz) 0.4 5

Supply

current in

run mode,

code

executed

from Flash

fCPU = fMASTER = 24 MHz,

TA  105 °C HSE crystal osc. (24 MHz) 11.0

HSE user ext. clock (24 MHz) 10.8 18.0

fCPU = fMASTER = 16 MHz

HSE crystal osc. (16 MHz) 8.4

HSE user ext. clock (16 MHz) 8.2 15.2

HSI RC osc. (16 MHz) 8.1 13.2

fCPU = fMASTER = 2 MHz. HSI RC osc. (16 MHz/8)(2) 1.5

fCPU = fMASTER/128 = 125 kHz HSI RC osc. (16 MHz) 1.1

fCPU = fMASTER/128 = 15.625

kHz HSI RC osc. (16 MHz/8) 0.6

fCPU = fMASTER = 128 kHz LSI RC osc. (128 kHz) 0.5 5

1. Data based on characterization results, not tested in production.

2. Default clock configuration.

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Total current consumption in wait mode

Table 22. Total cu rrent consumption in wait mode at VDD = 5 V

Symbol Parameter Conditions Typ Max(1) Unit

IDD(WFI)

Supply

current in

wait mode

fCPU = fMASTER = 24 MHz, 

TA  105 °C HSE crystal osc. (24 MHz) 2.4

HSE user ext. clock (24 MHz) 1.8 4.7

fCPU = fMASTER = 16 MH z

HSE crystal osc. (16 MHz) 2.0

HSE user ext. clock (16 MHz) 1.4 4.4

HSI RC osc. (16 MHz) 1.2 1.6

fCPU = fMASTER/128 = 125 kHz HSI RC osc. (16 MHz) 1.0

fCPU = fMASTER/128 = 15.625

kHz HSI RC osc. (16 MHz/8)(2) 0.55

fCPU = fMASTER = 128 kHz LSI RC osc. (128 kHz) 0.5

1. Data based on characterization results, not tested in production.

2. Default clock configuration measured with all peripherals off.

Table 23. Total current consumption in wait mode at VDD = 3.3 V

Symbol Parameter Conditions Typ Max(1) Unit

IDD(WFI)

Supply

current in

wait mode

fCPU = fMASTER = 24 MHz, 

TA  105 °C HSE crystal osc. (24 MHz) 2.0

HSE user ext. clock (24 MHz) 1.8 4.7

fCPU = fMASTER = 16 MHz

HSE crystal osc. (16 MHz) 1.6

HSE user ext. clock (16 MHz) 1.4 4.4

HSI RC osc. (16 MHz) 1.2 1.6

fCPU = fMASTER/128 = 125 kHz HSI RC osc. (16 MHz) 1.0

fCPU = fMASTER/128 = 15.625

kHz HSI RC osc. (16 MHz/8)(2) 0.55

fCPU = fMASTER/128 = 15.625

kHz LSI RC osc. (128 kHz) 0.5

1. Data based on characterization results, not tested in production.

2. Default clock configuration measured with all peripherals off.

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Total current consumption in active halt mode

Table 24. Total current consumption in active halt mode at VDD = 5 V, TA -40 to 85° C

Symbol Parameter

Conditions

Typ Max(1) Unit

Main voltage

regulator

(MVR)(2) Flash mode(3) Clock source

IDD(AH) Supply current in

active halt mod e

Operating mode

HSE crystal oscillator 

(16 MHz) 1000

µA

LSI RC oscillator 

(128 kHz) 200 260

Power-down mode

HSE crystal oscillator 

(16 MHz) 940

LSI RC oscillator 

(128 kHz) 140

Off Operating mode LSI RC oscillator 

128 kHz) 68

Power-down mode 11 45

1. Data based on characterization results, not tested in production.

2. Configured by the REGAH bit in the CLK_ICKR register.

3. Configured by the AHALT bit in the FLASH_CR1 register.

Table 25. Total current consumption in active halt mode at VDD = 3.3 V

Symbol Parameter

Conditions

Typ(1) Unit

Main voltage

regulator

(MVR)(2) Flash mode(3) Clock source

IDD(AH) Supply current in

active halt mode

Operating mode HSE crystal osc. (16 MHz) 600

µA

LSI RC osc. (128 kHz) 200

Power-down mode HSE crystal osc. (16 MHz) 540

LSI RC osc. (128 kHz) 140

Off Operating mode LSI RC osc. (128 kHz) 66

Power-down mode 9

1. Data based on characterization results, not tested in production.

2. Configured by the REGAH bit in the CLK_ICKR register.

3. Configured by the AHALT bit in the FLASH_CR1 register.

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Total current consumption in halt mode

Low power mode wakeup times

Table 26. Total current consumption in halt mode at VDD = 5 V

Symbol Parameter Conditions Typ Max at 85 °C Max at 125 °C Unit

IDD(H) Supply current in halt

mode

Flash in operating mode, HSI

clock after wakeup 63.5 µA

Flash in power-down mode,

HSI clock after wakeup 6.5 35 100

Table 27. Total current consumption in halt mode at VDD = 3.3 V

Symbol Parameter Conditions Typ Unit

IDD(H) Supply current in halt mode

Flash in operating mode, HSI clock after

wakeup 61.5 µA

Flash in power-down mode, HSI clock after

wakeup 4.5

Table 28. Wakeup times

Symbol Parameter Conditions Typ Max(1) Unit

tWU(WFI) Wakeup time from wait

mode to run mode(3)

See

note(2)

µs

fCPU = fMASTER = 16 MHz. 0.56

tWU(AH) Wakeup time active halt

mode to run mode.(3)

MVR voltage

regulator on(4)

Flash in operating

mode(5)

HSI (after

wakeup)

1(6) 2(6)

Flash in power-down

mode(5) 3(6)

MVR voltage

regulator off(4)

Flash in operating

mode(5) 48(6)

Flash in power-down

mode(5) 50(6)

tWU(H) Wakeup time from halt

mode to run mode(3) Flash in operating mode (5) 52

Flash in power-down mode(5) 54

1. Data guaranteed by design, not tested in production.

2. tWU(WFI) = 2 x 1/fmaster + 7 x 1/fCPU

3. Measured from interrupt event to interrupt vector fetch.

4. Configured by the REGAH bit in the CLK_ICKR register.

5. Configured by the AHALT bit in the FLASH_CR1 register.

6. Plus 1 LSI clock depending on synchronization.

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Total current consumption and timing in forced reset state

Current consumption of on-chip peripherals

Subject to general operating conditions for VDD and TA.

HSI internal RC/fCPU = fMASTER = 16 MHz.

Table 29. Total current consumption and timing in forced reset state

Symbol Parameter Conditions Typ Max(1) Unit

IDD(R) Supply cur rent in reset state VDD = 5 V 1.6 mA

VDD = 3.3 V 0.8

tRESETBL Reset release to bootloader vector

fetch 150 µs

1. Data guaranteed by design, not tested in production.

Table 30. Peripheral current consumption

Symbol Parameter Typ. Unit

IDD(TIM1) TIM1 supply current (1)

1. Data based on a differential IDD measurement between reset configuration and timer counter running at 

16 MHz. No IC/OC programmed (no I/O pads toggling). Not tested in production.

220

µA

IDD(TIM2) TIM2 supply current (1) 120

IDD(TIM3) TIM3 timer supply current (1) 100

IDD(TIM4) TIM4 timer supply current (1) 25

IDD(UART1) UART1 supply current (2)

2. Data based on a differential IDD measurement between the on-chip peripheral when kept under reset and

not clocked and the on-chip peripheral when clocked and not kept under reset. No I/O pads toggling. Not

tested in production.

IDD(UART3) UART3 supply current (2) 110

IDD(SPI) SPI supply current (2) 40

IDD(I2C) I2C supply current (2) 50

IDD(CAN) beCAN supply current (2) 210

IDD(ADC2) ADC2 supply current when converting (3)

3. Data based on a differential IDD measurement between reset configuration and continuous A/D

conversions. Not tested in production.

1000

Electrical characteristics STM8S207xx STM8S208xx

64/117 DocID14733 Rev 13

Current consumption curves

Figure 14 and Figure 15 show typical current consumption measured with code executing in

RAM.

Figure 14. Typ. IDD(RUN) vs VDD, HSI RC osc, fCPU = 16 MHz

Figure 15. Typ. IDD(WFI) vs VDD, HSI RC osc, fCPU = 16 MHz

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116

10.3.3 External clock sources and timing characteristics

HSE user external clock

Subject to general operating conditions for VDD and TA.

Figure 16. HSE external clock source

HSE crystal/ceramic resonator oscillator

The HSE clock can be supplied with a 1 to 24 MHz crystal/ceramic resonator oscillator. All

the information given in this paragraph is based on characterizatio n results with specified

typical external components. In the application, the resonator and the load capacitors have

to be placed as close as possible to the oscillator pins in order to minimize output distortion

and start-up stabilization time. Refer to the crystal resonator manufacturer for more details

(frequency, package, accuracy...).

Table 31. HSE user external clock characteristics

Symbol Parameter Conditions Min Typ Max Unit

fHSE_ext User external clock source

frequency 024MHz

VHSEH(1)

1. Data based on characterization results, not tested in production.

OSCIN input pin high level

voltage 0.7 x VDD VDD + 0.3 V V

VHSEL(1) OSCIN input pin low level

voltage VSS 0.3 x VDD

ILEAK_HSE OSCIN input leakage

current VSS < VIN < VDD -1 1 µA

OSCIN

fHSE

External clock

STM8

source

VHSEL

VHSEH

Electrical characteristics STM8S207xx STM8S208xx

66/117 DocID14733 Rev 13

Figure 17. HSE oscillator circuit diagram

HSE oscillator critical gm formula

Rm: Notional resistance (see crystal specification) 

Lm: Notional inductance (see crystal specification)

Cm: Notional capacit ance (see crystal specification)

Co: Shunt capacitance (see crystal specification)

CL1=CL2=C: Grounde d external capacitance

gm >> gmcrit

Table 32. HSE oscillator characteristics

Symbol Parameter Conditions Min Typ Max Unit

fHSE External high speed oscillator

frequency 124MHz

RFFeedback resistor 220 k

C(1) Recommended load capacitance (2) 20 pF

IDD(HSE) HSE oscillator power consumption

C = 20 pF,

fOSC = 24 MHz 6 (startup)

2 (stabilized)(3) mA

C = 10 pF,

fOSC = 24 MHz 6 (startup)

1.5 (stabilized)(3)

gmOscillator transconductance 5 mA/V

tSU(HSE)(4) Startup time VDD is stabilized 1 ms

1. C is approximately equivalent to 2 x crystal Cload.

2. The oscillator selection can be optimized in terms of supply current using a high quality resonator with small Rm value.

Refer to crystal manufacturer for more details

3. Data based on characterization results, not tested in production.

4. tSU(HSE) is the start-up time measured from the moment it is enabled (by software) to a stabilized 24 MHz oscillation is

reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.

OSCOUT

OSCIN

HSE

to core

STM8

Resonator

Consumption

control

Resonator

gmcrit 2 fHSE



2Rm

2Co C+

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10.3.4 Internal clock sources and timing characteristics

Subject to general operating conditions for VDD and TA. fHSE

High speed internal RC oscillator (HSI)

Figure 18. Typical HSI frequency variation vs VDD at 4 temperatures

Table 33. HSI oscillator characteristics

Symbol Parameter Conditions Min Typ Max Unit

fHSI Frequency 16 MHz

ACCHSI

Accuracy of HSI oscillator

Trimmed by the

CLK_HSITRIMR register

for given VDD and TA

conditions

-1.0(1)

1. Guaranteed by design, not tested in production.

1.0

Accuracy of HSI oscillator

(factory calibrated)

VDD = 5 V, TA = 25 °C -1.5 1.5

VDD  5 V, 

25 °C TA  85 °C -2.2 2.2

2.95 V  VDD  5.5 V,

-40 °C TA  125 °C -3.0(2)

2. Data based on characterization results, not tested in production

3.0(2)

tsu(HSI) HSI oscillator wakeup

time including calibration 1.0(1) µs

IDD(HSI) HSI oscillator power

consumption 170 250(2) µA

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Electrical characteristics STM8S207xx STM8S208xx

68/117 DocID14733 Rev 13

Low speed internal RC oscillator (LSI)

Subject to general operating conditions for VDD and TA.

Figure 19. Typical LSI frequency variation vs VDD @ 25 °C

Table 34. LSI oscillator characteristics

Symbol Parameter Conditions Min Typ Max Unit

fLSI Frequency 110 128 146 kHz

tsu(LSI) LSI oscillator wakeup time 7(1)

1. Guaranteed by design, not tested in production.

µs

IDD(LSI) LSI oscillator power consumption 5 µA

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10.3.5 Memory characteristics

RAM and hardware registers

Flash program memory/data EEPROM memory

General conditions: TA = -40 to 125 °C.

Table 35. RAM and hardware registers

Symbol Parameter Conditions Min Unit

VRM Data retention mode(1)

1. Minimum supply voltage without losing data stored in RAM (in halt mode or under reset) or in hardware

registers (only in halt mode). Guaranteed by design, not tested in production.

Halt mode (or reset) VIT-max(2)

2. Refer to Table 19 on page 57 for the value of VIT-max.

Table 36. Flash program memory/data EEPROM memory

Symbol Parameter Conditions Min(1)

1. Data based on characterization results, not tested in production.

Typ Max Unit

VDD Operating voltage 

(all modes, execution/write/erase) fCPU  24 MHz 2.95 5.5 V

tprog

Standard programming time (including

erase) for byte/word/block 

(1 byte/4 bytes/128 bytes) 66.6ms

Fast programming time for 1 block

(128 bytes) 33.3ms

terase Erase time for 1 block (128 bytes) 3 3.3 ms

NRW

Erase/write cycles(2) 

(program memory)

2. The physical granularity of the memory is 4 bytes, so cycling is performed on 4 bytes even when a

write/erase operation addresses a single byte.

TA 85 °C 10 k cycles

Erase/write cycles (data memory)(2) TA 125 ° C 300 k 1M

tRET

Data retention (program memory)

after 10 k erase/write cycles at 

TA 85 °C TRET = 55° C 20

years

Data retention (dat a memory) after 10

k erase/write cycles at TA 85 °C TRET = 55° C 20

Data retention (data memory) after

300k erase/write cycles at 

TA 125 °C TRET = 85° C 1

IDD Supply current (Flash programming or

erasing for 1 to 128 bytes) 2mA

Electrical characteristics STM8S207xx STM8S208xx

70/117 DocID14733 Rev 13

10.3.6 I/O port pin characteristics

General characteristics

Subject to general operating conditions for VDD and TA unless otherwise specified. All

unused pins must be ke pt at a fixed volta ge: using the output mode of the I/O for example or

an external pull-up or pull-down r esistor.

Tabl e 37. I/O static characteris tic s

Symbol Parameter Conditions Min Typ Max Unit

VIL Input low level

voltage

VDD = 5 V

-0.3 0.3 x VDD V

VIH Input high level

voltage 0.7 x VDD VDD + 0.3 V

Vhys Hysteresis(1) 700 mV

Rpu Pull-up resistor VDD = 5 V, VIN = VSS 30 55 80 k

tR, tFRise and fall time

(10% - 90%)

Fast I/Os

Load = 50 pF 20 (2)

Standard and high sink I/Os

Load = 50 pF 125 (2)

Fast I/Os

Load = 20 pF 35(3)

Standard and high sink I/Os

Load = 20 pF 125(3)

Ilkg

Input leakage

current,

analog and digital VSS  VIN VDD ±1 µA

Ilkg ana Analog input

leakage current VSS VIN VDD ±250 (2) nA

Ilkg(inj) Leakage current in

adjacent I/O(2) Injection current ±4 mA ±1(2) µA

1. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested in production.

2. Data based on characterization results, not tested in production.

3. Guaranteed by design.

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Figure 20. Typical VIL and VIH vs VDD @ 4 temperatures

Figure 21. Typical pull-up resistance vs VDD @ 4 temperatures

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72/117 DocID14733 Rev 13

Figure 22. Typical pull-up current vs VDD @ 4 temperatures

1. The pull-up is a pure resistor (slope goes through 0).

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Table 38. Output driving current (standard ports)

Symbol Parameter Conditions Min Max Unit

VOL Output low level with 8 pins sunk IIO = 10 mA, VDD = 5 V 2 V

Output low level with 4 pins sunk IIO = 4 mA, VDD = 3.3 V 1(1)

VOH Output high level with 8 pins sourced IIO = 10 mA, VDD = 5 V 2.8 V

Output high level with 4 pins sourced IIO = 4 mA, VDD = 3.3 V 2.1(1)

1. Data based on characterization results, not tested in production

Table 39. Output driving current (true open drain ports)

Symbol Parameter Conditions Max Unit

VOL Output low level with 2 pins sunk

IIO = 10 mA, VDD = 5 V 1

VIIO = 10 mA, VDD = 3.3 V 1.5(1)

IIO = 20 mA, VDD = 5 V 2(1)

1. Data based on characterization results, not tested in production

Table 40. Output driving current (high sink ports)

Symbol Parameter Conditions Min Max Unit

VOL

Output low level with 8 pins sunk IIO = 10 mA, VDD = 5 V 0.8

Output low level with 4 pins sunk IIO = 10 mA, VDD = 3.3 V 1(1)

Output low level with 4 pins sunk IIO = 20 mA, VDD = 5 V 1.5(1)

VOH

Output high level with 8 pins sourced IIO = 10 mA, VDD = 5 V 4.0

Output high level with 4 pins sourced IIO = 10 mA, VDD = 3.3 V 2.1(1)

Output high level with 4 pins sourced IIO = 20 mA, VDD = 5 V 3.3(1)

1. Data based on characterization results, not tested in production

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Typical output level curves

Figure 24 to Figure 31 show typical output level curves measured with output on a single

pin.

Figure 23. Typ. VOL @ VDD = 5 V (standard ports)

Figure 24. Typ. VOL @ VDD = 3.3 V (stan d a rd ports)

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74/117 DocID14733 Rev 13

Figure 25. Typ. VOL @ VDD = 5 V (true open drain ports)

Figure 26. Typ. VOL @ VDD = 3.3 V (true open dr ain ports)

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Figure 27. Typ. VOL @ VDD = 5 V (high sink ports)

Figure 28. Typ. VOL @ VDD = 3.3 V (high sink ports)

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76/117 DocID14733 Rev 13

Figure 29. Typ. VDD - VOH @ VDD = 5 V (standard ports)

Figure 30. Typ. VDD - VOH @ VDD = 3.3 V (standard ports)

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Figure 31. Typ. VDD - VOH @ VDD = 5 V (high sink ports)

Figure 32. Typ. VDD - VOH @ VDD = 3.3 V (high sink ports)

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78/117 DocID14733 Rev 13

10.3.7 Reset pin characteristics

Subject to general operating conditions for VDD and TA unless otherwise specified.

Figure 33. Typical NRST VIL and VIH vs VDD @ 4 temperatures

Table 41. NRST pin characteristics

Symbol Parameter Conditions Min Typ 1) Max Unit

VIL(NRST) NRST Input low level voltage (1) -0.3 V 0.3 x VDD

VVIH(NRST) NRST Input high level voltage (1) 0.7 x VDD VDD + 0.3

VOL(NRST) NRST Output low level voltage (1) IOL= 2 mA 0.5

RPU(NRST) NRST Pull-up resistor (2) 30 55 80 k

tIFP(NRST) NRST Input filtered pulse (3) 75 ns

tINFP(NRST) NRST Input not filtered pulse (3) 500 ns

tOP(NRST) NRST output pulse (1) 15 µs

1. Data based on characterization results, not tested in production.

2. The RPU pull-up equivalent resistor is based on a resistive transistor

3. Data guaranteed by design, not tested in production.

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DocID14733 Rev 13 79/117

STM8S207xx ST M8S2 08 xx Electrical chara cte ri st ic s

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Figure 34. Typical NRST pull-up resistance vs VDD @ 4 temperatures

Figure 35. Typical NRST pull -u p current vs VDD @ 4 temperatures

The reset network shown in Figure 36 protects the device against parasitic resets. The user

must ensure that the level on the NRST pin can go below the VIL max. level specified in

Table 41. Otherwise the reset is not taken into account internally. For power consumption

sensitive applications, the cap acity of the external reset capacitor can be reduced to limit

charge/discharge current. If the NRSTsignal is used to reset the external circuitry, care must

be taken of the charge/discharge time of the external capacitor to fulfill the external device’s

reset timing conditions. The minimum recommended capacity is 10 nF.

Figure 36. Recommended reset pin protection

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Electrical characteristics STM8S207xx STM8S208xx

80/117 DocID14733 Rev 13

10.3.8 SPI serial peripheral interface

Unless otherwise specified, the parameters given in Table 42 are derived from tests

performed under ambient temperature, fMASTER frequency and VDD supply voltage

conditions. tMASTER = 1/fMASTER.

Refer to I/O port characteristics for more details on the input/output alternate function

characteristics (NSS, SCK, MOSI, MISO).

Tabl e 42 . SPI ch ara ct e ri st ic s

Symbol Parameter Conditions Min Max Unit

fSCK

1/tc(SCK) SPI clock frequency Master mode 0 10 MHz

Slave mode 0 6

tr(SCK)

tf(SCK) SPI clock rise and fall time Capacitive load: C = 30 pF 25

tsu(NSS)(1) NSS setup time Slave mode 4 x tMASTER

th(NSS)(1) NSS hold time Slave mode 70

tw(SCKH)(1)

tw(SCKL)(1) SCK high and low time Master mode tSCK/2 - 15 tSCK/2 + 15

tsu(MI) (1)

tsu(SI)(1) Data input setup time Master mode 5

Slave mode 5

th(MI) (1)

th(SI)(1) Data input hold time Master mode 7

Slave mode 10

ta(SO)(1)(2) Data output access time Slave mode 3 x tMASTER

tdis(SO)(1)(3) Data output disable time Slave mode 25

tv(SO) (1) Data output valid time Slave mode (after enable edge) 75

tv(MO)(1) Data output valid time Master mode (after enable edge) 30

th(SO)(1) Data output hold time Slave mode (after enable edge) 31

th(MO)(1) Master mode (after enable edge) 12

1. Values based on design simulation and/or characterization results, and not tested in production.

2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data.

3. Min time is for th e minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z.

DocID14733 Rev 13 81/117

STM8S207xx ST M8S2 08 xx Electrical chara cte ri st ic s

116

Figure 37. SPI timing diagram - slave mode and CPHA = 0

Figure 38. SPI timing diagram - slave mode and CPHA = 1(1)

1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD.

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82/117 DocID14733 Rev 13

Figure 39. SPI timing diagram - master mode(1)

1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD.

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DocID14733 Rev 13 83/117

STM8S207xx ST M8S2 08 xx Electrical chara cte ri st ic s

116

10.3.9 I2C interface characteristics

Table 43. I2C characteristics

Symbol Parameter Standard mode I2CFast mode I

2C(1)

1. fMASTER, must be at least 8 MHz to achieve max fast I2C speed (400kHz)

Unit

Min(2)

2. Data based on standard I2C protocol requirement, not tested in production

Max(2) Min(2) Max(2)

tw(SCLL) SCL clock low time 4.7 1.3 µs

tw(SCLH) SCL clock high time 4.0 0.6

tsu(SDA) SDA setup time 250 100

th(SDA) SDA data hold time 0(3)

3. The maximum hold time of the start condition has only to be met if the interface does not stretch the low

time

0(4)

4. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the

undefined region of the falling edge of SCL

900(3)

tr(SDA)

tr(SCL) SDA and SCL rise time 1000 300

tf(SDA)

tf(SCL) SDA and SCL fall time 300 300

th(STA) START cond iti o n ho l d ti me 4.0 0.6 µs

tsu(STA) Repeated START condition setu p time 4.7 0.6

tsu(STO) STOP co nd iti o n setup time 4.0 0.6 µs

tw(STO:STA) STOP to START condition time 

(bus free) 4.7 1.3 µs

CbCapacitive load for each bus line 400 400 pF

Electrical characteristics STM8S207xx STM8S208xx

84/117 DocID14733 Rev 13

Figure 40. Typical application with I2C bus and timing diagram

1. Measurement points are made at CMOS levels: 0.3 x VDD and 0.7 x VDD

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STM8S207xx ST M8S2 08 xx Electrical chara cte ri st ic s

116

10.3.10 10-bit ADC characteristics

Subject to general operating conditions for VDDA, fMASTER, and TA unless otherwise

specified.

Table 44. ADC characteristics

Symbol Parameter Conditions Min Typ Max Unit

fADC ADC clock frequency VDDA = 3 to 5.5 V 1 4 MHz

VDDA = 4.5 to 5.5 V 1 6

VDDA Analog supply 3 5.5 V

VREF+ Positive reference voltage 2.75(1)

1. Da ta guaranteed by design, not tested in production.

VDDA V

VREF- Negative reference voltage VSSA 0.5(1) V

VAIN Conversion voltage range(2)

2. During the sample time the input capacitance CAIN (3 pF max) can be charged/discharged by the external

source. The internal resistance of the analog source must allow the capacitance to reach its final voltage

level within tS. After the end of the sample time tS, changes of the analog input voltage have no effect on

the conversion result. Values for the sample clock tS depend on programming.

VSSA VDDA V

Devices with external

VREF+/VREF- pins VREF- VREF+ V

CADC Internal sample and hold

capacitor 3pF

tS(2) Sampling time fADC = 4 MHz 0.75 µs

fADC = 6 MHz 0.5

tSTAB Wakeup time from standby 7 µs

tCONV Total conversion time (including

sampling time, 10-bit resolution)

fADC = 4 MHz 3.5 µs

fADC = 6 MHz 2.33 µs

14 1/fADC

Electrical characteristics STM8S207xx STM8S208xx

86/117 DocID14733 Rev 13

Table 45. ADC accuracy with RAIN < 10 k, VDDA = 5 V

Symbol Parameter Conditions Typ Max(1)

1. Data based on characterization results for LQFP80 device with VREF+/VREF-, not tested in production.

Unit

|ET| Total unadjusted error (2)

2. ADC accuracy vs. negative injection current: Injecting negative current on any of the analog input pins

should be avoided as this significantly reduces the accuracy of the conversion being performed on another

analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may

potentially inject negative current. Any positive injection current within the limits specified for IINJ(PIN) and

IINJ(PIN) in Section 10.3.6 does not affect the ADC accuracy.

fADC = 2 MHz 1 2.5

LSB

fADC = 4 MHz 1 .4 3

fADC = 6 MHz 1.6 3.5

|EO| Offset error (2)

fADC = 2 MHz 0 .6 2

fADC = 4 MHz 1.1 2.5

fADC = 6 MHz 1.2 2.5

|EG| Gain error (2)

fADC = 2 MHz 0 .2 2

fADC = 4 MHz 0.6 2.5

fADC = 6 MHz 0.8 2.5

|ED| Differential linearity error (2)

fADC = 2 MHz 0.7 1.5

fADC = 4 MHz 0.7 1.5

fADC = 6 MHz 0.8 1.5

|EL| Integral linearity error (2)

fADC = 2 MHz 0.6 1.5

fADC = 4 MHz 0.6 1.5

fADC = 6 MHz 0.6 1.5

Table 46. ADC accuracy with RAIN < 10 kRAIN, VDDA = 3.3 V

Symbol Parameter Conditions Typ Max(1) Unit

|ET| Total unadjusted error(2) fADC = 2 MHz 1.1 2

LSB

fADC = 4 MHz 1.6 2.5

|EO| Offset error(2) fADC = 2 MHz 0.7 1.5

fADC = 4 MHz 1 .3 2

|EG| Gain error(2) fADC = 2 MHz 0.2 1.5

fADC = 4 MHz 0 .5 2

|ED| Differential linearity error(2) fADC = 2 MHz 0.7 1

fADC = 4 MHz 0 .7 1

|EL| Integral linearity error(2) fADC = 2 MHz 0.6 1.5

fADC = 4 MHz 0.6 1.5

DocID14733 Rev 13 87/117

STM8S207xx ST M8S2 08 xx Electrical chara cte ri st ic s

116

Figure 41. ADC accuracy characteristics

1. Example of an actual transfer curve.

2. The ideal transfer curve

3. End point correlation line

ET = Total unadjusted error: maximum deviation between the actual and the ideal transfer curves.

EO = Offset error: deviation between the first actual transition and the first ideal one.

EG = Gain error: deviation between the last ideal transition and the last actual one.

ED = Differential linearity error: maximum deviation between actual steps and the ideal one.

EL = Integral linearity error: maximum deviation between any actual transition and the end point correlation

line.

Figure 42. Typical application with ADC

1LSB

IDEAL

1LSBIDEAL VDDA VSSA

–

1024

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1022

1021

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Electrical characteristics STM8S207xx STM8S208xx

88/117 DocID14733 Rev 13

10.3.11 EMC characteristics

Susceptibility tests are performed on a sample basis during product characterization.

Functional EMS (electromagnetic susceptibility)

While executing a simple application (toggling 2 LEDs through I/O ports), the product is

stressed by two electromagnetic events until a failure occurs (indicated by the LEDs).

ESD: Electrostatic discharge (p ositive and n egati ve) is applie d on all pins of the device

until a functional disturbance occurs. This test conforms with the IEC 61000-4-2

standard.

FTB: A burst of fa st transient volt age (positive and negative) is a pplied to V DD and VSS

through a 100 pF capacitor, until a functional disturbance occu rs. This test conforms

with the IEC 61000-4-4 standard.

A device reset allows normal operations to be resumed. The test results are given in the

table be low based on the EMS levels and classes defined in application note AN1709.

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical

application environment and simplified MCU software. It should be noted that go od EMC

performance is highly dependent on the user application and the software in particular.

Therefore it is recommended that the user applies EMC software optimization and

prequalification tests in relation with the EMC level requested for his application.

Software recommendations

The software flowchar t must include the management of runaway conditions such as:

Corrupted program counter

Unexpected reset

Critical data corruption (control registers...)

Prequalification trials

Most of the common failures (unexpected reset and pr ogram counter corruption) can be

recovered by applying a low state on the NRST pin or the oscillator pins for 1 second.

To complete these trials, ESD stress can be applied directly on the device, over the range of

specification values. When unexpe cted beh avior is detected, the software can be hardened

to prevent unrecoverable errors occurring (see application note AN1015).

Table 47. EMS data

Symbol Parameter Conditions Level/class

VFESD Voltage limits to be applied on any I/O pin to

induce a functional disturbance

VDD 5 V, TA 25 °C, 

fMASTER 16 MHz,

conforming to IEC 61000-4-2 2B

VEFTB

Fast transient voltage burst limits to be

applied through 100pF on VDD and VSS pins

to induce a functional disturbance

VDD 5 V, TA 25 °C, 

fMASTER 16 MHz, 

conforming to IEC 61000-4-4 4A

DocID14733 Rev 13 89/117

STM8S207xx ST M8S2 08 xx Electrical chara cte ri st ic s

116

Electromagnetic interference (EMI)

Emission tests conform to the SAE IEC 61967-2 standard for test software, board layout

and pin loading.

Absolute maximum ratings (electrical sensitivity)

Based on two different tests (ESD and LU) using specific measurement methods, the

product is stressed in order to determine its performance in terms of electrical sensitivity.

For more details, refer to the application note AN1181.

Electrosta tic discharge (ESD)

Electrostatic discharges (3 positive then 3 negative pulses separated by 1 second) are

applied to the pins of each sample according to each pin combination. The sample size

depends on the number of supply pins in the device (3 parts*(n+1) supply pin). This test

conforms to the JESD22-A114A/A115A standard. For more det ails, refer to the application

note AN1181.

Table 48. EMI data

Symbol Parameter

Conditions

Unit

General conditions Monitored

frequency band

Max fHSE/fCPU(1)

8 MHz/

8 MHz 8 MHz/

16 MHz 8 MHz/

24 MHz

SEMI

Peak level VDD 5 V 

TA 25 °C

LQFP80 package

conforming to SAE IEC

61967-2

0.1MHz to 30 MHz 15 20 24

dBµV30 MHz to 130 MHz 18 21 16

130 MHz to 1 GHz -1 1 4

SAE EMI

level SAE EMI level 2 2.5 2.5

1. Data based on characterization results, not tested in production.

Table 49. ESD absolute maximum ratings

Symbol Ratings Conditions Class Maximum

value(1)

1. Data based on characterization results, not tested in production.

Unit

VESD(HBM) Electrost atic discharge volt age

(Human body model) TA 25°C, conforming to

JESD22-A114 A 2000 V

VESD(CDM) Electrostatic discharge voltage

(Charge device model) TA 25°C, conforming to

JESD22-C101 IV 1000 V

Electrical characteristics STM8S207xx STM8S208xx

90/117 DocID14733 Rev 13

Static latch-up

Two comp lem e ntary static tests are required on 10 parts to assess the latch-up

performance:

A supply overvoltage (applied to each power supply pin)

A current injection (applie d to each input, o utput and con figurable I/O pin) is p erformed

on each sample.

This test conforms to the EIA/JESD 78 IC latch-up standard. For mo re details, refer to the

application note AN1181.

Table 50. Electrical sensitivities

Symbol Parameter Conditions Class(1)

1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the

JEDEC specifications, that means when a device belo ngs to class A it exceeds the JEDEC standard. B

class strictly covers all the JEDEC criteria (international standard).

LU Static latch-up class

TA 25 °C A

TA 85 °C A

TA 125 °C A

DocID14733 Rev 13 91/117

STM8S207xx STM8S208xx Package characteristics

116

11 Package characteristics

To meet environmental requirements, ST offers these devices in different grades of

ECOPACK® packages, depending on their level of environment al compliance. ECOPACK®

specifications, grade definitions and product status are available at www.st.com.

ECOPACK® is an ST trademark.

Package characteristics STM8S 207xx STM8S208xx

92/117 DocID14733 Rev 13

11.1 Package information

11.1.1 LQF P80 package information

Figure 43. LQFP80 - 80-pin, 14 x 14 mm low-profile quad flat package outline

1. Drawing is not to scale.

Table 51. LQFP80 - 80-pin, 14 x 14 mm low-profile quad flat package mechanical

data(1)

Symbol millimeters inches

Min Typ Max Min Typ Max

A - - 1.600 - - 0.0630

A1 0.050 - 0.150 0.0020 - 0.0059

A2 1.350 1.400 1.450 0.0531 0.0551 0.0571

b 0.220 0.320 0.380 0.0087 0.0126 0.0150

c 0.090 - 0.200 0.0035 - 0.0079

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STM8S207xx STM8S208xx Package characteristics

116

Figure 44. LQFP80 recommended footprint

D 15.800 16.000 16.200 0.6220 0.6299 0.6378

D1 13.800 14.000 14.200 0.5433 0.5512 0.5591

D3 - 12.350 - - 0.4862 -

E 15.800 16.000 16.200 0.6220 0.6299 0.6378

E1 13.800 14.000 14.200 0.5433 0.5512 0.5591

E3 - 12.350 - - 0.4862 -

e - 0.650 - - 0.0256 -

L 0.450 0.600 0.750 0.0177 0.0236 0.0295

L1 - 1.000 - - 0.0394 -

k 0°3.5°7° 0°3.5°7°

ccc - - 0.100 - - 0.0039

1. Values in inches are converted from mm and rounded to 4 decimal digits.

Table 51. LQFP80 - 80-pin, 14 x 14 mm low-profile quad flat package mechanical

data(1) (continued)

Symbol millimeters inches

Min Typ Max Min Typ Max

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94/117 DocID14733 Rev 13

Device marking

The following figure shows the markin g for the LQFP80 pa ckage.

Figure 45. LQFP80 marking example (package top view)

1. Parts marked as “ES”,”E” or accompanied by an Engineering Sample notification letter, are not yet

qualified and therefore not yet ready to be used in production and any consequences deriving from such

usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering

samples in production. ST Quality has to be contacted prior to any decision to use these Engineering

samples to run qualification activity.

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STM8S207xx STM8S208xx Package characteristics

116

11.1.2 LQF P64 package information

Figure 46. LQFP64 - 64-pin 14 mm x 14 mm low- profile quad flat package outline

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data

Symbol mm inches(1)

Min Typ Max Min Typ Max

A1.600 0.0630

A1 0.050 0.150 0.0020 0.0059

A2 1.350 1.400 1.450 0.0531 0.0551 0.0571

b0.300 0.370 0.450 0.0118 0.0146 0.0177

C0.090 0.200 0.0035 0.0079

D 15.800 16.000 16.200 0.6220 0.6299 0.6378

D1 13.800 14.000 14.200 0.5433 0.5512 0.5591

D3 12.000 0.4724

E 15.800 16.000 16.200 0.6220 0.6299 0.6378

E1 13.800 14.000 14.200 0.5433 0.5512 0.5591

E3 12.000 0.4724

e0.800 0.0315

L0.450

0.600 0.750 0.0177 0.0236 0.0295

L1 1.000 0.0394

Package characteristics STM8S 207xx STM8S208xx

96/117 DocID14733 Rev 13

Figure 47. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package outline

k 0.0 ° 3.5 ° 7.0 ° 0.0 ° 3.5 ° 7.0 °

ccc 0.100 0.0039

1. Values in inches are converted from mm and rounded to four decimal places.

Table 53. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package mechanical

data

Symbol mm inches(1)

Min Typ Max Min Typ Max

A - - 1.600 - - 0.0630

A1 0.050 - 0.150 0.0020 - 0.0059

A2 1.350 1.400 1.450 0.0531 0.0551 0.0571

b 0.170 0.220 0.270 0.0067 0.0087 0.0106

c 0.090 - 0.200 0.0035 - 0.0079

Table 52. LQFP64 - 64-pin, 14 x 14 mm low-profile quad flat package mechanical

data (continued)

Symbol mm inches(1)

Min Typ Max Min Typ Max

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DocID14733 Rev 13 97/117

STM8S207xx STM8S208xx Package characteristics

116

Figure 48. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat recommended footprint

D - 12.000 - - 0.4724 -

D1 - 10.000 - - 0.3937 -

D3 - 7.500 - - 0.2953 -

E - 12.000 - - 0.4724 -

E1 - 10.000 - - 0.3937 -

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Table 53. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package mechanical

data (continued)

Symbol mm inches(1)

Min Typ Max Min Typ Max

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Package characteristics STM8S 207xx STM8S208xx

98/117 DocID14733 Rev 13

Device marking

The following figure shows the markin g for the LQFP64 pa ckage.

Figure 49. LQFP64 marking example (package top view)

1. Parts marked as “ES”,”E” or accompanied by an Engineering Sample notification letter, are not yet

qualified and therefore not yet ready to be used in production and any consequences deriving from such

usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering

samples in production. ST Quality has to be contacted prior to any decision to use these Engineering

samples to run qualification activity.

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DocID14733 Rev 13 99/117

STM8S207xx STM8S208xx Package characteristics

116

11.1.3 LQF P48 package information

Figure 50. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package outline

Table 54. LQFP48 - 48-pin, 7x 7 mm low-profile quad flat package mechanica l

Symbol mm inches(1)

Min Typ Max Min Typ Max

A - - 1.600 - - 0.0630

A1 0.050 - 0.150 0.0020 - 0 .0059

A2 1.350 1.400 1.450 0.0531 0.0551 0.0571

b 0.170 0.220 0.270 0.0067 0.0087 0.0106

c 0.090 - 0.200 0.0035 - 0.0079

D 8.800 9.000 9.200 0.3465 0.3543 0.3622

D1 6.800 7.000 7.200 0.2677 0.2756 0.2835

D3 - 5.500 - - 0.2165 -

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100/117 DocID14733 Rev 13

Figure 51. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat recommended footprint

1. Dimensions are expressed in millimeters.

E1 6.800 7.000 7.200 0.2677 0.2756 0.2835

E3 - 5.500 - - 0.2165 -

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Table 54. LQFP48 - 48-pin, 7x 7 mm low-profile quad flat package mechanica l

(continued)

Symbol mm inches(1)

Min Typ Max Min Typ Max

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DocID14733 Rev 13 101/117

STM8S207xx STM8S208xx Package characteristics

116

Device marking

The following figure shows the markin g for the LQFP48 pa ckage.

Figure 52. LQFP48 marking example (package top view)

1. Parts marked as “ES”,”E” or accompanied by an Engineering Sample notification letter, are not yet

qualified and therefore not yet ready to be used in production and any consequences deriving from such

usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering

samples in production. ST Quality has to be contacted prior to any decision to use these Engineering

samples to run qualification activity.

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11.1.4 LQF P44 package information

Figure 53. LQFP44 - 44-pin, 10 x 10 mm low-profile quad flat package outline

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STM8S207xx STM8S208xx Package characteristics

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Table 55. LQFP44 - 44-pin, 10 x 10 mm low-profile quad flat package mechanical

data

Symbol mm inches(1)

1. Values in inches are converted from mm and rounded to four decimal places.

Min Typ Max Min Typ Max

A - - 1.600 - - 0.0630

A1 0.050 - 0.150 0.0020 - 0.0059

A2 1.350 1.400 1.450 0.0531 0.0551 0.0571

b 0.300 0.370 0.450 0.0118 0.0146 0.0177

c 0.090 - 0.200 0.0035 0.0079

D 11.800 12.000 12.200 0.4646 0.4724 0.4803

D1 9.800 10.000 10.200 0.3858 0.3937 0.4016

D3 - 8.000 - - 0.3150 -

E 11.800 12.000 12.200 0.4646 0.4724 0.4803

E1 9.800 10.000 10.200 0.3858 0.3937 0.4016

E3 - 8.000 - - 0.3150 -

e - 0.800 - - 0.0315 -

L 0.450 0.600 0.750 0.0177 0.0236 0.0295

L1 - 1.000 - - 0.0394 -

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Package characteristics STM8S 207xx STM8S208xx

104/117 DocID14733 Rev 13

Figure 54. LQFP44 - 44-pin, 10 x 10 mm low-profile quad flat recommended footprint

1. Dimensions are expressed in millimeters.

Device marking

The following figure shows the markin g for the LQFP44 pa ckage.

Figure 55. LQFP44 marking example (package top view)

1. Parts marked as “ES”,”E” or accompanied by an Engineering Sample notification letter, are not yet

qualified and therefore not yet ready to be used in production and any consequences deriving from such

usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering

samples in production. ST Quality has to be contacted prior to any decision to use these Engineering

samples to run qualification activity.

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STM8S207xx STM8S208xx Package characteristics

116

11.1.5 LQF P32 package information

Figure 56. LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package outline

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106/117 DocID14733 Rev 13

Figure 57. LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat recommended footprint

1. Dimensions are expressed in millimeters.

Table 56. LQFP32 - 32-pin, 7 x 7 mm low- profile quad flat package mecha nical

data

Symbol mm inches(1)

1. Values in inches are converted from mm and rounded to four decimal places.

Min Typ Max Min Typ Max

A - - 1.600 - - 0.0630

A1 0.050 - 0.150 0.0020 - 0.0059

A2 1.350 1.400 1.450 0.0531 0.0551 0.0571

b 0.300 0.370 0.450 0.0118 0.0146 0.0177

c 0.090 - 0.200 0.0035 - 0.0079

D 8.800 9.000 9.200 0.3465 0.3543 0.3622

D1 6.800 7.000 7.200 0.2677 0.2756 0.2835

D3 - 5.600 - - 0.2205 -

E 8.800 9.000 9.200 0.3465 0.3543 0.3622

E1 6.800 7.000 7.200 0.2677 0.2756 0.2835

E3 - 5.600 - - 0.2205 -

e - 0.800 - - 0.0315 -

L 0.450 0.600 0.750 0.0177 0.0236 0.0295

L1 - 1.000 - - 0.0394 -

k 0°3.5°7° 0°3.5°7°

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DocID14733 Rev 13 107/117

STM8S207xx STM8S208xx Package characteristics

116

Device marking

The following figure shows the markin g for the LQFP32 pa ckage.

Figure 58. LQFP32 marking example (package top view)

1. Parts marked as “ES”,”E” or accompanied by an Engineering Sample notification letter, are not yet

qualified and therefore not yet ready to be used in production and any consequences deriving from such

usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering

samples in production. ST Quality has to be contacted prior to any decision to use these Engineering

samples to run qualification activity.

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108/117 DocID14733 Rev 13

11.2 Thermal characteristics

The maximum chip junction temperature (TJmax) must never exceed the values given in

Table 18: General operating conditions on page 56.

The maximum chip-jun ction temperature, TJmax, in degrees Celsius, may be calculated

using the following equation:

TJmax = TAmax + (PDmax x JA)

Where:

TAmax is the maximum ambient temperature in C



JA is the package junction-to-ambient thermal resistance in C/W

PDmax is the sum of PINTmax and PI/Omax (PDmax = PINTmax + PI/Omax)

PINTmax is the product of IDD and VDD, expressed in Watts. This is the maximum chip

internal power.

PI/Omax represents the maximum power dissipation on output pin s , wher e: 

PI/Omax = (VOL*IOL) + ((VDD-VOH)*IOH), and ta king account of the actual V OL/IOL and

VOH/IOH of the I/Os at low and high level in the application.

11.2.1 Reference document

JESD51-2 integrated circuits thermal test method environment conditions - natural

convection (still air). Available from www.jedec.org.

Table 57. Thermal characteristics(1)

1. Thermal resistances are based on JEDEC JESD51-2 with 4-layer PCB in a natural convection

environment.

Symbol Parameter Value Unit

JA Thermal resistance junction-ambient

LQFP 80 - 14 x 14 mm 38 °C/W

JA Thermal resistance junction-ambient

LQFP 64 - 14 x 14 mm 45 °C/W

JA Thermal resistance junction-ambient

LQFP 64 - 10 x 10 mm 46 °C/W

JA Thermal resistance junction-ambient

LQFP 48 - 7 x 7 mm 57 °C/W

JA Thermal resistance junction-ambient

LQFP 44 - 10 x 10 mm 54 °C/W

JA Thermal resistance junction-ambient

LQFP 32 - 7 x 7 mm 60 °C/W

DocID14733 Rev 13 109/117

STM8S207xx STM8S208xx Package characteristics

116

11.2.2 Selecting the product temperature range

When ordering the microcontr oller , the te mperature range is specified in the orde r code (see

Figure 59: STM8S207xx/208xx performance line ordering information scheme(1) on

page 112).

The following example shows how to calculate the temperature range needed for a given

application.

Assuming the following application conditions:

Maximum ambient temperature TAmax= 82 °C (measured according to JESD51-2)

IDDmax = 15 mA, VDD = 5.5 V

Maximum eight stan dard I/Os used at the same time in o utput at low level with IOL = 10

mA, VOL= 2 V

Maximum four high sink I/Os used at the same time in output at low level with IOL = 20

mA, VOL= 1.5 V

Maximum two true open drain I/Os used at the same time in output at low level with 

IOL = 20 mA, VOL= 2 V

PINTmax = 15 mA x 5.5 V = 82.5 mW

PIOmax = (10 mA x 2 V x 8) + (20 mA x 2 V x 2) + (20 mA x 1.5 V x 4) = 360 mW

This gives: PINTmax = 82.5 mW and PIOmax 360 mW:

PDmax = 82.5 mW + 360 mW

Thus: PDmax = 443 mW

Using the values obtained in Table 57: Thermal characteristics on page 108 TJmax is

calculated as follows for LQFP64 10 x 10 mm = 46 °C/W:

TJmax = 82 °C + (46 °C/W x 443 mW) = 82 °C + 20 °C = 102 °C

This is within the range of the suffix 6 version parts (-40 < TJ < 105 °C).

In this case, parts must be ordered at least with the temperature range suffix 6.

STM8 development tools STM8S207xx STM8S208xx

110/117 DocID14733 Rev 13

12 STM8 development tools

Development tools for the STM8 microcontrollers include the full-featured STice emulation

system supported by a comple te software tool package including C compiler, assembler and

integrated developmen t environment with high-level language debugger. In addition, the

STM8 is to be supported by a complete range of tools including starter kits, evaluation

boards and a low-cost in-circuit debugger/programmer.

12.1 Emulation and in-circuit debugging tools

The STice emulation system offers a complete range of emulation and in-circuit debugging

features on a platform that is designed for versatility and cost-effectiveness. In addition,

STM8 application development is su pported by a low-cost in-circuit debugger/programmer.

The STice is the fourth generation of full featured emulators from STMicroelectronics. It

offers new advanced debugging capabilities including profiling and coverage to help detect

and eliminate bottlenecks in applicatio n execution and dead code when fine tuning an

application.

In addition, STice offers in-circuit debugging and programming of STM8 microcontro llers via

the STM8 single wire interface module (SWIM), which allows non-intrusive debugging of an

application while it runs on the target microcontroller.

For improved cost effectiveness, STice is based on a modular design that allows you to

order exactly what you need to meet the de velopment requirements and to adapt the

emulation system to support existing and future ST microcontrollers.

STice key features

Occurrence and time profiling and code coverage (new features)

Advanced breakpoints with up to 4 levels of conditions

Data breakpoint s

Program and data trace recording up to 128 KB records

Read/write on the fly of memor y during emulation

In-circuit debugging/programming via SWIM protocol

8-bit probe analyzer

1 input and 2 output triggers

Power supply follower managing application voltages between 1.62 to 5.5 V

Modularity that allows you to specify the components you need to meet the

development requirements and adapt to future requirements

Supported by free software tools that include integrated development environment

(IDE), programming software interface and asse mbler for STM8.

DocID14733 Rev 13 111/117

STM8S207xx STM8S208xx STM8 development tools

116

12.2 Software tools

STM8 development tools are supported by a complete, free sof tware package from

STMicroelectronics that includes ST Visual Develop (STVD) IDE and the ST Visual

Programmer (STVP) sof tware interf ace. STVD provides seamless inte gration of th e Cosmic

and Raisonance C compilers for STM8. A free version that outputs up to 32 Kbytes of code

is available.

12.2.1 STM8 toolset

STM8 toolset with STVD integrated development environment and STVP programming

software is available for free download at www.st.com/mcu. This package includes:

ST Visual Develop – Full-featured integrated development environment from ST, featuring

Seamless integratio n of C and ASM tool sets

Full-featured debugger

Project management

Syntax highlighting editor

Integrated programming interface

Support of advanced emulation features for STice such as code profiling and coverage

ST Visual Programmer (STVP) – Easy-to-use, unlimited graphical interface allowing read,

write and verification of the ST M8 microcontroller Flash program memory, data EEPROM

and option bytes. ST VP also offers project mode for saving programming configu rations and

automating programming sequences.

12.2.2 C and assembly toolchains

Control of C and assembly toolchains is seamles sly integrated into th e STVD inte gr at ed

development environment, making it possible to configure and control the building of the

application directly from an easy-to-use graphical interface.

Available toolchains include:

Cosmic C compiler for STM8 – One free version that output s up to 32 Kbytes of code

is available. For more information, see www.cosmic-software.com.

Raisonance C compiler for STM8 – One free version that outputs up to 32 Kbytes of

code. For more information, see www.raisonance.com.

STM8 assembler linker – Free assembly toolchain included in the STVD toolset,

which allows you to assemble and link the application source code.

12.3 Programming tools

During the development cycle, STice provides in-circuit programming of the STM8 Flash

microcontroller on the app lication board via the SWIM protocol. Additional tools are to

include a low-cost in-circuit programmer as well as ST socket boards, which pr ovide

dedicated programm ing platforms with sockets for programming the STM8.

For production environments, programmers will include a complete range of gang and

automated programming solutions from third-party tool developers already supplying

programmers for the STM8 family.

Ordering information STM8S207xx STM8S208xx

112/117 DocID14733 Rev 13

13 Ordering information

Figure 59. STM8S207xx/208xx performance line ordering information scheme (1)

1. For a list of available options (e.g. memory size, package) and order-able part numbers or for further

information on any aspect of this device, please go to www.st.com or contact the ST Sales Office nearest

to you.

2. Refer to Table 2: STM8S20xxx performance line features for detailed description.

STM8 S 208 M B T 6 B TR

Product class

STM8 microcontroller

Pin count

K = 32 pins

S = 44 pins

C = 48 pins

R = 64 pins

M = 80 pins

Package type

T = LQFP

Example:

Sub-family type(2)

208 = Full peripheral set

207 = Intermediate peripheral set

Family type

S = Standard

Temperature range

3 = -40 °C to 125 °C

6 = -40 °C to 85 °C

Program memory size

6 = 32 Kbyte

8 = 64 Kbyte

B = 128 Kbyte

Package pitch

No character = 0.5 mm

B = 0.65 mm

C = 0.8 mm

Packing

No character = Tray or tube

TR = Tape and re el

DocID14733 Rev 13 113/117
STM8S207xx STM8S208xx Revision history
116
14 Revision history
           Table 58. Document revision history 
Date Revision Changes
23-May-2008 1 Initial release.
05-Jun-2008 2 Added part numbers on page 1 and in Table 2 on page 11.
Updated Section 4: Product overview.
Updated Section 10: Electrical characte ristics.
22-Jun-2008 3 Added part numbers on page 1 and in Table 2 on page 11.
12-Aug-2008 4
Added 32 pin device pinout and ordering  information.
Updated UBC option description in Table 13 on page 48.
USART renamed UART1, LINUART renamed UART3.
Max. ADC frequency increased to 6 MHz.
20-Oct-2008 5
Removed STM8S207K4 part number. 
Removed LQFP64 14 x 14 mm package.
Added medium and high density Flash memo ry categories.
Added Section 6: Memory and register map on page 34.
Replaced beCAN3 by beCAN in Section 4.14.5: beCAN.
Updated Section 10: Electrical characteristics on page 52.
Updated LQFP44 (Figure 53 and Table 55), and LQFP32 outline and 
mechanical data (Figure 56, and Table 56).
08-Dec-2008 6
Changed VDD minimum value from 3.0 to  2.95 V. 
Updated number of High Sink I/Os in pinout.
Removed FLASH _NFPR and FLASH _FPR registers in Table 9: 
General hardware register map.
30-Jan-2009 7
Removed prelimi nary status.
Removed VQFN 32 package. 
Added STM8S207C6, STM8S207S6.
Updated external interrupts in Table 2 on page 11.
Updated Section 10: Electrical characte ristics.
10-Jul-2009 8
Document status changed from “preliminary data” to “datasheet”. 
Added LQFP64 14 x 14 mm package.
Added STM8S207M8, STM8S207SB, STM8S208R8, STM8S208R6, 
STM8S208C8, and STM8S20 8C6, STM8S208SB, STM8S208S8, 
and STM8S208S6.
Replaced “CAN” with “beCAN”.
Added Table  3  to Section 4.5: Clock controller.
Updated Section 4.8: Auto wakeup counter.
Added beCAN peripheral (impacting Table 1 and Figure 6).
Added footnote about CAN_RX/T X to pinout figures 5, 4, and 6.
Table 6: Removed ‘X’ fro m wpu column of I 2C pins (no wpu  
available).
Added Table  11: Interrupt mapping.

Revision history STM8S207xx STM8S208xx
114/117 DocID14733 Rev 13
10-Jul-2009 8
cont’d
Section 10: Electrical characteristics: Adde d data for TBD values; 
updated Table 15: V oltage characteristics and Table 1 8 : General 
operating conditions; updated VCAP specifications  in Table 18 and 
in Section 10.3.1: VCAP external capacitor; updated Figure 18; 
replaced Figure 19; updated Table 35: RAM and hardware registers; 
updated Figure 22 and Figure 35; added Figure 40: Typical 
application with I2C bus and timing diagram.
Removed Table 56: Junction temperature range.
Added link between ordering information Figure 59 and STM8S20xx 
features Table 2.
13-Apr-2010 9
Document status changed from “pre liminary data” to “datasheet”.
Table 2: STM8S20xxx performance line features: high sink I/O for 
STM8S207C8 is 16 (not 13).
Table 3: Peripheral clock gating bit assignments in 
CLK_PCKENR1/2 registers: updated bit positions for TIM2 and 
TIM3.
Figure 5: LQFP 48-pin pinout: added CAN_TX and CAN_RX to pins 
35 and 36; noted that these pins are available onl y in STM8S208 xx 
devices.
Figure 7: LQFP 32-pin pinout: replaced uart2 with uart3.
Table 6: Pin description: added footnotes concerning be CAN 
availability and UART1_RX and UART3_RX pins.
Table 13: Option byte description: added descriptio n of STM8 L 
bootloader option bytes to the option byte description table.
Added Section 9: Unique ID (and listed this attribute in Features).
Section 10.3: Operating conditions: added introductory text.
Table 18: General operating conditions: replaced “CEXT” with “VCA P” 
and added data for ESR and ESL; removed “low power dissipation” 
condition for TA.
Table 26: Total current consumpti on in halt mode at VDD = 5 V: 
replaced max value of IDD(H) at 85 °C from 30 µA to 35 µA for the 
condition “Flash in power-down mode, HSI clock after wakeup”.
Table 33: HSI oscillator characteristics: updated the ACCHSI factory 
calibrated values.
Functional EMS (electromagnetic susceptibility) and Table 47: 
replaced “IEC 1000” with “IEC 61000”.
Electromagnetic interference (EMI) and Table 48: replaced “SAE 
J1752/3” with “IEC 61967-2”.
Table 57: Thermal characteristics: changed the thermal resistance 
junction-ambient value of LQFP32 (7x7 mm) from 59 °C/W to 60 
°C/W.
Table 58. Document revision history (continued)
Date Revision Changes

DocID14733 Rev 13 115/117

STM8S207xx STM8S208xx Revision history

116

14-Sep-2010 10

Added part number STM8S208M8 to Table 1: Device summary.

Updated “reset state” of Table 5: Legend/abbreviations for pinout

table.

Added footnote 4 to Table 6: Pin description.

Table 9: General hardware register map: standardized all reset state

values; updated the reset state values of RST_SR, CLK_SWCR,

CLK_HSITRIMR, CLK_SWIMC CR, IWDG_KR, and ADC_DRx

registers; added the reset values of the CAN paged registers.

Figure 36: Recommended reset pin protection: replaced 0.01 µF with

0.1 µF.

Figure 40: Typical applica tion with I2C bus and timing diagram:

tw(SCKH), tw(SCKL), tr(SCK), and tf(SCK) replaced by tw(SCLH), tw(SCLL),

tr(SCL), and tf(SCL) respectively.

22-Mar-2011 11

Table 1: Device summary: added STM8S207K8.

Table 2: STM8S20xxx performance line features: added

STM8S207K8 device and changed the RAM value of all other

devices to 6 Kbytes.

Figure 5, Figure 4, Figure 5, and Figure 7: removed TIM1_CH4 from

pins 80, 64, 48, and 32 respectively.

Table 6: Pin description: updated note 3 and added note 5.

Table 9: General hardware register map: removed I2C_PECR

Section 10.3.7: Reset pin characteristics: add ed text regarding the

rest network.

10-Feb-2012 12

Figure 1: STM8S20xxx block diagram: updated POR/PDR and BOR;

updated LINUART input; added legend.

Table 18: General operati ng conditions: updated VCAP.

Table 26: Total current consumption in halt mode at VDD = 5 V:

updated title, modified existing max column, and added new max

column (at 125 °C) with data.

Table 37: I/O static characteristics: added new condition and new

max values for rise and fall time; added footnote 3; updated T yp and

max pull-up resistor values.

Section 10.3.7: Reset pin characteristics: updated cross reference in

text below Figure 35

Table 41: NRST pin charac teristics: updated Typ and max values of

the NRST pull-up resistor.

Table 58. Document revision history (continued)

Date Revision Changes

Revision history STM8S207xx STM8S208xx
116/117 DocID14733 Rev 13
18-Feb-2015 13
Updated:
–Figure 43: LQFP80 - 80-pin, 14 x 14 mm low-profile quad flat 
package outline
–Table 51: LQFP80 - 80-pin, 14 x 14 mm low-profile quad flat 
package mechanical   data
–Figure 51: LQFP80 - 80-pin, 14 x 14 mm low-profile quad flat 
package mechanical   data
–Figure 47: LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat 
package outline
–Table 53: LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat 
package mechanical   data
–Figure 50: LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat 
package outline
–Table 54: LQFP48 - 48-pin, 7x 7 mm low-profile quad flat package 
mechanical
–Figure 56: LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat 
package outline
–Table 56: LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package 
mechanical   data
Added:
–Figure 44: LQFP80 recommended footprint
–Figure 45: LQFP80 marking example (package top view)
–Figure 48: LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat 
recommended footprint
–Figure 49: LQFP64 marking example (package top view)
–Figure 51: LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat 
recommended footprint
–Figure 52: LQFP48 marking example (package top view)
–Figure 54: LQFP44 - 44-pin, 10 x 10 mm low-profile quad flat 
recommended footprint
–Figure 55: LQFP44 marking example (package top view)
–Figure 57: LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat 
recommended footprint
–Figure 58: LQFP32 marking example (package top view)
Table 58. Document revision history (continued)
Date Revision Changes

DocID14733 Rev 13 117/117

STM8S207xx STM8S208xx

117

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