CY74FCT163H952C - Texas Instruments

16-Bit Registered Transceivers

CY74FCT163952

CY74FCT163H952

SCCS048A - March 1997 - Revised November 2000

Data sheet acquired from Cypress Semiconductor Corporation.

Data sheet modiﬁed to remove devices not offered.

1CY74FCT163952

Features

• Low power, pin-compatible replacement for LCX and

LPT families

• 5V tolerant inputs and outputs

• 24 mA balanced drive outputs

• Power-off disable outputs permit live insertion

• Edge-rate control circuitry for reduced noise

• FCT-C speed at 4.4 ns

• Latch-up performance exceeds JEDEC standard no. 17

• Typical output skew < 250 ps

• Industrial temperature range of –40˚C to +85˚C

• TSSOP (19.6-mil pitch) or SSOP (25-mil pitch)

• TypicalVolp(groundbounce)performanceexceedsMil

Std 883D

•V

CC = 2.7V to 3.6V

• ESD (HBM) > 2000V

CY74FCT163H952

• Bus hold on data inputs

• Eliminates the need for external pull-up or pull-down

resistors

• Devices with bus hold are not recommended for trans-

lating rail-to-rail CMOS signals to 3.3V logic levels

Functional Description

These 16-bit registered transceivers are high-speed,

low-power devices. 16-bit operation is achieved by connecting

the control lines of the two 8-bit registered transceivers

together. For data ﬂow from bus A-to-B, CEAB must be LOW

to allow data to be stored when CLKAB transitions from

LOW-to-HIGH. The stored data will be present on the output

when OEAB is LOW. Control of data from B-to-A is similar and

is controlled by using the CEBA, CLKBA, and OEBA inputs.

The outputs are 24-mA balanced output drivers with current

limiting resistors to reduce the need for external terminating

resistors and provide for minimal undershoot and reduced

ground bounce.

The CY74FCT163H952 has “bus hold” on the data inputs,

whichretainstheinput’s last state whenever the source driving

the input goes to high impedance. This eliminates the need for

pull-up/down resistors and prevents ﬂoating inputs.

The CY74FCT163952 is designed with inputs and outputs

capable of being driven by 5.0V buses, allowing its use in

mixed voltage systems as a translator. The outputs are also

designed with a power off disable feature enabling its use in

applications requiring live insertion.

Logic Block Diagrams; CY74FCT163952, CY74FCT163H952 Pin Configuration

1OEAB

SSOP/TSSOP

Top View

1CLKBA

1B1

1B2

GND

VCC

GND

1B1

TO 7 OTHER CHANNELS

1CEBA

1OEAB

1CEAB

1CLKAB

1OEBA

1A1

1CEAB

1CLKAB

GND

1A1

1A2

1A3

1A4

GND

2A1

2A2

2A3

2A4

VCC

1A5

1A6

1A7

1A8

GND

2A5

2A6

2A7

2A8

2CLKAB

GND

2OEAB

2CEAB

VCC

1OEBA

1CEBA

1CLKBA

GND

2CLKBA

2OEBA

2CEBA

1B3

1B6

1B7

1B8

1B4

1B5

2B1

2B3

2B4

2B2

2B5

2B6

2B7

2B8

VCC

2CLKBA

2B1

2OEAB

2CEAB

2CLKAB

2OEBA

2A1

2CEBA

TO 7 OTHER CHANNELS

CY74FCT163952

CY74FCT163H952

Maximum Ratings[5, 6]

(Above which the useful life may be impaired. For user guide-

lines, not tested.)

Storage Temperature ..................................–55°C to +125°C

Ambient Temperature with

Power Applied .............................................–55°C to +125°C

Supply Voltage Range......................................0.5V to +4.6V

DC Input Voltage............................................–0.5V to +7.0V

DC Output Voltage .........................................–0.5V to +7.0V

DC Output Current

(Maximum Sink Current/Pin)........................ –60 to +120 mA

Power Dissipation.......................................................... 1.0W

Pin Description

Name Description

OEAB A-to-B Output Enable Input (Active LOW)

OEBA B-to-A Output Enable Input (Active LOW)

CEAB A-to-B Clock Enable Input (Active LOW)

CEBA B-to-A Clock Enable Input (Active LOW)

CLKAB A-to-B Clock Input

CLKBA B-to-A Clock Input

A A-to-B Data Inputs or B-to-A Three-State

Outputs[1]

B B-to-A Data Inputs or A-to-B Three-State

Outputs[1]

Function Table[2, 3]

For A-to-B (Symmetric with B-to-A)

Inputs Outputs

CEAB CLKAB OEAB A B

H X L X B[4]

X L L X B[4]

L L L L

L L H H

X X H X Z

Operating Range

Range Ambient

Temperature VCC

Industrial –40°C to +85°C 2.7V to 3.6V

Electrical Characteristics for Non Bus Hold Devices Over the Operating Range VCC=2.7V to 3.6V

Parameter Description Test Conditions Min. Typ.[7] Max. Unit

VIH Input HIGH Voltage All Inputs 2.0 5.5 V

VIL Input LOW Voltage 0.8 V

VHInput Hysteresis[8] 100 mV

VIK Input Clamp Diode Voltage VCC=Min., IIN=–18 mA –0.7 –1.2 V

IIH Input HIGH Current VCC=Max., VI=5.5 ±1µA

IIL Input LOW Current VCC=Max., VI=GND ±1µA

IOZH High Impedance Output Current

(Three-State Output pins) VCC=Max., VOUT=5.5V ±1µA

IOZL High Impedance Output Current

(Three-State Output pins) VCC=Max., VOUT=GND ±1µA

IOS Short Circuit Current[9] VCC=Max., VOUT=GND –60 –135 –240 mA

IOFF Power-Off Disable VCC=0V, VOUT≤4.5V ±100 µA

ICC Quiescent Power Supply Current VIN≤0.2V,

VIN>VCC–0.2V VCC=Max. 0.1 10 µA

∆ICC Quiescent Power Supply Current

(TTL inputs HIGH) VIN=VCC–0.6V[10] VCC=Max. 2.0 30 µA

Notes:

1. On the CY74FCT163H952, these pins have bus hold.

2. A-to-B data ﬂow is shown: B-to-A data ﬂow is similar but uses, CEBA, CLKBA, and OEBA.

3. H = HIGH Voltage Level. L = LOW Voltage Level. X = Don’t Care. = LOW-to-HIGH Transition. Z = HIGH Impedance.

4. Level of B before the indicated steady-state input conditions were established.

5. Operation beyond the limits set forth may impair the useful life of the device. Unless otherwise noted, these limits are over the operating free-air temperature.

6. With the exception of inputs with bus hold, unused inputs must always be connected to an appropriate logic voltage level, preferably either VCC or ground,

7. Typical values are at VCC=3.3V, TA = +25˚C ambient.

8. This parameter is speciﬁed but not tested.

9. Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample

and hold techniques are preferable in order to minimize internal chip heating and more accurately reﬂect operational values. Otherwise prolonged shorting of

a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests. In any sequence of parameter

tests, IOS tests should be performed last.

10. Per TTL driven input; all other inputs at VCC or GND.

CY74FCT163952

CY74FCT163H952

Electrical Characteristics For Bus Hold Devices Over the Operating Range VCC=2.7V to 3.6V

Parameter Description Test Conditions Min. Typ.[7] Max. Unit

VIH Input HIGH Voltage All Inputs 2.0 VCC V

VIL Input LOW Voltage 0.8 V

VHInput Hysteresis[8] 100 mV

VIK Input Clamp Diode Voltage VCC=Min., IIN=–18 mA –0.7 – 1.2 V

IIH Input HIGH Current VCC=Max., VI=VCC ±100 µA

IIL Input LOW Current ±100 µA

IBBH

IBBL Bus Hold Sustain Current on Bus Hold Input[11] VCC=Min. VI=2.0V –50 µA

VI=0.8V +50 µA

IBHHO

IBHLO Bus Hold Overdrive Current on Bus Hold Input[11] VCC=Max., VI=1.5V ±500 µA

IOZH High Impedance Output Current

(Three-State Output pins) VCC=Max., VOUT=VCC ±1µA

IOZL High Impedance Output Current

(Three-State Output pins) VCC=Max., VOUT=GND ±1µA

IOS Short Circuit Current[9] VCC=Max., VOUT=GND –60 –135 –240 mA

IOFF Power-Off Disable VCC=0V, VOUT≤4.5V ±100 µA

ICC Quiescent Power Supply Current VIN≤0.2V VCC

VIN>VCC–0.2V VCC=Max. +40 µA

∆ICC Quiescent Power supply Current

(TTL inputs HIGH) VIN=VCC–0.6V[10] VCC=Max. +350 µA

Electrical Characteristics For Balanced Drive Devices Over the Operating Range VCC=2.7V to 3.6V

Parameter Description Test Conditions Min. Typ.[7] Max. Unit

IODL Output LOW Dynamic Current[9] VCC=3.3V, VIN=VIH

or VIL, VOUT=1.5V 50 90 200 mA

IODH Output HIGH Dynamic Current[9] VCC=3.3V, VIN=VIH

or VIL, VOUT=1.5V –36 –60 –110 mA

VOH Output HIGH Voltage VCC=Min., IOH= –0.1 mA VCC–0.2 V

VCC=Min., IOH= –8 mA 2.4[12] 3.0 V

VCC=3.0V, IOH= –24 mA 2.0 3.0 V

VOL Output LOW Voltage VCC=Min., IOL= 0.1mA 0.2 V

VCC=Min., IOL= 24 mA 0.3 0.55

Notes:

11. Pins with bus hold are described in Pin Description.

12. VOH=VCC–0.6 V at rated current

Capacitance[8](TA = +25˚C, f = 1.0 MHz)

Parameter Description Test Conditions Typ.[7] Max. Unit

CIN Input Capacitance VIN = 0V 4.5 6.0 pF

COUT Output Capacitance VOUT = 0V 5.5 8.0 pF

CY74FCT163952

CY74FCT163H952

Power Supply Characteristics

Parameter Description Test Conditions Typ.[7] Max. Unit

ICCD Dynamic Power Supply

Current[13] VCC=Max., One Input Toggling,

50% Duty Cycle,

Outputs Open, OE=GND

VIN=VCC or

VIN=GND 50 75 µA/MHz

ICTotal Power Supply

Current[14] VCC=Max., f1=10 MHz, 50%

DutyCycle,Outputs Open, One

Bit Toggling, OE=GND

VIN=VCC or

VIN=GND 0.5 0.8 mA

VIN=VCC–0.6V or

VIN=GND 0.5 0.8 mA

VCC=Max., f1=2.5 MHz, 50%

Duty Cycle, Outputs Open, Six-

teen Bits Toggling, OE=GND

VIN=VCC or

VIN=GND 2.0 3.0[15] mA

VIN=VCC–0.6V or

VIN=GND 2.0 3.3[15] mA

Switching Characteristics Over the Operating Range VCC=3.0V to 3.6V[16,17]

Parameter Description CY74FCT163952A CY74FCT163952C

CY74FCT163H952C

Min. Max. Min. Max. Unit Fig. No.[18]

tPLH

tPHL Propagation Delay Data to Output 1.5 4.8 1.5 4.4 ns 1, 3

tPZH

tPZL Output Enable Time 1.5 6.2 1.5 5.8 ns 1, 7, 8

tPHZ

tPLZ Output Disable Time 1.5 5.6 1.5 5.2 ns 1, 7, 8

tSU Set-Up Time, HIGH or LOW

A, B to CLKAB, CLKBA 2.5 — 2.5 — ns 4

tHHold Time, HIGH or LOW

A, B to CLKAB, CLKBA 2.0 — 1.5 — ns 4

tSU Set-Up Time, HIGH or LOW

CEAB, CEBA to CLKAB, CLKBA 3.0 — 3.0 — ns 4

tHHold Time, HIGH or LOW

CEAB, CEBA to CLKAB, CLKBA 2.0 — 2.0 — ns 4

tWPulse Width, HIGH or LOW

CLKAB or CLKBA[19] 3.0 — 3.0 — ns 5

tSK(O) Output Skew[19] 0.5 0.5 ns —

Notes:

13. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.

14. IC=I

QUIESCENT + IINPUTS + IDYNAMIC

IC=I

CC+∆ICCDHNT+ICCD(f0/2 + f1N1)

ICC = Quiescent Current with CMOS input levels

∆ICC = Power Supply Current for a TTL HIGH input (VIN=3.4V)

DH= Duty Cycle for TTL inputs HIGH

NT= Number of TTL inputs at DH

ICCD = Dynamic Current caused by an input transition pair (HLH or LHL)

f0= Clock frequency for registered devices, otherwise zero

f1= Input signal frequency

N1= Number of inputs changing at f1

All currents are in milliamps and all frequencies are in megahertz.

15. Values for these conditions are examples of the ICC formula. These limits are speciﬁed but not tested.

16. Minimum limits are speciﬁed but not tested on Propagation Delays.

17. For VCC =2.7, propagation delay, output enable and output disable times should be degraded by 20%.

18. See “Parameter Measurement Information” in the General Information section.

19. Skew between any two outputs of the same package switching in the same direction. This parameter is ensured by design.

CY74FCT163952

CY74FCT163H952

Ordering Information CY74FCT163952

Speed

(ns) Ordering Code Package

Name Package Type Operating

Range

4.1 CY74FCT163952CPACT Z48 48-Lead (240-Mil) TSSOP Industrial

CY74FCT163952CPVC/PVCT O48 48-Lead (300-Mil) SSOP

4.8 CY74FCT163952APVC/PVCT O48 48-Lead (300-Mil) SSOP Industrial

Ordering Information CY74FCT163H952

Speed

(ns) Ordering Code Package

Name Package Type Operating

Range

4.1 74FCT163H952CPACT Z48 48-Lead (240-Mil) TSSOP Industrial

CY74FCT163H952CPVC O48 48-Lead (300-Mil) SSOP

74FCT163H952CPVCT O48 48-Lead (300-Mil) SSOP

Package Diagrams

56-Lead Shrunk Small Outline Package O56

CY74FCT163952

CY74FCT163H952

Package Diagrams

56-Lead Thin Shrunk Small Outline Package Z56

PACKAGING INFORMATION

Orderable Device Status (1) Package

Type Package

Drawing Pins Package

Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)

74FCT163H952CPACT OBSOLETE TSSOP DGG 56 TBD Call TI Call TI

74FCT163H952CPVCT OBSOLETE SSOP DL 56 TBD Call TI Call TI

CY74FCT163952CPAC OBSOLETE TSSOP DGG 56 TBD Call TI Call TI

CY74FCT163952CPACT OBSOLETE TSSOP DGG 56 TBD Call TI Call TI

CY74FCT163952CPVC OBSOLETE SSOP DL 56 TBD Call TI Call TI

CY74FCT163952CPVCT OBSOLETE SSOP DL 56 TBD Call TI Call TI

CY74FCT163H952CPAC OBSOLETE TSSOP DGG 56 TBD Call TI Call TI

CY74FCT163H952CPVC OBSOLETE SSOP DL 56 TBD Call TI Call TI

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

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PACKAGE OPTION ADDENDUM

www.ti.com 30-Mar-2005

Addendum-Page 1

MECHANICAL DATA

MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

DL (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

4040048/E 12/01

48 PINS SHOWN

0.730

(18,54)

0.720

(18,29)

4828

0.370

(9,40)

(9,65)

0.380

Gage Plane

DIM

0.420 (10,67)

0.395 (10,03)

A MIN

A MAX

0.010 (0,25)

PINS **

0.630

(16,00)

(15,75)

0.620

0.010 (0,25)

Seating Plane

0.020 (0,51)

0.040 (1,02)

0.008 (0,203)

0.0135 (0,343)

0.008 (0,20) MIN

0.110 (2,79) MAX

0.299 (7,59)

0.291 (7,39)

0.004 (0,10)

0.005 (0,13)

0.025 (0,635)

0°–ā8°

0.005 (0,13)

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).

D. Falls within JEDEC MO-118

MECHANICAL DATA

MTSS003D – JANUARY 1995 – REVISED JANUAR Y 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

4040078/F 12/97

48 PINS SHOWN

0,25

0,15 NOM

Gage Plane

6,00

6,20 8,30

7,90

0,75

0,50

Seating Plane

0,27

0,17

1,20 MAX

0,08

0,10

0,50

0°–8°

14,10

13,90

DIM

A MAX

A MIN

PINS **

12,40

12,60

17,10

16,90

0,15

0,05

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold protrusion not to exceed 0,15.

D. Falls within JEDEC MO-153

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