2010 Microchip Technology Inc. DS39770C
PIC18F85J90 Family
Data Sheet
64/80-Pin, High-Performance
Microcontrollers with LCD Driver
and nanoWatt Technology
DS39770C-page 2 2010 Microchip Technology Inc.
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Note the following details of the code protection feature on Microchip devices:
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intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
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Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
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2010 Microchip Technology Inc. DS39770C-page 3
PIC18F85J90 FAMILY
Low-Power Features:
• Power-Managed modes: Run, Idle, Sleep
• Run current down to 7 µA, typical
• Idle current down to 2.5 µA, typical
• Sleep current down to 100 nA, typical
• Fast INTOSC start-up from Sleep, 1 µs typical
• Two-Speed Oscillator Start-up reduces crystal
stabilization wait time
LCD Driver Module Features:
• Direct LCD Panel Drive Capability:
- Can drive LCD panel while in Sleep mode
• Up to 48 Segments and 192 Pixels; Software
Selectable
• Programmable LCD Timing module:
- Multiple LCD timing sources available
- Up to 4 commons: static, 1/2, 1/3 or 1/4 multiplex
- Static, 1/2 or 1/3 Bias configuration
• Integrated Charge Pump Module with Voltage
Boost
Special Microcontroller Features:
• 1000 Erase/Write Cycle Flash Program Memory,
Typical
• Flash Retention: 20 Years Minimum
• Self-Programmable under Software Control
• Priority Levels for Interrupts
• 8 x 8 Single-Cycle Hardware Multiplier
• Extended Watchdog Timer (WDT):
- Programmable period from 4 ms to 131s
• In-Circuit Serial Programming™ (ICSP™) via
Two Pins
• In-Circuit Debug with 3 Breakpoints via Two Pins
• Operating Voltage Range: 2.0V to 3.6V
• On-Chip 2.5V Regulator
Flexible Oscillator Structure:
• Two Crystal modes, 4-25 MHz
• Two External Clock modes, up to 40 MHz
• Internal Oscillator Block:
- 8 user-selectable frequencies from 31.25 kHz
to 8 MHz
• Secondary Oscillator using Timer1 @ 32 kHz
• Fail-Safe Clock Monitor:
- Allows for safe shutdown if peripheral clock fails
Peripheral Highlights:
• High-Current Sink/Source: 25 mA/25 mA
(PORTB and PORTC)
• Sleep Current as Low as 100 nA
• Up to Four External Interrupts
• Four 8-Bit/16-Bit Timer/Counter modules:
- Uses Timer1
• Two Capture/Compare/PWM (CCP) modules:
- Capture is 16-bit, max. resolution 6.25 ns (TCY/16)
- Compare is 16-bit, max. resolution 100 ns (TCY)
- PWM output: PWM resolution is up to 10-bit
• Master Synchronous Serial Port (MSSP) module
with Two Modes of Operation:
- 3-wire/4-wire SPI (supports all 4 SPI modes)
-I
2C™ Master and Slave modes
• One Addressable USART module
• One Enhanced USART module:
- Supports LIN/J2602
- Auto-wake-up on Start bit and Break character
- Auto-Baud Detect
• 10-Bit, up to 12-Channel A/D Converter:
- Auto-acquisition
- Conversion available during Sleep
• Two Analog Comparators
• Programmable Reference Voltage for
Comparators
Device
Program Memory SRAM
Data
Memory
(bytes)
I/O LCD
(Pixels)
Timers
8/16-Bit
CCP
MSSP
EUSART/
AUSART
10-Bit
A/D
(ch)
Comparators
BOR/
LVD
Flash
(bytes)
# Single-Word
Instructions SPI Master
I2C™
PIC18F63J90 8K 4096 1024 51 132 1/3 2 Y Y 1/1 12 2 Y
PIC18F64J90 16K 8192 1024 51 132 1/3 2 Y Y 1/1 12 2 Y
PIC18F65J90 32K 16384 2048 51 132 1/3 2 Y Y 1/1 12 2 Y
PIC18F83J90 8K 4096 1024 67 192 1/3 2 Y Y 1/1 12 2 Y
PIC18F84J90 16K 8192 1024 67 192 1/3 2 Y Y 1/1 12 2 Y
PIC18F85J90 32K 16384 2048 67 192 1/3 2 Y Y 1/1 12 2 Y
64/80-Pin, High-Performance Microcontrollers with
LCD Driver and nanoWatt Technology
PIC18F85J90 FAMILY
DS39770C-page 4 2010 Microchip Technology Inc.
Pin Diagrams
64-Pin TQFP
PIC18F63J90
1
2
3
4
5
6
7
8
9
10
11
12
13
14
38
37
36
35
34
33
50 49
17 18 19 20 21 22 23 24 25 26
LCDBIAS3
RE3/COM0
RE4/COM1
RE5/COM2
RE6/COM3
RE7/CCP2(1)/SEG31
RD0/SEG0
VDD
VSS
RD1/SEG1
RD2/SEG2
RD3/SEG3
RD4/SEG4
RD5/SEG5
RD6/SEG6
RD7/SEG7
RE1/LCDBIAS2
RE0/LCDBIAS1
RG0/LCDBIAS0
RG1/TX2/CK2
RG2/RX2/DT2/VLCAP1
RG3/VLCAP2
MCLR
RG4/SEG26
VSS
VDDCORE/VCAP
RF7/AN5/SS/SEG25
RF6/AN11/SEG24
RF5/AN10/CVREF/SEG23
RF4/AN9/SEG22
RF3/AN8/SEG21
RF2/AN7/C1OUT/SEG20
RB0/INT0/SEG30
RB1/INT1/SEG8
RB2/INT2/SEG9
RB3/INT3/SEG10
RB4/KBI0/SEG11
RB5/KBI1/SEG29
RB6/KBI2/PGC
VSS
OSC2/CLKO/RA6
OSC1/CLKI/RA7
VDD
RB7/KBI3/PGD
RC4/SDI/SDA/SEG16
RC3/SCK/SCL/SEG17
RC2/CCP1/SEG13
ENVREG
RF1/AN6/C2OUT/SEG19
AVDD
AVSS
RA3/AN3/VREF+
RA2/AN2/VREF-
RA1/AN1/SEG18
RA0/AN0
VSS
VDD
RA4/T0CKI/SEG14
RA5/AN4/SEG15
RC1/T1OSI/CCP2(1)/SEG32
RC0/T1OSO/T13CKI
RC7/RX1/DT1/SEG28
RC6/TX1/CK1/SEG27
RC5/SDO/SEG12
15
16
31
40
39
27 28 29 30 32
48
47
46
45
44
43
42
41
54 53 52 5158 57 56 5560 59
64 63 62 61
Note 1: The CCP2 pin placement depends on the CCP2MX bit setting.
PIC18F64J90
PIC18F65J90
Pins are up to 5.5V tolerant
2010 Microchip Technology Inc. DS39770C-page 5
PIC18F85J90 FAMILY
Pin Diagrams (Continued)
80-Pin TQFP
PIC18F83J90
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
64 63 62 61
21 22 23 24 25 26 27 28 29 30 31 32
LCDBIAS3
RE3/COM0
RE4/COM1
RE5/COM2
RE6/COM3
RE7/CCP2(1)/SEG31
RD0/SEG0
VDD
VSS
RD1/SEG1
RD2/SEG2
RD3/SEG3
RD4/SEG4
RD5/SEG5
RD6/SEG6
RD7/SEG7
RE1/LCDBIAS2
RE0/LCDBIAS1
RG0/LCDBIAS0
RG1/TX2/CK2
RG2/RX2/DT2/VLCAP1
RG3/VLCAP2
MCLR
RG4/SEG26
VSS
VDDCORE/VCAP
VSS
OSC2/CLKO/RA6
OSC1/CLKI/RA7
VDD
ENVREG
RF1/AN6/C2OUT/SEG19
AVDD
AVSS
RA3/AN3/VREF+
RA2/AN2/VREF-
RA1/AN1/SEG18
RA0/AN0
VSS
VDD
RJ0
RJ1/SEG33
RH1/SEG46
RH0/SEG47
1
2
RH2/SEG45
RH3/SEG44
17
18
RH7/SEG43
RH6/SEG42
RH5/SEG41
RH4/SEG40
RJ5/SEG38
RJ4/SEG39
37
RJ7/SEG36
RJ6/SEG37
50
49
RJ2/SEG34
RJ3/SEG35
19
20
33 34 35 36 38
58
57
56
55
54
53
52
51
60
59
68 67 66 6572 71 70 6974 73
78 77 76 75
79
80
RB0/INT0/SEG30
RB1/INT1/SEG8
RB2/INT2/SEG9
RB3/INT3/SEG10
RB4/KBI0/SEG11
RB5/KBI1/SEG29
RB6/KBI2/PGC
RB7/KBI3/PGD
RC2/CCP1/SEG13
RC5/SDO/SEG12
RA4/T0CKI/SEG14
RA5/AN4/SEG15
RC1/T1OSI/CCP2(1)I/SEG32
RC0/T1OSO/T13CKI
RC7/RX1/DT1/SEG28
RC6/TX1/CK1/SEG27
RF7/AN5/SS/SEG25
RF6/AN11/SEG24
RF5/AN10/CVREF/SEG23
RF4/AN9/SEG22
RF3/AN8/SEG21
RF2/AN7/C1OUT/SEG20
RC4/SDI/SDA/SEG16
RC3/SCK/SCL/SEG17
Note 1: The CCP2 pin placement depends on the CCP2MX bit setting.
PIC18F84J90
PIC18F85J90
Pins are up to 5.5V tolerant
PIC18F85J90 FAMILY
DS39770C-page 6 2010 Microchip Technology Inc.
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 9
2.0 Guidelines for Getting Started with PIC18FJ Microcontrollers ................................................................................................... 31
3.0 Oscillator Configurations ............................................................................................................................................................ 35
4.0 Power-Managed Modes ............................................................................................................................................................. 43
5.0 Reset .......................................................................................................................................................................................... 51
6.0 Memory Organization ................................................................................................................................................................. 63
7.0 Flash Program Memory.............................................................................................................................................................. 87
8.0 8 x 8 Hardware Multiplier............................................................................................................................................................ 97
9.0 Interrupts .................................................................................................................................................................................... 99
10.0 I/O Ports ................................................................................................................................................................................... 115
11.0 Timer0 Module ......................................................................................................................................................................... 137
12.0 Timer1 Module ......................................................................................................................................................................... 141
13.0 Timer2 Module ......................................................................................................................................................................... 147
14.0 Timer3 Module ......................................................................................................................................................................... 149
15.0 Capture/Compare/PWM (CCP) Modules ................................................................................................................................. 153
16.0 Liquid Crystal Display (LCD) Driver Module............................................................................................................................. 163
17.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 191
18.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ............................................................... 235
19.0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (AUSART) ........................................................... 257
20.0 10-bit Analog-to-Digital Converter (A/D) Module ...................................................................................................................... 271
21.0 Comparator Module.................................................................................................................................................................. 281
22.0 Comparator Voltage Reference Module ................................................................................................................................... 287
23.0 Special Features of the CPU.................................................................................................................................................... 291
24.0 Instruction Set Summary .......................................................................................................................................................... 305
25.0 Development Support............................................................................................................................................................... 355
26.0 Electrical Characteristics .......................................................................................................................................................... 359
27.0 Packaging Information.............................................................................................................................................................. 393
Appendix A: Revision History............................................................................................................................................................. 399
Appendix B: Migration Between High-End Device Families............................................................................................................... 400
Index .................................................................................................................................................................................................. 403
The Microchip Web Site..................................................................................................................................................................... 413
Customer Change Notification Service .............................................................................................................................................. 413
Customer Support .............................................................................................................................................................................. 413
Reader Response .............................................................................................................................................................................. 414
Product Identification System............................................................................................................................................................. 415
2010 Microchip Technology Inc. DS39770C-page 7
PIC18F85J90 FAMILY
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To determine if an errata sheet exists for a particular device, please check with one of the following:
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PIC18F85J90 FAMILY
DS39770C-page 8 2010 Microchip Technology Inc.
NOTES:
2010 Microchip Technology Inc. DS39770C-page 9
PIC18F85J90 FAMILY
1.0 DEVICE OVERVIEW
This document contains device-specific information for
the following devices:
This family combines the traditional advantages of all
PIC18 microcontrollers – namely, high computational
performance and a rich feature set – with a versatile
on-chip LCD driver, while maintaining an extremely
competitive price point. These features make the
PIC18F85J90 family a logical choice for many
high-performance applications where price is a primary
consideration.
1.1 Core Features
1.1.1 nanoWatt TECHNOLOGY
All of the devices in the PIC18F85J90 family incorporate
a range of features that can significantly reduce power
consumption during operation. Key items include:
•Alternate Run Modes: By clocking the controller
from the Timer1 source or the internal RC
oscillator, power consumption during code
execution can be reduced by as much as 90%.
•Multiple Idle Modes: The controller can also run
with its CPU core disabled but the peripherals still
active. In these states, power consumption can be
reduced even further, to as little as 4% of normal
operation requirements.
•On-the-Fly Mode Switching: The power-managed
modes are invoked by user code during operation,
allowing the user to incorporate power-saving ideas
into their application’s software design.
1.1.2 OSCILLATOR OPTIONS AND
FEATURES
All of the devices in the PIC18F85J90 family offer six
different oscillator options, allowing users a range of
choices in developing application hardware. These
include:
• Two Crystal modes, using crystals or ceramic
resonators.
• Two External Clock modes, offering the option of
a divide-by-4 clock output.
• A Phase Lock Loop (PLL) frequency multiplier,
available to the External Oscillator modes which
allows clock speeds of up to 40 MHz.
• An internal oscillator block which provides an
8 MHz clock (±2% accuracy) and an INTRC source
(approximately 31 kHz, stable over temperature
and VDD), as well as a range of six user-selectable
clock frequencies, between 125 kHz to 4 MHz, for a
total of eight clock frequencies. This option frees the
two oscillator pins for use as additional general
purpose I/O.
The internal oscillator block provides a stable reference
source that gives the family additional features for
robust operation:
•Fail-Safe Clock Monitor: This option constantly
monitors the main clock source against a reference
signal provided by the internal oscillator. If a clock
failure occurs, the controller is switched to the
internal oscillator, allowing for continued low-speed
operation or a safe application shutdown.
•Two-Speed Start-up: This option allows the
internal oscillator to serve as the clock source
from Power-on Reset, or wake-up from Sleep
mode, until the primary clock source is available.
1.1.3 MEMORY OPTIONS
The PIC18F85J90 family provides a range of program
memory options, from 8 Kbytes to 32 Kbytes of code
space. The Flash cells for program memory are rated
to last up to 1000 erase/write cycles. Data retention
without refresh is conservatively estimated to be
greater than 20 years.
The PIC18F85J90 family also provides plenty of room
for dynamic application data, with up to 2048 bytes of
data RAM.
1.1.4 EXTENDED INSTRUCTION SET
The PIC18F85J90 family implements the optional
extension to the PIC18 instruction set, adding 8 new
instructions and an Indexed Addressing mode.
Enabled as a device configuration option, the extension
has been specifically designed to optimize re-entrant
application code originally developed in high-level
languages, such as ‘C’.
1.1.5 EASY MIGRATION
Regardless of the memory size, all devices share the
same rich set of peripherals, allowing for a smooth
migration path as applications grow and evolve.
The consistent pinout scheme used throughout the
entire family also aids in migrating to the next larger
device. This is true when moving between the 64-pin
members, between the 80-pin members, or even
jumping from 64-pin to 80-pin devices.
The PIC18F85J90 family is also largely pin compatible
with other PIC18 families, such as the PIC18F8720 and
PIC18F8722, as well as the PIC18F8490 family of
microcontrollers with LCD drivers. This allows a new
dimension to the evolution of applications, allowing
developers to select different price points within
Microchip’s PIC18 portfolio, while maintaining a similar
feature set.
• PIC18F63J90 • PIC18F83J90
• PIC18F64J90 • PIC18F84J90
• PIC18F65J90 • PIC18F85J90
PIC18F85J90 FAMILY
DS39770C-page 10 2010 Microchip Technology Inc.
1.2 LCD Driver
The on-chip LCD driver includes many features that
make the integration of displays in low-power
applications easier. These include an integrated volt-
age regulator with charge pump that allows contrast
control in software and display operation above device
VDD.
1.3 Other Special Features
•Communications: The PIC18F85J90 family
incorporates a range of serial communication
peripherals, including an Addressable USART, a
separate Enhanced USART that supports
LIN/J2602 Specification 1.2, and one Master SSP
module capable of both SPI and I2C™ (Master and
Slave) modes of operation.
•CCP Modules: All devices in the family incorporate
two Capture/Compare/PWM (CCP) modules. Up to
four different time bases may be used to perform
several different operations at once.
•10-Bit A/D Converter: This module incorporates
programmable acquisition time, allowing for a
channel to be selected and a conversion to be
initiated without waiting for a sampling period and
thus, reducing code overhead.
•Extended Watchdog Timer (WDT): This
enhanced version incorporates a 16-bit prescaler,
allowing an extended time-out range that is stable
across operating voltage and temperature. See
Section 26.0 “Electrical Characteristics” for
time-out periods.
1.4 Details on Individual Family
Members
Devices in the PIC18F85J90 family are available in
64-pin and 80-pin packages. Block diagrams for the
two groups are shown in Figure 1-1 and Figure 1-2.
The devices are differentiated from each other in four
ways:
1. Flash program memory (three sizes, ranging
from 8 Kbytes for PIC18FX3J90 devices to
32 Kbytes for PIC18FX5J90 devices).
2. Data RAM (1024 bytes for PIC18FX3J90 and
PIC18FX4J90 devices, 2048 bytes for
PIC18FX5J90 devices).
3. I/O ports (7 bidirectional ports on 64-pin devices,
9 bidirectional ports on 80-pin devices).
4. LCD Pixels: 132 pixels (33 SEGs x 4 COMs) can
be driven by 64-pin devices; 192 pixels
(48 SEGs x 4 COMs) can be driven by 80-pin
devices.
All other features for devices in this family are identical.
These are summarized in Table 1-1 and Table 1-2.
The pinouts for all devices are listed in Table 1-3 and
Table 1-4.
2010 Microchip Technology Inc. DS39770C-page 11
PIC18F85J90 FAMILY
TABLE 1-1: DEVICE FEATURES FOR THE PIC18F85J90 FAMILY (64-PIN DEVICES)
TABLE 1-2: DEVICE FEATURES FOR THE PIC18F85J90 FAMILY (80-PIN DEVICES)
Features PIC18F63J90 PIC18F64J90 PIC18F65J90
Operating Frequency DC – 40 MHz
Program Memory (Bytes) 8K 16K 32K
Program Memory (Instructions) 4096 8192 16384
Data Memory (Bytes) 1024 1024 2048
Interrupt Sources 27
I/O Ports Ports A, B, C, D, E, F, G
LCD Driver (available pixels to drive) 132 (33 SEGs x 4 COMs)
Timers 4
Capture/Compare/PWM Modules 2
Serial Communications MSSP, Addressable USART, Enhanced USART
10-Bit Analog-to-Digital Module 12 Input Channels
Resets (and Delays) POR, BOR, RESET Instruction, Stack Full, Stack Underflow, MCLR, WDT
(PWRT, OST)
Instruction Set 75 Instructions, 83 with Extended Instruction Set enabled
Packages 64-pin TQFP
Features PIC18F83J90 PIC18F84J90 PIC18F85J90
Operating Frequency DC – 40 MHz
Program Memory (Bytes) 8K 16K 32K
Program Memory (Instructions) 4096 8192 16384
Data Memory (Bytes) 1024 1024 2048
Interrupt Sources 27
I/O Ports Ports A, B, C, D, E, F, G, H, J
LCD Driver (available pixels to drive) 192 (48 SEGs x 4 COMs)
Timers 4
Capture/Compare/PWM Modules 2
Serial Communications MSSP, Addressable USART, Enhanced USART
10-Bit Analog-to-Digital Module 12 Input Channels
Resets (and Delays) POR, BOR, RESET Instruction, Stack Full, Stack Underflow, MCLR, WDT
(PWRT, OST)
Instruction Set 75 Instructions, 83 with Extended Instruction Set enabled
Packages 80-pin TQFP
PIC18F85J90 FAMILY
DS39770C-page 12 2010 Microchip Technology Inc.
FIGURE 1-1: PIC18F6XJ90 (64-PIN) BLOCK DIAGRAM
Instruction
Decode and
Control
PORTA
Data Latch
Data Memory
(2.0, 3.9
Address Latch
Data Address<12>
12
Access
BSR FSR0
FSR1
FSR2
inc/dec
logic
Address
412 4
PCH PCL
PCLATH
8
31 Level Stack
Program Counter
PRODLPRODH
8 x 8 Multiply
8
BITOP
8
8
ALU<8>
Address Latch
Program Memory
(96 Kbytes)
Data Latch
20
8
8
Table Pointer<21>
inc/dec logic
21
8
Data Bus<8>
Table Latch
8
IR
12
3
PCLATU
PCU
Note 1: See Table 1-3 for I/O port pin descriptions.
2: RA6 and RA7 are only available as digital I/O in select oscillator modes. See Section 3.0 “Oscillator Configurations” for more
information
3: Brown-out Reset and Low-Voltage Detect functions are provided when the on-board voltage regulator is enabled.
AUSART
Comparators
MSSP
Timer2Timer1 Timer3Timer0
CCP1
ADC
10-Bit
W
Instruction Bus <16>
STKPTR Bank
8
State Machine
Control Signals
Decode
8
8
EUSART
CCP2
ROM Latch
LCD
PORTC
PORTD
PORTE
PORTF
PORTG
RA0:RA7(1,2)
RC0:RC7(1)
RD0:RD7(1)
RE0:RE1,
RF1:RF7(1)
RG0:RG4(1)
PORTB
RB0:RB7(1)
OSC1/CLKI
OSC2/CLKO
VDD,
Timing
Generation
VSS MCLR
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
BOR and
LVD(3)
Precision
Reference
Band Gap
INTRC
Oscillator
Regulator
Voltage
VDDCORE/VCAP
ENVREG
Kbytes)
Driver
8 MHz
Oscillator
RE3:RE7(1)
2010 Microchip Technology Inc. DS39770C-page 13
PIC18F85J90 FAMILY
FIGURE 1-2: PIC18F8XJ90 (80-PIN) BLOCK DIAGRAM
Instruction
Decode and
Control
Data Latch
Data Memory
(2.0, 3.9
Address Latch
Data Address<12>
12
Access
BSR FSR0
FSR1
FSR2
inc/dec
logic
Address
412 4
PCH PCL
PCLATH
8
31 Level Stack
Program Counter
PRODLPRODH
8 x 8 Multiply
8
BITOP
8
8
ALU<8>
Address Latch
Program Memory
(96 Kbytes)
Data Latch
20
8
8
Table Pointer<21>
inc/dec logic
21
8
Data Bus<8>
Table Latch
8
IR
12
3
PCLATU
PCU
W
Instruction Bus <16>
STKPTR Bank
8
State Machine
Control Signals
Decode
8
8
ROM Latch
OSC1/CLKI
OSC2/CLKO
VDD,VSS MCLR
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Precision
Reference
Band Gap
Regulator
Voltage
VDDCORE/VCAP
ENVREG
Kbytes)
PORTA
PORTC
PORTD
PORTE
PORTF
PORTG
RA0:RA7(1,2)
RC0:RC7(1)
RD0:RD7(1)
RF1:RF7(1)
RG0:RG4(1)
PORTB
RB0:RB7(1)
PORTH
RH0:RH7(1)
PORTJ
RJ0:RJ7(1)
Note 1: See Table 1-3 for I/O port pin descriptions.
2: RA6 and RA7 are only available as digital I/O in select oscillator modes. See Section 3.0 “Oscillator Configurations” for
more information.
3: Brown-out Reset and Low-Voltage Detect functions are provided when the on-board voltage regulator is enabled.
Timing
Generation
INTRC
Oscillator
8 MHz
Oscillator
AUSART
Comparators
MSSP
Timer2Timer1 Timer3Timer0
CCP1
ADC
10-Bit
EUSART
CCP2 LCD
Driver
RE0:RE1,
RE3:RE7(1)
BOR and
LVD(3)
PIC18F85J90 FAMILY
DS39770C-page 14 2010 Microchip Technology Inc.
TABLE 1-3: PIC18F6XJ90 PINOUT I/O DESCRIPTIONS
Pin Name
Pin Number Pin
Type
Buffer
Type Description
TQFP
MCLR 7 I ST Master Clear (input) or programming voltage (input). This
pin is an active-low Reset to the device.
OSC1/CLKI/RA7
OSC1
CLKI
RA7
39
I
I
I/O
CMOS
CMOS
TTL
Oscillator crystal or external clock input.
Oscillator crystal input.
External clock source input. Always associated
with pin function OSC1. (See related OSC1/CLKI,
OSC2/CLKO pins.)
General purpose I/O pin.
OSC2/CLKO/RA6
OSC2
CLKO
RA6
40
O
O
I/O
—
—
TTL
Oscillator crystal or clock output.
Oscillator crystal output. Connects to crystal or
resonator in Crystal Oscillator mode.
In EC modes, OSC2 pin outputs CLKO, which has
1/4 the frequency of OSC1 and denotes the
instruction cycle rate.
General purpose I/O pin.
PORTA is a bidirectional I/O port.
RA0/AN0
RA0
AN0
24
I/O
I
TTL
Analog
Digital I/O.
Analog Input 0.
RA1/AN1/SEG18
RA1
AN1
SEG18
23
I/O
I
O
TTL
Analog
Analog
Digital I/O.
Analog Input 1.
SEG18 output for LCD.
RA2/AN2/VREF-
RA2
AN2
VREF-
22
I/O
I
I
TTL
Analog
Analog
Digital I/O.
Analog Input 2.
A/D reference voltage (low) input.
RA3/AN3/VREF+
RA3
AN3
VREF+
21
I/O
I
I
TTL
Analog
Analog
Digital I/O.
Analog Input 3.
A/D reference voltage (high) input.
RA4/T0CKI/SEG14
RA4
T0CKI
SEG14
28
I/O
I
O
ST/OD
ST
Analog
Digital I/O. Open-drain when configured as output.
Timer0 external clock input.
SEG14 output for LCD.
RA5/AN4/SEG15
RA5
AN4
SEG15
27
I/O
I
O
TTL
Analog
Analog
Digital I/O.
Analog Input 4.
SEG15 output for LCD.
RA6 See the OSC2/CLKO/RA6 pin.
RA7 See the OSC1/CLKI/RA7 pin.
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to VDD)
I2C™ = I2C/SMBus
Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set.
2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.
2010 Microchip Technology Inc. DS39770C-page 15
PIC18F85J90 FAMILY
PORTB is a bidirectional I/O port. PORTB can be software
programmed for internal weak pull-ups on all inputs.
RB0/INT0/SEG30
RB0
INT0
SEG30
48
I/O
I
O
TTL
ST
Analog
Digital I/O.
External Interrupt 0.
SEG30 output for LCD.
RB1/INT1/SEG8
RB1
INT1
SEG8
47
I/O
I
O
TTL
ST
Analog
Digital I/O.
External Interrupt 1.
SEG8 output for LCD.
RB2/INT2/SEG9
RB2
INT2
SEG9
46
I/O
I
O
TTL
ST
Analog
Digital I/O.
External Interrupt 2.
SEG9 output for LCD.
RB3/INT3/SEG10
RB3
INT3
SEG10
45
I/O
I
O
TTL
ST
Analog
Digital I/O.
External Interrupt 3.
SEG10 output for LCD.
RB4/KBI0/SEG11
RB4
KBI0
SEG11
44
I/O
I
O
TTL
TTL
Analog
Digital I/O.
Interrupt-on-change pin.
SEG11 output for LCD.
RB5/KBI1/SEG29
RB5
KBI1
SEG29
43
I/O
I
O
TTL
TTL
Analog
Digital I/O.
Interrupt-on-change pin.
SEG29 output for LCD.
RB6/KBI2/PGC
RB6
KBI2
PGC
42
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP™ programming clock pin.
RB7/KBI3/PGD
RB7
KBI3
PGD
37
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming data pin.
TABLE 1-3: PIC18F6XJ90 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number Pin
Type
Buffer
Type Description
TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to VDD)
I2C™ = I2C/SMBus
Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set.
2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.
PIC18F85J90 FAMILY
DS39770C-page 16 2010 Microchip Technology Inc.
PORTC is a bidirectional I/O port.
RC0/T1OSO/T13CKI
RC0
T1OSO
T13CKI
30
I/O
O
I
ST
—
ST
Digital I/O.
Timer1 oscillator output.
Timer1/Timer3 external clock input.
RC1/T1OSI/CCP2/SEG32
RC1
T1OSI
CCP2(1)
SEG32
29
I/O
I
I/O
O
ST
CMOS
ST
Analog
Digital I/O.
Timer1 oscillator input.
Capture 2 input/Compare 2 output/PWM2 output.
SEG32 output for LCD.
RC2/CCP1/SEG13
RC2
CCP1
SEG13
33
I/O
I/O
O
ST
ST
Analog
Digital I/O.
Capture 1 input/Compare 1 output/PWM1 output.
SEG13 output for LCD.
RC3/SCK/SCL/SEG17
RC3
SCK
SCL
SEG17
34
I/O
I/O
I/O
O
ST
ST
I2C
Analog
Digital I/O.
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I2C™ mode.
SEG17 output for LCD.
RC4/SDI/SDA/SEG16
RC4
SDI
SDA
SEG16
35
I/O
I
I/O
O
ST
ST
I2C
Analog
Digital I/O.
SPI data in.
I2C data I/O.
SEG16 output for LCD.
RC5/SDO/SEG12
RC5
SDO
SEG12
36
I/O
O
O
ST
—
Analog
Digital I/O.
SPI data out.
SEG12 output for LCD.
RC6/TX1/CK1/SEG27
RC6
TX1
CK1
SEG27
31
I/O
O
I/O
O
ST
—
ST
Analog
Digital I/O.
EUSART asynchronous transmit.
EUSART synchronous clock (see related RX1/DT1).
SEG27 output for LCD.
RC7/RX1/DT1/SEG28
RC7
RX1
DT1
SEG28
32
I/O
I
I/O
O
ST
ST
ST
Analog
Digital I/O.
EUSART asynchronous receive.
EUSART synchronous data (see related TX1/CK1).
SEG28 output for LCD.
TABLE 1-3: PIC18F6XJ90 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number Pin
Type
Buffer
Type Description
TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to VDD)
I2C™ = I2C/SMBus
Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set.
2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.
2010 Microchip Technology Inc. DS39770C-page 17
PIC18F85J90 FAMILY
PORTD is a bidirectional I/O port.
RD0/SEG0
RD0
SEG0
58
I/O
O
ST
Analog
Digital I/O.
SEG0 output for LCD.
RD1/SEG1
RD1
SEG1
55
I/O
O
ST
Analog
Digital I/O.
SEG1 output for LCD.
RD2/SEG2
RD2
SEG2
54
I/O
O
ST
Analog
Digital I/O.
SEG2 output for LCD.
RD3/SEG3
RD3
SEG3
53
I/O
O
ST
Analog
Digital I/O.
SEG3 output for LCD.
RD4/SEG4
RD4
SEG4
52
I/O
O
ST
Analog
Digital I/O.
SEG4 output for LCD.
RD5/SEG5
RD5
SEG5
51
I/O
O
ST
Analog
Digital I/O.
SEG5 output for LCD.
RD6/SEG6
RD6
SEG6
50
I/O
O
ST
Analog
Digital I/O.
SEG6 output for LCD.
RD7/SEG7
RD7
SEG7
49
I/O
O
ST
Analog
Digital I/O.
SEG7 output for LCD.
TABLE 1-3: PIC18F6XJ90 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number Pin
Type
Buffer
Type Description
TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to VDD)
I2C™ = I2C/SMBus
Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set.
2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.
PIC18F85J90 FAMILY
DS39770C-page 18 2010 Microchip Technology Inc.
PORTE is a bidirectional I/O port.
RE0/LCDBIAS1
RE0
LCDBIAS1
2
I/O
I
ST
Analog
Digital I/O.
BIAS1 input for LCD.
RE1/LCDBIAS2
RE1
LCDBIAS2
1
I/O
I
ST
Analog
Digital I/O.
BIAS2 input for LCD.
LCDBIAS3 64 I Analog BIAS3 input for LCD.
RE3/COM0
RE3
COM0
63
I/O
O
ST
Analog
Digital I/O.
COM0 output for LCD.
RE4/COM1
RE4
COM1
62
I/O
O
ST
Analog
Digital I/O.
COM1 output for LCD.
RE5/COM2
RE5
COM2
61
I/O
O
ST
Analog
Digital I/O.
COM2 output for LCD.
RE6/COM3
RE6
COM3
60
I/O
O
ST
Analog
Digital I/O.
COM3 output for LCD.
RE7/CCP2/SEG31
RE7
CCP2(2)
SEG31
59
I/O
I/O
O
ST
ST
Analog
Digital I/O.
Capture 2 input/Compare 2 output/PWM2 output.
SEG31 output for LCD.
TABLE 1-3: PIC18F6XJ90 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number Pin
Type
Buffer
Type Description
TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to VDD)
I2C™ = I2C/SMBus
Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set.
2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.
2010 Microchip Technology Inc. DS39770C-page 19
PIC18F85J90 FAMILY
PORTF is a bidirectional I/O port.
RF1/AN6/C2OUT/SEG19
RF1
AN6
C2OUT
SEG19
17
I/O
I
O
O
ST
Analog
—
Analog
Digital I/O.
Analog Input 6.
Comparator 2 output.
SEG19 output for LCD.
RF2/AN7/C1OUT/SEG20
RF2
AN7
C1OUT
SEG20
16
I/O
I
O
O
ST
Analog
—
Analog
Digital I/O.
Analog Input 7.
Comparator 1 output.
SEG20 output for LCD.
RF3/AN8/SEG21
RF3
AN8
SEG21
15
I/O
I
O
ST
Analog
Analog
Digital I/O.
Analog input 8.
SEG21 output for LCD.
RF4/AN9/SEG22
RF4
AN9
SEG22
14
I/O
I
O
ST
Analog
Analog
Digital I/O.
Analog Input 9.
SEG22 output for LCD.
RF5/AN10/CVREF/SEG23
RF5
AN10
CVREF
SEG23
13
I/O
I
O
O
ST
Analog
Analog
Analog
Digital I/O.
Analog Input 10.
Comparator reference voltage output.
SEG23 output for LCD.
RF6/AN11/SEG24
RF6
AN11
SEG24
12
I/O
I
O
ST
Analog
Analog
Digital I/O.
Analog Input 11.
SEG24 output for LCD.
RF7/AN5/SS/SEG25
RF7
AN5
SS
SEG25
11
I/O
O
I
O
ST
Analog
TTL
Analog
Digital I/O.
Analog Input 5.
SPI slave select input.
SEG25 output for LCD.
TABLE 1-3: PIC18F6XJ90 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number Pin
Type
Buffer
Type Description
TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to VDD)
I2C™ = I2C/SMBus
Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set.
2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.
PIC18F85J90 FAMILY
DS39770C-page 20 2010 Microchip Technology Inc.
PORTG is a bidirectional I/O port.
RG0/LCDBIAS0
RG0
LCDBIAS0
3
I/O
I
ST
Analog
Digital I/O.
BIAS0 input for LCD.
RG1/TX2/CK2
RG1
TX2
CK2
4
I/O
O
I/O
ST
—
ST
Digital I/O.
AUSART asynchronous transmit.
AUSART synchronous clock (see related RX2/DT2).
RG2/RX2/DT2/VLCAP1
RG2
RX2
DT2
VLCAP1
5
I/O
I
I/O
I
ST
ST
ST
Analog
Digital I/O.
AUSART asynchronous receive.
AUSART synchronous data (see related TX2/CK2).
LCD charge pump capacitor input.
RG3/VLCAP2
RG3
VLCAP2
6
I/O
I
ST
Analog
Digital I/O.
LCD charge pump capacitor input.
RG4/SEG26
RG4
SEG26
8
I/O
O
ST
Analog
Digital I/O.
SEG26 output for LCD.
VSS 9, 25, 41, 56 P — Ground reference for logic and I/O pins.
VDD 26, 38, 57 P — Positive supply for logic and I/O pins.
AVSS 20 P — Ground reference for analog modules.
AVDD 19 P — Positive supply for analog modules.
ENVREG 18 I ST Enable for on-chip voltage regulator.
VDDCORE/VCAP
VDDCORE
VCAP
10
P
P
—
—
Core logic power or external filter capacitor connection.
Positive supply for microcontroller core logic
(regulator disabled).
External filter capacitor connection (regulator enabled).
TABLE 1-3: PIC18F6XJ90 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number Pin
Type
Buffer
Type Description
TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to VDD)
I2C™ = I2C/SMBus
Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set.
2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.
2010 Microchip Technology Inc. DS39770C-page 21
PIC18F85J90 FAMILY
TABLE 1-4: PIC18F8XJ90 PINOUT I/O DESCRIPTIONS
Pin Name
Pin Number Pin
Type
Buffer
Type Description
TQFP
MCLR 9 I ST Master Clear (input) or programming voltage (input). This
pin is an active-low Reset to the device.
OSC1/CLKI/RA7
OSC1
CLKI
RA7
49
I
I
I/O
CMOS
CMOS
TTL
Oscillator crystal or external clock input.
Oscillator crystal input.
External clock source input. Always associated
with pin function OSC1. (See related OSC1/CLKI,
OSC2/CLKO pins.)
General purpose I/O pin.
OSC2/CLKO/RA6
OSC2
CLKO
RA6
50
O
O
I/O
—
—
TTL
Oscillator crystal or clock output.
Oscillator crystal output. Connects to crystal or
resonator in Crystal Oscillator mode.
In EC modes, OSC2 pin outputs CLKO, which has
1/4 the frequency of OSC1 and denotes the
instruction cycle rate.
General purpose I/O pin.
PORTA is a bidirectional I/O port.
RA0/AN0
RA0
AN0
30
I/O
I
TTL
Analog
Digital I/O.
Analog Input 0.
RA1/AN1/SEG18
RA1
AN1
SEG18
29
I/O
I
O
TTL
Analog
Analog
Digital I/O.
Analog Input 1.
SEG18 output for LCD.
RA2/AN2/VREF-
RA2
AN2
VREF-
28
I/O
I
I
TTL
Analog
Analog
Digital I/O.
Analog Input 2.
A/D reference voltage (low) input.
RA3/AN3/VREF+
RA3
AN3
VREF+
27
I/O
I
I
TTL
Analog
Analog
Digital I/O.
Analog Input 3.
A/D reference voltage (high) input.
RA4/T0CKI/SEG14
RA4
T0CKI
SEG14
34
I/O
I
O
ST/OD
ST
Analog
Digital I/O. Open-drain when configured as output.
Timer0 external clock input.
SEG14 output for LCD.
RA5/AN4/SEG15
RA5
AN4
SEG15
33
I/O
I
O
TTL
Analog
Analog
Digital I/O.
Analog Input 4.
SEG15 output for LCD.
RA6 See the OSC2/CLKO/RA6 pin.
RA7 See the OSC1/CLKI/RA7 pin.
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to VDD)
I2C™ = I2C/SMBus
Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set.
2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.
PIC18F85J90 FAMILY
DS39770C-page 22 2010 Microchip Technology Inc.
PORTB is a bidirectional I/O port. PORTB can be software
programmed for internal weak pull-ups on all inputs.
RB0/INT0/SEG30
RB0
INT0
SEG30
58
I/O
I
O
TTL
ST
Analog
Digital I/O.
External Interrupt 0.
SEG30 output for LCD.
RB1/INT1/SEG8
RB1
INT1
SEG8
57
I/O
I
O
TTL
ST
Analog
Digital I/O.
External Interrupt 1.
SEG8 output for LCD.
RB2/INT2/SEG9
RB2
INT2
SEG9
56
I/O
I
O
TTL
ST
Analog
Digital I/O.
External Interrupt 2.
SEG9 output for LCD.
RB3/INT3/SEG10
RB3
INT3
SEG10
55
I/O
I
O
TTL
ST
Analog
Digital I/O.
External Interrupt 3.
SEG10 output for LCD.
RB4/KBI0/SEG11
RB4
KBI0
SEG11
54
I/O
I
O
TTL
TTL
Analog
Digital I/O.
Interrupt-on-change pin.
SEG11 output for LCD.
RB5/KBI1/SEG29
RB5
KBI1
SEG29
53
I/O
I
O
TTL
TTL
Analog
Digital I/O.
Interrupt-on-change pin.
SEG29 output for LCD.
RB6/KBI2/PGC
RB6
KBI2
PGC
52
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP™ programming clock pin.
RB7/KBI3/PGD
RB7
KBI3
PGD
47
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming data pin.
TABLE 1-4: PIC18F8XJ90 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number Pin
Type
Buffer
Type Description
TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to VDD)
I2C™ = I2C/SMBus
Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set.
2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.
2010 Microchip Technology Inc. DS39770C-page 23
PIC18F85J90 FAMILY
PORTC is a bidirectional I/O port.
RC0/T1OSO/T13CKI
RC0
T1OSO
T13CKI
36
I/O
O
I
ST
—
ST
Digital I/O.
Timer1 oscillator output.
Timer1/Timer3 external clock input.
RC1/T1OSI/CCP2/SEG32
RC1
T1OSI
CCP2(1)
SEG32
35
I/O
I
I/O
O
ST
CMOS
ST
Analog
Digital I/O.
Timer1 oscillator input.
Capture 2 input/Compare 2 output/PWM2 output.
SEG32 output for LCD.
RC2/CCP1/SEG13
RC2
CCP1
SEG13
43
I/O
I/O
O
ST
ST
Analog
Digital I/O.
Capture 1 input/Compare 1 output/PWM1 output.
SEG13 output for LCD.
RC3/SCK/SCL/SEG17
RC3
SCK
SCL
SEG17
44
I/O
I/O
I/O
O
ST
ST
I2C
Analog
Digital I/O.
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I2C™ mode.
SEG17 output for LCD.
RC4/SDI/SDA/SEG16
RC4
SDI
SDA
SEG16
45
I/O
I
I/O
O
ST
ST
I2C
Analog
Digital I/O.
SPI data in.
I2C data I/O.
SEG16 output for LCD.
RC5/SDO/SEG12
RC5
SDO
SEG12
46
I/O
O
O
ST
—
Analog
Digital I/O.
SPI data out.
SEG12 output for LCD.
RC6/TX1/CK1/SEG27
RC6
TX1
CK1
SEG27
37
I/O
O
I/O
O
ST
—
ST
Analog
Digital I/O.
EUSART asynchronous transmit.
EUSART synchronous clock (see related RX1/DT1).
SEG27 output for LCD.
RC7/RX1/DT1/SEG28
RC7
RX1
DT1
SEG28
38
I/O
I
I/O
O
ST
ST
ST
Analog
Digital I/O.
EUSART asynchronous receive.
EUSART synchronous data (see related TX1/CK1).
SEG28 output for LCD.
TABLE 1-4: PIC18F8XJ90 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number Pin
Type
Buffer
Type Description
TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to VDD)
I2C™ = I2C/SMBus
Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set.
2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.
PIC18F85J90 FAMILY
DS39770C-page 24 2010 Microchip Technology Inc.
PORTD is a bidirectional I/O port.
RD0/SEG0
RD0
SEG0
72
I/O
O
ST
Analog
Digital I/O.
SEG0 output for LCD.
RD1/SEG1
RD1
SEG1
69
I/O
O
ST
Analog
Digital I/O.
SEG1 output for LCD.
RD2/SEG2
RD2
SEG2
68
I/O
O
ST
Analog
Digital I/O.
SEG2 output for LCD.
RD3/SEG3
RD3
SEG3
67
I/O
O
ST
Analog
Digital I/O.
SEG3 output for LCD.
RD4/SEG4
RD4
SEG4
66
I/O
O
ST
Analog
Digital I/O.
SEG4 output for LCD.
RD5/SEG5
RD5
SEG5
65
I/O
O
ST
Analog
Digital I/O.
SEG5 output for LCD.
RD6/SEG6
RD6
SEG6
64
I/O
O
ST
Analog
Digital I/O.
SEG6 output for LCD.
RD7/SEG7
RD7
SEG7
63
I/O
O
ST
Analog
Digital I/O.
SEG7 output for LCD.
TABLE 1-4: PIC18F8XJ90 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number Pin
Type
Buffer
Type Description
TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to VDD)
I2C™ = I2C/SMBus
Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set.
2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.
2010 Microchip Technology Inc. DS39770C-page 25
PIC18F85J90 FAMILY
PORTE is a bidirectional I/O port.
RE0/LCDBIAS1
RE0
LCDBIAS1
4
I/O
I
ST
Analog
Digital I/O.
BIAS1 input for LCD.
RE1/LCDBIAS2
RE1
LCDBIAS2
3
I/O
I
ST
Analog
Digital I/O.
BIAS2 input for LCD.
LCDBIAS3 78 I Analog BIAS3 input for LCD.
RE3/COM0
RE3
COM0
77
I/O
O
ST
Analog
Digital I/O.
COM0 output for LCD.
RE4/COM1
RE4
COM1
76
I/O
O
ST
Analog
Digital I/O.
COM1 output for LCD.
RE5/COM2
RE5
COM2
75
I/O
O
ST
Analog
Digital I/O.
COM2 output for LCD.
RE6/COM3
RE6
COM3
74
I/O
O
ST
Analog
Digital I/O.
COM3 output for LCD.
RE7/CCP2/SEG31
RE7
CCP2(2)
SEG31
73
I/O
I/O
O
ST
ST
Analog
Digital I/O.
Capture 2 input/Compare 2 output/PWM2 output.
SEG31 output for LCD.
TABLE 1-4: PIC18F8XJ90 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number Pin
Type
Buffer
Type Description
TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to VDD)
I2C™ = I2C/SMBus
Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set.
2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.
PIC18F85J90 FAMILY
DS39770C-page 26 2010 Microchip Technology Inc.
PORTF is a bidirectional I/O port.
RF1/AN6/C2OUT/SEG19
RF1
AN6
C2OUT
SEG19
23
I/O
I
O
O
ST
Analog
—
Analog
Digital I/O.
Analog Input 6.
Comparator 2 output.
SEG19 output for LCD.
RF2/AN7/C1OUT/SEG20
RF2
AN7
C1OUT
SEG20
18
I/O
I
O
O
ST
Analog
—
Analog
Digital I/O.
Analog Input 7.
Comparator 1 output.
SEG20 output for LCD.
RF3/AN8/SEG21
RF3
AN8
SEG21
17
I/O
I
O
ST
Analog
Analog
Digital I/O.
Analog Input 8.
SEG21 output for LCD.
RF4/AN9/SEG22
RF4
AN9
SEG22
16
I/O
I
O
ST
Analog
Analog
Digital I/O.
Analog Input 9.
SEG22 output for LCD.
RF5/AN10/CVREF/SEG23
RF5
AN10
CVREF
SEG23
15
I/O
I
O
O
ST
Analog
Analog
Analog
Digital I/O.
Analog Input 10.
Comparator reference voltage output.
SEG23 output for LCD.
RF6/AN11/SEG24
RF6
AN11
SEG24
14
I/O
I
O
ST
Analog
Analog
Digital I/O.
Analog Input 11.
SEG24 output for LCD.
RF7/AN5/SS/SEG25
RF7
AN5
SS
SEG25
13
I/O
O
I
O
ST
Analog
TTL
Analog
Digital I/O.
Analog Input 5.
SPI slave select input.
SEG25 output for LCD.
TABLE 1-4: PIC18F8XJ90 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number Pin
Type
Buffer
Type Description
TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to VDD)
I2C™ = I2C/SMBus
Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set.
2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.
2010 Microchip Technology Inc. DS39770C-page 27
PIC18F85J90 FAMILY
PORTG is a bidirectional I/O port.
RG0/LCDBIAS0
RG0
LCDBIAS0
5
I/O
I
ST
Analog
Digital I/O.
BIAS0 input for LCD.
RG1/TX2/CK2
RG1
TX2
CK2
6
I/O
O
I/O
ST
—
ST
Digital I/O.
AUSART asynchronous transmit.
AUSART synchronous clock (see related RX2/DT2).
RG2/RX2/DT2/VLCAP1
RG2
RX2
DT2
VLCAP1
7
I/O
I
I/O
I
ST
ST
ST
Analog
Digital I/O.
AUSART asynchronous receive.
AUSART synchronous data (see related TX2/CK2).
LCD charge pump capacitor input.
RG3/VLCAP2
RG3
VLCAP2
8
I/O
I
ST
Analog
Digital I/O.
LCD charge pump capacitor input.
RG4/SEG26
RG4
SEG26
10
I/O
O
ST
Analog
Digital I/O.
SEG26 output for LCD.
TABLE 1-4: PIC18F8XJ90 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number Pin
Type
Buffer
Type Description
TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to VDD)
I2C™ = I2C/SMBus
Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set.
2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.
PIC18F85J90 FAMILY
DS39770C-page 28 2010 Microchip Technology Inc.
PORTH is a bidirectional I/O port.
RH0/SEG47
RH0
SEG47
79
I/O
O
ST
Analog
Digital I/O.
SEG47 output for LCD.
RH1/SEG46
RH1
SEG46
80
I/O
O
ST
Analog
Digital I/O.
SEG46 output for LCD.
RH2/SEG45
RH2
SEG45
1
I/O
O
ST
Analog
Digital I/O.
SEG45 output for LCD.
RH3/SEG44
RH3
SEG44
2
I/O
O
ST
Analog
Digital I/O.
SEG44 output for LCD.
RH4/SEG40
RH4
SEG40
22
I/O
O
ST
Analog
Digital I/O.
SEG40 output for LCD.
RH5/SEG41
RH5
SEG41
21
I/O
O
ST
Analog
Digital I/O.
SEG41 output for LCD.
RH6/SEG42
RH6
SEG42
20
I/O
O
ST
Analog
Digital I/O.
SEG42 output for LCD.
RH7/SEG43
RH7
SEG43
19
I/O
O
ST
Analog
Digital I/O.
SEG43 output for LCD.
TABLE 1-4: PIC18F8XJ90 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number Pin
Type
Buffer
Type Description
TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to VDD)
I2C™ = I2C/SMBus
Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set.
2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.
2010 Microchip Technology Inc. DS39770C-page 29
PIC18F85J90 FAMILY
PORTJ is a bidirectional I/O port.
RJ0 62 I/O ST Digital I/O.
RJ1/SEG33
RJ1
SEG33
61
I/O
O
ST
Analog
Digital I/O.
SEG33 output for LCD.
RJ2/SEG34
RJ2
SEG34
60
I/O
O
ST
Analog
Digital I/O.
SEG34 output for LCD.
RJ3/SEG35
RJ3
SEG35
59
I/O
O
ST
Analog
Digital I/O.
SEG35 output for LCD.
RJ4/SEG39
RJ4
SEG39
39
I/O
O
ST
Analog
Digital I/O.
SEG39 output for LCD.
RJ5/SEG38
RJ5
SEG38
40
I/O
O
ST
Analog
Digital I/O
SEG38 output for LCD.
RJ6/SEG37
RJ6
SEG37
41
I/O
O
ST
Analog
Digital I/O.
SEG37 output for LCD.
RJ7/SEG36
RJ7
SEG36
42
I/O
O
ST
Analog
Digital I/O.
SEG36 output for LCD.
VSS 11, 31, 51, 70 P — Ground reference for logic and I/O pins.
VDD 32, 48, 71 P — Positive supply for logic and I/O pins.
AVSS 26 P — Ground reference for analog modules.
AVDD 25 P — Positive supply for analog modules.
ENVREG 24 I ST Enable for on-chip voltage regulator.
VDDCORE/VCAP
VDDCORE
VCAP
12
P
P
—
—
Core logic power or external filter capacitor connection.
Positive supply for microcontroller core logic
(regulator disabled).
External filter capacitor connection (regulator enabled).
TABLE 1-4: PIC18F8XJ90 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number Pin
Type
Buffer
Type Description
TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to VDD)
I2C™ = I2C/SMBus
Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set.
2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.
PIC18F85J90 FAMILY
DS39770C-page 30 2010 Microchip Technology Inc.
NOTES:
2010 Microchip Technology Inc. DS39770C-page 31
PIC18F85J90 FAMILY
2.0 GUIDELINES FOR GETTING
STARTED WITH PIC18FJ
MICROCONTROLLERS
2.1 Basic Connection Requirements
Getting started with the PIC18F85J90 family family of
8-bit microcontrollers requires attention to a minimal
set of device pin connections before proceeding with
development.
The following pins must always be connected:
•All V
DD and VSS pins
(see Section 2.2 “Power Supply Pins”)
•All AV
DD and AVSS pins, regardless of whether or
not the analog device features are used
(see Section 2.2 “Power Supply Pins”)
•M
CLR pin
(see Section 2.3 “Master Clear (MCLR) Pin”)
• ENVREG (if implemented) and VCAP/VDDCORE pins
(see Section 2.4 “Voltage Regulator Pins
(ENVREG and VCAP/VDDCORE)”)
These pins must also be connected if they are being
used in the end application:
• PGC/PGD pins used for In-Circuit Serial
Programming™ (ICSP™) and debugging purposes
(see Section 2.5 “ICSP Pins”)
• OSCI and OSCO pins when an external oscillator
source is used
(see Section 2.6 “External Oscillator Pins”)
Additionally, the following pins may be required:
•V
REF+/VREF- pins are used when external voltage
reference for analog modules is implemented
The minimum mandatory connections are shown in
Figure 2-1.
FIGURE 2-1: RECOMMENDED
MINIMUM CONNECTIONS
Note: The AVDD and AVSS pins must always be
connected, regardless of whether any of
the analog modules are being used.
PIC18FXXJXX
VDD
VSS
VDD
VSS
VSS
VDD
AVDD
AVSS
VDD
VSS
C1
R1
VDD
MCLR
VCAP/VDDCORE
R2 ENVREG
(1)
C7
C2(2)
C3(2)
C4(2)
C5(2)
C6(2)
Key (all values are recommendations):
C1 through C6: 0.1 F, 20V ceramic
C7: 10 F, 6.3V or greater, tantalum or ceramic
R1: 10 kΩ
R2: 100Ω to 470Ω
Note 1: See Section 2.4 “Voltage Regulator Pins
(ENVREG and VCAP/VDDCORE)” for
explanation of ENVREG pin connections.
2: The example shown is for a PIC18F device
with five VDD/VSS and AVDD/AVSS pairs.
Other devices may have more or less pairs;
adjust the number of decoupling capacitors
appropriately.
(1)
PIC18F85J90 FAMILY
DS39770C-page 32 2010 Microchip Technology Inc.
2.2 Power Supply Pins
2.2.1 DECOUPLING CAPACITORS
The use of decoupling capacitors on every pair of
power supply pins, such as VDD, VSS, AVDD and
AVSS, is required.
Consider the following criteria when using decoupling
capacitors:
•Value and type of capacitor: A 0.1 F (100 nF),
10-20V capacitor is recommended. The capacitor
should be a low-ESR device, with a resonance
frequency in the range of 200 MHz and higher.
Ceramic capacitors are recommended.
•Placement on the printed circuit board: The
decoupling capacitors should be placed as close
to the pins as possible. It is recommended to
place the capacitors on the same side of the
board as the device. If space is constricted, the
capacitor can be placed on another layer on the
PCB using a via; however, ensure that the trace
length from the pin to the capacitor is no greater
than 0.25 inch (6 mm).
•Handling high-frequency noise: If the board is
experiencing high-frequency noise (upward of
tens of MHz), add a second ceramic type capaci-
tor in parallel to the above described decoupling
capacitor. The value of the second capacitor can
be in the range of 0.01 F to 0.001 F. Place this
second capacitor next to each primary decoupling
capacitor. In high-speed circuit designs, consider
implementing a decade pair of capacitances as
close to the power and ground pins as possible
(e.g., 0.1 F in parallel with 0.001 F).
•Maximizing performance: On the board layout
from the power supply circuit, run the power and
return traces to the decoupling capacitors first,
and then to the device pins. This ensures that the
decoupling capacitors are first in the power chain.
Equally important is to keep the trace length
between the capacitor and the power pins to a
minimum, thereby reducing PCB trace
inductance.
2.2.2 TANK CAPACITORS
On boards with power traces running longer than
six inches in length, it is suggested to use a tank capac-
itor for integrated circuits, including microcontrollers, to
supply a local power source. The value of the tank
capacitor should be determined based on the trace
resistance that connects the power supply source to
the device, and the maximum current drawn by the
device in the application. In other words, select the tank
capacitor so that it meets the acceptable voltage sag at
the device. Typical values range from 4.7 F to 47 F.
2.3 Master Clear (MCLR) Pin
The MCLR pin provides two specific device
functions: Device Reset, and Device Programming
and Debugging. If programming and debugging are
not required in the end application, a direct
connection to VDD may be all that is required. The
addition of other components, to help increase the
application’s resistance to spurious Resets from
voltage sags, may be beneficial. A typical
configuration is shown in Figure 2-1. Other circuit
designs may be implemented, depending on the
application’s requirements.
During programming and debugging, the resistance
and capacitance that can be added to the pin must
be considered. Device programmers and debuggers
drive the MCLR pin. Consequently, specific voltage
levels (VIH and VIL) and fast signal transitions must
not be adversely affected. Therefore, specific values
of R1 and C1 will need to be adjusted based on the
application and PCB requirements. For example, it is
recommended that the capacitor, C1, be isolated
from the MCLR pin during programming and
debugging operations by using a jumper (Figure 2-2).
The jumper is replaced for normal run-time
operations.
Any components associated with the MCLR pin
should be placed within 0.25 inch (6 mm) of the pin.
FIGURE 2-2: EXAMPLE OF MCLR PIN
CONNECTIONS
Note 1: R1 10 k is recommended. A suggested
starting value is 10 k. Ensure that the
MCLR pin VIH and VIL specifications are met.
2: R2 470 will limit any current flowing into
MCLR from the external capacitor, C, in the
event of MCLR pin breakdown, due to
Electrostatic Discharge (ESD) or Electrical
Overstress (EOS). Ensure that the MCLR pin
VIH and VIL specifications are met.
C1
R2
R1
VDD
MCLR
PIC18FXXJXX
JP
2010 Microchip Technology Inc. DS39770C-page 33
PIC18F85J90 FAMILY
2.4 Voltage Regulator Pins (ENVREG
and VCAP/VDDCORE)
The on-chip voltage regulator enable pin, ENVREG,
must always be connected directly to either a supply
voltage or to ground. Tying ENVREG to VDD enables
the regulator, while tying it to ground disables the
regulator. Refer to Section 23.3 “On-Chip Voltage
Regulator” for details on connecting and using the
on-chip regulator.
When the regulator is enabled, a low-ESR (< 5Ω)
capacitor is required on the VCAP/VDDCORE pin to
stabilize the voltage regulator output voltage. The
VCAP/VDDCORE pin must not be connected to VDD and
must use a capacitor of 10 F connected to ground. The
type can be ceramic or tantalum. A suitable example is
the Murata GRM21BF50J106ZE01 (10 F, 6.3V) or
equivalent. Designers may use Figure 2-3 to evaluate
ESR equivalence of candidate devices.
It is recommended that the trace length not exceed
0.25 inch (6 mm). Refer to Section 26.0 “Electrical
Characteristics” for additional information.
When the regulator is disabled, the VCAP/VDDCORE pin
must be tied to a voltage supply at the VDDCORE level.
Refer to Section 26.0 “Electrical Characteristics” for
information on VDD and VDDCORE.
Note that the “LF” versions of some low pin count
PIC18FJ parts (e.g., the PIC18LF45J10) do not have
the ENVREG pin. These devices are provided with the
voltage regulator permanently disabled; they must
always be provided with a supply voltage on the
VDDCORE pin.
FIGURE 2-3: FREQUENCY vs. ESR
PERFORMANCE FOR
SUGGESTED VCAP
2.5 ICSP Pins
The PGC and PGD pins are used for In-Circuit Serial
Programming™ (ICSP™) and debugging purposes. It
is recommended to keep the trace length between the
ICSP connector and the ICSP pins on the device as
short as possible. If the ICSP connector is expected to
experience an ESD event, a series resistor is recom-
mended, with the value in the range of a few tens of
ohms, not to exceed 100Ω.
Pull-up resistors, series diodes, and capacitors on the
PGC and PGD pins are not recommended as they will
interfere with the programmer/debugger communica-
tions to the device. If such discrete components are an
application requirement, they should be removed from
the circuit during programming and debugging. Alter-
natively, refer to the AC/DC characteristics and timing
requirements information in the respective device
Flash programming specification for information on
capacitive loading limits, and pin input voltage high
(VIH) and input low (VIL) requirements.
For device emulation, ensure that the “Communication
Channel Select” (i.e., PGCx/PGDx pins) programmed
into the device matches the physical connections for
the ICSP to the Microchip debugger/emulator tool.
For more information on available Microchip
development tools connection requirements, refer
toSection 24.0 “Development Support”.
10
1
0.1
0.01
0.001 0.01 0.1 1 10 100 1000 10,000
Frequency (MHz)
ESR ()
Note: Data for Murata GRM21BF50J106ZE01 shown.
Measurements at 25°C, 0V DC bias.
PIC18F85J90 FAMILY
DS39770C-page 34 2010 Microchip Technology Inc.
2.6 External Oscillator Pins
Many microcontrollers have options for at least two
oscillators: a high-frequency primary oscillator and a
low-frequency secondary oscillator (refer to
Section 3.0 “Oscillator Configurations” for details).
The oscillator circuit should be placed on the same
side of the board as the device. Place the oscillator
circuit close to the respective oscillator pins with no
more than 0.5 inch (12 mm) between the circuit
components and the pins. The load capacitors should
be placed next to the oscillator itself, on the same side
of the board.
Use a grounded copper pour around the oscillator cir-
cuit to isolate it from surrounding circuits. The
grounded copper pour should be routed directly to the
MCU ground. Do not run any signal traces or power
traces inside the ground pour. Also, if using a two-sided
board, avoid any traces on the other side of the board
where the crystal is placed.
Layout suggestions are shown in Figure 2-4. In-line
packages may be handled with a single-sided layout
that completely encompasses the oscillator pins. With
fine-pitch packages, it is not always possible to com-
pletely surround the pins and components. A suitable
solution is to tie the broken guard sections to a mirrored
ground layer. In all cases, the guard trace(s) must be
returned to ground.
In planning the application’s routing and I/O assign-
ments, ensure that adjacent port pins and other signals
in close proximity to the oscillator are benign (i.e., free
of high frequencies, short rise and fall times, and other
similar noise).
For additional information and design guidance on
oscillator circuits, please refer to these Microchip
Application Notes, available at the corporate web site
(www.microchip.com):
•AN826, “Crystal Oscillator Basics and Crystal
Selection for rfPIC™ and PICmicro® Devices”
• AN849, “Basic PICmicro® Oscillator Design”
• AN943, “Practical PICmicro® Oscillator Analysis
and Design”
•AN949, “Making Your Oscillator Work”
2.7 Unused I/Os
Unused I/O pins should be configured as outputs and
driven to a logic low state. Alternatively, connect a 1 kΩ
to 10 kΩ resistor to VSS on unused pins and drive the
output to logic low.
FIGURE 2-4: SUGGESTED PLACEMENT
OF THE OSCILLATOR
CIRCUIT
GND
`
`
`
OSC1
OSC2
T1OSO
T1OS I
Copper Pour Primary Oscillator
Crystal
Timer1 Oscillator
Crystal
DEVICE PINS
Primary
Oscillator
C1
C2
T1 Oscillator: C1 T1 Oscillator: C2
(tied to ground)
Single-Sided and In-Line Layouts:
Fine-Pitch (Dual-Sided) Layouts:
GND
OSCO
OSCI
Bottom Layer
Copper Pour
Oscillator
Crystal
Top Layer Copper Pour
C2
C1
DEVICE PINS
(tied to ground)
(tied to ground)
2010 Microchip Technology Inc. DS39770C-page 35
PIC18F85J90 FAMILY
3.0 OSCILLATOR
CONFIGURATIONS
3.1 Oscillator Types
The PIC18F85J90 family of devices can be operated in
six different oscillator modes:
1. HS High-Speed Crystal/Resonator
2. HSPLL High-Speed Crystal/Resonator
with Software PLL Control
3. EC External Clock with FOSC/4 Output
4. ECPLL External Clock with Software PLL
Control
5. INTOSC Internal Fast RC (8 MHz) oscillator
6. INTRC Internal 31 kHz Oscillator
Five of these are selected by the user by programming
the FOSC<2:0> Configuration bits. The sixth mode
(INTRC) may be invoked under software control; it can
also be configured as the default mode on device
Resets.
In addition, PIC18F85J90 family devices can switch
between different clock sources, either under software
control, or automatically under certain conditions. This
allows for additional power savings by managing
device clock speed in real time without resetting the
application.
The clock sources for the PIC18F85J90 family of
devices are shown in Figure 3-1.
FIGURE 3-1: PIC18F85J90 FAMILY CLOCK DIAGRAM
PIC18F85J90 Family
4 x PLL
FOSC<2:0>
Secondary Oscillator
T1OSCEN
Enable
Oscillator
T1OSO
T1OSI
Clock Source Option
for other modules
OSC1
OSC2
Sleep HSPLL, ECPLL
HS, EC
T1OSC
CPU
Peripherals
IDLEN
Postscaler
MUX
MUX
8 MHz
4 MHz
2 MHz
1 MHz
500 kHz
125 kHz
250 kHz
OSCCON<6:4>
111
110
101
100
011
010
001
000
31 kHz
INTRC
Source
Internal
Oscillator
Block
WDT, PWRT, FSCM
8 MHz
Internal Oscillator
(INTOSC)
OSCCON<6:4>
Clock
Control
OSCCON<1:0>
Source
8 MHz
31 kHz (INTRC)
0
1
OSCTUNE<7>
and Two-Speed Start-up
Primary Oscillator
PIC18F85J90 FAMILY
DS39770C-page 36 2010 Microchip Technology Inc.
3.2 Control Registers
The OSCCON register (Register 3-1) controls the main
aspects of the device clock’s operation. It selects the
oscillator type to be used, which of the power-managed
modes to invoke and the output frequency of the
INTOSC source. It also provides status on the
oscillators.
The OSCTUNE register (Register 3-2) controls the
tuning and operation of the internal oscillator block. It
also implements the PLLEN bits, which control the
operation of the Phase Locked Loop (PLL) in Internal
Oscillator modes (see Section 3.4.3 “PLL Frequency
Multiplier”).
REGISTER 3-1: OSCCON: OSCILLATOR CONTROL REGISTER
R/W-0 R/W-1 R/W-0 R/W-0 R(1) R-0 R/W-0 R/W-0
IDLEN IRCF2(2) IRCF1(2) IRCF0(2) OSTS IOFS SCS1(4) SCS0(4)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 IDLEN: Idle Enable bit
1 = Device enters an Idle mode when a SLEEP instruction is executed
0 = Device enters Sleep mode when a SLEEP instruction is executed
bit 6-4 IRCF<2:0>: INTOSC Source Frequency Select bits(2)
111 = 8 MHz (INTOSC drives clock directly)
110 = 4MHz
101 = 2MHz
100 = 1 MHz (default)
011 = 500kHz
010 = 250kHz
001 = 125kHz
000 = 31 kHz (from either INTOSC/256 or INTRC)(3)
bit 3 OSTS: Oscillator Start-up Time-out Status bit(1)
1 = Oscillator Start-up Timer (OST) time-out has expired; primary oscillator is running
0 = Oscillator Start-up Timer (OST) time-out is running; primary oscillator is not ready
bit 2 IOFS: INTOSC Frequency Stable bit
1 = Fast RC oscillator frequency is stable
0 = Fast RC oscillator frequency is not stable
bit 1-0 SCS<1:0:> System Clock Select bits(4)
11 = Internal oscillator block
10 = Primary oscillator
01 = Timer1 oscillator
When FOSC2 = 1:
00 = Primary oscillator
When FOSC2 = 0:
00 = Internal oscillator
Note 1: Reset state depends on state of the IESO Configuration bit.
2: Modifying these bits will cause an immediate clock frequency switch if the internal oscillator is providing
the device clocks.
3: Source selected by the INTSRC bit (OSCTUNE<7>), see text.
4: Modifying these bits will cause an immediate clock source switch.
2010 Microchip Technology Inc. DS39770C-page 37
PIC18F85J90 FAMILY
3.3 Clock Sources and
Oscillator Switching
Essentially, PIC18F85J90 family devices have three
independent clock sources:
• Primary oscillators
• Secondary oscillators
• Internal oscillator
The primary oscillators can be thought of as the main
device oscillators. These are any external oscillators
connected to the OSC1 and OSC2 pins, and include
the External Crystal and Resonator modes and the
External Clock modes. In some circumstances, the
internal oscillator block may be considered a primary
oscillator. The particular mode is defined by the FOSC
Configuration bits. The details of these modes are
covered in Section 3.4 “External Oscillator Modes”.
The secondary oscillators are external clock sources
that are not connected to the OSC1 or OSC2 pins.
These sources may continue to operate even after the
controller is placed in a power-managed mode.
PIC18F85J90 family devices offer the Timer1 oscillator
as a secondary oscillator source. This oscillator, in all
power-managed modes, is often the time base for
functions such as a Real-Time Clock. The Timer1
oscillator is discussed in greater detail in Section 12.3
“Timer1 Oscillator”
In addition to being a primary clock source in some
circumstances, the internal oscillator is available as a
power-managed mode clock source. The INTRC
source is also used as the clock source for several
special features, such as the WDT and Fail-Safe Clock
Monitor. The internal oscillator block is discussed in
more detail in Section 3.5 “Internal Oscillator
Block”.
The PIC18F85J90 family includes features that allow
the device clock source to be switched from the main
oscillator, chosen by device configuration, to one of the
alternate clock sources. When an alternate clock
source is enabled, various power-managed operating
modes are available.
REGISTER 3-2: OSCTUNE: OSCILLATOR TUNING REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
INTSRC PLLEN(1) TUN5 TUN4 TUN3 TUN2 TUN1 TUN0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 INTSRC: Internal Oscillator Low-Frequency Source Select bit
1 = 31.25 kHz device clock derived from 8 MHz INTOSC source (divide-by-256 enabled)
0 = 31 kHz device clock derived from INTRC 31 kHz oscillator
bit 6 PLLEN: Frequency Multiplier PLL Enable bit(1)
1 = PLL enabled
0 = PLL disabled
bit 5-0 TUN<5:0>: Fast RC Oscillator (INTOSC) Frequency Tuning bits
011111 = Maximum frequency
• •
• •
000001
000000 = Center frequency. Fast RC oscillator is running at the calibrated frequency.
111111
• •
• •
100000 = Minimum frequency
Note 1: Available only for ECPLL and HSPLL oscillator configurations; otherwise, this bit is unavailable and reads
as ‘0’.
PIC18F85J90 FAMILY
DS39770C-page 38 2010 Microchip Technology Inc.
3.3.1 CLOCK SOURCE SELECTION
The System Clock Select bits, SCS<1:0>
(OSCCON<1:0>), select the clock source. The avail-
able clock sources are the primary clock defined by the
FOSC<1:0> Configuration bits, the secondary clock
(Timer1 oscillator) and the internal oscillator. The clock
source changes after one or more of the bits are written
to, following a brief clock transition interval.
The OSTS (OSCCON<3>) and T1RUN (T1CON<6>)
bits indicate which clock source is currently providing
the device clock. The OSTS bit indicates that the
Oscillator Start-up Timer (OST) has timed out and the
primary clock is providing the device clock in primary
clock modes. The T1RUN bit indicates when the
Timer1 oscillator is providing the device clock in sec-
ondary clock modes. In power-managed modes, only
one of these bits will be set at any time. If neither of
these bits are set, the INTRC is providing the clock, or
the internal oscillator has just started and is not yet
stable.
The IDLEN bit determines if the device goes into Sleep
mode or one of the Idle modes when the SLEEP
instruction is executed.
The use of the flag and control bits in the OSCCON
register is discussed in more detail in Section 4.0
“Power-Managed Modes”.
3.3.1.1 System Clock Selection and the
FOSC2 Configuration Bit
The SCS bits are cleared on all forms of Reset. In the
device’s default configuration, this means the primary
oscillator defined by FOSC<1:0> (that is, one of the HS
or EC modes) is used as the primary clock source on
device Resets.
The default clock configuration on Reset can be
changed with the FOSC2 Configuration bit. This bit
determines whether the external or internal oscillator will
be the default clock source on subsequent device
Resets. By extension, it also has the effect of determin-
ing the clock source selected when SCS<1:0> are in
their Reset state (= 00). When FOSC2 = 1 (default), the
oscillator source defined by FOSC<1:0> is selected
whenever SCS<1:0> = 00. When FOSC2 = 0, the
internal oscillator block is selected whenever
SCS<1:2> = 00.
In those cases when the internal oscillator block is the
default clock on Reset, the Fast RC oscillator
(INTOSC) will be used as the device clock source. It will
initially start at 1 MHz, the postscaler selection that
corresponds to the Reset value of the IRCF<2:0> bits
(‘100’).
Regardless of the setting of FOSC2, INTRC will always
be enabled on device power-up. It serves as the clock
source until the device has loaded its configuration
values from memory. It is at this point that the FOSC
Configuration bits are read and the oscillator selection
of the operational mode is made.
Note that either the primary clock or the internal
oscillator will have two bit setting options for the
possible values of SCS<1:0>, at any given time,
depending on the setting of FOSC2.
3.3.2 OSCILLATOR TRANSITIONS
PIC18F85J90 family devices contain circuitry to
prevent clock “glitches” when switching between clock
sources. A short pause in the device clock occurs dur-
ing the clock switch. The length of this pause is the sum
of two cycles of the old clock source and three to four
cycles of the new clock source. This formula assumes
that the new clock source is stable.
Clock transitions are discussed in greater detail in
Section 4.1.2 “Entering Power-Managed Modes”.
Note 1: The Timer1 oscillator must be enabled to
select the secondary clock source. The
Timer1 oscillator is enabled by setting the
T1OSCEN bit in the Timer1 Control regis-
ter (T1CON<3>). If the Timer1 oscillator is
not enabled, then any attempt to select a
secondary clock source when executing a
SLEEP instruction will be ignored.
2: It is recommended that the Timer1
oscillator be operating and stable before
executing the SLEEP instruction or a very
long delay may occur while the Timer1
oscillator starts.
2010 Microchip Technology Inc. DS39770C-page 39
PIC18F85J90 FAMILY
3.4 External Oscillator Modes
3.4.1 CRYSTAL OSCILLATOR/CERAMIC
RESONATORS (HS MODES)
In HS or HSPLL Oscillator modes, a crystal or ceramic
resonator is connected to the OSC1 and OSC2 pins to
establish oscillation. Figure 3-2 shows the pin
connections.
The oscillator design requires the use of a parallel
resonant crystal.
TABLE 3-1: CAPACITOR SELECTION FOR
CERAMIC RESONATORS
TABLE 3-2: CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR
FIGURE 3-2: CRYSTAL/CERAMIC
RESONATOR OPERATION
(HS OR HSPLL
CONFIGURATION)
Note: Use of a series resonant crystal may give a
frequency out of the crystal manufacturer’s
specifications.
Typical Capacitor Values Used:
Mode Freq. OSC1 OSC2
HS 8.0 MHz
16.0 MHz
27 pF
22 pF
27 pF
22 pF
Capacitor values are for design guidance only.
Different capacitor values may be required to produce
acceptable oscillator operation. The user should test
the performance of the oscillator over the expected
VDD and temperature range for the application. Refer
to the following application notes for oscillator-specific
information:
• AN588, “PIC® Microcontroller Oscillator Design
Guide”
• AN826, “Crystal Oscillator Basics and Crystal
Selection for rfPIC® and PIC® Devices”
• AN849, “Basic PIC® Oscillator Design”
• AN943, “Practical PIC® Oscillator Analysis and
Design”
• AN949, “Making Your Oscillator Work”
See the notes following Table 3-2 for additional
information.
Osc Type Crystal
Freq.
Typical Capacitor Values
Tested:
C1 C2
HS 4 MHz 27 pF 27 pF
8 MHz 22 pF 22 pF
20 MHz 15 pF 15 pF
Capacitor values are for design guidance only.
Different capacitor values may be required to produce
acceptable oscillator operation. The user should test
the performance of the oscillator over the expected
VDD and temperature range for the application.
Refer to the Microchip application notes cited in
Table 3-1 for oscillator-specific information. Also see
the notes following this table for additional
information.
Note 1: Higher capacitance increases the
stability of oscillator but also increases
the start-up time.
2: Since each resonator/crystal has its own
characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate values of external
components.
3: Rs may be required to avoid overdriving
crystals with low drive level specification.
4: Always verify oscillator performance over
the VDD and temperature range that is
expected for the application.
Note 1: See Table 3-1 and Table 3-2 for initial values of
C1 and C2.
2: A series resistor (RS) may be required for AT
strip cut crystals.
3: RF varies with the oscillator mode chosen.
C1(1)
C2(1)
XTAL
OSC2
OSC1
RF(3)
Sleep
To
Logic
PIC18F85J90
RS(2)
Internal
PIC18F85J90 FAMILY
DS39770C-page 40 2010 Microchip Technology Inc.
3.4.2 EXTERNAL CLOCK INPUT
(EC MODES)
The EC and ECPLL Oscillator modes require an exter-
nal clock source to be connected to the OSC1 pin.
There is no oscillator start-up time required after a
Power-on Reset or after an exit from Sleep mode.
In the EC Oscillator mode, the oscillator frequency
divided by 4 is available on the OSC2 pin. This signal
may be used for test purposes or to synchronize other
logic. Figure 3-3 shows the pin connections for the EC
Oscillator mode.
FIGURE 3-3: EXTERNAL CLOCK
INPUT OPERATION
(EC CONFIGURATION)
An external clock source may also be connected to the
OSC1 pin in the HS mode, as shown in Figure 3-4. In
this configuration, the divide-by-4 output on OSC2 is
not available.
FIGURE 3-4: EXTERNAL CLOCK INPUT
OPERATION (HS OSC
CONFIGURATION)
3.4.3 PLL FREQUENCY MULTIPLIER
A Phase Locked Loop (PLL) circuit is provided as an
option for users who want to use a lower frequency
oscillator circuit, or to clock the device up to its highest
rated frequency from a crystal oscillator. This may be
useful for customers who are concerned with EMI due
to high-frequency crystals, or users who require higher
clock speeds from an internal oscillator. For these
reasons, the HSPLL and ECPLL modes are available.
The HSPLL and ECPLL modes provide the ability to
selectively run the device at 4 times the external oscil-
lating source to produce frequencies up to 40 MHz.
The PLL is enabled by programming the FOSC<2:0>
Configuration bits (CONFIG2L<2:0>) to either ‘110’
(for ECPLL) or ‘100’ (for HSPLL). In addition, the
PLLEN bit (OSCTUNE<6>) must also be set. Clearing
PLLEN disables the PLL, regardless of the chosen
oscillator configuration. It also allows additional flexibil-
ity for controlling the application’s clock speed in
software.
FIGURE 3-5: PLL BLOCK DIAGRAM
OSC1/CLKI
OSC2/CLKO
FOSC/4
Clock from
Ext. System PIC18F85J90
or RA6
OSC1
OSC2
Open
Clock from
Ext. System PIC18F85J90
(HS Mode)
MUX
VCO
Loop
Filter
OSC2
OSC1
PLL Enable (OSCTUNE)
FIN
FOUT
SYSCLK
Phase
Comparator
HSPLL or ECPLL (CONFIG2L)
4
HS or EC
Mode
2010 Microchip Technology Inc. DS39770C-page 41
PIC18F85J90 FAMILY
3.5 Internal Oscillator Block
The PIC18F85J90 family of devices includes an internal
oscillator block which generates two different clock
signals; either can be used as the microcontroller’s clock
source. This may eliminate the need for an external
oscillator circuit on the OSC1 and/or OSC2 pins.
The main output is the Fast RC oscillator, or INTOSC,
an 8 MHz clock source which can be used to directly
drive the device clock. It also drives a postscaler, which
can provide a range of clock frequencies from 31 kHz
to 4 MHz. INTOSC is enabled when a clock frequency
from 125 kHz to 8 MHz is selected. The INTOSC out-
put can also be enabled when 31 kHz is selected,
depending on the INTSRC bit (OSCTUNE<7>).
The other clock source is the Internal RC oscillator
(INTRC), which provides a nominal 31 kHz output.
INTRC is enabled if it is selected as the device clock
source. It is also enabled automatically when any of the
following are enabled:
• Power-up Timer
• Fail-Safe Clock Monitor
• Watchdog Timer
• Two-Speed Start-up
These features are discussed in greater detail in
Section 23.0 “Special Features of the CPU”.
The clock source frequency (INTOSC direct, INTOSC
with postscaler or INTRC direct) is selected by config-
uring the IRCF bits of the OSCCON register. The
default frequency on device Resets is 1 MHz.
3.5.1 OSC1 AND OSC2 PIN
CONFIGURATION
Whenever the internal oscillator is configured as the
default clock source (FOSC2 = 0), the OSC1 and OSC2
pins are reconfigured automatically as port pins, RA6
and RA7. In this mode, they function as general digital
I/O. All oscillator functions on the pins are disabled.
3.5.2 INTERNAL OSCILLATOR OUTPUT
FREQUENCY AND TUNING
The internal oscillator block is calibrated at the factory
to produce an INTOSC output frequency of 8 MHz. It
can be adjusted in the user’s application by writing to
TUN<5:0> (OSCTUNE<5:0>) in the OSCTUNE
register (Register 3-2).
When the OSCTUNE register is modified, the INTOSC
frequency will begin shifting to the new frequency. The
oscillator will stabilize within 1 ms. Code execution
continues during this shift. There is no indication that
the shift has occurred.
The INTRC oscillator operates independently of the
INTOSC source. Any changes in INTOSC across
voltage and temperature are not necessarily reflected
by changes in INTRC or vice versa. The frequency of
INTRC is not affected by OSCTUNE.
3.5.3 INTOSC FREQUENCY DRIFT
The INTOSC frequency may drift as VDD or tempera-
ture changes, and can affect the controller operation in
a variety of ways. It is possible to adjust the INTOSC
frequency by modifying the value in the OSCTUNE
register. This will have no effect on the INTRC clock
source frequency.
Tuning INTOSC requires knowing when to make the
adjustment, in which direction it should be made and in
some cases, how large a change is needed. Three
compensation techniques are shown here.
3.5.3.1 Compensating with the EUSART
An adjustment may be required when the EUSART
begins to generate framing errors or receives data with
errors while in Asynchronous mode. Framing errors
indicate that the device clock frequency is too high. To
adjust for this, decrement the value in OSCTUNE to
reduce the clock frequency. On the other hand, errors
in data may suggest that the clock speed is too low. To
compensate, increment OSCTUNE to increase the
clock frequency.
3.5.3.2 Compensating with the Timers
This technique compares device clock speed to some
reference clock. Two timers may be used; one timer is
clocked by the peripheral clock, while the other is
clocked by a fixed reference source, such as the
Timer1 oscillator.
Both timers are cleared, but the timer clocked by the
reference generates interrupts. When an interrupt
occurs, the internally clocked timer is read and both
timers are cleared. If the internally clocked timer value
is much greater than expected, then the internal
oscillator block is running too fast. To adjust for this,
decrement the OSCTUNE register.
3.5.3.3 Compensating with the CCP Module
in Capture Mode
A CCP module can use free-running Timer1 (or
Timer3), clocked by the internal oscillator block and an
external event with a known period (i.e., AC power
frequency). The time of the first event is captured in the
CCPRxH:CCPRxL registers and is recorded for use
later. When the second event causes a capture, the
time of the first event is subtracted from the time of the
second event. Since the period of the external event is
known, the time difference between events can be
calculated.
If the measured time is much greater than the
calculated time, the internal oscillator block is running
too fast. To compensate, decrement the OSCTUNE
register. If the measured time is much less than the
calculated time, the internal oscillator block is running
too slow. To compensate, increment the OSCTUNE
register.
PIC18F85J90 FAMILY
DS39770C-page 42 2010 Microchip Technology Inc.
3.6 Effects of Power-Managed Modes
on the Various Clock Sources
When PRI_IDLE mode is selected, the designated pri-
mary oscillator continues to run without interruption.
For all other power-managed modes, the oscillator
using the OSC1 pin is disabled. The OSC1 pin (and
OSC2 pin if used by the oscillator) will stop oscillating.
In secondary clock modes (SEC_RUN and
SEC_IDLE), the Timer1 oscillator is operating and
providing the device clock. The Timer1 oscillator may
also run in all power-managed modes if required to
clock Timer1 or Timer3.
In RC_RUN and RC_IDLE modes, the internal oscilla-
tor provides the device clock source. The 31 kHz
INTRC output can be used directly to provide the clock
and may be enabled to support various special
features, regardless of the power-managed mode (see
Section 23.2 “Watchdog Timer (WDT)” through
Section 23.5 “Fail-Safe Clock Monitor” for more
information on WDT, Fail-Safe Clock Monitor and
Two-Speed Start-up).
If the Sleep mode is selected, all clock sources are
stopped. Since all the transistor switching currents
have been stopped, Sleep mode achieves the lowest
current consumption of the device (only leakage
currents).
Enabling any on-chip feature that will operate during
Sleep will increase the current consumed during Sleep.
The INTRC is required to support WDT operation. The
Timer1 oscillator may be operating to support a Real-
Time Clock. Other features may be operating that do
not require a device clock source (i.e., MSSP slave,
PSP, INTx pins and others). Peripherals that may add
significant current consumption are listed in
Section 26.2 “DC Characteristics: Power-Down and
Supply Current”.
3.7 Power-up Delays
Power-up delays are controlled by two timers, so that
no external Reset circuitry is required for most applica-
tions. The delays ensure that the device is kept in
Reset until the device power supply is stable under nor-
mal circumstances and the primary clock is operating
and stable. For additional information on power-up
delays, see Section 5.6 “Power-up Timer (PWRT)”.
The first timer is the Power-up Timer (PWRT), which
provides a fixed delay on power-up (parameter 33,
Table 26-11). It is always enabled.
The second timer is the Oscillator Start-up Timer
(OST), intended to keep the chip in Reset until the
crystal oscillator is stable (HS modes). The OST does
this by counting 1024 oscillator cycles before allowing
the oscillator to clock the device.
There is a delay of interval TCSD (parameter 38,
Table 26-11), following POR, while the controller
becomes ready to execute instructions.
TABLE 3-3: OSC1 AND OSC2 PIN STATES IN SLEEP MODE
Oscillator Mode OSC1 Pin OSC2 Pin
EC, ECPLL Floating, pulled by external clock At logic low (clock/4 output)
HS, HSPLL Feedback inverter disabled at quiescent
voltage level
Feedback inverter disabled at quiescent
voltage level
INTOSC I/O pin, RA6, direction controlled by
TRISA<6>
I/O pin, RA7, direction controlled by
TRISA<7>
Note: See Table 5-2 in Section 5.0 “Reset” for time-outs due to Sleep and MCLR Reset.
2010 Microchip Technology Inc. DS39770C-page 43
PIC18F85J90 FAMILY
4.0 POWER-MANAGED MODES
The PIC18F85J90 family devices provide the ability to
manage power consumption by simply managing clock-
ing to the CPU and the peripherals. In general, a lower
clock frequency and a reduction in the number of circuits
being clocked constitutes lower consumed power. For
the sake of managing power in an application, there are
three primary modes of operation:
• Run mode
• Idle mode
• Sleep mode
These modes define which portions of the device are
clocked and at what speed. The Run and Idle modes
may use any of the three available clock sources
(primary, secondary or internal oscillator block); the
Sleep mode does not use a clock source.
The power-managed modes include several
power-saving features offered on previous PIC®
devices. One is the clock switching feature, offered in
other PIC18 devices, allowing the controller to use the
Timer1 oscillator in place of the primary oscillator. Also
included is the Sleep mode, offered by all PIC devices,
where all device clocks are stopped.
4.1 Selecting Power-Managed Modes
Selecting a power-managed mode requires two
decisions: if the CPU is to be clocked or not and which
clock source is to be used. The IDLEN bit
(OSCCON<7>) controls CPU clocking, while the
SCS<1:0> bits (OSCCON<1:0>) select the clock
source. The individual modes, bit settings, clock
sources and affected modules are summarized in
Table 4-1.
4.1.1 CLOCK SOURCES
The SCS<1:0> bits allow the selection of one of three
clock sources for power-managed modes. They are:
• the primary clock, as defined by the FOSC<2:0>
Configuration bits
• the secondary clock (Timer1 oscillator)
• the internal oscillator
4.1.2 ENTERING POWER-MANAGED
MODES
Switching from one power-managed mode to another
begins by loading the OSCCON register. The
SCS<1:0> bits select the clock source and determine
which Run or Idle mode is to be used. Changing these
bits causes an immediate switch to the new clock
source, assuming that it is running. The switch may
also be subject to clock transition delays. These are
discussed in Section 4.1.3 “Clock Transitions and
Status Indicators” and subsequent sections.
Entry to the power-managed Idle or Sleep modes is
triggered by the execution of a SLEEP instruction. The
actual mode that results depends on the status of the
IDLEN bit.
Depending on the current mode and the mode being
switched to, a change to a power-managed mode does
not always require setting all of these bits. Many
transitions may be done by changing the oscillator
select bits, or changing the IDLEN bit, prior to issuing a
SLEEP instruction. If the IDLEN bit is already
configured correctly, it may only be necessary to
perform a SLEEP instruction to switch to the desired
mode.
TABLE 4-1: POWER-MANAGED MODES
Mode
OSCCON bits Module Clocking
Available Clock and Oscillator Source
IDLEN<7>(1) SCS<1:0> CPU Peripherals
Sleep 0N/A Off Off None – All clocks are disabled
PRI_RUN N/A 10 Clocked Clocked Primary – HS, EC, HSPLL, ECPLL;
this is the normal full-power execution mode
SEC_RUN N/A 01 Clocked Clocked Secondary – Timer1 Oscillator
RC_RUN N/A 11 Clocked Clocked Internal Oscillator
PRI_IDLE 110Off Clocked Primary – HS, EC, HSPLL, ECPLL
SEC_IDLE 101Off Clocked Secondary – Timer1 Oscillator
RC_IDLE 111Off Clocked Internal Oscillator
Note 1: IDLEN reflects its value when the SLEEP instruction is executed.
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DS39770C-page 44 2010 Microchip Technology Inc.
4.1.3 CLOCK TRANSITIONS AND STATUS
INDICATORS
The length of the transition between clock sources is
the sum of two cycles of the old clock source and three
to four cycles of the new clock source. This formula
assumes that the new clock source is stable.
Two bits indicate the current clock source and its
status: OSTS (OSCCON<3>) and T1RUN
(T1CON<6>). In general, only one of these bits will be
set while in a given power-managed mode. When the
OSTS bit is set, the primary clock is providing the
device clock. When the T1RUN bit is set, the Timer1
oscillator is providing the clock. If neither of these bits
is set, INTRC is clocking the device.
4.1.4 MULTIPLE SLEEP COMMANDS
The power-managed mode that is invoked with the
SLEEP instruction is determined by the setting of the
IDLEN bit at the time the instruction is executed. If
another SLEEP instruction is executed, the device will
enter the power-managed mode specified by IDLEN at
that time. If IDLEN has changed, the device will enter
the new power-managed mode specified by the new
setting.
4.2 Run Modes
In the Run modes, clocks to both the core and
peripherals are active. The difference between these
modes is the clock source.
4.2.1 PRI_RUN MODE
The PRI_RUN mode is the normal, full-power execu-
tion mode of the microcontroller. This is also the default
mode upon a device Reset unless Two-Speed Start-up
is enabled (see Section 23.4 “Two-Speed Start-up”
for details). In this mode, the OSTS bit is set (see
Section 3.2 “Control Registers”).
4.2.2 SEC_RUN MODE
The SEC_RUN mode is the compatible mode to the
“clock switching” feature offered in other PIC18
devices. In this mode, the CPU and peripherals are
clocked from the Timer1 oscillator. This gives users the
option of lower power consumption while still using a
high-accuracy clock source.
SEC_RUN mode is entered by setting the SCS<1:0>
bits to ‘01’. The device clock source is switched to the
Timer1 oscillator (see Figure 4-1), the primary oscilla-
tor is shut down, the T1RUN bit (T1CON<6>) is set and
the OSTS bit is cleared.
Note: Executing a SLEEP instruction does not
necessarily place the device into Sleep
mode. It acts as the trigger to place the
controller into either the Sleep mode, or
one of the Idle modes, depending on the
setting of the IDLEN bit.
2010 Microchip Technology Inc. DS39770C-page 45
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On transitions from SEC_RUN mode to PRI_RUN
mode, the peripherals and CPU continue to be clocked
from the Timer1 oscillator while the primary clock is
started. When the primary clock becomes ready, a
clock switch back to the primary clock occurs (see
Figure 4-2). When the clock switch is complete, the
T1RUN bit is cleared, the OSTS bit is set and the
primary clock is providing the clock. The IDLEN and
SCS bits are not affected by the wake-up; the Timer1
oscillator continues to run.
FIGURE 4-1: TRANSITION TIMING FOR ENTRY TO SEC_RUN MODE
FIGURE 4-2: TRANSITION TIMING FROM SEC_RUN MODE TO PRI_RUN MODE (HSPLL)
Note: The Timer1 oscillator should already be
running prior to entering SEC_RUN mode.
If the T1OSCEN bit is not set when the
SCS<1:0> bits are set to ‘01’, entry to
SEC_RUN mode will not occur. If the
Timer1 oscillator is enabled, but not yet
running, device clocks will be delayed until
the oscillator has started. In such situa-
tions, initial oscillator operation is far from
stable and unpredictable operation may
result.
Q4Q3Q2
OSC1
Peripheral
Program
Q1
T1OSI
Q1
Counter
Clock
CPU
Clock
PC + 2PC
123
n-1
n
Clock Transition
Q4Q3Q2 Q1 Q3Q2
PC + 4
Q1 Q3 Q4
OSC1
Peripheral
Program PC
T1OSI
PLL Clock
Q1
PC + 4
Q2
Output
Q3 Q4 Q1
CPU Clock
PC + 2
Clock
Counter
Q2 Q2 Q3
Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
SCS<1:0> bits Changed
TPLL(1)
12 n-1n
Clock
OSTS bit Set
Transition
TOST(1)
PIC18F85J90 FAMILY
DS39770C-page 46 2010 Microchip Technology Inc.
4.2.3 RC_RUN MODE
In RC_RUN mode, the CPU and peripherals are
clocked from the internal oscillator; the primary clock is
shut down. This mode provides the best power conser-
vation of all the Run modes while still executing code.
It works well for user applications which are not highly
timing-sensitive or do not require high-speed clocks at
all times.
This mode is entered by setting the SCS bits to ‘11’.
When the clock source is switched to the INTRC (see
Figure 4-3), the primary oscillator is shut down and the
OSTS bit is cleared.
On transitions from RC_RUN mode to PRI_RUN mode,
the device continues to be clocked from the INTRC
while the primary clock is started. When the primary
clock becomes ready, a clock switch to the primary
clock occurs (see Figure 4-4). When the clock switch is
complete, the OSTS bit is set and the primary clock is
providing the device clock. The IDLEN and SCS bits
are not affected by the switch. The INTRC source will
continue to run if either the WDT or the Fail-Safe Clock
Monitor is enabled.
FIGURE 4-3: TRANSITION TIMING TO RC_RUN MODE
FIGURE 4-4: TRANSITION TIMING FROM RC_RUN MODE TO PRI_RUN MODE
Q4Q3Q2
OSC1
Peripheral
Program
Q1
INTRC
Q1
Counter
Clock
CPU
Clock
PC + 2PC
123 n-1n
Clock Transition
Q4Q3Q2 Q1 Q3Q2
PC + 4
Q1 Q3 Q4
OSC1
Peripheral
Program PC
INTRC
PLL Clock
Q1
PC + 4
Q2
Output
Q3 Q4 Q1
CPU Clock
PC + 2
Clock
Counter
Q2 Q2 Q3
Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
SCS<1:0> bits Changed
TPLL(1)
12 n-1n
Clock
OSTS bit Set
Transition
TOST(1)
2010 Microchip Technology Inc. DS39770C-page 47
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4.3 Sleep Mode
The power-managed Sleep mode is identical to the leg-
acy Sleep mode offered in all other PIC devices. It is
entered by clearing the IDLEN bit (the default state on
device Reset) and executing the SLEEP instruction.
This shuts down the selected oscillator (Figure 4-5). All
clock source status bits are cleared.
Entering the Sleep mode from any other mode does not
require a clock switch. This is because no clocks are
needed once the controller has entered Sleep. If the
WDT is selected, the INTRC source will continue to
operate. If the Timer1 oscillator is enabled, it will also
continue to run.
When a wake event occurs in Sleep mode (by interrupt,
Reset or WDT time-out), the device will not be clocked
until the clock source selected by the SCS<1:0> bits
becomes ready (see Figure 4-6), or it will be clocked
from the internal oscillator if either the Two-Speed
Start-up or the Fail-Safe Clock Monitor are enabled
(see Section 23.0 “Special Features of the CPU”). In
either case, the OSTS bit is set when the primary clock
is providing the device clocks. The IDLEN and SCS bits
are not affected by the wake-up.
4.4 Idle Modes
The Idle modes allow the controller’s CPU to be
selectively shut down while the peripherals continue to
operate. Selecting a particular Idle mode allows users
to further manage power consumption.
If the IDLEN bit is set to a ‘1’ when a SLEEP instruction is
executed, the peripherals will be clocked from the clock
source selected using the SCS<1:0> bits; however, the
CPU will not be clocked. The clock source status bits are
not affected. Setting IDLEN and executing a SLEEP
instruction provides a quick method of switching from a
given Run mode to its corresponding Idle mode.
If the WDT is selected, the INTRC source will continue
to operate. If the Timer1 oscillator is enabled, it will also
continue to run.
Since the CPU is not executing instructions, the only
exits from any of the Idle modes are by interrupt, WDT
time-out or a Reset. When a wake event occurs, CPU
execution is delayed by an interval of T
CSD
(parameter 38, Table 26-11) while it becomes ready to
execute code. When the CPU begins executing code,
it resumes with the same clock source for the current
Idle mode. For example, when waking from RC_IDLE
mode, the internal oscillator block will clock the CPU
and peripherals (in other words, RC_RUN mode). The
IDLEN and SCS bits are not affected by the wake-up.
While in any Idle mode or the Sleep mode, a WDT
time-out will result in a WDT wake-up to the Run mode
currently specified by the SCS<1:0> bits.
FIGURE 4-5: TRANSITION TIMING FOR ENTRY TO SLEEP MODE
FIGURE 4-6: TRANSITION TIMING FOR WAKE FROM SLEEP (HSPLL)
Q4Q3Q2
OSC1
Peripheral
Sleep
Program
Q1Q1
Counter
Clock
CPU
Clock
PC + 2PC
Q3 Q4 Q1 Q2
OSC1
Peripheral
Program PC
PLL Clock
Q3 Q4
Output
CPU Clock
Q1 Q2 Q3 Q4 Q1 Q2
Clock
Counter PC + 6PC + 4
Q1 Q2 Q3 Q4
Wake Event
Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
TOST(1) TPLL(1)
OSTS bit Set
PC + 2
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DS39770C-page 48 2010 Microchip Technology Inc.
4.4.1 PRI_IDLE MODE
This mode is unique among the three low-power Idle
modes, in that it does not disable the primary device
clock. For timing-sensitive applications, this allows for
the fastest resumption of device operation with its more
accurate primary clock source, since the clock source
does not have to “warm up” or transition from another
oscillator.
PRI_IDLE mode is entered from PRI_RUN mode by
setting the IDLEN bit and executing a SLEEP instruc-
tion. If the device is in another Run mode, set IDLEN
first, then set the SCS bits to ‘10’ and execute SLEEP.
Although the CPU is disabled, the peripherals continue
to be clocked from the primary clock source specified
by the FOSC<1:0> Configuration bits. The OSTS bit
remains set (see Figure 4-7).
When a wake event occurs, the CPU is clocked from the
primary clock source. A delay of interval TCSD is
required between the wake event and when code exe-
cution starts. This is required to allow the CPU to
become ready to execute instructions. After the
wake-up, the OSTS bit remains set. The IDLEN and
SCS bits are not affected by the wake-up (see
Figure 4-8).
4.4.2 SEC_IDLE MODE
In SEC_IDLE mode, the CPU is disabled but the
peripherals continue to be clocked from the Timer1
oscillator. This mode is entered from SEC_RUN by set-
ting the IDLEN bit and executing a SLEEP instruction. If
the device is in another Run mode, set IDLEN first, then
set SCS<1:0> to ‘01’ and execute SLEEP. When the
clock source is switched to the Timer1 oscillator, the
primary oscillator is shut down, the OSTS bit is cleared
and the T1RUN bit is set.
When a wake event occurs, the peripherals continue to
be clocked from the Timer1 oscillator. After an interval
of TCSD following the wake event, the CPU begins exe-
cuting code being clocked by the Timer1 oscillator. The
IDLEN and SCS bits are not affected by the wake-up;
the Timer1 oscillator continues to run (see Figure 4-8).
FIGURE 4-7: TRANSITION TIMING FOR ENTRY TO IDLE MODE
FIGURE 4-8: TRANSITION TIMING FOR WAKE FROM IDLE TO RUN MODE
Note: The Timer1 oscillator should already be
running prior to entering SEC_IDLE mode.
If the T1OSCEN bit is not set when the
SLEEP instruction is executed, the SLEEP
instruction will be ignored and entry to
SEC_IDLE mode will not occur. If the
Timer1 oscillator is enabled, but not yet
running, peripheral clocks will be delayed
until the oscillator has started. In such
situations, initial oscillator operation is far
from stable and unpredictable operation
may result.
Q1
Peripheral
Program PC PC + 2
OSC1
Q3 Q4 Q1
CPU Clock
Clock
Counter
Q2
OSC1
Peripheral
Program PC
CPU Clock
Q1 Q3 Q4
Clock
Counter
Q2
Wake Event
TCSD
2010 Microchip Technology Inc. DS39770C-page 49
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4.4.3 RC_IDLE MODE
In RC_IDLE mode, the CPU is disabled but the periph-
erals continue to be clocked from the internal oscillator.
This mode allows for controllable power conservation
during Idle periods.
From RC_RUN, this mode is entered by setting the
IDLEN bit and executing a SLEEP instruction. If the
device is in another Run mode, first set IDLEN, then
clear the SCS bits and execute SLEEP. When the clock
source is switched to the INTRC, the primary oscillator
is shut down and the OSTS bit is cleared.
When a wake event occurs, the peripherals continue to
be clocked from the INTOSC. After a delay of T
CSD,
following the wake event, the CPU begins executing
code being clocked by the INTOSC. The IDLEN and
SCS bits are not affected by the wake-up. The INTOSC
source will continue to run if either the WDT or the
Fail-Safe Clock Monitor is enabled.
4.5 Exiting Idle and Sleep Modes
An exit from Sleep mode, or any of the Idle modes, is
triggered by an interrupt, a Reset or a WDT time-out.
This section discusses the triggers that cause exits
from power-managed modes. The clocking subsystem
actions are discussed in each of the power-managed
mode sections (see Section 4.2 “Run Modes”,
Section 4.3 “Sleep Mode” and Section 4.4 “Idle
Modes”).
4.5.1 EXIT BY INTERRUPT
Any of the available interrupt sources can cause the
device to exit from an Idle mode, or the Sleep mode, to
a Run mode. To enable this functionality, an interrupt
source must be enabled by setting its enable bit in one
of the INTCON or PIE registers. The exit sequence is
initiated when the corresponding interrupt flag bit is set.
On all exits from Idle or Sleep modes by interrupt, code
execution branches to the interrupt vector if the
GIE/GIEH bit (INTCON<7>) is set. Otherwise, code
execution continues or resumes without branching
(see Section 9.0 “Interrupts”).
A fixed delay of interval TCSD, following the wake event,
is required when leaving Sleep and Idle modes. This
delay is required for the CPU to prepare for execution.
Instruction execution resumes on the first clock cycle
following this delay.
4.5.2 EXIT BY WDT TIME-OUT
A WDT time-out will cause different actions depending
on which power-managed mode the device is in when
the time-out occurs.
If the device is not executing code (all Idle modes and
Sleep mode), the time-out will result in an exit from the
power-managed mode (see Section 4.2 “Run
Modes” and Section 4.3 “Sleep Mode”). If the device
is executing code (all Run modes), the time-out will
result in a WDT Reset (see Section 23.2 “Watchdog
Timer (WDT)”).
The Watchdog Timer and postscaler are cleared by one
of the following events:
• executing a SLEEP or CLRWDT instruction
• the loss of a currently selected clock source (if the
Fail-Safe Clock Monitor is enabled)
4.5.3 EXIT BY RESET
Exiting an Idle or Sleep mode by Reset automatically
forces the device to run from the INTRC.
4.5.4 EXIT WITHOUT AN OSCILLATOR
START-UP DELAY
Certain exits from power-managed modes do not
invoke the OST at all. There are two cases:
• PRI_IDLE mode, where the primary clock source
is not stopped; and
• the primary clock source is either the EC or
ECPLL mode.
In these instances, the primary clock source either
does not require an oscillator start-up delay, since it is
already running (PRI_IDLE), or normally does not
require an oscillator start-up delay (EC). However, a
fixed delay of interval T
CSD, following the wake event,
is still required when leaving Sleep and Idle modes to
allow the CPU to prepare for execution. Instruction
execution resumes on the first clock cycle following this
delay.
PIC18F85J90 FAMILY
DS39770C-page 50 2010 Microchip Technology Inc.
NOTES:
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PIC18F85J90 FAMILY
5.0 RESET
The PIC18F85J90 family of devices differentiate
between various kinds of Reset:
a) Power-on Reset (POR)
b) MCLR Reset during normal operation
c) MCLR Reset during power-managed modes
d) Watchdog Timer (WDT) Reset (during
execution)
e) Brown-out Reset (BOR)
f) RESET Instruction
g) Stack Full Reset
h) Stack Underflow Reset
This section discusses Resets generated by MCLR,
POR and BOR, and covers the operation of the various
start-up timers. Stack Reset events are covered in
Section 6.1.4.4 “Stack Full and Underflow Resets”.
WDT Resets are covered in Section 23.2 “Watchdog
Timer (WDT)”.
A simplified block diagram of the on-chip Reset circuit
is shown in Figure 5-1.
5.1 RCON Register
Device Reset events are tracked through the RCON
register (Register 5-1). The lower five bits of the
register indicate that a specific Reset event has
occurred. In most cases, these bits can only be set by
the event and must be cleared by the application after
the event. The state of these flag bits, taken together,
can be read to indicate the type of Reset that just
occurred. This is described in more detail in
Section 5.7 “Reset State of Registers”.
The RCON register also has a control bit for setting
interrupt priority (IPEN). Interrupt priority is discussed
in Section 9.0 “Interrupts”.
FIGURE 5-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
S
RQ
External Reset
MCLR
VDD
WDT
Time-out
VDD Rise
Detect
PWRT
INTRC
POR Pulse
PWRT Chip_Reset
11-Bit Ripple Counter
Brown-out
Reset(1)
RESET
Instruction
Stack
Pointer
Stack Full/Underflow Reset
Sleep
( )_IDLE
65.5 ms
32 s
Note 1: The ENVREG pin must be tied high to enable Brown-out Reset. The Brown-out Reset is provided by the on-chip
voltage regulator when there is insufficient source voltage to maintain regulation.
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DS39770C-page 52 2010 Microchip Technology Inc.
REGISTER 5-1: RCON: RESET CONTROL REGISTER
R/W-0 U-0 R/W-1 R/W-1 R-1 R-1 R/W-0 R/W-0
IPEN —CMRI TO PD POR BOR
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 IPEN: Interrupt Priority Enable bit
1 = Enable priority levels on interrupts
0 = Disable priority levels on interrupts (PIC16XXXX Compatibility mode)
bit 6 Unimplemented: Read as ‘0’
bit 5 CM: Configuration Mismatch Flag bit
1 = A Configuration Mismatch Reset has not occurred
0 = A Configuration Mismatch Reset occurred. Must be set in software once the Reset occurs.
bit 4 RI: RESET Instruction Flag bit
1 =The RESET instruction was not executed (set by firmware only)
0 =The RESET instruction was executed causing a device Reset (must be set in software after a
Brown-out Reset occurs)
bit 3 TO: Watchdog Time-out Flag bit
1 = Set by power-up, CLRWDT instruction or SLEEP instruction
0 = A WDT time-out occurred
bit 2 PD: Power-Down Detection Flag bit
1 = Set by power-up or by the CLRWDT instruction
0 = Set by execution of the SLEEP instruction
bit 1 POR: Power-on Reset Status bit
1 = A Power-on Reset has not occurred (set by firmware only)
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0 BOR: Brown-out Reset Status bit
1 = A Brown-out Reset has not occurred (set by firmware only)
0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
Note 1: It is recommended that the POR bit be set after a Power-on Reset has been detected, so that subsequent
Power-on Resets may be detected.
2: If the on-chip voltage regulator is disabled, BOR remains ‘0’ at all times. See Section 5.4.1 “Detecting
BOR” for more information.
3: Brown-out Reset is said to have occurred when BOR is ‘0’ and POR is ‘1’ (assuming that POR was set to
‘1’ by software immediately after a Power-on Reset).
2010 Microchip Technology Inc. DS39770C-page 53
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5.2 Master Clear (MCLR)
The MCLR pin provides a method for triggering a hard
external Reset of the device. A Reset is generated by
holding the pin low. PIC18 extended microcontroller
devices have a noise filter in the MCLR Reset path
which detects and ignores small pulses.
The MCLR pin is not driven low by any internal Resets,
including the WDT.
5.3 Power-on Reset (POR)
A Power-on Reset condition is generated on-chip
whenever VDD rises above a certain threshold. This
allows the device to start in the initialized state when
VDD is adequate for operation.
To take advantage of the POR circuitry, tie the MCLR
pin through a resistor (1 k to 10 k) to VDD. This will
eliminate external RC components usually needed to
create a Power-on Reset delay. A minimum rise rate for
VDD is specified (parameter D004). For a slow rise
time, see Figure 5-2.
When the device starts normal operation (i.e., exits the
Reset condition), device operating parameters
(voltage, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in Reset until the operating
conditions are met.
Power-on Reset events are captured by the POR bit
(RCON<1>). The state of the bit is set to ‘0’ whenever
a Power-on Reset occurs; it does not change for any
other Reset event. POR is not reset to ‘1’ by any
hardware event. To capture multiple events, the user
manually resets the bit to ‘1’ in software following any
Power-on Reset.
5.4 Brown-out Reset (BOR)
The PIC18F85J90 family of devices incorporates a
simple BOR function when the internal regulator is
enabled (ENVREG pin is tied to VDD). The voltage reg-
ulator will trigger a Brown-out Reset when output of the
regulator to the device core approaches the voltage at
which the device is unable to run at full speed. The
BOR circuit also keeps the device in Reset as VDD
rises, until the regulator’s output level is sufficient for
full-speed operation.
Once a BOR has occurred, the Power-up Timer will
keep the chip in Reset for TPWRT (parameter 33). If
VDD drops below the threshold for full-speed operation
while the Power-up Timer is running, the chip will go
back into a Brown-out Reset and the Power-up Timer
will be initialized. Once VDD rises to the point where
regulator output is sufficient, the Power-up Timer will
execute the additional time delay.
FIGURE 5-2: EXTERNAL POWER-ON
RESET CIRCUIT (FOR
SLOW VDD POWER-UP)
5.4.1 DETECTING BOR
The BOR bit always resets to ‘0’ on any Brown-out
Reset or Power-on Reset event. This makes it difficult
to determine if a Brown-out Reset event has occurred
just by reading the state of BOR alone. A more reliable
method is to simultaneously check the state of both
POR and BOR. This assumes that the POR bit is reset
to ‘1’ in software immediately after any Power-on Reset
event. If BOR is ‘0’ while POR is ‘1’, it can be reliably
assumed that a Brown-out Reset event has occurred.
If the voltage regulator is disabled, Brown-out Reset
functionality is disabled. In this case, the BOR bit
cannot be used to determine a Brown-out Reset event.
The BOR bit is still cleared by a Power-on Reset event.
5.5 Configuration Mismatch (CM)
The Configuration Mismatch (CM) Reset register is
designed to detect and attempt to recover from
random, memory corrupting events. This includes
Electrostatic Discharge (ESD) events which can cause
widespread, single bit changes throughout the device
and result in catastrophic failure.
In PIC18FXXXX Flash devices, the device Configura-
tion registers (located in the configuration memory
space) are continuously monitored during operation by
comparing their values to complimentary shadow reg-
isters. If a mismatch is detected between the two sets
of registers, a CM Reset automatically occurs.
These events are captured by the CM bit (RCON<5>).
Whenever a CM event occurs, this bit is set to ‘0’. For
any other Reset event, this bit does not change.
Note 1: External Power-on Reset circuit is required
only if the VDD power-up slope is too slow.
The diode D helps discharge the capacitor
quickly when VDD powers down.
2: R < 40 k is recommended to make sure that
the voltage drop across R does not violate
the device’s electrical specification.
3: R1 1 k will limit any current flowing into
MCLR from external capacitor C, in the event
of MCLR/VPP pin breakdown, due to
Electrostatic Discharge (ESD) or Electrical
Overstress (EOS).
C
R1
R
D
VDD
MCLR
PIC18F85J90
VDD
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DS39770C-page 54 2010 Microchip Technology Inc.
A CM Reset behaves similarly to a Master Clear Reset,
RESET instruction, WDT time-out or Stack Event
Resets. As with all hard and power Reset events, the
device Configuration Words are reloaded from the
Flash Configuration Words in program memory as the
device restarts.
5.6 Power-up Timer (PWRT)
PIC18F85J90 family devices incorporate an on-chip
Power-up Timer (PWRT) to help regulate the Power-on
Reset process. The PWRT is always enabled. The
main function is to ensure that the device voltage is
stable before code is executed.
The Power-up Timer (PWRT) of the PIC18F85J90 fam-
ily devices is an 11-bit counter which uses the INTRC
source as the clock input. This yields an approximate
time interval of 2048 x 32 s = 65.6 ms. While the
PWRT is counting, the device is held in Reset.
The power-up time delay depends on the INTRC clock
and will vary from chip-to-chip due to temperature and
process variation. See DC parameter 33 for details.
5.6.1 TIME-OUT SEQUENCE
If enabled, the PWRT time-out is invoked after the POR
pulse has cleared. The total time-out will vary based on
the status of the PWRT. Figure 5-3, Figure 5-4,
Figure 5-5 and Figure 5-6 all depict time-out
sequences on power-up with the Power-up Timer
enabled.
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, the PWRT will expire. Bringing
MCLR high will begin execution immediately
(Figure 5-5). This is useful for testing purposes, or to
synchronize more than one PIC18FXXXX device
operating in parallel.
FIGURE 5-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD, VDD RISE < TPWRT)
FIGURE 5-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
TPWRT
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
INTERNAL RESET
TPWRT
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
INTERNAL RESET
2010 Microchip Technology Inc. DS39770C-page 55
PIC18F85J90 FAMILY
FIGURE 5-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
FIGURE 5-6: SLOW RISE TIME (MCLR TIED TO VDD, VDD RISE > TPWRT)
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
INTERNAL RESET
TPWRT
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
INTERNAL RESET
0V 1V
3.3V
TPWRT
PIC18F85J90 FAMILY
DS39770C-page 56 2010 Microchip Technology Inc.
5.7 Reset State of Registers
Most registers are unaffected by a Reset. Their status
is unknown on POR and unchanged by all other
Resets. The other registers are forced to a “Reset
state” depending on the type of Reset that occurred.
Most registers are not affected by a WDT wake-up,
since this is viewed as the resumption of normal
operation. Status bits from the RCON register, CM, RI,
TO, PD, POR and BOR, are set or cleared differently in
different Reset situations, as indicated in Table 5-1.
These bits are used in software to determine the nature
of the Reset.
Table 5-2 describes the Reset states for all of the
Special Function Registers. These are categorized by
Power-on and Brown-out Resets, Master Clear and
WDT Resets and WDT wake-ups.
TABLE 5-1: STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR
RCON REGISTER
Condition Program
Counter(1)
RCON Register STKPTR Register
CM RI TO PD POR BOR STKFUL STKUNF
Power-on Reset 0000h 1 11100 0 0
RESET Instruction 0000h u 0uuuu u u
Brown-out Reset 0000h 1 111u0 u u
MCLR during
power-managed Run
modes
0000h u u1uuu u u
MCLR during power-
managed Idle modes and
Sleep mode
0000h u u10uu u u
WDT time-out during full
power or power-managed
Run modes
0000h u u0uuu u u
MCLR during full-power
execution
0000h u uuuuu u u
Stack Full Reset
(STVREN = 1)
0000h u uuuuu 1 u
Stack Underflow Reset
(STVREN = 1)
0000h u uuuuu u 1
Stack Underflow Error (not
an actual Reset,
STVREN = 0)
0000h u uuuuu u 1
WDT time-out during
power-managed Idle or
Sleep modes
PC + 2 u u00uu u u
Interrupt exit from
power-managed modes
PC + 2 u uu0uu u u
Legend: u = unchanged
Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bit is set, the PC is loaded with the
interrupt vector (0008h or 0018h).
2010 Microchip Technology Inc. DS39770C-page 57
PIC18F85J90 FAMILY
TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS
Register Applicable Devices Power-on Reset,
Brown-out Reset
MCLR Resets
WDT Reset
RESET Instruction
Stack Resets
CM Resets
Wake-up via WDT
or Interrupt
TOSU PIC18F6XJ90 PIC18F8XJ90 ---0 0000 ---0 0000 ---0 uuuu(1)
TOSH PIC18F6XJ90 PIC18F8XJ90 0000 0000 0000 0000 uuuu uuuu(1)
TOSL PIC18F6XJ90 PIC18F8XJ90 0000 0000 0000 0000 uuuu uuuu(1)
STKPTR PIC18F6XJ90 PIC18F8XJ90 uu-0 0000 00-0 0000 uu-u uuuu(1)
PCLATU PIC18F6XJ90 PIC18F8XJ90 ---0 0000 ---0 0000 ---u uuuu
PCLATH PIC18F6XJ90 PIC18F8XJ90 0000 0000 0000 0000 uuuu uuuu
PCL PIC18F6XJ90 PIC18F8XJ90 0000 0000 0000 0000 PC + 2(2)
TBLPTRU PIC18F6XJ90 PIC18F8XJ90 --00 0000 --00 0000 --uu uuuu
TBLPTRH PIC18F6XJ90 PIC18F8XJ90 0000 0000 0000 0000 uuuu uuuu
TBLPTRL PIC18F6XJ90 PIC18F8XJ90 0000 0000 0000 0000 uuuu uuuu
TABLAT PIC18F6XJ90 PIC18F8XJ90 0000 0000 0000 0000 uuuu uuuu
PRODH PIC18F6XJ90 PIC18F8XJ90 xxxx xxxx uuuu uuuu uuuu uuuu
PRODL PIC18F6XJ90 PIC18F8XJ90 xxxx xxxx uuuu uuuu uuuu uuuu
INTCON PIC18F6XJ90 PIC18F8XJ90 0000 000x 0000 000u uuuu uuuu(3)
INTCON2 PIC18F6XJ90 PIC18F8XJ90 1111 1111 1111 1111 uuuu uuuu(3)
INTCON3 PIC18F6XJ90 PIC18F8XJ90 1100 0000 1100 0000 uuuu uuuu(3)
INDF0 PIC18F6XJ90 PIC18F8XJ90 N/A N/A N/A
POSTINC0 PIC18F6XJ90 PIC18F8XJ90 N/A N/A N/A
POSTDEC0 PIC18F6XJ90 PIC18F8XJ90 N/A N/A N/A
PREINC0 PIC18F6XJ90 PIC18F8XJ90 N/A N/A N/A
PLUSW0 PIC18F6XJ90 PIC18F8XJ90 N/A N/A N/A
FSR0H PIC18F6XJ90 PIC18F8XJ90 ---- xxxx ---- uuuu ---- uuuu
FSR0L PIC18F6XJ90 PIC18F8XJ90 xxxx xxxx uuuu uuuu uuuu uuuu
WREG PIC18F6XJ90 PIC18F8XJ90 xxxx xxxx uuuu uuuu uuuu uuuu
INDF1 PIC18F6XJ90 PIC18F8XJ90 N/A N/A N/A
POSTINC1 PIC18F6XJ90 PIC18F8XJ90 N/A N/A N/A
POSTDEC1 PIC18F6XJ90 PIC18F8XJ90 N/A N/A N/A
PREINC1 PIC18F6XJ90 PIC18F8XJ90 N/A N/A N/A
PLUSW1 PIC18F6XJ90 PIC18F8XJ90 N/A N/A N/A
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
4: See Table 5-1 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When
not enabled as PORTA pins, they are disabled and read as ‘0’.
PIC18F85J90 FAMILY
DS39770C-page 58 2010 Microchip Technology Inc.
FSR1H PIC18F6XJ90 PIC18F8XJ90 ---- xxxx ---- uuuu ---- uuuu
FSR1L PIC18F6XJ90 PIC18F8XJ90 xxxx xxxx uuuu uuuu uuuu uuuu
BSR PIC18F6XJ90 PIC18F8XJ90 ---- 0000 ---- 0000 ---- uuuu
INDF2 PIC18F6XJ90 PIC18F8XJ90 N/A N/A N/A
POSTINC2 PIC18F6XJ90 PIC18F8XJ90 N/A N/A N/A
POSTDEC2 PIC18F6XJ90 PIC18F8XJ90 N/A N/A N/A
PREINC2 PIC18F6XJ90 PIC18F8XJ90 N/A N/A N/A
PLUSW2 PIC18F6XJ90 PIC18F8XJ90 N/A N/A N/A
FSR2H PIC18F6XJ90 PIC18F8XJ90 ---- xxxx ---- uuuu ---- uuuu
FSR2L PIC18F6XJ90 PIC18F8XJ90 xxxx xxxx uuuu uuuu uuuu uuuu
STATUS PIC18F6XJ90 PIC18F8XJ90 ---x xxxx ---u uuuu ---u uuuu
TMR0H PIC18F6XJ90 PIC18F8XJ90 0000 0000 0000 0000 uuuu uuuu
TMR0L PIC18F6XJ90 PIC18F8XJ90 xxxx xxxx uuuu uuuu uuuu uuuu
T0CON PIC18F6XJ90 PIC18F8XJ90 1111 1111 1111 1111 uuuu uuuu
OSCCON PIC18F6XJ90 PIC18F8XJ90 0100 q000 0100 q000 uuuu quuu
LCDREG PIC18F6XJ90 PIC18F8XJ90 -011 1100 -011 1000 -uuu uuuu
WDTCON PIC18F6XJ90 PIC18F8XJ90 0--- ---0 0--- ---0 u--- ---u
RCON(4) PIC18F6XJ90 PIC18F8XJ90 0-11 11q0 0-qq qquu u-uu qquu
TMR1H PIC18F6XJ90 PIC18F8XJ90 xxxx xxxx uuuu uuuu uuuu uuuu
TMR1L PIC18F6XJ90 PIC18F8XJ90 xxxx xxxx uuuu uuuu uuuu uuuu
T1CON PIC18F6XJ90 PIC18F8XJ90 0000 0000 u0uu uuuu uuuu uuuu
TMR2 PIC18F6XJ90 PIC18F8XJ90 0000 0000 0000 0000 uuuu uuuu
PR2 PIC18F6XJ90 PIC18F8XJ90 1111 1111 1111 1111 1111 1111
T2CON PIC18F6XJ90 PIC18F8XJ90 -000 0000 -000 0000 -uuu uuuu
SSPBUF PIC18F6XJ90 PIC18F8XJ90 xxxx xxxx uuuu uuuu uuuu uuuu
SSPADD PIC18F6XJ90 PIC18F8XJ90 0000 0000 0000 0000 uuuu uuuu
SSPSTAT PIC18F6XJ90 PIC18F8XJ90 0000 0000 0000 0000 uuuu uuuu
SSPCON1 PIC18F6XJ90 PIC18F8XJ90 0000 0000 0000 0000 uuuu uuuu
SSPCON2 PIC18F6XJ90 PIC18F8XJ90 0000 0000 0000 0000 uuuu uuuu
TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register Applicable Devices Power-on Reset,
Brown-out Reset
MCLR Resets
WDT Reset
RESET Instruction
Stack Resets
CM Resets
Wake-up via WDT
or Interrupt
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
4: See Table 5-1 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When
not enabled as PORTA pins, they are disabled and read as ‘0’.
2010 Microchip Technology Inc. DS39770C-page 59
PIC18F85J90 FAMILY
ADRESH PIC18F6XJ90 PIC18F8XJ90 xxxx xxxx uuuu uuuu uuuu uuuu
ADRESL PIC18F6XJ90 PIC18F8XJ90 xxxx xxxx uuuu uuuu uuuu uuuu
ADCON0 PIC18F6XJ90 PIC18F8XJ90 0-00 0000 0-00 0000 u-uu uuuu
ADCON1 PIC18F6XJ90 PIC18F8XJ90 --00 0000 --00 0000 --uu uuuu
ADCON2 PIC18F6XJ90 PIC18F8XJ90 0-00 0000 0-00 0000 u-uu uuuu
LCDDATA4 PIC18F6XJ90 PIC18F8XJ90 ---- ---x ---- ---u ---- ---u
LCDDATA4 PIC18F6XJ90 PIC18F8XJ90 xxxx xxxx uuuu uuuu uuuu uuuu
LCDDATA3 PIC18F6XJ90 PIC18F8XJ90 xxxx xxxx uuuu uuuu uuuu uuuu
LCDDATA2 PIC18F6XJ90 PIC18F8XJ90 xxxx xxxx uuuu uuuu uuuu uuuu
LCDDATA1 PIC18F6XJ90 PIC18F8XJ90 xxxx xxxx uuuu uuuu uuuu uuuu
LCDDATA0 PIC18F6XJ90 PIC18F8XJ90 xxxx xxxx uuuu uuuu uuuu uuuu
LCDSE5 PIC18F6XJ90 PIC18F8XJ90 0000 0000 uuuu uuuu uuuu uuuu
LCDSE4 PIC18F6XJ90 PIC18F8XJ90 ---- ---0 ---- ---u ---- ---u
LCDSE4 PIC18F6XJ90 PIC18F8XJ90 0000 0000 uuuu uuuu uuuu uuuu
LCDSE3 PIC18F6XJ90 PIC18F8XJ90 0000 0000 uuuu uuuu uuuu uuuu
LCDSE2 PIC18F6XJ90 PIC18F8XJ90 0000 0000 uuuu uuuu uuuu uuuu
LCDSE1 PIC18F6XJ90 PIC18F8XJ90 0000 0000 uuuu uuuu uuuu uuuu
CVRCON PIC18F6XJ90 PIC18F8XJ90 0000 0000 0000 0000 uuuu uuuu
CMCON PIC18F6XJ90 PIC18F8XJ90 0000 0111 0000 0111 uuuu uuuu
TMR3H PIC18F6XJ90 PIC18F8XJ90 xxxx xxxx uuuu uuuu uuuu uuuu
TMR3L PIC18F6XJ90 PIC18F8XJ90 xxxx xxxx uuuu uuuu uuuu uuuu
T3CON PIC18F6XJ90 PIC18F8XJ90 0000 0000 uuuu uuuu uuuu uuuu
SPBRG1 PIC18F6XJ90 PIC18F8XJ90 0000 0000 0000 0000 uuuu uuuu
RCREG1 PIC18F6XJ90 PIC18F8XJ90 0000 0000 0000 0000 uuuu uuuu
TXREG1 PIC18F6XJ90 PIC18F8XJ90 0000 0000 0000 0000 uuuu uuuu
TXSTA1 PIC18F6XJ90 PIC18F8XJ90 0000 0010 0000 0010 uuuu uuuu
RCSTA1 PIC18F6XJ90 PIC18F8XJ90 0000 000x 0000 000x uuuu uuuu
LCDPS PIC18F6XJ90 PIC18F8XJ90 0000 0000 0000 0000 uuuu uuuu
LCDSE0 PIC18F6XJ90 PIC18F8XJ90 0000 0000 uuuu uuuu uuuu uuuu
LCDCON PIC18F6XJ90 PIC18F8XJ90 000- 0000 000- 0000 uuu- uuuu
EECON2 PIC18F6XJ90 PIC18F8XJ90 ---- ---- ---- ---- ---- ----
EECON1 PIC18F6XJ90 PIC18F8XJ90 ---0 x00- ---0 u00- ---0 u00-
TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register Applicable Devices Power-on Reset,
Brown-out Reset
MCLR Resets
WDT Reset
RESET Instruction
Stack Resets
CM Resets
Wake-up via WDT
or Interrupt
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
4: See Table 5-1 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When
not enabled as PORTA pins, they are disabled and read as ‘0’.
PIC18F85J90 FAMILY
DS39770C-page 60 2010 Microchip Technology Inc.
IPR3 PIC18F6XJ90 PIC18F8XJ90 -111 -11- -111 -11- -uuu -uu-
PIR3 PIC18F6XJ90 PIC18F8XJ90 -000 -00- -000 -00- -uuu -00-(3)
PIE3 PIC18F6XJ90 PIC18F8XJ90 -000 -00- -000 -00- -uuu -00-
IPR2 PIC18F6XJ90 PIC18F8XJ90 11-- 111- 11-- 111- uu-- uuu-
PIR2 PIC18F6XJ90 PIC18F8XJ90 00-- 000- 00-- 000- uu-- uuu-(3)
PIE2 PIC18F6XJ90 PIC18F8XJ90 00-- 000- 00-- 000- uu-- uuu-
IPR1 PIC18F6XJ90 PIC18F8XJ90 -111 1-11 -111 1-11 -uuu u-uu
PIR1 PIC18F6XJ90 PIC18F8XJ90 -000 0-00 -000 0-00 -uuu u-uu(3)
PIE1 PIC18F6XJ90 PIC18F8XJ90 -000 0-00 -000 0-00 -uuu u-uu
OSCTUNE PIC18F6XJ90 PIC18F8XJ90 0000 0000 0000 0000 uuuu uuuu
TRISJ PIC18F6XJ90 PIC18F8XJ90 1111 1111 1111 1111 uuuu uuuu
TRISH PIC18F6XJ90 PIC18F8XJ90 1111 1111 1111 1111 uuuu uuuu
TRISG PIC18F6XJ90 PIC18F8XJ90 0001 1111 0001 1111 uuuu uuuu
TRISF PIC18F6XJ90 PIC18F8XJ90 1111 111- 1111 111- uuuu uuu-
TRISE PIC18F6XJ90 PIC18F8XJ90 1111 1-11 1111 1-11 uuuu u-uu
TRISD PIC18F6XJ90 PIC18F8XJ90 1111 1111 1111 1111 uuuu uuuu
TRISC PIC18F6XJ90 PIC18F8XJ90 1111 1111 1111 1111 uuuu uuuu
TRISB PIC18F6XJ90 PIC18F8XJ90 1111 1111 1111 1111 uuuu uuuu
TRISA(5) PIC18F6XJ90 PIC18F8XJ90 1111 1111(5) 1111 1111(5) uuuu uuuu(5)
LATJ PIC18F6XJ90 PIC18F8XJ90 xxxx xxxx uuuu uuuu uuuu uuuu
LATH PIC18F6XJ90 PIC18F8XJ90 xxxx xxxx uuuu uuuu uuuu uuuu
LATG PIC18F6XJ90 PIC18F8XJ90 00-x xxxx 00-u uuuu uu-u uuuu
LATF PIC18F6XJ90 PIC18F8XJ90 xxxx xxx- uuuu uuu- uuuu uuu-
LATE PIC18F6XJ90 PIC18F8XJ90 xxxx xxxx uuuu uuuu uuuu uuuu
LATD PIC18F6XJ90 PIC18F8XJ90 xxxx xxxx uuuu uuuu uuuu uuuu
LATC PIC18F6XJ90 PIC18F8XJ90 xxxx xxxx uuuu uuuu uuuu uuuu
LATB PIC18F6XJ90 PIC18F8XJ90 xxxx xxxx uuuu uuuu uuuu uuuu
LATA(5) PIC18F6XJ90 PIC18F8XJ90 xxxx xxxx(5) uuuu uuuu(5) uuuu uuuu(5)
PORTJ PIC18F6XJ90 PIC18F8XJ90 xxxx xxxx uuuu uuuu uuuu uuuu
PORTH PIC18F6XJ90 PIC18F8XJ90 xxxx xxxx uuuu uuuu uuuu uuuu
PORTG PIC18F6XJ90 PIC18F8XJ90 000x xxxx 000u uuuu 000u uuuu
PORTF PIC18F6XJ90 PIC18F8XJ90 xxxx xxx- uuuu uuu- uuuu uuu-
TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register Applicable Devices Power-on Reset,
Brown-out Reset
MCLR Resets
WDT Reset
RESET Instruction
Stack Resets
CM Resets
Wake-up via WDT
or Interrupt
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
4: See Table 5-1 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When
not enabled as PORTA pins, they are disabled and read as ‘0’.
2010 Microchip Technology Inc. DS39770C-page 61
PIC18F85J90 FAMILY
PORTE PIC18F6XJ90 PIC18F8XJ90 xxxx x-xx uuuu u-uu uuuu u-uu
PORTD PIC18F6XJ90 PIC18F8XJ90 xxxx xxxx uuuu uuuu uuuu uuuu
PORTC PIC18F6XJ90 PIC18F8XJ90 xxxx xxxx uuuu uuuu uuuu uuuu
PORTB PIC18F6XJ90 PIC18F8XJ90 xxxx xxxx uuuu uuuu uuuu uuuu
PORTA(5) PIC18F6XJ90 PIC18F8XJ90 xx0x 0000(5) uu0u 0000(5) uuuu uuuu(5)
SPBRGH1 PIC18F6XJ90 PIC18F8XJ90 0000 0000 0000 0000 uuuu uuuu
BAUDCON1 PIC18F6XJ90 PIC18F8XJ90 0100 0-00 0100 0-00 uuuu u-uu
LCDDATA23 PIC18F6XJ90 PIC18F8XJ90 xxxx xxxx uuuu uuuu uuuu uuuu
LCDDATA22 PIC18F6XJ90 PIC18F8XJ90 ---- ---x ---- ---u ---- ---u
LCDDATA22 PIC18F6XJ90 PIC18F8XJ90 xxxx xxxx uuuu uuuu uuuu uuuu
LCDDATA21 PIC18F6XJ90 PIC18F8XJ90 xxxx xxxx uuuu uuuu uuuu uuuu
LCDDATA20 PIC18F6XJ90 PIC18F8XJ90 xxxx xxxx uuuu uuuu uuuu uuuu
LCDDATA19 PIC18F6XJ90 PIC18F8XJ90 xxxx xxxx uuuu uuuu uuuu uuuu
LCDDATA18 PIC18F6XJ90 PIC18F8XJ90 xxxx xxxx uuuu uuuu uuuu uuuu
LCDDATA17 PIC18F6XJ90 PIC18F8XJ90 xxxx xxxx uuuu uuuu uuuu uuuu
LCDDATA16 PIC18F6XJ90 PIC18F8XJ90 ---- ---x ---- ---u ---- ---u
LCDDATA16 PIC18F6XJ90 PIC18F8XJ90 xxxx xxxx uuuu uuuu uuuu uuuu
LCDDATA15 PIC18F6XJ90 PIC18F8XJ90 xxxx xxxx uuuu uuuu uuuu uuuu
LCDDATA14 PIC18F6XJ90 PIC18F8XJ90 xxxx xxxx uuuu uuuu uuuu uuuu
LCDDATA13 PIC18F6XJ90 PIC18F8XJ90 xxxx xxxx uuuu uuuu uuuu uuuu
LCDDATA12 PIC18F6XJ90 PIC18F8XJ90 xxxx xxxx uuuu uuuu uuuu uuuu
LCDDATA11 PIC18F6XJ90 PIC18F8XJ90 xxxx xxxx uuuu uuuu uuuu uuuu
LCDDATA10 PIC18F6XJ90 PIC18F8XJ90 ---- ---x ---- ---u ---- ---u
LCDDATA10 PIC18F6XJ90 PIC18F8XJ90 xxxx xxxx uuuu uuuu uuuu uuuu
LCDDATA9 PIC18F6XJ90 PIC18F8XJ90 xxxx xxxx uuuu uuuu uuuu uuuu
LCDDATA8 PIC18F6XJ90 PIC18F8XJ90 xxxx xxxx uuuu uuuu uuuu uuuu
LCDDATA7 PIC18F6XJ90 PIC18F8XJ90 xxxx xxxx uuuu uuuu uuuu uuuu
LCDDATA6 PIC18F6XJ90 PIC18F8XJ90 xxxx xxxx uuuu uuuu uuuu uuuu
LCDDATA5 PIC18F6XJ90 PIC18F8XJ90 xxxx xxxx uuuu uuuu uuuu uuuu
CCPR1H PIC18F6XJ90 PIC18F8XJ90 xxxx xxxx uuuu uuuu uuuu uuuu
CCPR1L PIC18F6XJ90 PIC18F8XJ90 xxxx xxxx uuuu uuuu uuuu uuuu
CCP1CON PIC18F6XJ90 PIC18F8XJ90 --00 0000 --00 0000 --uu uuuu
CCPR2H PIC18F6XJ90 PIC18F8XJ90 xxxx xxxx uuuu uuuu uuuu uuuu
TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register Applicable Devices Power-on Reset,
Brown-out Reset
MCLR Resets
WDT Reset
RESET Instruction
Stack Resets
CM Resets
Wake-up via WDT
or Interrupt
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
4: See Table 5-1 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When
not enabled as PORTA pins, they are disabled and read as ‘0’.
PIC18F85J90 FAMILY
DS39770C-page 62 2010 Microchip Technology Inc.
CCPR2L PIC18F6XJ90 PIC18F8XJ90 xxxx xxxx uuuu uuuu uuuu uuuu
CCP2CON PIC18F6XJ90 PIC18F8XJ90 --00 0000 --00 0000 --uu uuuu
SPBRG2 PIC18F6XJ90 PIC18F8XJ90 0000 0000 0000 0000 uuuu uuuu
RCREG2 PIC18F6XJ90 PIC18F8XJ90 0000 0000 0000 0000 uuuu uuuu
TXREG2 PIC18F6XJ90 PIC18F8XJ90 0000 0000 0000 0000 uuuu uuuu
TXSTA2 PIC18F6XJ90 PIC18F8XJ90 0000 -010 0000 -010 uuuu -uuu
RCSTA2 PIC18F6XJ90 PIC18F8XJ90 0000 000x 0000 000x uuuu uuuu
TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register Applicable Devices Power-on Reset,
Brown-out Reset
MCLR Resets
WDT Reset
RESET Instruction
Stack Resets
CM Resets
Wake-up via WDT
or Interrupt
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
4: See Table 5-1 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When
not enabled as PORTA pins, they are disabled and read as ‘0’.
2010 Microchip Technology Inc. DS39770C-page 63
PIC18F85J90 FAMILY
6.0 MEMORY ORGANIZATION
There are two types of memory in PIC18 Flash
microcontroller devices:
• Program Memory
• Data RAM
As Harvard architecture devices, the data and program
memories use separate busses; this allows for
concurrent access of the two memory spaces.
Additional detailed information on the operation of the
Flash program memory is provided in Section 7.0
“Flash Program Memory”.
6.1 Program Memory Organization
PIC18 microcontrollers implement a 21-bit program
counter which is capable of addressing a 2-Mbyte
program memory space. Accessing a location between
the upper boundary of the physically implemented
memory and the 2-Mbyte address will return all ‘0’s (a
NOP instruction).
The entire PIC18F85J90 family offers a range of
on-chip Flash program memory sizes, from 8 Kbytes
(up to 4,096 single-word instructions) to 32 Kbytes
(32,768 single-word instructions). The program
memory maps for individual family members are shown
in Figure 6-1.
FIGURE 6-1: MEMORY MAPS FOR PIC18F85J90 FAMILY DEVICES
Note: Sizes of memory areas are not to scale. Sizes of program memory areas are enhanced to show detail.
Unimplemented
Read as ‘0’
Unimplemented
Read as ‘0’
Unimplemented
Read as ‘0’
000000h
1FFFFFh
007FFFh
PIC18FX3J90 PIC18FX4J90 PIC18FX5J90
001FFFh
003FFFh
PC<20:0>
Stack Level 1
Stack Level 31
CALL, CALLW, RCALL,
RETURN, RETFIE, RETLW,
21
User Memory Space
On-Chip
Memory
On-Chip
Memory
On-Chip
Memory
ADDULNK, SUBULNK
Config. Words
Config. Words
Config. Words
PIC18F85J90 FAMILY
DS39770C-page 64 2010 Microchip Technology Inc.
6.1.1 HARD MEMORY VECTORS
All PIC18 devices have a total of three hard-coded
return vectors in their program memory space. The
Reset vector address is the default value to which the
program counter returns on all device Resets; it is
located at 0000h.
PIC18 devices also have two interrupt vector
addresses for the handling of high-priority and
low-priority interrupts. The high-priority interrupt vector
is located at 0008h and the low-priority interrupt vector
is at 0018h. Their locations in relation to the program
memory map are shown in Figure 6-2.
FIGURE 6-2: HARD VECTOR AND
CONFIGURATION WORD
LOCATIONS FOR
PIC18F85J90 FAMILY
FAMILY DEVICES
6.1.2 FLASH CONFIGURATION WORDS
Because PIC18F85J90 family devices do not have per-
sistent configuration memory, the top four words of
on-chip program memory are reserved for configuration
information. On Reset, the configuration information is
copied into the Configuration registers.
The Configuration Words are stored in their program
memory location in numerical order, starting with the
lower byte of CONFIG1 at the lowest address and end-
ing with the upper byte of CONFIG4. For these devices,
only Configuration Words, CONFIG1 through
CONFIG3, are used; CONFIG4 is reserved. The actual
addresses of the Flash Configuration Word for devices
in the PIC18F85J90 family are shown in Table 6-1.
Their location in the memory map is shown with the
other memory vectors in Figure 6-2.
Additional details on the device Configuration Words
are provided in Section 23.1 “Configuration Bits”.
TABLE 6-1: FLASH CONFIGURATION
WORD FOR PIC18F85J90
FAMILY DEVICES
Reset Vector
Low-Priority Interrupt Vector
0000h
0018h
On-Chip
Program Memory
High-Priority Interrupt Vector 0008h
1FFFFFh
(Top of Memory)
(Top of Memory-7)
Flash Configuration Words
Read ‘0’
Legend: (Top of Memory) represents upper boundary
of on-chip program memory space (see
Figure 6-1 for device-specific values).
Shaded area represents unimplemented
memory. Areas are not shown to scale.
Device
Program
Memory
(Kbytes)
Configuration
Word
Addresses
PIC18F63J90 8 1FF8h to 1FFFh
PIC18F83J90
PIC18F64J90 16 3FF8h to 3FFFh
PIC18F84J90
PIC18F65J90 32 7FF8h to 7FFFh
PIC18F85J90
2010 Microchip Technology Inc. DS39770C-page 65
PIC18F85J90 FAMILY
6.1.3 PROGRAM COUNTER
The Program Counter (PC) specifies the address of the
instruction to fetch for execution. The PC is 21 bits wide
and is contained in three separate 8-bit registers. The
low byte, known as the PCL register, is both readable
and writable. The high byte, or PCH register, contains
the PC<15:8> bits; it is not directly readable or writable.
Updates to the PCH register are performed through the
PCLATH register. The upper byte is called PCU. This
register contains the PC<20:16> bits; it is also not
directly readable or writable. Updates to the PCU
register are performed through the PCLATU register.
The contents of PCLATH and PCLATU are transferred
to the program counter by any operation that writes
PCL. Similarly, the upper two bytes of the program
counter are transferred to PCLATH and PCLATU by an
operation that reads PCL. This is useful for computed
offsets to the PC (see Section 6.1.6.1 “Computed
GOTO”).
The PC addresses bytes in the program memory. To
prevent the PC from becoming misaligned with word
instructions, the Least Significant bit of PCL is fixed to
a value of ‘0’. The PC increments by 2 to address
sequential instructions in the program memory.
The CALL, RCALL, GOTO and program branch
instructions write to the program counter directly. For
these instructions, the contents of PCLATH and
PCLATU are not transferred to the program counter.
6.1.4 RETURN ADDRESS STACK
The return address stack allows any combination of up
to 31 program calls and interrupts to occur. The PC is
pushed onto the stack when a CALL or RCALL instruc-
tion is executed, or an interrupt is Acknowledged. The
PC value is pulled off the stack on a RETURN, RETLW
or a RETFIE instruction (and on ADDULNK and
SUBULNK instructions if the extended instruction set is
enabled). PCLATU and PCLATH are not affected by
any of the RETURN or CALL instructions.
The stack operates as a 31-word by 21-bit RAM and a
5-bit Stack Pointer, STKPTR. The stack space is not
part of either program or data space. The Stack Pointer
is readable and writable and the address on the top of
the stack is readable and writable through the
Top-of-Stack Special Function Registers. Data can also
be pushed to, or popped from, the stack using these
registers.
A CALL type instruction causes a push onto the stack.
The Stack Pointer is first incremented and the location
pointed to by the Stack Pointer is written with the
contents of the PC (already pointing to the instruction
following the CALL). A RETURN type instruction causes
a pop from the stack. The contents of the location
pointed to by the STKPTR are transferred to the PC
and then the Stack Pointer is decremented.
The Stack Pointer is initialized to ‘00000’ after all
Resets. There is no RAM associated with the location
corresponding to a Stack Pointer value of ‘00000’; this
is only a Reset value. Status bits indicate if the stack is
full, has overflowed or has underflowed.
6.1.4.1 Top-of-Stack Access
Only the top of the return address stack (TOS) is
readable and writable. A set of three registers,
TOSU:TOSH:TOSL, holds the contents of the stack
location pointed to by the STKPTR register
(Figure 6-3). This allows users to implement a software
stack if necessary. After a CALL, RCALL or interrupt
(and ADDULNK and SUBULNK instructions if the
extended instruction set is enabled), the software can
read the pushed value by reading the
TOSU:TOSH:TOSL registers. These values can be
placed on a user-defined software stack. At return time,
the software can return these values to
TOSU:TOSH:TOSL and do a return.
The user must disable the global interrupt enable bits
while accessing the stack to prevent inadvertent stack
corruption.
FIGURE 6-3: RETURN ADDRESS STACK AND ASSOCIATED REGISTERS
00011
001A34h
11111
11110
11101
00010
00001
00000
00010
Return Address Stack <20:0>
Top-of-Stack
000D58h
TOSLTOSHTOSU
34h1Ah00h
STKPTR<4:0>
Top-of-Stack Registers Stack Pointer
PIC18F85J90 FAMILY
DS39770C-page 66 2010 Microchip Technology Inc.
6.1.4.2 Return Stack Pointer (STKPTR)
The STKPTR register (Register 6-1) contains the Stack
Pointer value, the STKFUL (Stack Full) status bit and
the STKUNF (Stack Underflow) status bits. The value
of the Stack Pointer can be 0 through 31. The Stack
Pointer increments before values are pushed onto the
stack and decrements after values are popped off the
stack. On Reset, the Stack Pointer value will be zero.
The user may read and write the Stack Pointer value.
This feature can be used by a Real-Time Operating
System (RTOS) for return stack maintenance.
After the PC is pushed onto the stack 31 times (without
popping any values off the stack), the STKFUL bit is
set. The STKFUL bit is cleared by software or by a
POR.
The action that takes place when the stack becomes
full depends on the state of the STVREN (Stack Over-
flow Reset Enable) Configuration bit. (Refer to
Section 23.1 “Configuration Bits” for a description of
the device Configuration bits.) If STVREN is set
(default), the 31st push will push the (PC + 2) value
onto the stack, set the STKFUL bit and reset the
device. The STKFUL bit will remain set and the Stack
Pointer will be set to zero.
If STVREN is cleared, the STKFUL bit will be set on the
31st push and the Stack Pointer will increment to 31.
Any additional pushes will not overwrite the 31st push
and the STKPTR will remain at 31.
When the stack has been popped enough times to
unload the stack, the next pop will return a value of zero
to the PC and set the STKUNF bit, while the Stack
Pointer remains at zero. The STKUNF bit will remain
set until cleared by software or until a POR occurs.
6.1.4.3 PUSH and POP Instructions
Since the Top-of-Stack is readable and writable, the
ability to push values onto the stack and pull values off
the stack, without disturbing normal program execu-
tion, is a desirable feature. The PIC18 instruction set
includes two instructions, PUSH and POP, that permit
the TOS to be manipulated under software control.
TOSU, TOSH and TOSL can be modified to place data
or a return address on the stack.
The PUSH instruction places the current PC value onto
the stack. This increments the Stack Pointer and loads
the current PC value onto the stack.
The POP instruction discards the current TOS by
decrementing the Stack Pointer. The previous value
pushed onto the stack then becomes the TOS value.
Note: Returning a value of zero to the PC on an
underflow has the effect of vectoring the
program to the Reset vector, where the
stack conditions can be verified and
appropriate actions can be taken. This is
not the same as a Reset, as the contents
of the SFRs are not affected.
REGISTER 6-1: STKPTR: STACK POINTER REGISTER
R/C-0 R/C-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
STKFUL(1) STKUNF(1) — SP4 SP3 SP2 SP1 SP0
bit 7 bit 0
Legend: C = Clearable-only bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 STKFUL: Stack Full Flag bit(1)
1 = Stack has become full or overflowed
0 = Stack has not become full or overflowed
bit 6 STKUNF: Stack Underflow Flag bit(1)
1 = Stack underflow occurred
0 = Stack underflow did not occur
bit 5 Unimplemented: Read as ‘0’
bit 4-0 SP<4:0>: Stack Pointer Location bits
Note 1: Bit 7 and bit 6 are cleared by user software or by a POR.
2010 Microchip Technology Inc. DS39770C-page 67
PIC18F85J90 FAMILY
6.1.4.4 Stack Full and Underflow Resets
Device Resets on stack overflow and stack underflow
conditions are enabled by setting the STVREN bit in
Configuration Register 1L. When STVREN is set, a full
or underflow condition will set the appropriate STKFUL
or STKUNF bit and then cause a device Reset. When
STVREN is cleared, a full or underflow condition will set
the appropriate STKFUL or STKUNF bit, but not cause
a device Reset. The STKFUL or STKUNF bits are
cleared by the user software or a Power-on Reset.
6.1.5 FAST REGISTER STACK
A Fast Register Stack is provided for the STATUS,
WREG and BSR registers to provide a “fast return”
option for interrupts. This stack is only one level deep
and is neither readable nor writable. It is loaded with the
current value of the corresponding register when the
processor vectors for an interrupt. All interrupt sources
will push values into the Stack registers. The values in
the registers are then loaded back into the working
registers if the RETFIE, FAST instruction is used to
return from the interrupt.
If both low and high-priority interrupts are enabled, the
Stack registers cannot be used reliably to return from
low-priority interrupts. If a high-priority interrupt occurs
while servicing a low-priority interrupt, the Stack
register values stored by the low-priority interrupt will
be overwritten. In these cases, users must save the key
registers in software during a low-priority interrupt.
If interrupt priority is not used, all interrupts may use the
Fast Register Stack for returns from interrupt. If no
interrupts are used, the Fast Register Stack can be
used to restore the STATUS, WREG and BSR registers
at the end of a subroutine call. To use the Fast Register
Stack for a subroutine call, a CALL label, FAST
instruction must be executed to save the STATUS,
WREG and BSR registers to the Fast Register Stack. A
RETURN, FAST instruction is then executed to restore
these registers from the Fast Register Stack.
Example 6-1 shows a source code example that uses
the Fast Register Stack during a subroutine call and
return.
EXAMPLE 6-1: FAST REGISTER STACK
CODE EXAMPLE
6.1.6 LOOK-UP TABLES IN PROGRAM
MEMORY
There may be programming situations that require the
creation of data structures, or look-up tables, in
program memory. For PIC18 devices, look-up tables
can be implemented in two ways:
• Computed GOTO
• Table Reads
6.1.6.1 Computed GOTO
A computed GOTO is accomplished by adding an offset
to the program counter. An example is shown in
Example 6-2.
A look-up table can be formed with an ADDWF PCL
instruction and a group of RETLW nn instructions. The
W register is loaded with an offset into the table before
executing a call to that table. The first instruction of the
called routine is the ADDWF PCL instruction. The next
instruction executed will be one of the RETLW nn
instructions that returns the value ‘nn’ to the calling
function.
The offset value (in WREG) specifies the number of
bytes that the program counter should advance and
should be multiples of 2 (LSb = 0).
In this method, only one data byte may be stored in
each instruction location and room on the return
address stack is required.
EXAMPLE 6-2: COMPUTED GOTO USING
AN OFFSET VALUE
6.1.6.2 Table Reads
A better method of storing data in program memory
allows two bytes of data to be stored in each instruction
location.
Look-up table data may be stored two bytes per
program word while programming. The Table Pointer
(TBLPTR) specifies the byte address and the Table
Latch (TABLAT) contains the data that is read from the
program memory. Data is transferred from program
memory one byte at a time.
Table read operation is discussed further in
Section 7.1 “Table Reads and Table Writes”.
CALL SUB1, FAST ;STATUS, WREG, BSR
;SAVED IN FAST REGISTER
;STACK
SUB1
RETURN FAST ;RESTORE VALUES SAVED
;IN FAST REGISTER STACK
MOVF OFFSET, W
CALL TABLE
ORG nn00h
TABLE ADDWF PCL
RETLW nnh
RETLW nnh
RETLW nnh
.
.
.
PIC18F85J90 FAMILY
DS39770C-page 68 2010 Microchip Technology Inc.
6.2 PIC18 Instruction Cycle
6.2.1 CLOCKING SCHEME
The microcontroller clock input, whether from an
internal or external source, is internally divided by four
to generate four non-overlapping quadrature clocks
(Q1, Q2, Q3 and Q4). Internally, the program counter is
incremented on every Q1; the instruction is fetched
from the program memory and latched into the
Instruction Register (IR) during Q4. The instruction is
decoded and executed during the following Q1 through
Q4. The clocks and instruction execution flow are
shown in Figure 6-4.
6.2.2 INSTRUCTION FLOW/PIPELINING
An “Instruction Cycle” consists of four Q cycles, Q1
through Q4. The instruction fetch and execute are pipe-
lined in such a manner that a fetch takes one instruction
cycle, while the decode and execute take another
instruction cycle. However, due to the pipelining, each
instruction effectively executes in one cycle. If an
instruction causes the program counter to change (e.g.,
GOTO), then two cycles are required to complete the
instruction (Example 6-3).
A fetch cycle begins with the Program Counter (PC)
incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the Instruction Register (IR) in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3 and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
FIGURE 6-4: CLOCK/INSTRUCTION CYCLE
EXAMPLE 6-3: INSTRUCTION PIPELINE FLOW
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
Q1
Q2
Q3
Q4
PC
OSC2/CLKO
(RC mode)
PC PC + 2 PC + 4
Fetch INST (PC)
Execute INST (PC – 2)
Fetch INST (PC + 2)
Execute INST (PC)
Fetch INST (PC + 4)
Execute INST (PC + 2)
Internal
Phase
Clock
All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction
is “flushed” from the pipeline while the new instruction is being fetched and then executed.
TCY 0TCY 1TCY 2TCY 3TCY 4TCY 5
1. MOVLW 55h Fetch 1 Execute 1
2. MOVWF PORTB Fetch 2 Execute 2
3. BRA SUB_1 Fetch 3 Execute 3
4. BSF PORTA, BIT3 (Forced NOP) Fetch 4 Flush (NOP)
5. Instruction @ address SUB_1 Fetch SUB_1 Execute SUB_1
2010 Microchip Technology Inc. DS39770C-page 69
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6.2.3 INSTRUCTIONS IN PROGRAM
MEMORY
The program memory is addressed in bytes. Instruc-
tions are stored as two bytes or four bytes in program
memory. The Least Significant Byte of an instruction
word is always stored in a program memory location
with an even address (LSB = 0). To maintain alignment
with instruction boundaries, the PC increments in steps
of 2 and the LSB will always read ‘0’ (see Section 6.1.3
“Program Counter”).
Figure 6-5 shows an example of how instruction words
are stored in the program memory.
The CALL and GOTO instructions have the absolute
program memory address embedded into the instruc-
tion. Since instructions are always stored on word
boundaries, the data contained in the instruction is a
word address. The word address is written to PC<20:1>
which accesses the desired byte address in program
memory. Instruction #2 in Figure 6-5 shows how the
instruction, GOTO 0006h, is encoded in the program
memory. Program branch instructions, which encode a
relative address offset, operate in the same manner. The
offset value stored in a branch instruction represents the
number of single-word instructions that the PC will be
offset by. Section 24.0 “Instruction Set Summary”
provides further details of the instruction set.
FIGURE 6-5: INSTRUCTIONS IN PROGRAM MEMORY
6.2.4 TWO-WORD INSTRUCTIONS
The standard PIC18 instruction set has four, two-word
instructions: CALL, MOVFF, GOTO and LSFR. In all
cases, the second word of the instructions always has
‘1111’ as its four Most Significant bits; the other 12 bits
are literal data, usually a data memory address.
The use of ‘1111’ in the 4 MSbs of an instruction
specifies a special form of NOP. If the instruction is
executed in proper sequence – immediately after the
first word – the data in the second word is accessed
and used by the instruction sequence. If the first word
is skipped for some reason and the second word is
executed by itself, a NOP is executed instead. This is
necessary for cases when the two-word instruction is
preceded by a conditional instruction that changes the
PC. Example 6-4 shows how this works.
EXAMPLE 6-4: TWO-WORD INSTRUCTIONS
Word Address
LSB = 1LSB = 0
Program Memory
Byte Locations
000000h
000002h
000004h
000006h
Instruction 1: MOVLW 055h 0Fh 55h 000008h
Instruction 2: GOTO 0006h EFh 03h 00000Ah
F0h 00h 00000Ch
Instruction 3: MOVFF 123h, 456h C1h 23h 00000Eh
F4h 56h 000010h
000012h
000014h
Note: See Section 6.5 “Program Memory and
the Extended Instruction Set” for
information on two-word instructions in the
extended instruction set.
CASE 1:
Object Code Source Code
0110 01 10 000 0 00 00 TSTFS Z REG 1 ; is RA M lo ca ti on 0?
1100 0001 0010 0011 MOVFF REG1, REG2 ; No, skip this word
1111 0100 0101 0110 ; Execute this word as a NOP
0010 0100 0000 0000 ADDWF REG3 ; continue code
CASE 2:
Object Code Source Code
0110 01 10 000 0 00 00 TSTFSZ R EG 1 ; is RA M lo ca ti on 0?
1100 0001 0010 0011 MOVFF REG1, REG2 ; Yes , ex ec ut e th is wor d
1111 0100 0101 0110 ; 2nd word of instruction
0010 01 00 000 0 00 00 ADDWF REG 3 ; con ti nu e co de
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6.3 Data Memory Organization
The data memory in PIC18 devices is implemented as
static RAM. Each register in the data memory has a
12-bit address, allowing up to 4096 bytes of data
memory. The memory space is divided into as many as
16 banks that contain 256 bytes each. The
PIC18FX3J90/X4J90 devices, with up to 16 Kbytes of
program memory, implement 4 complete banks for a
total of 1024 bytes. PIC18FX5J90 devices, with
32 Kbytes of program memory, implement 8 complete
banks for a total of 2048 bytes. Figure 6-6 and
Figure 6-7 show the data memory organization for the
devices.
The data memory contains Special Function Registers
(SFRs) and General Purpose Registers (GPRs). The
SFRs are used for control and status of the controller
and peripheral functions, while GPRs are used for data
storage and scratchpad operations in the user’s
application. Any read of an unimplemented location will
read as ‘0’s.
The instruction set and architecture allow operations
across all banks. The entire data memory may be
accessed by Direct, Indirect or Indexed Addressing
modes. Addressing modes are discussed later in this
section.
To ensure that commonly used registers (select SFRs
and select GPRs) can be accessed in a single cycle,
PIC18 devices implement an Access Bank. This is a
256-byte memory space that provides fast access to
select SFRs and the lower portion of GPR Bank 0 with-
out using the BSR. Section 6.3.2 “Access Bank”
provides a detailed description of the Access RAM.
6.3.1 BANK SELECT REGISTER
Large areas of data memory require an efficient
addressing scheme to make rapid access to any
address possible. Ideally, this means that an entire
address does not need to be provided for each read or
write operation. For PIC18 devices, this is accom-
plished with a RAM banking scheme. This divides the
memory space into 16 contiguous banks of 256 bytes.
Depending on the instruction, each location can be
addressed directly by its full 12-bit address, or an 8-bit
low-order address and a 4-bit Bank Pointer.
Most instructions in the PIC18 instruction set make use
of the Bank Pointer, known as the Bank Select Register
(BSR). This SFR holds the 4 Most Significant bits
(MSbs) of a location’s address; the instruction itself
includes the 8 Least Significant bits (LSbs). Only the
four lower bits of the BSR are implemented
(BSR<3:0>). The upper four bits are unused; they will
always read ‘0’ and cannot be written to. The BSR can
be loaded directly by using the MOVLB instruction.
The value of the BSR indicates the bank in data
memory. The 8 bits in the instruction show the location
in the bank and can be thought of as an offset from the
bank’s lower boundary. The relationship between the
BSR’s value and the bank division in data memory is
shown in Figure 6-8.
Since up to 16 registers may share the same low-order
address, the user must always be careful to ensure that
the proper bank is selected before performing a data
read or write. For example, writing what should be
program data to an 8-bit address of F9h while the BSR
is 0Fh, will end up resetting the program counter.
While any bank can be selected, only those banks that
are actually implemented can be read or written to.
Writes to unimplemented banks are ignored, while
reads from unimplemented banks will return ‘0’s. Even
so, the STATUS register will still be affected as if the
operation was successful. The data memory map in
Figure 6-6 indicates which banks are implemented.
In the core PIC18 instruction set, only the MOVFF
instruction fully specifies the 12-bit address of the
source and target registers. This instruction ignores the
BSR completely when it executes. All other instructions
include only the low-order address as an operand and
must use either the BSR or the Access Bank to locate
their target registers.
Note: The operation of some aspects of data
memory are changed when the PIC18
extended instruction set is enabled. See
Section 6.6 “Data Memory and the
Extended Instruction Set” for more
information.
2010 Microchip Technology Inc. DS39770C-page 71
PIC18F85J90 FAMILY
FIGURE 6-6: DATA MEMORY MAP FOR PIC18FX3J90/X4J90 DEVICES
00h
5Fh
60h
FFh
Access Bank
When a = 0:
The BSR is ignored and the
Access Bank is used.
The first 96 bytes are general
purpose RAM (from Bank 0).
The second 160 bytes are
Special Function Registers
(from Bank 15).
When a = 1:
The BSR specifies the bank
used by the instruction.
Access RAM High
Access RAM Low
(SFRs)
Bank 0
Bank 1
Bank 14
Bank 15
Data Memory Map
BSR<3:0>
= 0000
= 0001
= 1111
060h
05Fh
F60h
FFFh
F5Fh
F00h
EFFh
1FFh
100h
0FFh
000h
Access RAM
FFh
00h
FFh
00h
FFh
00h
GPR
GPR
SFR
Bank 2
= 0010
2FFh
200h
Bank 3
FFh
00h
GPR
FFh
= 0011
Unused
GPR
400h
3FFh
300h
FFh
00h
00h
= 0100 Bank 4
= 1110
to
Unused
Read as ‘0’
PIC18F85J90 FAMILY
DS39770C-page 72 2010 Microchip Technology Inc.
FIGURE 6-7: DATA MEMORY MAP FOR PIC18FX5J90 DEVICES
00h
5Fh
60h
FFh
Access Bank
When a = 0:
The BSR is ignored and the
Access Bank is used.
The first 96 bytes are general
purpose RAM (from Bank 0).
The second 160 bytes are
Special Function Registers
(from Bank 15).
When a = 1:
The BSR specifies the bank
used by the instruction.
Access RAM High
Access RAM Low
(SFRs)
Bank 0
Bank 1
Bank 14
Bank 15
Data Memory Map
BSR<3:0>
= 0000
= 0001
= 1111
060h
05Fh
F60h
FFFh
F5Fh
F00h
EFFh
1FFh
100h
0FFh
000h
Access RAM
FFh
00h
FFh
00h
FFh
00h
GPR
GPR
SFR
Bank 2
= 0010
2FFh
200h
Bank 3
FFh
00h
GPR
FFh
= 0011
Unused
GPR
GPR
GPR
GPR
GPR
4FFh
400h
5FFh
500h
3FFh
300h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
00h
= 0110
= 0111
= 1000
= 0101
= 0100 Bank 4
Bank 5
Bank 6
Bank 7
Bank 8
= 1110
6FFh
600h
7FFh
700h
800h
to
Unused
Read as ‘0’
2010 Microchip Technology Inc. DS39770C-page 73
PIC18F85J90 FAMILY
FIGURE 6-8: USE OF THE BANK SELECT REGISTER (DIRECT ADDRESSING)
6.3.2 ACCESS BANK
While the use of the BSR with an embedded 8-bit
address allows users to address the entire range of data
memory, it also means that the user must always ensure
that the correct bank is selected. Otherwise, data may
be read from, or written to, the wrong location. This can
be disastrous if a GPR is the intended target of an oper-
ation, but an SFR is written to instead. Verifying and/or
changing the BSR for each read or write to data memory
can become very inefficient.
To streamline access for the most commonly used data
memory locations, the data memory is configured with
an Access Bank, which allows users to access a
mapped block of memory without specifying a BSR.
The Access Bank consists of the first 96 bytes of
memory (00h-5Fh) in Bank 0 and the last 160 bytes of
memory (60h-FFh) in Bank 15. The lower half is known
as the “Access RAM” and is composed of GPRs. The
upper half is where the device’s SFRs are mapped.
These two areas are mapped contiguously in the
Access Bank and can be addressed in a linear fashion
by an 8-bit address (Figure 6-6).
The Access Bank is used by core PIC18 instructions
that include the Access RAM bit (the ‘a’ parameter in
the instruction). When ‘a’ is equal to ‘1’, the instruction
uses the BSR and the 8-bit address included in the
opcode for the data memory address. When ‘a’ is ‘0’,
however, the instruction is forced to use the Access
Bank address map; the current value of the BSR is
ignored entirely.
Using this “forced” addressing allows the instruction to
operate on a data address in a single cycle without
updating the BSR first. For 8-bit addresses of 60h and
above, this means that users can evaluate and operate
on SFRs more efficiently. The Access RAM below 60h
is a good place for data values that the user might need
to access rapidly, such as immediate computational
results or common program variables. Access RAM
also allows for faster and more code efficient context
saving and switching of variables.
The mapping of the Access Bank is slightly different
when the extended instruction set is enabled (XINST
Configuration bit = 1). This is discussed in more detail
in Section 6.6.3 “Mapping the Access Bank in
Indexed Literal Offset Mode”.
6.3.3 GENERAL PURPOSE
REGISTER FILE
PIC18 devices may have banked memory in the GPR
area. This is data RAM which is available for use by all
instructions. GPRs start at the bottom of Bank 0
(address 000h) and grow upwards towards the bottom of
the SFR area. GPRs are not initialized by a Power-on
Reset and are unchanged on all other Resets.
Note 1: The Access RAM bit of the instruction can be used to force an override of the selected bank (BSR<3:0>)
to the registers of the Access Bank.
2: The MOVFF instruction embeds the entire 12-bit address in the instruction.
Data Memory
Bank Select(2)
70
From Opcode(2)
0000
000h
100h
200h
300h
F00h
E00h
FFFh
Bank 0
Bank 1
Bank 2
Bank 14
Bank 15
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
Bank 3
through
Bank 13
0010 11111111
70
BSR(1)
11111111
PIC18F85J90 FAMILY
DS39770C-page 74 2010 Microchip Technology Inc.
6.3.4 SPECIAL FUNCTION REGISTERS
The Special Function Registers (SFRs) are registers
used by the CPU and peripheral modules for controlling
the desired operation of the device. These registers are
implemented as static RAM. SFRs start at the top of
data memory (FFFh) and extend downward to occupy
more than the top half of Bank 15 (F60h to FFFh). A list
of these registers is given in Table 6-2 and Table 6-3.
The SFRs can be classified into two sets: those
associated with the “core” device functionality (ALU,
Resets and interrupts) and those related to the
peripheral functions. The Reset and Interrupt registers
are described in their respective chapters, while the
ALU’s STATUS register is described later in this section.
Registers related to the operation of the peripheral
features are described in the chapter for that peripheral.
The SFRs are typically distributed among the
peripherals whose functions they control. Unused SFR
locations are unimplemented and read as ‘0’s.
TABLE 6-2: SPECIAL FUNCTION REGISTER MAP FOR PIC18F85J90 FAMILY DEVICES
Address Name Address Name Address Name Address Name Address Name
FFFh TOSU FDFh INDF2(1) FBFh LCDDATA4(3) F9Fh IPR1 F7Fh SPBRGH1
FFEh TOSH FDEh POSTINC2(1) FBEh LCDDATA3 F9Eh PIR1 F7Eh BAUDCON1
FFDh TOSL FDDh POSTDEC2(1) FBDh LCDDATA2 F9Dh PIE1 F7Dh
LCDDATA23
(3)
FFCh STKPTR FDCh PREINC2(1) FBCh LCDDATA1 F9Ch —(2) F7Ch
LCDDATA22
(3)
FFBh PCLATU FDBh PLUSW2(1) FBBh LCDDATA0 F9Bh OSCTUNE F7Bh
LCDDATA21
FFAh PCLATH FDAh FSR2H FBAh LCDSE5(3) F9Ah TRISJ(3) F7Ah
LCDDATA20
FF9h PCL FD9h FSR2L FB9h LCDSE4(3) F99h TRISH(3) F79h
LCDDATA19
FF8h TBLPTRU FD8h STATUS FB8h LCDSE3 F98h TRISG F78h
LCDDATA18
FF7h TBLPTRH FD7h TMR0H FB7h LCDSE2 F97h TRISF F77h
LCDDATA17
(3)
FF6h TBLPTRL FD6h TMR0L FB6h LCDSE1 F96h TRISE F76h
LCDDATA16
(3)
FF5h TABLAT FD5h T0CON FB5h CVRCON F95h TRISD F75h
LCDDATA15
FF4h PRODH FD4h —(2) FB4h CMCON F94h TRISC F74h
LCDDATA14
FF3h PRODL FD3h OSCCON FB3h TMR3H F93h TRISB F73h
LCDDATA13
FF2h INTCON FD2h LCDREG FB2h TMR3L F92h TRISA F72h
LCDDATA12
FF1h INTCON2 FD1h WDTCON FB1h T3CON F91h LATJ(3) F71h
LCDDATA11
(3)
FF0h INTCON3 FD0h RCON FB0h —(2) F90h LATH(3) F70h
LCDDATA10
(3)
FEFh INDF0(1) FCFh TMR1H FAFh SPBRG1 F8Fh LATG F6Fh LCDDATA9
FEEh POSTINC0(1) FCEh TMR1L FAEh RCREG1 F8Eh LATF F6Eh LCDDATA8
FEDh POSTDEC0(1) FCDh T1CON FADh TXREG1 F8Dh LATE F6Dh LCDDATA7
FECh PREINC0(1) FCCh TMR2 FACh TXSTA1 F8Ch LATD F6Ch LCDDATA6
FEBh PLUSW0(1) FCBh PR2 FABh RCSTA1 F8Bh LATC F6Bh LCDDATA5(3)
FEAh FSR0H FCAh T2CON FAAh LCDPS F8Ah LATB F6Ah CCPR1H
FE9h FSR0L FC9h SSPBUF FA9h LCDSE0 F89h LATA F69h CCPR1L
FE8h WREG FC8h SSPADD FA8h LCDCON F88h PORTJ(3) F68h CCP1CON
FE7h INDF1(1) FC7h SSPSTAT FA7h EECON2 F87h PORTH(3) F67h CCPR2H
FE6h POSTINC1(1) FC6h SSPCON1 FA6h EECON1 F86h PORTG F66h CCPR2L
FE5h POSTDEC1(1) FC5h SSPCON2 FA5h IPR3 F85h PORTF F65h CCP2CON
FE4h PREINC1(1) FC4h ADRESH FA4h PIR3 F84h PORTE F64h SPBRG2
FE3h PLUSW1(1) FC3h ADRESL FA3h PIE3 F83h PORTD F63h RCREG2
FE2h FSR1H FC2h ADCON0 FA2h IPR2 F82h PORTC F62h TXREG2
FE1h FSR1L FC1h ADCON1 FA1h PIR2 F81h PORTB F61h TXSTA2
FE0h BSR FC0h ADCON2 FA0h PIE2 F80h PORTA F60h RCSTA2
Note 1: This is not a physical register.
2: Unimplemented registers are read as ‘0’.
3: This register is not available on 64-pin devices.
2010 Microchip Technology Inc. DS39770C-page 75
PIC18F85J90 FAMILY
TABLE 6-3: PIC18F85J90 FAMILY REGISTER FILE SUMMARY
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR
Details
on page
TOSU — — — Top-of-Stack Upper Byte (TOS<20:16>) ---0 0000 57, 65
TOSH Top-of-Stack High Byte (TOS<15:8>) 0000 0000 57, 65
TOSL Top-of-Stack Low Byte (TOS<7:0>) 0000 0000 57, 65
STKPTR STKFUL STKUNF — Return Stack Pointer uu-0 0000 57, 66
PCLATU ——bit 21
(1) Holding Register for PC<20:16> ---0 0000 57, 65
PCLATH Holding Register for PC<15:8> 0000 0000 57, 65
PCL PC Low Byte (PC<7:0>) 0000 0000 57, 65
TBLPTRU —— bit 21 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) --00 0000 57, 90
TBLPTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 0000 0000 57, 90
TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) 0000 0000 57, 90
TABLAT Program Memory Table Latch 0000 0000 57, 90
PRODH Product Register High Byte xxxx xxxx 57, 97
PRODL Product Register Low Byte xxxx xxxx 57, 97
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 57, 101
INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INT3IP RBIP 1111 1111 57, 102
INTCON3 INT2IP INT1IP INT3IE INT2IE INT1IE INT3IF INT2IF INT1IF 1100 0000 57, 103
INDF0 Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register) N/A 57, 81
POSTINC0 Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register) N/A 57, 82
POSTDEC0 Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register) N/A 57, 82
PREINC0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) N/A 57, 82
PLUSW0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) –
value of FSR0 offset by W
N/A 57, 82
FSR0H — — — — Indirect Data Memory Address Pointer 0 High ---- xxxx 57, 81
FSR0L Indirect Data Memory Address Pointer 0 Low Byte xxxx xxxx 57, 81
WREG Working Register xxxx xxxx 57
INDF1 Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register) N/A 57, 81
POSTINC1 Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register) N/A 57, 82
POSTDEC1 Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register) N/A 57, 82
PREINC1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) N/A 57, 82
PLUSW1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) –
value of FSR1 offset by W
N/A 57, 82
FSR1H — — — — Indirect Data Memory Address Pointer 1 High Byte ---- xxxx 58, 81
FSR1L Indirect Data Memory Address Pointer 1 Low Byte xxxx xxxx 58, 81
BSR — — — — Bank Select Register ---- 0000 58, 70
INDF2 Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register) N/A 58, 81
POSTINC2 Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register) N/A 58, 82
POSTDEC2 Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register) N/A 58, 82
PREINC2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) N/A 58, 82
PLUSW2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) –
value of FSR2 offset by W
N/A 58, 82
FSR2H — — — — Indirect Data Memory Address Pointer 2 High Byte ---- xxxx 58, 81
FSR2L Indirect Data Memory Address Pointer 2 Low Byte xxxx xxxx 58, 81
STATUS — — —NOVZDCC---x xxxx 58, 79
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved, do not modify
Note 1: Bit 21 of the PC is only available in Test mode and Serial Programming modes.
2: These registers and/or bits are available only on 80-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset states shown
are for 80-pin devices.
3: Alternate names and definitions for these bits when the MSSP module is operating in I2C™ Slave mode. See Section 17.4.3.2 “Address
Masking” for details.
4: The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as ‘0’. See Section 3.4.3 “PLL
Frequency Multiplier” for details.
5: RA6/RA7 and their associated latch and direction bits are configured as port pins only when the internal oscillator is selected as the default
clock source (FOSC2 Configuration bit = 0); otherwise, they are disabled and these bits read as ‘0’.
PIC18F85J90 FAMILY
DS39770C-page 76 2010 Microchip Technology Inc.
TMR0H Timer0 Register High Byte 0000 0000 58, 139
TMR0L Timer0 Register Low Byte xxxx xxxx 58, 139
T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 1111 1111 58, 137
OSCCON IDLEN IRCF2 IRCF1 IRCF0 OSTS IOFS SCS1 SCS0 0100 q000 36, 58
LCDREG — CPEN BIAS2 BIAS1 BIAS0 MODE13 CKSEL1 CKSEL0 -011 1100 58, 169
WDTCON REGSLP ——————SWDTEN0--- ---0 58, 298
RCON IPEN —CMRI TO PD POR BOR 0-11 11q0 52, 58
TMR1H Timer1 Register High Byte xxxx xxxx 58, 145
TMR1L Timer1 Register Low Byte xxxx xxxx 58, 145
T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 58, 141
TMR2 Timer2 Register 0000 0000 58, 148
PR2 Timer2 Period Register 1111 1111 58, 148
T2CON —
T2OUTPS3
T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 58, 147
SSPBUF MSSP Receive Buffer/Transmit Register xxxx xxxx 58, 199,
234
SSPADD MSSP Address Register in I2C™ Slave mode. MSSP1 Baud Rate Reload Register in I2C Master mode. 0000 0000 58, 234
SSPSTAT SMP CKE D/A PSR/WUA BF 0000 0000 58, 192,
201
SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 58, 193,
202
SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 58, 203,
204
GCEN ACKSTAT ADMSK5(3) ADMSK4(3) ADMSK3(3) ADMSK2(3) ADMSK1(3) SEN
ADRESH A/D Result Register High Byte xxxx xxxx 59, 279
ADRESL A/D Result Register Low Byte xxxx xxxx 59, 279
ADCON0 ADCAL — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON 0-00 0000 59, 271
ADCON1 —— VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 --00 0000 59, 272
ADCON2 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 0-00 0000 59, 273
LCDDATA4 S39C0(2) S38C0(2) S37C0(2) S36C0(2) S35C0(2) S34C0(2) S33C0(2) S32C0 xxxx xxxx 59, 167
LCDDATA3 S31C0 S30C0 S29C0 S28C0 S27C0 S26C0 S25C0 S24C0 xxxx xxxx 59, 167
LCDDATA2 S23C0 S22C0 S21C0 S20C0 S19C0 S18C0 S17C0 S16C0 xxxx xxxx 59, 167
LCDDATA1 S15C0 S14C0 S13C0 S12C0 S11C0 S10C0 S09C0 S08C0 xxxx xxxx 59, 167
LCDDATA0 S07C0 S06C0 S05C0 S04C0 S03C0 S02C0 S01C0 S00C0 xxxx xxxx 59, 167
LCDSE5(2) SE47 SE46 SE45 SE44 SE43 SE42 SE41 SE40 0000 0000 59, 166
LCDSE4 SE39(2) SE38(2) S37(2) SE36(2) SE35(2) SE34(2) SE33(2) SE32 0000 0000 59, 166
LCDSE3 SE31 SE30 SE29 SE28 SE27 SE26 SE25 SE24 0000 0000 59, 166
LCDSE2 SE23 SE22 SE21 SE20 SE19 SE18 SE17 SE16 0000 0000 59, 166
LCDSE1 SE15 SE14 SE13 SE12 SE11 SE10 SE09 SE08 0000 0000 59, 166
CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 0000 0000 59, 287
CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0111 59, 281
TMR3H Timer3 Register High Byte xxxx xxxx 59, 151
TMR3L Timer3 Register Low Byte xxxx xxxx 59, 151
T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0000 0000 59, 149
TABLE 6-3: PIC18F85J90 FAMILY REGISTER FILE SUMMARY (CONTINUED)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR
Details
on page
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved, do not modify
Note 1: Bit 21 of the PC is only available in Test mode and Serial Programming modes.
2: These registers and/or bits are available only on 80-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset states shown
are for 80-pin devices.
3: Alternate names and definitions for these bits when the MSSP module is operating in I2C™ Slave mode. See Section 17.4.3.2 “Address
Masking” for details.
4: The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as ‘0’. See Section 3.4.3 “PLL
Frequency Multiplier” for details.
5: RA6/RA7 and their associated latch and direction bits are configured as port pins only when the internal oscillator is selected as the default
clock source (FOSC2 Configuration bit = 0); otherwise, they are disabled and these bits read as ‘0’.
2010 Microchip Technology Inc. DS39770C-page 77
PIC18F85J90 FAMILY
SPBRG1 EUSART Baud Rate Generator 0000 0000 59, 240
RCREG1 EUSART Receive Register 0000 0000 59, 248
TXREG1 EUSART Transmit Register 0000 0000 59, 246
TXSTA1 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 59, 236
RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 59, 237
LCDPS WFT BIASMD LCDA WA LP3 LP2 LP1 LP0 0000 0000 59, 165
LCDSE0 SE07 SE06 SE05 SE04 SE03 SE02 SE01 SE00 0000 0000 59, 166
LCDCON LCDEN SLPEN WERR —CS1CS0LMUX1LMUX0000- 0000 59, 164
EECON2 EEPROM Control Register 2 (not a physical register) ---- ---- 59, 88
EECON1 — — — FREE WRERR WREN WR —---0 x00- 59, 89
IPR3 — LCDIP RC2IP TX2IP — CCP2IP CCP1IP —-111 -11- 60, 112
PIR3 — LCDIF RC2IF TX2IF — CCP2IF CCP1IF —-000 -00- 60, 106
PIE3 — LCDIE RC2IE TX2IE — CCP2IE CCP1IE —-000 -00- 60, 109
IPR2 OSCFIP CMIP — — BCLIP LVDIP TMR3IP — 11-- 111- 60, 111
PIR2 OSCFIF CMIF — — BCLIF LVDIF TMR3IF — 00-- 000- 60, 105
PIE2 OSCFIE CMIE — — BCLIE LVDIE TMR3IE — 00-- 000- 60, 108
IPR1 — ADIP RC1IP TX1IP SSPIP — TMR2IP TMR1IP -111 1-11 60, 110
PIR1 — ADIF RC1IF TX1IF SSPIF —TMR2IFTMR1IF-000 0-00 60, 104
PIE1 — ADIE RC1IE TX1IE SSPIE — TMR2IE TMR1IE -000 0-00 60, 107
OSCTUNE INTSRC PLLEN(4) TUN5 TUN4 TUN3 TUN2 TUN1 TUN0 0000 0000 37, 60
TRISJ(2) TRISJ7 TRISJ6 TRISJ5 TRISJ4 TRISJ3 TRISJ2 TRISJ1 TRISJ0 1111 1111 60, 136
TRISH(2) TRISH7 TRISH6 TRISH5 TRISH4 TRISH3 TRISH2 TRISH1 TRISH0 1111 1111 60, 134
TRISG SPIOD CCP2OD CCP1OD TRISG4TRISG3TRISG2TRISG1 TRISG0 0001 1111 60, 132
TRISF TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 —1111 111- 60, 130
TRISE TRISE7 TRISE6 TRISE5 TRISE4 TRISE3 — TRISE1 TRISE0 1111 1-11 60, 127
TRISD TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 1111 1111 60, 125
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 60, 123
TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 60, 120
TRISA TRISA7(5) TRISA6(5) TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 60, 117
LATJ(2) LATJ7 LATJ6 LATJ5 LATJ4 LATJ3 LATJ2 LATJ1 LATJ0 xxxx xxxx 60, 136
LATH(2) LATH7 LATH6 LATH5 LATH4 LATH3 LATH2 LATH1 LATH0 xxxx xxxx 60, 134
LATG U2OD U1OD — LATG4 LATG3 LATG2 LATG1 LATG0 00-x xxxx 60, 132
LATF LATF7 LATF6 LATF5 LATF4 LATF3 LATF2 LATF1 —xxxx xxx- 60, 130
LATE LATE7 LATE6 LATE5 LATE4 LATE3 —LATE1LATE0xxxx x-xx 60, 127
LATD LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 xxxx xxxx 60, 125
LATC LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 xxxx xxxx 60, 123
LATB LATB7LATB6LATB5LATB4LATB3LATB2LATB1LATB0xxxx xxxx 60, 120
LATA LATA7(5) LATA6(5) LATA5LATA4LATA3LATA2LATA1LATA0xxxx xxxx 60, 117
TABLE 6-3: PIC18F85J90 FAMILY REGISTER FILE SUMMARY (CONTINUED)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR
Details
on page
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved, do not modify
Note 1: Bit 21 of the PC is only available in Test mode and Serial Programming modes.
2: These registers and/or bits are available only on 80-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset states shown
are for 80-pin devices.
3: Alternate names and definitions for these bits when the MSSP module is operating in I2C™ Slave mode. See Section 17.4.3.2 “Address
Masking” for details.
4: The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as ‘0’. See Section 3.4.3 “PLL
Frequency Multiplier” for details.
5: RA6/RA7 and their associated latch and direction bits are configured as port pins only when the internal oscillator is selected as the default
clock source (FOSC2 Configuration bit = 0); otherwise, they are disabled and these bits read as ‘0’.
PIC18F85J90 FAMILY
DS39770C-page 78 2010 Microchip Technology Inc.
PORTJ(2) RJ7 RJ6 RJ5 RJ4 RJ3 RJ2 RJ1 RJ0 xxxx xxxx 60, 136
PORTH(2) RH7 RH6 RH5 RH4 RH3 RH2 RH1 RH0 xxxx xxxx 60, 134
PORTG RDPU REPU RJPU(2) RG4 RG3 RG2 RG1 RG0 000x xxxx 60, 132
PORTF RF7 RF6 RF5 RF4 RF3 RF2 RF1 —xxxx xxx- 60, 130
PORTE RE7 RE6 RE5 RE4 RE3 —RE1RE0xxxx x-xx 61, 127
PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx 61, 125
PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx 61, 123
PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx 61, 120
PORTA RA7(5) RA6(5) RA5RA4RA3RA2RA1RA0xx0x 0000 61, 117
SPBRGH1 EUSART Baud Rate Generator High Byte 0000 0000 61, 240
BAUDCON1 ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN 0100 0-00 61, 238
LCDDATA23(2) S47C3 S46C3 S45C3 S44C3 S43C3 S42C3 S41C3 S40C3 xxxx xxxx 61, 167
LCDDATA22 S39C3(2) S38C3(2) S37C3(2) S36C3(2) S35C3(2) S34C3(2) S33C3(2) S32C3 xxxx xxxx 61, 167
LCDDATA21 S31C3 S30C3 S29C3 S28C3 S27C3 S26C3 S25C3 S24C3 xxxx xxxx 61, 167
LCDDATA20 S23C3 S22C3 S21C3 S20C3 S19C3 S18C3 S17C3 S16C3 xxxx xxxx 61, 167
LCDDATA19 S15C3 S14C3 S13C3 S12C3 S11C3 S10C3 S09C3 S08C3 xxxx xxxx 61, 167
LCDDATA18 S07C3 S06C3 S05C3 S04C3 S03C3 S02C3 S01C3 S00C3 xxxx xxxx 61, 167
LCDDATA17(2) S47C2 S46C2 S45C2 S44C2 S43C2 S42C2 S41C2 S40C2 xxxx xxxx 61, 167
LCDDATA16 S39C2(2) S38C2(2) S37C2(2) S36C2(2) S35C2(2) S34C2(2) S33C2(2) S32C2 xxxx xxxx 61, 167
LCDDATA15 S31C2 S30C2 S29C2 S28C2 S27C2 S26C2 S25C2 S24C2 xxxx xxxx 61, 167
LCDDATA14 S23C2 S22C2 S21C2 S20C2 S19C2 S18C2 S17C2 S16C2 xxxx xxxx 61, 167
LCDDATA13 S15C2 S14C2 S13C2 S12C2 S11C2 S10C2 S09C2 S08C2 xxxx xxxx 61, 167
LCDDATA12 S07C2 S06C2 S05C2 S04C2 S03C2 S02C2 S01C2 S00C2 xxxx xxxx 61, 167
LCDDATA11(2) S47C1 S46C1 S45C1 S44C1 S43C1 S42C1 S41C1 S40C1 xxxx xxxx 61, 167
LCDDATA10 S39C1(2) S38C1(2) S37C1(2) S36C1(2) S35C1(2) S34C1(2) S33C1(2) S32C1 xxxx xxxx 61, 167
LCDDATA9 S31C1 S30C1 S29C1 S28C1 S27C1 S26C1 S25C1 S24C1 xxxx xxxx 61, 167
LCDDATA8 S23C1 S22C1 S21C1 S20C1 S19C1 S18C1 S17C1 S16C1 xxxx xxxx 61, 167
LCDDATA7 S15C1 S14C1 S13C1 S12C1 S11C1 S10C1 S09C1 S08C1 xxxx xxxx 61, 167
LCDDATA6 S07C1 S06C1 S05C1 S04C1 S03C1 S02C1 S01C1 S00C1 xxxx xxxx 61, 167
LCDDATA5(2) S47C0 S46C0 S45C0 S44C0 S43C0 S42C0 S41C0 S40C0 xxxx xxxx 61, 167
CCPR1H Capture/Compare/PWM Register 1 High Byte xxxx xxxx 61, 154
CCPR1L Capture/Compare/PWM Register 1 Low Byte xxxx xxxx 61, 154
CCP1CON —— DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 61, 153
CCPR2H Capture/Compare/PWM Register 2 High Byte xxxx xxxx 61, 154
CCPR2L Capture/Compare/PWM Register 2 Low Byte xxxx xxxx 62, 154
CCP2CON —— DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 62, 153
SPBRG2 AUSART Baud Rate Generator Register 0000 0000 62, 260
RCREG2 AUSART Receive Register 0000 0000 62, 265
TXREG2 AUSART Transmit Register 0000 0000 62, 263
TXSTA2 CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 62, 258
RCSTA2 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 62, 259
TABLE 6-3: PIC18F85J90 FAMILY REGISTER FILE SUMMARY (CONTINUED)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR
Details
on page
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved, do not modify
Note 1: Bit 21 of the PC is only available in Test mode and Serial Programming modes.
2: These registers and/or bits are available only on 80-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset states shown
are for 80-pin devices.
3: Alternate names and definitions for these bits when the MSSP module is operating in I2C™ Slave mode. See Section 17.4.3.2 “Address
Masking” for details.
4: The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as ‘0’. See Section 3.4.3 “PLL
Frequency Multiplier” for details.
5: RA6/RA7 and their associated latch and direction bits are configured as port pins only when the internal oscillator is selected as the default
clock source (FOSC2 Configuration bit = 0); otherwise, they are disabled and these bits read as ‘0’.
2010 Microchip Technology Inc. DS39770C-page 79
PIC18F85J90 FAMILY
6.3.5 STATUS REGISTER
The STATUS register, shown in Register 6-2, contains
the arithmetic status of the ALU. The STATUS register
can be the operand for any instruction, as with any
other register. If the STATUS register is the destination
for an instruction that affects the Z, DC, C, OV or N bits,
then the write to these five bits is disabled.
These bits are set or cleared according to the device
logic. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended. For example, CLRF STATUS will set the Z bit
but leave the other bits unchanged. The STATUS
register then reads back as ‘000u u1uu’. It is recom-
mended, therefore, that only BCF, BSF, SWAPF, MOVFF
and MOVWF instructions are used to alter the STATUS
register because these instructions do not affect the Z,
C, DC, OV or N bits in the STATUS register.
For other instructions not affecting any Status bits, see
the instruction set summaries in Table 24-2 and
Table 24-3.
Note: The C and DC bits operate as a borrow and
digit borrow bit respectively, in subtraction.
REGISTER 6-2: STATUS REGISTER
U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x
— — —NOVZDC
(1) C(2)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-5 Unimplemented: Read as ‘0’
bit 4 N: Negative bit
This bit is used for signed arithmetic (2’s complement). It indicates whether the result was
negative (ALU MSB = 1).
1 = Result was negative
0 = Result was positive
bit 3 OV: Overflow bit
This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the
7-bit magnitude which causes the sign bit (bit 7) to change state.
1 = Overflow occurred for signed arithmetic (in this arithmetic operation)
0 = No overflow occurred
bit 2 Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1 DC: Digit Carry/Borrow bit(1)
For ADDWF, ADDLW, SUBLW and SUBWF instructions:
1 = A carry-out from the 4th low-order bit of the result occurred
0 = No carry-out from the 4th low-order bit of the result
bit 0 C: Carry/Borrow bit(2)
For ADDWF, ADDLW, SUBLW and SUBWF instructions:
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note 1: For borrow, the polarity is reversed. A subtraction is executed by adding the 2’s complement of the second
operand. For rotate (RRF, RLF) instructions, this bit is loaded with either bit 4 or bit 3 of the source register.
2: For borrow, the polarity is reversed. A subtraction is executed by adding the 2’s complement of the second
operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low-order bit of the
source register.
PIC18F85J90 FAMILY
DS39770C-page 80 2010 Microchip Technology Inc.
6.4 Data Addressing Modes
While the program memory can be addressed in only
one way – through the program counter – information
in the data memory space can be addressed in several
ways. For most instructions, the addressing mode is
fixed. Other instructions may use up to three modes,
depending on which operands are used and whether or
not the extended instruction set is enabled.
The addressing modes are:
• Inherent
• Literal
•Direct
•Indirect
An additional addressing mode, Indexed Literal Offset,
is available when the extended instruction set is
enabled (XINST Configuration bit = 1). Its operation is
discussed in greater detail in Section 6.6.1 “Indexed
Addressing with Literal Offset”.
6.4.1 INHERENT AND LITERAL
ADDRESSING
Many PIC18 control instructions do not need any
argument at all; they either perform an operation that
globally affects the device, or they operate implicitly on
one register. This addressing mode is known as Inherent
Addressing. Examples include SLEEP, RESET and DAW.
Other instructions work in a similar way, but require an
additional explicit argument in the opcode. This is
known as Literal Addressing mode, because they
require some literal value as an argument. Examples
include ADDLW and MOVLW, which, respectively, add or
move a literal value to the W register. Other examples
include CALL and GOTO, which include a 20-bit
program memory address.
6.4.2 DIRECT ADDRESSING
Direct Addressing specifies all or part of the source
and/or destination address of the operation within the
opcode itself. The options are specified by the
arguments accompanying the instruction.
In the core PIC18 instruction set, bit-oriented and
byte-oriented instructions use some version of Direct
Addressing by default. All of these instructions include
some 8-bit literal address as their Least Significant
Byte. This address specifies either a register address in
one of the banks of data RAM (Section 6.3.3 “General
Purpose Register File”), or a location in the Access
Bank (Section 6.3.2 “Access Bank”) as the data
source for the instruction.
The Access RAM bit ‘a’ determines how the address is
interpreted. When ‘a’ is ‘1’, the contents of the BSR
(Section 6.3.1 “Bank Select Register”) are used with
the address to determine the complete 12-bit address
of the register. When ‘a’ is ‘0’, the address is interpreted
as being a register in the Access Bank. Addressing that
uses the Access RAM is sometimes also known as
Direct Forced Addressing mode.
A few instructions, such as MOVFF, include the entire
12-bit address (either source or destination) in their
opcodes. In these cases, the BSR is ignored entirely.
The destination of the operation’s results is determined
by the destination bit ‘d’. When ‘d’ is ‘1’, the results are
stored back in the source register, overwriting its origi-
nal contents. When ‘d’ is ‘0’, the results are stored in
the W register. Instructions without the ‘d’ argument
have a destination that is implicit in the instruction; their
destination is either the target register being operated
on or the W register.
6.4.3 INDIRECT ADDRESSING
Indirect Addressing allows the user to access a location
in data memory without giving a fixed address in the
instruction. This is done by using File Select Registers
(FSRs) as pointers to the locations to be read or written
to. Since the FSRs are themselves located in RAM as
Special Function Registers, they can also be directly
manipulated under program control. This makes FSRs
very useful in implementing data structures such as
tables and arrays in data memory.
The registers for Indirect Addressing are also
implemented with Indirect File Operands (INDFs) that
permit automatic manipulation of the pointer value with
auto-incrementing, auto-decrementing or offsetting
with another value. This allows for efficient code using
loops, such as the example of clearing an entire RAM
bank in Example 6-5. It also enables users to perform
Indexed Addressing and other Stack Pointer
operations for program memory in data memory.
EXAMPLE 6-5: HOW TO CLEAR RAM
(BANK 1) USING
INDIRECT ADDRESSING
Note: The execution of some instructions in the
core PIC18 instruction set are changed
when the PIC18 extended instruction set is
enabled. See Section 6.6 “Data Memory
and the Extended Instruction Set” for
more information.
LFSR FSR0, 100h ;
NEXT CLRF POSTINC0 ; Clear INDF
; register then
; inc pointer
BTFSS FSR0H, 1 ; All done with
; Bank1?
BRA NEXT ; NO, clear next
CONTINUE ; YES, continue
2010 Microchip Technology Inc. DS39770C-page 81
PIC18F85J90 FAMILY
6.4.3.1 FSR Registers and the
INDF Operand
At the core of Indirect Addressing are three sets of
registers: FSR0, FSR1 and FSR2. Each represents a
pair of 8-bit registers, FSRnH and FSRnL. The four
upper bits of the FSRnH register are not used, so each
FSR pair holds a 12-bit value. This represents a value
that can address the entire range of the data memory
in a linear fashion. The FSR register pairs, then, serve
as pointers to data memory locations.
Indirect Addressing is accomplished with a set of Indi-
rect File Operands, INDF0 through INDF2. These can
be thought of as “virtual” registers; they are mapped in
the SFR space but are not physically implemented.
Reading or writing to a particular INDF register actually
accesses its corresponding FSR register pair. A read
from INDF1, for example, reads the data at the address
indicated by FSR1H:FSR1L. Instructions that use the
INDF registers as operands actually use the contents
of their corresponding FSR as a pointer to the instruc-
tion’s target. The INDF operand is just a convenient
way of using the pointer.
Because Indirect Addressing uses a full 12-bit address,
data RAM banking is not necessary. Thus, the current
contents of the BSR and the Access RAM bit have no
effect on determining the target address.
FIGURE 6-9: INDIRECT ADDRESSING
FSR1H:FSR1L
0
7
Data Memory
000h
100h
200h
300h
F00h
E00h
FFFh
Bank 0
Bank 1
Bank 2
Bank 14
Bank 15
Bank 3
through
Bank 13
ADDWF, INDF1, 1
07
Using an instruction with one of the
Indirect Addressing registers as the
operand....
...uses the 12-bit address stored in
the FSR pair associated with that
register....
...to determine the data memory
location to be used in that operation.
In this case, the FSR1 pair contains
FCCh. This means the contents of
location FCCh will be added to that
of the W register and stored back in
FCCh.
xxxx1111 11001100
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DS39770C-page 82 2010 Microchip Technology Inc.
6.4.3.2 FSR Registers and POSTINC,
POSTDEC, PREINC and PLUSW
In addition to the INDF operand, each FSR register pair
also has four additional indirect operands. Like INDF,
these are “virtual” registers that cannot be indirectly
read or written to. Accessing these registers actually
accesses the associated FSR register pair, but also
performs a specific action on its stored value. They are:
• POSTDEC: accesses the FSR value, then
automatically decrements it by ‘1’ afterwards
• POSTINC: accesses the FSR value, then
automatically increments it by ‘1’ afterwards
• PREINC: increments the FSR value by ‘1’, then
uses it in the operation
• PLUSW: adds the signed value of the W register
(range of -127 to 128) to that of the FSR and uses
the new value in the operation
In this context, accessing an INDF register uses the
value in the FSR registers without changing them.
Similarly, accessing a PLUSW register gives the FSR
value offset by the value in the W register; neither value
is actually changed in the operation. Accessing the
other virtual registers changes the value of the FSR
registers.
Operations on the FSRs with POSTDEC, POSTINC
and PREINC affect the entire register pair; that is, roll-
overs of the FSRnL register from FFh to 00h carry over
to the FSRnH register. On the other hand, results of
these operations do not change the value of any flags
in the STATUS register (e.g., Z, N, OV, etc.).
The PLUSW register can be used to implement a form
of Indexed Addressing in the data memory space. By
manipulating the value in the W register, users can
reach addresses that are fixed offsets from pointer
addresses. In some applications, this can be used to
implement some powerful program control structure,
such as software stacks, inside of data memory.
6.4.3.3 Operations by FSRs on FSRs
Indirect Addressing operations that target other FSRs
or virtual registers represent special cases. For
example, using an FSR to point to one of the virtual
registers will not result in successful operations. As a
specific case, assume that FSR0H:FSR0L contains
FE7h, the address of INDF1. Attempts to read the
value of the INDF1, using INDF0 as an operand, will
return 00h. Attempts to write to INDF1, using INDF0 as
the operand, will result in a NOP.
On the other hand, using the virtual registers to write to
an FSR pair may not occur as planned. In these cases,
the value will be written to the FSR pair but without any
incrementing or decrementing. Thus, writing to INDF2
or POSTDEC2 will write the same value to the
FSR2H:FSR2L.
Since the FSRs are physical registers mapped in the
SFR space, they can be manipulated through all direct
operations. Users should proceed cautiously when
working on these registers, particularly if their code
uses Indirect Addressing.
Similarly, operations by Indirect Addressing are gener-
ally permitted on all other SFRs. Users should exercise
the appropriate caution that they do not inadvertently
change settings that might affect the operation of the
device.
6.5 Program Memory and the
Extended Instruction Set
The operation of program memory is unaffected by the
use of the extended instruction set.
Enabling the extended instruction set adds five
additional two-word commands to the existing PIC18
instruction set: ADDFSR, CALLW, MOVSF, MOVSS and
SUBFSR. These instructions are executed as described
in Section 6.2.4 “Two-Word Instructions”.
2010 Microchip Technology Inc. DS39770C-page 83
PIC18F85J90 FAMILY
6.6 Data Memory and the Extended
Instruction Set
Enabling the PIC18 extended instruction set (XINST
Configuration bit = 1) significantly changes certain
aspects of data memory and its addressing. Specifically,
the use of the Access Bank for many of the core PIC18
instructions is different; this is due to the introduction of
a new addressing mode for the data memory space.
This mode also alters the behavior of Indirect
Addressing using FSR2 and its associated operands.
What does not change is just as important. The size of
the data memory space is unchanged, as well as its
linear addressing. The SFR map remains the same.
Core PIC18 instructions can still operate in both Direct
and Indirect Addressing mode; inherent and literal
instructions do not change at all. Indirect Addressing
with FSR0 and FSR1 also remains unchanged.
6.6.1 INDEXED ADDRESSING WITH
LITERAL OFFSET
Enabling the PIC18 extended instruction set changes
the behavior of Indirect Addressing using the FSR2
register pair and its associated file operands. Under the
proper conditions, instructions that use the Access
Bank – that is, most bit-oriented and byte-oriented
instructions – can invoke a form of Indexed Addressing
using an offset specified in the instruction. This special
addressing mode is known as Indexed Addressing with
Literal Offset, or Indexed Literal Offset mode.
When using the extended instruction set, this
addressing mode requires the following:
• The use of the Access Bank is forced (‘a’ = 0);
and
• The file address argument is less than or equal to
5Fh.
Under these conditions, the file address of the
instruction is not interpreted as the lower byte of an
address (used with the BSR in Direct Addressing) or as
an 8-bit address in the Access Bank. Instead, the value
is interpreted as an offset value to an Address Pointer
specified by FSR2. The offset and the contents of FSR2
are added to obtain the target address of the operation.
6.6.2 INSTRUCTIONS AFFECTED BY
INDEXED LITERAL OFFSET MODE
Any of the core PIC18 instructions that can use Direct
Addressing are potentially affected by the Indexed
Literal Offset Addressing mode. This includes all
byte-oriented and bit-oriented instructions, or almost
one-half of the standard PIC18 instruction set. Instruc-
tions that only use Inherent or Literal Addressing
modes are unaffected.
Additionally, byte-oriented and bit-oriented instructions
are not affected if they do not use the Access Bank
(Access RAM bit is ‘1’) or include a file address of 60h
or above. Instructions meeting these criteria will
continue to execute as before. A comparison of the
different possible addressing modes when the
extended instruction set is enabled is shown in
Figure 6-10.
Those who desire to use byte-oriented or bit-oriented
instructions in the Indexed Literal Offset mode should
note the changes to assembler syntax for this mode.
This is described in more detail in Section 24.2.1
“Extended Instruction Syntax”.
PIC18F85J90 FAMILY
DS39770C-page 84 2010 Microchip Technology Inc.
FIGURE 6-10: COMPARING ADDRESSING OPTIONS FOR BIT-ORIENTED AND
BYTE-ORIENTED INSTRUCTIONS (EXTENDED INSTRUCTION SET ENABLED)
EXAMPLE INSTRUCTION: ADDWF, f, d, a (Opcode: 0010 01da ffff ffff)
When a = 0 and f 60h:
The instruction executes in
Direct Forced mode. ‘f’ is
interpreted as a location in the
Access RAM between 060h
and FFFh. This is the same as
locations F60h to FFFh
(Bank 15) of data memory.
Locations below 060h are not
available in this addressing
mode.
When a = 0 and f5Fh:
The instruction executes in
Indexed Literal Offset mode. ‘f’
is interpreted as an offset to the
address value in FSR2. The
two are added together to
obtain the address of the target
register for the instruction. The
address can be anywhere in
the data memory space.
Note that in this mode, the
correct syntax is now:
ADDWF [k], d
where ‘k’ is the same as ‘f’.
When a = 1 (all values of f):
The instruction executes in
Direct mode (also known as
Direct Long mode). ‘f’ is
interpreted as a location in
one of the 16 banks of the data
memory space. The bank is
designated by the Bank Select
Register (BSR). The address
can be in any implemented
bank in the data memory
space.
000h
060h
100h
F00h
F40h
FFFh
Valid range
00h
60h
FFh
Data Memory
Access RAM
Bank 0
Bank 1
through
Bank 14
Bank 15
SFRs
000h
060h
100h
F00h
F40h
FFFh
Data Memory
Bank 0
Bank 1
through
Bank 14
Bank 15
SFRs
FSR2H FSR2L
ffffffff001001da
ffffffff001001da
000h
060h
100h
F00h
F40h
FFFh
Data Memory
Bank 0
Bank 1
through
Bank 14
Bank 15
SFRs
for ‘f’
BSR
00000000
2010 Microchip Technology Inc. DS39770C-page 85
PIC18F85J90 FAMILY
6.6.3 MAPPING THE ACCESS BANK IN
INDEXED LITERAL OFFSET MODE
The use of Indexed Literal Offset Addressing mode
effectively changes how the lower part of Access RAM
(00h to 5Fh) is mapped. Rather than containing just the
contents of the bottom part of Bank 0, this mode maps
the contents from Bank 0 and a user-defined “window”
that can be located anywhere in the data memory
space. The value of FSR2 establishes the lower bound-
ary of the addresses mapped into the window, while the
upper boundary is defined by FSR2 plus 95 (5Fh).
Addresses in the Access RAM above 5Fh are mapped
as previously described (see Section 6.3.2 “Access
Bank”). An example of Access Bank remapping in this
addressing mode is shown in Figure 6-11.
Remapping of the Access Bank applies only to opera-
tions using the Indexed Literal Offset mode. Operations
that use the BSR (Access RAM bit is ‘1’) will continue
to use Direct Addressing as before. Any Indirect or
Indexed Addressing operation that explicitly uses any
of the indirect file operands (including FSR2) will con-
tinue to operate as standard Indirect Addressing. Any
instruction that uses the Access Bank, but includes a
register address of greater than 05Fh, will use Direct
Addressing and the normal Access Bank map.
6.6.4 BSR IN INDEXED LITERAL
OFFSET MODE
Although the Access Bank is remapped when the
extended instruction set is enabled, the operation of the
BSR remains unchanged. Direct Addressing, using the
BSR to select the data memory bank, operates in the
same manner as previously described.
FIGURE 6-11: REMAPPING THE ACCESS BANK WITH INDEXED LITERAL
OFFSET ADDRESSING
Data Memory
000h
100h
200h
F60h
F00h
FFFh
Bank 1
Bank 15
Bank 2
through
Bank 14
SFRs
05Fh
ADDWF f, d, a
FSR2H:FSR2L = 120h
Locations in the region
from the FSR2 Pointer
(120h) to the pointer plus
05Fh (17Fh) are mapped
to the bottom of the
Access RAM (000h-05Fh).
Special Function Regis-
ters at F60h through FFFh
are mapped to 60h
through FFh, as usual.
Bank 0 addresses below
5Fh are not available in
this mode. They can still
be addressed by using the
BSR.
Access Bank
00h
FFh
Bank 0
SFRs
Bank 1 “Window”
Not Accessible
Window
Example Situation:
120h
17Fh
5Fh
60h
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DS39770C-page 86 2010 Microchip Technology Inc.
NOTES:
2010 Microchip Technology Inc. DS39770C-page 87
PIC18F85J90 FAMILY
7.0 FLASH PROGRAM MEMORY
The Flash program memory is readable, writable and
erasable during normal operation over the entire VDD
range.
A read from program memory is executed on one byte
at a time. A write to program memory is executed on
blocks of 64 bytes at a time. Program memory is
erased in blocks of 1024 bytes at a time. A bulk erase
operation may not be issued from user code.
Writing or erasing program memory will cease
instruction fetches until the operation is complete. The
program memory cannot be accessed during the write
or erase, therefore, code cannot execute. An internal
programming timer terminates program memory writes
and erases.
A value written to program memory does not need to be
a valid instruction. Executing a program memory
location that forms an invalid instruction results in a
NOP.
7.1 Table Reads and Table Writes
In order to read and write program memory, there are
two operations that allow the processor to move bytes
between the program memory space and the data RAM:
• Table Read (TBLRD)
• Table Write (TBLWT)
The program memory space is 16 bits wide, while the
data RAM space is 8 bits wide. Table reads and table
writes move data between these two memory spaces
through an 8-bit register (TABLAT).
Table read operations retrieve data from program
memory and place it into the data RAM space.
Figure 7-1 shows the operation of a table read with
program memory and data RAM.
Table write operations store data from the data memory
space into holding registers in program memory. The
procedure to write the contents of the holding registers
into program memory is detailed in Section 7.5 “Writing
to Flash Program Memory”. Figure 7-2 shows the
operation of a table write with program memory and data
RAM.
Table operations work with byte entities. A table block
containing data, rather than program instructions, is not
required to be word-aligned. Therefore, a table block can
start and end at any byte address. If a table write is being
used to write executable code into program memory,
program instructions will need to be word-aligned.
FIGURE 7-1: TABLE READ OPERATION
Tab l e P o i n te r(1)
Table Latch (8-bit)
Program Memory
TBLPTRH TBLPTRL
TABLAT
TBLPTRU
Instruction: TBLRD*
Note 1: The Table Pointer register points to a byte in program memory.
Program Memory
(TBLPTR)
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FIGURE 7-2: TABLE WRITE OPERATION
7.2 Control Registers
Several control registers are used in conjunction with
the TBLRD and TBLWT instructions. These include the:
• EECON1 register
• EECON2 register
• TABLAT register
• TBLPTR registers
7.2.1 EECON1 AND EECON2 REGISTERS
The EECON1 register (Register 7-1) is the control
register for memory accesses. The EECON2 register is
not a physical register; it is used exclusively in the
memory write and erase sequences. Reading
EECON2 will read all ‘0’s.
The FREE bit, when set, will allow a program memory
erase operation. When FREE is set, the erase
operation is initiated on the next WR command. When
FREE is clear, only writes are enabled.
The WREN bit, when set, will allow a write operation.
On power-up, the WREN bit is clear. The WRERR bit is
set in hardware when the WR bit is set and cleared
when the internal programming timer expires and the
write operation is complete.
The WR control bit initiates write operations. The bit
cannot be cleared, only set, in software. It is cleared in
hardware at the completion of the write operation.
Table Pointer(1) Table Latch (8-bit)
TBLPTRH TBLPTRL TABLAT
Program Memory
(TBLPTR)
TBLPTRU
Instruction: TBLWT*
Note 1: The Table Pointer actually points to one of 64 holding registers, the address of which is determined by
TBLPTRL<5:0>. The process for physically writing data to the program memory array is discussed in
Section 7.5 “Writing to Flash Program Memory”.
Holding Registers
Program Memory
Note: During normal operation, the WRERR is
read as ‘1’. This can indicate that a write
operation was prematurely terminated by
a Reset, or a write operation was
attempted improperly.
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REGISTER 7-1: EECON1: EEPROM CONTROL REGISTER 1
U-0 U-0 U-0 R/W-0 R/W-x R/W-0 R/S-0 U-0
— — — FREE WRERR WREN WR —
bit 7 bit 0
Legend: U = Unimplemented bit, read as ‘0’
R = Readable bit W = Writable bit S = Settable bit (cannot be cleared in software)
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-5 Unimplemented: Read as ‘0’
bit 4 FREE: Flash Erase Enable bit
1 = Erase the program memory block addressed by TBLPTR on the next WR command (cleared by
completion of erase operation)
0 = Perform write only
bit 3 WRERR: Flash Program Error Flag bit
1 = A write operation is prematurely terminated (any Reset during self-timed programming in normal
operation, or an improper write attempt)
0 = The write operation completed
bit 2 WREN: Flash Program Write Enable bit
1 = Allows write cycles to Flash program memory
0 = Inhibits write cycles to Flash program memory
bit 1 WR: Write Control bit
1 = Initiates a program memory erase cycle or write cycle
(The operation is self-timed and the bit is cleared by hardware once the write is complete. The WR
bit can only be set (not cleared) in software.)
0 = Write cycle is complete
bit 0 Unimplemented: Read as ‘0’
PIC18F85J90 FAMILY
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7.2.2 TABLE LATCH REGISTER (TABLAT)
The Table Latch (TABLAT) is an 8-bit register mapped
into the SFR space. The Table Latch register is used to
hold 8-bit data during data transfers between program
memory and data RAM.
7.2.3 TABLE POINTER REGISTER
(TBLPTR)
The Table Pointer (TBLPTR) register addresses a byte
within the program memory. The TBLPTR is comprised
of three SFR registers: Table Pointer Upper Byte, Table
Pointer High Byte and Table Pointer Low Byte
(TBLPTRU:TBLPTRH:TBLPTRL). These three regis-
ters join to form a 22-bit wide pointer. The low-order
21 bits allow the device to address up to 2 Mbytes of
program memory space. The 22nd bit allows access to
the device ID, the user ID and the Configuration bits.
The Table Pointer register, TBLPTR, is used by the
TBLRD and TBLWT instructions. These instructions can
update the TBLPTR in one of four ways based on the
table operation. These operations are shown in
Table 7-1. These operations on the TBLPTR only affect
the low-order 21 bits.
7.2.4 TABLE POINTER BOUNDARIES
TBLPTR is used in reads, writes and erases of the
Flash program memory.
When a TBLRD is executed, all 22 bits of the TBLPTR
determine which byte is read from program memory
into TABLAT.
When a TBLWT is executed, the seven LSbs of the
Table Pointer register (TBLPTR<6:0>) determine which
of the 64 program memory holding registers is written
to. When the timed write to program memory begins
(via the WR bit), the 12 MSbs of the TBLPTR
(TBLPTR<21:10>) determine which program memory
block of 1024 bytes is written to. For more detail, see
Section 7.5 “Writing to Flash Program Memory”.
When an erase of program memory is executed, the
12 MSbs of the Table Pointer register point to the
1024-byte block that will be erased. The Least
Significant bits are ignored.
Figure 7-3 describes the relevant boundaries of the
TBLPTR based on Flash program memory operations.
TABLE 7-1: TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS
FIGURE 7-3: TABLE POINTER BOUNDARIES BASED ON OPERATION
Example Operation on Table Pointer
TBLRD*
TBLWT* TBLPTR is not modified
TBLRD*+
TBLWT*+ TBLPTR is incremented after the read/write
TBLRD*-
TBLWT*- TBLPTR is decremented after the read/write
TBLRD+*
TBLWT+* TBLPTR is incremented before the read/write
21 16 15 87 0
ERASE: TBLPTR<21:10>
TABLE WRITE: TBLPTR<21:6>
TABLE READ: TBLPTR<21:0>
TBLPTRLTBLPTRH
TBLPTRU
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7.3 Reading the Flash Program Memory
The TBLRD instruction is used to retrieve data from
program memory and places it into data RAM. Table
reads from program memory are performed one byte at
a time.
The TBLPTR points to a byte address in program
space. Executing TBLRD places the byte pointed to into
TABLAT. In addition, the TBLPTR can be modified
automatically for the next table read operation.
The internal program memory is typically organized by
words. The Least Significant bit of the address selects
between the high and low bytes of the word. Figure 7-4
shows the interface between the internal program
memory and the TABLAT.
FIGURE 7-4: READS FROM FLASH PROGRAM MEMORY
EXAMPLE 7-1: READING A FLASH PROGRAM MEMORY WORD
(Even Byte Address)
Program Memory
(Odd Byte Address)
TBLRD TABLAT
TBLPTR = xxxxx1
FETCH
Instruction Register
(IR) Read Register
TBLPTR = xxxxx0
MOVLW CODE_ADDR_UPPER ; Load TBLPTR with the base
MOVWF TBLPTRU ; address of the word
MOVLW CODE_ADDR_HIGH
MOVWF TBLPTRH
MOVLW CODE_ADDR_LOW
MOVWF TBLPTRL
READ_WORD TBLRD*+ ; read into TABLAT and increment
MOVF TABLAT, W ; get data
MOVWF WORD_EVEN
TBLRD*+ ; read into TABLAT and increment
MOVF TABLAT, W ; get data
MOVWF WORD_ODD
PIC18F85J90 FAMILY
DS39770C-page 92 2010 Microchip Technology Inc.
7.4 Erasing Flash Program Memory
The minimum erase block is 512 words or 1024 bytes.
Only through the use of an external programmer, or
through ICSP control, can larger blocks of program
memory be Bulk Erased. Word erase in the Flash array
is not supported.
When initiating an erase sequence from the micro-
controller itself, a block of 1024 bytes of program
memory is erased. The Most Significant 12 bits of the
TBLPTR<21:10> point to the block being erased;
TBLPTR<9:0> are ignored.
The EECON1 register commands the erase operation.
The WREN bit must be set to enable write operations.
The FREE bit is set to select an erase operation. For
protection, the write initiate sequence for EECON2
must be used.
A long write is necessary for erasing the internal Flash.
Instruction execution is halted while in a long write
cycle. The long write will be terminated by the internal
programming timer.
7.4.1 FLASH PROGRAM MEMORY
ERASE SEQUENCE
The sequence of events for erasing a block of internal
program memory location is:
1. Load the Table Pointer register with the address
of the block being erased.
2. Set the WREN and FREE bits (EECON1<2,4>)
to enable the erase operation.
3. Disable interrupts.
4. Write 55h to EECON2.
5. Write 0AAh to EECON2.
6. Set the WR bit; this will begin the erase cycle.
7. The CPU will stall for the duration of the erase
for TIE (see parameter D133B).
8. Re-enable interrupts.
EXAMPLE 7-2: ERASING A FLASH PROGRAM MEMORY BLOCK
MOVLW CODE_ADDR_UPPER ; load TBLPTR with the base
MOVWF TBLPTRU ; address of the memory block
MOVLW CODE_ADDR_HIGH
MOVWF TBLPTRH
MOVLW CODE_ADDR_LOW
MOVWF TBLPTRL
ERASE_BLOCK BSF EECON1, WREN ; enable write to memory
BSF EECON1, FREE ; enable Erase operation
BCF INTCON, GIE ; disable interrupts
Required MOVLW 55h
Sequence MOVWF EECON2 ; write 55h
MOVLW 0AAh
MOVWF EECON2 ; write 0AAh
BSF EECON1, WR ; start erase (CPU stall)
BSF INTCON, GIE ; re-enable interrupts
2010 Microchip Technology Inc. DS39770C-page 93
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7.5 Writing to Flash Program Memory
The minimum programming block is 32 words or
64 bytes. Word or byte programming is not supported.
Table writes are used internally to load the holding
registers needed to program the Flash memory. There
are 64 holding registers used by the table writes for
programming.
Since the Table Latch (TABLAT) is only a single byte, the
TBLWT instruction may need to be executed 64 times for
each programming operation. All of the table write oper-
ations will essentially be short writes because only the
holding registers are written. At the end of updating the
64 holding registers, the EECON1 register must be
written to in order to start the programming operation
with a long write.
The long write is necessary for programming the inter-
nal Flash. Instruction execution is halted while in a long
write cycle. The long write will be terminated by the
internal programming timer.
The on-chip timer controls the write time. The
write/erase voltages are generated by an on-chip
charge pump, rated to operate over the voltage range
of the device.
FIGURE 7-5: TABLE WRITES TO FLASH PROGRAM MEMORY
7.5.1 FLASH PROGRAM MEMORY WRITE
SEQUENCE
The sequence of events for programming an internal
program memory location should be:
1. Read 1024 bytes into RAM.
2. Update data values in RAM as necessary.
3. Load the Table Pointer register with the address
being erased.
4. Execute the block erase procedure.
5. Load the Table Pointer register with the address
of the first byte being written, minus 1.
6. Write the 64 bytes into the holding registers with
auto-increment.
7. Set the WREN bit (EECON1<2>) to enable byte
writes.
8. Disable interrupts.
9. Write 55h to EECON2.
10. Write 0AAh to EECON2.
11. Set the WR bit; this will begin the write cycle.
12. The CPU will stall for the duration of the write for
TIW (see parameter D133A).
13. Re-enable interrupts.
14. Repeat steps 6 through 13 until all 1024 bytes
are written to program memory.
15. Verify the memory (table read).
An example of the required code is shown in
Example 7-3 on the following page.
Note 1: Unlike previous PIC® devices, members
of the PIC18F85J90 family do not reset
the holding registers after a write occurs.
The holding registers must be cleared or
overwritten before a programming
sequence.
2: To maintain the endurance of the program
memory cells, each Flash byte should not
be programmed more than one time
between erase operations. Before
attempting to modify the contents of the
target cell a second time, a block erase of
the target block, or a bulk erase of the
entire memory, must be performed.
TABLAT
TBLPTR = xxxx3FTBLPTR = xxxxx1TBLPTR = xxxxx0
Write Register
TBLPTR = xxxxx2
Program Memory
Holding Register Holding Register Holding Register Holding Register
88 8 8
Note: Before setting the WR bit, the Table
Pointer address needs to be within the
intended address range of the 64 bytes in
the holding register.
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EXAMPLE 7-3: WRITING TO FLASH PROGRAM MEMORY
MOVLW CODE_ADDR_UPPER ; Load TBLPTR with the base address
MOVWF TBLPTRU ; of the memory block, minus 1
MOVLW CODE_ADDR_HIGH
MOVWF TBLPTRH
MOVLW CODE_ADDR_LOW
MOVWF TBLPTRL
ERASE_BLOCK BSF EECON1, WREN ; enable write to memory
BSF EECON1, FREE ; enable Erase operation
BCF INTCON, GIE ; disable interrupts
MOVLW 55h
MOVWF EECON2 ; write 55h
MOVLW 0AAh
MOVWF EECON2 ; write 0AAh
BSF EECON1, WR ; start erase (CPU stall)
BSF INTCON, GIE ; re-enable interrupts
MOVLW D'16'
MOVWF WRITE_COUNTER ; Need to write 16 blocks of 64 to write
; one erase block of 1024
RESTART_BUFFER MOVLW D'64'
MOVWF COUNTER
MOVLW BUFFER_ADDR_HIGH ; point to buffer
MOVWF FSR0H
MOVLW BUFFER_ADDR_LOW
MOVWF FSR0L
FILL_BUFFER ... ; read the new data from I2C, SPI,
; PSP, USART, etc.
WRITE_BUFFER MOVLW D’64 ; number of bytes in holding register
MOVWF COUNTER
WRITE_BYTE_TO_HREGSMOVFF POSTINC0, WREG ; get low byte of buffer data
MOVWF TABLAT ; present data to table latch
TBLWT+* ; write data, perform a short write
; to internal TBLWT holding register.
DECFSZ COUNTER ; loop until buffers are full
BRA WRITE_BYTE_TO_HREGS
PROGRAM_MEMORY BSF EECON1, WREN ; enable write to memory
BCF INTCON, GIE ; disable interrupts
MOVLW 55h
Required MOVWF EECON2 ; write 55h
Sequence MOVLW 0AAh
MOVWF EECON2 ; write 0AAh
BSF EECON1, WR ; start program (CPU stall)
BSF INTCON, GIE ; re-enable interrupts
BCF EECON1, WREN ; disable write to memory
DECFSZ WRITE_COUNTER ; done with one write cycle
BRA RESTART_BUFFER ; if not done replacing the erase block
2010 Microchip Technology Inc. DS39770C-page 95
PIC18F85J90 FAMILY
7.5.2 WRITE VERIFY
Depending on the application, good programming
practice may dictate that the value written to the
memory should be verified against the original value.
This should be used in applications where excessive
writes can stress bits near the specification limit.
7.5.3 UNEXPECTED TERMINATION OF
WRITE OPERATION
If a write is terminated by an unplanned event, such as
loss of power or an unexpected Reset, the memory
location just programmed should be verified and repro-
grammed if needed. If the write operation is interrupted
by a MCLR Reset or a WDT Time-out Reset during
normal operation, the user can check the WRERR bit
and rewrite the location(s) as needed.
7.6 Flash Program Operation During
Code Protection
See Section 23.6 “Program Verification and Code
Protection” for details on code protection of Flash
program memory.
TABLE 7-2: REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values on
page
TBLPTRU —— bit 21 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) 57
TBPLTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 57
TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) 57
TABLAT Program Memory Table Latch 57
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 57
EECON2 EEPROM Control Register 2 (not a physical register) 59
EECON1 — — — FREE WRERR WREN WR —59
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during program memory access.
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NOTES:
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PIC18F85J90 FAMILY
8.0 8 x 8 HARDWARE MULTIPLIER
8.1 Introduction
All PIC18 devices include an 8 x 8 hardware multiplier
as part of the ALU. The multiplier performs an unsigned
operation and yields a 16-bit result that is stored in the
Product register pair, PRODH:PRODL. The multiplier’s
operation does not affect any flags in the STATUS
register.
Making multiplication a hardware operation allows it to
be completed in a single instruction cycle. This has the
advantages of higher computational throughput and
reduced code size for multiplication algorithms and
allows the PIC18 devices to be used in many applica-
tions previously reserved for digital signal processors.
A comparison of various hardware and software
multiply operations, along with the savings in memory
and execution time, is shown in Table 8-1.
8.2 Operation
Example 8-1 shows the instruction sequence for an 8 x 8
unsigned multiplication. Only one instruction is required
when one of the arguments is already loaded in the
WREG register.
Example 8-2 shows the sequence to do an 8 x 8 signed
multiplication. To account for the sign bits of the argu-
ments, each argument’s Most Significant bit (MSb) is
tested and the appropriate subtractions are done.
EXAMPLE 8-1: 8 x 8 UNSIGNED
MULTIPLY ROUTINE
EXAMPLE 8-2: 8 x 8 SIGNED MULTIPLY
ROUTINE
TABLE 8-1: PERFORMANCE COMPARISON FOR VARIOUS MULTIPLY OPERATIONS
MOVF ARG1, W ;
MULWF ARG2 ; ARG1 * ARG2 ->
; PRODH:PRODL
MOVF ARG1, W
MULWF ARG2 ; ARG1 * ARG2 ->
; PRODH:PRODL
BTFSC ARG2, SB ; Test Sign Bit
SUBWF PRODH, F ; PRODH = PRODH
; - ARG1
MOVF ARG2, W
BTFSC ARG1, SB ; Test Sign Bit
SUBWF PRODH, F ; PRODH = PRODH
; - ARG2
Routine Multiply Method
Program
Memory
(Words)
Cycles
(Max)
Time
@ 40 MHz @ 10 MHz @ 4 MHz
8 x 8 unsigned Without hardware multiply 13 69 6.9 s27.6 s69 s
Hardware multiply 1 1 100 ns 400 ns 1 s
8 x 8 signed Without hardware multiply 33 91 9.1 s36.4 s91 s
Hardware multiply 6 6 600 ns 2.4 s6 s
16 x 16 unsigned Without hardware multiply 21 242 24.2 s96.8 s242 s
Hardware multiply 28 28 2.8 s 11.2 s28 s
16 x 16 signed Without hardware multiply 52 254 25.4 s 102.6 s254 s
Hardware multiply 35 40 4.0 s16.0 s40 s
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DS39770C-page 98 2010 Microchip Technology Inc.
Example 8-3 shows the sequence to do a 16 x 16
unsigned multiplication. Equation 8-1 shows the
algorithm that is used. The 32-bit result is stored in four
registers (RES3:RES0).
EQUATION 8-1: 16 x 16 UNSIGNED
MULTIPLICATION
ALGORITHM
EXAMPLE 8-3: 16 x 16 UNSIGNED
MULTIPLY ROUTINE
Example 8-4 shows the sequence to do a 16 x 16
signed multiply. Equation 8-2 shows the algorithm
used. The 32-bit result is stored in four registers
(RES3:RES0). To account for the sign bits of the
arguments, the MSb for each argument pair is tested
and the appropriate subtractions are done.
EQUATION 8-2: 16 x 16 SIGNED
MULTIPLICATION
ALGORITHM
EXAMPLE 8-4: 16 x 16 SIGNED
MULTIPLY ROUTINE
RES3:RES0 = ARG1H:ARG1L ARG2H:ARG2L
= (ARG1H ARG2H 216) +
(ARG1H ARG2L 28) +
(ARG1L ARG2H 28) +
(ARG1L ARG2L)
MOVF ARG1L, W
MULWF ARG2L ; ARG1L * ARG2L->
; PRODH:PRODL
MOVFF PRODH, RES1 ;
MOVFF PRODL, RES0 ;
; MOVF ARG1H, W
MULWF ARG2H ; ARG1H * ARG2H->
; PRODH:PRODL
MOVFF PRODH, RES3 ;
MOVFF PRODL, RES2 ;
; MOVF ARG1L, W
MULWF ARG2H ; ARG1L * ARG2H->
; PRODH:PRODL
MOVF PRODL, W ;
ADDWF RES1, F ; Add cross
MOVF PRODH, W ; products
ADDWFC RES2, F ;
CLRF WREG ;
ADDWFC RES3, F ;
; MOVF ARG1H, W ;
MULWF ARG2L ; ARG1H * ARG2L->
; PRODH:PRODL
MOVF PRODL, W ;
ADDWF RES1, F ; Add cross
MOVF PRODH, W ; products
ADDWFC RES2, F ;
CLRF WREG ;
ADDWFC RES3, F ;
RES3:RES0 = ARG1H:ARG1L ARG2H:ARG2L
= (ARG1H ARG2H 216) +
(ARG1H ARG2L 28) +
(ARG1L ARG2H 28) +
(ARG1L ARG2L) +
(-1 ARG2H<7> ARG1H:ARG1L 216) +
(-1 ARG1H<7> ARG2H:ARG2L 216)
MOVF ARG1L, W
MULWF ARG2L ; ARG1L * ARG2L ->
; PRODH:PRODL
MOVFF PRODH, RES1 ;
MOVFF PRODL, RES0 ;
; MOVF ARG1H, W
MULWF ARG2H ; ARG1H * ARG2H ->
; PRODH:PRODL
MOVFF PRODH, RES3 ;
MOVFF PRODL, RES2 ;
; MOVF ARG1L, W
MULWF ARG2H ; ARG1L * ARG2H ->
; PRODH:PRODL
MOVF PRODL, W ;
ADDWF RES1, F ; Add cross
MOVF PRODH, W ; products
ADDWFC RES2, F ;
CLRF WREG ;
ADDWFC RES3, F ;
; MOVF ARG1H, W ;
MULWF ARG2L ; ARG1H * ARG2L ->
; PRODH:PRODL
MOVF PRODL, W ;
ADDWF RES1, F ; Add cross
MOVF PRODH, W ; products
ADDWFC RES2, F ;
CLRF WREG ;
ADDWFC RES3, F ;
; BTFSS ARG2H, 7 ; ARG2H:ARG2L neg?
BRA SIGN_ARG1 ; no, check ARG1
MOVF ARG1L, W ;
SUBWF RES2 ;
MOVF ARG1H, W ;
SUBWFB RES3
;
SIGN_ARG1
BTFSS ARG1H, 7 ; ARG1H:ARG1L neg?
BRA CONT_CODE ; no, done
MOVF ARG2L, W ;
SUBWF RES2 ;
MOVF ARG2H, W ;
SUBWFB RES3
;
CONT_CODE
:
2010 Microchip Technology Inc. DS39770C-page 99
PIC18F85J90 FAMILY
9.0 INTERRUPTS
Members of the PIC18F85J90 family of devices have
multiple interrupt sources and an interrupt priority
feature that allows most interrupt sources to be
assigned a high-priority level or a low-priority level. The
high-priority interrupt vector is at 0008h and the
low-priority interrupt vector is at 0018h. High-priority
interrupt events will interrupt any low-priority interrupts
that may be in progress.
There are thirteen registers which are used to control
interrupt operation. These registers are:
• RCON
•INTCON
• INTCON2
• INTCON3
• PIR1, PIR2, PIR3
• PIE1, PIE2, PIE3
• IPR1, IPR2, IPR3
It is recommended that the Microchip header files
supplied with MPLAB® IDE be used for the symbolic bit
names in these registers. This allows the
assembler/compiler to automatically take care of the
placement of these bits within the specified register.
In general, interrupt sources have three bits to control
their operation. They are:
•Flag bit to indicate that an interrupt event
occurred
•Enable bit that allows program execution to
branch to the interrupt vector address when the
flag bit is set
•Priority bit to select high priority or low priority
The interrupt priority feature is enabled by setting the
IPEN bit (RCON<7>). When interrupt priority is
enabled, there are two bits which enable interrupts
globally. Setting the GIEH bit (INTCON<7>) enables all
interrupts that have the priority bit set (high priority).
Setting the GIEL bit (INTCON<6>) enables all
interrupts that have the priority bit cleared (low priority).
When the interrupt flag, enable bit and appropriate
global interrupt enable bit are set, the interrupt will
vector immediately to address 0008h or 0018h,
depending on the priority bit setting. Individual
interrupts can be disabled through their corresponding
enable bits.
When the IPEN bit is cleared (default state), the
interrupt priority feature is disabled and interrupts are
compatible with PIC® mid-range devices. In
Compatibility mode, the interrupt priority bits for each
source have no effect. INTCON<6> is the PEIE bit
which enables/disables all peripheral interrupt sources.
INTCON<7> is the GIE bit which enables/disables all
interrupt sources. All interrupts branch to address
0008h in Compatibility mode.
When an interrupt is responded to, the global interrupt
enable bit is cleared to disable further interrupts. If the
IPEN bit is cleared, this is the GIE bit. If interrupt priority
levels are used, this will be either the GIEH or GIEL bit.
High-priority interrupt sources can interrupt a
low-priority interrupt. Low-priority interrupts are not
processed while high-priority interrupts are in progress.
The return address is pushed onto the stack and the
PC is loaded with the interrupt vector address (0008h
or 0018h). Once in the Interrupt Service Routine, the
source(s) of the interrupt can be determined by polling
the interrupt flag bits. The interrupt flag bits must be
cleared in software before re-enabling interrupts to
avoid recursive interrupts.
The “return from interrupt” instruction, RETFIE, exits
the interrupt routine and sets the GIE bit (GIEH or GIEL
if priority levels are used) which re-enables interrupts.
For external interrupt events, such as the INT pins or
the PORTB input change interrupt, the interrupt latency
will be three to four instruction cycles. The exact
latency is the same for one or two-cycle instructions.
Individual interrupt flag bits are set regardless of the
status of their corresponding enable bit or the GIE bit.
Note: Do not use the MOVFF instruction to modify
any of the Interrupt Control registers while
any interrupt is enabled. Doing so may
cause erratic microcontroller behavior.
PIC18F85J90 FAMILY
DS39770C-page 100 2010 Microchip Technology Inc.
FIGURE 9-1: PIC18F85J90 FAMILY INTERRUPT LOGIC
TMR0IE
GIE/GIEH
PEIE/GIEL
Wake-up if in
Interrupt to CPU
Vector to Location
0008h
INT2IF
INT2IE
INT2IP
INT1IF
INT1IE
INT1IP
TMR0IF
TMR0IE
TMR0IP
RBIF
RBIE
RBIP
IPEN
TMR0IF
TMR0IP
INT1IF
INT1IE
INT1IP
INT2IF
INT2IE
INT2IP
RBIF
RBIE
RBIP
INT0IF
INT0IE
PEIE/GIEL
Interrupt to CPU
Vector to Location
IPEN
IPEN
0018h
PIR1<6:3,1:0>
PIE1<6:3,1:0>
IPR1<6:3,1:0>
High-Priority Interrupt Generation
Low-Priority Interrupt Generation
Idle or Sleep modes
GIE/GIEH
INT3IF
INT3IE
INT3IP
INT3IF
INT3IE
INT3IP
PIR2<7:6,3:1>
PIE2<7:6 3:1>
IPR2<7:6,3:1>
PIR3<6:4,2:1>
PIE3<6:4,2:1>
IPR3<6:4,2:1>
PIR1<6:3,1:0>
PIE1<6:3,1:0>
IPR1<6:3,1:0>
PIR2<7:6,3:1>
PIE2<7:6,3:1>
IPR2<7:6,3:1>
PIR3<6:4,2:1>
PIE3<6:4,2:1>
IPR3<6:4,2:1>
IPEN
2010 Microchip Technology Inc. DS39770C-page 101
PIC18F85J90 FAMILY
9.1 INTCON Registers
The INTCON registers are readable and writable
registers which contain various enable, priority and flag
bits.
Note: Interrupt flag bits are set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the global
interrupt enable bit. User software should
ensure the appropriate interrupt flag bits
are clear prior to enabling an interrupt.
This feature allows for software polling.
REGISTER 9-1: INTCON: INTERRUPT CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x
GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF(1)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 GIE/GIEH: Global Interrupt Enable bit
When IPEN = 0:
1 = Enables all unmasked interrupts
0 = Disables all interrupts
When IPEN = 1:
1 = Enables all high-priority interrupts
0 = Disables all interrupts
bit 6 PEIE/GIEL: Peripheral Interrupt Enable bit
When IPEN = 0:
1 = Enables all unmasked peripheral interrupts
0 = Disables all peripheral interrupts
When IPEN = 1:
1 = Enables all low-priority peripheral interrupts
0 = Disables all low-priority peripheral interrupts
bit 5 TMR0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 overflow interrupt
0 = Disables the TMR0 overflow interrupt
bit 4 INT0IE: INT0 External Interrupt Enable bit
1 = Enables the INT0 external interrupt
0 = Disables the INT0 external interrupt
bit 3 RBIE: RB Port Change Interrupt Enable bit
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
bit 2 TMR0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
bit 1 INT0IF: INT0 External Interrupt Flag bit
1 = The INT0 external interrupt occurred (must be cleared in software)
0 = The INT0 external interrupt did not occur
bit 0 RBIF: RB Port Change Interrupt Flag bit(1)
1 = At least one of the RB<7:4> pins changed state (must be cleared in software)
0 = None of the RB<7:4> pins have changed state
Note 1: A mismatch condition will continue to set this bit. Reading PORTB, and then waiting one additional instruction
cycle, will end the mismatch condition and allow the bit to be cleared.
PIC18F85J90 FAMILY
DS39770C-page 102 2010 Microchip Technology Inc.
REGISTER 9-2: INTCON2: INTERRUPT CONTROL REGISTER 2
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
RBPU INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INT3IP RBIP
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 RBPU: PORTB Pull-up Enable bit
1 = All PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual port latch values
bit 6 INTEDG0: External Interrupt 0 Edge Select bit
1 = Interrupt on rising edge
0 = Interrupt on falling edge
bit 5 INTEDG1: External Interrupt 1 Edge Select bit
1 = Interrupt on rising edge
0 = Interrupt on falling edge
bit 4 INTEDG2: External Interrupt 2 Edge Select bit
1 = Interrupt on rising edge
0 = Interrupt on falling edge
bit 3 INTEDG3: External Interrupt 3 Edge Select bit
1 = Interrupt on rising edge
0 = Interrupt on falling edge
bit 2 TMR0IP: TMR0 Overflow Interrupt Priority bit
1 =High priority
0 = Low priority
bit 1 INT3IP: INT3 External Interrupt Priority bit
1 =High priority
0 = Low priority
bit 0 RBIP: RB Port Change Interrupt Priority bit
1 =High priority
0 = Low priority
Note: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding
enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits
are clear prior to enabling an interrupt. This feature allows for software polling.
2010 Microchip Technology Inc. DS39770C-page 103
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REGISTER 9-3: INTCON3: INTERRUPT CONTROL REGISTER 3
R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
INT2IP INT1IP INT3IE INT2IE INT1IE INT3IF INT2IF INT1IF
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 INT2IP: INT2 External Interrupt Priority bit
1 =High priority
0 = Low priority
bit 6 INT1IP: INT1 External Interrupt Priority bit
1 =High priority
0 = Low priority
bit 5 INT3IE: INT3 External Interrupt Enable bit
1 = Enables the INT3 external interrupt
0 = Disables the INT3 external interrupt
bit 4 INT2IE: INT2 External Interrupt Enable bit
1 = Enables the INT2 external interrupt
0 = Disables the INT2 external interrupt
bit 3 INT1IE: INT1 External Interrupt Enable bit
1 = Enables the INT1 external interrupt
0 = Disables the INT1 external interrupt
bit 2 INT3IF: INT3 External Interrupt Flag bit
1 = The INT3 external interrupt occurred (must be cleared in software)
0 = The INT3 external interrupt did not occur
bit 1 INT2IF: INT2 External Interrupt Flag bit
1 = The INT2 external interrupt occurred (must be cleared in software)
0 = The INT2 external interrupt did not occur
bit 0 INT1IF: INT1 External Interrupt Flag bit
1 = The INT1 external interrupt occurred (must be cleared in software)
0 = The INT1 external interrupt did not occur
Note: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding
enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits
are clear prior to enabling an interrupt. This feature allows for software polling.
PIC18F85J90 FAMILY
DS39770C-page 104 2010 Microchip Technology Inc.
9.2 PIR Registers
The PIR registers contain the individual flag bits for the
peripheral interrupts. Due to the number of peripheral
interrupt sources, there are three Peripheral Interrupt
Request (Flag) registers (PIR1, PIR2, PIR3).
Note 1: Interrupt flag bits are set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the Global
Interrupt Enable bit, GIE (INTCON<7>).
2: User software should ensure the
appropriate interrupt flag bits are cleared
prior to enabling an interrupt and after
servicing that interrupt.
REGISTER 9-4: PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1
U-0 R/W-0 R-0 R-0 R/W-0 U-0 R/W-0 R/W-0
— ADIF RC1IF TX1IF SSPIF —TMR2IFTMR1IF
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 Unimplemented: Read as ‘0’
bit 6 ADIF: A/D Converter Interrupt Flag bit
1 = An A/D conversion completed (must be cleared in software)
0 = The A/D conversion is not complete
bit 5 RC1IF: EUSART Receive Interrupt Flag bit
1 = The EUSART receive buffer, RCREG1, is full (cleared when RCREG1 is read)
0 = The EUSART receive buffer is empty
bit 4 TX1IF: EUSART Transmit Interrupt Flag bit
1 = The EUSART transmit buffer, TXREG1, is empty (cleared when TXREG1 is written)
0 = The EUSART transmit buffer is full
bit 3 SSPIF: Master Synchronous Serial Port Interrupt Flag bit
1 = The transmission/reception is complete (must be cleared in software)
0 = Waiting to transmit/receive
bit 2 Unimplemented: Read as ‘0’
bit 1 TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1 = TMR2 to PR2 match occurred (must be cleared in software)
0 = No TMR2 to PR2 match occurred
bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overflowed (must be cleared in software)
0 = TMR1 register did not overflow
2010 Microchip Technology Inc. DS39770C-page 105
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REGISTER 9-5: PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2
R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 U-0
OSCFIF CMIF ——BCLIFLVDIFTMR3IF—
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 OSCFIF: Oscillator Fail Interrupt Flag bit
1 = Device oscillator failed, clock input has changed to INTOSC (must be cleared in software)
0 = Device clock operating
bit 6 CMIF: Comparator Interrupt Flag bit
1 = Comparator input has changed (must be cleared in software)
0 = Comparator input has not changed
bit 5-4 Unimplemented: Read as ‘0’
bit 3 BCLIF: Bus Collision Interrupt Flag bit
1 = A bus collision occurred (must be cleared in software)
0 = No bus collision occurred
bit 2 LVDIF: Low-Voltage Detect Interrupt Flag bit
1 = A low-voltage condition occurred (must be cleared in software)
0 = The device voltage is above the regulator’s low-voltage trip point
bit 1 TMR3IF: TMR3 Overflow Interrupt Flag bit
1 = TMR3 register overflowed (must be cleared in software)
0 = TMR3 register did not overflow
bit 0 Unimplemented: Read as ‘0’
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DS39770C-page 106 2010 Microchip Technology Inc.
REGISTER 9-6: PIR3: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 3
U-0 R/W-0 R-0 R-0 U-0 R/W-0 R/W-0 U-0
— LCDIF RC2IF TX2IF — CCP2IF CCP1IF —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 Unimplemented: Read as ‘0’
bit 6 LCDIF: LCD Interrupt Flag bit (valid when Type-B waveform with Non-Static mode is selected)
1 = LCD data of all COMs is output (must be cleared in software)
0 = LCD data of all COMs is not yet output
bit 5 RC2IF: AUSART Receive Interrupt Flag bit
1 = The AUSART receive buffer, RCREG2, is full (cleared when RCREG2 is read)
0 = The AUSART receive buffer is empty
bit 4 TX2IF: AUSART Transmit Interrupt Flag bit
1 = The AUSART transmit buffer, TXREG2, is empty (cleared when TXREG2 is written)
0 = The AUSART transmit buffer is full
bit 3 Unimplemented: Read as ‘0’
bit 2 CCP2IF: CCP2 Interrupt Flag bit
Capture mode:
1 = A TMR1/TMR3 register capture occurred (must be cleared in software)
0 = No TMR1/TMR3 register capture occurred
Compare mode:
1 = A TMR1/TMR3 register compare match occurred (must be cleared in software)
0 = No TMR1/TMR3 register compare match occurred
PWM mode:
Unused in this mode.
bit 1 CCP1IF: CCP1 Interrupt Flag bit
Capture mode:
1 = A TMR1/TMR3 register capture occurred (must be cleared in software)
0 = No TMR1/TMR3 register capture occurred
Compare mode:
1 = A TMR1/TMR3 register compare match occurred (must be cleared in software)
0 = No TMR1/TMR3 register compare match occurred
PWM mode:
Unused in this mode.
bit 0 Unimplemented: Read as ‘0’
2010 Microchip Technology Inc. DS39770C-page 107
PIC18F85J90 FAMILY
9.3 PIE Registers
The PIE registers contain the individual enable bits for
the peripheral interrupts. Due to the number of
peripheral interrupt sources, there are three Peripheral
Interrupt Enable registers (PIE1, PIE2, PIE3). When
IPEN = 0, the PEIE bit must be set to enable any of
these peripheral interrupts.
REGISTER 9-7: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1
U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0
— ADIE RC1IE TX1IE SSPIE — TMR2IE TMR1IE
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 Unimplemented: Read as ‘0’
bit 6 ADIE: A/D Converter Interrupt Enable bit
1 = Enables the A/D interrupt
0 = Disables the A/D interrupt
bit 5 RC1IE: EUSART Receive Interrupt Enable bit
1 = Enables the EUSART receive interrupt
0 = Disables the EUSART receive interrupt
bit 4 TX1IE: EUSART Transmit Interrupt Enable bit
1 = Enables the EUSART transmit interrupt
0 = Disables the EUSART transmit interrupt
bit 3 SSPIE: Master Synchronous Serial Port Interrupt Enable bit
1 = Enables the MSSP interrupt
0 = Disables the MSSP interrupt
bit 2 Unimplemented: Read as ‘0’
bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt
bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt
PIC18F85J90 FAMILY
DS39770C-page 108 2010 Microchip Technology Inc.
REGISTER 9-8: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2
R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 U-0
OSCFIE CMIE —— BCLIE LVDIE TMR3IE —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 OSCFIE: Oscillator Fail Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 6 CMIE: Comparator Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 5-4 Unimplemented: Read as ‘0’
bit 3 BCLIE: Bus Collision Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 2 LVDIE: Low-Voltage Detect Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 1 TMR3IE: TMR3 Overflow Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 0 Unimplemented: Read as ‘0’
2010 Microchip Technology Inc. DS39770C-page 109
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REGISTER 9-9: PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3
U-0 R/W-0 R-0 R-0 U-0 R/W-0 R/W-0 U-0
— LCDIE RC2IE TX2IE — CCP2IE CCP1IE —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 Unimplemented: Read as ‘0’
bit 6 LCDIE: LCD Interrupt Enable bit (valid when Type-B waveform with Non-Static mode is selected)
1 = Enabled
0 = Disabled
bit 5 RC2IE: AUSART Receive Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 4 TX2IE: AUSART Transmit Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 3 Unimplemented: Read as ‘0’
bit 2 CCP2IE: CCP2 Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 1 CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
bit 0 Unimplemented: Read as ‘0’
PIC18F85J90 FAMILY
DS39770C-page 110 2010 Microchip Technology Inc.
9.4 IPR Registers
The IPR registers contain the individual priority bits for
the peripheral interrupts. Due to the number of
peripheral interrupt sources, there are three Peripheral
Interrupt Priority registers (IPR1, IPR2, IPR3). Using
the priority bits requires that the Interrupt Priority
Enable (IPEN) bit be set.
REGISTER 9-10: IPR1: PERIPHERAL INTERRUPT PRIORITY REGISTER 1
U-0 R/W-1 R/W-1 R/W-1 R/W-1 U-0 R/W-1 R/W-1
— ADIP RC1IP TX1IP SSPIP — TMR2IP TMR1IP
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 Unimplemented: Read as ‘0’
bit 6 ADIP: A/D Converter Interrupt Priority bit
1 =High priority
0 = Low priority
bit 5 RC1IP: EUSART Receive Interrupt Priority bit
1 =High priority
0 = Low priority
bit 4 TX1IP: EUSART Transmit Interrupt Priority bit
1 =High priority
0 = Low priority
bit 3 SSPIP: Master Synchronous Serial Port Interrupt Priority bit
1 =High priority
0 = Low priority
bit 2 Unimplemented: Read as ‘0’
bit 1 TMR2IP: TMR2 to PR2 Match Interrupt Priority bit
1 =High priority
0 = Low priority
bit 0 TMR1IP: TMR1 Overflow Interrupt Priority bit
1 =High priority
0 = Low priority
2010 Microchip Technology Inc. DS39770C-page 111
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REGISTER 9-11: IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2
R/W-1 R/W-1 U-0 U-0 R/W-1 R/W-1 R/W-1 U-0
OSCFIP CMIP —— BCLIP LVDIP TMR3IP —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 OSCFIP: Oscillator Fail Interrupt Priority bit
1 =High priority
0 = Low priority
bit 6 CMIP: Comparator Interrupt Priority bit
1 =High priority
0 = Low priority
bit 5-4 Unimplemented: Read as ‘0’
bit 3 BCLIP: Bus Collision Interrupt Priority bit
1 =High priority
0 = Low priority
bit 2 LVDIP: Low-Voltage Detect Interrupt Priority bit
1 =High priority
0 = Low priority
bit 1 TMR3IP: TMR3 Overflow Interrupt Priority bit
1 =High priority
0 = Low priority
bit 0 Unimplemented: Read as ‘0’
PIC18F85J90 FAMILY
DS39770C-page 112 2010 Microchip Technology Inc.
REGISTER 9-12: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3
U-0 R/W-1 R-1 R-1 U-0 R/W-1 R/W-1 U-0
— LCDIP RC2IP TX2IP — CCP2IP CCP1IP —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 Unimplemented: Read as ‘0’
bit 6 LCDIP: LCD Interrupt Priority bit (valid when Type-B waveform with Non-Static mode is selected)
1 =High priority
0 = Low priority
bit 5 RC2IP: AUSART Receive Priority Flag bit
1 =High priority
0 = Low priority
bit 4 TX2IP: AUSART Transmit Interrupt Priority bit
1 =High priority
0 = Low priority
bit 3 Unimplemented: Read as ‘0’
bit CCP2IP: CCP2 Interrupt Priority bit
1 =High priority
0 = Low priority
bit CCP1IP: CCP1 Interrupt Priority bit
1 =High priority
0 = Low priority
bit 0 Unimplemented: Read as ‘0’
2010 Microchip Technology Inc. DS39770C-page 113
PIC18F85J90 FAMILY
9.5 RCON Register
The RCON register contains bits used to determine the
cause of the last Reset or wake-up from Idle or Sleep
modes. RCON also contains the bit that enables
interrupt priorities (IPEN).
REGISTER 9-13: RCON: RESET CONTROL REGISTER
R/W-0 U-0 R/W-1 R/W-1 R-1 R-1 R/W-0 R/W-0
IPEN —CMRI TO PD POR BOR
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 IPEN: Interrupt Priority Enable bit
1 = Enable priority levels on interrupts
0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode)
bit 6 Unimplemented: Read as ‘0’
bit 5 CM: Configuration Mismatch Flag bit
For details of bit operation, see Register 5-1.
bit 4 RI: RESET Instruction Flag bit
For details of bit operation, see Register 5-1.
bit 3 TO: Watchdog Timer Time-out Flag bit
For details of bit operation, see Register 5-1.
bit 2 PD: Power-Down Detection Flag bit
For details of bit operation, see Register 5-1.
bit 1 POR: Power-on Reset Status bit
For details of bit operation, see Register 5-1.
bit 0 BOR: Brown-out Reset Status bit
For details of bit operation, see Register 5-1.
PIC18F85J90 FAMILY
DS39770C-page 114 2010 Microchip Technology Inc.
9.6 INTx Pin Interrupts
External interrupts on the RB0/INT0, RB1/INT1,
RB2/INT2 and RB3/INT3 pins are edge-triggered. If the
corresponding INTEDGx bit in the INTCON2 register is
set (= 1), the interrupt is triggered by a rising edge; if
the bit is clear, the trigger is on the falling edge. When
a valid edge appears on the RBx/INTx pin, the
corresponding flag bit, INTxIF, is set. This interrupt can
be disabled by clearing the corresponding enable bit,
INTxIE. Flag bit, INTxIF, must be cleared in software in
the Interrupt Service Routine before re-enabling the
interrupt.
All external interrupts (INT0, INT1, INT2 and INT3) can
wake-up the processor from the power-managed
modes if bit, INTxIE, was set prior to going into the
power-managed modes. If the Global Interrupt Enable
bit, GIE, is set, the processor will branch to the interrupt
vector following wake-up.
Interrupt priority for INT1, INT2 and INT3 is determined
by the value contained in the interrupt priority bits,
INT1IP (INTCON3<6>), INT2IP (INTCON3<7>) and
INT3IP (INTCON2<1>). There is no priority bit
associated with INT0. It is always a high-priority
interrupt source.
9.7 TMR0 Interrupt
In 8-bit mode (which is the default), an overflow in the
TMR0 register (FFh 00h) will set flag bit, TMR0IF. In
16-bit mode, an overflow in the TMR0H:TMR0L register
pair (FFFFh 0000h) will set TMR0IF. The interrupt can
be enabled/disabled by setting/clearing enable bit,
TMR0IE (INTCON<5>). Interrupt priority for Timer0 is
determined by the value contained in the interrupt priority
bit, TMR0IP (INTCON2<2>). See Section 11.0 “Timer0
Module” for further details on the Timer0 module.
9.8 PORTB Interrupt-on-Change
An input change on PORTB<7:4> sets flag bit, RBIF
(INTCON<0>). The interrupt can be enabled/disabled
by setting/clearing enable bit, RBIE (INTCON<3>).
Interrupt priority for the PORTB interrupt-on-change is
determined by the value contained in the interrupt
priority bit, RBIP (INTCON2<0>).
9.9 Context Saving During Interrupts
During interrupts, the return PC address is saved on
the stack. Additionally, the WREG, STATUS and BSR
registers are saved on the Fast Return Stack. If a fast
return from interrupt is not used (see Section 6.3
“Data Memory Organization”), the user may need to
save the WREG, STATUS and BSR registers on entry
to the Interrupt Service Routine. Depending on the
user’s application, other registers may also need to be
saved. Example 9-1 saves and restores the WREG,
STATUS and BSR registers during an Interrupt Service
Routine.
EXAMPLE 9-1: SAVING STATUS, WREG AND BSR REGISTERS IN RAM
MOVWF W_TEMP ; W_TEMP is in virtual bank
MOVFF STATUS, STATUS_TEMP ; STATUS_TEMP located anywhere
MOVFF BSR, BSR_TEMP ; BSR_TMEP located anywhere
;
; USER ISR CODE
;
MOVFF BSR_TEMP, BSR ; Restore BSR
MOVF W_TEMP, W ; Restore WREG
MOVFF STATUS_TEMP, STATUS ; Restore STATUS
2010 Microchip Technology Inc. DS39770C-page 115
PIC18F85J90 FAMILY
10.0 I/O PORTS
Depending on the device selected and features
enabled, there are up to nine ports available. Some
pins of the I/O ports are multiplexed with an alternate
function from the peripheral features on the device. In
general, when a peripheral is enabled, that pin may not
be used as a general purpose I/O pin.
Each port has three memory mapped registers for its
operation:
• TRIS register (Data Direction register)
• PORT register (reads the levels on the pins of the
device)
• LAT register (Data Latch register)
Reading the PORT register reads the current status of
the pins, whereas writing to the PORT register writes to
the Data Latch (LAT) register.
Setting a TRIS bit (= 1) makes the corresponding port
pin an input (i.e., puts the corresponding output driver
in a High-Impedance mode). Clearing a TRIS bit (= 0)
makes the corresponding port pin an output (i.e., puts
the contents of the corresponding LAT bit on the
selected pin).
The Data Latch (LAT register) is useful for
read-modify-write operations on the value that the I/O
pins are driving. Read-modify-write operations on the
LAT register read and write the latched output value for
the PORT register.
A simplified model of a generic I/O port, without the
interfaces to other peripherals, is shown in Figure 10-1.
FIGURE 10-1: GENERIC I/O PORT
OPERATION
10.1 I/O Port Pin Capabilities
When developing an application, the capabilities of the
port pins must be considered. Outputs on some pins
have higher output drive strength than others. Similarly,
some pins can tolerate higher than VDD input levels.
10.1.1 INPUT PINS AND VOLTAGE
CONSIDERATIONS
The voltage tolerance of pins used as device inputs is
dependent on the pin’s input function. Most pins that
are used as digital only inputs are able to handle DC
volta ges up to 5.5V, a level typical for digital logic
circuits. The digital pins that cannot exceed VDD are
RE0, RE1, RE2, RG0, RG2 and RG3.
In contrast, pins that also have analog input functions of
any kind can only tolerate voltages up to VDD. Voltage
excursions beyond VDD on these pins should be avoided.
Table 10-1 summarizes the input voltage capabilities.
Refer to Section 26.0 “Electrical Characteristics” for
more details.
TABLE 10-1: INPUT VOLTAGE TOLERANCE
10.1.2 PIN OUTPUT DRIVE
When used as digital I/O, the output pin drive strengths
vary for groups of pins intended to meet the needs for
a variety of applications. In general, there are three
classes of output pins in terms of drive capability.
PORTB and PORTC, as well as PORTA<7:6>, are
designed to drive higher current loads, such as LEDs.
PORTD, PORTE and PORTJ can also drive LEDs but
only those with smaller current requirements. PORTF,
PORTG and PORTH, along with PORTA<5:0>, have
the lowest drive level but are capable of driving normal
digital circuit loads with a high input impedance.
Regardless of which port it is located on, all output pins
in LCD Segment or Common mode have sufficient
output to directly drive a display.
Table 10-2 summarizes the output capabilities of the
ports. Refer to the “Absolute Maximum Ratings” in
Section 26.0 “Electrical Characteristics” for more
details.
Data
Bus
WR LAT
WR TRIS
RD PORT
Data Latch
TRIS Latch
RD TRIS
Input
Buffer
I/O pin(1)
QD
CKx
QD
CKx
EN
QD
EN
RD LAT
or PORT
Note 1: I/O pins have diode protection to VDD and VSS.
PORT or Pin Tolerated
Input Description
PORTA<7:0> VDD Only VDD input levels
are tolerated.
PORTC<1:0>
PORTF<7:1>
PORTB<7:0> 5.5V Tolerates input levels
above VDD; useful for
most standard logic.
PORTC<7:2>
PORTD<7:0>
PORTE<7:3>
PORTG<4,1>
PORTH<7:0>(1)
PORTJ<7:0>(1)
Note 1: Not available on 64-pin devices.
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DS39770C-page 116 2010 Microchip Technology Inc.
TABLE 10-2: OUTPUT DRIVE LEVELS FOR
VARIOUS PORTS
10.1.3 PULL-UP CONFIGURATION
Four of the I/O ports (PORTB, PORTD, PORTE and
PORTJ) implement configurable weak pull-ups on all
pins. These are internal pull-ups that allow floating
digital input signals to be pulled to a consistent level
without the use of external resistors.
The pull-ups are enabled with a single bit for each of the
ports: RBPU (INTCON2<7>) for PORTB, and RDPU,
REPU and PJPU (PORTG<7:5>) for the other ports.
10.1.4 OPEN-DRAIN OUTPUTS
The output pins for several peripherals are also
equipped with a configurable, open-drain output option.
This allows the peripherals to communicate with
external digital logic, operating at a higher voltage
level, without the use of level translators.
The open-drain option is implemented on port pins
specifically associated with the data and clock outputs
of the USARTs, the MSSP module (in SPI mode) and
the CCP modules. This option is selectively enabled by
setting the open-drain control bit for the corresponding
module in TRISG and LATG. Their configuration is dis-
cussed in more detail in Section 10.4 “PORTC, TRISC
and LATC Registers”, Section 10.6 “PORTE, TRISE
and LATE Registers” and Section 10.8 “PORTG,
TRISG and LATG Registers”.
When the open-drain option is required, the output pin
must also be tied through an external pull-up resistor
provided by the user to a higher voltage level, up to 5V
(Figure 10-2). When a digital logic high signal is output,
it is pulled up to the higher voltage level.
FIGURE 10-2: USING THE OPEN-DRAIN
OUTPUT (USART SHOWN
AS EXAMPLE)
10.2 PORTA, TRISA and
LATA Registers
PORTA is an 8-bit wide, bidirectional port. The corre-
sponding Data Direction and Data Latch registers are
TRISA and LATA.
RA4/T0CKI is a Schmitt Trigger input. All other PORTA
pins have TTL input levels and full CMOS output
drivers.
The RA4 pin is multiplexed with the Timer0 clock input
and one of the LCD segment drives. RA5 and RA<3:0>
are multiplexed with analog inputs for the A/D
Converter.
The operation of the analog inputs as A/D Converter
inputs is selected by clearing or setting the PCFG<3:0>
control bits in the ADCON1 register. The corresponding
TRISA bits control the direction of these pins, even
when they are being used as analog inputs. The user
must ensure the bits in the TRISA register are
maintained set when using them as analog inputs.
OSC2/CLKO/RA6 and OSC1/CLKI/RA7 normally
serve as the external circuit connections for the exter-
nal (primary) oscillator circuit (HS Oscillator modes), or
the external clock input and output (EC Oscillator
modes). In these cases, RA6 and RA7 are not available
as digital I/O and their corresponding TRIS and LAT
bits are read as ‘0’. When the device is configured to
use INTOSC or INTRC as the default oscillator mode
(FOSC2 Configuration bit is ‘0’), RA6 and RA7 are
automatically configured as digital I/O; the oscillator
and clock in/clock out functions are disabled.
RA1, RA4 and RA5 are multiplexed with LCD segment
drives, controlled by bits in the LCDSE1 and LCDSE2
registers. I/O port functionality is only available when
the LCD segments are disabled.
EXAMPLE 10-1: INITIALIZING PORTA
Low Medium High
PORTA<5:0> PORTD PORTA<7:6>
PORTF PORTE PORTB
PORTG PORTJ(1) PORTC
PORTH(1)
Note 1: Not available on 64-pin devices.
TXX
PIC18F85J90
+5V
3.3V
(at logic ‘1’)
3.3V
VDD 5V
Note: RA5 and RA<3:0> are configured as
analog inputs on any Reset and are read
as ‘0’. RA4 is configured as a digital input.
CLRF PORTA ; Initialize PORTA by
; clearing output latches
CLRF LATA ; Alternate method to
; clear output data latches
MOVLW 07h ; Configure A/D
MOVWF ADCON1 ; for digital inputs
MOVLW 0BFh ; Value used to initialize
; data direction
MOVWF TRISA ; Set RA<7, 5:0> as inputs,
; RA<6> as output
2010 Microchip Technology Inc. DS39770C-page 117
PIC18F85J90 FAMILY
TABLE 10-3: PORTA FUNCTIONS
TABLE 10-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Pin Name Function TRIS
Setting I/O I/O
Type Description
RA0/AN0 RA0 0O DIG LATA<0> data output; not affected by analog input.
1I TTL PORTA<0> data input; disabled when analog input is enabled.
AN0 1I ANA A/D Input Channel 0. Default input configuration on POR; does not
affect digital output.
RA1/AN1/SEG18 RA1 0O DIG LATA<1> data output; not affected by analog input.
1I TTL PORTA<1> data input; disabled when analog input enabled.
AN1 1I ANA A/D Input Channel 1. Default input configuration on POR; does not
affect digital output.
SEG18 xO ANA LCD Segment 18 output; disables all other pin functions.
RA2/AN2/VREF-RA20O DIG LATA<2> data output; not affected by analog input.
1I TTL PORTA<2> data input; disabled when analog functions are enabled.
AN2 1I ANA A/D Input Channel 2. Default input configuration on POR.
VREF-1I ANA A/D and comparator low reference voltage input.
RA3/AN3/VREF+RA3 0O DIG LATA<3> data output; not affected by analog input.
1I TTL PORTA<3> data input; disabled when analog input is enabled.
AN3 1I ANA A/D Input Channel 3. Default input configuration on POR.
VREF+1I ANA A/D and comparator high reference voltage input.
RA4/T0CKI/
SEG14
RA4 0O DIG LATA<4> data output.
1I ST PORTA<4> data input. Default configuration on POR.
T0CKI xI ST Timer0 clock input.
SEG14 xO ANA LCD Segment 14 output; disables all other pin functions.
RA5/AN4/SEG15 RA5 0O DIG LATA<5> data output; not affected by analog input.
1I TTL PORTA<5> data input; disabled when analog input is enabled.
AN4 1I ANA A/D Input Channel 4. Default configuration on POR.
SEG15 xO ANA LCD Segment 15 output; disables all other pin functions.
OSC2/CLKO/RA6 OSC2 xO ANA Main oscillator feedback output connection (HS and HSPLL modes).
CLKO xO DIG System cycle clock output (FOSC/4) (EC and ECPLL modes).
RA6 0O DIG LATA<6> data output; disabled when FOSC2 Configuration bit is set.
1I TTL PORTA<6> data input; disabled when FOSC2 Configuration bit is set.
OSC1/CLKI/RA7 OSC1 xI ANA Main oscillator input connection (HS and HSPLL modes).
CLKI xI ANA Main external clock source input (EC and ECPLL modes).
RA7 0O DIG LATA<7> data output; disabled when FOSC2 Configuration bit is set.
1I TTL PORTA<7> data input; disabled when FOSC2 Configuration bit is set.
Legend: O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Trigger Buffer Input,
TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values
on page
PORTA RA7(1) RA6(1) RA5RA4RA3RA2RA1RA0 61
LATA LATA7(1) LATA6(1) LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 60
TRISA TRISA7(1) TRISA6(1) TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 60
ADCON1 — — VCFG1 VCFG0PCFG3PCFG2PCFG1PCFG0 59
LCDSE1 SE15 SE14 SE13 SE12 SE11 SE10 SE09 SE08 59
LCDSE2 SE23 SE22 SE21 SE20 SE19 SE18 SE17 SE16 59
Legend: — = unimplemented, read as ‘0’, x = don’t care. Shaded cells are not used by PORTA.
Note 1: These bits are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are
disabled and read as ‘x’.
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DS39770C-page 118 2010 Microchip Technology Inc.
10.3 PORTB, TRISB and
LATB Registers
PORTB is an 8-bit wide, bidirectional port. The
corresponding Data Direction and Data Latch registers
are TRISB and LATB. All pins on PORTB are digital only
and tolerate voltages up to 5.5V.
EXAMPLE 10-2: INITIALIZING PORTB
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is
performed by clearing bit, RBPU (INTCON2<7>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are
disabled on a Power-on Reset.
Four of the PORTB pins (RB<7:4>) have an
interrupt-on-change feature. Only pins configured as
inputs can cause this interrupt to occur (i.e., any
RB<7:4> pin configured as an output is excluded from
the interrupt-on-change comparison). The input pins (of
RB<7:4>) are compared with the old value latched on
the last read of PORTB. The “mismatch” outputs of
RB<7:4> are ORed together to generate the RB Port
Change Interrupt with Flag bit, RBIF (INTCON<0>).
This interrupt can wake the device from
power-managed modes. The user, in the Interrupt
Service Routine, can clear the interrupt in the following
manner:
a) Any read or write of PORTB (except with the
MOVFF (ANY), PORTB instruction). This will
end the mismatch condition.
b) Wait one instruction cycle (such as executing a
NOP instruction).
c) Clear flag bit, RBIF.
A mismatch condition will continue to set flag bit, RBIF.
Reading PORTB will end the mismatch condition and
allow flag bit, RBIF, to be cleared after one T
CY delay.
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
RB<5:0> are also multiplexed with LCD segment
drives, controlled by bits in the LCDSE1 and LCDSE3
registers. I/O port functionality is only available when
the LCD segments are disabled.
CLRF PORTB ; Initialize PORTB by
; clearing output
; data latches
CLRF LATB ; Alternate method
; to clear output
; data latches
MOVLW 0CFh ; Value used to
; initialize data
; direction
MOVWF TRISB ; Set RB<3:0> as inputs
; RB<5:4> as outputs
; RB<7:6> as inputs
2010 Microchip Technology Inc. DS39770C-page 119
PIC18F85J90 FAMILY
TABLE 10-5: PORTB FUNCTIONS
Pin Name Function TRIS
Setting I/O I/O
Type Description
RB0/INT0/SEG30 RB0 0O DIG LATB<0> data output.
1I TTL PORTB<0> data input; weak pull-up when RBPU bit is cleared.
INT0 1I ST External Interrupt 0 input.
SEG30 xO ANA LCD Segment 30 output; disables all other pin functions.
RB1/INT1/SEG8 RB1 0O DIG LATB<1> data output.
1I TTL PORTB<1> data input; weak pull-up when RBPU bit is cleared.
INT1 1I ST External Interrupt 1 input.
SEG8 xO ANA LCD Segment 8 output; disables all other pin functions.
RB2/INT2/SEG9 RB2 0O DIG LATB<2> data output.
1I TTL PORTB<2> data input; weak pull-up when RBPU bit is cleared.
INT2 1I ST External Interrupt 2 input.
SEG9 xO ANA LCD Segment 9 output; disables all other pin functions.
RB3/INT3/SEG10 RB3 0O DIG LATB<3> data output.
1I TTL PORTB<3> data input; weak pull-up when RBPU bit is cleared.
INT3 1I ST External Interrupt 3 input.
SEG10 xO ANA LCD Segment 10 output; disables all other pin functions.
RB4/KBI0/SEG11 RB4 0O DIG LATB<4> data output.
1I TTL PORTB<4> data input; weak pull-up when RBPU bit is cleared.
KBI0 1I TTL Interrupt-on-pin change.
SEG11 xO ANA LCD Segment 11 output; disables all other pin functions.
RB5/KBI1/SEG29 RB5 0O DIG LATB<5> data output.
1I TTL PORTB<5> data input; weak pull-up when RBPU bit is cleared.
KBI1 1I TTL Interrupt-on-pin change.
SEG29 xO ANA LCD Segment 29 output; disables all other pin functions.
RB6/KBI2/PGC RB6 0O DIG LATB<6> data output.
1I TTL PORTB<6> data input; weak pull-up when RBPU bit is cleared.
KBI2 1I TTL Interrupt-on-pin change.
PGC xI ST Serial execution (ICSP™) clock input for ICSP and ICD operation.
RB7/KBI3/PGD RB7 0O DIG LATB<7> data output.
1I TTL PORTB<7> data input; weak pull-up when RBPU bit is cleared.
KBI3 1I TTL Interrupt-on-pin change.
PGD xO DIG Serial execution data output for ICSP and ICD operation.
xI ST Serial execution data input for ICSP and ICD operation.
Legend: O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Trigger Buffer Input,
TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
PIC18F85J90 FAMILY
DS39770C-page 120 2010 Microchip Technology Inc.
TABLE 10-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
NameBit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
Reset
Values on
page
PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 61
LATB LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 60
TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 60
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 57
INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INT3IP RBIP 57
INTCON3 INT2IP INT1IP INT3IE INT2IE INT1IE INT3IF INT2IF INT1IF 57
LCDSE1 SE15 SE14 SE13 SE12 SE11 SE10 SE09 SE08 59
LCDSE3 SE31 SE30 SE29 SE28 SE27 SE26 SE25 SE24 59
Legend: Shaded cells are not used by PORTB.
2010 Microchip Technology Inc. DS39770C-page 121
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10.4 PORTC, TRISC and
LATC Registers
PORTC is an 8-bit wide, bidirectional port. The
corresponding Data Direction and Data Latch registers
are TRISC and LATC. Only PORTC pins, RC2 through
RC7, are digital only pins and can tolerate input voltages
up to 5.5V.
PORTC is multiplexed with CCP, MSSP and EUSART
peripheral functions (Table 10-7). The pins have
Schmitt Trigger input buffers. The pins for CCP, SPI
and EUSART are also configurable for open-drain out-
put whenever these functions are active. Open-drain
configuration is selected by setting the SPIOD,
CCPxOD, and U1OD control bits (TRISG<7:5> and
LATG<6>, respectively).
RC1 is normally configured as the default peripheral
pin for the CCP2 module. Assignment of CCP2 is
controlled by Configuration bit, CCP2MX (default state,
CCP2MX = 1).
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTC pin. Some
peripherals override the TRIS bit to make a pin an output,
while other peripherals override the TRIS bit to make a
pin an input. The user should refer to the corresponding
peripheral section for the correct TRIS bit settings.
The contents of the TRISC register are affected by
peripheral overrides. Reading TRISC always returns
the current contents, even though a peripheral device
may be overriding one or more of the pins.
RC<7:1> pins are multiplexed with LCD segment
drives, controlled by bits in the LCDSE1, LCDSE2,
LCDSE3 and LCDSE4 registers. I/O port functionality
is only available when the LCD segments are disabled.
EXAMPLE 10-3: INITIALIZING PORTC
Note: These pins are configured as digital inputs
on any device Reset.
CLRF PORTC ; Initialize PORTC by
; clearing output
; data latches
CLRF LATC ; Alternate method
; to clear output
; data latches
MOVLW 0CFh ; Value used to
; initialize data
; direction
MOVWF TRISC ; Set RC<3:0> as inputs
; RC<5:4> as outputs
; RC<7:6> as inputs
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DS39770C-page 122 2010 Microchip Technology Inc.
TABLE 10-7: PORTC FUNCTIONS
Pin Name Function TRIS
Setting I/O I/O
Type Description
RC0/T1OSO/
T13CKI
RC0 0O DIG LATC<0> data output.
1I ST PORTC<0> data input.
T1OSO xO ANA Timer1 oscillator output; enabled when Timer1 oscillator is enabled. Disables
digital I/O and LCD segment driver.
T13CKI 1I ST Timer1/Timer3 counter input.
RC1/T1OSI/
CCP2/SEG32
RC1 0O DIG LATC<1> data output.
1I ST PORTC<1> data input.
T1OSI xI ANA Timer1 oscillator input.
CCP2(1) 0O DIG CCP2 compare/PWM output.
1I ST CCP2 capture input.
SEG32 xO ANA LCD Segment 32 output; disables all other pin functions.
RC2/CCP1/
SEG13
RC2 0O DIG LATC<2> data output.
1I ST PORTC<2> data input.
CCP1 0O DIG CCP1 compare/PWM output; takes priority over port data.
1I ST CCP1 capture input.
SEG13 xO ANA LCD Segment 13 output; disables all other pin functions.
RC3/SCK/SCL/
SEG17
RC3 0O DIG LATC<3> data output.
1I ST PORTC<3> data input.
SCK 0O DIG SPI clock output (MSSP module); takes priority over port data.
1I ST SPI clock input (MSSP module).
SCL 0ODIGI
2C™ clock output (MSSP module); takes priority over port data.
1II2CI
2C clock input (MSSP module); input type depends on module setting.
SEG17 xO ANA LCD Segment 17 output; disables all other pin functions.
RC4/SDI/SDA/
SEG16
RC4 0O DIG LATC<4> data output.
1I ST PORTC<4> data input.
SDI I ST SPI data input (MSSP module).
SDA 1ODIGI
2C data output (MSSP module); takes priority over port data.
1II2CI
2C data input (MSSP module); input type depends on module setting.
SEG16 xO ANA LCD Segment 16 output; disables all other pin functions.
RC5/SDO/
SEG12
RC5 0O DIG LATC<5> data output.
1I ST PORTC<5> data input.
SDO 0O DIG SPI data output (MSSP module).
SEG12 xO ANA LCD Segment 12 output; disables all other pin functions.
RC6/TX1/CK1/
SEG27
RC6 0O DIG LATC<6> data output.
1I ST PORTC<6> data input.
TX1 1O DIG Synchronous serial data output (EUSART module); takes priority over port data.
CK1 1O DIG Synchronous serial data input (EUSART module); user must configure as an input.
1I ST Synchronous serial clock input (EUSART module).
SEG27 xO ANA LCD Segment 27 output; disables all other pin functions.
RC7/RX1/DT1/
SEG28
RC7 0O DIG LATC<7> data output.
1I ST PORTC<7> data input.
RX1 1I ST Asynchronous serial receive data input (EUSART module).
DT1 1O DIG Synchronous serial data output (EUSART module); takes priority over port data.
1I ST Synchronous serial data input (EUSART module); user must configure as an input.
SEG28 xO ANA LCD Segment 28 output; disables all other pin functions.
Legend: O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Trigger Buffer Input, TTL = TTL Buffer Input,
I2C = I2C/SMBus Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set.
2010 Microchip Technology Inc. DS39770C-page 123
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TABLE 10-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 61
LATC LATC7 LATBC6 LATC5 LATCB4 LATC3 LATC2 LATC1 LATC0 60
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 60
LATG U2OD U1OD —LATG4 LATG3 LATG2 LATG1 LATG0 60
TRISG SPIOD CCP2OD CCP1OD TRISG4 TRISG3 TRISG2 TRISG1 TRISG0 60
LCDSE1 SE15 SE14 SE13 SE12 SE11 SE10 SE09 SE08 59
LCDSE2 SE23 SE22 SE21 SE20 SE19 SE18 SE17 SE16 59
LCDSE3 SE31 SE30 SE29 SE28 SE27 SE26 SE25 SE24 59
LCDSE4 SE39(1) SE38(1) SE37(1) SE36(1) SE35(1) SE34(1) SE33(1) SE32 59
Legend: Shaded cells are not used by PORTC.
Note 1: Unimplemented on 64-pin devices, read as ‘0’.
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DS39770C-page 124 2010 Microchip Technology Inc.
10.5 PORTD, TRISD and
LATD Registers
PORTD is an 8-bit wide, bidirectional port. The
corresponding Data Direction and Data Latch registers
are TRISD and LATD. All pins on PORTD are digital only
and tolerate voltages up to 5.5V.
All pins on PORTD are implemented with Schmitt
Trigger input buffers. Each pin is individually
configurable as an input or output.
Each of the PORTD pins has a weak internal pull-up. A
single control bit can turn off all the pull-ups. This is
performed by clearing bit, RDPU (PORTG<7>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are
disabled on all device Resets.
All of the PORTD pins are multiplexed with LCD
segment drives, controlled by bits in the LCDSE0
register. I/O port functionality is only available when the
LCD segments are disabled.
EXAMPLE 10-4: INITIALIZING PORTD
Note: These pins are configured as digital inputs
on any device Reset.
CLRF PORTD ; Initialize PORTD by
; clearing output
; data latches
CLRF LATD ; Alternate method
; to clear output
; data latches
MOVLW 0CFh ; Value used to
; initialize data
; direction
MOVWF TRISD ; Set RD<3:0> as inputs
; RD<5:4> as outputs
; RD<7:6> as inputs
2010 Microchip Technology Inc. DS39770C-page 125
PIC18F85J90 FAMILY
TABLE 10-9: PORTD FUNCTIONS
TABLE 10-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD
Pin Name Function TRIS
Setting I/O I/O
Type Description
RD0/SEG0 RD0 0O DIG LATD<0> data output.
1I ST PORTD<0> data input.
SEG0 xO ANA LCD Segment 0 output; disables all other pin functions.
RD1/SEG1 RD1 0O DIG LATD<1> data output.
1I ST PORTD<1> data input.
SEG1 xO ANA LCD Segment 1 output; disables all other pin functions.
RD2/SEG2 RD2 0O DIG LATD<2> data output.
1I ST PORTD<2> data input.
SEG2 xO ANA LCD Segment 2 output; disables all other pin functions.
RD3/SEG3 RD3 0O DIG LATD<3> data output.
1I ST PORTD<3> data input.
SEG3 xO ANA LCD Segment 3 output; disables all other pin functions.
RD4/SEG4 RD4 0O DIG LATD<4> data output.
1I ST PORTD<4> data input.
SEG4 xO ANA LCD Segment 4 output; disables all other pin functions.
RD5/SEG5 RD5 0O DIG LATD<5> data output.
1I ST PORTD<5> data input.
SEG5 xO ANA LCD Segment 5 output; disables all other pin functions.
RD6/SEG6 RD6 0O DIG LATD<6> data output.
1I ST PORTD<6> data input.
SEG6 xO ANA LCD Segment 6 output; disables all other pin functions.
RD7/SEG7 RD7 0O DIG LATD<7> data output.
1I ST PORTD<7> data input.
SEG7 xI ANA LCD Segment 7 output; disables all other pin functions.
Legend: O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Trigger Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 61
LATD LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 60
TRISD TRISD7 TRISD6 TRISD5 TRISD4TRISD3TRISD2TRISD1TRISD0 60
PORTG RDPU REPU RJPU(1) RG4 RG3 RG2 RG1 RG0 60
LCDSE0 SE7 SE6 SE5 SE4 SE3 SE2 SE1 SE0 59
Legend: Shaded cells are not used by PORTD.
Note 1: Unimplemented on 64-pin devices, read as ‘0’.
PIC18F85J90 FAMILY
DS39770C-page 126 2010 Microchip Technology Inc.
10.6 PORTE, TRISE and
LATE Registers
PORTE is a 7-bit wide, bidirectional port. The
corresponding Data Direction and Data Latch registers
are TRISE and LATE. All pins on PORTE are digital only
and tolerate voltages up to 5.5V.
All pins on PORTE are implemented with Schmitt
Trigger input buffers. Each pin is individually
configurable as an input or output. The RE7 pin is also
configurable for open-drain output when CCP2 is active
on this pin. Open-drain configuration is selected by
setting the CCP2OD control bit (TRISG<6>)
Each of the PORTE pins has a weak internal pull-up. A
single control bit can turn off all the pull-ups. This is
performed by clearing bit, REPU (PORTG<6>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are
disabled on any device Reset.
Pins, RE<6:3>, are multiplexed with the LCD common
drives. I/O port functions are only available on those
PORTE pins depending on which commons are active.
The configuration is determined by the LMUX<1:0>
control bits (LCDCON<1:0>). The availability is
summarized in Table 10-11.
TABLE 10-11: PORTE PINS AVAILABLE IN
DIFFERENT LCD DRIVE
CONFIGURATIONS
Pins, RE1 and RE0, are multiplexed with the functions
of LCDBIAS2 and LCDBIAS1. When LCD bias genera-
tion is required (i.e., any application where the device
is connected to an external LCD), these pins cannot be
used as digital I/O.
RE7 is multiplexed with LCD segment drive (SEG31)
controlled by the LCDSE3<7> bit. I/O port function is
only available when the segment is disabled.
RE7 can also be configured as the alternate peripheral
pin for the CCP2 module. This is done by clearing the
CCP2MX Configuration bit.
EXAMPLE 10-5: INITIALIZING PORTE
Note: These pins are configured as digital inputs
on any device Reset.
LCDCON
<1:0>
Active LCD
Commons
PORTE Available
for I/O
00 COM0 RE6, RE5, RE4
01 COM0, COM1 RE6, RE5
10 COM0, COM1
and COM2
RE6
11 All (COM0
through COM3)
None
Note: The pin corresponding to RE2 of other
PIC18F parts has the function of
LCDBIAS3 in this device. It cannot be used
as digital I/O.
CLRF PORTE ; Initialize PORTE by
; clearing output
; data latches
CLRF LATE ; Alternate method
; to clear output
; data latches
MOVLW 03h ; Value used to
; initialize data
; direction
MOVWF TRISE ; Set RE<1:0> as inputs
; RE<7:2> as outputs
2010 Microchip Technology Inc. DS39770C-page 127
PIC18F85J90 FAMILY
TABLE 10-12: PORTE FUNCTIONS
TABLE 10-13: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
Pin Name Function TRIS
Setting I/O I/O
Type Description
RE0/LCDBIAS1 RE0 0O DIG LATE<0> data output.
1I ST PORTE<0> data input.
LCDBIAS1 — I ANA LCD module bias voltage input.
RE1/LCDBIAS2 RE1 0O DIG LATE<1> data output.
1I ST PORTE<1> data input.
LCDBIAS2 — I ANA LCD module bias voltage input.
RE3/COM0 RE3 0O DIG LATE<3> data output.
1I ST PORTE<3> data input.
COM0 xO ANA LCD Common 0 output; disables all other outputs.
RE4/COM1 RE4 0O DIG LATE<4> data output.
1I ST PORTE<4> data input.
COM1 xO ANA LCD Common 1 output; disables all other outputs.
RE5/COM2 RE5 0O DIG LATE<5> data output.
1I ST PORTE<5> data input.
COM2 xO ANA LCD Common 2 output; disables all other outputs.
RE6/COM3 RE6 0O DIG LATE<6> data output.
1I ST PORTE<6> data input.
COM3 xO ANA LCD Common 3 output; disables all other outputs.
RE7/CCP2/
SEG31
RE7 0O DIG LATE<7> data output.
1I ST PORTE<7> data input.
CCP2(1) 0O DIG CCP2 compare/PWM output; takes priority over port data.
1I ST CCP2 capture input.
SEG31 xO ANA Segment 31 analog output for LCD; disables digital output.
Legend: O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Trigger Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Note 1: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
PORTE RE7 RE6 RE5 RE4 RE3 —RE1RE061
LATE LATE7 LATE6 LATE5 LATE4 LATE3 —LATE1LATE060
TRISE TRISE7 TRISE6 TRISE5 TRISE4 TRISE3 — TRISE1 TRISE0 60
PORTG RDPU REPU RJPU(1) RG4 RG3 RG2 RG1 RG0 60
TRISG SPIOD CCP2OD CCP1OD TRISG4 TRISG3 TRISG2 TRISG1 TRISG0 60
LCDCON LCDEN SLPEN WERR —CS1 CS0 LMUX1 LMUX0 59
LCDSE3 SE31 SE30 SE29 SE28 SE27 SE26 SE25 SE24 59
Legend: Shaded cells are not used by PORTE.
Note 1: Unimplemented on 64-pin devices, read as ‘0’.
PIC18F85J90 FAMILY
DS39770C-page 128 2010 Microchip Technology Inc.
10.7 PORTF, LATF and TRISF Registers
PORTF is a 7-bit wide, bidirectional port. The
corresponding Data Direction and Data Latch registers
are TRISF and LATF. All pins on PORTF are
implemented with Schmitt Trigger input buffers. Each pin
is individually configurable as an input or output.
PORTF is multiplexed with analog peripheral functions,
as well as LCD segments. Pins RF1 through RF6 may
be used as comparator inputs or outputs by setting the
appropriate bits in the CMCON register. To use
RF<6:3> as digital inputs, it is also necessary to turn off
the comparators.
PORTF is also multiplexed with LCD segment drives
controlled by bits in the LCDSE2 and LCDSE3
registers. I/O port functions are only available when the
segments are disabled.
EXAMPLE 10-6: INITIALIZING PORTF
Note 1: On device Resets, pins, RF<6:1>, are
configured as analog inputs and are read
as ‘0’.
2: To configure PORTF as a digital I/O, turn
off the comparators and set the ADCON1
value.
CLRF PORTF ; Initialize PORTF by
; clearing output
; data latches
CLRF LATF ; Alternate method
; to clear output
; data latches
MOVLW 07h ;
MOVWF CMCON ; Turn off comparators
MOVLW 0Fh ;
MOVWF ADCON1 ; Set PORTF as digital I/O
MOVLW 0CEh ; Value used to
; initialize data
; direction
MOVWF TRISF ; Set RF3:RF1 as inputs
; RF5:RF4 as outputs
; RF7:RF6 as inputs
2010 Microchip Technology Inc. DS39770C-page 129
PIC18F85J90 FAMILY
TABLE 10-14: PORTF FUNCTIONS
Pin Name Function TRIS
Setting I/O I/O
Type Description
RF1/AN6/C2OUT/
SEG19
RF1 0O DIG LATF<1> data output; not affected by analog input.
1I ST PORTF<1> data input; disabled when analog input is enabled.
AN6 1I ANA A/D Input Channel 6. Default configuration on POR.
C2OUT 0O DIG Comparator 2 output; takes priority over port data.
SEG19 xO ANA LCD Segment 19 output; disables all other pin functions.
RF2/AN7/C1OUT/
SEG20
RF2 0O DIG LATF<2> data output; not affected by analog input.
1I ST PORTF<2> data input; disabled when analog input is enabled.
AN7 1I ANA A/D Input Channel 7. Default configuration on POR.
C1OUT 0O DIG Comparator 1 output; takes priority over port data.
SEG20 xO ANA LCD Segment 20 output; disables all other pin functions.
RF3/AN8/SEG21 RF3 0O DIG LATF<3> data output; not affected by analog input.
1I ST PORTF<3> data input; disabled when analog input is enabled.
AN8 1I ANA A/D Input Channel 8 and Comparator C2+ input. Default input
configuration on POR; not affected by analog output.
SEG21 xO ANA LCD Segment 21 output; disables all other pin functions.
RF4/AN9/SEG22 RF4 0O DIG LATF<4> data output; not affected by analog input.
1I ST PORTF<4> data input; disabled when analog input is enabled.
AN9 1I ANA A/D Input Channel 9 and Comparator C2- input. Default input
configuration on POR; does not affect digital output.
SEG22 xO ANA LCD Segment 22 output; disables all other pin functions.
RF5/AN10/CVREF/
SEG23
RF5 0O DIG LATF<5> data output; not affected by analog input. Disabled when
CVREF output is enabled.
1I ST PORTF<5> data input; disabled when analog input is enabled.
Disabled when CVREF output is enabled.
AN10 1I ANA A/D Input Channel 10 and Comparator C1+ input. Default input
configuration on POR.
CVREF xO ANA Comparator voltage reference output. Enabling this feature disables
digital I/O.
SEG23 xO ANA LCD Segment 23 output; disables all other pin functions.
RF6/AN11/SEG24 RF6 0O DIG LATF<6> data output; not affected by analog input.
1I ST PORTF<6> data input; disabled when analog input is enabled.
AN11 1I ANA A/D Input Channel 11 and Comparator C1- input. Default input
configuration on POR; does not affect digital output.
SEG24 xO ANA LCD Segment 24 output; disables all other pin functions.
RF7/AN5/SS/
SEG25
RF7 0O DIG LATF<7> data output; not affected by analog input.
1I ST PORTF<7> data input; disabled when analog input is enabled.
AN5 1I ANA A/D Input Channel 5. Default configuration on POR.
SS 1I TTL Slave select input for MSSP module.
SEG25 xO ANA LCD Segment 25 output; disables all other pin functions.
Legend: O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Trigger Buffer Input,
TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
PIC18F85J90 FAMILY
DS39770C-page 130 2010 Microchip Technology Inc.
TABLE 10-15: SUMMARY OF REGISTERS ASSOCIATED WITH PORTF
Name Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
Reset
Values
on page
PORTF RF7 RF6 RF5 RF4 RF3 RF2 RF1 —60
LATF LATF7 LATF6 LATF5 LATF4 LATF3 LATF2 LATF1 —60
TRISF TRISF7TRISF6TRISF5TRISF4TRISF3TRISF2TRISF1 —60
ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 59
CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 59
CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 59
LCDSE2 SE23 SE22 SE21 SE20 SE19 SE18 SE17 SE16 59
LCDSE3 SE31 SE30 SE29 SE28 SE27 SE26 SE25 SE24 59
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTF.
2010 Microchip Technology Inc. DS39770C-page 131
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10.8 PORTG, TRISG and
LATG Registers
PORTG is a 5-bit wide, bidirectional port. The
corresponding Data Direction and Data Latch registers
are TRISG and LATG. All pins on PORTG are digital only
and tolerate voltages up to 5.5V.
PORTG is multiplexed with both AUSART and LCD
functions (Table 10-16). When operating as I/O, all
PORTG pins have Schmitt Trigger input buffers. The
RG1 pin is also configurable for open-drain output
when the AUSART is active. Open-drain configuration
is selected by setting the U2OD control bit (LATG<7>).
RG4 is multiplexed with LCD segment drives controlled
by bits in the LCDSE2 register. The I/O port function is
only available when the segments are disabled.
RG3 and RG2 are multiplexed with the VLCAP pins for
the LCD charge pump and RG0 is multiplexed with the
LCDBIAS0 bias voltage input. When these pins are
used for LCD bias generation, the I/O and other
functions are unavailable.
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTG pin. Some
peripherals override the TRIS bit to make a pin an
output, while other peripherals override the TRIS bit to
make a pin an input. The user should refer to the
corresponding peripheral section for the correct TRIS bit
settings. The pin override value is not loaded into the
TRIS register. This allows read-modify-write of the TRIS
register without concern due to peripheral overrides.
Although the port itself is only five bits wide, the
PORTG<7:5> bits are still implemented to control the
weak pull-ups on the I/O ports associated with PORTD,
PORTE and PORTJ. Clearing these bits enables the
respective port pull-ups. All pull-ups are disabled by
default on all device Resets.
Most of the corresponding TRISG and LATG bits are
implemented as open-drain control bits for CCP1,
CCP2 and SPI (TRISG<7:5>), and the USARTs
(LATG<7:6>). Setting these bits configures the output
pin for the corresponding peripheral for open-drain
operation. LATG<5> is not implemented.
EXAMPLE 10-7: INITIALIZING PORTG
CLRF PORTG ; Initialize PORTG by
; clearing output
; data latches
CLRF LATG ; Alternate method
; to clear output
; data latches
MOVLW 04h ; Value used to
; initialize data
; direction
MOVWF TRISG ; Set RG1:RG0 as outputs
; RG2 as input
; RG4:RG3 as inputs
PIC18F85J90 FAMILY
DS39770C-page 132 2010 Microchip Technology Inc.
TABLE 10-16: PORTG FUNCTIONS
TABLE 10-17: SUMMARY OF REGISTERS ASSOCIATED WITH PORTG
Pin Name Function TRIS
Setting I/O I/O
Type Description
RG0/LCDBIAS0 RG0 0O DIG LATG<0> data output.
1I ST PORTG<0> data input.
LCDBIAS0 xI ANA LCD module bias voltage input.
RG1/TX2/CK2 RG1 0O DIG LATG<1> data output.
1I ST PORTG<1> data input.
TX2 1O DIG Synchronous serial data output (AUSART module); takes priority over
port data.
CK2 1O DIG Synchronous serial data input (AUSART module); user must configure
as an input.
1I ST Synchronous serial clock input (AUSART module).
RG2/RX2/DT2/V
LCAP1
RG2 0O DIG LATG<2> data output.
1I ST PORTG<2> data input.
RX2 1I ST Asynchronous serial receive data input (AUSART module).
DT2 1O DIG Synchronous serial data output (AUSART module); takes priority over
port data.
1I ST Synchronous serial data input (AUSART module); user must configure
as an input.
VLCAP1xI ANA LCD charge pump capacitor input.
RG3/VLCAP2RG30O DIG LATG<3> data output.
1I ST PORTG<3> data input.
VLCAP2xI ANA LCD charge pump capacitor input.
RG4/SEG26 RG4 0O DIG LATG<4> data output.
1I ST PORTG<4> data input.
SEG26 xO ANA LCD Segment 26 output; disables all other pin functions.
Legend: O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Trigger Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values on
page
PORTG RDPU REPU RJPU(1) RG4 RG3 RG2 RG1 RG0 60
LATG U2OD U1OD — LATG4 LATG3 LATG2 LATG1 LATG0 60
TRISG SPIOD CCP2OD CCP1OD TRISG4 TRISG3 TRISG2 TRISG1 TRISG0 60
LCDSE3 SE31 SE30 SE29 SE28 SE27 SE26 SE25 SE24 59
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTG.
Note 1: Unimplemented on 64-pin devices, read as ‘0’.
2010 Microchip Technology Inc. DS39770C-page 133
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10.9 PORTH, LATH and
TRISH Registers
PORTH is an 8-bit wide, bidirectional I/O port. The
corresponding Data Direction and Data Latch registers
are TRISH and LATH. All pins are digital only and
tolerate voltages up to 5.5V.
All pins on PORTH are implemented with Schmitt
Trigger input buffers. Each pin is individually
configurable as an input or output.
All PORTH pins are multiplexed with LCD segment
drives controlled by the LCDSE5 register. I/O port
functions are only available when the segments are
disabled.
EXAMPLE 10-8: INITIALIZING PORTH
Note: PORTH is available only on 80-pin
devices.
CLRF PORTH ; Initialize PORTH by
; clearing output
; data latches
CLRF LATH ; Alternate method
; to clear output
; data latches
MOVLW 0Fh ; Configure PORTH as
MOVWF ADCON1 ; digital I/O
MOVLW 0CFh ; Value used to
; initialize data
; direction
MOVWF TRISH ; Set RH3:RH0 as inputs
; RH5:RH4 as outputs
; RH7:RH6 as inputs
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DS39770C-page 134 2010 Microchip Technology Inc.
TABLE 10-18: PORTH FUNCTIONS
TABLE 10-19: SUMMARY OF REGISTERS ASSOCIATED WITH PORTH
Pin Name Function TRIS
Setting I/O I/O
Type Description
RH0/SEG47 RH0 0O DIG LATH<0> data output.
1I ST PORTH<0> data input.
SEG47 xO ANA LCD Segment 47 output; disables all other pin functions.
RH1/SEG46 RH1 0O DIG LATH<1> data output.
1I ST PORTH<1> data input.
SEG46 xO ANA LCD Segment 46 output; disables all other pin functions.
RH2/SEG45 RH2 0O DIG LATH<2> data output.
1I ST PORTH<2> data input.
SEG45 xO ANA LCD Segment 45 output; disables all other pin functions.
RH3/SEG44 RH3 0O DIG LATH<3> data output.
1I ST PORTH<3> data input.
SEG44 xO ANA LCD Segment 44 output; disables all other pin functions.
RH4/SEG40 RH4 0O DIG LATH<4> data output.
1I ST PORTH<4> data input.
SEG40 xO ANA LCD Segment 40 output; disables all other pin functions.
RH5/SEG41 RH5 0O DIG LATH<5> data output.
1I ST PORTH<5> data input.
SEG41 xO ANA LCD Segment 41 output; disables all other pin functions.
RH6/SEG42 RH6 0O DIG LATH<6> data output.
1I ST PORTH<6> data input.
SEG42 xO ANA LCD Segment 42 output; disables all other pin functions.
RH7/SEG43 RH7 0O DIG LATH<7> data output.
1I ST PORTH<7> data input.
SEG43 xO ANA LCD Segment 43 output; disables all other pin functions.
Legend: O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Trigger Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
PORTH RH7 RH6 RH5 RH4 RH3 RH2 RH1 RH0 60
LATH LATH7 LATH6 LATH5 LATH4 LATH3 LATH2 LATH1 LATH0 60
TRISH TRISH7 TRISH6 TRISH5 TRISH4 TRISH3 TRISH2 TRISH1 TRISH0 60
LCDSE5 SE47 SE46 SE45 SE44 SE43 SE42 SE41 SE40 59
2010 Microchip Technology Inc. DS39770C-page 135
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10.10 PORTJ, TRISJ and
LATJ Registers
PORTJ is an 8-bit wide, bidirectional port. The
corresponding Data Direction and Data Latch registers
are TRISJ and LATJ. All pins on PORTJ are digital only
and tolerate voltages up to 5.5V.
All pins on PORTJ are implemented with Schmitt
Trigger input buffers. Each pin is individually
configurable as an input or output.
All PORTJ pins, except RJ0, are multiplexed with LCD
segment drives controlled by the LCDSE4 register. I/O
port functions are only available on these pins when the
segments are disabled.
Each of the PORTJ pins has a weak internal pull-up.
The pull-ups are provided to keep the inputs at a known
state for the external memory interface while powering
up. A single control bit can turn off all the pull-ups. This
is performed by clearing bit RJPU (PORTG<5>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are
disabled on any device Reset.
EXAMPLE 10-9: INITIALIZING PORTJ
Note: PORTJ is available only on 80-pin devices.
Note: These pins are configured as digital inputs
on any device Reset.
CLRF PORTJ ; Initialize PORTJ by
; clearing output latches
CLRF LATJ ; Alternate method
; to clear output latches
MOVLW 0CFh ; Value used to
; initialize data
; direction
MOVWF TRISJ ; Set RJ3:RJ0 as inputs
; RJ5:RJ4 as output
; RJ7:RJ6 as inputs
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DS39770C-page 136 2010 Microchip Technology Inc.
TABLE 10-20: PORTJ FUNCTIONS
TABLE 10-21: SUMMARY OF REGISTERS ASSOCIATED WITH PORTJ
Pin Name Function TRIS
Setting I/O I/O
Type Description
RJ0 RJ0 0O DIG LATJ<0> data output.
1I ST PORTJ<0> data input.
RJ1/SEG33 RJ1 0O DIG LATJ<1> data output.
1I ST PORTJ<1> data input.
SEG33 xO ANA LCD Segment 33 output; disables all other pin functions.
RJ2/SEG34 RJ2 0O DIG LATJ<2> data output.
1I ST PORTJ<2> data input.
SEG34 xO ANA LCD Segment 34 output; disables all other pin functions.
RJ3/SEG35 RJ3 0O DIG LATJ<3> data output.
1I ST PORTJ<3> data input.
SEG35 xO ANA LCD Segment 35 output; disables all other pin functions.
RJ4/SEG39 RJ4 0O DIG LATJ<4> data output.
1I ST PORTJ<4> data input.
SEG39 xO ANA LCD Segment 39 output; disables all other pin functions.
RJ5/SEG38 RJ5 0O DIG LATJ<5> data output.
1I ST PORTJ<5> data input.
SEG38 xO ANA LCD Segment 38 output; disables all other pin functions.
RJ6/SEG37 RJ6 0O DIG LATJ<6> data output.
1I ST PORTJ<6> data input.
SEG37 xO ANA LCD Segment 37 output; disables all other pin functions.
RJ7/SEG36 RJ7 0O DIG LATJ<7> data output.
1I ST PORTJ<7> data input.
SEG36 xO ANA LCD Segment 36 output; disables all other pin functions.
Legend: O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Trigger Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
PORTJ RJ7 RJ6 RJ5 RJ4 RJ3 RJ2 RJ1 RJ0 60
LATJ LATJ7 LATJ6 LATJ5 LATJ4 LATJ3 LATJ2 LATJ1 LATJ0 60
TRISJ TRISJ7 TRISJ6 TRISJ5 TRISJ4 TRISJ3 TRISJ2 TRISJ1 TRISJ0 60
PORTG RDPU REPU RJPU(1) RG4 RG3 RG2 RG1 RG0 60
LCDSE4 SE39 SE38 SE37 SE36 SE35 SE34 SE33 SE32 59
Legend: Shaded cells are not used by PORTJ.
Note 1: Unimplemented on 64-pin devices, read as ‘0’.
2010 Microchip Technology Inc. DS39770C-page 137
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11.0 TIMER0 MODULE
The Timer0 module incorporates the following features:
• Software selectable operation as a timer or coun-
ter in both 8-bit or 16-bit modes
• Readable and writable registers
• Dedicated 8-bit, software programmable
prescaler
• Selectable clock source (internal or external)
• Edge select for external clock
• Interrupt-on-overflow
The T0CON register (Register 11-1) controls all
aspects of the module’s operation, including the
prescale selection; it is both readable and writable.
A simplified block diagram of the Timer0 module in 8-bit
mode is shown in Figure 11-1. Figure 11-2 shows a
simplified block diagram of the Timer0 module in 16-bit
mode.
REGISTER 11-1: T0CON: TIMER0 CONTROL REGISTER
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 TMR0ON: Timer0 On/Off Control bit
1 = Enables Timer0
0 = Stops Timer0
bit 6 T08BIT: Timer0 8-Bit/16-Bit Control bit
1 = Timer0 is configured as an 8-bit timer/counter
0 = Timer0 is configured as a 16-bit timer/counter
bit 5 T0CS: Timer0 Clock Source Select bit
1 = Transition on T0CKI pin input edge
0 = Internal clock (FOSC/4)
bit 4 T0SE: Timer0 Source Edge Select bit
1 = Increment on high-to-low transition on T0CKI pin
0 = Increment on low-to-high transition on T0CKI pin
bit 3 PSA: Timer0 Prescaler Assignment bit
1 = TImer0 prescaler is not assigned. Timer0 clock input bypasses prescaler.
0 = Timer0 prescaler is assigned. Timer0 clock input comes from prescaler output.
bit 2-0 T0PS<2:0>: Timer0 Prescaler Select bits
111 = 1:256 Prescale value
110 = 1:128 Prescale value
101 = 1:64 Prescale value
100 = 1:32 Prescale value
011 = 1:16 Prescale value
010 = 1:8 Prescale value
001 = 1:4 Prescale value
000 = 1:2 Prescale value
PIC18F85J90 FAMILY
DS39770C-page 138 2010 Microchip Technology Inc.
11.1 Timer0 Operation
Timer0 can operate as either a timer or a counter. The
mode is selected with the T0CS bit (T0CON<5>). In
Timer mode (T0CS = 0), the module increments on
every clock by default unless a different prescaler value
is selected (see Section 11.3 “Prescaler”). If the
TMR0 register is written to, the increment is inhibited
for the following two instruction cycles. The user can
work around this by writing an adjusted value to the
TMR0 register.
The Counter mode is selected by setting the T0CS bit
(= 1). In this mode, Timer0 increments either on every
rising or falling edge of pin RA4/T0CKI. The increment-
ing edge is determined by the Timer0 Source Edge
Select bit, T0SE (T0CON<4>); clearing this bit selects
the rising edge. Restrictions on the external clock input
are discussed below.
An external clock source can be used to drive Timer0,
however, it must meet certain requirements to ensure
that the external clock can be synchronized with the
internal phase clock (TOSC). There is a delay between
synchronization and the onset of incrementing the
timer/counter.
11.2 Timer0 Reads and Writes in
16-Bit Mode
TMR0H is not the actual high byte of Timer0 in 16-bit
mode. It is actually a buffered version of the real high
byte of Timer0, which is not directly readable nor writ-
able (refer to Figure 11-2). TMR0H is updated with the
contents of the high byte of Timer0 during a read of
TMR0L. This provides the ability to read all 16 bits of
Timer0 without having to verify that the read of the high
and low byte were valid, due to a rollover between
successive reads of the high and low byte.
Similarly, a write to the high byte of Timer0 must also
take place through the TMR0H Buffer register. The high
byte is updated with the contents of TMR0H when a
write occurs to TMR0L. This allows all 16 bits of Timer0
to be updated at once.
FIGURE 11-1: TIMER0 BLOCK DIAGRAM (8-BIT MODE)
FIGURE 11-2: TIMER0 BLOCK DIAGRAM (16-BIT MODE)
Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.
T0CKI pin
T0SE
0
1
1
0
T0CS
FOSC/4
Sync with
Internal
Clocks
TMR0L
(2 TCY Delay)
Internal Data Bus
PSA
T0PS<2:0>
Set
TMR0IF
on Overflow
38
8
Programmable
Prescaler
Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.
T0CKI pin
T0SE
0
1
1
0
T0CS
FOSC/4
Sync with
Internal
Clocks
TMR0L
(2 TCY Delay)
Internal Data Bus
8
PSA
T0PS<2:0>
Set
TMR0IF
on Overflow
3
TMR0
TMR0H
High Byte
88
8
Read TMR0L
Write TMR0L
8
Programmable
Prescaler
2010 Microchip Technology Inc. DS39770C-page 139
PIC18F85J90 FAMILY
11.3 Prescaler
An 8-bit counter is available as a prescaler for the Timer0
module. The prescaler is not directly readable or writable.
Its value is set by the PSA and T0PS<2:0> bits
(T0CON<3:0>) which determine the prescaler
assignment and prescale ratio.
Clearing the PSA bit assigns the prescaler to the
Timer0 module. When it is assigned, prescale values
from 1:2 through 1:256, in power-of-2 increments, are
selectable.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g., CLRF TMR0, MOVWF
TMR0, BSF TMR0, etc.) clear the prescaler count.
11.3.1 SWITCHING PRESCALER
ASSIGNMENT
The prescaler assignment is fully under software
control and can be changed “on-the-fly” during program
execution.
11.4 Timer0 Interrupt
The TMR0 interrupt is generated when the TMR0
register overflows from FFh to 00h in 8-bit mode, or
from FFFFh to 0000h in 16-bit mode. This overflow sets
the TMR0IF flag bit. The interrupt can be masked by
clearing the TMR0IE bit (INTCON<5>). Before
re-enabling the interrupt, the TMR0IF bit must be
cleared in software by the Interrupt Service Routine.
Since Timer0 is shut down in Sleep mode, the TMR0
interrupt cannot awaken the processor from Sleep.
TABLE 11-1: REGISTERS ASSOCIATED WITH TIMER0
Note: Writing to TMR0 when the prescaler is
assigned to Timer0 will clear the prescaler
count but will not change the prescaler
assignment.
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
TMR0L Timer0 Register Low Byte 58
TMR0H Timer0 Register High Byte 58
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 57
T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 58
TRISA TRISA7(1) TRISA6(1) TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 60
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by Timer0.
Note 1: RA6/RA7 and their associated latch and direction bits are configured as port pins only when the internal
oscillator is selected as the default clock source (FOSC2 Configuration bit = 0); otherwise, they are
disabled and these bits read as ‘0’.
PIC18F85J90 FAMILY
DS39770C-page 140 2010 Microchip Technology Inc.
NOTES:
2010 Microchip Technology Inc. DS39770C-page 141
PIC18F85J90 FAMILY
12.0 TIMER1 MODULE
The Timer1 timer/counter module incorporates these
features:
• Software selectable operation as a 16-bit timer or
counter
• Readable and writable 8-bit registers (TMR1H
and TMR1L)
• Selectable clock source (internal or external) with
device clock or Timer1 oscillator internal options
• Interrupt on overflow
• Reset on CCP Special Event Trigger
• Device clock status flag (T1RUN)
A simplified block diagram of the Timer1 module is
shown in Figure 12-1. A block diagram of the module’s
operation in Read/Write mode is shown in Figure 12-2.
The module incorporates its own low-power oscillator
to provide an additional clocking option. The Timer1
oscillator can also be used as a low-power clock source
for the microcontroller in power-managed operation.
Timer1 can also be used to provide Real-Time Clock
(RTC) functionality to applications with only a minimal
addition of external components and code overhead.
Timer1 is controlled through the T1CON Control
register (Register 12-1). It also contains the Timer1
Oscillator Enable bit (T1OSCEN). Timer1 can be
enabled or disabled by setting or clearing control bit,
TMR1ON (T1CON<0>).
REGISTER 12-1: T1CON: TIMER1 CONTROL REGISTER
R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
RD16 T1RUN T1CKPS1 T1CKPS0
T1OSCEN
T1SYNC TMR1CS TMR1ON
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 RD16: 16-Bit Read/Write Mode Enable bit
1 = Enables register read/write of TImer1 in one 16-bit operation
0 = Enables register read/write of Timer1 in two 8-bit operations
bit 6 T1RUN: Timer1 System Clock Status bit
1 = Device clock is derived from Timer1 oscillator
0 = Device clock is derived from another source
bit 5-4 T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits
11 = 1:8 Prescale value
10 = 1:4 Prescale value
01 = 1:2 Prescale value
00 = 1:1 Prescale value
bit 3 T1OSCEN: Timer1 Oscillator Enable bit
1 = Timer1 oscillator is enabled
0 = Timer1 oscillator is shut off
The oscillator inverter and feedback resistor are turned off to eliminate power drain.
bit 2 T1SYNC: Timer1 External Clock Input Synchronization Select bit
When TMR1CS = 1:
1 = Do not synchronize external clock input
0 = Synchronize external clock input
When TMR1CS = 0:
This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.
bit 1 TMR1CS: Timer1 Clock Source Select bit
1 = External clock from pin RC0/T1OSO/T13CKI (on the rising edge)
0 = Internal clock (FOSC/4)
bit 0 TMR1ON: Timer1 On bit
1 = Enables Timer1
0 =Stops Timer1
PIC18F85J90 FAMILY
DS39770C-page 142 2010 Microchip Technology Inc.
12.1 Timer1 Operation
Timer1 can operate in one of these modes:
•Timer
• Synchronous Counter
• Asynchronous Counter
The operating mode is determined by the clock select
bit, TMR1CS (T1CON<1>). When TMR1CS is cleared
(= 0), Timer1 increments on every internal instruction
cycle (FOSC/4). When the bit is set, Timer1 increments
on every rising edge of the Timer1 external clock input
or the Timer1 oscillator, if enabled.
When Timer1 is enabled, the RC1/T1OSI and
RC0/T1OSO/T13CKI pins become inputs. This means
the values of TRISC<1:0> are ignored and the pins are
read as ‘0’.
FIGURE 12-1: TIMER1 BLOCK DIAGRAM (8-BIT MODE)
FIGURE 12-2: TIMER1 BLOCK DIAGRAM (16-BIT READ/WRITE MODE)
T1SYNC
TMR1CS
T1CKPS<1:0>
Sleep Input
T1OSCEN(1)
FOSC/4
Internal
Clock
On/Off
1
0
2
T1OSO/T13CKI
T1OSI
1
0
TMR1ON
TMR1L
Set
TMR1IF
on Overflow
TMR1
High Byte
Clear TMR1
(CCP Special Event Trigger)
Timer1 Oscillator
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
On/Off
Timer1
Timer1 Clock Input
Prescaler
1, 2, 4, 8
Synchronize
Detect
T1SYNC
TMR1CS
T1CKPS<1:0>
Sleep Input
T1OSCEN(1)
FOSC/4
Internal
Clock
1
0
2
T1OSO/T13CKI
T1OSI
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
1
0
TMR1L
Internal Data Bus
8
Set
TMR1IF
on Overflow
TMR1
TMR1H
High Byte
88
8
Read TMR1L
Write TMR1L
8
TMR1ON
Clear TMR1
(CCP Special Event Trigger)
Timer1 Oscillator
On/Off
Timer1
Timer1 Clock Input
Prescaler
1, 2, 4, 8
Synchronize
Detect
2010 Microchip Technology Inc. DS39770C-page 143
PIC18F85J90 FAMILY
12.2 Timer1 16-Bit Read/Write Mode
Timer1 can be configured for 16-bit reads and writes
(see Figure 12-2). When the RD16 control bit
(T1CON<7>) is set, the address for TMR1H is mapped
to a buffer register for the high byte of Timer1. A read
from TMR1L will load the contents of the high byte of
Timer1 into the Timer1 High Byte Buffer register. This
provides the user with the ability to accurately read all
16 bits of Timer1 without having to determine whether
a read of the high byte, followed by a read of the low
byte, has become invalid due to a rollover between
reads.
A write to the high byte of Timer1 must also take place
through the TMR1H Buffer register. The Timer1 high
byte is updated with the contents of TMR1H when a
write occurs to TMR1L. This allows a user to write all
16 bits to both the high and low bytes of Timer1 at once.
The high byte of Timer1 is not directly readable or
writable in this mode. All reads and writes must take
place through the Timer1 High Byte Buffer register.
Writes to TMR1H do not clear the Timer1 prescaler.
The prescaler is only cleared on writes to TMR1L.
12.3 Timer1 Oscillator
An on-chip crystal oscillator circuit is incorporated
between pins T1OSI (input) and T1OSO (amplifier
output). It is enabled by setting the Timer1 Oscillator
Enable bit, T1OSCEN (T1CON<3>). The oscillator is a
low-power circuit rated for 32 kHz crystals. It will
continue to run during all power-managed modes. The
circuit for a typical LP oscillator is shown in Figure 12-3.
Table 12-1 shows the capacitor selection for the Timer1
oscillator.
The user must provide a software time delay to ensure
proper start-up of the Timer1 oscillator.
FIGURE 12-3: EXTERNAL
COMPONENTS FOR THE
TIMER1 LP OSCILLATOR
TABLE 12-1: CAPACITOR SELECTION FOR
THE TIMER1
OSCILLATOR(2,3,4)
12.3.1 USING TIMER1 AS A
CLOCK SOURCE
The Timer1 oscillator is also available as a clock source
in power-managed modes. By setting the System
Clock Select bits, SCS<1:0> (OSCCON<1:0>), to ‘01’,
the device switches to SEC_RUN mode; both the CPU
and peripherals are clocked from the Timer1 oscillator.
If the IDLEN bit (OSCCON<7>) is cleared and a SLEEP
instruction is executed, the device enters SEC_IDLE
mode. Additional details are available in Section 4.0
“Power-Managed Modes”.
Whenever the Timer1 oscillator is providing the clock
source, the Timer1 system clock status flag, T1RUN
(T1CON<6>), is set. This can be used to determine the
controller’s current clocking mode. It can also indicate
the clock source being currently used by the Fail-Safe
Clock Monitor. If the Clock Monitor is enabled and the
Timer1 oscillator fails while providing the clock, polling
the T1RUN bit will indicate whether the clock is being
provided by the Timer1 oscillator or another source.
Note: See the Notes with Table 12-1 for additional
information about capacitor selection.
C1
C2
XTAL
PIC18F85J90
T1OSI
T1OSO
32.768 kHz
27 pF
27 pF
Oscillator
Type Freq. C1 C2
LP 32.768 kHz 27 pF(1) 27 pF(1)
Note 1: Microchip suggests these values as a
starting point in validating the oscillator
circuit.
2: Higher capacitance increases the stability
of the oscillator but also increases the
start-up time.
3: Since each resonator/crystal has its own
characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate values of external
components.
4: Capacitor values are for design guidance
only.
PIC18F85J90 FAMILY
DS39770C-page 144 2010 Microchip Technology Inc.
12.3.2 TIMER1 OSCILLATOR LAYOUT
CONSIDERATIONS
The Timer1 oscillator circuit draws very little power
during operation. Due to the low-power nature of the
oscillator, it may also be sensitive to rapidly changing
signals in close proximity.
The oscillator circuit, shown in Figure 12-3, should be
located as close as possible to the microcontroller.
There should be no circuits passing within the oscillator
circuit boundaries other than VSS or VDD.
If a high-speed circuit must be located near the oscilla-
tor (such as the CCP1 pin in Output Compare or PWM
mode, or the primary oscillator using the OSC2 pin), a
grounded guard ring around the oscillator circuit, as
shown in Figure 12-4, may be helpful when used on a
single-sided PCB or in addition to a ground plane.
FIGURE 12-4: OSCILLATOR CIRCUIT
WITH GROUNDED
GUARD RING
12.4 Timer1 Interrupt
The TMR1 register pair (TMR1H:TMR1L) increments
from 0000h to FFFFh and rolls over to 0000h. The
Timer1 interrupt, if enabled, is generated on overflow
which is latched in interrupt flag bit, TMR1IF
(PIR1<0>). This interrupt can be enabled or disabled
by setting or clearing the Timer1 Interrupt Enable bit,
TMR1IE (PIE1<0>).
12.5 Resetting Timer1 Using the CCP
Special Event Trigger
If CCP1 or CCP2 is configured to use Timer1 and to
generate a Special Event Trigger in Compare mode
(CCPxM<3:0> = 1011), this signal will reset Timer3.
The trigger from CCP2 will also start an A/D conversion
if the A/D module is enabled (see Section 15.3.4
“Special Event Trigger” for more information).
The module must be configured as either a timer or a
synchronous counter to take advantage of this feature.
When used this way, the CCPRxH:CCPRxL register
pair effectively becomes a period register for Timer1.
If Timer1 is running in Asynchronous Counter mode,
this Reset operation may not work.
In the event that a write to Timer1 coincides with a
Special Event Trigger, the write operation will take
precedence.
12.6 Using Timer1 as a Real-Time Clock
Adding an external LP oscillator to Timer1 (such as the
one described in Section 12.3 “Timer1 Oscillator”)
gives users the option to include RTC functionality to
their applications. This is accomplished with an
inexpensive watch crystal to provide an accurate time
base and several lines of application code to calculate
the time. When operating in Sleep mode and using a
battery or supercapacitor as a power source, it can
completely eliminate the need for a separate RTC
device and battery backup.
The application code routine, RTCisr, shown in
Example 12-1, demonstrates a simple method to
increment a counter at one-second intervals using an
Interrupt Service Routine. Incrementing the TMR1
register pair to overflow triggers the interrupt and calls
the routine which increments the seconds counter by
one. Additional counters for minutes and hours are
incremented as the previous counter overflows.
Since the register pair is 16 bits wide, counting up to
overflow the register directly from a 32.768 kHz clock
would take 2 seconds. To force the overflow at the
required one-second intervals, it is necessary to pre-
load it. The simplest method is to set the MSb of
TMR1H with a BSF instruction. Note that the TMR1L
register is never preloaded or altered; doing so may
introduce cumulative error over many cycles.
For this method to be accurate, Timer1 must operate in
Asynchronous mode and the Timer1 overflow interrupt
must be enabled (PIE1<0> = 1) as shown in the
routine, RTCinit. The Timer1 oscillator must also be
enabled and running at all times.
VDD
OSC1
VSS
OSC2
RC0
RC1
RC2
Note: Not drawn to scale.
Note: The Special Event Triggers from the CCPx
module will not set the TMR1IF interrupt
flag bit (PIR1<0>).
2010 Microchip Technology Inc. DS39770C-page 145
PIC18F85J90 FAMILY
EXAMPLE 12-1: IMPLEMENTING A REAL-TIME CLOCK USING A TIMER1 INTERRUPT SERVICE
TABLE 12-2: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 57
PIR1 —ADIF RC1IF TX1IF SSPIF —TMR2IF TMR1IF 60
PIE1 —ADIE RC1IE TX1IE SSPIE —TMR2IE TMR1IE 60
IPR1 —ADIP RC1IP TX1IP SSPIP —TMR2IP TMR1IP 60
TMR1L Timer1 Register Low Byte 58
TMR1H Timer1 Register High Byte 58
T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 58
Legend: Shaded cells are not used by the Timer1 module.
RTCinit MOVLW 80h ; Preload TMR1 register pair
MOVWF TMR1H ; for 1 second overflow
CLRF TMR1L
MOVLW b’00001111’ ; Configure for external clock,
MOVWF T1CON ; Asynchronous operation, external oscillator
CLRF secs ; Initialize timekeeping registers
CLRF mins ;
MOVLW .12
MOVWF hours
BSF PIE1, TMR1IE ; Enable Timer1 interrupt
RETURN
RTCisr BSF TMR1H, 7 ; Preload for 1 sec overflow
BCF PIR1, TMR1IF ; Clear interrupt flag
INCF secs, F ; Increment seconds
MOVLW .59 ; 60 seconds elapsed?
CPFSGT secs
RETURN ; No, done
CLRF secs ; Clear seconds
INCF mins, F ; Increment minutes
MOVLW .59 ; 60 minutes elapsed?
CPFSGT mins
RETURN ; No, done
CLRF mins ; clear minutes
INCF hours, F ; Increment hours
MOVLW .23 ; 24 hours elapsed?
CPFSGT hours
RETURN ; No, done
CLRF hours ; Reset hours
RETURN ; Done
PIC18F85J90 FAMILY
DS39770C-page 146 2010 Microchip Technology Inc.
NOTES:
2010 Microchip Technology Inc. DS39770C-page 147
PIC18F85J90 FAMILY
13.0 TIMER2 MODULE
The Timer2 module incorporates the following features:
• 8-bit Timer and Period registers (TMR2 and PR2,
respectively)
• Readable and writable (both registers)
• Software programmable prescaler
(1:1, 1:4 and 1:16)
• Software programmable postscaler
(1:1 through 1:16)
• Interrupt on TMR2 to PR2 match
• Optional use as the shift clock for the
MSSP module
The module is controlled through the T2CON register
(Register 13-1) which enables or disables the timer and
configures the prescaler and postscaler. Timer2 can be
shut off by clearing control bit, TMR2ON (T2CON<2>),
to minimize power consumption.
A simplified block diagram of the module is shown in
Figure 13-1.
13.1 Timer2 Operation
In normal operation, TMR2 is incremented from 00h on
each clock (FOSC/4). A 4-bit counter/prescaler on the
clock input gives direct input, divide-by-4 and
divide-by-16 prescale options. These are selected by
the prescaler control bits, T2CKPS<1:0>
(T2CON<1:0>). The value of TMR2 is compared to that
of the Period register, PR2, on each clock cycle. When
the two values match, the comparator generates a
match signal as the timer output. This signal also resets
the value of TMR2 to 00h on the next cycle and drives
the output counter/postscaler (see Section 13.2
“Timer2 Interrupt”).
The TMR2 and PR2 registers are both directly readable
and writable. The TMR2 register is cleared on any
device Reset, while the PR2 register initializes at FFh.
Both the prescaler and postscaler counters are cleared
on the following events:
• a write to the TMR2 register
• a write to the T2CON register
• any device Reset (Power-on Reset, MCLR Reset,
Watchdog Timer Reset or Brown-out Reset)
TMR2 is not cleared when T2CON is written.
REGISTER 13-1: T2CON: TIMER2 CONTROL REGISTER
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 Unimplemented: Read as ‘0’
bit 6-3 T2OUTPS<3:0>: Timer2 Output Postscale Select bits
0000 = 1:1 Postscale
0001 = 1:2 Postscale
•
•
•
1111 = 1:16 Postscale
bit 2 TMR2ON: Timer2 On bit
1 = Timer2 is on
0 = Timer2 is off
bit 1-0 T2CKPS<1:0>: Timer2 Clock Prescale Select bits
00 = Prescaler is 1
01 = Prescaler is 4
1x = Prescaler is 16
PIC18F85J90 FAMILY
DS39770C-page 148 2010 Microchip Technology Inc.
13.2 Timer2 Interrupt
Timer2 can also generate an optional device interrupt.
The Timer2 output signal (TMR2 to PR2 match) pro-
vides the input for the 4-bit output counter/postscaler.
This counter generates the TMR2 match interrupt flag
which is latched in TMR2IF (PIR1<1>). The interrupt is
enabled by setting the TMR2 Match Interrupt Enable
bit, TMR2IE (PIE1<1>).
A range of 16 postscale options (from 1:1 through 1:16
inclusive) can be selected with the postscaler control
bits, T2OUTPS<3:0> (T2CON<6:3>).
13.3 Timer2 Output
The unscaled output of TMR2 is available primarily to
the CCP modules, where it is used as a time base for
operations in PWM mode.
Timer2 can be optionally used as the shift clock source
for the MSSP module operating in SPI mode.
Additional information is provided in Section 17.0
“Master Synchronous Serial Port (MSSP) Module”.
FIGURE 13-1: TIMER2 BLOCK DIAGRAM
TABLE 13-1: REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 57
PIR1 —ADIF RC1IF TX1IF SSPIF —TMR2IFTMR1IF 60
PIE1 —ADIE RC1IE TX1IE SSPIE —TMR2IETMR1IE 60
IPR1 —ADIP RC1IP TX1IP SSPIP —TMR2IPTMR1IP 60
TMR2 Timer2 Register 58
T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 58
PR2 Timer2 Period Register 58
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer2 module.
Comparator
TMR2 Output
TMR2
Postscaler
Prescaler PR2
2
FOSC/4
1:1 to 1:16
1:1, 1:4, 1:16
4
T2OUTPS<3:0>
T2CKPS<1:0>
Set TMR2IF
Internal Data Bus
8
Reset
TMR2/PR2
8
8
(to PWM or MSSP)
Match
2010 Microchip Technology Inc. DS39770C-page 149
PIC18F85J90 FAMILY
14.0 TIMER3 MODULE
The Timer3 timer/counter module incorporates these
features:
• Software selectable operation as a 16-bit timer or
counter
• Readable and writable 8-bit registers (TMR3H
and TMR3L)
• Selectable clock source (internal or external) with
device clock or Timer1 oscillator internal options
• Interrupt on overflow
• Module Reset on CCP Special Event Trigger
A simplified block diagram of the Timer3 module is
shown in Figure 14-1. A block diagram of the module’s
operation in Read/Write mode is shown in Figure 14-2.
The Timer3 module is controlled through the T3CON
register (Register 14-1). It also selects the clock source
options for the CCP modules. See Section 15.2.2
“Timer1/Timer3 Mode Selection” for more
information.
REGISTER 14-1: T3CON: TIMER3 CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 RD16: 16-Bit Read/Write Mode Enable bit
1 = Enables register read/write of Timer3 in one 16-bit operation
0 = Enables register read/write of Timer3 in two 8-bit operations
bit 6,3 T3CCP<2:1>: Timer3 and Timer1 to CCPx Enable bits
1x = Timer3 is the capture/compare clock source for the CCP modules
01 = Timer3 is the capture/compare clock source for CCP2;
Timer1 is the capture/compare clock source for CCP1
00 = Timer1 is the capture/compare clock source for the CCP modules
bit 5-4 T3CKPS<1:0>: Timer3 Input Clock Prescale Select bits
11 = 1:8 Prescale value
10 = 1:4 Prescale value
01 = 1:2 Prescale value
00 = 1:1 Prescale value
bit 2 T3SYNC: Timer3 External Clock Input Synchronization Control bit
(Not usable if the device clock comes from Timer1/Timer3.)
When TMR3CS = 1:
1 = Do not synchronize external clock input
0 = Synchronize external clock input
When TMR3CS = 0:
This bit is ignored. Timer3 uses the internal clock when TMR3CS = 0.
bit 1 TMR3CS: Timer3 Clock Source Select bit
1 = External clock input from Timer1 oscillator or T13CKI (on the rising edge after the first
falling edge)
0 = Internal clock (FOSC/4)
bit 0 TMR3ON: Timer3 On bit
1 = Enables Timer3
0 = Stops Timer3
PIC18F85J90 FAMILY
DS39770C-page 150 2010 Microchip Technology Inc.
14.1 Timer3 Operation
Timer3 can operate in one of three modes:
•Timer
• Synchronous Counter
• Asynchronous Counter
The operating mode is determined by the clock select
bit, TMR3CS (T3CON<1>). When TMR3CS is cleared
(= 0), Timer3 increments on every internal instruction
cycle (FOSC/4). When the bit is set, Timer3 increments
on every rising edge of the Timer1 external clock input
or the Timer1 oscillator, if enabled.
As with Timer1, the RC1/T1OSI and
RC0/T1OSO/T13CKI pins become inputs when the
Timer1 oscillator is enabled. This means the values of
TRISC<1:0> are ignored and the pins are read as ‘0’.
FIGURE 14-1: TIMER3 BLOCK DIAGRAM (8-BIT MODE)
FIGURE 14-2: TIMER3 BLOCK DIAGRAM (16-BIT READ/WRITE MODE)
T3SYNC
TMR3CS
T3CKPS<1:0>
Sleep Input
T1OSCEN(1)
FOSC/4
Internal
Clock
Prescaler
1, 2, 4, 8
Synchronize
Detect
1
0
2
T1OSO/T13CKI
T1OSI
1
0
TMR3ON
TMR3L Set
TMR3IF
on Overflow
TMR3
High Byte
Timer1 Oscillator
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
On/Off
Timer3
CCPx Special Event Trigger
CCPx Select from T3CON<6,3>
Clear TMR3
Timer1 Clock Input
T3SYNC
TMR3CS
T3CKPS<1:0>
Sleep Input
T1OSCEN(1)
FOSC/4
Internal
Clock
Prescaler
1, 2, 4, 8
Synchronize
Detect
1
0
2
T13CKI/T1OSO
T1OSI
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
1
0
TMR3L
Internal Data Bus
8
Set
TMR3IF
on Overflow
TMR3
TMR3H
High Byte
88
8
Read TMR3L
Write TMR3L
8
TMR3ON
CCPx Special Event Trigger
Timer1 Oscillator
On/Off
Timer3
Timer1 Clock Input
CCPx Select from T3CON<6,3>
Clear TMR3
2010 Microchip Technology Inc. DS39770C-page 151
PIC18F85J90 FAMILY
14.2 Timer3 16-Bit Read/Write Mode
Timer3 can be configured for 16-bit reads and writes
(see Figure 14-2). When the RD16 control bit
(T3CON<7>) is set, the address for TMR3H is mapped
to a buffer register for the high byte of Timer3. A read
from TMR3L will load the contents of the high byte of
Timer3 into the Timer3 High Byte Buffer register. This
provides the user with the ability to accurately read all
16 bits of Timer1 without having to determine whether
a read of the high byte, followed by a read of the low
byte, has become invalid due to a rollover between
reads.
A write to the high byte of Timer3 must also take place
through the TMR3H Buffer register. The Timer3 high
byte is updated with the contents of TMR3H when a
write occurs to TMR3L. This allows a user to write all
16 bits to both the high and low bytes of Timer3 at once.
The high byte of Timer3 is not directly readable or
writable in this mode. All reads and writes must take
place through the Timer3 High Byte Buffer register.
Writes to TMR3H do not clear the Timer3 prescaler.
The prescaler is only cleared on writes to TMR3L.
14.3 Using the Timer1 Oscillator as the
Timer3 Clock Source
The Timer1 internal oscillator may be used as the clock
source for Timer3. The Timer1 oscillator is enabled by
setting the T1OSCEN (T1CON<3>) bit. To use it as the
Timer3 clock source, the TMR3CS bit must also be set.
As previously noted, this also configures Timer3 to
increment on every rising edge of the oscillator source.
The Timer1 oscillator is described in Section 12.0
“Timer1 Module”.
14.4 Timer3 Interrupt
The TMR3 register pair (TMR3H:TMR3L) increments
from 0000h to FFFFh and overflows to 0000h. The
Timer3 interrupt, if enabled, is generated on overflow
and is latched in interrupt flag bit, TMR3IF (PIR2<1>).
This interrupt can be enabled or disabled by setting or
clearing the Timer3 Interrupt Enable bit, TMR3IE
(PIE2<1>).
14.5 Resetting Timer3 Using the CCP
Special Event Trigger
If CCP1 or CCP2 is configured to use Timer3 and to
generate a Special Event Trigger in Compare mode
(CCPxM<3:0> = 1011), this signal will reset Timer3.
The trigger from CCP2 will also start an A/D conversion
if the A/D module is enabled (see Section 15.3.4
“Special Event Trigger” for more information).
The module must be configured as either a timer or
synchronous counter to take advantage of this feature.
When used this way, the CCPRxH:CCPRxL register
pair effectively becomes a period register for Timer3.
If Timer3 is running in Asynchronous Counter mode,
the Reset operation may not work.
In the event that a write to Timer3 coincides with a
Special Event Trigger from a CCP module, the write will
take precedence.
TABLE 14-1: REGISTERS ASSOCIATED WITH TIMER3 AS A TIMER/COUNTER
Note: The Special Event Triggers from the CCPx
module will not set the TMR3IF interrupt
flag bit (PIR2<1>).
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 57
PIR2 OSCFIF CMIF — — BCLIF LVDIF TMR3IF —60
PIE2 OSCFIE CMIE — — BCLIE LVDIE TMR3IE —60
IPR2 OSCFIP CMIP — — BCLIP LVDIP TMR3IP —60
TMR3L Timer3 Register Low Byte 59
TMR3H Timer3 Register High Byte 59
T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 58
T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 59
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer3 module.
PIC18F85J90 FAMILY
DS39770C-page 152 2010 Microchip Technology Inc.
NOTES:
2010 Microchip Technology Inc. DS39770C-page 153
PIC18F85J90 FAMILY
15.0 CAPTURE/COMPARE/PWM
(CCP) MODULES
PIC18F85J90 family devices have two CCP
(Capture/Compare/PWM) modules, designated CCP1
and CCP2. Both modules implement standard Capture,
Compare and Pulse-Width Modulation (PWM) modes.
Each CCP module contains a 16-bit register which can
operate as a 16-bit Capture register, a 16-bit Compare
register or a PWM Master/Slave Duty Cycle register.
For the sake of clarity, all CCP module operation in the
following sections is described with respect to CCP2,
but is equally applicable to CCP1.
REGISTER 15-1: CCPxCON: CCPx CONTROL REGISTER (CCP1, CCP2 MODULES)
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—— DCxB1 DCxB0 CCPxM3 CCPxM2 CCPxM1 CCPxM0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 Unimplemented: Read as ‘0’
bit 5-4 DCxB<1:0>: PWM Duty Cycle bit 1 and bit 0 for CCPx Module
Capture mode:
Unused.
Compare mode:
Unused.
PWM mode:
These bits are the two Least Significant bits (bit 1 and bit 0) of the 10-bit PWM duty cycle. The eight
Most Significant bits (DCx<9:2>) of the duty cycle are found in CCPRxL.
bit 3-0 CCPxM<3:0>: CCPx Module Mode Select bits
0000 = Capture/Compare/PWM disabled (resets CCPx module)
0001 = Reserved
0010 = Compare mode, toggle output on match (CCPxIF bit is set)
0011 = Reserved
0100 = Capture mode, every falling edge
0101 = Capture mode, every rising edge
0110 = Capture mode, every 4th rising edge
0111 = Capture mode, every 16th rising edge
1000 = Compare mode: initialize CCPx pin low; on compare match, force CCPx pin high (CCPxIF bit
is set)
1001 = Compare mode: initialize CCPx pin high; on compare match, force CCPx pin low (CCPxIF bit
is set)
1010 = Compare mode: generate software interrupt on compare match (CCPxIF bit is set, CCPx pin
reflects I/O state)
1011 = Compare mode: Special Event Trigger; reset timer; start A/D conversion on CCPx match
(CCPxIF bit is set)(1)
11xx =PWM mode
Note 1: CCPxM<3:0> = 1011 will only reset the timer and not start an A/D conversion on CCP1 match.
PIC18F85J90 FAMILY
DS39770C-page 154 2010 Microchip Technology Inc.
15.1 CCP Module Configuration
Each Capture/Compare/PWM module is associated
with a control register (generically, CCPxCON) and a
data register (CCPRx). The data register in turn is com-
prised of two 8-bit registers: CCPRxL (low byte) and
CCPRxH (high byte). All registers are both readable
and writable.
15.1.1 CCP MODULES AND TIMER
RESOURCES
The CCP modules utilize Timers 1, 2 or 3, depending
on the mode selected. Timer1 and Timer3 are available
to modules in Capture or Compare modes, while
Timer2 is available for modules in PWM mode.
TABLE 15-1: CCP MODE – TIMER
RESOURCE
The assignment of a particular timer to a module is
determined by the Timer to CCP enable bits in the
T3CON register (Register 14-1). Both modules may be
active at any given time and may share the same timer
resource if they are configured to operate in the same
mode (Capture/Compare or PWM) at the same time.
The interactions between the two modules are
summarized in Table 15-2.
Depending on the configuration selected, up to four
timers may be active at once, with modules in the same
configuration (Capture/Compare or PWM) sharing
timer resources. The possible configurations are
shown in Figure 15-1.
15.1.2 OPEN-DRAIN OUTPUT OPTION
When operating in Output mode (i.e., in Compare or
PWM modes), the drivers for the CCPx pins can be
optionally configured as open-drain outputs. This
feature allows the voltage level on the pin to be pulled
to a higher level through an external pull-up resistor
and allows the output to communicate with external
circuits without the need for additional level shifters.
The open-drain output option is controlled by the
CCP2OD and CCP1OD bits (TRISG<6:5>). Setting the
appropriate bit configures the pin for the corresponding
module for open-drain operation.
15.1.3 CCP2 PIN ASSIGNMENT
The pin assignment for CCP2 (Capture input, Compare
and PWM output) can change, based on device config-
uration. The CCP2MX Configuration bit determines
which pin CCP2 is multiplexed to. By default, it is
assigned to RC1 (CCP2MX = 1). If the Configuration bit
is cleared, CCP2 is multiplexed with RE7.
Changing the pin assignment of CCP2 does not
automatically change any requirements for configuring
the port pin. Users must always verify that the appropri-
ate TRIS register is configured correctly for CCP2
operation, regardless of where it is located.
FIGURE 15-1: CCP AND TIMER INTERCONNECT CONFIGURATIONS
CCP Mode Timer Resource
Capture
Compare
PWM
Timer1 or Timer3
Timer1 or Timer3
Timer2
TMR1
TMR2
TMR3
CCP2
CCP1
TMR1
TMR2
TMR3
CCP2
CCP1
TMR1 TMR3
TMR2
CCP2
CCP1
T3CCP<2:1> = 00 T3CCP<2:1> = 01 T3CCP<2:1> = 1x
Timer1 is used for all Capture
and Compare operations for
all CCP modules. Timer2 is
used for PWM operations for
all CCP modules. Modules
may share either timer
resource as a common time
base.
Timer1 is used for Capture
and Compare operations for
CCP1 and Timer 3 is used for
CCP2.
Both the modules use Timer2
as a common time base if they
are in PWM modes.
Timer3 is used for all Capture
and Compare operations for
all CCP modules. Timer2 is
used for PWM operations for
all CCP modules. Modules
may share either timer
resource as a common time
base.
2010 Microchip Technology Inc. DS39770C-page 155
PIC18F85J90 FAMILY
TABLE 15-2: INTERACTIONS BETWEEN CCP1 AND CCP2 FOR TIMER RESOURCES
CCP1 Mode CCP2 Mode Interaction
Capture Capture Each module can use TMR1 or TMR3 as the time base. The time base can be different
for each CCP.
Capture Compare CCP2 can be configured for the Special Event Trigger to reset TMR1 or TMR3
(depending upon which time base is used). Automatic A/D conversions on a trigger event
can also be done. Operation of CCP1 could be affected if it is using the same timer as a
time base.
Compare Capture CCP1 can be configured for the Special Event Trigger to reset TMR1 or TMR3
(depending upon which time base is used). Operation of CCP2 could be affected if it is
using the same timer as a time base.
Compare Compare Either module can be configured for the Special Event Trigger to reset the time base.
Automatic A/D conversions on CCP2 trigger event can be done. Conflicts may occur if
both modules are using the same time base.
Capture PWM None
Compare PWM None
PWM Capture None
PWM Compare None
PWM PWM Both PWMs will have the same frequency and update rate (TMR2 interrupt).
PIC18F85J90 FAMILY
DS39770C-page 156 2010 Microchip Technology Inc.
15.2 Capture Mode
In Capture mode, the CCPR2H:CCPR2L register pair
captures the 16-bit value of the TMR1 or TMR3 register
when an event occurs on the CCP2 pin (RC1 or RE7,
depending on device configuration). An event is
defined as one of the following:
• every falling edge
• every rising edge
• every 4th rising edge
• every 16th rising edge
The event is selected by the mode select bits,
CCP2M<3:0> (CCP2CON<3:0>). When a capture is
made, the interrupt request flag bit, CCP2IF (PIR3<2>),
is set; it must be cleared in software. If another capture
occurs before the value in register, CCPR2, is read, the
old captured value is overwritten by the new captured
value.
15.2.1 CCP PIN CONFIGURATION
In Capture mode, the appropriate CCPx pin should be
configured as an input by setting the corresponding
TRIS direction bit.
15.2.2 TIMER1/TIMER3 MODE SELECTION
The timers that are to be used with the capture feature
(Timer1 and/or Timer3) must be running in Timer mode or
Synchronized Counter mode. In Asynchronous Counter
mode, the capture operation may not work. The timer to
be used with each CCP module is selected in the T3CON
register (see Section 15.1.1 “CCP Modules and Timer
Resources”).
15.2.3 SOFTWARE INTERRUPT
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep the
CCP2IE bit (PIE3<2>) clear to avoid false interrupts
and should clear the flag bit, CCP2IF, following any
such change in operating mode.
15.2.4 CCP PRESCALER
There are four prescaler settings in Capture mode.
They are specified as part of the operating mode
selected by the mode select bits (CCP2M<3:0>).
Whenever the CCP module is turned off, or the CCP
module is not in Capture mode, the prescaler counter
is cleared. This means that any Reset will clear the
prescaler counter.
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleared; therefore, the first capture may be from
a non-zero prescaler. Example 15-1 shows the
recommended method for switching between capture
prescalers. This example also clears the prescaler
counter and will not generate the “false” interrupt.
EXAMPLE 15-1: CHANGING BETWEEN
CAPTURE PRESCALERS
FIGURE 15-2: CAPTURE MODE OPERATION BLOCK DIAGRAM
Note: If RC1/CCP2 or RE7/CCP2 is configured
as an output, a write to the port can cause
a capture condition.
CLRF CCP2CON ; Turn CCP module off
MOVLW NEW_CAPT_PS ; Load WREG with the
; new prescaler mode
; value and CCP ON
MOVWF CCP2CON ; Load CCP2CON with
; this value
CCPR1H CCPR1L
TMR1H TMR1L
Set CCP1IF
TMR3
Enable
Q1:Q4
CCP1CON<3:0>
CCP1 Pin
Prescaler
1, 4, 16
and
Edge Detect
TMR1
Enable
T3CCP2
T3CCP2
CCPR2H CCPR2L
TMR1H TMR1L
Set CCP2IF
TMR3
Enable
CCP2CON<3:0>
CCP2 Pin
Prescaler
1, 4, 16
TMR3H TMR3L
TMR1
Enable
T3CCP2
T3CCP1
T3CCP2
T3CCP1
TMR3H TMR3L
and
Edge Detect
4
4
4
2010 Microchip Technology Inc. DS39770C-page 157
PIC18F85J90 FAMILY
15.3 Compare Mode
In Compare mode, the 16-bit CCPR2 register value is
constantly compared against either the TMR1 or TMR3
register pair value. When a match occurs, the CCP2
pin can be:
• driven high
• driven low
• toggled (high-to-low or low-to-high)
• remain unchanged (that is, reflects the state of the
I/O latch)
The action on the pin is based on the value of the mode
select bits (CCP2M<3:0>). At the same time, the
interrupt flag bit, CCP2IF, is set.
15.3.1 CCP PIN CONFIGURATION
The user must configure the CCPx pin as an output by
clearing the appropriate TRIS bit.
15.3.2 TIMER1/TIMER3 MODE SELECTION
Timer1 and/or Timer3 must be running in Timer mode,
or Synchronized Counter mode, if the CCP module is
using the compare feature. In Asynchronous Counter
mode, the compare operation may not work.
15.3.3 SOFTWARE INTERRUPT MODE
When the Generate Software Interrupt mode is chosen
(CCP2M<3:0> = 1010), the CCP2 pin is not affected.
Only a CCP interrupt is generated, if enabled, and the
CCP2IE bit is set.
15.3.4 SPECIAL EVENT TRIGGER
Both CCP modules are equipped with a Special Event
Trigger. This is an internal hardware signal generated
in Compare mode to trigger actions by other modules.
The Special Event Trigger is enabled by selecting
the Compare Special Event Trigger mode
(CCP2M<3:0> = 1011).
For either CCP module, the Special Event Trigger resets
the timer register pair for whichever timer resource is
currently assigned as the module’s time base. This
allows the CCPRx registers to serve as a programmable
period register for either timer.
The Special Event Trigger for CCP2 can also start an
A/D conversion. In order to do this, the A/D Converter
must already be enabled.
FIGURE 15-3: COMPARE MODE OPERATION BLOCK DIAGRAM
Note: Clearing the CCP2CON register will force
the RC1 or RE7 compare output latch
(depending on device configuration) to the
default low level. This is not the PORTC or
PORTE I/O data latch.
Note: The Special Event Trigger of CCP1 only
resets Timer1/Timer3 and cannot start an
A/D conversion even when the A/D
Converter is enabled.
CCPR1H CCPR1L
TMR1H TMR1L
Comparator Q
S
R
Output
Logic
Special Event Trigger
Set CCP1IF
CCP1 Pin
TRIS
CCP1CON<3:0>
Output Enable
TMR3H TMR3L
CCPR2H CCPR2L
Comparator
1
0
T3CCP2
T3CCP1
Set CCP2IF
1
0
Compare
4
(Timer1 Reset)
Q
S
R
Output
Logic
Special Event Trigger
CCP2 Pin
TRIS
CCP2CON<3:0>
Output Enable
4
(Timer1/Timer3 Reset, A/D Trigger)
Match
Compare
Match
PIC18F85J90 FAMILY
DS39770C-page 158 2010 Microchip Technology Inc.
TABLE 15-3: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on Page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 57
RCON IPEN —CM RI TO PD POR BOR 58
PIR3 —LCDIF RC2IF TX2IF — CCP2IF CCP1IF —60
PIE3 —LCDIE RC2IE TX2IE — CCP2IE CCP1IE —60
IPR3 —LCDIP RC2IP TX2IP — CCP2IP CCP1IP —60
PIR2 OSCFIF CMIF — — BCLIF LVDIF TMR3IF —60
PIE2 OSCFIE CMIE — — BCLIE LVDIE TMR3IE —60
IPR2 OSCFIP CMIP — — BCLIP LVDIP TMR3IP —60
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 60
TRISE TRISE7 TRISE6 TRISE5 TRISE4 TRISE3 —TRISE1 TRISE0 60
TRISG SPIOD CCP2OD CCP1OD TRISG4 TRISG3 TRISG2 TRISG1 TRISG0 60
TMR1L Timer1 Register Low Byte 58
TMR1H Timer1 Register High Byte 58
T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 58
TMR3H Timer3 Register High Byte 59
TMR3L Timer3 Register Low Byte 59
T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 59
CCPR1L Capture/Compare/PWM Register 1 Low Byte 61
CCPR1H Capture/Compare/PWM Register 1 High Byte 61
CCP1CON — — DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 61
CCPR2L Capture/Compare/PWM Register 2 Low Byte 62
CCPR2H Capture/Compare/PWM Register 2 High Byte 61
CCP2CON — — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 62
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by Capture/Compare, Timer1 or Timer3.
2010 Microchip Technology Inc. DS39770C-page 159
PIC18F85J90 FAMILY
15.4 PWM Mode
In Pulse-Width Modulation (PWM) mode, the CCP2 pin
produces up to a 10-bit resolution PWM output. Since
the CCP2 pin is multiplexed with a PORTC or PORTE
data latch, the appropriate TRIS bit must be cleared to
make the CCP2 pin an output.
Figure 15-4 shows a simplified block diagram of the
CCP1 module in PWM mode.
For a step-by-step procedure on how to set up the CCP
module for PWM operation, see Section 15.4.3
“Setup for PWM Operation”.
FIGURE 15-4: SIMPLIFIED PWM BLOCK
DIAGRAM
A PWM output (Figure 15-5) has a time base (period)
and a time that the output stays high (duty cycle). The
frequency of the PWM is the inverse of the period
(1/period).
FIGURE 15-5: PWM OUTPUT
15.4.1 PWM PERIOD
The PWM period is specified by writing to the PR2
register. The PWM period can be calculated using the
following formula:
EQUATION 15-1:
PWM frequency is defined as 1/[PWM period].
When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
•TMR2 is cleared
• The CCP2 pin is set (exception: if PWM duty
cycle = 0%, the CCP2 pin will not be set)
• The PWM duty cycle is latched from CCPR2L into
CCPR2H
Note: Clearing the CCP2CON register will force
the RC1 or RE7 output latch (depending
on device configuration) to the default low
level. This is not the PORTC or PORTE
I/O data latch.
CCPR1L
CCPR1H (Slave)
Comparator
TMR2
Comparator
PR2
(Note 1)
RQ
S
Duty Cycle Registers CCP1CON<5:4>
Clear Timer,
CCP1 pin and
latch D.C.
TRISC<2>
RC2/CCP1
Note 1: The 8-bit TMR2 value is concatenated with the 2-bit
internal Q clock, or 2 bits of the prescaler, to create
the 10-bit time base.
Note: The Timer2 postscalers (see Section 13.0
“Timer2 Module”) are not used in the
determination of the PWM frequency. The
postscaler could be used to have a servo
update rate at a different frequency than
the PWM output.
Period
Duty Cycle
TMR2 = PR2
TMR2 = Duty Cycle
TMR2 = PR2
PWM Period = (PR2) + 1] • 4 • TOSC •
(TMR2 Prescale Value)
PIC18F85J90 FAMILY
DS39770C-page 160 2010 Microchip Technology Inc.
15.4.2 PWM DUTY CYCLE
The PWM duty cycle is specified by writing to the
CCPR2L register and to the CCP2CON<5:4> bits. Up
to 10-bit resolution is available. The CCPR2L contains
the eight MSbs and the CCP2CON<5:4> contains the
two LSbs. This 10-bit value is represented by
CCPR2L:CCP2CON<5:4>. The following equation is
used to calculate the PWM duty cycle in time:
EQUATION 15-2:
CCPR2L and CCP2CON<5:4> can be written to at any
time, but the duty cycle value is not latched into
CCPR2H until after a match between PR2 and TMR2
occurs (i.e., the period is complete). In PWM mode,
CCPR2H is a read-only register.
The CCPR2H register and a 2-bit internal latch are
used to double-buffer the PWM duty cycle. This
double-buffering is essential for glitchless PWM
operation.
When the CCPR2H and 2-bit latch match TMR2,
concatenated with an internal 2-bit Q clock or 2 bits of
the TMR2 prescaler, the CCP2 pin is cleared.
The maximum PWM resolution (bits) for a given PWM
frequency is given by the equation:
EQUATION 15-3:
TABLE 15-4: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz
PWM Duty Cycle = (CCPR2L:CCP2CON<5:4>) •
TOSC • (TMR2 Prescale Value)
Note: If the PWM duty cycle value is longer than
the PWM period, the CCP2 pin will not be
cleared.
FOSC
FPWM
---------------
log
2log
----------------------------- b i t s=
PWM Resolution (max)
PWM Frequency 2.44 kHz 9.77 kHz 39.06 kHz 156.25 kHz 312.50 kHz 416.67 kHz
Timer Prescaler (1, 4, 16)1641111
PR2 Value FFh FFh FFh 3Fh 1Fh 17h
Maximum Resolution (bits) 14 12 10 8 7 6.58
2010 Microchip Technology Inc. DS39770C-page 161
PIC18F85J90 FAMILY
15.4.3 SETUP FOR PWM OPERATION
The following steps should be taken when configuring
the CCP module for PWM operation:
1. Set the PWM period by writing to the PR2
register.
2. Set the PWM duty cycle by writing to the
CCPR2L register and CCP2CON<5:4> bits.
3. Make the CCP2 pin an output by clearing the
appropriate TRIS bit.
4. Set the TMR2 prescale value, then enable
Timer2 by writing to T2CON.
5. Configure the CCP2 module for PWM operation.
TABLE 15-5: REGISTERS ASSOCIATED WITH PWM AND TIMER2
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on Page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 57
RCON IPEN —CM RI TO PD POR BOR 58
PIR1 —ADIF RC1IF TX1IF SSPIF —TMR2IFTMR1IF 60
PIE1 —ADIE RC1IE TX1IE SSPIE —TMR2IETMR1IE 60
IPR1 —ADIP RC1IP TX1IP SSPIP —TMR2IPTMR1IP 60
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 60
TRISE TRISE7 TRISE6 TRISE5 TRISE4 TRISE3 —TRISE1 TRISE0 60
TRISG SPIOD CCP2OD CCP1OD TRISG4 TRISG3 TRISG2 TRISG1 TRISG0 60
TMR2 Timer2 Register 58
PR2 Timer2 Period Register 58
T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 58
CCPR1L Capture/Compare/PWM Register 1 Low Byte 61
CCPR1H Capture/Compare/PWM Register 1 High Byte 61
CCP1CON —— DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 61
CCPR2L Capture/Compare/PWM Register 2 Low Byte 62
CCPR2H Capture/Compare/PWM Register 2 High Byte 61
CCP2CON —— DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 62
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PWM or Timer2.
PIC18F85J90 FAMILY
DS39770C-page 162 2010 Microchip Technology Inc.
NOTES:
2010 Microchip Technology Inc. DS39770C-page 163
PIC18F85J90 FAMILY
16.0 LIQUID CRYSTAL DISPLAY
(LCD) DRIVER MODULE
The Liquid Crystal Display (LCD) driver module
generates the timing control to drive a static or
multiplexed LCD panel. It also provides control of the
LCD pixel data. The module can drive panels of up to
192 pixels (48 segments by 4 commons) in 80-pin
devices, and 132 pixels (33 segments by 4 commons) in
64-pin devices.
The LCD driver module supports these features:
• Direct driving of LCD panel
• On-chip bias generator with dedicated charge
pump to support a range of fixed and variable bias
options
• Up to four commons, with four Multiplexing modes
• Up to 48 (80-pin devices) or 33 (64-pin devices)
segments
• Three LCD clock sources with selectable prescaler,
with a fourth source available for use with the LCD
charge pump
A simplified block diagram of the module is shown in
Figure 16-1.
FIGURE 16-1: LCD DRIVER MODULE BLOCK DIAGRAM
COM3:COM0
Timing Control
Data Bus
INTRC Oscillator
FOSC/4
T13CKI
192
to
48
MUX SEG<47:0>
To I/O Pins
24 x 8 (= 4 x 48)
LCD DATA
LCDCON
LCDPS
LCDSEx
LCDDATA0
LCDDATA1
LCDDATA22
LCDDATA23
.
.
.
LCD Bias Generation
LCD Clock
Source Select
LCD
Charge Pump
48
4
Bias
Voltage
8
INTOSC Oscillator
PIC18F85J90 FAMILY
DS39770C-page 164 2010 Microchip Technology Inc.
16.1 LCD Registers
The LCD driver module has 33 registers:
• LCD Control Register (LCDCON)
• LCD Phase Register (LCDPS)
• LCD Regulator Control Register (LCDREG)
• Six LCD Segment Enable Registers
(LCDSE5:LCDSE0)
• 24 LCD Data Registers
(LCDDATA23:LCDDATA0)
16.1.1 LCD CONTROL REGISTERS
The LCDCON register, shown in Register 16-1,
controls the overall operation of the module. Once the
module is configured, the LCDEN (LCDCON<7>) bit is
used to enable or disable the LCD module. The LCD
panel can also operate during Sleep by clearing the
SLPEN (LCDCON<6>) bit.
The LCDPS register, shown in Register 16-2,
configures the LCD clock source prescaler and the type
of waveform: Type-A or Type-B. Details on these
features are provided in Section 16.2 “LCD Clock
Source”, Section 16.3 “LCD Bias Generation” and
Section 16.8 “LCD Waveform Generation”.
The LCDREG register is described in Section 16.3
“LCD Bias Generation”.
The LCD Segment Enable registers (LCDSEx)
configure the functions of the port pins. Setting the
segment enable bit for a particular segment configures
that pin as an LCD driver. The prototype LCDSE
register is shown in Register 16-3. There are six
LCDSE registers (LCDSE5:LCDSE0) listed in
Table 16-1.
REGISTER 16-1: LCDCON: LCD CONTROL REGISTER
R/W-0 R/W-0 R/C-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
LCDEN SLPEN WERR — CS1 CS0 LMUX1 LMUX0
bit 7 bit 0
Legend: C = Clearable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 LCDEN: LCD Driver Enable bit
1 = LCD driver module is enabled
0 = LCD driver module is disabled
bit 6 SLPEN: LCD Driver Enable in Sleep mode bit
1 = LCD driver module is disabled in Sleep mode
0 = LCD driver module is enabled in Sleep mode
bit 5 WERR: LCD Write Failed Error bit
1 = LCDDATAx register written while LCDPS<4> = 0 (must be cleared in software)
0 = No LCD write error
bit 4 Unimplemented: Read as ‘0’
bit 3-2 CS<1:0>: Clock Source Select bits
1x = INTRC (31 kHz)
01 = T13CKI (Timer1)
00 = System clock (FOSC/4)
bit 1-0 LMUX<1:0>: Commons Select bits
LMUX<1:0> Multiplex Type
Maximum Number of Pixels:
Bias Type
PIC18F6XJ90 PIC18F8XJ90
00 Static (COM0) 33 48 Static
01 1/2 (COM1:COM0) 66 96 1/2 or 1/3
10 1/3 (COM2:COM0) 99 144 1/2 or 1/3
11 1/4 (COM3:COM0) 132 192 1/3
2010 Microchip Technology Inc. DS39770C-page 165
PIC18F85J90 FAMILY
REGISTER 16-2: LCDPS: LCD PHASE REGISTER
R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0
WFT BIASMD LCDA WA LP3 LP2 LP1 LP0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 WFT: Waveform Type Select bit
1 = Type-B waveform (phase changes on each frame boundary)
0 = Type-A waveform (phase changes within each common type)
bit 6 BIASMD: Bias Mode Select bit
When LMUX<1:0> = 00:
0 = Static Bias mode (do not set this bit to ‘1’)
When LMUX<1:0> = 01 or 10:
1 = 1/2 Bias mode
0 = 1/3 Bias mode
When LMUX<1:0> = 11:
0 = 1/3 Bias mode (do not set this bit to ‘1’)
bit 5 LCDA: LCD Active Status bit
1 = LCD driver module is active
0 = LCD driver module is inactive
bit 4 WA: LCD Write Allow Status bit
1 = Write into the LCDDATAx registers is allowed
0 = Write into the LCDDATAx registers is not allowed
bit 3-0 LP<3:0>: LCD Prescaler Select bits
1111 = 1:16
1110 = 1:15
1101 = 1:14
1100 = 1:13
1011 = 1:12
1010 = 1:11
1001 = 1:10
1000 = 1:9
0111 = 1:8
0110 = 1:7
0101 = 1:6
0100 = 1:5
0011 = 1:4
0010 = 1:3
0001 = 1:2
0000 = 1:1
PIC18F85J90 FAMILY
DS39770C-page 166 2010 Microchip Technology Inc.
TABLE 16-1: LCDSE REGISTERS AND ASSOCIATED SEGMENTS
REGISTER 16-3: LCDSEx: LCD SEGMENT ENABLE REGISTERS
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
SE(n + 7) SE(n + 6) SE(n + 5) SE(n + 4) SE(n + 3) SE(n + 2) SE(n + 1) SE(n)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 SEG(n + 7):SEG(n): Segment Enable bits
For LCDSE0: n = 0
For LCDSE1: n = 8
For LCDSE2: n = 16
For LCDSE3: n = 24
For LCDSE4: n = 32
For LCDSE5: n = 40
1 = Segment function of the pin is enabled, digital I/O disabled
0 = I/O function of the pin is enabled
Register Segments
LCDSE0 7:0
LCDSE1 15:8
LCDSE2 23:16
LCDSE3 31:24
LCDSE4(1) 39:32
LCDSE5(2) 47:40
Note 1: LCDSE4<7:1> (SEG39:SEG33) are not implemented in 64-pin devices.
2: LCDSE5 is not implemented in 64-pin devices.
2010 Microchip Technology Inc. DS39770C-page 167
PIC18F85J90 FAMILY
16.1.2 LCD DATA REGISTERS
Once the module is initialized for the LCD panel, the
individual bits of the LCDDATA23:LCDDATA0 registers
are cleared or set to represent a clear or dark pixel,
respectively. Specific sets of LCDDATA registers are
used with specific segments and common signals.
Each bit represents a unique combination of a specific
segment connected to a specific common.
Individual LCDDATA bits are named by the convention
“SxxCy”, with “xx” as the segment number and “y” as
the common number. The relationship is summarized
in Table 16-2. The prototype LCDDATA register is
shown in Register 16-4.
TABLE 16-2: LCDDATA REGISTERS AND BITS FOR SEGMENT AND COM COMBINATIONS
Note: In 64-pin devices, writing into the registers
LCDDATA5, LCDDATA11, LCDDATA17,
and LCDDATA23 will not affect the status
of any pixels.
REGISTER 16-4: LCDDATAx: LCD DATA REGISTERS
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
S(n + 7)Cy S(n + 6)Cy S(n + 5)Cy S(n + 4)Cy S(n + 3)Cy S(n + 2)Cy S(n + 1)Cy S(n)Cy
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 S(n + 7)Cy:S(n)Cy: Pixel On bits
For LCDDATA0 through LCDDATA5: n = (8x), y = 0
For LCDDATA6 through LCDDATA11: n = (8(x – 6)), y = 1
For LCDDATA12 through LCDDATA17: n = (8(x – 12)), y = 2
For LCDDATA18 through LCDDATA23: n = (8(x – 18)), y = 3
1 = Pixel on (dark)
0 = Pixel off (clear)
Segments
COM Lines
0123
0 through 7 LCDDATA0 LCDDATA6 LCDDATA12 LCDDATA18
S00C0:S07C0 S00C1:S07C1 S00C2:S07C2 S00C3:S07C3
8 through 15 LCDDATA1 LCDDATA7 LCDDATA13 LCDDATA19
S08C0:S15C0 S08C1:S15C1 S08C2:S15C2 S08C0:S15C3
16 through 23 LCDDATA2 LCDDATA8 LCDDATA14 LCDDATA20
S16C0:S23C0 S16C1:S23C1 S16C2:S23C2 S16C3:S23C3
24 through 31 LCDDATA3 LCDDATA9 LCDDATA15 LCDDATA21
S24C0:S31C0 S24C1:S31C1 S24C2:S31C2 S24C3:S31C3
32 through 39 LCDDATA4(1) LCDDATA10(1) LCDDATA16(1) LCDDATA22(1)
S32C0:S39C0 S32C1:S39C1 S32C2:S39C2 S32C3:S39C3
40 through 47 LCDDATA5(2) LCDDATA11(2) LCDDATA17(2) LCDDATA23(2)
S40C0:S47C0 S40C1:S47C1 S40C2:S47C2 S40C3:S47C3
Note 1: Bits<7:1> of these registers are not implemented in 64-pin devices. Bit 0 of these registers (SEG32Cy) is
always implemented.
2: These registers are not implemented on 64-pin devices.
PIC18F85J90 FAMILY
DS39770C-page 168 2010 Microchip Technology Inc.
16.2 LCD Clock Source
The LCD driver module generates its internal clock
from 3 possible sources:
• System clock (FOSC/4)
• Timer1 oscillator
• INTRC source
The LCD clock generator uses a configurable
divide-by-32/divide-by-8192 postscaler to produce a
baseline frequency of about 1 kHz nominal, regardless
of the source selected. The clock source selection and
the postscaler configuration are determined by the
Clock Source Select bits, CS<1:0> (LCDCON<3:2>).
An additional programmable prescaler is used to derive
the LCD frame frequency from the 1 kHz baseline. The
prescaler is configured using the LP<3:0> bits
(LCDPS<3:0>) for any one of 16 options, ranging from
1:1 to 1:16.
Proper timing for waveform generation is set by the
LMUX<1:0> bits (LCDCON<1:0>). These bits
determine which Commons Multiplexing mode is to be
used, and divide down the LCD clock source as
required. They also determine the configuration of the
ring counter that is used to switch the LCD commons
on or off.
16.2.1 LCD VOLTAGE REGULATOR
CLOCK SOURCE
In addition to the clock source for LCD timing, a
separate 31 kHz nominal clock is required for the LCD
charge pump. This is provided from a distinct branch of
the LCD clock source.
The charge pump clock can use either the Timer1
oscillator or the INTRC source, as well as the 8 MHz
INTOSC source (after being divided by 256 by a
prescaler). The charge pump clock source is configured
using the CKSEL<1:0> bits (LCDREG<1:0>).
16.2.2 CLOCK SOURCE
CONSIDERATIONS
When using the system clock as the LCD clock source,
it is assumed that the system clock frequency is a nom-
inal 32 MHz (for a FOSC/4 frequency of 8 MHz).
Because the prescaler option for the FOSC/4 clock
selection is fixed at divide-by-8192, system clock
speeds that differ from 32 MHz will produce frame
frequencies and refresh rates different than discussed
in this chapter. The user will need to keep this in mind
when designing the display application.
The Timer1 and INTRC sources can be used as LCD
clock sources when the device is in Sleep mode. To
use the Timer1 oscillator, it is necessary to set the
T1OSCEN bit (T1CON<3>). Selecting either Timer1 or
INTRC as the LCD clock source will not automatically
activate these sources.
Similarly, selecting the INTOSC as the charge pump
clock source will not turn the oscillator on. To use
INTOSC, it must be selected as the system clock
source by using the FOSC2 Configuration bit.
If Timer1 is used as a clock source for the device, either
as an LCD clock source or for any other purpose, LCD
segment 32 become unavailable.
FIGURE 16-2: LCD CLOCK GENERATION
LCDCON<3:2>
Timer1 Oscillator
Internal 31 kHz Source
÷4
Programmable
÷1, 2, 3, 4
Ring Counter
COM0
COM1
COM2
COM3
÷2 ÷32
LCDCON<1:0>
LCDPS<3:0>
System Clock (FOSC/4)
INTOSC 8 MHz Source
1:1 to 1:16
Prescaler
1x
01
00
11
10
01
00
31 kHz Clock
11
10
01
LCDREG<1:0>
to LCD Charge Pump
÷8192
or
4
2
2
2
÷256
2010 Microchip Technology Inc. DS39770C-page 169
PIC18F85J90 FAMILY
16.3 LCD Bias Generation
The LCD driver module is capable of generating the
required bias voltages for LCD operation with a mini-
mum of external components. This includes the ability
to generate the different voltage levels required by the
different bias types required by the LCD. The driver
module can also provide bias voltages both above and
below microcontroller VDD through the use of an
on-chip LCD voltage regulator.
16.3.1 LCD BIAS TYPES
PIC18F85J90 family devices support three bias types
based on the waveforms generated to control
segments and commons:
• Static (two discrete levels)
• 1/2 Bias (three discrete levels
• 1/3 Bias (four discrete levels)
The use of different waveforms in driving the LCD is dis-
cussed in more detail in Section 16.8 “LCD Waveform
Generation”.
16.3.2 LCD VOLTAGE REGULATOR
The purpose of the LCD regulator is to provide proper
bias voltage and good contrast for the LCD, regardless
of VDD levels. This module contains a charge pump and
internal voltage reference. The regulator can be config-
ured by using external components to boost bias
voltage above VDD. It can also operate a display at a
constant voltage below VDD. The regulator can also be
selectively disabled to allow bias voltages to be
generated by an external resistor network.
The LCD regulator is controlled through the LCDREG
register (Register 16-5). It is enabled or disabled using
the CKSEL<1:0> bits, while the charge pump can be
selectively enabled using the CPEN bit. When the reg-
ulator is enabled, the MODE13 bit is used to select the
bias type. The peak LCD bias voltage, measured as a
difference between the potentials of LCDBIAS3 and
LCDBIAS0, is configured with the BIAS bits.
REGISTER 16-5: LCDREG: VOLTAGE REGULATOR CONTROL REGISTER
U-0 RW-0RW-1RW-1RW-1RW-1RW-0RW-0
— CPEN BIAS2 BIAS1 BIAS0 MODE13 CKSEL1 CKSEL0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 Unimplemented: Read as ‘0’
bit 6 CPEN: LCD Charge Pump Enable bit
1 = Charge pump enabled; highest LCD bias voltage is 3.6V
0 = Charge pump disabled; highest LCD bias voltage is AVDD
bit 5-3 BIAS<2:0>: Regulator Voltage Output Control bits
111 = 3.60V peak (offset on LCDBIAS0 of 0V)
110 = 3.47V peak (offset on LCDBIAS0 of 0.13V)
101 = 3.34V peak (offset on LCDBIAS0 of 0.26V)
100 = 3.21V peak (offset on LCDBIAS0 of 0.39V)
011 = 3.08V peak (offset on LCDBIAS0 of 0.52V)
010 = 2.95V peak (offset on LCDBIAS0 of 0.65V)
001 = 2.82V peak (offset on LCDBIAS0 of 0.78V)
000 = 2.69V peak (offset on LCDBIAS0 of 0.91V)
bit 2 MODE13: 1/3 LCD Bias Enable bit
1 = Regulator output supports 1/3 LCD Bias mode
0 = Regulator output supports static LCD Bias mode
bit 1-0 CKSEL<1:0>: Regulator Clock Source Select bits
11 = INTRC
10 = INTOSC 8 MHz source
01 = Timer1 oscillator
00 = LCD regulator disabled
PIC18F85J90 FAMILY
DS39770C-page 170 2010 Microchip Technology Inc.
16.3.3 BIAS CONFIGURATIONS
PIC18F85J90 family devices have four distinct circuit
configurations for LCD bias generation:
• M0: Regulator with Boost
• M1: Regulator without Boost
• M2: Resistor Ladder with Software Contrast
• M3: Resistor Ladder with Hardware Contrast
16.3.3.1 M0 (Regulator with Boost)
In M0 operation, the LCD charge pump feature is
enabled. This allows the regulator to generate voltages
up to +3.6V to the LCD (as measured at LCDBIAS3).
M0 uses a flyback capacitor connected between
VLCAP1 and VLCAP2, as well as filter capacitors on
LCDBIAS0 through LCDBIAS3, to obtain the required
voltage boost (Figure 16-3).
The output voltage (VBIAS) is the difference of potential
between LCDBIAS3 and LCDBIAS0. It is set by the
BIAS<2:0> bits which adjust the offset between
LCDBIAS0 and VSS. The flyback capacitor (CFLY) acts
as a charge storage element for large LCD loads. This
mode is useful in those cases where the voltage
requirements of the LCD are higher than the micro-
controller’s VDD. It also permits software control of the
display’s contrast by adjustment of bias voltage by
changing the value of the BIAS bits.
M0 supports Static and 1/3 Bias types. Generation of
the voltage levels for 1/3 Bias is handled automatically,
but must be configured in software.
M0 is enabled by selecting a valid regulator clock
source (CKSEL<1:0> set to any value except ‘00’) and
setting the CPEN bit. If static Bias type is required, the
MODE13 bit must be cleared.
16.3.3.2 M1 (Regulator without Boost)
M1 operation is similar to M0, but does not use the LCD
charge pump. It can provide VBIAS up to the voltage
level supplied directly to LCDBIAS3. It can be used in
cases where VDD for the application is expected to
never drop below a level that can provide adequate
contrast for the LCD. The connection of external com-
ponents is very similar to M0, except that LCDBIAS3
must be tied directly to VDD (Figure 16-3).
The BIAS<2:0> bits can still be used to adjust contrast
in software by changing VBIAS. As with M0, changing
these bits changes the offset between LCDBIAS0 and
VSS. In M1, this is reflected in the change between the
LCDBIAS0 and the voltage tied to LCDBIAS3. Thus, if
VDD should change, VBIAS will also change; where in
M0, the level of VBIAS is constant.
Like M0, M1 supports Static and 1/3 Bias types.
Generation of the voltage levels for 1/3 Bias is handled
automatically but must be configured in software.
M1 is enabled by selecting a valid regulator clock
source (CKSEL<1:0> set to any value except ‘00’) and
clearing the CPEN bit. If 1/3 Bias type is required, the
MODE13 bit should also be set.
FIGURE 16-3: LCD REGULATOR CONNECTIONS FOR M0 AND M1 CONFIGURATIONS
Note: When the device is put to Sleep while
operating in M0 or M1 mode, make sure
that the Bias capacitors are fully discharged
to get the lowest Sleep current.
LCDBIAS3
LCDBIAS2
LCDBIAS1
LCDBIAS0
AVDD
PIC18F85J90 VDD
VLCAP1
VLCAP2
CFLY
C0
C1
C2
C3
C0
C1
C2
VDD
VDD
(VBIAS up to 3.6V)
Mode 0
(VBIAS VDD)
Mode 1
CFLY
Note 1: These values are provided for design guidance only; they should be optimized for the application by the designer
based on the actual LCD specifications.
0.047 F(1)
0.047 F(1)
0.047 F(1)
0.047 F(1)
0.047 F(1)
0.047 F(1)
0.047 F(1)
0.047 F(1)
0.047 F(1)
2010 Microchip Technology Inc. DS39770C-page 171
PIC18F85J90 FAMILY
16.3.3.3 M2 (Resistor Ladder with
Software Contrast)
M2 operation also uses the LCD regulator but disables
the charge pump. The regulator’s internal voltage refer-
ence remains active as a way to regulate contrast. It is
used in cases where the current requirements of the
LCD exceed the capacity of the regulator’s charge
pump.
In this configuration, the LCD bias voltage levels are
created by an external resistor voltage divider
connected across LCDBIAS0 through LCDBIAS3, with
the top of the divider tied to VDD (Figure 16-4). The
potential at the bottom of the ladder is determined by
the LCD regulator’s voltage reference, tied internally to
LCDBIAS0. The bias type is determined by the volt-
ages on the LCDBIAS pins, which are controlled by the
configuration of the resistor ladder. Most applications
using M2 will use a 1/3 or 1/2 Bias type. While Static
Bias can also be used, it offers extremely limited
contrast range and additional current consumption
over other bias generation modes.
Like M1, the LCDBIAS bits can be used to control con-
trast, limited by the level of VDD supplied to the device.
Also, since there is no capacitor required across
VLCAP1 and VLCAP2, these pins are available as digital
I/O ports, RG2 and RG3.
M2 is selected by clearing the CKSEL<1:0> bits and
setting the CPEN bit.
FIGURE 16-4: RESISTOR LADDER CONNECTIONS FOR CONFIGURATION M2
LCDBIAS3
Note 1: These values are provided for design guidance only; they should be optimized for the application by the designer
based on the actual LCD specifications.
Bias Level at Pin
Bias Type
1/2 Bias 1/3 Bias
LCDBIAS0 (Internal low reference voltage) (Internal low reference voltage)
LCDBIAS1 1/2 VBIAS 1/3 VBIAS
LCDBIAS2 1/2 VBIAS 2/3 VBIAS
LCDBIAS3 VBIAS (up to AVDD)VBIAS (up to AVDD)
10 k(1)
10 k(1)
1/2 Bias 1/3 Bias
LCDBIAS2
LCDBIAS1
LCDBIAS0
AVDD
PIC18F85J90
10 k(1)
10 k(1)
10 k(1)
VDD
PIC18F85J90 FAMILY
DS39770C-page 172 2010 Microchip Technology Inc.
16.3.3.4 M3 (Hardware Contrast)
In M3, the LCD regulator is completely disabled. Like
M2, LCD bias levels are tied to AVDD, and are generated
using an external divider. The difference is that the inter-
nal voltage reference is also disabled and the bottom of
the ladder is tied to ground (VSS); see Figure 16-5. The
value of the resistors and the difference between VSS
and VDD determine the contrast range; no software
adjustment is possible. This configuration is also used
where the LCD’s current requirements exceed the
capacity of the charge pump, and software contrast
control is not needed.
Depending on the bias type required, resistors are
connected between some or all of the pins. A potentio-
meter can also be connected between LCDBIAS3 and
VDD to allow for hardware controlled contrast
adjustment.
M3 is selected by clearing the CKSEL<1:0> and CPEN
bits.
FIGURE 16-5: RESISTOR LADDER CONNECTIONS FOR CONFIGURATION M3
LCDBIAS3
Note 1: These values are provided for design guidance only; they should be optimized for the application by the
designer based on the actual LCD specifications.
2: Potentiometer for manual contrast adjustment is optional; it may be omitted entirely.
Bias Level at Pin
Bias Type
Static 1/2 Bias 1/3 Bias
LCDBIAS0 AVSS AVSS AVSS
LCDBIAS1 AVSS 1/2 AVDD 1/3 AVDD
LCDBIAS2 AVDD 1/2 AVDD 2/3 AVDD
LCDBIAS3 AVDD AVDD AVDD
10 k(1)
10 k(1)
Static Bias 1/2 Bias 1/3 Bias
LCDBIAS2
LCDBIAS1
LCDBIAS0
AVDD
PIC18F85J90
10 k(1)
10 k(1)
10 k(1)
VDD
(2)
2010 Microchip Technology Inc. DS39770C-page 173
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16.3.4 DESIGN CONSIDERATIONS FOR
THE LCD CHARGE PUMP
When designing applications that use the LCD regula-
tor with the charge pump enabled, users must always
consider both the dynamic current and RMS (static)
current requirements of the display, and what the
charge pump can deliver. Both dynamic and static
current can be determined by Equation 16-1:
EQUATION 16-1: STATIC AND DYNAMIC
CURRENT
For dynamic current, C is the value of the capacitors
attached to LCDBIAS3 and LCDBIAS2. The variable,
dV, is the voltage drop allowed on C2 and C3 during a
voltage switch on the LCD display, and dT is the dura-
tion of the transient current after a clock pulse occurs.
For practical design purposes, these will be assumed
to be 0.047 F for C, 0.1V for dV and 1 s for dT. This
yields a dynamic current of 4.7 mA for 1 s.
RMS current is determined by the value of CFLY for C,
the voltage across VLCAP1 and VLCAP2 for dV and the
regulator clock period (TPER) for dT. Assuming CFLY of
0.047 F, a value of 1.02V across CFLY and TPER of
30 s, the maximum theoretical static current will be
1.8 mA. Since the charge pump must charge five
capacitors, the maximum current becomes 360 A. For
a real-world assumption of 50% efficiency, this yields a
practical current of 180 A.
Users should compare the calculated current capacity
against the requirements of the LCD. While dV and dT
are relatively fixed by device design, the values of CFLY
and the capacitors on the LCDBIAS pins can be
changed to increase or decrease current. As always,
any changes should be evaluated in the actual circuit
for its impact on the application.
16.4 LCD Multiplex Types
The LCD driver module can be configured into four
multiplex types:
• Static (only COM0 used)
• 1/2 multiplex (COM0 and COM1 are used)
• 1/3 multiplex (COM0, COM1 and COM2 are used)
• 1/4 multiplex (all COM0, COM1, COM2 and COM3
are used)
The number of active commons used is configured by
the LMUX<1:0> bits (LCDCON<1:0>), which deter-
mines the function of the PORTE<6:4> pins (see
Table 16-3 for details). If the pin is configured as a COM
drive, the port I/O function is disabled and the TRIS
setting of that pin is overridden.
TABLE 16-3: PORTE<6:4> FUNCTION
16.5 Segment Enables
The LCDSEx registers are used to select the pin
function for each segment pin. Setting a bit configures
the corresponding pin to function as a segment driver.
LCDSEx registers do not override the TRIS bit settings,
so the TRIS bits must be configured as input for that
pin.
16.6 Pixel Control
The LCDDATAx registers contain bits which define the
state of each pixel. Each bit defines one unique pixel.
Table 16-2 shows the correlation of each bit in the
LCDDATAx registers to the respective common and
segment signals. Any LCD pixel location not being
used for display can be used as general purpose RAM.
I = C x dV
dT
Note: On a Power-on Reset, the LMUX<1:0>
bits are ‘00’.
LMUX<1:0> PORTE<6> PORTE<5> PORTE<4>
00 Digital I/O Digital I/O Digital I/O
01 Digital I/O Digital I/O COM1 Driver
10 Digital I/O COM2 Driver COM1 Driver
11 COM3 Driver COM2 Driver COM1 Driver
Note: On a Power-on Reset, these pins are
configured as digital I/O.
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DS39770C-page 174 2010 Microchip Technology Inc.
16.7 LCD Frame Frequency
The rate at which the COM and SEG outputs changes
is called the LCD frame frequency. Frame frequency is
set by the LP<3:0> bits (LCDPS<3:0>), and is also
affected by the Multiplex mode being used. The rela-
tionship between the Multiplex mode, LP bits setting
and frame rate is shown in Table 16-4 and Table 16-5.
TABLE 16-4: FRAME FREQUENCY
FORMULAS
TABLE 16-5: APPROXIMATE FRAME
FREQUENCY (IN Hz) FOR LP
PRESCALER SETTINGS
16.8 LCD Waveform Generation
LCD waveform generation is based on the principle
that the net AC voltage across the dark pixel should be
maximized and the net AC voltage across the clear
pixel should be minimized. The net DC voltage across
any pixel should be zero.
The COM signal represents the time slice for each
common, while the SEG contains the pixel data. The
pixel signal (COM-SEG) will have no DC component
and it can take only one of the two rms values. The
higher rms value will create a dark pixel and a lower
rms value will create a clear pixel.
As the number of commons increases, the delta
between the two rms values decreases. The delta
represents the maximum contrast that the display can
have.
The LCDs can be driven by two types of waveform:
Type-A and Type-B. In the Type-A waveform, the
phase changes within each common type, whereas in
the Type-B waveform, the phase changes on each
frame boundary. Thus, the Type-A waveform maintains
0 VDC over a single frame, whereas the Type-B
waveform takes two frames.
Figure 16-6 through Figure 16-16 provide waveforms
for static, half multiplex, one-third multiplex and quarter
multiplex drives for Type-A and Type-B waveforms.
Multiplex
Mode Frame Frequency (Hz)
Static Clock source/(4 x 1 x (LP3:LP0 + 1))
1/2 Clock source/(2 x 2 x (LP3:LP0 + 1))
1/3 Clock source/(1 x 3 x (LP3:LP0 + 1))
1/4 Clock source/(1 x 4 x (LP3:LP0 + 1))
LP<3:0>
Multiplex Mode
Static 1/2 1/3 1/4
1 125 125 167 125
2 83 83 111 83
3 62628362
4 50506750
5 42425642
6 36364836
7 31314231
Note 1: If the power-managed Sleep mode is
invoked while the LCD Sleep bit is set
(LCDCON<6> is ‘1’), take care to execute
Sleep only when the VDC on all the pixels
is ‘0’.
2: When the LCD clock source is the system
clock, the LCD module will go to Sleep if
the microcontroller goes into Sleep mode,
regardless of the setting of the SPLEN bit.
Thus, always take care to see that the VDC
on all pixels is ‘0’ whenever Sleep mode is
invoked.
2010 Microchip Technology Inc. DS39770C-page 175
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FIGURE 16-6: TYPE-A/TYPE-B WAVEFORMS IN STATIC DRIVE
V1
V0
COM0
SEG0
COM0-SEG0
COM0-SEG1
SEG1
V1
V0
V1
V0
V0
V1
-V1
V0
1 Frame
COM0
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
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DS39770C-page 176 2010 Microchip Technology Inc.
FIGURE 16-7: TYPE-A WAVEFORMS IN 1/2 MUX, 1/2 BIAS DRIVE
V2
V1
V0
V2
V1
V0
V2
V1
V0
V2
V1
V0
V2
V1
V0
-V2
-V1
V2
V1
V0
-V2
-V1
COM0
COM1
SEG0
SEG1
COM0-SEG0
COM0-SEG1
1 Frame
COM1
COM0
SEG0
SEG1
SEG2
SEG3
2010 Microchip Technology Inc. DS39770C-page 177
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FIGURE 16-8: TYPE-B WAVEFORMS IN 1/2 MUX, 1/2 BIAS DRIVE
V2
V1
V0
V2
V1
V0
V2
V1
V0
V2
V1
V0
V2
V1
V0
-V2
-V1
V2
V1
V0
-V2
-V1
COM0
COM1
SEG0
SEG1
COM0-SEG0
COM0-SEG1
COM1
COM0
SEG0
SEG1
SEG2
SEG3
2 Frames
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DS39770C-page 178 2010 Microchip Technology Inc.
FIGURE 16-9: TYPE-A WAVEFORMS IN 1/2 MUX, 1/3 BIAS DRIVE
V3
V2
V1
V0
V3
V2
V1
V0
V3
V2
V1
V0
V3
V2
V1
V0
V3
V2
V1
V0
-V3
-V2
-V1
V3
V2
V1
V0
-V3
-V2
-V1
COM0
COM1
SEG0
SEG1
COM0-SEG0
COM0-SEG1
1 Frame
COM1
COM0
SEG0
SEG1
SEG2
SEG3
2010 Microchip Technology Inc. DS39770C-page 179
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FIGURE 16-10: TYPE-B WAVEFORMS IN 1/2 MUX, 1/3 BIAS DRIVE
V3
V2
V1
V0
V3
V2
V1
V0
V3
V2
V1
V0
V3
V2
V1
V0
V3
V2
V1
V0
-V3
-V2
-V1
V3
V2
V1
V0
-V3
-V2
-V1
COM0
COM1
SEG0
SEG1
COM0-SEG0
COM0-SEG1
COM1
COM0
SEG0
SEG1
SEG2
SEG3
2 Frames
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DS39770C-page 180 2010 Microchip Technology Inc.
FIGURE 16-11: TYPE-A WAVEFORMS IN 1/3 MUX, 1/2 BIAS DRIVE
V2
V1
V0
V2
V1
V0
V2
V1
V0
V2
V1
V0
V2
V1
V0
V2
V1
V0
-V2
-V1
V2
V1
V0
-V2
-V1
COM0
COM1
COM2
SEG0
SEG1
COM0-SEG0
COM0-SEG1
1 Frame
COM2
COM1
COM0
SEG0
SEG1
SEG2
SEG2
2010 Microchip Technology Inc. DS39770C-page 181
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FIGURE 16-12: TYPE-B WAVEFORMS IN 1/3 MUX, 1/2 BIAS DRIVE
V2
V1
V0
V2
V1
V0
V2
V1
V0
V2
V1
V0
V2
V1
V0
V2
V1
V0
-V2
-V1
V2
V1
V0
-V2
-V1
COM0
COM1
COM2
SEG0
SEG1
COM0-SEG0
COM0-SEG1
2 Frames
COM2
COM1
COM0
SEG0
SEG1
SEG2
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DS39770C-page 182 2010 Microchip Technology Inc.
FIGURE 16-13: TYPE-A WAVEFORMS IN 1/3 MUX, 1/3 BIAS DRIVE
V3
V2
V1
V0
V3
V2
V1
V0
V3
V2
V1
V0
V3
V2
V1
V0
V3
V2
V1
V0
V3
V2
V1
V0
-V3
-V2
-V1
V3
V2
V1
V0
-V3
-V2
-V1
COM0
COM1
COM2
SEG0
SEG1
COM0-SEG0
COM0-SEG1
1 Frame
COM2
COM1
COM0
SEG0
SEG1
SEG2
SEG2
2010 Microchip Technology Inc. DS39770C-page 183
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FIGURE 16-14: TYPE-B WAVEFORMS IN 1/3 MUX, 1/3 BIAS DRIVE
V3
V2
V1
V0
V3
V2
V1
V0
V3
V2
V1
V0
V3
V2
V1
V0
V3
V2
V1
V0
V3
V2
V1
V0
-V3
-V2
-V1
V3
V2
V1
V0
-V3
-V2
-V1
COM0
COM1
COM2
SEG0
SEG1
COM0-SEG0
COM0-SEG1
2 Frames
COM2
COM1
COM0
SEG0
SEG1
SEG2
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DS39770C-page 184 2010 Microchip Technology Inc.
FIGURE 16-15: TYPE-A WAVEFORMS IN 1/4 MUX, 1/3 BIAS DRIVE
V3
V2
V1
V0
V3
V2
V1
V0
V3
V2
V1
V0
V3
V2
V1
V0
V3
V2
V1
V0
V3
V2
V1
V0
V3
V2
V1
V0
-V3
-V2
-V1
V3
V2
V1
V0
-V3
-V2
-V1
COM0
COM1
COM2
COM3
SEG0
SEG1
COM0-SEG0
COM0-SEG1
COM3
COM2
COM1
COM0
1 Frame
SEG0
SEG1
2010 Microchip Technology Inc. DS39770C-page 185
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FIGURE 16-16: TYPE-B WAVEFORMS IN 1/4 MUX, 1/3 BIAS DRIVE
V3
V2
V1
V0
V3
V2
V1
V0
V3
V2
V1
V0
V3
V2
V1
V0
V3
V2
V1
V0
V3
V2
V1
V0
V3
V2
V1
V0
-V3
-V2
-V1
V3
V2
V1
V0
-V3
-V2
-V1
COM0
COM1
COM2
COM3
SEG0
SEG1
COM0-SEG0
COM0-SEG1
COM3
COM2
COM1
COM0
2 Frames
SEG0
SEG1
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DS39770C-page 186 2010 Microchip Technology Inc.
16.9 LCD Interrupts
The LCD timing generation provides an interrupt that
defines the LCD frame timing. This interrupt can be
used to coordinate the writing of the pixel data with the
start of a new frame. Writing pixel data at the frame
boundary allows a visually crisp transition of the image.
This interrupt can also be used to synchronize external
events to the LCD. For example, the interface to an
external segment driver can be synchronized for
segment data update to the LCD frame.
A new frame is defined to begin at the leading edge of
the COM0 common signal. The interrupt will be set
immediately after the LCD controller completes
accessing all pixel data required for a frame. This will
occur at a fixed interval before the frame boundary
(TFINT), as shown in Figure 16-17. The LCD controller
will begin to access data for the next frame within the
interval from the interrupt to when the controller begins
to access data after the interrupt (TFWR). New data
must be written within TFWR, as this is when the LCD
controller will begin to access the data for the next
frame.
When the LCD driver is running with Type-B wave-
forms, and the LMUX<1:0> bits are not equal to ‘00’,
there are some additional issues that must be
addressed. Since the DC voltage on the pixel takes two
frames to maintain zero volts, the pixel data must not
change between subsequent frames. If the pixel data
were allowed to change, the waveform for the odd
frames would not necessarily be the complement of the
waveform generated in the even frames and a DC
component would be introduced into the panel. There-
fore, when using Type-B waveforms, the user must
synchronize the LCD pixel updates to occur within a
subframe after the frame interrupt.
To correctly sequence writing while in Type-B, the
interrupt will only occur on complete phase intervals. If
the user attempts to write when the write is disabled,
the WERR (LCDCON<5>) bit is set.
FIGURE 16-17: EXAMPLE WAVEFORMS AND INTERRUPT TIMING
IN QUARTER DUTY CYCLE DRIVE
Note: The interrupt is not generated when the
Type-A waveform is selected and when the
Type-B with no multiplex (static) is
selected.
Frame
Boundary
Frame
Boundary
LCD
Interrupt
Occurs
Controller Accesses
Next Frame Data
TFINT
TFWR
TFWR =TFRAME/2 * (LMUX<1:0> + 1) + TCY/2
TFINT =(TFWR/2 – (2 TCY + 40 ns)) Minimum = 1.5(TFRAME/4) – (2 TCY + 40 ns)
(TFWR/2 – (1 TCY + 40 ns)) Maximum = 1.5(TFRAME/4) – (1 TCY + 40 ns)
Frame
Boundary
V3
V2
V1
V0
V3
V2
V1
V0
V3
V2
V1
V0
V3
V2
V1
V0
COM0
COM1
COM2
COM3
2 Frames
2010 Microchip Technology Inc. DS39770C-page 187
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16.10 Operation During Sleep
The LCD module can operate during Sleep. The selec-
tion is controlled by the SLPEN bit (LCDCON<6>).
Setting the SLPEN bit allows the LCD module to go to
Sleep. Clearing the SLPEN bit allows the module to
continue to operate during Sleep.
If a SLEEP instruction is executed and SLPEN = 1, the
LCD module will cease all functions and go into a very
low-current consumption mode. The module will stop
operation immediately and drive the minimum LCD
voltage on both segment and common lines.
Figure 16-18 shows this operation.
To ensure that no DC component is introduced on the
panel, the SLEEP instruction should be executed imme-
diately after a LCD frame boundary. The LCD interrupt
can be used to determine the frame boundary. See
Section 16.9 “LCD Interrupts” for the formulas to
calculate the delay.
If a SLEEP instruction is executed and SLPEN = 0, the
module will continue to display the current contents of
the LCDDATA registers. To allow the module to
continue operation while in Sleep, the clock source
must be either the Timer1 oscillator or one of the
internal oscillators (either INTRC or INTOSC as the
default system clock). While in Sleep, the LCD data
cannot be changed. The LCD module current
consumption will not decrease in this mode; however,
the overall consumption of the device will be lower due
to shut down of the core and other peripheral functions.
If the system clock is selected and the module is not
configured for Sleep operation, the module will ignore
the SLPEN bit and stop operation immediately. The
minimum LCD voltage will then be driven onto the
segments and commons
16.10.1 USING THE LCD REGULATOR
DURING SLEEP
Applications that use the LCD regulator for bias
generation may not achieve the same degree of power
reductions in Sleep mode when compared to applica-
tions using Mode 3 (resistor ladder) biasing. This is
particularly true with Mode 0 operation, where the
charge pump is active.
If Modes 0, 1 or 2 are used for bias generation,
software contrast control will not be available.
FIGURE 16-18: SLEEP ENTRY/EXIT WHEN SLPEN = 1 OR CS<1:0> = 00
SLEEP Instruction Execution Wake-up
2 Frames
V3
V2
V1
V0
V3
V2
V1
V0
V3
V2
V1
V0
V3
V2
V1
V0
COM0
COM1
COM2
SEG0
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16.11 Configuring the LCD Module
The following is the sequence of steps to configure the
LCD module.
1. Select the frame clock prescale using bits,
LP<3:0> (LCDPS<3:0>).
2. Configure the appropriate pins to function as
segment drivers using the LCDSEx registers.
3. Configure the appropriate pins as inputs using
the TRISx registers.
4. Configure the LCD module for the following
using the LCDCON register:
• Multiplex and Bias mode (LMUX<1:0>)
• Timing source (CS<1:0>)
• Sleep mode (SLPEN)
5. Write initial values to Pixel Data registers,
LCDDATA0 through LCDDATA23.
6. Configure the LCD Regulator:
a) If M2 or M3 bias configuration is to be used,
turn off the regulator by setting
CKSEL<1:0> (LCDREG<1:0>) to ‘00’. Set
or clear the CPEN bit (LCDREG<6>) to
select Mode 2 or Mode 3, as appropriate.
b) If M0 or M1 bias generation is to be used:
•Set the V
BIAS level using the BIAS<2:0>
bits (LCDREG<5:3>).
• Set or clear the CPEN bit to enable or
disable the charge pump.
• Set or clear the MODE13 bit
(LCDREG<2>) to select the Bias mode.
• Select a regulator clock source using the
CKSEL<1:0> bits.
7. Clear the LCD Interrupt Flag, LCDIF (PIR3<6>),
and if desired, enable the interrupt by setting the
LCDIE bit (PIE3<6>).
8. Enable the LCD module by setting the LCDEN
bit (LCDCON<7>).
2010 Microchip Technology Inc. DS39770C-page 189
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TABLE 16-6: REGISTERS ASSOCIATED WITH LCD OPERATION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on Page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 57
PIR3 —LCDIFRC2IF TX2IF —CCP2IF CCP1IF —60
PIE3 — LCDIE RC2IE TX2IE —CCP2IE CCP1IE —60
IPR3 — LCDIP RC2IP TX2IP —CCP2IP CCP1IP —60
RCON IPEN —CM RI TO PD POR BOR 58
LCDDATA23(1) S47C3 S46C3 S45C3 S44C3 S43C3 S42C3 S41C3 S40C3 61
LCDDATA22 S39C3(1) S38C3(1) S37C3(1) S36C3(1) S35C3(1) S34C3(1) S33C3(1) S32C3 61
LCDDATA21 S31C3 S30C3 S29C3 S28C3 S27C3 S26C3 S25C3 S24C3 61
LCDDATA20 S23C3 S22C3 S21C3 S20C3 S19C3 S18C3 S17C3 S16C3 61
LCDDATA19 S15C3 S14C3 S13C3 S12C3 S11C3 S10C3 S09C3 S08C3 61
LCDDATA18 S07C3 S06C3 S05C3 S04C3 S03C3 S02C3 S01C3 S00C3 61
LCDDATA17(1) S47C2 S46C2 S45C2 S44C2 S43C2 S42C2 S41C2 S40C2 61
LCDDATA16 S39C2(1) S38C2(1) S37C2(1) S36C2(1) S35C2(1) S34C2(1) S33C2(1) S32C2 61
LCDDATA15 S31C2 S30C2 S29C2 S28C2 S27C2 S26C2 S25C2 S24C2 61
LCDDATA14 S23C2 S22C2 S21C2 S20C2 S19C2 S18C2 S17C2 S16C2 61
LCDDATA13 S15C2 S14C2 S13C2 S12C2 S11C2 S10C2 S09C2 S08C2 61
LCDDATA12 S07C2 S06C2 S05C2 S04C2 S03C2 S02C2 S01C2 S00C2 61
LCDDATA11(1) S47C1 S46C1 S45C1 S44C1 S43C1 S42C1 S41C1 S40C1 61
LCDDATA10 S39C1(1) S38C1(1) S37C1(1) S36C1(1) S35C1(1) S34C1(1) S33C1(1) S32C1 61
LCDDATA9 S31C1 S30C1 S29C1 S28C1 S27C1 S26C1 S25C1 S24C1 61
LCDDATA8 S23C1 S22C1 S21C1 S20C1 S19C1 S18C1 S17C1 S16C1 61
LCDDATA7 S15C1 S14C1 S13C1 S12C1 S11C1 S10C1 S09C1 S08C1 61
LCDDATA6 S07C1 S06C1 S05C1 S04C1 S03C1 S02C1 S01C1 S00C1 61
LCDDATA5(1) S47C0 S46C0 S45C0 S44C0 S43C0 S42C0 S41C0 S40C0 61
LCDDATA4 S39C0(1) S38C0(1) S37C0(1) S36C0(1) S35C0(1) S34C0(1) S33C0(1) S32C0 59
LCDDATA3 S31C0 S30C0 S29C0 S28C0 S27C0 S26C0 S25C0 S24C0 59
LCDDATA2 S23C0 S22C0 S21C0 S20C0 S19C0 S18C0 S17C0 S16C0 59
LCDDATA1 S15C0 S14C0 S13C0 S12C0 S11C0 S10C0 S09C0 S08C0 59
LCDDATA0 S07C0 S06C0 S05C0 S04C0 S03C0 S02C0 S01C0 S00C0 59
LCDSE5(1) SE47 SE46 SE45 SE44 SE43 SE42 SE41 SE40 59
LCDSE4 SE39(1) SE38(1) SE37(1) SE36(1) SE35(1) SE34(1) SE33(1) SE32 59
LCDSE3 SE31 SE30 SE29 SE28 SE27 SE26 SE25 SE24 59
LCDSE2 SE23 SE22 SE21 SE20 SE19 SE18 SE17 SE16 59
LCDSE1 SE15 SE14 SE13 SE12 SE11 SE10 SE09 SE08 59
LCDSE0 SE07 SE06 SE05 SE04 SE03 SE02 SE01 SE00 59
LCDCON LCDEN SLPEN WERR — CS1 CS0 LMUX1 LMUX0 59
LCDPS WFT BIASMD LCDA WA LP3 LP2 LP1 LP0 59
LCDREG — CPEN BIAS2 BIAS1 BIAS0 MODE13 CKSEL1 CKSEL0
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for LCD operation.
Note 1: These registers or individual bits are unimplemented on 64-pin devices.
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NOTES:
2010 Microchip Technology Inc. DS39770C-page 191
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17.0 MASTER SYNCHRONOUS
SERIAL PORT (MSSP)
MODULE
17.1 Master SSP (MSSP) Module
Overview
The Master Synchronous Serial Port (MSSP) module is
a serial interface, useful for communicating with other
peripheral or microcontroller devices. These peripheral
devices may be serial EEPROMs, shift registers,
display drivers, A/D Converters, etc. The MSSP
module can operate in one of two modes:
• Serial Peripheral Interface (SPI)
• Inter-Integrated Circuit (I2C™)
- Full Master mode
- Slave mode (with general address call)
The I2C interface supports the following modes in
hardware:
•Master mode
• Multi-Master mode
• Slave mode
17.2 Control Registers
Each MSSP module has three associated control
registers. These include a status register (SSPSTAT)
and two control registers (SSPCON1 and SSPCON2).
The use of these registers and their individual bits differ
significantly depending on whether the MSSP module
is operated in SPI or I2C mode.
Additional details are provided under the individual
sections.
17.3 SPI Mode
The SPI mode allows 8 bits of data to be synchronously
transmitted and received simultaneously. All four
modes of SPI are supported. To accomplish
communication, typically three pins are used:
• Serial Data Out (SDO) – RC5/SDO
• Serial Data In (SDI) – RC4/SDI/SDA
• Serial Clock (SCK) – RC3/SCK/SCL
Additionally, a fourth pin may be used when in a Slave
mode of operation:
• Slave Select (SS) – RF7/SS
Figure 17-1 shows the block diagram of the MSSP
module when operating in SPI mode.
FIGURE 17-1: MSSP BLOCK DIAGRAM
(SPI MODE)
Note: Disabling the MSSP module by clearing
the SSPEN (SSPCON1<5>) bit may not
reset the module. It is recommended to
clear the SSPSTAT, SSPCON1 and
SSPCON2 registers and select the mode
prior to setting the SSPEN bit to enable
the MSSP module.
Note: Disabling the MSSP module by clearing
the SSPEN (SSPCON1<5>) bit may not
reset the module. It is recommended to
clear the SSPSTAT, SSPCON1 and
SSPCON2 registers and select the mode
prior to setting the SSPEN bit to enable
the MSSP module.
( )
Read Write
Internal
Data Bus
SSPSR reg
SSPM<3:0>
bit 0 Shift
Clock
SS Control
Enable
Edge
Select
Clock Select
TMR2 Output
TOSC
Prescaler
4, 16, 64
2
Edge
Select
2
4
Data to TXx/RXx in SSPSR
TRIS bit
2
SMP:CKE
SDO
SSPBUF reg
SDI
SS
SCK
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DS39770C-page 192 2010 Microchip Technology Inc.
17.3.1 REGISTERS
Each MSSP module has four registers for SPI mode
operation. These are:
• MSSP Control Register 1 (SSPCON1)
• MSSP Status Register (SSPSTAT)
• MSSP Serial Receive/Transmit Buffer Register
(SSPBUF)
• MSSP Shift Register (SSPSR) – Not directly
accessible
SSPCON1 and SSPSTAT are the control and status
registers in SPI mode operation. The SSPCON1
register is readable and writable. The lower 6 bits of
the SSPSTAT are read-only. The upper two bits of the
SSPSTAT are read/write.
SSPSR is the shift register used for shifting data in or
out. SSPBUF is the buffer register to which data bytes
are written to or read from.
In receive operations, SSPSR and SSPBUF together
create a double-buffered receiver. When SSPSR
receives a complete byte, it is transferred to SSPBUF
and the SSPIF interrupt is set.
During transmission, the SSPBUF is not
double-buffered. A write to SSPBUF will write to both
SSPBUF and SSPSR.
REGISTER 17-1: SSPSTAT: MSSP STATUS REGISTER (SPI MODE)
R/W-0 R/W-0 R-0 R-0 R-0 R-0 R0 R-0
SMP CKE(1) D/A PSR/WUA BF
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 SMP: Sample bit
SPI Master mode:
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time
SPI Slave mode:
SMP must be cleared when SPI is used in Slave mode.
bit 6 CKE: SPI Clock Select bit(1)
1 = Transmit occurs on transition from active to Idle clock state
0 = Transmit occurs on transition from Idle to active clock state
bit 5 D/A: Data/Address bit
Used in I2C™ mode only.
bit 4 P: Stop bit
Used in I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.
bit 3 S: Start bit
Used in I2C mode only.
bit 2 R/W: Read/Write Information bit
Used in I2C mode only.
bit 1 UA: Update Address bit
Used in I2C mode only.
bit 0 BF: Buffer Full Status bit (Receive mode only)
1 = Receive complete, SSPBUF is full
0 = Receive not complete, SSPBUF is empty
Note 1: Polarity of clock state is set by the CKP bit (SSPCON1<4>).
2010 Microchip Technology Inc. DS39770C-page 193
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REGISTER 17-2: SSPCON1: MSSP CONTROL REGISTER 1 (SPI MODE)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
WCOL SSPOV(1) SSPEN(2) CKP SSPM3(3) SSPM2(3) SSPM1(3) SSPM0(3)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 WCOL: Write Collision Detect bit (Transmit mode only)
1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in
software)
0 = No collision
bit 6 SSPOV: Receive Overflow Indicator bit(1)
SPI Slave mode:
1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of over-
flow, the data in SSPSR is lost. Overflow can only occur in Slave mode. The user must read the
SSPBUF, even if only transmitting data, to avoid setting overflow (must be cleared in software).
0 = No overflow
bit 5 SSPEN: Master Synchronous Serial Port Enable bit(2)
1 = Enables serial port and configures SCK, SDO, SDI and SS as serial port pins
0 = Disables serial port and configures these pins as I/O port pins
bit 4 CKP: Clock Polarity Select bit
1 = Idle state for clock is a high level
0 = Idle state for clock is a low level
bit 3-0 SSPM<3:0>: Master Synchronous Serial Port Mode Select bits(3)
0101 = SPI Slave mode, clock = SCK pin, SS pin control disabled, SS can be used as I/O pin
0100 = SPI Slave mode, clock = SCK pin, SS pin control enabled
0011 = SPI Master mode, clock = TMR2 output/2
0010 = SPI Master mode, clock = FOSC/64
0001 = SPI Master mode, clock = FOSC/16
0000 = SPI Master mode, clock = FOSC/4
Note 1: In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by
writing to the SSPBUF register.
2: When enabled, these pins must be properly configured as input or output.
3: Bit combinations not specifically listed here are either reserved or implemented in I2C™ mode only.
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DS39770C-page 194 2010 Microchip Technology Inc.
17.3.2 OPERATION
When initializing the SPI, several options need to be
specified. This is done by programming the appropriate
control bits (SSPCON1<5:0> and SSPSTAT<7:6>).
These control bits allow the following to be specified:
• Master mode (SCK is the clock output)
• Slave mode (SCK is the clock input)
• Clock Polarity (Idle state of SCK)
• Data Input Sample Phase (middle or end of data
output time)
• Clock Edge (output data on rising/falling edge of
SCK)
• Clock Rate (Master mode only)
• Slave Select mode (Slave mode only)
Each MSSP consists of a transmit/receive shift register
(SSPSR) and a buffer register (SSPBUF). The SSPSR
shifts the data in and out of the device, MSb first. The
SSPBUF holds the data that was written to the SSPSR
until the received data is ready. Once the 8 bits of data
have been received, that byte is moved to the SSPBUF
register. Then, the Buffer Full detect bit, BF
(SSPSTAT<0>), and the MSSP Interrupt Flag bit, SSPIF,
are set. This double-buffering of the received data
(SSPBUF) allows the next byte to start reception before
reading the data that was just received. Any write to the
SSPBUF register during transmission/reception of data
will be ignored and the Write Collision detect bit, WCOL
(SSPCON1<7>), will be set. User software must clear
the WCOL bit so that it can be determined if the following
write(s) to the SSPBUF register completed successfully.
When the application software is expecting to receive
valid data, the SSPBUF should be read before the next
byte of data to transfer is written to the SSPBUF. The
Buffer Full bit, BF (SSPSTAT<0>), indicates when
SSPBUF has been loaded with the received data (trans-
mission is complete). When the SSPBUF is read, the BF
bit is cleared. This data may be irrelevant if the SPI is
only a transmitter. Generally, the MSSP interrupt is used
to determine when the transmission/reception has com-
pleted. The SSPBUF must be read and/or written. If the
interrupt method is not going to be used, then software
polling can be done to ensure that a write collision does
not occur. Example 17-1 shows the loading of the
SSPBUF (SSPSR) for data transmission.
The SSPSR is not directly readable or writable and can
only be accessed by addressing the SSPBUF register.
Additionally, the SSPSTAT register indicates the
various status conditions.
EXAMPLE 17-1: LOADING THE SSPBUF (SSPSR) REGISTER
Note: To avoid lost data in Master mode, a read of
the SSPBUF must be performed to clear the
Buffer Full (BF) detect bit (SSPSTAT<0>)
between each transmission.
LOOP BTFSS SSPSTAT, BF ;Has data been received (transmit complete)?
BRA LOOP ;No
MOVF SSPBUF, W ;WREG reg = contents of SSPBUF
MOVWF RXDATA ;Save in user RAM, if data is meaningful
MOVF TXDATA, W ;W reg = contents of TXDATA
MOVWF SSPBUF ;New data to xmit
2010 Microchip Technology Inc. DS39770C-page 195
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17.3.3 ENABLING SPI I/O
To enable the serial port, MSSP Enable bit, SSPEN
(SSPCON1<5>), must be set. To reset or reconfigure
SPI mode, clear the SSPEN bit, reinitialize the
SSPCON registers and then set the SSPEN bit. This
configures the SDI, SDO, SCK and SS pins as serial
port pins. For the pins to behave as the serial port func-
tion, some must have their data direction bits (in the
TRIS register) appropriately programmed as follows:
• SDI is automatically controlled by the SPI module
• SDO must have TRISC<5> bit cleared
• SCK (Master mode) must have TRISC<3> bit
cleared
• SCK (Slave mode) must have TRISC<3> bit set
•SS
must have TRISF<7> bit set
Any serial port function that is not desired may be
overridden by programming the corresponding data
direction (TRIS) register to the opposite value.
17.3.4 OPEN-DRAIN OUTPUT OPTION
The drivers for the SDO output and SCK clock pins can
be optionally configured as open-drain outputs. This
feature allows the voltage level on the pin to be pulled
to a higher level through an external pull-up resistor,
and allows the output to communicate with external
circuits without the need for additional level shifters.
The open-drain output option is controlled by the
SPIOD bit (TRISG<7>). Setting the bit configures both
pins for open-drain operation.
17.3.5 TYPICAL CONNECTION
Figure 17-2 shows a typical connection between two
microcontrollers. The master controller (Processor 1)
initiates the data transfer by sending the SCK signal.
Data is shifted out of both shift registers on their pro-
grammed clock edge and latched on the opposite edge
of the clock. Both processors should be programmed to
the same Clock Polarity (CKP), then both controllers
would send and receive data at the same time.
Whether the data is meaningful (or dummy data)
depends on the application software. This leads to
three scenarios for data transmission:
• Master sends data–Slave sends dummy data
• Master sends data–Slave sends data
• Master sends dummy data–Slave sends data
FIGURE 17-2: SPI MASTER/SLAVE CONNECTION
Serial Input Buffer
(SSPBUF)
Shift Register
(SSPSR)
MSb LSb
SDO
SDI
PROCESSOR 1
SCK
SPI Master SSPM<3:0> = 00xx
Serial Input Buffer
(SSPBUF)
Shift Register
(SSPSR)
LSb
MSb
SDI
SDO
PROCESSOR 2
SCK
SPI Slave SSPM<3:0> = 010x
Serial Clock
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DS39770C-page 196 2010 Microchip Technology Inc.
17.3.6 MASTER MODE
The master can initiate the data transfer at any time
because it controls the SCK. The master determines
when the slave (Processor 2, Figure 17-2) will
broadcast data by the software protocol.
In Master mode, the data is transmitted/received as
soon as the SSPBUF register is written to. If the SPI is
only going to receive, the SDO output could be dis-
abled (programmed as an input). The SSPSR register
will continue to shift in the signal present on the SDI pin
at the programmed clock rate. As each byte is
received, it will be loaded into the SSPBUF register as
if a normal received byte (interrupts and status bits
appropriately set). This could be useful in receiver
applications as a “Line Activity Monitor” mode.
The clock polarity is selected by appropriately
programming the CKP bit (SSPCON1<4>). This, then,
would give waveforms for SPI communication as
shown in Figure 17-3, Figure 17-5 and Figure 17-6,
where the MSB is transmitted first. In Master mode, the
SPI clock rate (bit rate) is user-programmable to be one
of the following:
•F
OSC/4 (or TCY)
•FOSC/16 (or 4 • TCY)
•F
OSC/64 (or 16 • TCY)
• Timer2 output/2
This allows a maximum data rate (at 40 MHz) of
10.00 Mbps.
Figure 17-3 shows the waveforms for Master mode.
When the CKE bit is set, the SDO data is valid before
there is a clock edge on SCK. The change of the input
sample is shown based on the state of the SMP bit. The
time when the SSPBUF is loaded with the received
data is shown.
FIGURE 17-3: SPI MODE WAVEFORM (MASTER MODE)
SCK
(CKP = 0
SCK
(CKP = 1
SCK
(CKP = 0
SCK
(CKP = 1
4 Clock
Modes
Input
Sample
Input
Sample
SDI
bit 7 bit 0
SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
bit 7
SDI
SSPIF
(SMP = 1)
(SMP = 0)
(SMP = 1)
CKE = 1)
CKE = 0)
CKE = 1)
CKE = 0)
(SMP = 0)
Write to
SSPBUF
SSPSR to
SSPBUF
SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
(CKE = 0)
(CKE = 1)
Next Q4 Cycle
after Q2
bit 0
2010 Microchip Technology Inc. DS39770C-page 197
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17.3.7 SLAVE MODE
In Slave mode, the data is transmitted and received as
the external clock pulses appear on SCK. When the
last bit is latched, the SSPIF interrupt flag bit is set.
Before enabling the module in SPI Slave mode, the
clock line must match the proper Idle state. The clock
line can be observed by reading the SCK pin. The Idle
state is determined by the CKP bit (SSPCON1<4>).
While in Slave mode, the external clock is supplied by
the external clock source on the SCK pin. This external
clock must meet the minimum high and low times as
specified in the electrical specifications.
While in Sleep mode, the slave can transmit/receive
data. When a byte is received, the device will wake-up
from Sleep.
17.3.8 SLAVE SELECT
SYNCHRONIZATION
The SS pin allows a Synchronous Slave mode. The SPI
must be in Slave mode with SS pin control enabled
(SSPCON1<3:0> = 04h). When the SS pin is low, trans-
mission and reception are enabled and the SDO pin is
driven. When the SS pin goes high, the SDO pin is no
longer driven, even if in the middle of a transmitted byte
and becomes a floating output. External
pull-up/pull-down resistors may be desirable depending
on the application.
When the SPI module resets, the bit counter is forced
to ‘0’. This can be done by either forcing the SS pin to
a high level or clearing the SSPEN bit.
To emulate two-wire communication, the SDO pin can
be connected to the SDI pin. When the SPI needs to
operate as a receiver, the SDO pin can be configured
as an input. This disables transmissions from the SDO.
The SDI can always be left as an input (SDI function)
since it cannot create a bus conflict.
FIGURE 17-4: SLAVE SYNCHRONIZATION WAVEFORM
Note 1: When the SPI is in Slave mode with SS pin
control enabled (SSPCON1<3:0> = 0100),
the SPI module will reset if the SS pin is set
to VDD.
2: If the SPI is used in Slave mode with CKE
set, then the SS pin control must be
enabled.
SCK
(CKP = 1
SCK
(CKP = 0
Input
Sample
SDI
bit 7
SDO bit 7 bit 6 bit 7
SSPIF
Interrupt
(SMP = 0)
CKE = 0)
CKE = 0)
(SMP = 0)
Write to
SSPBUF
SSPSR to
SSPBUF
SS
Flag
bit 0
bit 7
bit 0
Next Q4 Cycle
after Q2
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DS39770C-page 198 2010 Microchip Technology Inc.
FIGURE 17-5: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0)
FIGURE 17-6: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1)
SCK
(CKP = 1
SCK
(CKP = 0
Input
Sample
SDI
bit 7
SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
SSPIF
Interrupt
(SMP = 0)
CKE = 0)
CKE = 0)
(SMP = 0)
Write to
SSPBUF
SSPSR to
SSPBUF
SS
Flag
Optional
Next Q4 Cycle
after Q2
bit 0
SCK
(CKP = 1
SCK
(CKP = 0
Input
Sample
SDI
bit 7 bit 0
SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
SSPIF
Interrupt
(SMP = 0)
CKE = 1)
CKE = 1)
(SMP = 0)
Write to
SSPBUF
SSPSR to
SSPBUF
SS
Flag
Not Optional
Next Q4 Cycle
after Q2
2010 Microchip Technology Inc. DS39770C-page 199
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17.3.9 OPERATION IN POWER-MANAGED
MODES
In SPI Master mode, module clocks may be operating
at a different speed than when in Full-Power mode; in
the case of Sleep mode, all clocks are halted.
In Idle modes, a clock is provided to the peripherals.
That clock should be from the primary clock source, the
secondary clock (Timer1 oscillator at 32.768 kHz) or
the INTRC source. See Section 3.3 “Clock Sources
and Oscillator Switching” for additional information.
In most cases, the speed that the master clocks SPI
data is not important; however, this should be
evaluated for each system.
If MSSP interrupts are enabled, they can wake the con-
troller from Sleep mode, or one of the Idle modes, when
the master completes sending data. If an exit from
Sleep or Idle mode is not desired, MSSP interrupts
should be disabled.
If the Sleep mode is selected, all module clocks are
halted and the transmission/reception will remain in
that state until the devices wakes. After the device
returns to Run mode, the module will resume
transmitting and receiving data.
In SPI Slave mode, the SPI Transmit/Receive Shift
register operates asynchronously to the device. This
allows the device to be placed in any power-managed
mode and data to be shifted into the SPI
Transmit/Receive Shift register. When all 8 bits have
been received, the MSSP interrupt flag bit will be set
and if enabled, will wake the device.
17.3.10 EFFECTS OF A RESET
A Reset disables the MSSP module and terminates the
current transfer.
17.3.11 BUS MODE COMPATIBILITY
Table 17-1 shows the compatibility between the
standard SPI modes and the states of the CKP and
CKE control bits.
TABLE 17-1: SPI BUS MODES
There is also an SMP bit which controls when the data
is sampled.
TABLE 17-2: REGISTERS ASSOCIATED WITH SPI OPERATION
Standard SPI Mode
Terminology
Control Bits State
CKP CKE
0, 0 0 1
0, 1 0 0
1, 0 1 1
1, 1 1 0
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 57
PIR1 —ADIF RC1IF TX1IF SSPIF —TMR2IF TMR1IF 60
PIE1 —ADIE RC1IE TX1IE SSPIE —TMR2IE TMR1IE 60
IPR1 —ADIP RC1IP TX1IP SSPIP —TMR2IP TMR1IP 60
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 60
TRISF TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 —60
TRISG SPIOD CCP2OD CCP1OD TRISG4 TRISG3 TRISG2 TRISG1 TRISG0 60
SSPBUF MSSP Receive Buffer/Transmit Register 58
SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 58
SSPSTAT SMP CKE D/A P S R/W UA BF 58
Legend: Shaded cells are not used by the MSSP module in SPI mode.
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17.4 I2C Mode
The MSSP module in I2C mode fully implements all
master and slave functions (including general call
support) and provides interrupts on Start and Stop bits
in hardware to determine a free bus (multi-master
function). The MSSP module implements the standard
mode specifications as well as 7-bit and 10-bit
addressing.
Two pins are used for data transfer:
• Serial clock (SCL) – RC3/SCK/SCL
• Serial data (SDA) – RC4/SDI/SDA
The user must configure these pins as inputs by setting
the TRISC<4:3> bits.
FIGURE 17-7: MSSP BLOCK DIAGRAM
(I2C™ MODE)
17.4.1 REGISTERS
The MSSP module has six registers for I2C operation.
These are:
• MSSP Control Register 1 (SSPCON1)
• MSSP Control Register 2 (SSPCON2)
• MSSP Status Register (SSPSTAT)
• MSSP Serial Receive/Transmit Buffer Register
(SSPBUF)
• MSSP Shift Register (SSPSR) – Not directly
accessible
• MSSP Address Register (SSPADD)
SSPCON1, SSPCON2 and SSPSTAT are the control
and status registers in I2C mode operation. The
SSPCON1 and SSPCON2 registers are readable and
writable. The lower 6 bits of the SSPSTAT are
read-only. The upper two bits of the SSPSTAT are
read/write.
Many of the bits in SSPCON2 assume different
functions, depending on whether the module is operat-
ing in Master or Slave mode; bits<5:2> also assume
different names in Slave mode. The different aspects of
SSPCON2 are shown in Register 17-5 (for Master
mode) and Register 17-6 (Slave mode).
SSPSR is the shift register used for shifting data in or
out. SSPBUF is the buffer register to which data bytes
are written to or read from.
SSPADD register holds the slave device address when
the MSSP is configured in I2C Slave mode. When the
MSSP is configured in Master mode, the lower seven
bits of SSPADD act as the Baud Rate Generator reload
value.
In receive operations, SSPSR and SSPBUF together
create a double-buffered receiver. When SSPSR
receives a complete byte, it is transferred to SSPBUF
and the SSPIF interrupt is set.
During transmission, the SSPBUF is not
double-buffered. A write to SSPBUF will write to both
SSPBUF and SSPSR.
Note: Disabling the MSSP module by clearing
the SSPEN (SSPCON1<5>) bit may not
reset the module. It is recommended to
clear the SSPSTAT, SSPCON1 and
SSPCON2 registers and select the mode
prior to setting the SSPEN bit to enable
the MSSP module.
Read Write
SSPSR reg
Match Detect
SSPADD reg
Start and
Stop bit Detect
SSPBUF reg
Internal
Data Bus
Addr Match
Set, Reset
S, P bits
(SSPSTAT reg)
Shift
Clock
MSb LSb
SCL
SDA
Address Mask
2010 Microchip Technology Inc. DS39770C-page 201
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REGISTER 17-3: SSPSTAT: MSSP STATUS REGISTER (I2C™ MODE)
R/W-0 R/W-0 R-0 R-0 R-0 R-0 R0 R-0
SMP CKE D/A P(1) S(1) R/W UA BF
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 SMP: Slew Rate Control bit
In Master or Slave mode:
1 = Slew rate control disabled for Standard Speed mode (100 kHz and 1 MHz)
0 = Slew rate control enabled for High-Speed mode (400 kHz)
bit 6 CKE: SMBus Select bit
In Master or Slave mode:
1 = Enable SMBus specific inputs
0 = Disable SMBus specific inputs
bit 5 D/A: Data/Address bit
In Master mode:
Reserved.
In Slave mode:
1 = Indicates that the last byte received or transmitted was data
0 = Indicates that the last byte received or transmitted was address
bit 4 P: Stop bit(1)
1 = Indicates that a Stop bit has been detected last
0 = Stop bit was not detected last
bit 3 S: Start bit(1)
1 = Indicates that a Start bit has been detected last
0 = Start bit was not detected last
bit 2 R/W: Read/Write Information bit (I2C mode only)
In Slave mode:(2)
1 = Read
0 = Write
In Master mode:(3)
1 = Transmit is in progress
0 = Transmit is not in progress
bit 1 UA: Update Address bit (10-Bit Slave mode only)
1 = Indicates that the user needs to update the address in the SSPADD register
0 = Address does not need to be updated
bit 0 BF: Buffer Full Status bit
In Transmit mode:
1 = SSPBUF is full
0 = SSPBUF is empty
In Receive mode:
1 = SSPBUF is full (does not include the ACK and Stop bits)
0 = SSPBUF is empty (does not include the ACK and Stop bits)
Note 1: This bit is cleared on Reset and when SSPEN is cleared.
2: This bit holds the R/W bit information following the last address match. This bit is only valid from the
address match to the next Start bit, Stop bit or not ACK bit.
3: ORing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in Active mode.
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DS39770C-page 202 2010 Microchip Technology Inc.
REGISTER 17-4: SSPCON1: MSSP CONTROL REGISTER 1 (I2C™ MODE)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
WCOL SSPOV SSPEN(1) CKP SSPM3 SSPM2 SSPM1 SSPM0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 WCOL: Write Collision Detect bit
In Master Transmit mode:
1 = A write to the SSPBUF register was attempted while the I2C conditions were not valid for a
transmission to be started (must be cleared in software)
0 = No collision
In Slave Transmit mode:
1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in
software)
0 = No collision
In Receive mode (Master or Slave modes):
This is a “don’t care” bit.
bit 6 SSPOV: Receive Overflow Indicator bit
In Receive mode:
1 = A byte is received while the SSPBUF register is still holding the previous byte (must be cleared in
software)
0 = No overflow
In Transmit mode:
This is a “don’t care” bit in Transmit mode.
bit 5 SSPEN: Master Synchronous Serial Port Enable bit(1)
1 = Enables the serial port and configures the SDA and SCL pins as the serial port pins
0 = Disables serial port and configures these pins as I/O port pins
bit 4 CKP: SCK Release Control bit
In Slave mode:
1 = Release clock
0 = Holds clock low (clock stretch), used to ensure data setup time
In Master mode:
Unused in this mode.
bit 3-0 SSPM<3:0>: Synchronous Serial Port Mode Select bits
1111 = I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled
1110 = I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled
1011 = I2C Firmware Controlled Master mode (slave Idle)
1000 = I2C Master mode, clock = FOSC/(4 * (SSPADD + 1))
0111 = I2C Slave mode, 10-bit address
0110 = I2C Slave mode, 7-bit address
Bit combinations not specifically listed here are either reserved or implemented in SPI mode only.
Note 1: When enabled, the SDA and SCL pins must be configured as inputs.
2010 Microchip Technology Inc. DS39770C-page 203
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REGISTER 17-5: SSPCON2: MSSP CONTROL REGISTER 2 (I2C™ MASTER MODE)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
GCEN ACKSTAT ACKDT(1) ACKEN(2) RCEN(2) PEN(2) RSEN(2) SEN(2)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 GCEN: General Call Enable bit
Unused in Master mode.
bit 6 ACKSTAT: Acknowledge Status bit (Master Transmit mode only)
1 = Acknowledge was not received from slave
0 = Acknowledge was received from slave
bit 5 ACKDT: Acknowledge Data bit (Master Receive mode only)(1)
1 = Not Acknowledge
0 = Acknowledge
bit 4 ACKEN: Acknowledge Sequence Enable bit(2)
1 = Initiate Acknowledge sequence on SDA and SCL pins and transmit ACKDT data bit. Automatically
cleared by hardware.
0 = Acknowledge sequence Idle
bit 3 RCEN: Receive Enable bit (Master Receive mode only)(2)
1 = Enables Receive mode for I2C
0 = Receive Idle
bit 2 PEN: Stop Condition Enable bit(2)
1 = Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Stop condition Idle
bit 1 RSEN: Repeated Start Condition Enable bit(2)
1 = Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Repeated Start condition Idle
bit 0 SEN: Start Condition Enable bit(2)
1 = Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Start condition Idle
Note 1: Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive.
2: If the I2C module is active, these bits may not be set (no spooling) and the SSPBUF may not be written (or
writes to the SSPBUF are disabled).
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DS39770C-page 204 2010 Microchip Technology Inc.
REGISTER 17-6: SSPCON2: MSSP CONTROL REGISTER 2 (I2C™ SLAVE MODE)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
GCEN ACKSTAT ADMSK5 ADMSK4 ADMSK3 ADMSK2 ADMSK1 SEN(1)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 GCEN: General Call Enable bit
1 = Enable interrupt when a general call address (0000h) is received in the SSPSR
0 = General call address disabled
bit 6 ACKSTAT: Acknowledge Status bit
Unused in Slave mode.
bit 5-2 ADMSK<5:2>: Slave Address Mask Select bits
1 = Masking of corresponding bits of SSPADD enabled
0 = Masking of corresponding bits of SSPADD disabled
bit 1 ADMSK1: Slave Address Least Significant bit(s) Mask Select bit
In 7-Bit Address mode:
1 = Masking of SSPADD<1> only enabled
0 = Masking of SSPADD<1> only disabled
In 10-Bit Address mode:
1 = Masking of SSPADD<1:0> enabled
0 = Masking of SSPADD<1:0> disabled
bit 0 SEN: Stretch Enable bit(1)
1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled)
0 = Clock stretching is disabled
Note 1: If the I2C module is active, this bit may not be set (no spooling) and the SSPBUF may not be written (or
writes to the SSPBUF are disabled).
2010 Microchip Technology Inc. DS39770C-page 205
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17.4.2 OPERATION
The MSSP module functions are enabled by setting the
MSSP Enable bit, SSPEN (SSPCON1<5>).
The SSPCON1 register allows control of the I2C
operation. Four mode selection bits (SSPCON1<3:0>)
allow one of the following I2C modes to be selected:
•I
2C Master mode,
clock = (FOSC/4) x (SSPADD + 1)
•I
2C Slave mode (7-bit address)
•I
2C Slave mode (10-bit address)
•I
2C Slave mode (7-bit address) with Start and
Stop bit interrupts enabled
•I
2C Slave mode (10-bit address) with Start and
Stop bit interrupts enabled
•I
2C Firmware Controlled Master mode,
slave is Idle
Selection of any I2C mode, with the SSPEN bit set,
forces the SCL and SDA pins to be open-drain,
provided these pins are programmed to inputs by
setting the appropriate TRISC or TRISD bits. To ensure
proper operation of the module, pull-up resistors must
be provided externally to the SCL and SDA pins.
17.4.3 SLAVE MODE
In Slave mode, the SCL and SDA pins must be
configured as inputs (TRISC<4:3> set). The MSSP
module will override the input state with the output data
when required (slave-transmitter).
The I2C Slave mode hardware will always generate an
interrupt on an exact address match. In addition,
address masking will also allow the hardware to gener-
ate an interrupt for more than one address (up to 31 in
7-bit addressing and up to 63 in 10-bit addressing).
Through the mode select bits, the user can also choose
to interrupt on Start and Stop bits.
When an address is matched, or the data transfer after
an address match is received, the hardware auto-
matically will generate the Acknowledge (ACK) pulse
and load the SSPBUF register with the received value
currently in the SSPSR register.
Any combination of the following conditions will cause
the MSSP module not to give this ACK pulse:
• The Buffer Full bit, BF (SSPSTAT<0>), was set
before the transfer was received.
• The overflow bit, SSPOV (SSPCON1<6>), was
set before the transfer was received.
In this case, the SSPSR register value is not loaded
into the SSPBUF, but bit SSPIF is set. The BF bit is
cleared by reading the SSPBUF register, while bit
SSPOV is cleared through software.
The SCL clock input must have a minimum high and
low for proper operation. The high and low times of the
I2C specification, as well as the requirement of the
MSSP module, are shown in timing parameter 100 and
parameter 101.
17.4.3.1 Addressing
Once the MSSP module has been enabled, it waits for a
Start condition to occur. Following the Start condition, the
8 bits are shifted into the SSPSR register. All incoming
bits are sampled with the rising edge of the clock (SCL)
line. The value of register SSPSR<7:1> is compared to
the value of the SSPADD register. The address is com-
pared on the falling edge of the eighth clock (SCL) pulse.
If the addresses match and the BF and SSPOV bits are
clear, the following events occur:
1. The SSPSR register value is loaded into the
SSPBUF register.
2. The Buffer Full bit, BF, is set.
3. An ACK pulse is generated.
4. The MSSP Interrupt Flag bit, SSPIF, is set (and
interrupt is generated, if enabled) on the falling
edge of the ninth SCL pulse.
In 10-Bit Address mode, two address bytes need to be
received by the slave. The five Most Significant bits
(MSbs) of the first address byte specify if this is a 10-bit
address. Bit, R/W (SSPSTAT<2>), must specify a write
so the slave device will receive the second address byte.
For a 10-bit address, the first byte would equal ‘11110
A9 A8 0’, where ‘A9’ and ‘A8’ are the two MSbs of the
address. The sequence of events for 10-bit address is as
follows, with steps 7 through 9 for the slave-transmitter:
1. Receive the first (high) byte of address (bits,
SSPIF, BF and UA (SSPSTAT<1>), are set).
2. Update the SSPADD register with the second
(low) byte of address (clears bit, UA, and
releases the SCL line).
3. Read the SSPBUF register (clears bit, BF) and
clear flag bit, SSPIF.
4. Receive second (low) byte of address (SSPIF,
BF and UA bits are set).
5. Update the SSPADD register with the first (high)
byte of address. If match releases SCL line, this
will clear the UA bit.
6. Read the SSPBUF register (clears bit, BF) and
clear flag bit, SSPIF.
7. Receive Repeated Start condition.
8. Receive first (high) byte of address (SSPIF and
BF bits are set).
9. Read the SSPBUF register (clears BF bit) and
clear flag bit, SSPIF.
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DS39770C-page 206 2010 Microchip Technology Inc.
17.4.3.2 Address Masking
Masking an address bit causes that bit to become a
“don’t care”. When one address bit is masked, two
addresses will be Acknowledged and cause an
interrupt. It is possible to mask more than one address
bit at a time, which makes it possible to Acknowledge
up to 31 addresses in 7-bit mode and up to
63 addresses in 10-bit mode (see Example 17-2).
The I2C Slave behaves the same way whether address
masking is used or not. However, when address
masking is used, the I2C slave can Acknowledge
multiple addresses and cause interrupts. When this
occurs, it is necessary to determine which address
caused the interrupt by checking SSPBUF.
In 7-Bit Address mode, address mask bits, ADMSK<5:1>
(SSPCON<5:1>), mask the corresponding address bits
in the SSPADD register. For any ADMSK bits that are set
(ADMSK<n> = 1), the corresponding address bit is
ignored (SSPADD<n> = x). For the module to issue an
address Acknowledge, it is sufficient to match only on
addresses that do not have an active address mask.
In 10-Bit Address mode, the ADMSK<5:2> bits mask
the corresponding address bits in the SSPADD regis-
ter. In addition, ADMSK1 simultaneously masks the two
LSbs of the address (SSPADD<1:0>). For any ADMSK
bits that are active (ADMSK<n> = 1), the correspond-
ing address bit is ignored (SSPADD<n> = x). Also
note, that although in 10-Bit Addressing mode, the
upper address bits reuse part of the SSPADD register
bits. The address mask bits do not interact with those
bits; they only affect the lower address bits.
EXAMPLE 17-2: ADDRESS MASKING EXAMPLES
Note 1: ADMSK1 masks the two Least Significant
bits of the address.
2: The two Most Significant bits of the
address are not affected by address
masking.
7-Bit Addressing:
SSPADD<7:1> = A0h (1010000) (SSPADD<0> is assumed to be ‘0’)
ADMSK<5:1> = 00111
Addresses Acknowledged: A0h, A2h, A4h, A6h, A8h, AAh, ACh, AEh
10-Bit Addressing:
SSPADD<7:0> = A0h (10100000) (the two MSbs of the address are ignored in this example, since they are
not affected by masking)
ADMSK<5:1> = 00111
Addresses Acknowledged: A0h, A1h, A2h, A3h, A4h, A5h, A6h, A7h, A8h, A9h, AAh, ABh, ACh, ADh, AEh, AFh
2010 Microchip Technology Inc. DS39770C-page 207
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17.4.3.3 Reception
When the R/W bit of the address byte is clear and an
address match occurs, the R/W bit of the SSPSTAT
register is cleared. The received address is loaded into
the SSPBUF register and the SDA line is held low
(ACK).
When the address byte overflow condition exists, then
the no Acknowledge (ACK) pulse is given. An overflow
condition is defined as either bit, BF (SSPSTAT<0>), is
set or bit, SSPOV (SSPCON1<6>), is set.
An MSSP interrupt is generated for each data transfer
byte. The interrupt flag bit, SSPIF, must be cleared in
software. The SSPSTAT register is used to determine
the status of the byte.
If SEN is enabled (SSPCON2<0> = 1), SCK/SCL will
be held low (clock stretch) following each data
transfer. The clock must be released by setting bit,
CKP (SSPCON1<4>). See Section 17.4.4 “Clock
Stretching” for more details.
17.4.3.4 Transmission
When the R/W bit of the incoming address byte is set
and an address match occurs, the R/W bit of the
SSPSTAT register is set. The received address is
loaded into the SSPBUF register. The ACK pulse will
be sent on the ninth bit and pin RC3 is held low, regard-
less of SEN (see Section 17.4.4 “Clock Stretching”
for more details). By stretching the clock, the master
will be unable to assert another clock pulse until the
slave is done preparing the transmit data. The transmit
data must be loaded into the SSPBUF register which
also loads the SSPSR register. Then, pin RC3 should
be enabled by setting bit, CKP (SSPCON1<4>). The
eight data bits are shifted out on the falling edge of the
SCL input. This ensures that the SDA signal is valid
during the SCL high time (Figure 17-10).
The ACK pulse from the master-receiver is latched on
the rising edge of the ninth SCL input pulse. If the SDA
line is high (not ACK), then the data transfer is
complete. In this case, when the ACK is latched by the
slave, the slave logic is reset and the slave monitors for
another occurrence of the Start bit. If the SDA line was
low (ACK), the next transmit data must be loaded into
the SSPBUF register. Again, pin RC3 must be enabled
by setting bit, CKP.
An MSSP interrupt is generated for each data transfer
byte. The SSPIF bit must be cleared in software and
the SSPSTAT register is used to determine the status
of the byte. The SSPIF bit is set on the falling edge of
the ninth clock pulse.
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DS39770C-page 208 2010 Microchip Technology Inc.
FIGURE 17-8: I2C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 7-BIT ADDRESS)
SDA
SCL
SSPIF (PIR1<3>)
BF (SSPSTAT<0>)
SSPOV (SSPCON1<6>)
S12345678912345678912345 789 P
A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D1 D0
ACK
Receiving Data
ACK
Receiving Data
R/W = 0
ACK
Receiving Address
Cleared in software
SSPBUF is read
Bus master
terminates
transfer
SSPOV is set
because SSPBUF is
still full. ACK is not sent.
D2
6
CKP
(CKP does not reset to ‘0’ when SEN = 0)
2010 Microchip Technology Inc. DS39770C-page 209
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FIGURE 17-9: I2C™ SLAVE MODE TIMING WITH SEN = 0 AND ADMSK<5:1> = 01011
(RECEPTION, 7-BIT ADDRESS)
SDA
SCL
SSPIF (PIR1<3>)
BF (SSPSTAT<0>)
SSPOV (SSPCON1<6>)
S1 234567 89 12 34567 891 2345 7 89 P
A7 A6 A5 X A3 X X D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D1 D0
ACK
Receiving Data
ACK
Receiving Data
R/W = 0
ACK
Receiving Address
Cleared in software
SSPBUF is read
Bus master
terminates
transfer
SSPOV is set
because SSPBUF is
still full. ACK is not sent.
D2
6
CKP
(CKP does not reset to ‘0’ when SEN = 0)
Note 1: x = Don’t care (i.e., address bit can be either a ‘1’ or a ‘0’).
2: In this example, an address equal to A7.A6.A5.X.A3.X.X will be Acknowledged and cause an interrupt.
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DS39770C-page 210 2010 Microchip Technology Inc.
FIGURE 17-10: I2C™ SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESS)
SDAx
SCLx
BF (SSPxSTAT<0>)
A6 A5 A4 A3 A2 A1 D6 D5 D4 D3 D2 D1 D0
1 2 3 4 5 6 7 8 2 3 4 5 6 7 8 9
SSPxBUF is written in software
Cleared in software
Data in
sampled
S
ACK
Transmitting Data
R/W = 1
ACK
Receiving Address
A7 D7
9 1
D6 D5 D4 D3 D2 D1 D0
2 3 4 5 6 7 8 9
SSPxBUF is written in software
Cleared in software
From SSPxIF ISR
Transmitting Data
D7
1
CKP
(SSPxCON1<4>)
P
ACK
CKP is set in software CKP is set in software
SCLx held low
while CPU
responds to SSPxIF
SSPxIF (PIR1<3> or PIR3<7>)
From SSPxIF ISR
Clear by reading
2010 Microchip Technology Inc. DS39770C-page 211
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FIGURE 17-11: I2C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 10-BIT ADDRESS)
SDA
SCL
SSPIF (PIR1<3>)
BF (SSPSTAT<0>)
S123456789 123456789 12345 789 P
1 1 1 1 0 A9A8 A7 A6A5A4A3A2A1A0 D7 D6D5D4D3 D1D0
Receive Data Byte
ACK
R/W = 0
ACK
Receive First Byte of Address
Cleared in software
D2
6
Cleared in software
Receive Second Byte of Address
Cleared by hardware
when SSPADD is updated
with low byte of address
UA (SSPSTAT<1>)
Clock is held low until
update of SSPADD has
taken place
UA is set indicating that
the SSPADD needs to be
updated
UA is set indicating that
SSPADD needs to be
updated
Cleared by hardware when
SSPADD is updated with high
byte of address
SSPBUF is written with
contents of SSPSR
Dummy read of SSPBUF
to clear BF flag
ACK
CKP
12345 789
D7 D6 D5 D4 D3 D1 D0
Receive Data Byte
Bus master
terminates
transfer
D2
6
ACK
Cleared in software Cleared in software
SSPOV (SSPCON1<6>)
SSPOV is set
because SSPBUF is
still full. ACK is not sent.
(CKP does not reset to ‘0’ when SEN = 0)
Clock is held low until
update of SSPADD has
taken place
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DS39770C-page 212 2010 Microchip Technology Inc.
FIGURE 17-12: I2C™ SLAVE MODE TIMING WITH SEN = 0 AND ADMSK<5:1> = 01001
(RECEPTION, 10-BIT ADDRESS)
SDA
SCL
SSPIF (PIR1<3>)
BF (SSPSTAT<0>)
S123456789 123456789 12345 789 P
1 1 1 1 0 A9 A8 A7 A6 A5 X A3 A2 X X D7 D6 D5 D4 D3 D1 D0
Receive Data Byte
ACK
R/W = 0
ACK
Receive First Byte of Address
Cleared in software
D2
6
Cleared in software
Receive Second Byte of Address
Cleared by hardware
when SSPADD is updated
with low byte of address
UA (SSPSTAT<1>)
Clock is held low until
update of SSPADD has
taken place
UA is set indicating that
the SSPADD needs to be
updated
UA is set indicating that
SSPADD needs to be
updated
Cleared by hardware when
SSPADD is updated with high
byte of address
SSPBUF is written with
contents of SSPSR
Dummy read of SSPBUF
to clear BF flag
ACK
CKP
12345 789
D7 D6 D5 D4 D3 D1 D0
Receive Data Byte
Bus master
terminates
transfer
D2
6
ACK
Cleared in software Cleared in software
SSPOV (SSPCON1<6>)
SSPOV is set
because SSPBUF is
still full. ACK is not sent.
(CKP does not reset to ‘0’ when SEN = 0)
Clock is held low until
update of SSPADD has
taken place
Note 1: x = Don’t care (i.e., address bit can be either a ‘1’ or a ‘0’).
2: In this example, an address equal to A9.A8.A7.A6.A5.X.A3.A2.X.X will be Acknowledged and cause an interrupt.
3: Note that the Most Significant bits of the address are not affected by the bit masking.
2010 Microchip Technology Inc. DS39770C-page 213
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FIGURE 17-13: I2C™ SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS)
SDA
SCL
SSPIF (PIR1<3>)
BF (SSPSTAT<0>)
S12345 6789 123 45 678 9 12345 7 89 P
1 1 1 1 0 A9A8 A7 A6A5A4A3A2A1A0 11110 A8
R/W = 1
ACK
ACK
R/W = 0
ACK
Receive First Byte of Address
Cleared in software
Bus master
terminates
transfer
A9
6
Receive Second Byte of Address
Cleared by hardware when
SSPADD is updated with low
byte of address
UA (SSPSTAT<1>)
Clock is held low until
update of SSPADD has
taken place
UA is set indicating that
the SSPADD needs to be
updated
UA is set indicating that
SSPADD needs to be
updated
Cleared by hardware when
SSPADD is updated with high
byte of address.
SSPBUF is written with
contents of SSPSR
Dummy read of SSPBUF
to clear BF flag
Receive First Byte of Address
12345 789
D7 D6 D5 D4 D3 D1
ACK
D2
6
Transmitting Data Byte
D0
Dummy read of SSPBUF
to clear BF flag
Sr
Cleared in software
Write of SSPBUF
initiates transmit
Cleared in software
Completion of
clears BF flag
CKP (SSPCON1<4>)
CKP is set in software
CKP is automatically cleared in hardware, holding SCL low
Clock is held low until
update of SSPADD has
taken place
data transmission
Clock is held low until
CKP is set to ‘1’
third address sequence
BF flag is clear
at the end of the
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17.4.4 CLOCK STRETCHING
Both 7-Bit and 10-Bit Slave modes implement
automatic clock stretching during a transmit sequence.
The SEN bit (SSPCON2<0>) allows clock stretching to
be enabled during receives. Setting SEN will cause
the SCL pin to be held low at the end of each data
receive sequence.
17.4.4.1 Clock Stretching for 7-Bit Slave
Receive Mode (SEN = 1)
In 7-Bit Slave Receive mode, on the falling edge of the
ninth clock at the end of the ACK sequence, if the BF
bit is set, the CKP bit in the SSPCON1 register is
automatically cleared, forcing the SCL output to be
held low. The CKP being cleared to ‘0’ will assert the
SCL line low. The CKP bit must be set in the user’s
ISR before reception is allowed to continue. By holding
the SCL line low, the user has time to service the ISR
and read the contents of the SSPBUF before the
master device can initiate another receive sequence.
This will prevent buffer overruns from occurring (see
Figure 17-15).
17.4.4.2 Clock Stretching for 10-Bit Slave
Receive Mode (SEN = 1)
In 10-Bit Slave Receive mode, during the address
sequence, clock stretching automatically takes place
but CKP is not cleared. During this time, if the UA bit is
set after the ninth clock, clock stretching is initiated.
The UA bit is set after receiving the upper byte of the
10-bit address and following the receive of the second
byte of the 10-bit address with the R/W bit cleared to
‘0’. The release of the clock line occurs upon updating
SSPADD. Clock stretching will occur on each data
receive sequence as described in 7-bit mode.
17.4.4.3 Clock Stretching for 7-Bit Slave
Transmit Mode
The 7-Bit Slave Transmit mode implements clock
stretching by clearing the CKP bit after the falling edge
of the ninth clock if the BF bit is clear. This occurs
regardless of the state of the SEN bit.
The user’s ISR must set the CKP bit before transmis-
sion is allowed to continue. By holding the SCL line
low, the user has time to service the ISR and load the
contents of the SSPBUF before the master device can
initiate another transmit sequence (see Figure 17-10).
17.4.4.4 Clock Stretching for 10-Bit Slave
Transmit Mode
In 10-Bit Slave Transmit mode, clock stretching is con-
trolled during the first two address sequences by the
state of the UA bit, just as it is in 10-Bit Slave Receive
mode. The first two addresses are followed by a third
address sequence which contains the high-order bits
of the 10-bit address and the R/W bit set to ‘1’. After
the third address sequence is performed, the UA bit is
not set, the module is now configured in Transmit
mode and clock stretching is controlled by the BF flag
as in 7-Bit Slave Transmit mode (see Figure 17-13).
Note 1: If the user reads the contents of the
SSPBUF before the falling edge of the
ninth clock, thus clearing the BF bit, the
CKP bit will not be cleared and clock
stretching will not occur.
2: The CKP bit can be set in software
regardless of the state of the BF bit. The
user should be careful to clear the BF bit
in the ISR before the next receive
sequence in order to prevent an overflow
condition.
Note: If the user polls the UA bit and clears it by
updating the SSPADD register before the
falling edge of the ninth clock occurs and if
the user hasn’t cleared the BF bit by read-
ing the SSPBUF register before that time,
then the CKP bit will still NOT be asserted
low. Clock stretching on the basis of the
state of the BF bit only occurs during a
data sequence, not an address sequence.
Note 1: If the user loads the contents of SSPBUF,
setting the BF bit before the falling edge of
the ninth clock, the CKP bit will not be
cleared and clock stretching will not occur.
2: The CKP bit can be set in software
regardless of the state of the BF bit.
2010 Microchip Technology Inc. DS39770C-page 215
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17.4.4.5 Clock Synchronization and
the CKP bit
When the CKP bit is cleared, the SCL output is forced
to ‘0’. However, clearing the CKP bit will not assert the
SCL output low until the SCL output is already sam-
pled low. Therefore, the CKP bit will not assert the
SCL line until an external I2C master device has
already asserted the SCL line. The SCL output will
remain low until the CKP bit is set and all other
devices on the I2C bus have deasserted SCL. This
ensures that a write to the CKP bit will not violate the
minimum high time requirement for SCL (see
Figure 17-14).
FIGURE 17-14: CLOCK SYNCHRONIZATION TIMING
SDA
SCL
DX – 1DX
WR
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
SSPCON
CKP
Master device
deasserts clock
Master device
asserts clock
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DS39770C-page 216 2010 Microchip Technology Inc.
FIGURE 17-15: I2C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 7-BIT ADDRESS)
SDA
SCL
SSPIF (PIR1<3>)
BF (SSPSTAT<0>)
SSPOV (SSPCON1<6>)
S123456789 123456789 12345 789 P
A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D1 D0
ACK
Receiving Data
ACK
Receiving Data
R/W = 0
ACK
Receiving Address
Cleared in software
SSPBUF is read
Bus master
terminates
transfer
SSPOV is set
because SSPBUF is
still full. ACK is not sent.
D2
6
CKP
CKP
written
to ‘1’ in
If BF is cleared
prior to the falling
edge of the 9th clock,
CKP will not be reset
to ‘0’ and no clock
stretching will occur
software
Clock is held low until
CKP is set to ‘1’
Clock is not held low
because buffer full bit is
clear prior to falling edge
of 9th clock
Clock is not held low
because ACK =
1
BF is set after falling
edge of the 9th clock,
CKP is reset to ‘0’ and
clock stretching occurs
2010 Microchip Technology Inc. DS39770C-page 217
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FIGURE 17-16: I2C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 10-BIT ADDRESS)
SDA
SCL
SSPIF (PIR1<3>)
BF (SSPSTAT<0>)
S123456789 123456789 12345 789 P
1 1 1 1 0 A9A8 A7 A6A5A4A3A2A1A0 D7D6D5D4D3 D1D0
Receive Data Byte
ACK
R/W = 0
ACK
Receive First Byte of Address
Cleared in software
D2
6
Cleared in software
Receive Second Byte of Address
Cleared by hardware when
SSPADD is updated with low
byte of address after falling edge
UA (SSPSTAT<1>)
Clock is held low until
update of SSPADD has
taken place
UA is set indicating that
the SSPADD needs to be
updated
UA is set indicating that
SSPADD needs to be
updated
Cleared by hardware when
SSPADD is updated with high
byte of address after falling edge
SSPBUF is written with
contents of SSPSR
Dummy read of SSPBUF
to clear BF flag
ACK
CKP
12345 789
D7 D6 D5 D4 D3 D1 D0
Receive Data Byte
Bus master
terminates
transfer
D2
6
ACK
Cleared in software Cleared in software
SSPOV (SSPCON1<6>)
CKP written to
‘
1
’
Note: An update of the SSPADD register before the
falling edge of the ninth clock will have no effect
on UA and UA will remain set.
Note: An update of the SSPADD
register before the falling
edge of the ninth clock will
have no effect on UA and
UA will remain set.
in software
Clock is held low until
update of SSPADD has
taken place
of ninth clock
of ninth clock
SSPOV is set
because SSPBUF is
still full. ACK is not sent.
Dummy read of SSPBUF
to clear BF flag
Clock is held low until
CKP is set to
‘
1
’
Clock is not held low
because ACK =
1
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DS39770C-page 218 2010 Microchip Technology Inc.
17.4.5 GENERAL CALL ADDRESS
SUPPORT
The addressing procedure for the I2C bus is such that
the first byte after the Start condition usually
determines which device will be the slave addressed by
the master. The exception is the general call address
which can address all devices. When this address is
used, all devices should, in theory, respond with an
Acknowledge.
The general call address is one of eight addresses
reserved for specific purposes by the I2C protocol. It
consists of all ‘0’s with R/W = 0.
The general call address is recognized when the
General Call Enable bit, GCEN, is enabled
(SSPCON2<7> set). Following a Start bit detect, 8 bits
are shifted into the SSPSR and the address is
compared against the SSPADD. It is also compared to
the general call address and fixed in hardware.
If the general call address matches, the SSPSR is
transferred to the SSPBUF, the BF flag bit is set (eighth
bit) and on the falling edge of the ninth bit (ACK bit), the
SSPIF interrupt flag bit is set.
When the interrupt is serviced, the source for the
interrupt can be checked by reading the contents of the
SSPBUF. The value can be used to determine if the
address was device-specific or a general call address.
In 10-bit mode, the SSPADD is required to be updated
for the second half of the address to match and the UA
bit is set (SSPSTAT<1>). If the general call address is
sampled when the GCEN bit is set, while the slave is
configured in 10-Bit Address mode, then the second
half of the address is not necessary, the UA bit will not
be set and the slave will begin receiving data after the
Acknowledge (Figure 17-17).
FIGURE 17-17: SLAVE MODE GENERAL CALL ADDRESS SEQUENCE
(7 OR 10-BIT ADDRESS MODE)
SDA
SCL
S
SSPIF
BF (SSPSTAT<0>)
SSPOV (SSPCON1<6>)
Cleared in software
SSPBUF is read
R/W = 0
ACK
General Call Address
Address is compared to General Call Address
GCEN (SSPCON2<7>)
Receiving Data ACK
123456789123456789
D7 D6 D5 D4 D3 D2 D1 D0
after ACK, set interrupt
‘0’
‘1’
2010 Microchip Technology Inc. DS39770C-page 219
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17.4.6 MASTER MODE
Master mode is enabled by setting and clearing the
appropriate SSPM bits in SSPCON1 and by setting the
SSPEN bit. In Master mode, the SCL and SDA lines
are manipulated by the MSSP hardware.
Master mode of operation is supported by interrupt
generation on the detection of the Start and Stop con-
ditions. The Stop (P) and Start (S) bits are cleared from
a Reset or when the MSSP module is disabled. Control
of the I2C bus may be taken when the P bit is set, or the
bus is Idle, with both the S and P bits clear.
In Firmware Controlled Master mode, user code
conducts all I2C bus operations based on Start and
Stop bit conditions.
Once Master mode is enabled, the user has six
options.
1. Assert a Start condition on SDA and SCL.
2. Assert a Repeated Start condition on SDA and
SCL.
3. Write to the SSPBUF register initiating
transmission of data/address.
4. Configure the I2C port to receive data.
5. Generate an Acknowledge condition at the end
of a received byte of data.
6. Generate a Stop condition on SDA and SCL.
The following events will cause the MSSP Interrupt
Flag bit, SSPIF, to be set (and MSSP interrupt, if
enabled):
• Start condition
• Stop condition
• Data transfer byte transmitted/received
• Acknowledge transmit
• Repeated Start
FIGURE 17-18: MSSP BLOCK DIAGRAM (I2C™ MASTER MODE)
Note: The MSSP module, when configured in
I2C Master mode, does not allow queueing
of events. For instance, the user is not
allowed to initiate a Start condition and
immediately write the SSPBUF register to
initiate transmission before the Start con-
dition is complete. In this case, the
SSPBUF will not be written to and the
WCOL bit will be set, indicating that a write
to the SSPBUF did not occur.
Read Write
SSPSR
Start bit, Stop bit,
SSPBUF
Internal
Data Bus
Set/Reset S, P, WCOL (SSPSTAT, SSPCON1)
Shift
Clock
MSb LSb
SDA
Acknowledge
Generate
Stop bit Detect
Write Collision Detect
Clock Arbitration
State Counter for
End of XMIT/RCV
SCL
SCL In
Bus Collision
SDA In
Receive Enable
Clock Cntl
Clock Arbitrate/WCOL Detect
(hold off clock source)
SSPADD<6:0>
Baud
Set SSPIF, BCLIF
Reset ACKSTAT, PEN (SSPCON2)
Rate
Generator
SSPM<3:0>
Start bit Detect
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17.4.6.1 I2C Master Mode Operation
The master device generates all of the serial clock
pulses and the Start and Stop conditions. A transfer is
ended with a Stop condition or with a Repeated Start
condition. Since the Repeated Start condition is also
the beginning of the next serial transfer, the I2C bus will
not be released.
In Master Transmitter mode, serial data is output
through SDA, while SCL outputs the serial clock. The
first byte transmitted contains the slave address of the
receiving device (7 bits) and the Read/Write (R/W) bit.
In this case, the R/W bit will be logic ‘0’. Serial data is
transmitted 8 bits at a time. After each byte is transmit-
ted, an Acknowledge bit is received. Start and Stop
conditions are output to indicate the beginning and the
end of a serial transfer.
In Master Receive mode, the first byte transmitted
contains the slave address of the transmitting device
(7 bits) and the R/W bit. In this case, the R/W bit will be
logic ‘1’. Thus, the first byte transmitted is a 7-bit slave
address followed by a ‘1’ to indicate the receive bit.
Serial data is received via SDA, while SCL outputs the
serial clock. Serial data is received 8 bits at a time. After
each byte is received, an Acknowledge bit is transmit-
ted. Start and Stop conditions indicate the beginning
and end of transmission.
The Baud Rate Generator used for the SPI mode
operation is used to set the SCL clock frequency for
either 100 kHz, 400 kHz or 1 MHz I2C operation. See
Section 17.4.7 “Baud Rate” for more details.
A typical transmit sequence would go as follows:
1. The user generates a Start condition by setting
the Start Enable bit, SEN (SSPCON2<0>).
2. SSPIF is set. The MSSP module will wait the
required start time before any other operation
takes place.
3. The user loads the SSPBUF with the slave
address to transmit.
4. The address is shifted out of the SDA pin until all
8 bits are transmitted.
5. The MSSP module shifts in the ACK bit from the
slave device and writes its value into the
SSPCON2 register (SSPCON2<6>).
6. The MSSP module generates an interrupt at the
end of the ninth clock cycle by setting the SSPIF
bit.
7. The user loads the SSPBUF with eight bits of
data.
8. Data is shifted out of the SDA pin until all 8 bits
are transmitted.
9. The MSSP module shifts in the ACK bit from the
slave device and writes its value into the
SSPCON2 register (SSPCON2<6>).
10. The MSSP module generates an interrupt at the
end of the ninth clock cycle by setting the SSPIF
bit.
11. The user generates a Stop condition by setting
the Stop Enable bit, PEN (SSPCON2<2>).
12. The interrupt is generated once the Stop condition
is complete.
2010 Microchip Technology Inc. DS39770C-page 221
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17.4.7 BAUD RATE
In I2C Master mode, the Baud Rate Generator (BRG)
reload value is placed in the lower 7 bits of the
SSPADD register (Figure 17-19). When a write occurs
to SSPBUF, the Baud Rate Generator will automatically
begin counting. The BRG counts down to 0 and stops
until another reload has taken place. The BRG count is
decremented twice per instruction cycle (TCY) on the
Q2 and Q4 clocks. In I2C Master mode, the BRG is
reloaded automatically.
Once the given operation is complete (i.e., transmis-
sion of the last data bit is followed by ACK), the internal
clock will automatically stop counting and the SCL pin
will remain in its last state.
Table 17-3 demonstrates clock rates based on
instruction cycles and the BRG value loaded into
SSPADD. The SSPADD BRG value of 0x00 is not
supported
17.4.7.1 Baud Rate Generation in
Power-Managed Modes
When the device is operating in one of the
power-managed modes, the clock source to the BRG
may change frequency or even stop, depending on the
mode and clock source selected. Switching to a Run or
Idle mode from either the secondary clock or internal
oscillator is likely to change the clock rate to the BRG.
In Sleep mode, the BRG will not be clocked at all.
FIGURE 17-19: BAUD RATE GENERATOR BLOCK DIAGRAM
TABLE 17-3: I2C™ CLOCK RATE w/BRG
FCY FCY * 2 BRG Value FSCL
(2 Rollovers of BRG)
10 MHz 20 MHz 18h 400 kHz(1)
10 MHz 20 MHz 1Fh 312.5 kHz
10 MHz 20 MHz 63h 100 kHz
4 MHz 8 MHz 09h 400 kHz(1)
4 MHz 8 MHz 0Ch 308 kHz
4 MHz 8 MHz 27h 100 kHz
1 MHz 2 MHz 02h 333 kHz(1)
1 MHz 2 MHz 09h 100 kHz
Note 1: The I2C interface does not conform to the 400 kHz I2C specification (which applies to rates greater than
100 kHz) in all details, but may be used with care where higher rates are required by the application.
SSPM<3:0>
BRG Down Counter
CLKO FOSC/4
SSPADD<6:0>
SSPM<3:0>
SCL
Reload
Control
Reload
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17.4.7.2 Clock Arbitration
Clock arbitration occurs when the master, during any
receive, transmit or Repeated Start/Stop condition,
deasserts the SCL pin (SCL allowed to float high).
When the SCL pin is allowed to float high, the Baud
Rate Generator (BRG) is suspended from counting
until the SCL pin is actually sampled high. When the
SCL pin is sampled high, the Baud Rate Generator is
reloaded with the contents of SSPADD<6:0> and
begins counting. This ensures that the SCL high time
will always be at least one BRG rollover count in the
event that the clock is held low by an external device
(Figure 17-20).
FIGURE 17-20: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION
SDA
SCL
SCL deasserted but slave holds
DX – 1DX
BRG
SCL is sampled high, reload takes
place and BRG starts its count
03h 02h 01h 00h (hold off) 03h 02h
Reload
BRG
Value
SCL low (clock arbitration)
SCL allowed to transition high
BRG decrements on
Q2 and Q4 cycles
2010 Microchip Technology Inc. DS39770C-page 223
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17.4.8 I2C MASTER MODE START
CONDITION TIMING
To initiate a Start condition, the user sets the Start
Enable bit, SEN (SSPCON2<0>). If the SDA and SCL
pins are sampled high, the Baud Rate Generator is
reloaded with the contents of SSPADD<6:0> and starts
its count. If SCL and SDA are both sampled high when
the Baud Rate Generator times out (TBRG), the SDA
pin is driven low. The action of the SDA being driven
low while SCL is high is the Start condition and causes
the S bit (SSPSTAT<3>) to be set. Following this, the
Baud Rate Generator is reloaded with the contents of
SSPADD<6:0> and resumes its count. When the Baud
Rate Generator times out (TBRG), the SEN bit
(SSPCON2<0>) will be automatically cleared by
hardware. The Baud Rate Generator is suspended,
leaving the SDA line held low and the Start condition is
complete.
17.4.8.1 WCOL Status Flag
If the user writes the SSPBUF when a Start sequence
is in progress, the WCOL is set and the contents of the
buffer are unchanged (the write doesn’t occur).
FIGURE 17-21: FIRST START BIT TIMING
Note: If, at the beginning of the Start condition, the
SDA and SCL pins are already sampled
low, or if during the Start condition, the SCL
line is sampled low before the SDA line is
driven low, a bus collision occurs. The Bus
Collision Interrupt Flag, BCLIF, is set, the
Start condition is aborted and the I2C
module is reset into its Idle state.
Note: Because queueing of events is not
allowed, writing to the lower 5 bits of
SSPCON2 is disabled until the Start
condition is complete.
SDA
SCL
S
TBRG
1st bit 2nd bit
TBRG
SDA = 1, At completion of Start bit,
SCL = 1
Write to SSPBUF occurs here
TBRG
hardware clears SEN bit
TBRG
Write to SEN bit occurs here Set S bit (SSPSTAT<3>)
and sets SSPIF bit
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DS39770C-page 224 2010 Microchip Technology Inc.
17.4.9 I2C MASTER MODE REPEATED
START CONDITION TIMING
A Repeated Start condition occurs when the RSEN bit
(SSPCON2<1>) is programmed high and the I2C logic
module is in the Idle state. When the RSEN bit is set,
the SCL pin is asserted low. When the SCL pin is
sampled low, the Baud Rate Generator is loaded with
the contents of SSPADD<6:0> and begins counting.
The SDA pin is released (brought high) for one Baud
Rate Generator count (TBRG). When the Baud Rate
Generator times out, if SDA is sampled high, the SCL
pin will be deasserted (brought high). When SCL is
sampled high, the Baud Rate Generator is reloaded
with the contents of SSPADD<6:0> and begins
counting. SDA and SCL must be sampled high for one
TBRG. This action is then followed by assertion of the
SDA pin (SDA = 0) for one TBRG while SCL is high.
Following this, the RSEN bit (SSPCON2<1>) will be
automatically cleared and the Baud Rate Generator will
not be reloaded, leaving the SDA pin held low. As soon
as a Start condition is detected on the SDA and SCL
pins, the S bit (SSPSTAT<3>) will be set. The SSPIF bit
will not be set until the Baud Rate Generator has timed
out.
Immediately following the SSPIF bit getting set, the user
may write the SSPBUF with the 7-bit address in 7-bit
mode or the default first address in 10-bit mode. After the
first eight bits are transmitted and an ACK is received,
the user may then transmit an additional eight bits of
address (10-bit mode) or eight bits of data (7-bit mode).
17.4.9.1 WCOL Status Flag
If the user writes the SSPBUF when a Repeated Start
sequence is in progress, the WCOL is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
FIGURE 17-22: REPEATED START CONDITION WAVEFORM
Note 1: If RSEN is programmed while any other
event is in progress, it will not take effect.
2: A bus collision during the Repeated Start
condition occurs if:
• SDA is sampled low when SCL goes
from low-to-high.
• SCL goes low before SDA is
asserted low. This may indicate that
another master is attempting to
transmit a data ‘1’.
Note: Because queueing of events is not
allowed, writing of the lower 5 bits of
SSPCON2 is disabled until the Repeated
Start condition is complete.
SDA
SCL
Sr = Repeated Start
Write to SSPCON2
Write to SSPBUF occurs here
on falling edge of ninth clock,
end of Xmit
At completion of Start bit,
hardware clears RSEN bit
1st bit
S bit set by hardware
TBRG
TBRG
SDA = 1,
SDA = 1,
SCL (no change)
SCL = 1
occurs here:
TBRG TBRG
and sets SSPIF
RSEN bit set by hardware
TBRG
2010 Microchip Technology Inc. DS39770C-page 225
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17.4.10 I2C MASTER MODE
TRANSMISSION
Transmission of a data byte, a 7-bit address or the
other half of a 10-bit address is accomplished by simply
writing a value to the SSPBUF register. This action will
set the Buffer Full bit, BF, and allow the Baud Rate
Generator to begin counting and start the next trans-
mission. Each bit of address/data will be shifted out
onto the SDA pin after the falling edge of SCL is
asserted (see data hold time specification
parameter 106). SCL is held low for one Baud Rate
Generator rollover count (TBRG). Data should be valid
before SCL is released high (see data setup time
specification parameter 107). When the SCL pin is
released high, it is held that way for TBRG. The data on
the SDA pin must remain stable for that duration and
some hold time after the next falling edge of SCL. After
the eighth bit is shifted out (the falling edge of the eighth
clock), the BF flag is cleared and the master releases
SDA. This allows the slave device being addressed to
respond with an ACK bit during the ninth bit time if an
address match occurred, or if data was received prop-
erly. The status of ACK is written into the ACKDT bit on
the falling edge of the ninth clock. If the master receives
an Acknowledge, the Acknowledge Status bit,
ACKSTAT, is cleared; if not, the bit is set. After the ninth
clock, the SSPIF bit is set and the master clock (Baud
Rate Generator) is suspended until the next data byte
is loaded into the SSPBUF, leaving SCL low and SDA
unchanged (Figure 17-23).
After the write to the SSPBUF, each bit of the address
will be shifted out on the falling edge of SCL until all
seven address bits and the R/W bit are completed. On
the falling edge of the eighth clock, the master will
deassert the SDA pin, allowing the slave to respond
with an Acknowledge. On the falling edge of the ninth
clock, the master will sample the SDA pin to see if the
address was recognized by a slave. The status of the
ACK bit is loaded into the ACKSTAT status bit
(SSPCON2<6>). Following the falling edge of the ninth
clock transmission of the address, the SSPIF is set, the
BF flag is cleared and the Baud Rate Generator is
turned off until another write to the SSPBUF takes
place, holding SCL low and allowing SDA to float.
17.4.10.1 BF Status Flag
In Transmit mode, the BF bit (SSPSTAT<0>) is set
when the CPU writes to SSPBUF and is cleared when
all 8 bits are shifted out.
17.4.10.2 WCOL Status Flag
If the user writes to the SSPBUF when a transmit is
already in progress (i.e., SSPSR is still shifting out a
data byte), the WCOL is set and the contents of the buf-
fer are unchanged (the write doesn’t occur) after 2 TCY
after the SSPBUF write. If SSPBUF is rewritten within
2 TCY, the WCOL bit is set and SSPBUF is updated.
This may result in a corrupted transfer.
The user should verify that the WCOL is clear after
each write to SSPBUF to ensure the transfer is correct.
In all cases, WCOL must be cleared in software.
17.4.10.3 ACKSTAT Status Flag
In Transmit mode, the ACKSTAT bit (SSPCON2<6>) is
cleared when the slave has sent an Acknowledge
(ACK =0) and is set when the slave does not Acknowl-
edge (ACK = 1). A slave sends an Acknowledge when
it has recognized its address (including a general call),
or when the slave has properly received its data.
17.4.11 I2C MASTER MODE RECEPTION
Master mode reception is enabled by programming the
Receive Enable bit, RCEN (SSPCON2<3>).
The Baud Rate Generator begins counting and on each
rollover, the state of the SCL pin changes
(high-to-low/low-to-high) and data is shifted into the
SSPSR. After the falling edge of the eighth clock, the
receive enable flag is automatically cleared, the con-
tents of the SSPSR are loaded into the SSPBUF, the
BF flag bit is set, the SSPIF flag bit is set and the Baud
Rate Generator is suspended from counting, holding
SCL low. The MSSP is now in Idle state awaiting the
next command. When the buffer is read by the CPU,
the BF flag bit is automatically cleared. The user can
then send an Acknowledge bit at the end of reception
by setting the Acknowledge Sequence Enable bit,
ACKEN (SSPCON2<4>).
17.4.11.1 BF Status Flag
In receive operation, the BF bit is set when an address
or data byte is loaded into SSPBUF from SSPSR. It is
cleared when the SSPBUF register is read.
17.4.11.2 SSPOV Status Flag
In receive operation, the SSPOV bit is set when 8 bits
are received into the SSPSR and the BF flag bit is
already set from a previous reception.
17.4.11.3 WCOL Status Flag
If the user writes the SSPBUF when a receive is
already in progress (i.e., SSPSR is still shifting in a data
byte), the WCOL bit is set and the contents of the buffer
are unchanged (the write doesn’t occur).
Note: The MSSP module must be in an Idle state
before the RCEN bit is set or the RCEN bit
will be disregarded.
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DS39770C-page 226 2010 Microchip Technology Inc.
FIGURE 17-23: I2C™ MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS)
SDA
SCL
SSPIF
BF (SSPSTAT<0>)
SEN
A7 A6 A5 A4 A3 A2 A1 ACK = 0D7 D6 D5 D4 D3 D2 D1 D0
ACK
Transmitting Data or Second Half
R/W = 0Transmit Address to Slave
123456789 123456789 P
Cleared in software service routine
SSPBUF is written in software
from MSSP interrupt
After Start condition, SEN cleared by hardware
S
SSPBUF written with 7-bit address and R/W
start transmit
SCL held low
while CPU
responds to SSPIF
SEN = 0
of 10-bit Address
Write SSPCON2<0> (SEN = 1),
Start condition begins From slave, clear ACKSTAT bit (SSPCON2<6>)
ACKSTAT in
SSPCON2 = 1
Cleared in software
SSPBUF written
PEN
R/W
Cleared in software
2010 Microchip Technology Inc. DS39770C-page 227
PIC18F85J90 FAMILY
FIGURE 17-24: I2C™ MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS)
P
98765
D0D1D2D3D4D5D6D7
S
A7 A6 A5 A4 A3 A2 A1
SDA
SCL 1 23456 789 123456 78 9 123 4
Bus master
terminates
transfer
ACK
Receiving Data from Slave
Receiving Data from Slave
D0D1D2D3D4D5D6D7
ACK
R/W = 1
Transmit Address to Slave
SSPIF
BF
ACK is not sent
Write to SSPCON2<0> (SEN = 1),
Write to SSPBUF occurs here, ACK from Slave
Master configured as a receiver
by programming SSPCON2<3> (RCEN = 1)
PEN bit = 1
written here
Data shifted in on falling edge of CLK
Cleared in software
start XMIT
SEN = 0
SSPOV
SDA = 0, SCL = 1
while CPU
(SSPSTAT<0>)
ACK
Cleared in software
Cleared in software
Set SSPIF interrupt
at end of receive
Set P bit
(SSPSTAT<4>)
and SSPIF
ACK from Master,
Set SSPIF at end
Set SSPIF interrupt
at end of Acknowledge
sequence
Set SSPIF interrupt
at end of Acknowledge
sequence
of receive
Set ACKEN, start Acknowledge sequence,
SDA = ACKDT = 1
RCEN cleared
automatically
RCEN = 1, start
next receive
Write to SSPCON2<4>
to start Acknowledge sequence,
SDA = ACKDT (SSPCON2<5>) = 0
RCEN cleared
automatically
ACKEN
begin Start condition
Cleared in software
SDA = ACKDT = 0
Last bit is shifted into SSPSR and
contents are unloaded into SSPBUF
Cleared in
software
SSPOV is set because
SSPBUF is still full
responds to SSPIF
PIC18F85J90 FAMILY
DS39770C-page 228 2010 Microchip Technology Inc.
17.4.12 ACKNOWLEDGE SEQUENCE
TIMING
An Acknowledge sequence is enabled by setting the
Acknowledge Sequence Enable bit, ACKEN
(SSPCON2<4>). When this bit is set, the SCL pin is
pulled low and the contents of the Acknowledge data bit
are presented on the SDA pin. If the user wishes to gen-
erate an Acknowledge, then the ACKDT bit should be
cleared. If not, the user should set the ACKDT bit before
starting an Acknowledge sequence. The Baud Rate
Generator then counts for one rollover period (TBRG)
and the SCL pin is deasserted (pulled high). When the
SCL pin is sampled high (clock arbitration), the Baud
Rate Generator counts for TBRG. The SCL pin is then
pulled low. Following this, the ACKEN bit is automatically
cleared, the Baud Rate Generator is turned off and the
MSSP module then goes into Idle mode (Figure 17-25).
17.4.12.1 WCOL Status Flag
If the user writes the SSPBUF when an Acknowledge
sequence is in progress, then WCOL is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
17.4.13 STOP CONDITION TIMING
A Stop bit is asserted on the SDA pin at the end of a
receive/transmit by setting the Stop Sequence Enable
bit, PEN (SSPCON2<2>). At the end of a
receive/transmit, the SCL line is held low after the fall-
ing edge of the ninth clock. When the PEN bit is set, the
master will assert the SDA line low. When the SDA line
is sampled low, the Baud Rate Generator is reloaded
and counts down to 0. When the Baud Rate Generator
times out, the SCL pin will be brought high and one
TBRG (Baud Rate Generator rollover count) later, the
SDA pin will be deasserted. When the SDA pin is
sampled high while SCL is high, the P bit
(SSPSTAT<4>) is set. A TBRG later, the PEN bit is
cleared and the SSPIF bit is set (Figure 17-26).
17.4.13.1 WCOL Status Flag
If the user writes the SSPBUF when a Stop sequence
is in progress, then the WCOL bit is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
FIGURE 17-25: ACKNOWLEDGE SEQUENCE WAVEFORM
FIGURE 17-26: STOP CONDITION RECEIVE OR TRANSMIT MODE
Note: TBRG = one Baud Rate Generator period.
SDA
SCL
SSPIF set at
Acknowledge sequence starts here,
write to SSPCON2, ACKEN automatically cleared
Cleared in
TBRG TBRG
the end of receive
8
ACKEN = 1, ACKDT = 0
D0
9
SSPIF
software SSPIF set at the end
of Acknowledge sequence
Cleared in
software
ACK
SCL
SDA
SDA asserted low before rising edge of clock
Write to SSPCON2,
set PEN
Falling edge of
SCL = 1 for TBRG, followed by SDA = 1 for TBRG
9th clock
SCL brought high after TBRG
Note: TBRG = one Baud Rate Generator period.
TBRG TBRG
after SDA sampled high. P bit (SSPSTAT<4>) is set.
TBRG
to setup Stop condition
ACK
P
TBRG
PEN bit (SSPCON2<2>) is cleared by
hardware and the SSPIF bit is set
2010 Microchip Technology Inc. DS39770C-page 229
PIC18F85J90 FAMILY
17.4.14 SLEEP OPERATION
While in Sleep mode, the I2C module can receive
addresses or data and when an address match or
complete byte transfer occurs, wake the processor
from Sleep (if the MSSP interrupt is enabled).
17.4.15 EFFECTS OF A RESET
A Reset disables the MSSP module and terminates the
current transfer.
17.4.16 MULTI-MASTER MODE
In Multi-Master mode, the interrupt generation on the
detection of the Start and Stop conditions allows the
determination of when the bus is free. The Stop (P) and
Start (S) bits are cleared from a Reset or when the
MSSP module is disabled. Control of the I2C bus may
be taken when the P bit (SSPSTAT<4>) is set, or the
bus is Idle, with both the S and P bits clear. When the
bus is busy, enabling the MSSP interrupt will generate
the interrupt when the Stop condition occurs.
In multi-master operation, the SDA line must be
monitored for arbitration to see if the signal level is the
expected output level. This check is performed in
hardware with the result placed in the BCLIF bit.
The states where arbitration can be lost are:
• Address Transfer
• Data Transfer
• A Start Condition
• A Repeated Start Condition
• An Acknowledge Condition
17.4.17 MULTI -MASTER COMMUNICATION,
BUS COLLISION AND BUS
ARBITRATION
Multi-Master mode support is achieved by bus arbitra-
tion. When the master outputs address/data bits onto
the SDA pin, arbitration takes place when the master
outputs a ‘1’ on SDA by letting SDA float high, and
another master asserts a ‘0’. When the SCL pin floats
high, data should be stable. If the expected data on
SDA is a ‘1’ and the data sampled on the SDA pin = 0,
then a bus collision has taken place. The master will set
the Bus Collision Interrupt Flag, BCLIF and reset the
I2C port to its Idle state (Figure 17-27).
If a transmit was in progress when the bus collision
occurred, the transmission is halted, the BF flag is
cleared, the SDA and SCL lines are deasserted and the
SSPBUF can be written to. When the user services the
bus collision Interrupt Service Routine and if the I2C bus
is free, the user can resume communication by asserting
a Start condition.
If a Start, Repeated Start, Stop or Acknowledge condition
was in progress when the bus collision occurred, the
condition is aborted, the SDA and SCL lines are
deasserted and the respective control bits in the
SSPCON2 register are cleared. When the user services
the bus collision Interrupt Service Routine and if the I2C
bus is free, the user can resume communication by
asserting a Start condition.
The master will continue to monitor the SDA and SCL
pins. If a Stop condition occurs, the SSPIF bit will be set.
A write to the SSPBUF will start the transmission of
data at the first data bit regardless of where the
transmitter left off when the bus collision occurred.
In Multi-Master mode, the interrupt generation on the
detection of Start and Stop conditions allows the determi-
nation of when the bus is free. Control of the I2C bus can
be taken when the P bit is set in the SSPSTAT register, or
the bus is Idle and the S and P bits are cleared.
FIGURE 17-27: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE
SDA
SCL
BCLIF
SDA released
SDA line pulled low
by another source
Sample SDA. While SCL is high,
data doesn’t match what is driven
Bus collision has occurred.
Set Bus Collision
Interrupt (BCLIF)
by the master.
by master
Data changes
while SCL = 0
PIC18F85J90 FAMILY
DS39770C-page 230 2010 Microchip Technology Inc.
17.4.17.1 Bus Collision During a Start
Condition
During a Start condition, a bus collision occurs if:
a) SDA or SCL are sampled low at the beginning of
the Start condition (Figure 17-28).
b) SCL is sampled low before SDA is asserted low
(Figure 17-29).
During a Start condition, both the SDA and the SCL
pins are monitored.
If the SDA pin is already low, or the SCL pin is already
low, then all of the following occur:
• the Start condition is aborted;
• the BCLIF flag is set; and
• the MSSP module is reset to its Idle state
(Figure 17-28).
The Start condition begins with the SDA and SCL pins
deasserted. When the SDA pin is sampled high, the
Baud Rate Generator is loaded from SSPADD<6:0>
and counts down to 0. If the SCL pin is sampled low
while SDA is high, a bus collision occurs, because it is
assumed that another master is attempting to drive a
data ‘1’ during the Start condition.
If the SDA pin is sampled low during this count, the
BRG is reset and the SDA line is asserted early
(Figure 17-30). If, however, a ‘1’ is sampled on the SDA
pin, the SDA pin is asserted low at the end of the BRG
count. The Baud Rate Generator is then reloaded and
counts down to 0. If the SCL pin is sampled as ‘0’
during this time, a bus collision does not occur. At the
end of the BRG count, the SCL pin is asserted low.
FIGURE 17-28: BUS COLLISION DURING START CONDITION (SDA ONLY)
Note: The reason that bus collision is not a factor
during a Start condition is that no two bus
masters can assert a Start condition at the
exact same time. Therefore, one master
will always assert SDA before the other.
This condition does not cause a bus colli-
sion because the two masters must be
allowed to arbitrate the first address
following the Start condition. If the address
is the same, arbitration must be allowed to
continue into the data portion, Repeated
Start or Stop conditions.
SDA
SCL
SEN
SDA sampled low before
SDA goes low before the SEN bit is set.
S bit and SSPIF set because
MSSP module reset into Idle state.
SEN cleared automatically because of bus collision.
S bit and SSPIF set because
Set SEN, enable Start
condition if SDA = 1, SCL = 1
SDA = 0, SCL = 1.
BCLIF
SSPIF
SDA = 0, SCL = 1.
SSPIF and BCLIF are
cleared in software
SSPIF and BCLIF are
cleared in software
Set BCLIF,
Start condition. Set BCLIF.
S
2010 Microchip Technology Inc. DS39770C-page 231
PIC18F85J90 FAMILY
FIGURE 17-29: BUS COLLISION DURING START CONDITION (SCL = 0)
FIGURE 17-30: BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION
SDA
SCL
SEN bus collision occurs. Set BCLIF.
SCL = 0 before SDA = 0,
Set SEN, enable Start
sequence if SDA = 1, SCL = 1
TBRG TBRG
SDA = 0, SCL = 1
BCLIF
S
SSPIF
Interrupt cleared
in software
bus collision occurs. Set BCLIF.
SCL = 0 before BRG time-out,
‘0’‘0’
‘0’‘0’
SDA
SCL
SEN
Set S
Less than TBRG TBRG
SDA = 0, SCL = 1
BCLIF
S
SSPIF
S
Interrupts cleared
in software
set SSPIF
SDA = 0, SCL = 1,
SCL pulled low after BRG
time-out
Set SSPIF
‘0’
SDA pulled low by other master.
Reset BRG and assert SDA.
Set SEN, enable Start
sequence if SDA = 1, SCL = 1
PIC18F85J90 FAMILY
DS39770C-page 232 2010 Microchip Technology Inc.
17.4.17.2 Bus Collision During a Repeated
Start Condition
During a Repeated Start condition, a bus collision
occurs if:
a) A low level is sampled on SDA when SCL goes
from low level to high level.
b) SCL goes low before SDA is asserted low,
indicating that another master is attempting to
transmit a data ‘1’.
When the user deasserts SDA and the pin is allowed to
float high, the BRG is loaded with SSPADD<6:0> and
counts down to 0. The SCL pin is then deasserted and
when sampled high, the SDA pin is sampled.
If SDA is low, a bus collision has occurred (i.e., another
master is attempting to transmit a data ‘0’, see
Figure 17-31). If SDA is sampled high, the BRG is
reloaded and begins counting. If SDA goes from
high-to-low before the BRG times out, no bus collision
occurs because no two masters can assert SDA at
exactly the same time.
If SCL goes from high-to-low before the BRG times out
and SDA has not already been asserted, a bus collision
occurs. In this case, another master is attempting to
transmit a data ‘1’ during the Repeated Start condition
(see Figure 17-32).
If, at the end of the BRG time-out, both SCL and SDA
are still high, the SDA pin is driven low and the BRG is
reloaded and begins counting. At the end of the count,
regardless of the status of the SCL pin, the SCL pin is
driven low and the Repeated Start condition is complete.
FIGURE 17-31: BUS COLLISION DURING A REPEATED START CONDITION (CASE 1)
FIGURE 17-32: BUS COLLISION DURING REPEATED START CONDITION (CASE 2)
SDA
SCL
RSEN
BCLIF
S
SSPIF
Sample SDA when SCL goes high.
If SDA = 0, set BCLIF and release SDA and SCL.
Cleared in software
‘0’
‘0’
SDA
SCL
BCLIF
RSEN
S
SSPIF
Interrupt cleared
in software
SCL goes low before SDA,
set BCLIF. Release SDA and SCL.
TBRG TBRG
‘0’
2010 Microchip Technology Inc. DS39770C-page 233
PIC18F85J90 FAMILY
17.4.17.3 Bus Collision During a Stop
Condition
Bus collision occurs during a Stop condition if:
a) After the SDA pin has been deasserted and
allowed to float high, SDA is sampled low after
the BRG has timed out.
b) After the SCL pin is deasserted, SCL is sampled
low before SDA goes high.
The Stop condition begins with SDA asserted low.
When SDA is sampled low, the SCL pin is allowed to
float. When the pin is sampled high (clock arbitration),
the Baud Rate Generator is loaded with SSPADD<6:0>
and counts down to 0. After the BRG times out, SDA is
sampled. If SDA is sampled low, a bus collision has
occurred. This is due to another master attempting to
drive a data ‘0’ (Figure 17-33). If the SCL pin is
sampled low before SDA is allowed to float high, a bus
collision occurs. This is another case of another master
attempting to drive a data ‘0’ (Figure 17-34).
FIGURE 17-33: BUS COLLISION DURING A STOP CONDITION (CASE 1)
FIGURE 17-34: BUS COLLISION DURING A STOP CONDITION (CASE 2)
SDA
SCL
BCLIF
PEN
P
SSPIF
TBRG TBRG TBRG
SDA asserted low
SDA sampled
low after TBRG,
set BCLIF
‘0’
‘0’
SDA
SCL
BCLIF
PEN
P
SSPIF
TBRG TBRG TBRG
Assert SDA SCL goes low before SDA goes high,
set BCLIF
‘0’
‘0’
PIC18F85J90 FAMILY
DS39770C-page 234 2010 Microchip Technology Inc.
TABLE 17-4: REGISTERS ASSOCIATED WITH I2C™ OPERATION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on Page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 57
PIR1 —ADIF RC1IF TX1IF SSPIF —TMR2IF TMR1IF 60
PIE1 —ADIE RC1IE TX1IE SSPIE —TMR2IE TMR1IE 60
IPR1 —ADIP RC1IP TX1IP SSPIP —TMR2IP TMR1IP 60
PIR2 OSCFIF CMIF ——BCLIFLVDIF TMR3IF —60
PIE2 OSCFIE CMIE — —BCLIELVDIE TMR3IE —60
IPR2 OSCFIP CMIP — —BCLIPLVDIP TMR3IP —60
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 60
SSPBUF MSSP Receive Buffer/Transmit Register 58
SSPADD MSSP Address Register (I2C™ Slave mode),
MSSP Baud Rate Reload Register (I2C Master mode)
58
SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 58
SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 58
GCEN ACKSTAT ADMSK5(1) ADMSK4(1) ADMSK3(1) ADMSK2(1) ADMSK1(1) SEN
SSPSTAT SMP CKE D/A PSR/WUA BF 58
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the MSSP module in I2C™ mode.
Note 1: Alternate bit definitions for use in I2C Slave mode operations only.
2010 Microchip Technology Inc. DS39770C-page 235
PIC18F85J90 FAMILY
18.0 ENHANCED UNIVERSAL
SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (EUSART)
PIC18F85J90 family devices have three serial I/O mod-
ules: the MSSP module, discussed in the previous
chapter and two Universal Synchronous Asynchronous
Receiver Transmitter (USART) modules. (Generically,
the USART is also known as a Serial Communications
Interface or SCI.) The USART can be configured as a
full-duplex, asynchronous system that can communi-
cate with peripheral devices, such as CRT terminals
and personal computers. It can also be configured as a
half-duplex synchronous system that can communicate
with peripheral devices, such as A/D or D/A integrated
circuits, serial EEPROMs, etc.
There are two distinct implementations of the USART
module in these devices: the Enhanced USART
(EUSART) discussed here and the Addressable
USART discussed in the next chapter. For this device
family, USART1 always refers to the EUSART, while
USART2 is always the AUSART.
The EUSART and AUSART modules implement the
same core features for serial communications; their
basic operation is essentially the same. The EUSART
module provides additional features, including Auto-
matic Baud Rate Detection and calibration, automatic
wake-up on Sync Break reception and 12-bit Break
character transmit. These features make it ideally
suited for use in Local Interconnect Network bus
(LIN/J2602 bus) systems.
The EUSART can be configured in the following
modes:
• Asynchronous (full-duplex) with:
- Auto-wake-up on character reception
- Auto-baud calibration
- 12-bit Break character transmission
• Synchronous – Master (half-duplex) with
selectable clock polarity
• Synchronous – Slave (half-duplex) with selectable
clock polarity
The pins of the EUSART are multiplexed with the
functions of PORTC (RC6/TX1/CK1/SEG27 and
RC7/RX1/DT1/SEG28). In order to configure these
pins as an EUSART:
• bit, SPEN (RCSTA1<7>), must be set (= 1)
• bit, TRISC<7>, must be set (= 1)
• bit, TRISC<6>, must be set (= 1)
The driver for the TX1 output pin can also be optionally
configured as an open-drain output. This feature allows
the voltage level on the pin to be pulled to a higher level
through an external pull-up resistor, and allows the out-
put to communicate with external circuits without the
need for additional level shifters.
The open-drain output option is controlled by the U1OD
bit (LATG<6>). Setting the bit configures the pin for
open-drain operation.
18.1 Control Registers
The operation of the Enhanced USART module is
controlled through three registers:
• Transmit Status and Control Register 1 (TXSTA1)
• Receive Status and Control Register 1 (RCSTA1)
• Baud Rate Control Register 1 (BAUDCON1)
The registers are described in Register 18-1,
Register 18-2 and Register 18-3.
Note: The EUSART control will automatically
reconfigure the pin from input to output as
needed.
PIC18F85J90 FAMILY
DS39770C-page 236 2010 Microchip Technology Inc.
REGISTER 18-1: TXSTA1: EUSART TRANSMIT STATUS AND CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-1 R/W-0
CSRC TX9 TXEN(1) SYNC SENDB BRGH TRMT TX9D
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 CSRC: Clock Source Select bit
Asynchronous mode:
Don’t care.
Synchronous mode:
1 = Master mode (clock generated internally from BRG)
0 = Slave mode (clock from external source)
bit 6 TX9: 9-Bit Transmit Enable bit
1 = Selects 9-bit transmission
0 = Selects 8-bit transmission
bit 5 TXEN: Transmit Enable bit(1)
1 = Transmit enabled
0 = Transmit disabled
bit 4 SYNC: AUSART Mode Select bit
1 = Synchronous mode
0 = Asynchronous mode
bit 3 SENDB: Send Break Character bit
Asynchronous mode:
1 = Send Sync Break on next transmission (cleared by hardware upon completion)
0 = Sync Break transmission completed
Synchronous mode:
Don’t care.
bit 2 BRGH: High Baud Rate Select bit
Asynchronous mode:
1 = High speed
0 = Low speed
Synchronous mode:
Unused in this mode.
bit 1 TRMT: Transmit Shift Register Status bit
1 = TSR empty
0 = TSR full
bit 0 TX9D: 9th bit of Transmit Data
Can be address/data bit or a parity bit.
Note 1: SREN/CREN overrides TXEN in Sync mode.
2010 Microchip Technology Inc. DS39770C-page 237
PIC18F85J90 FAMILY
REGISTER 18-2: RCSTA1: EUSART RECEIVE STATUS AND CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x
SPEN RX9 SREN CREN ADDEN FERR OERR RX9D
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 SPEN: Serial Port Enable bit
1 = Serial port enabled
0 = Serial port disabled (held in Reset)
bit 6 RX9: 9-Bit Receive Enable bit
1 = Selects 9-bit reception
0 = Selects 8-bit reception
bit 5 SREN: Single Receive Enable bit
Asynchronous mode:
Don’t care.
Synchronous mode – Master:
1 = Enables single receive
0 = Disables single receive
This bit is cleared after reception is complete.
Synchronous mode – Slave:
Don’t care.
bit 4 CREN: Continuous Receive Enable bit
Asynchronous mode:
1 = Enables receiver
0 = Disables receiver
Synchronous mode:
1 = Enables continuous receive until enable bit, CREN, is cleared (CREN overrides SREN)
0 = Disables continuous receive
bit 3 ADDEN: Address Detect Enable bit
Asynchronous mode 9-bit (RX9 = 1):
1 = Enables address detection, enables interrupt and loads the receive buffer when RSR<8> is set
0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit
Asynchronous mode 9-bit (RX9 = 0):
Don’t care.
bit 2 FERR: Framing Error bit
1 = Framing error (can be cleared by reading RCREG1 register and receiving the next valid byte)
0 = No framing error
bit 1 OERR: Overrun Error bit
1 = Overrun error (can be cleared by clearing bit, CREN)
0 = No overrun error
bit 0 RX9D: 9th bit of Received Data
This can be an address/data bit or a parity bit and must be calculated by user firmware.
PIC18F85J90 FAMILY
DS39770C-page 238 2010 Microchip Technology Inc.
REGISTER 18-3: BAUDCON1: BAUD RATE CONTROL REGISTER 1
R/W-0 R-1 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0
ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 ABDOVF: Auto-Baud Acquisition Rollover Status bit
1 = A BRG rollover has occurred during Auto-Baud Rate Detect mode (must be cleared in software)
0 = No BRG rollover has occurred
bit 6 RCIDL: Receive Operation Idle Status bit
1 = Receive operation is Idle
0 = Receive operation is active
bit 5 RXDTP: Received Data Polarity Select bit (Asynchronous mode only)
Asynchronous mode:
1 = RX data is inverted
0 = RX data received is not inverted
bit 4 TXCKP: Clock and Data Polarity Select bit
Asynchronous mode:
1 = Idle state for transmit (TX) is a low level
0 = Idle state for transmit (TX) is a high level
Synchronous mode:
1 = Idle state for clock (CK) is a high level
0 = Idle state for clock (CK) is a low level
bit 3 BRG16: 16-Bit Baud Rate Register Enable bit
1 = 16-bit Baud Rate Generator – SPBRGH1 and SPBRG1
0 = 8-bit Baud Rate Generator – SPBRG1 only (Compatible mode), SPBRGH1 value ignored
bit 2 Unimplemented: Read as ‘0’
bit 1 WUE: Wake-up Enable bit
Asynchronous mode:
1 = EUSART will continue to sample the RX1 pin – interrupt generated on falling edge; bit cleared in
hardware on following rising edge
0 = RX1 pin not monitored or rising edge detected
Synchronous mode:
Unused in this mode.
bit 0 ABDEN: Auto-Baud Detect Enable bit
Asynchronous mode:
1 = Enable baud rate measurement on the next character. Requires reception of a Sync field (55h);
cleared in hardware upon completion.
0 = Baud rate measurement disabled or completed
Synchronous mode:
Unused in this mode.
2010 Microchip Technology Inc. DS39770C-page 239
PIC18F85J90 FAMILY
18.2 EUSART Baud Rate Generator
(BRG)
The BRG is a dedicated, 8-bit or 16-bit generator that
supports both the Asynchronous and Synchronous
modes of the EUSART. By default, the BRG operates
in 8-bit mode; setting the BRG16 bit (BAUDCON1<3>)
selects 16-bit mode.
The SPBRGH1:SPBRG1 register pair controls the
period of a free-running timer. In Asynchronous mode,
BRGH (TXSTA1<2>) and BRG16 (BAUDCON1<3>) bits
also control the baud rate. In Synchronous mode, BRGH
is ignored. Table 18-1 shows the formula for computa-
tion of the baud rate for different EUSART modes that
only apply in Master mode (internally generated clock).
Given the desired baud rate and FOSC, the nearest
integer value for the SPBRGH1:SPBRG1 registers can
be calculated using the formulas in Table 18-1. From this,
the error in baud rate can be determined. An example
calculation is shown in Example 18-1. Typical baud rates
and error values for the various Asynchronous modes
are shown in Table 18-2. It may be advantageous to use
the high baud rate (BRGH = 1) or the 16-bit BRG to
reduce the baud rate error, or achieve a slow baud rate
for a fast oscillator frequency.
Writing a new value to the SPBRGH1:SPBRG1 registers
causes the BRG timer to be reset (or cleared). This
ensures the BRG does not wait for a timer overflow
before outputting the new baud rate. When operated in
the Synchronous mode, SPBRGH:SPBRG values of
0000h and 0001h are not supported. In the
Asynchronous mode, all BRG values may be used.
18.2.1 OPERATION IN POWER-MANAGED
MODES
The device clock is used to generate the desired baud
rate. When one of the power-managed modes is
entered, the new clock source may be operating at a
different frequency. This may require an adjustment to
the value in the SPBRG1 register pair.
18.2.2 SAMPLING
The data on the RX1 pin is sampled three times by a
majority detect circuit to determine if a high or a low
level is present at the RX1 pin.
TABLE 18-1: BAUD RATE FORMULAS
Configuration Bits BRG/EUSART Mode Baud Rate Formula
SYNC BRG16 BRGH
000 8-bit/Asynchronous FOSC/[64 (n + 1)]
001 8-bit/Asynchronous FOSC/[16 (n + 1)]
010 16-bit/Asynchronous
011 16-bit/Asynchronous
FOSC/[4 (n + 1)]10x 8-bit/Synchronous
11x 16-bit/Synchronous
Legend: x = Don’t care, n = Value of SPBRGH1:SPBRG1 register pair
PIC18F85J90 FAMILY
DS39770C-page 240 2010 Microchip Technology Inc.
EXAMPLE 18-1: CALCULATING BAUD RATE ERROR
TABLE 18-2: REGISTERS ASSOCIATED WITH THE BAUD RATE GENERATOR
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values
on Page
TXSTA1 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 59
RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 59
BAUDCON1 ABDOVF RCIDL RXDTP TXCKP BRG16 —WUE ABDEN 61
SPBRGH1 EUSART Baud Rate Generator Register High Byte 61
SPBRG1 EUSART Baud Rate Generator Register Low Byte 59
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the BRG.
For a device with FOSC of 16 MHz, desired baud rate of 9600, Asynchronous mode, 8-bit BRG:
Desired Baud Rate = FOSC/(64 ([SPBRGH1:SPBRG1] + 1))
Solving for SPBRGH1:SPBRG1:
X = ((FOSC/Desired Baud Rate)/64) – 1
= ((16000000/9600)/64) – 1
= [25.042] = 25
Calculated Baud Rate = 16000000/(64 (25 + 1))
= 9615
Error = (Calculated Baud Rate – Desired Baud Rate)/Desired Baud Rate
= (9615 – 9600)/9600 = 0.16%
2010 Microchip Technology Inc. DS39770C-page 241
PIC18F85J90 FAMILY
TABLE 18-3: BAUD RATES FOR ASYNCHRONOUS MODES
BAUD
RATE
(K)
SYNC = 0, BRGH = 0, BRG16 = 0
FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz FOSC = 8.000 MHz
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
0.3————————————
1.2 — — — 1.221 1.73 255 1.202 0.16 129 1.201 -0.16 103
2.4 2.441 1.73 255 2.404 0.16 129 2.404 0.16 64 2.403 -0.16 51
9.6 9.615 0.16 64 9.766 1.73 31 9.766 1.73 15 9.615 -0.16 12
19.2 19.531 1.73 31 19.531 1.73 15 19.531 1.73 7 — — —
57.6 56.818 -1.36 10 62.500 8.51 4 52.083 -9.58 2 — — —
115.2 125.000 8.51 4 104.167 -9.58 2 78.125 -32.18 1 — — —
BAUD
RATE
(K)
SYNC = 0, BRGH = 0, BRG16 = 0
FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
0.3 0.300 0.16 207 0.300 -0.16 103 0.300 -0.16 51
1.2 1.202 0.16 51 1.201 -0.16 25 1.201 -0.16 12
2.4 2.404 0.16 25 2.403 -0.16 12 — — —
9.6 8.929 -6.99 6 — — — — — —
19.2 20.833 8.51 2 — — — — — —
57.6 62.500 8.51 0 — — — — — —
115.2 62.500 -45.75 0 — — — — — —
BAUD
RATE
(K)
SYNC = 0, BRGH = 1, BRG16 = 0
FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz FOSC = 8.000 MHz
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
0.3————————————
1.2————————————
2.4 — — — — — — 2.441 1.73 255 2.403 -0.16 207
9.6 9.766 1.73 255 9.615 0.16 129 9.615 0.16 64 9.615 -0.16 51
19.2 19.231 0.16 129 19.231 0.16 64 19.531 1.73 31 19.230 -0.16 25
57.6 58.140 0.94 42 56.818 -1.36 21 56.818 -1.36 10 55.555 3.55 8
115.2 113.636 -1.36 21 113.636 -1.36 10 125.000 8.51 4 — — —
BAUD
RATE
(K)
SYNC = 0, BRGH = 1, BRG16 = 0
FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
0.3 — — — — — — 0.300 -0.16 207
1.2 1.202 0.16 207 1.201 -0.16 103 1.201 -0.16 51
2.4 2.404 0.16 103 2.403 -0.16 51 2.403 -0.16 25
9.6 9.615 0.16 25 9.615 -0.16 12 — — —
19.2 19.231 0.16 12 — — — — — —
57.6 62.500 8.51 3 — — — — — —
115.2 125.000 8.51 1 — — — — — —
PIC18F85J90 FAMILY
DS39770C-page 242 2010 Microchip Technology Inc.
BAUD
RATE
(K)
SYNC = 0, BRGH = 0, BRG16 = 1
FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz FOSC = 8.000 MHz
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
0.3 0.300 0.00 8332 0.300 0.02 4165 0.300 0.02 2082 0.300 -0.04 1665
1.2 1.200 0.02 2082 1.200 -0.03 1041 1.200 -0.03 520 1.201 -0.16 415
2.4 2.402 0.06 1040 2.399 -0.03 520 2.404 0.16 259 2.403 -0.16 207
9.6 9.615 0.16 259 9.615 0.16 129 9.615 0.16 64 9.615 -0.16 51
19.2 19.231 0.16 129 19.231 0.16 64 19.531 1.73 31 19.230 -0.16 25
57.6 58.140 0.94 42 56.818 -1.36 21 56.818 -1.36 10 55.555 3.55 8
115.2 113.636 -1.36 21 113.636 -1.36 10 125.000 8.51 4 — — —
BAUD
RATE
(K)
SYNC = 0, BRGH = 0, BRG16 = 1
FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
0.3 0.300 0.04 832 0.300 -0.16 415 0.300 -0.16 207
1.2 1.202 0.16 207 1.201 -0.16 103 1.201 -0.16 51
2.4 2.404 0.16 103 2.403 -0.16 51 2.403 -0.16 25
9.6 9.615 0.16 25 9.615 -0.16 12 — — —
19.2 19.231 0.16 12 — — — — — —
57.6 62.500 8.51 3 — — — — — —
115.2 125.000 8.51 1 — — — — — —
BAUD
RATE
(K)
SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1
FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz FOSC = 8.000 MHz
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
0.3 0.300 0.00 33332 0.300 0.00 16665 0.300 0.00 8332 0.300 -0.01 6665
1.2 1.200 0.00 8332 1.200 0.02 4165 1.200 0.02 2082 1.200 -0.04 1665
2.4 2.400 0.02 4165 2.400 0.02 2082 2.402 0.06 1040 2.400 -0.04 832
9.6 9.606 0.06 1040 9.596 -0.03 520 9.615 0.16 259 9.615 -0.16 207
19.2 19.193 -0.03 520 19.231 0.16 259 19.231 0.16 129 19.230 -0.16 103
57.6 57.803 0.35 172 57.471 -0.22 86 58.140 0.94 42 57.142 0.79 34
115.2 114.943 -0.22 86 116.279 0.94 42 113.636 -1.36 21 117.647 -2.12 16
BAUD
RATE
(K)
SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1
FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
0.3 0.300 0.01 3332 0.300 -0.04 1665 0.300 -0.04 832
1.2 1.200 0.04 832 1.201 -0.16 415 1.201 -0.16 207
2.4 2.404 0.16 415 2.403 -0.16 207 2.403 -0.16 103
9.6 9.615 0.16 103 9.615 -0.16 51 9.615 -0.16 25
19.2 19.231 0.16 51 19.230 -0.16 25 19.230 -0.16 12
57.6 58.824 2.12 16 55.555 3.55 8 — — —
115.2 111.111 -3.55 8 — — — — — —
TABLE 18-3: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)
2010 Microchip Technology Inc. DS39770C-page 243
PIC18F85J90 FAMILY
18.2.3 AUTO-BAUD RATE DETECT
The Enhanced USART module supports the automatic
detection and calibration of baud rate. This feature is
active only in Asynchronous mode and while the WUE
bit is clear.
The automatic baud rate measurement sequence
(Figure 18-1) begins whenever a Start bit is received
and the ABDEN bit is set. The calculation is
self-averaging.
In the Auto-Baud Rate Detect (ABD) mode, the clock to
the BRG is reversed. Rather than the BRG clocking the
incoming RX1 signal, the RX1 signal is timing the BRG.
In ABD mode, the internal Baud Rate Generator is
used as a counter to time the bit period of the incoming
serial byte stream.
Once the ABDEN bit is set, the state machine will clear
the BRG and look for a Start bit. The Auto-Baud Rate
Detect must receive a byte with the value, 55h (ASCII
“U”, which is also the LIN/J2602 bus Sync character), in
order to calculate the proper bit rate. The measurement
is taken over both a low and a high bit time in order to
minimize any effects caused by asymmetry of the
incoming signal. After a Start bit, the SPBRG1 begins
counting up, using the preselected clock source on the
first rising edge of RX1. After eight bits on the RX1 pin
or the fifth rising edge, an accumulated value totalling
the proper BRG period is left in the
SPBRGH1:SPBRG1 register pair. Once the 5th edge is
seen (this should correspond to the Stop bit), the
ABDEN bit is automatically cleared.
If a rollover of the BRG occurs (an overflow from FFFFh
to 0000h), the event is trapped by the ABDOVF status bit
(BAUDCON1<7>). It is set in hardware by BRG rollovers
and can be set or cleared by the user in software. ABD
mode remains active after rollover events and the
ABDEN bit remains set (Figure 18-2).
While calibrating the baud rate period, the BRG regis-
ters are clocked at 1/8th the preconfigured clock rate.
Note that the BRG clock can be configured by the
BRG16 and BRGH bits. The BRG16 bit must be set to
use both SPBRG1 and SPBRGH1 as a 16-bit counter.
This allows the user to verify that no carry occurred for
8-bit modes by checking for 00h in the SPBRGH1 reg-
ister. Refer to Table 18-4 for counter clock rates to the
BRG.
While the ABD sequence takes place, the EUSART
state machine is held in Idle. The RC1IF interrupt is set
once the fifth rising edge on RX1 is detected. The value
in the RCREG1 needs to be read to clear the RC1IF
interrupt. The contents of RCREG1 should be
discarded.
TABLE 18-4: BRG COUNTER CLOCK
RATES
18.2.3.1 ABD and EUSART Transmission
Since the BRG clock is reversed during ABD acquisi-
tion, the EUSART transmitter cannot be used during
ABD. This means that whenever the ABDEN bit is set,
TXREG1 cannot be written to. Users should also
ensure that ABDEN does not become set during a
transmit sequence. Failing to do this may result in
unpredictable EUSART operation.
Note 1: If the WUE bit is set with the ABDEN bit,
Auto-Baud Rate Detection will occur on
the byte following the Break character.
2: It is up to the user to determine that the
incoming character baud rate is within the
range of the selected BRG clock source.
Some combinations of oscillator frequency
and EUSART baud rates are not possible
due to bit error rates. Overall system
timing and communication baud rates
must be taken into consideration when
using the Auto-Baud Rate Detection
feature.
BRG16 BRGH BRG Counter Clock
00 FOSC/512
01 FOSC/128
10 FOSC/128
11 FOSC/32
Note: During the ABD sequence, SPBRG1 and
SPBRGH1 are both used as a 16-bit
counter, independent of the BRG16 setting.
PIC18F85J90 FAMILY
DS39770C-page 244 2010 Microchip Technology Inc.
FIGURE 18-1: AUTOMATIC BAUD RATE CALCULATION
FIGURE 18-2: BRG OVERFLOW SEQUENCE
BRG Value
RX1 pin
ABDEN bit
RC1IF bit
bit 0 bit 1
(Interrupt)
Read
RCREG1
BRG Clock
Start
Auto-Cleared
Set by User
XXXXh 0000h
Edge #1
bit 2 bit 3
Edge #2
bit 4 bit 5
Edge #3
bit 6 bit 7
Edge #4
Stop bit
Edge #5
001Ch
Note: The ABD sequence requires the EUSART module to be configured in Asynchronous mode and WUE = 0.
SPBRG1 XXXXh 1Ch
SPBRGH1 XXXXh 00h
Start bit 0
XXXXh 0000h 0000h
FFFFh
BRG Clock
ABDEN bit
RX1 pin
ABDOVF bit
BRG Value
2010 Microchip Technology Inc. DS39770C-page 245
PIC18F85J90 FAMILY
18.3 EUSART Asynchronous Mode
The Asynchronous mode of operation is selected by
clearing the SYNC bit (TXSTA1<4>). In this mode, the
EUSART uses standard Non-Return-to-Zero (NRZ) for-
mat (one Start bit, eight or nine data bits and one Stop
bit). The most common data format is 8 bits. An on-chip
dedicated 8-bit/16-bit Baud Rate Generator can be
used to derive standard baud rate frequencies from the
oscillator.
The EUSART transmits and receives the LSb first. The
EUSART’s transmitter and receiver are functionally
independent, but use the same data format and baud
rate. The Baud Rate Generator produces a clock, either
x16 or x64 of the bit shift rate, depending on the BRGH
and BRG16 bits (TXSTA1<2> and BAUDCON1<3>).
Parity is not supported by the hardware but can be
implemented in software and stored as the 9th data bit.
When operating in Asynchronous mode, the EUSART
module consists of the following important elements:
• Baud Rate Generator
• Sampling Circuit
• Asynchronous Transmitter
• Asynchronous Receiver
• Auto-Wake-up on Sync Break Character
• 12-Bit Break Character Transmit
• Auto-Baud Rate Detection
18.3.1 EUSART ASYNCHRONOUS
TRANSMITTER
The EUSART transmitter block diagram is shown in
Figure 18-3. The heart of the transmitter is the Transmit
(Serial) Shift register (TSR). The Shift register obtains
its data from the Read/Write Transmit Buffer register,
TXREG1. The TXREG1 register is loaded with data in
software. The TSR register is not loaded until the Stop
bit has been transmitted from the previous load. As
soon as the Stop bit is transmitted, the TSR is loaded
with new data from the TXREG1 register (if available).
Once the TXREG1 register transfers the data to the
TSR register (occurs in one TCY), the TXREG1 register
is empty and the TX1IF flag bit (PIR1<4>) is set. This
interrupt can be enabled or disabled by setting or clear-
ing the interrupt enable bit, TX1IE (PIE1<4>). TX1IF
will be set regardless of the state of TX1IE; it cannot be
cleared in software. TX1IF is also not cleared immedi-
ately upon loading TXREG1, but becomes valid in the
second instruction cycle following the load instruction.
Polling TX1IF immediately following a load of TXREG1
will return invalid results.
While TX1IF indicates the status of the TXREG1 regis-
ter, another bit, TRMT (TXSTA1<1>), shows the status
of the TSR register. TRMT is a read-only bit which is set
when the TSR register is empty. No interrupt logic is
tied to this bit so the user has to poll this bit in order to
determine if the TSR register is empty.
To set up an Asynchronous Transmission:
1. Initialize the SPBRGH1:SPBRG1 registers for
the appropriate baud rate. Set or clear the
BRGH and BRG16 bits, as required, to achieve
the desired baud rate.
2. Enable the asynchronous serial port by clearing
bit, SYNC, and setting bit, SPEN.
3. If interrupts are desired, set enable bit, TX1IE.
4. If 9-bit transmission is desired, set transmit bit,
TX9; can be used as address/data bit.
5. Enable the transmission by setting bit, TXEN,
which will also set bit, TX1IF.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit, TX9D.
7. Load data to the TXREG1 register (starts
transmission).
8. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
FIGURE 18-3: EUSART TRANSMIT BLOCK DIAGRAM
Note 1: The TSR register is not mapped in data
memory so it is not available to the user.
2: Flag bit, TX1IF, is set when enable bit,
TXEN, is set.
TX1IF
TX1IE
Interrupt
TXEN Baud Rate CLK
SPBRG1
Baud Rate Generator TX9D
MSb LSb
Data Bus
TXREG1 Register
TSR Register
(8) 0
TX9
TRMT SPEN
TX1 pin
Pin Buffer
and Control
8
SPBRGH1
BRG16
PIC18F85J90 FAMILY
DS39770C-page 246 2010 Microchip Technology Inc.
FIGURE 18-4: ASYNCHRONOUS TRANSMISSION
FIGURE 18-5: ASYNCHRONOUS TRANSMISSION (BACK TO BACK)
TABLE 18-5: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on Page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 57
PIR1 —ADIF RC1IF TX1IF SSPIF —TMR2IF TMR1IF 60
PIE1 —ADIE RC1IE TX1IE SSPIE —TMR2IE TMR1IE 60
IPR1 —ADIP RC1IP TX1IP SSPIP —TMR2IP TMR1IP 60
RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 59
TXREG1 EUSART Transmit Register 59
TXSTA1 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 59
BAUDCON1 ABDOVF RCIDL RXDTP TXCKP BRG16 —WUE ABDEN 61
SPBRGH1 EUSART Baud Rate Generator Register High Byte 61
SPBRG1 EUSART Baud Rate Generator Register Low Byte 59
LATG U2OD U1OD —LATG4 LATG3 LATG2 LATG1 LATG0 60
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous transmission.
Word 1
Word 1
Transmit Shift Reg
Start bit bit 0 bit 1 bit 7/8
Write to TXREG1
BRG Output
(Shift Clock)
TX1 (pin)
TX1IF bit
(Transmit Buffer
Reg. Empty Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
1 TCY
Word 1
Stop bit
Transmit Shift Reg.
Write to TXREG1
BRG Output
(Shift Clock)
TX1 (pin)
TX1IF bit
(Interrupt Reg. Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
Word 1 Word 2
Word 1 Word 2
Stop bit Start bit
Transmit Shift Reg.
Word 1 Word 2
bit 0 bit 1 bit 7/8 bit 0
Note: This timing diagram shows two consecutive transmissions.
1 TCY
1 TCY
Start bit
2010 Microchip Technology Inc. DS39770C-page 247
PIC18F85J90 FAMILY
18.3.2 EUSART ASYNCHRONOUS
RECEIVER
The receiver block diagram is shown in Figure 18-6.
The data is received on the RX1 pin and drives the data
recovery block. The data recovery block is actually a
high-speed shifter operating at x16 times the baud rate,
whereas the main receive serial shifter operates at the
bit rate or at FOSC. This mode would typically be used
in RS-232 systems.
To set up an Asynchronous Reception:
1. Initialize the SPBRGH1:SPBRG1 registers for
the appropriate baud rate. Set or clear the
BRGH and BRG16 bits, as required, to achieve
the desired baud rate.
2. Enable the asynchronous serial port by clearing
bit, SYNC, and setting bit, SPEN.
3. If interrupts are desired, set enable bit, RC1IE.
4. If 9-bit reception is desired, set bit, RX9.
5. Enable the reception by setting bit, CREN.
6. Flag bit, RC1IF, will be set when reception is
complete and an interrupt will be generated if
enable bit, RC1IE, was set.
7. Read the RCSTA1 register to get the 9th bit (if
enabled) and determine if any error occurred
during reception.
8. Read the 8-bit received data by reading the
RCREG1 register.
9. If any error occurred, clear the error by clearing
enable bit, CREN.
10. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
18.3.3 SETTING UP 9-BIT MODE WITH
ADDRESS DETECT
This mode would typically be used in RS-485 systems.
To set up an Asynchronous Reception with Address
Detect Enable:
1. Initialize the SPBRGH1:SPBRG1 registers for
the appropriate baud rate. Set or clear the
BRGH and BRG16 bits, as required, to achieve
the desired baud rate.
2. Enable the asynchronous serial port by clearing
the SYNC bit and setting the SPEN bit.
3. If interrupts are required, set the RCEN bit and
select the desired priority level with the RC1IP
bit.
4. Set the RX9 bit to enable 9-bit reception.
5. Set the ADDEN bit to enable address detect.
6. Enable reception by setting the CREN bit.
7. The RC1IF bit will be set when reception is
complete. The interrupt will be Acknowledged if
the RC1IE and GIE bits are set.
8. Read the RCSTA1 register to determine if any
error occurred during reception, as well as read
bit 9 of data (if applicable).
9. Read RCREG1 to determine if the device is
being addressed.
10. If any error occurred, clear the CREN bit.
11. If the device has been addressed, clear the
ADDEN bit to allow all received data into the
receive buffer and interrupt the CPU.
FIGURE 18-6: EUSART RECEIVE BLOCK DIAGRAM
x64 Baud Rate CLK
Baud Rate Generator
RX1
Pin Buffer
and Control
SPEN
Data
Recovery
CREN OERR FERR
RSR Register
MSb LSb
RX9D RCREG1 Register
FIFO
Interrupt RC1IF
RC1IE
Data Bus
8
64
16
or
Stop Start
(8) 7 1 0
RX9
SPBRG1SPBRGH1
BRG16
or
4
PIC18F85J90 FAMILY
DS39770C-page 248 2010 Microchip Technology Inc.
FIGURE 18-7: ASYNCHRONOUS RECEPTION
TABLE 18-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on Page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 57
PIR1 —ADIF RC1IF TX1IF SSPIF —TMR2IF TMR1IF 60
PIE1 —ADIE RC1IE TX1IE SSPIE —TMR2IE TMR1IE 60
IPR1 —ADIP RC1IP TX1IP SSPIP —TMR2IP TMR1IP 60
RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 59
RCREG1 EUSART Receive Register 59
TXSTA1 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 59
BAUDCON1 ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN 61
SPBRGH1 EUSART Baud Rate Generator Register High Byte 61
SPBRG1 EUSART Baud Rate Generator Register Low Byte 59
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.
Start
bit bit 7/8
bit 1bit 0 bit 7/8 bit 0Stop
bit
Start
bit
Start
bit
bit 7/8 Stop
bit
RX1 (pin)
Rcv Buffer Reg
Rcv Shift Reg
Read Rcv
Buffer Reg
RCREG1
RC1IF
(Interrupt Flag)
OERR bit
CREN bit
Word 1
RCREG1
Word 2
RCREG1
Stop
bit
Note: This timing diagram shows three words appearing on the RX1 input. The RCREG1 (Receive Buffer register) is read after the third word
causing the OERR (Overrun) bit to be set.
2010 Microchip Technology Inc. DS39770C-page 249
PIC18F85J90 FAMILY
18.3.4 AUTO-WAKE-UP ON SYNC BREAK
CHARACTER
During Sleep mode, all clocks to the EUSART are
suspended. Because of this, the Baud Rate Generator
is inactive and a proper byte reception cannot be per-
formed. The auto-wake-up feature allows the controller
to wake-up, due to activity on the RX1/DT1 line, while
the EUSART is operating in Asynchronous mode.
The auto-wake-up feature is enabled by setting the
WUE bit (BAUDCON<1>). Once set, the typical receive
sequence on RX1/DT1 is disabled and the EUSART
remains in an Idle state, monitoring for a wake-up event
independent of the CPU mode. A wake-up event
consists of a high-to-low transition on the RX1/DT1
line. (This coincides with the start of a Sync Break or a
Wake-up Signal character for the LIN/J2602 protocol.)
Following a wake-up event, the module generates an
RC1IF interrupt. The interrupt is generated synchro-
nously to the Q clocks in normal operating modes
(Figure 18-8) and asynchronously, if the device is in
Sleep mode (Figure 18-9). The interrupt condition is
cleared by reading the RCREG1 register.
The WUE bit is automatically cleared once a low-to-high
transition is observed on the RX1 line following the
wake-up event. At this point, the EUSART module is in
Idle mode and returns to normal operation. This signals
to the user that the Sync Break event is over.
18.3.4.1 Special Considerations Using
Auto-Wake-up
Since auto-wake-up functions by sensing rising edge
transitions on RX1/DT1, information with any state
changes before the Stop bit may signal a false
End-Of-Character (EOC) and cause data or framing
errors. Therefore, to work properly, the initial character
in the transmission must be all ‘0’s. This can be 00h
(8 bits) for standard RS-232 devices, or 000h (12 bits)
for LIN/J2602 bus.
Oscillator start-up time must also be considered,
especially in applications using oscillators with longer
start-up intervals (i.e., XT or HS mode). The Sync
Break (or Wake-up Signal) character must be of
sufficient length and be followed by a sufficient interval
to allow enough time for the selected oscillator to start
and provide proper initialization of the EUSART.
18.3.4.2 Special Considerations Using
the WUE Bit
The timing of WUE and RC1IF events may cause some
confusion when it comes to determining the validity of
received data. As noted, setting the WUE bit places the
EUSART in an Idle mode. The wake-up event causes
a receive interrupt by setting the RC1IF bit. The WUE
bit is cleared after this when a rising edge is seen on
RX1/DT1. The interrupt condition is then cleared by
reading the RCREG1 register. Ordinarily, the data in
RCREG1 will be dummy data and should be discarded.
The fact that the WUE bit has been cleared (or is still
set) and the RC1IF flag is set should not be used as an
indicator of the integrity of the data in RCREG1. Users
should consider implementing a parallel method in
firmware to verify received data integrity.
To assure that no actual data is lost, check the RCIDL
bit to verify that a receive operation is not in process. If
a receive operation is not occurring, the WUE bit may
then be set just prior to entering the Sleep mode.
FIGURE 18-8: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING NORMAL OPERATION
FIGURE 18-9: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
WUE bit(1)
RX1/DT1 Line
RC1IF
Cleared due to user read of RCREG1
Note 1: The EUSART remains in Idle while the WUE bit is set.
Bit set by user Auto-Cleared
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
WUE bit(2)
RX1/DT1 Line
RC1IF
Cleared due to user read of RCREG1
SLEEP Command Executed
Note 1: If the wake-up event requires long oscillator warm-up time, the auto-clear of the WUE bit can occur while the stposc signal is still active.
This sequence should not depend on the presence of Q clocks.
2: The EUSART remains in Idle while the WUE bit is set.
Sleep Ends
Auto-Cleared
Note 1
Bit set by user
PIC18F85J90 FAMILY
DS39770C-page 250 2010 Microchip Technology Inc.
18.3.5 BREAK CHARACTER SEQUENCE
The Enhanced USART module has the capability of
sending the special Break character sequences that are
required by the LIN/J2602 bus standard. The Break
character transmit consists of a Start bit, followed by
twelve ‘0’ bits and a Stop bit. The Frame Break character
is sent whenever the SENDB and TXEN bits
(TXSTA<3> and TXSTA<5>) are set while the Transmit
Shift register is loaded with data. Note that the value of
data written to TXREG1 will be ignored and all ‘0’s will be
transmitted.
The SENDB bit is automatically reset by hardware after
the corresponding Stop bit is sent. This allows the user
to preload the transmit FIFO with the next transmit byte
following the Break character (typically, the Sync
character in the LIN/J2602 specification).
Note that the data value written to the TXREG1 for the
Break character is ignored. The write simply serves the
purpose of initiating the proper sequence.
The TRMT bit indicates when the transmit operation is
active or Idle, just as it does during normal transmis-
sion. See Figure 18-10 for the timing of the Break
character sequence.
18.3.5.1 Break and Sync Transmit Sequence
The following sequence will send a message frame
header made up of a Break, followed by an Auto-Baud
Sync byte. This sequence is typical of a LIN/J2602 bus
master.
1. Configure the EUSART for the desired mode.
2. Set the TXEN and SENDB bits to set up the
Break character.
3. Load the TXREG1 with a dummy character to
initiate transmission (the value is ignored).
4. Write ‘55h’ to TXREG1 to load the Sync
character into the transmit FIFO buffer.
5. After the Break has been sent, the SENDB bit is
reset by hardware. The Sync character now
transmits in the preconfigured mode.
When the TXREG1 becomes empty, as indicated by the
TX1IF, the next data byte can be written to TXREG1.
18.3.6 RECEIVING A BREAK CHARACTER
The Enhanced USART module can receive a Break
character in two ways.
The first method forces configuration of the baud rate
at a frequency of 9/13 the typical speed. This allows for
the Stop bit transition to be at the correct sampling
location (13 bits for Break versus Start bit and 8 data
bits for typical data).
The second method uses the auto-wake-up feature
described in Section 18.3.4 “Auto-Wake-up On Sync
Break Character”. By enabling this feature, the
EUSART will sample the next two transitions on
RX1/DT1, cause an RC1IF interrupt and receive the
next data byte followed by another interrupt.
Note that following a Break character, the user will
typically want to enable the Auto-Baud Rate Detect
feature. For both methods, the user can set the ABD bit
once the TX1IF interrupt is observed.
FIGURE 18-10: SEND BREAK CHARACTER SEQUENCE
Write to TXREG1
BRG Output
(Shift Clock)
Start bit bit 0 bit 1 bit 11 Stop bit
Break
TX1IF bit
(Transmit Buffer
Reg. Empty Flag)
TX1 (pin)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
SENDB
(Transmit Shift
Reg. Empty Flag)
SENDB sampled here Auto-Cleared
Dummy Write
2010 Microchip Technology Inc. DS39770C-page 251
PIC18F85J90 FAMILY
18.4 EUSART Synchronous
Master Mode
The Synchronous Master mode is entered by setting
the CSRC bit (TXSTA<7>). In this mode, the data is
transmitted in a half-duplex manner (i.e., transmission
and reception do not occur at the same time). When
transmitting data, the reception is inhibited and vice
versa. Synchronous mode is entered by setting bit,
SYNC (TXSTA<4>). In addition, enable bit, SPEN
(RCSTA1<7>), is set in order to configure the TX1 and
RX1 pins to CK1 (clock) and DT1 (data) lines,
respectively.
The Master mode indicates that the processor trans-
mits the master clock on the CK1 line. Clock polarity is
selected with the TXCKP bit (BAUDCON<4>). Setting
TXCKP sets the Idle state on CK1 as high, while clear-
ing the bit sets the Idle state as low. This option is
provided to support Microwire devices with this module.
18.4.1 EUSART SYNCHRONOUS MASTER
TRANSMISSION
The EUSART transmitter block diagram is shown in
Figure 18-3. The heart of the transmitter is the Transmit
(Serial) Shift register (TSR). The Shift register obtains
its data from the Read/Write Transmit Buffer register,
TXREG1. The TXREG1 register is loaded with data in
software. The TSR register is not loaded until the last
bit has been transmitted from the previous load. As
soon as the last bit is transmitted, the TSR is loaded
with new data from the TXREG1 (if available).
Once the TXREG1 register transfers the data to the
TSR register (occurs in one TCYCLE), the TXREG1 is
empty and the TX1IF flag bit (PIR1<4>) is set. The
interrupt can be enabled or disabled by setting or clear-
ing the interrupt enable bit, TX1IE (PIE1<4>). TX1IF is
set regardless of the state of enable bit TX1IE; it cannot
be cleared in software. It will reset only when new data
is loaded into the TXREG1 register.
While flag bit, TX1IF, indicates the status of the TXREG1
register, another bit, TRMT (TXSTA<1>), shows the
status of the TSR register. TRMT is a read-only bit which
is set when the TSR is empty. No interrupt logic is tied to
this bit so the user has to poll this bit in order to deter-
mine if the TSR register is empty. The TSR is not
mapped in data memory so it is not available to the user.
To set up a Synchronous Master Transmission:
1. Initialize the SPBRGH1:SPBRG1 registers for
the appropriate baud rate. Set or clear the
BRG16 bit, as required, to achieve the desired
baud rate.
2. Enable the synchronous master serial port by
setting bits, SYNC, SPEN and CSRC.
3. If interrupts are desired, set enable bit, TX1IE.
4. If 9-bit transmission is desired, set bit, TX9.
5. Enable the transmission by setting bit, TXEN.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit, TX9D.
7. Start transmission by loading data to the
TXREG1 register.
8. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
FIGURE 18-11: SYNCHRONOUS TRANSMISSION
bit 0 bit 1 bit 7
Word 1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4
bit 2 bit 0 bit 1 bit 7
RC7/RX1/DT1
RC6/TX1/CK1 pin
Write to
TXREG1 Reg
TX1IF bit
(Interrupt Flag)
TXEN bit ‘1’ ‘1’
Word 2
TRMT bit
Write Word 1 Write Word 2
Note: Sync Master mode, SPBRG1 = 0; continuous transmission of two 8-bit words.
pin
RC6/TX1/CK1 pin
(TXCKP = 0)
(TXCKP = 1)
PIC18F85J90 FAMILY
DS39770C-page 252 2010 Microchip Technology Inc.
FIGURE 18-12: SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
TABLE 18-7: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on Page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 57
PIR1 —ADIF RC1IF TX1IF SSPIF —TMR2IF TMR1IF 60
PIE1 —ADIE RC1IE TX1IE SSPIE —TMR2IE TMR1IE 60
IPR1 —ADIP RC1IP TX1IP SSPIP —TMR2IP TMR1IP 60
RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 59
TXREG1 EUSART Transmit Register 59
TXSTA1 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 59
BAUDCON1 ABDOVF RCIDL RXDTP TXCKP BRG16 —WUE ABDEN 61
SPBRGH1 EUSART Baud Rate Generator Register High Byte 61
SPBRG1 EUSART Baud Rate Generator Register Low Byte 59
LATG U2OD U1OD —LATG4 LATG3 LATG2 LATG1 LATG0 60
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master transmission.
RC7/RX1/DT1 pin
RC6/TX1/CK1 pin
Write to
TXREG1 Reg
TX1IF bit
TRMT bit
bit 0 bit 1 bit 2 bit 6 bit 7
TXEN bit
2010 Microchip Technology Inc. DS39770C-page 253
PIC18F85J90 FAMILY
18.4.2 EUSART SYNCHRONOUS
MASTER RECEPTION
Once Synchronous mode is selected, reception is
enabled by setting either the Single Receive Enable bit,
SREN (RCSTA1<5>), or the Continuous Receive
Enable bit, CREN (RCSTA1<4>). Data is sampled on
the RX1 pin on the falling edge of the clock.
If enable bit, SREN, is set, only a single word is
received. If enable bit, CREN, is set, the reception is
continuous until CREN is cleared. If both bits are set,
then CREN takes precedence.
To set up a Synchronous Master Reception:
1. Initialize the SPBRGH1:SPBRG1 registers for the
appropriate baud rate. Set or clear the BRG16 bit,
as required, to achieve the desired baud rate.
2. Enable the synchronous master serial port by
setting bits, SYNC, SPEN and CSRC.
3. Ensure bits, CREN and SREN, are clear.
4. If interrupts are desired, set enable bit, RC1IE.
5. If 9-bit reception is desired, set bit, RX9.
6. If a single reception is required, set bit, SREN.
For continuous reception, set bit, CREN.
7. Interrupt flag bit, RC1IF, will be set when recep-
tion is complete and an interrupt will be generated
if the enable bit, RC1IE, was set.
8. Read the RCSTA1 register to get the 9th bit (if
enabled) and determine if any error occurred
during reception.
9. Read the 8-bit received data by reading the
RCREG1 register.
10. If any error occurred, clear the error by clearing
bit, CREN.
11. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
FIGURE 18-13: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
TABLE 18-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on Page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 57
PIR1 —ADIF RC1IF TX1IF SSPIF —TMR2IF TMR1IF 60
PIE1 —ADIE RC1IE TX1IE SSPIE —TMR2IE TMR1IE 60
IPR1 —ADIP RC1IP TX1IP SSPIP —TMR2IP TMR1IP 60
RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 59
RCREG1 EUSART Receive Register 59
TXSTA1 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 59
BAUDCON1 ABDOVF RCIDL RXDTP TXCKP BRG16 —WUE ABDEN 61
SPBRGH1 EUSART Baud Rate Generator Register High Byte 61
SPBRG1 EUSART Baud Rate Generator Register Low Byte 59
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception.
CREN bit
RC7/RX1/DT1
RC6/TX1/CK1 pin
Write to
SREN bit
SREN bit
RC1IF bit
(Interrupt)
Read
RCREG1
Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q2 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
‘
0
’
bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7
‘
0
’
Q1 Q2 Q3 Q4
Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
RC6/TX1/CK1 pin
pin
(TXCKP = 0)
(TXCKP = 1)
PIC18F85J90 FAMILY
DS39770C-page 254 2010 Microchip Technology Inc.
18.5 EUSART Synchronous Slave Mode
Synchronous Slave mode is entered by clearing bit
CSRC (TXSTA<7>). This mode differs from the
Synchronous Master mode in that the shift clock is
supplied externally at the CK1 pin (instead of being
supplied internally in Master mode). This allows the
device to transfer or receive data while in any
low-power mode.
18.5.1 EUSART SYNCHRONOUS SLAVE
TRANSMIT
The operation of the Synchronous Master and Slave
modes are identical except in the case of the Sleep
mode.
If two words are written to the TXREG1 and then the
SLEEP instruction is executed, the following will occur:
a) The first word will immediately transfer to the
TSR register and transmit.
b) The second word will remain in the TXREG1
register.
c) Flag bit, TX1IF, will not be set.
d) When the first word has been shifted out of TSR,
the TXREG1 register will transfer the second
word to the TSR and flag bit, TX1IF, will now be
set.
e) If enable bit, TX1IE, is set, the interrupt will wake
the chip from Sleep. If the global interrupt is
enabled, the program will branch to the interrupt
vector.
To set up a Synchronous Slave Transmission:
1. Enable the synchronous slave serial port by
setting bits, SYNC and SPEN, and clearing bit,
CSRC.
2. Clear bits, CREN and SREN.
3. If interrupts are desired, set enable bit, TX1IE.
4. If 9-bit transmission is desired, set bit, TX9.
5. Enable the transmission by setting enable bit,
TXEN.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit, TX9D.
7. Start transmission by loading data to the
TXREG1 register.
8. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
TABLE 18-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on Page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 57
PIR1 —ADIF RC1IF TX1IF SSPIF —TMR2IF TMR1IF 60
PIE1 —ADIE RC1IE TX1IE SSPIE —TMR2IE TMR1IE 60
IPR1 —ADIP RC1IP TX1IP SSPIP —TMR2IP TMR1IP 60
RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 59
TXREG1 EUSART Transmit Register 59
TXSTA1 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 59
BAUDCON1 ABDOVF RCIDL RXDTP TXCKP BRG16 —WUE ABDEN 61
SPBRGH1 EUSART Baud Rate Generator Register High Byte 61
SPBRG1 EUSART Baud Rate Generator Register Low Byte 59
LATG U2OD U1OD —LATG4 LATG3 LATG2 LATG1 LATG0 60
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave transmission.
2010 Microchip Technology Inc. DS39770C-page 255
PIC18F85J90 FAMILY
18.5.2 EUSART SYNCHRONOUS SLAVE
RECEPTION
The operation of the Synchronous Master and Slave
modes is identical except in the case of Sleep or any
Idle mode, and bit SREN, which is a “don’t care” in
Slave mode.
If receive is enabled by setting the CREN bit prior to
entering Sleep or any Idle mode, then a word may be
received while in this low-power mode. Once the word
is received, the RSR register will transfer the data to the
RCREG1 register; if the RC1IE enable bit is set, the
interrupt generated will wake the chip from the
low-power mode. If the global interrupt is enabled, the
program will branch to the interrupt vector.
To set up a Synchronous Slave Reception:
1. Enable the synchronous master serial port by
setting bits, SYNC and SPEN, and clearing bit,
CSRC.
2. If interrupts are desired, set enable bit, RC1IE.
3. If 9-bit reception is desired, set bit, RX9.
4. To enable reception, set enable bit, CREN.
5. Flag bit, RC1IF, will be set when reception is
complete. An interrupt will be generated if
enable bit, RC1IE, was set.
6. Read the RCSTA1 register to get the 9th bit (if
enabled) and determine if any error occurred
during reception.
7. Read the 8-bit received data by reading the
RCREG1 register.
8. If any error occurred, clear the error by clearing
bit, CREN.
9. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
TABLE 18-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on Page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 57
PIR1 —ADIF RC1IF TX1IF SSPIF —TMR2IF TMR1IF 60
PIE1 —ADIE RC1IE TX1IE SSPIE —TMR2IE TMR1IE 60
IPR1 —ADIP RC1IP TX1IP SSPIP —TMR2IP TMR1IP 60
RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 59
RCREG1 EUSART Receive Register 59
TXSTA1 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 59
BAUDCON1 ABDOVF RCIDL RXDTP TXCKP BRG16 —WUE ABDEN 61
SPBRGH1 EUSART Baud Rate Generator Register High Byte 61
SPBRG1 EUSART Baud Rate Generator Register Low Byte 59
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception.
PIC18F85J90 FAMILY
DS39770C-page 256 2010 Microchip Technology Inc.
NOTES:
2010 Microchip Technology Inc. DS39770C-page 257
PIC18F85J90 FAMILY
19.0 ADDRESSABLE UNIVERSAL
SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (AUSART)
The Addressable Universal Synchronous Asynchro-
nous Receiver Transmitter (AUSART) module is very
similar in function to the Enhanced USART module,
discussed in the previous chapter. It is provided as an
additional channel for serial communication with
external devices, for those situations that do not require
auto-baud detection or LIN/J2602 bus support.
The AUSART can be configured in the following modes:
• Asynchronous (full duplex)
• Synchronous – Master (half duplex)
• Synchronous – Slave (half duplex)
The pins of the AUSART module are multiplexed with
the functions of PORTG (RG1/TX2/CK2 and
RG2/RX2/DT2/VLCAP1, respectively). In order to
configure these pins as an AUSART:
• bit, SPEN (RCSTA2<7>), must be set (= 1)
• bit, TRISG<2>, must be set (= 1)
• bit, TRISG<1>, must be cleared (= 0) for
Asynchronous and Synchronous Master modes
• bit, TRISG<1>, must be set (= 1) for Synchronous
Slave mode
The driver for the TX2 output pin can also be optionally
configured as an open-drain output. This feature allows
the voltage level on the pin to be pulled to a higher level
through an external pull-up resistor, and allows the
output to communicate with external circuits without the
need for additional level shifters.
The open-drain output option is controlled by the U2OD
bit (LATG<7>). Setting the bit configures the pin for
open-drain operation.
19.1 Control Registers
The operation of the Addressable USART module is
controlled through two registers, TXSTA2 and
RXSTA2. These are detailed in Register 19-1 and
Register 19-2, respectively.
Note: The AUSART control will automatically
reconfigure the pin from input to output as
needed.
PIC18F85J90 FAMILY
DS39770C-page 258 2010 Microchip Technology Inc.
REGISTER 19-1: TXSTA2: AUSART TRANSMIT STATUS AND CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R-1 R/W-0
CSRC TX9 TXEN(1) SYNC — BRGH TRMT TX9D
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 CSRC: Clock Source Select bit
Asynchronous mode:
Don’t care.
Synchronous mode:
1 = Master mode (clock generated internally from BRG)
0 = Slave mode (clock from external source)
bit 6 TX9: 9-Bit Transmit Enable bit
1 = Selects 9-bit transmission
0 = Selects 8-bit transmission
bit 5 TXEN: Transmit Enable bit(1)
1 = Transmit enabled
0 = Transmit disabled
bit 4 SYNC: AUSART Mode Select bit
1 = Synchronous mode
0 = Asynchronous mode
bit 3 Unimplemented: Read as ‘0’
bit 2 BRGH: High Baud Rate Select bit
Asynchronous mode:
1 = High speed
0 = Low speed
Synchronous mode:
Unused in this mode.
bit 1 TRMT: Transmit Shift Register Status bit
1 = TSR empty
0 = TSR full
bit 0 TX9D: 9th bit of Transmit Data
Can be address/data bit or a parity bit.
Note 1: SREN/CREN overrides TXEN in Sync mode.
2010 Microchip Technology Inc. DS39770C-page 259
PIC18F85J90 FAMILY
REGISTER 19-2: RCSTA2: AUSART RECEIVE STATUS AND CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x
SPEN RX9 SREN CREN ADDEN FERR OERR RX9D
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 SPEN: Serial Port Enable bit
1 = Serial port enabled (configures RX2/DT2 and TX2/CK2 (TXEN = 1) pins as serial port pins)
0 = Serial port disabled (held in Reset)
bit 6 RX9: 9-Bit Receive Enable bit
1 = Selects 9-bit reception
0 = Selects 8-bit reception
bit 5 SREN: Single Receive Enable bit
Asynchronous mode:
Don’t care.
Synchronous mode – Master:
1 = Enables single receive
0 = Disables single receive
This bit is cleared after reception is complete.
Synchronous mode – Slave:
Don’t care.
bit 4 CREN: Continuous Receive Enable bit
Asynchronous mode:
1 = Enables receiver
0 = Disables receiver
Synchronous mode:
1 = Enables continuous receive until enable bit, CREN, is cleared (CREN overrides SREN)
0 = Disables continuous receive
bit 3 ADDEN: Address Detect Enable bit
Asynchronous mode 9-bit (RX9 = 1):
1 = Enables address detection, enables interrupt and loads the receive buffer when RSR<8> is set
0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit
Asynchronous mode 9-bit (RX9 = 0):
Don’t care.
bit 2 FERR: Framing Error bit
1 = Framing error (can be cleared by reading the RCREGx register and receiving the next valid byte)
0 = No framing error
bit 1 OERR: Overrun Error bit
1 = Overrun error (can be cleared by clearing bit, CREN)
0 = No overrun error
bit 0 RX9D: 9th bit of Received Data
This can be address/data bit or a parity bit and must be calculated by user firmware.
PIC18F85J90 FAMILY
DS39770C-page 260 2010 Microchip Technology Inc.
19.2 AUSART Baud Rate Generator
(BRG)
The BRG is a dedicated, 8-bit generator that supports
both the Asynchronous and Synchronous modes of the
AUSART.
The SPBRG2 register controls the period of a
free-running timer. In Asynchronous mode, bit BRGH
(TXSTA<2>) also controls the baud rate. In Synchro-
nous mode, BRGH is ignored. Table 19-1 shows the
formula for computation of the baud rate for different
AUSART modes, which only apply in Master mode
(internally generated clock).
Given the desired baud rate and FOSC, the nearest
integer value for the SPBRG2 register can be calcu-
lated using the formulas in Table 19-1. From this, the
error in baud rate can be determined. An example
calculation is shown in Example 19-1. Typical baud
rates and error values for the various Asynchronous
modes are shown in Table 19-2. It may be advanta-
geous to use the high baud rate (BRGH = 1) to reduce
the baud rate error, or achieve a slow baud rate for a
fast oscillator frequency.
Writing a new value to the SPBRG2 register causes the
BRG timer to be reset (or cleared). This ensures the
BRG does not wait for a timer overflow before outputting
the new baud rate.
19.2.1 OPERATION IN POWER-MANAGED
MODES
The device clock is used to generate the desired baud
rate. When one of the power-managed modes is
entered, the new clock source may be operating at a
different frequency. This may require an adjustment to
the value in the SPBRG2 register.
19.2.2 SAMPLING
The data on the RX2 pin is sampled three times by a
majority detect circuit to determine if a high or a low
level is present at the RX2 pin.
TABLE 19-1: BAUD RATE FORMULAS
EXAMPLE 19-1: CALCULATING BAUD RATE ERROR
TABLE 19-2: REGISTERS ASSOCIATED WITH THE BAUD RATE GENERATOR
Configuration Bits
BRG/AUSART Mode Baud Rate Formula
SYNC BRGH
00 Asynchronous FOSC/[64 (n + 1)]
01 Asynchronous FOSC/[16 (n + 1)]
1x Synchronous FOSC/[4 (n + 1)]
Legend: x = Don’t care, n = Value of SPBRG2 register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values on
Page
TXSTA2 CSRC TX9 TXEN SYNC —BRGHTRMT TX9D 62
RCSTA2 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 62
SPBRG2 AUSART Baud Rate Generator Register 62
Legend: Shaded cells are not used by the BRG.
For a device with FOSC of 16 MHz, desired baud rate of 9600, Asynchronous mode, BRGH = 0:
Desired Baud Rate = FOSC/(64 ([SPBRG2] + 1))
Solving for SPBRG2:
X = ((FOSC/Desired Baud Rate)/64) – 1
= ((16000000/9600)/64) – 1
= [25.042] = 25
Calculated Baud Rate = 16000000/(64 (25 + 1))
= 9615
Error = (Calculated Baud Rate – Desired Baud Rate)/Desired Baud Rate
= (9615 – 9600)/9600 = 0.16%
2010 Microchip Technology Inc. DS39770C-page 261
PIC18F85J90 FAMILY
TABLE 19-3: BAUD RATES FOR ASYNCHRONOUS MODES
BRGH = 0
FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz FOSC = 8.000 MHz
BAUD
RATE
(K)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
0.3————————————
1.2 — — — 1.221 1.73 255 1.202 0.16 129 1.201 -0.16 103
2.4 2.441 1.73 255 2.404 0.16 129 2.404 0.16 64 2.403 -0.16 51
9.6 9.615 0.16 64 9.766 1.73 31 9.766 1.73 15 9.615 -0.16 12
19.2 19.531 1.73 31 19.531 1.73 15 19.531 1.73 7 — — —
57.6 56.818 -1.36 10 62.500 8.51 4 52.083 -9.58 2 — — —
115.2 125.000 8.51 4 104.167 -9.58 2 78.125 -32.18 1 — — —
BRGH = 0
FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz
BAUD
RATE
(K)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
0.3 0.300 0.16 207 0.300 -0.16 103 0.300 -0.16 51
1.2 1.202 0.16 51 1.201 -0.16 25 1.201 -0.16 12
2.4 2.404 0.16 25 2.403 -0.16 12 — — —
9.6 8.929 -6.99 6 — — — — — —
19.2 20.833 8.51 2 — — — — — —
57.6 62.500 8.51 0 — — — — — —
115.2 62.500 -45.75 0 — — — — — —
BAUD
RATE
(K)
BRGH = 1
FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz FOSC = 8.000 MHz
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
0.3————————————
1.2————————————
2.4 — — — — — — 2.441 1.73 255 2.403 -0.16 207
9.6 9.766 1.73 255 9.615 0.16 129 9.615 0.16 64 9.615 -0.16 51
19.2 19.231 0.16 129 19.231 0.16 64 19.531 1.73 31 19.230 -0.16 25
57.6 58.140 0.94 42 56.818 -1.36 21 56.818 -1.36 10 55.555 3.55 8
115.2 113.636 -1.36 21 113.636 -1.36 10 125.000 8.51 4 — — —
BAUD
RATE
(K)
BRGH = 1
FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
0.3 — — — — — — 0.300 -0.16 207
1.2 1.202 0.16 207 1.201 -0.16 103 1.201 -0.16 51
2.4 2.404 0.16 103 2.403 -0.16 51 2.403 -0.16 25
9.6 9.615 0.16 25 9.615 -0.16 12 — — —
19.2 19.231 0.16 12 — — — — — —
57.6 62.500 8.51 3 — — — — — —
115.2 125.000 8.51 1 — — — — — —
PIC18F85J90 FAMILY
DS39770C-page 262 2010 Microchip Technology Inc.
19.3 AUSART Asynchronous Mode
The Asynchronous mode of operation is selected by
clearing the SYNC bit (TXSTA2<4>). In this mode, the
AUSART uses standard Non-Return-to-Zero (NRZ)
format (one Start bit, eight or nine data bits and one
Stop bit). The most common data format is 8 bits. An
on-chip, dedicated, 8-bit Baud Rate Generator can be
used to derive standard baud rate frequencies from the
oscillator.
The AUSART transmits and receives the LSb first. The
AUSART’s transmitter and receiver are functionally
independent but use the same data format and baud
rate. The Baud Rate Generator produces a clock,
either x16 or x64 of the bit shift rate, depending on the
BRGH bit (TXSTA2<2>). Parity is not supported by the
hardware but can be implemented in software and
stored as the 9th data bit.
When operating in Asynchronous mode, the AUSART
module consists of the following important elements:
• Baud Rate Generator
• Sampling Circuit
• Asynchronous Transmitter
• Asynchronous Receiver
19.3.1 AUSART ASYNCHRONOUS
TRANSMITTER
The AUSART transmitter block diagram is shown in
Figure 19-1. The heart of the transmitter is the Transmit
(Serial) Shift register (TSR). The Shift register obtains
its data from the Read/Write Transmit Buffer register,
TXREG2. The TXREG2 register is loaded with data in
software. The TSR register is not loaded until the Stop
bit has been transmitted from the previous load. As
soon as the Stop bit is transmitted, the TSR is loaded
with new data from the TXREG2 register (if available).
Once the TXREG2 register transfers the data to the
TSR register (occurs in one TCY), the TXREG2 register
is empty and the TX2IF flag bit (PIR3<4>) is set. This
interrupt can be enabled or disabled by setting or
clearing the interrupt enable bit, TX2IE (PIE3<4>).
TX2IF will be set regardless of the state of TX2IE; it
cannot be cleared in software. TX2IF is also not
cleared immediately upon loading TXREG2, but
becomes valid in the second instruction cycle following
the load instruction. Polling TX2IF immediately
following a load of TXREG2 will return invalid results.
While TX2IF indicates the status of the TXREG2
register, another bit, TRMT (TXSTA2<1>), shows the
status of the TSR register. TRMT is a read-only bit
which is set when the TSR register is empty. No inter-
rupt logic is tied to this bit so the user has to poll this bit
in order to determine if the TSR register is empty.
To set up an Asynchronous Transmission:
1. Initialize the SPBRG2 register for the appropriate
baud rate. Set or clear the BRGH bit, as required,
to achieve the desired baud rate.
2. Enable the asynchronous serial port by clearing
bit, SYNC, and setting bit, SPEN.
3. If interrupts are desired, set enable bit, TX2IE.
4. If 9-bit transmission is desired, set transmit bit,
TX9. Can be used as address/data bit.
5. Enable the transmission by setting bit, TXEN,
which will also set bit, TX2IF.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit, TX9D.
7. Load data to the TXREG2 register (starts
transmission).
8. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
FIGURE 19-1: AUSART TRANSMIT BLOCK DIAGRAM
Note 1: The TSR register is not mapped in data
memory so it is not available to the user.
2: Flag bit, TX2IF, is set when enable bit,
TXEN, is set.
TX2IF
TX2IE
Interrupt
TXEN Baud Rate CLK
SPBRG2
Baud Rate Generator
TX9D
MSb LSb
Data Bus
TXREG2 Register
TSR Register
(8) 0
TX9
TRMT SPEN
TX2 pin
Pin Buffer
and Control
8
2010 Microchip Technology Inc. DS39770C-page 263
PIC18F85J90 FAMILY
FIGURE 19-2: ASYNCHRONOUS TRANSMISSION
FIGURE 19-3: ASYNCHRONOUS TRANSMISSION (BACK TO BACK)
TABLE 19-4: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on Page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 57
PIR3 —LCDIF RC2IF TX2IF —CCP2IF CCP1IF —60
PIE3 —LCDIE RC2IE TX2IE —CCP2IE CCP1IE —60
IPR3 —LCDIP RC2IP TX2IP —CCP2IP CCP1IP —60
RCSTA2 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 62
TXREG2 AUSART Transmit Register 62
TXSTA2 CSRC TX9 TXEN SYNC —BRGH TRMT TX9D 62
SPBRG2 AUSART Baud Rate Generator Register 62
LATG U2OD U1OD —LATG4 LATG3 LATG2 LATG1 LATG0 60
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous transmission.
Word 1
Word 1
Transmit Shift Reg
Start bit bit 0 bit 1 bit 7/8
Write to TXREG2
BRG Output
(Shift Clock)
TX2 (pin)
TX2IF bit
(Transmit Buffer
Reg. Empty Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
1 TCY
Word 1
Stop bit
Transmit Shift Reg.
Write to TXREG2
BRG Output
(Shift Clock)
TX2 (pin)
TX2IF bit
(Interrupt Reg. Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
Word 1 Word 2
Word 1 Word 2
Stop bit Start bit
Transmit Shift Reg.
Word 1 Word 2
bit 0 bit 1 bit 7/8 bit 0
Note: This timing diagram shows two consecutive transmissions.
1 TCY
1 TCY
Start bit
PIC18F85J90 FAMILY
DS39770C-page 264 2010 Microchip Technology Inc.
19.3.2 AUSART ASYNCHRONOUS
RECEIVER
The receiver block diagram is shown in Figure 19-4.
The data is received on the RX2 pin and drives the data
recovery block. The data recovery block is actually a
high-speed shifter operating at x16 times the baud rate,
whereas the main receive serial shifter operates at the
bit rate or at FOSC. This mode would typically be used
in RS-232 systems.
To set up an Asynchronous Reception:
1. Initialize the SPBRG2 register for the appropriate
baud rate. Set or clear the BRGH bit, as required,
to achieve the desired baud rate.
2. Enable the asynchronous serial port by clearing
bit, SYNC, and setting bit, SPEN.
3. If interrupts are desired, set enable bit, RC2IE.
4. If 9-bit reception is desired, set bit, RX9.
5. Enable the reception by setting bit, CREN.
6. Flag bit, RC2IF, will be set when reception is
complete and an interrupt will be generated if
enable bit, RC2IE, was set.
7. Read the RCSTA2 register to get the 9th bit (if
enabled) and determine if any error occurred
during reception.
8. Read the 8-bit received data by reading the
RCREG2 register.
9. If any error occurred, clear the error by clearing
enable bit, CREN.
10. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
19.3.3 SETTING UP 9-BIT MODE WITH
ADDRESS DETECT
This mode would typically be used in RS-485 systems.
To set up an Asynchronous Reception with Address
Detect Enable:
1. Initialize the SPBRG2 register for the appropriate
baud rate. Set or clear the BRGH and BRG16
bits, as required, to achieve the desired baud
rate.
2. Enable the asynchronous serial port by clearing
the SYNC bit and setting the SPEN bit.
3. If interrupts are required, set the RCEN bit and
select the desired priority level with the RC2IP
bit.
4. Set the RX9 bit to enable 9-bit reception.
5. Set the ADDEN bit to enable address detect.
6. Enable reception by setting the CREN bit.
7. The RC2IF bit will be set when reception is
complete. The interrupt will be Acknowledged if
the RC2IE and GIE bits are set.
8. Read the RCSTA2 register to determine if any
error occurred during reception, as well as read
bit 9 of data (if applicable).
9. Read RCREG2 to determine if the device is
being addressed.
10. If any error occurred, clear the CREN bit.
11. If the device has been addressed, clear the
ADDEN bit to allow all received data into the
receive buffer and interrupt the CPU.
FIGURE 19-4: AUSART RECEIVE BLOCK DIAGRAM
x64 Baud Rate CLK
Baud Rate Generator
RX2
Pin Buffer
and Control
SPEN
Data
Recovery
CREN OERR FERR
RSR Register
MSb LSb
RX9D RCREG2 Register
FIFO
Interrupt RC2IF
RC2IE
Data Bus
8
64
16
or
Stop Start
(8) 7 1 0
RX9
SPBRG2
or
4
2010 Microchip Technology Inc. DS39770C-page 265
PIC18F85J90 FAMILY
FIGURE 19-5: ASYNCHRONOUS RECEPTION
TABLE 19-5: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on Page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 57
PIR3 —LCDIF RC2IF TX2IF —CCP2IF CCP1IF —60
PIE3 —LCDIE RC2IE TX2IE —CCP2IE CCP1IE —60
IPR3 —LCDIP RC2IP TX2IP —CCP2IP CCP1IP —60
RCSTA2 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 62
RCREG2 AUSART Receive Register 62
TXSTA2 CSRC TX9 TXEN SYNC —BRGHTRMT TX9D 62
SPBRG2 AUSART Baud Rate Generator Register 62
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.
Start
bit bit 7/8
bit 1bit 0 bit 7/8 bit 0Stop
bit
Start
bit
Start
bit
bit 7/8 Stop
bit
RX2 (pin)
Rcv Buffer Reg
Rcv Shift Reg
Read Rcv
Buffer Reg
RCREG2
RC2IF
(Interrupt Flag)
OERR bit
CREN
Word 1
RCREG2
Word 2
RCREG2
Stop
bit
Note: This timing diagram shows three words appearing on the RX2 input. The RCREG2 (Receive Buffer register) is read after the third word
causing the OERR (Overrun) bit to be set.
PIC18F85J90 FAMILY
DS39770C-page 266 2010 Microchip Technology Inc.
19.4 AUSART Synchronous
Master Mode
The Synchronous Master mode is entered by setting
the CSRC bit (TXSTA2<7>). In this mode, the data is
transmitted in a half-duplex manner (i.e., transmission
and reception do not occur at the same time). When
transmitting data, the reception is inhibited and vice
versa. Synchronous mode is entered by setting bit,
SYNC (TXSTA2<4>). In addition, enable bit, SPEN
(RCSTA2<7>), is set in order to configure the TX2 and
RX2 pins to CK2 (clock) and DT2 (data) lines,
respectively.
The Master mode indicates that the processor transmits
the master clock on the CK2 line.
19.4.1 AUSART SYNCHRONOUS MASTER
TRANSMISSION
The AUSART transmitter block diagram is shown in
Figure 19-1. The heart of the transmitter is the Transmit
(Serial) Shift register (TSR). The Shift register obtains
its data from the Read/Write Transmit Buffer register,
TXREG2. The TXREG2 register is loaded with data in
software. The TSR register is not loaded until the last
bit has been transmitted from the previous load. As
soon as the last bit is transmitted, the TSR is loaded
with new data from the TXREG2 (if available).
Once the TXREG2 register transfers the data to the
TSR register (occurs in one T
CYCLE), the TXREG2 is
empty and the TX2IF flag bit (PIR3<4>) is set. The
interrupt can be enabled or disabled by setting or clear-
ing the interrupt enable bit, TX2IE (PIE3<4>). TX2IF is
set regardless of the state of enable bit, TX2IE; it
cannot be cleared in software. It will reset only when
new data is loaded into the TXREG2 register.
While flag bit, TX2IF, indicates the status of the TXREG2
register, another bit, TRMT (TXSTA2<1>), shows the
status of the TSR register. TRMT is a read-only bit which
is set when the TSR is empty. No interrupt logic is tied to
this bit so the user has to poll this bit in order to deter-
mine if the TSR register is empty. The TSR is not
mapped in data memory so it is not available to the user.
To set up a Synchronous Master Transmission:
1. Initialize the SPBRG2 register for the appropriate
baud rate.
2. Enable the synchronous master serial port by
setting bits, SYNC, SPEN and CSRC.
3. If interrupts are desired, set enable bit, TX2IE.
4. If 9-bit transmission is desired, set bit, TX9.
5. Enable the transmission by setting bit, TXEN.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit, TX9D.
7. Start transmission by loading data to the
TXREG2 register.
8. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
FIGURE 19-6: SYNCHRONOUS TRANSMISSION
bit 0 bit 1 bit 7
Word 1
Q1 Q2 Q3Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
bit 2 bit 0 bit 1 bit 7
RX2/DT2 pin
TX2/CK2 pin
Write to
TXREG2 Reg
TX2IF bit
(Interrupt Flag)
TXEN bit ‘1’ ‘1’
Word 2
TRMT bit
Write Word 1 Write Word 2
Note: Sync Master mode, SPBRG2 = 0; continuous transmission of two 8-bit words.
2010 Microchip Technology Inc. DS39770C-page 267
PIC18F85J90 FAMILY
FIGURE 19-7: SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
TABLE 19-6: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on Page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 57
PIR3 —LCDIF RC2IF TX2IF — CCP2IF CCP1IF —60
PIE3 —LCDIE RC2IE TX2IE — CCP2IE CCP1IE —60
IPR3 —LCDIP RC2IP TX2IP — CCP2IP CCP1IP —60
RCSTA2 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 62
TXREG2 AUSART Transmit Register 62
TXSTA2 CSRC TX9 TXEN SYNC —BRGH TRMT TX9D 62
SPBRG2 AUSART Baud Rate Generator Register 62
LATG U2OD U1OD —LATG4 LATG3 LATG2 LATG1 LATG0 60
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master transmission.
RX2/DT2 pin
TX2/CK2 pin
Write to
TXREG2 Reg
TX2IF bit
TRMT bit
bit 0 bit 1 bit 2 bit 6 bit 7
TXEN bit
PIC18F85J90 FAMILY
DS39770C-page 268 2010 Microchip Technology Inc.
19.4.2 AUSART SYNCHRONOUS
MASTER RECEPTION
Once Synchronous mode is selected, reception is
enabled by setting either the Single Receive Enable bit,
SREN (RCSTA2<5>), or the Continuous Receive
Enable bit, CREN (RCSTA2<4>). Data is sampled on
the RX2 pin on the falling edge of the clock.
If enable bit SREN is set, only a single word is received.
If enable bit CREN is set, the reception is continuous
until CREN is cleared. If both bits are set, then CREN
takes precedence.
To set up a Synchronous Master Reception:
1. Initialize the SPBRG2 register for the appropriate
baud rate.
2. Enable the synchronous master serial port by
setting bits, SYNC, SPEN and CSRC.
3. Ensure bits, CREN and SREN, are clear.
4. If interrupts are desired, set enable bit, RC2IE.
5. If 9-bit reception is desired, set bit, RX9.
6. If a single reception is required, set bit, SREN.
For continuous reception, set bit, CREN.
7. Interrupt flag bit, RC2IF, will be set when recep-
tion is complete and an interrupt will be generated
if the enable bit, RC2IE, was set.
8. Read the RCSTA2 register to get the 9th bit (if
enabled) and determine if any error occurred
during reception.
9. Read the 8-bit received data by reading the
RCREG2 register.
10. If any error occurred, clear the error by clearing
bit, CREN.
11. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
FIGURE 19-8: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
TABLE 19-7: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on Page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 57
PIR3 —LCDIF RC2IF TX2IF —CCP2IF CCP1IF —60
PIE3 —LCDIE RC2IE TX2IE —CCP2IE CCP1IE —60
IPR3 —LCDIP RC2IP TX2IP —CCP2IP CCP1IP —60
RCSTA2 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 62
RCREG2 AUSART Receive Register 62
TXSTA2 CSRC TX9 TXEN SYNC —BRGH TRMT TX9D 62
SPBRG2 AUSART Baud Rate Generator Register 62
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception.
CREN bit
RX2/DT2 pin
TX2/CK2 pin
Write to
bit SREN
SREN bit
RC2IF bit
(Interrupt)
Read
RCREG2
Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q2 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
‘
0
’
bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7
‘
0
’
Q1 Q2 Q3 Q4
Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
2010 Microchip Technology Inc. DS39770C-page 269
PIC18F85J90 FAMILY
19.5 AUSART Synchronous Slave Mode
Synchronous Slave mode is entered by clearing bit,
CSRC (TXSTA2<7>). This mode differs from the
Synchronous Master mode in that the shift clock is
supplied externally at the CK2 pin (instead of being
supplied internally in Master mode). This allows the
device to transfer or receive data while in any
low-power mode.
19.5.1 AUSART SYNCHRONOUS
SLAVE TRANSMIT
The operation of the Synchronous Master and Slave
modes are identical except in the case of the Sleep
mode.
If two words are written to the TXREG2 and then the
SLEEP instruction is executed, the following will occur:
a) The first word will immediately transfer to the
TSR register and transmit.
b) The second word will remain in the TXREG2
register.
c) Flag bit, TX2IF, will not be set.
d) When the first word has been shifted out of TSR,
the TXREG2 register will transfer the second
word to the TSR and flag bit, TX2IF, will now be
set.
e) If enable bit, TX2IE, is set, the interrupt will wake
the chip from Sleep. If the global interrupt is
enabled, the program will branch to the interrupt
vector.
To set up a Synchronous Slave Transmission:
1. Enable the synchronous slave serial port by
setting bits, SYNC and SPEN, and clearing bit,
CSRC.
2. Clear bits, CREN and SREN.
3. If interrupts are desired, set enable bit, TX2IE.
4. If 9-bit transmission is desired, set bit, TX9.
5. Enable the transmission by setting enable bit,
TXEN.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit, TX9D.
7. Start transmission by loading data to the
TXREG2 register.
8. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
TABLE 19-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on Page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 57
PIR3 —LCDIF RC2IF TX2IF —CCP2IF CCP1IF —60
PIE3 —LCDIE RC2IE TX2IE —CCP2IE CCP1IE —60
IPR3 —LCDIP RC2IP TX2IP —CCP2IP CCP1IP —60
RCSTA2 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 62
TXREG2 AUSART Transmit Register 62
TXSTA2 CSRC TX9 TXEN SYNC —BRGH TRMT TX9D 62
SPBRG2 AUSART Baud Rate Generator Register 62
LATG U2OD U1OD —LATG4 LATG3 LATG2 LATG1 LATG0 60
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave transmission.
PIC18F85J90 FAMILY
DS39770C-page 270 2010 Microchip Technology Inc.
19.5.2 AUSART SYNCHRONOUS
SLAVE RECEPTION
The operation of the Synchronous Master and Slave
modes is identical except in the case of Sleep or any
Idle mode, and bit SREN, which is a “don’t care” in
Slave mode.
If receive is enabled by setting the CREN bit prior to
entering Sleep, or any Idle mode, then a word may be
received while in this low-power mode. Once the word
is received, the RSR register will transfer the data to the
RCREG2 register; if the RC2IE enable bit is set, the
interrupt generated will wake the chip from low-power
mode. If the global interrupt is enabled, the program will
branch to the interrupt vector.
To set up a Synchronous Slave Reception:
1. Enable the synchronous master serial port by
setting bits, SYNC and SPEN, and clearing bit,
CSRC.
2. If interrupts are desired, set enable bit, RC2IE.
3. If 9-bit reception is desired, set bit, RX9.
4. To enable reception, set enable bit, CREN.
5. Flag bit, RC2IF, will be set when reception is
complete. An interrupt will be generated if
enable bit, RC2IE, was set.
6. Read the RCSTA2 register to get the 9th bit (if
enabled) and determine if any error occurred
during reception.
7. Read the 8-bit received data by reading the
RCREG2 register.
8. If any error occurred, clear the error by clearing
bit, CREN.
9. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
TABLE 19-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on Page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 57
PIR3 —LCDIF RC2IF TX2IF —CCP2IF CCP1IF —60
PIE3 —LCDIE RC2IE TX2IE —CCP2IE CCP1IE —60
IPR3 —LCDIP RC2IP TX2IP —CCP2IP CCP1IP —60
RCSTA2 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 62
RCREG2 AUSART Receive Register 62
TXSTA2 CSRC TX9 TXEN SYNC —BRGH TRMT TX9D 62
SPBRG2 AUSART Baud Rate Generator Register 62
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception.
2010 Microchip Technology Inc. DS39770C-page 271
PIC18F85J90 FAMILY
20.0 10-BIT ANALOG-TO-DIGITAL
CONVERTER (A/D) MODULE
The Analog-to-Digital (A/D) Converter module has
12 inputs for all PIC18F85J90 family devices. This
module allows conversion of an analog input signal to
a corresponding 10-bit digital number.
The module has five registers:
• A/D Result High Register (ADRESH)
• A/D Result Low Register (ADRESL)
• A/D Control Register 0 (ADCON0)
• A/D Control Register 1 (ADCON1)
• A/D Control Register 2 (ADCON2)
The ADCON0 register, shown in Register 20-1,
controls the operation of the A/D module. The
ADCON1 register, shown in Register 20-2, configures
the functions of the port pins. The ADCON2 register,
shown in Register 20-3, configures the A/D clock
source, programmed acquisition time and justification.
REGISTER 20-1: ADCON0: A/D CONTROL REGISTER 0
R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ADCAL — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 ADCAL: A/D Calibration bit
1 = Calibration is performed on next A/D conversion
0 = Normal A/D Converter operation (no calibration is performed)
bit 6 Unimplemented: Read as ‘0’
bit 5-2 CHS<3:0>: Analog Channel Select bits
0000 = Channel 00 (AN0)
0001 = Channel 01 (AN1)
0010 = Channel 02 (AN2)
0011 = Channel 03 (AN3)
0100 = Channel 04 (AN4)
0101 = Channel 05 (AN5)
0110 = Channel 06 (AN6)
0111 = Channel 07 (AN7)
1000 = Channel 08 (AN8)
1001 = Channel 09 (AN9)
1010 = Channel 10 (AN10)
1011 = Channel 11 (AN11)
11xx = Unused
bit 1 GO/DONE: A/D Conversion Status bit
When ADON = 1:
1 = A/D conversion in progress
0 = A/D Idle
bit 0 ADON: A/D On bit
1 = A/D Converter module is enabled
0 = A/D Converter module is disabled
PIC18F85J90 FAMILY
DS39770C-page 272 2010 Microchip Technology Inc.
REGISTER 20-2: ADCON1: A/D CONTROL REGISTER 1
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—— VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 Unimplemented: Read as ‘0’
bit 5 VCFG1: Voltage Reference Configuration bit (VREF- source)
1 =V
REF- (AN2)
0 =AV
SS
bit 4 VCFG0: Voltage Reference Configuration bit (VREF+ source)
1 =V
REF+ (AN3)
0 =AV
DD
bit 3-0 PCFG<3:0>: A/D Port Configuration Control bits:
A = Analog input D = Digital I/O
PCFG<3:0> AN11 AN10 AN9 AN8 AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0
0000 AAAAAAAAAAAA
0001 AAAAAAAAAAAA
0010 AAAAAAAAAAAA
0011 AAAAAAAAAAAA
0100 DAAAAAAAAAAA
0101 DDAAAAAAAAAA
0110 DDDAAAAAAAAA
0111 DDDDAAAAAAAA
1000 DDDDDAAAAAAA
1001 DDDDDDAAAAAA
1010 DDDDDDDAAAAA
1011 DDDDDDDDAAAA
1100 DDDDDDDDDAAA
1101 DDDDDDDDDDAA
1110 DDDDDDDDDDDA
1111 DDDDDDDDDDDD
2010 Microchip Technology Inc. DS39770C-page 273
PIC18F85J90 FAMILY
REGISTER 20-3: ADCON2: A/D CONTROL REGISTER 2
R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 ADFM: A/D Result Format Select bit
1 = Right justified
0 = Left justified
bit 6 Unimplemented: Read as ‘0’
bit 5-3 ACQT<2:0>: A/D Acquisition Time Select bits
111 = 20 T
AD
110 = 16 TAD
101 = 12 TAD
100 = 8 TAD
011 = 6 TAD
010 = 4 TAD
001 = 2 TAD
000 = 0 TAD(1)
bit 2-0 ADCS<2:0>: A/D Conversion Clock Select bits
111 = FRC (clock derived from A/D RC oscillator)(1)
110 = FOSC/64
101 = FOSC/16
100 = FOSC/4
011 = FRC (clock derived from A/D RC oscillator)(1)
010 = FOSC/32
001 = FOSC/8
000 = FOSC/2
Note 1: If the A/D FRC clock source is selected, a delay of one TCY (instruction cycle) is added before the A/D
clock starts. This allows the SLEEP instruction to be executed before starting a conversion.
PIC18F85J90 FAMILY
DS39770C-page 274 2010 Microchip Technology Inc.
The analog reference voltage is software selectable to
either the device’s positive and negative supply voltage
(AVDD and AVSS), or the voltage level on the
RA3/AN3/VREF+ and RA2/AN2/VREF- pins.
The A/D Converter has a unique feature of being able
to operate while the device is in Sleep mode. To
operate in Sleep, the A/D conversion clock must be
derived from the A/D’s internal RC oscillator.
The output of the sample and hold is the input into the
converter, which generates the result via successive
approximation.
Each port pin associated with the A/D Converter can be
configured as an analog input or as a digital I/O. The
ADRESH and ADRESL registers contain the result of
the A/D conversion. When the A/D conversion is com-
plete, the result is loaded into the ADRESH:ADRESL
register pair, the GO/DONE bit (ADCON0<1>) is
cleared and A/D Interrupt Flag bit, ADIF, is set.
A device Reset forces all registers to their Reset state.
This forces the A/D module to be turned off and any
conversion in progress is aborted. The value in the
ADRESH:ADRESL register pair is not modified for a
Power-on Reset. These registers will contain unknown
data after a Power-on Reset.
The block diagram of the A/D module is shown in
Figure 20-1.
FIGURE 20-1: A/D BLOCK DIAGRAM(1,2)
(Input Voltage)
VAIN
VREF+
Reference
Voltage
VDD
VCFG<1:0>
CHS<3:0>
AN7
AN6
AN4
AN3
AN2
AN1
AN0
0111
0110
0100
0011
0010
0001
0000
10-Bit
A/D
VREF-
VSS
Converter
AN11
AN10
AN9
AN8
1011
1010
1001
1000
Note 1: Channels AN15 through AN12 are not available on 64-pin devices.
2: I/O pins have diode protection to VDD and VSS.
AN5
0101
2010 Microchip Technology Inc. DS39770C-page 275
PIC18F85J90 FAMILY
After the A/D module has been configured as desired,
the selected channel must be acquired before the
conversion is started. The analog input channels must
have their corresponding TRIS bits selected as an
input. To determine acquisition time, see Section 20.1
“A/D Acquisition Requirements”. After this acquisi-
tion time has elapsed, the A/D conversion can be
started. An acquisition time can be programmed to
occur between setting the GO/DONE bit and the actual
start of the conversion.
The following steps should be followed to do an A/D
conversion:
1. Configure the A/D module:
• Configure analog pins, voltage reference and
digital I/O (ADCON1)
• Select A/D input channel (ADCON0)
• Select A/D acquisition time (ADCON2)
• Select A/D conversion clock (ADCON2)
• Turn on A/D module (ADCON0)
2. Configure A/D interrupt (if desired):
• Clear ADIF bit
• Set ADIE bit
• Set GIE bit
3. Wait the required acquisition time (if required).
4. Start conversion:
• Set GO/DONE bit (ADCON0<1>)
5. Wait for A/D conversion to complete, by either:
• Polling for the GO/DONE bit to be cleared
OR
• Waiting for the A/D interrupt
6. Read A/D Result registers (ADRESH:ADRESL);
clear ADIF bit, if required.
7. For next conversion, go to step 1 or step 2, as
required. The A/D conversion time per bit is
defined as T
AD. A minimum wait of 2 TAD is
required before next acquisition starts.
FIGURE 20-2: ANALOG INPUT MODEL
VAIN CPIN
RSANx
5 pF
VDD
VT = 0.6V
VT = 0.6V ILEAKAGE
RIC 1k
Sampling
Switch
SS RSS
CHOLD = 25 pF
VSS
Sampling Switch
1234
(k)
VDD
±100 nA
Legend: CPIN
VT
ILEAKAGE
RIC
SS
CHOLD
= Input Capacitance
= Threshold Voltage
= Leakage Current at the pin due to
= Interconnect Resistance
= Sampling Switch
= Sample/Hold Capacitance (from DAC)
various junctions
= Sampling Switch ResistanceRSS
PIC18F85J90 FAMILY
DS39770C-page 276 2010 Microchip Technology Inc.
20.1 A/D Acquisition Requirements
For the A/D Converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 20-2. The
source impedance (RS) and the internal sampling
switch (RSS) impedance directly affect the time
required to charge the capacitor CHOLD. The sampling
switch (RSS) impedance varies over the device voltage
(VDD). The source impedance affects the offset voltage
at the analog input (due to pin leakage current). The
maximum recommended impedance for analog
sources is 2.5 k. After the analog input channel is
selected (changed), the channel must be sampled for
at least the minimum acquisition time before starting a
conversion.
To calculate the minimum acquisition time,
Equation 20-1 may be used. This equation assumes
that 1/2 LSb error is used (1024 steps for the A/D). The
1/2 LSb error is the maximum error allowed for the A/D
to meet its specified resolution.
Equation 20-3 shows the calculation of the minimum
required acquisition time, TACQ. This calculation is
based on the following application system
assumptions:
CHOLD =25 pF
Rs = 2.5 k
Conversion Error 1/2 LSb
VDD =3VRss = 2 k
Temperature = 85C (system max.)
EQUATION 20-1: ACQUISITION TIME
EQUATION 20-2: A/D MINIMUM CHARGING TIME
EQUATION 20-3: CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME
Note: When the conversion is started, the
holding capacitor is disconnected from the
input pin.
TACQ = Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient
=T
AMP + TC + TCOFF
VHOLD = (VREF – (VREF/2048)) • (1 – e(-TC/CHOLD(RIC + RSS + RS)))
or
TC = -(CHOLD)(RIC + RSS + RS) ln(1/2048)
TACQ =TAMP + TC + TCOFF
TAMP =0.2 s
TCOFF = (Temp – 25C)(0.02 s/C)
(85C – 25C)(0.02 s/C)
1.2 s
Temperature coefficient is only required for temperatures > 25C. Below 25C, TCOFF = 0 ms.
TC = -(CHOLD)(RIC + RSS + RS) ln(1/2048) s
-(25 pF) (1 k + 2 k + 2.5 k) ln(0.0004883) s
1.05 s
TACQ =0.2 s + 1 s + 1.2 s
2.4 s
2010 Microchip Technology Inc. DS39770C-page 277
PIC18F85J90 FAMILY
20.2 Selecting and Configuring
Automatic Acquisition Time
The ADCON2 register allows the user to select an
acquisition time that occurs each time the GO/DONE
bit is set.
When the GO/DONE bit is set, sampling is stopped and
a conversion begins. The user is responsible for ensur-
ing the required acquisition time has passed between
selecting the desired input channel and setting the
GO/DONE bit. This occurs when the ACQT<2:0> bits
(ADCON2<5:3>) remain in their Reset state (‘000’) and
is compatible with devices that do not offer
programmable acquisition times.
If desired, the ACQT bits can be set to select a pro-
grammable acquisition time for the A/D module. When
the GO/DONE bit is set, the A/D module continues to
sample the input for the selected acquisition time, then
automatically begins a conversion. Since the acquisi-
tion time is programmed, there may be no need to wait
for an acquisition time between selecting a channel and
setting the GO/DONE bit.
In either case, when the conversion is completed, the
GO/DONE bit is cleared, the ADIF flag is set and the
A/D begins sampling the currently selected channel
again. If an acquisition time is programmed, there is
nothing to indicate if the acquisition time has ended or
if the conversion has begun.
20.3 Selecting the A/D Conversion
Clock
The A/D conversion time per bit is defined as TAD. The
A/D conversion requires 11 T
AD per 10-bit conversion.
The source of the A/D conversion clock is software
selectable.
There are seven possible options for TAD:
•2 T
OSC
•4 TOSC
•8 TOSC
•16 TOSC
•32 TOSC
•64 T
OSC
• Internal RC Oscillator
For correct A/D conversions, the A/D conversion clock
(T
AD) must be as short as possible but greater than the
minimum TAD (see parameter 130 in Table 26-25 for
more information).
Table 20-1 shows the resultant TAD times derived from
the device operating frequencies and the A/D clock
source selected.
TABLE 20-1: TAD vs. DEVICE OPERATING
FREQUENCIES
20.4 Configuring Analog Port Pins
The ADCON1, TRISA, TRISF and TRISH registers
control the operation of the A/D port pins. The port pins
needed as analog inputs must have their correspond-
ing TRIS bits set (input). If the TRIS bit is cleared
(output), the digital output level (VOH or VOL) will be
converted.
The A/D operation is independent of the state of the
CHS<3:0> bits and the TRIS bits.
AD Clock Source (TAD)Maximum
Device
Frequency
Operation ADCS<2:0>
2 T
OSC 000 2.86 MHz
4 T
OSC 100 5.71 MHz
8 TOSC 001 11.43 MHz
16 TOSC 101 22.86 MHz
32 T
OSC 010 40.0 MHz
64 TOSC 110 40.0 MHz
RC(2) x11 1.00 MHz(1)
Note 1: The RC source has a typical TAD time of
4s.
2: For device frequencies above 1 MHz, the
device must be in Sleep mode for the entire
conversion or the A/D accuracy may be out
of specification.
Note 1: When reading the PORT register, all pins
configured as analog input channels will
read as cleared (a low level). Pins config-
ured as digital inputs will convert an
analog input. Analog levels on a digitally
configured input will be accurately
converted.
2: Analog levels on any pin defined as a
digital input may cause the digital input
buffer to consume current out of the
device’s specification limits.
PIC18F85J90 FAMILY
DS39770C-page 278 2010 Microchip Technology Inc.
20.5 A/D Conversions
Figure 20-3 shows the operation of the A/D Converter
after the GO/DONE bit has been set and the
ACQT<2:0> bits are cleared. A conversion is started
after the following instruction to allow entry into Sleep
mode before the conversion begins.
Figure 20-4 shows the operation of the A/D Converter
after the GO/DONE bit has been set, the ACQT<2:0>
bits are set to ‘010’ and selecting a 4 T
AD acquisition
time before the conversion starts.
Clearing the GO/DONE bit during a conversion will
abort the current conversion. The A/D Result register
pair will NOT be updated with the partially completed
A/D conversion sample. This means the
ADRESH:ADRESL registers will continue to contain
the value of the last completed conversion (or the last
value written to the ADRESH:ADRESL registers).
After the A/D conversion is completed or aborted, a
2T
AD wait is required before the next acquisition can be
started. After this wait, acquisition on the selected
channel is automatically started.
20.6 Use of the CCP2 Trigger
An A/D conversion can be started by the “Special Event
Trigger” of the CCP2 module. This requires that the
CCP2M<3:0> bits (CCP2CON<3:0>) be programmed
as ‘1011’ and that the A/D module is enabled (ADON
bit is set). When the trigger occurs, the GO/DONE bit
will be set, starting the A/D acquisition and conversion
and the Timer1 (or Timer3) counter will be reset to zero.
Timer1 (or Timer3) is reset to automatically repeat the
A/D acquisition period with minimal software overhead
(moving ADRESH/ADRESL to the desired location).
The appropriate analog input channel must be selected
and the minimum acquisition period is either timed by
the user, or an appropriate TACQ time is selected before
the Special Event Trigger sets the GO/DONE bit (starts
a conversion).
If the A/D module is not enabled (ADON is cleared), the
Special Event Trigger will be ignored by the A/D module
but will still reset the Timer1 (or Timer3) counter.
FIGURE 20-3: A/D CONVERSION TAD CYCLES (ACQT<2:0> = 000, TACQ = 0)
FIGURE 20-4: A/D CONVERSION TAD CYCLES (ACQT<2:0> = 010, TACQ = 4 TAD)
Note: The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
TAD1 TAD2TAD3TAD4 TAD5TAD6 TAD7TAD8TAD11
Set GO/DONE bit
Holding capacitor is disconnected from analog input (typically 100 ns)
TAD9 TAD10
TCY - TAD
Next Q4: ADRESH/ADRESL is loaded, GO/DONE bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
Conversion starts
b0
b9 b6 b5 b4 b3 b2 b1
b8 b7
1234567811
Set GO/DONE bit
(Holding capacitor is disconnected)
910
Next Q4: ADRESH:ADRESL is loaded, GO/DONE bit is cleared,
ADIF bit is set, holding capacitor is reconnected to analog input.
Conversion starts
123 4
(Holding capacitor continues
acquiring input)
TACQT Cycles TAD Cycles
Automatic
Acquisition
Time
b0b9 b6 b5 b4 b3 b2 b1
b8 b7
2010 Microchip Technology Inc. DS39770C-page 279
PIC18F85J90 FAMILY
20.7 A/D Converter Calibration
The A/D Converter in the PIC18F85J90 family of
devices includes a self-calibration feature which com-
pensates for any offset generated within the module.
The calibration process is automated and is initiated by
setting the ADCAL bit (ADCON0<7>). The next time
the GO/DONE bit is set, the module will perform a
“dummy” conversion (that is, with reading none of the
input channels) and store the resulting value internally
to compensate for offset. Thus, subsequent offsets will
be compensated.
The calibration process assumes that the device is in a
relatively steady-state operating condition. If A/D
calibration is used, it should be performed after each
device Reset or if there are other major changes in
operating conditions.
20.8 Operation in Power-Managed
Modes
The selection of the automatic acquisition time and A/D
conversion clock is determined in part by the clock
source and frequency while in a power-managed
mode.
If the A/D is expected to operate while the device is in
a power-managed mode, the ACQT<2:0> and
ADCS<2:0> bits in ADCON2 should be updated in
accordance with the power-managed mode clock that
will be used. After the power-managed mode is entered
(either of the power-managed Run modes), an A/D
acquisition or conversion may be started. Once an
acquisition or conversion is started, the device should
continue to be clocked by the same power-managed
mode clock source until the conversion has been
completed. If desired, the device may be placed into
the corresponding power-managed Idle mode during
the conversion.
If the power-managed mode clock frequency is less
than 1 MHz, the A/D RC clock source should be
selected.
Operation in the Sleep mode requires the A/D RC clock
to be selected. If bits ACQT<2:0> are set to ‘000’ and
a conversion is started, the conversion will be delayed
one instruction cycle to allow execution of the SLEEP
instruction and entry to Sleep mode. The IDLEN and
SCS bits in the OSCCON register must have already
been cleared prior to starting the conversion.
TABLE 20-2: SUMMARY OF A/D REGISTERS
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 57
PIR1 —ADIFRC1IF TX1IF SSPIF —TMR2IF TMR1IF 60
PIE1 —ADIERC1IE TX1IE SSPIE —TMR2IE TMR1IE 60
IPR1 —ADIPRC1IP TX1IP SSPIP —TMR2IP TMR1IP 60
PIR3 —LCDIF RC2IF TX2IF — CCP2IF CCP1IF —60
PIE3 —LCDIE RC2IE TX2IE — CCP2IE CCP1IE —60
IPR3 —LCDIP RC2IP TX2IP — CCP2IP CCP1IP —60
ADRESH A/D Result Register High Byte 59
ADRESL A/D Result Register Low Byte 59
ADCON0 ADCAL — CHS3 CHS3 CHS1 CHS0 GO/DONE ADON 59
ADCON1 —— VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 59
ADCON2 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 59
CCP2CON — — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 61
PORTA RA7(1) RA6(1) RA5 RA4 RA3 RA2 RA1 RA0 61
TRISA TRISA7(1) TRISA6(1) TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 60
PORTF RF7 RF6 RF5 RF4 RF3 RF2 RF1 —60
TRISF TRISF5 TRISF4 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 —60
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.
Note 1: RA6/RA7 and their associated latch and direction bits are configured as port pins only when the internal
oscillator is selected as the default clock source (FOSC2 Configuration bit = 0); otherwise, they are
disabled and these bits read as ‘0’.
PIC18F85J90 FAMILY
DS39770C-page 280 2010 Microchip Technology Inc.
NOTES:
2010 Microchip Technology Inc. DS39770C-page 281
PIC18F85J90 FAMILY
21.0 COMPARATOR MODULE
The analog comparator module contains two
comparators that can be configured in a variety of
ways. The inputs can be selected from the analog
inputs multiplexed with pins RF1 through RF6, as well
as the on-chip voltage reference (see Section 22.0
“Comparator Voltage Reference Module”). The digi-
tal outputs (normal or inverted) are available at the pin
level and can also be read through the control register.
The CMCON register (Register 21-1) selects the
comparator input and output configuration. Block
diagrams of the various comparator configurations are
shown in Figure 21-1.
REGISTER 21-1: CMCON: COMPARATOR MODULE CONTROL REGISTER
R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 R/W-1
C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 C2OUT: Comparator 2 Output bit
When C2INV = 0:
1 = C2 VIN+ > C2 VIN-
0 = C2 VIN+ < C2 VIN-
When C2INV = 1:
1 = C2 VIN+ < C2 VIN-
0 = C2 VIN+ > C2 VIN-
bit 6 C1OUT: Comparator 1 Output bit
When C1INV = 0:
1 = C1 VIN+ > C1 VIN-
0 = C1 VIN+ < C1 VIN-
When C1INV = 1:
1 = C1 VIN+ < C1 VIN-
0 = C1 VIN+ > C1 VIN-
bit 5 C2INV: Comparator 2 Output Inversion bit
1 = C2 output inverted
0 = C2 output not inverted
bit 4 C1INV: Comparator 1 Output Inversion bit
1 = C1 output inverted
0 = C1 output not inverted
bit 3 CIS: Comparator Input Switch bit
When CM<2:0> = 110:
1 =C1 VIN- connects to RF5/AN10/CVREF
C2 VIN- connects to RF3/AN8
0 =C1 V
IN- connects to RF6/AN11
C2 VIN- connects to RF4/AN9
bit 2-0 CM<2:0>: Comparator Mode bits
Figure 21-1 shows the Comparator modes and the CM<2:0> bit settings.
PIC18F85J90 FAMILY
DS39770C-page 282 2010 Microchip Technology Inc.
21.1 Comparator Configuration
There are eight modes of operation for the compara-
tors, shown in Figure 21-1. Bits, CM<2:0> of the
CMCON register, are used to select these modes. The
TRISF register controls the data direction of the
comparator pins for each mode. If the Comparator
mode is changed, the comparator output level may not
be valid for the specified mode change delay shown in
Section 26.0 “Electrical Characteristics”.
FIGURE 21-1: COMPARATOR I/O OPERATING MODES
Note: Comparator interrupts should be disabled
during a Comparator mode change;
otherwise, a false interrupt may occur.
C1
VIN-
VIN+Off (Read as ‘0’)
Comparator Outputs Disabled
A
A
CM<2:0> = 000
C2
VIN-
VIN+Off (Read as ‘0’)
A
A
C1
VIN-
VIN+C1OUT
Two Independent Comparators
A
A
CM<2:0> = 010
C2
VIN-
VIN+C2OUT
A
A
C1
VIN-
VIN+C1OUT
Two Common Reference Comparators
A
A
CM<2:0> = 100
C2
VIN-
VIN+C2OUT
A
D
C2
VIN-
VIN+Off (Read as ‘0’)
One Independent Comparator with Output
D
D
CM<2:0> = 001
C1
VIN-
VIN+C1OUT
A
A
C1
VIN-
VIN+Off (Read as ‘0’)
Comparators Off (POR Default Value)
D
D
CM<2:0> = 111
C2
VIN-
VIN+Off (Read as ‘0’)
D
D
C1
VIN-
VIN+C1OUT
Four Inputs Multiplexed to Two Comparators
A
A
CM<2:0> = 110
C2
VIN-
VIN+C2OUT
A
A
From VREF module
CIS = 0
CIS = 1
CIS = 0
CIS = 1
C1
VIN-
VIN+C1OUT
Two Common Reference Comparators with Outputs
A
A
CM<2:0> = 101
C2
VIN-
VIN+C2OUT
A
D
A = Analog Input, port reads zeros always D = Digital Input CIS (CMCON<3>) is the Comparator Input Switch
CVREF
C1
VIN-
VIN+C1OUT
Two Independent Comparators with Outputs
A
A
CM<2:0> = 011
C2
VIN-
VIN+C2OUT
A
A
RF1/AN6/C2OUT*/SEG19
RF2/AN7/C1OUT*/SEG20
* Setting the TRISF<2:1> bits will disable the comparator outputs by configuring the pins as inputs.
RF6/AN11/
RF5/AN10/
RF4/AN9/
RF3/AN8/
CVREF/SEG23
RF6/AN11/
RF5/AN10/
RF4/AN9/
RF3/AN8/
CVREF/SEG23
RF6/AN11/
RF5/AN10/
RF4/AN9/
RF3/AN8/
CVREF/SEG23
RF6/AN11/
RF5/AN10/
RF4/AN9/
RF3/AN8/
CVREF/SEG23
RF6/AN11/
RF5/AN10/
RF4/AN9/
RF3/AN8/
CVREF/SEG23
RF2/AN7/C1OUT*/SEG20
RF6/AN11/
RF5/AN10/
RF4/AN9/
RF3/AN8/
CVREF/SEG23
RF1/AN6/C2OUT*/SEG19
RF2/AN7/C1OUT*/
RF6/AN11/
RF5/AN10/
RF4/AN9/
RF3/AN8/
CVREF/SEG23
RF6/AN11/
RF5/AN10/
RF4/AN9/
RF3/AN8/
CVREF/SEG23
SEG24
SEG22
SEG21
SEG24
SEG22
SEG21
SEG24
SEG22
SEG21
SEG24
SEG22
SEG21
SEG24
SEG22
SEG21
SEG24
SEG22
SEG21
SEG24
SEG22
SEG21
SEG24
SEG20
SEG22
SEG21
2010 Microchip Technology Inc. DS39770C-page 283
PIC18F85J90 FAMILY
21.2 Comparator Operation
A single comparator is shown in Figure 21-2, along with
the relationship between the analog input levels and
the digital output. When the analog input at VIN+ is less
than the analog input VIN-, the output of the comparator
is a digital low level. When the analog input at VIN+ is
greater than the analog input VIN-, the output of the
comparator is a digital high level. The shaded areas of
the output of the comparator in Figure 21-2 represent
the uncertainty due to input offsets and response time.
21.3 Comparator Reference
Depending on the comparator operating mode, either
an external or internal voltage reference may be used.
The analog signal present at VIN- is compared to the
signal at VIN+ and the digital output of the comparator
is adjusted accordingly (Figure 21-2).
FIGURE 21-2: SINGLE COMPARATOR
21.3.1 EXTERNAL REFERENCE SIGNAL
When external voltage references are used, the
comparator module can be configured to have the com-
parators operate from the same or different reference
sources. However, threshold detector applications may
require the same reference. The reference signal must
be between VSS and VDD and can be applied to either
pin of the comparator(s).
21.3.2 INTERNAL REFERENCE SIGNAL
The comparator module also allows the selection of an
internally generated voltage reference from the
comparator voltage reference module. This module is
described in more detail in Section 22.0 “Comparator
Voltage Reference Module”.
The internal reference is only available in the mode
where four inputs are multiplexed to two comparators
(CM<2:0> = 110). In this mode, the internal voltage
reference is applied to the VIN+ pin of both
comparators.
21.4 Comparator Response Time
Response time is the minimum time, after selecting a
new reference voltage or input source, before the
comparator output has a valid level. If the internal ref-
erence is changed, the maximum delay of the internal
voltage reference must be considered when using the
comparator outputs; otherwise, the maximum delay of
the comparators should be used (see Section 26.0
“Electrical Characteristics”).
21.5 Comparator Outputs
The comparator outputs are read through the CMCON
register. These bits are read-only. The comparator
outputs may also be directly output to the RF1 and RF2
I/O pins. When enabled, multiplexors in the output path
of the RF1 and RF2 pins will switch and the output of
each pin will be the unsynchronized output of the
comparator. The uncertainty of each of the
comparators is related to the input offset voltage and
the response time given in the specifications.
Figure 21-3 shows the comparator output block
diagram.
The TRISF bits will still function as an output enable/
disable for the RF1 and RF2 pins while in this mode.
The polarity of the comparator outputs can be changed
using the C2INV and C1INV bits (CMCON<5:4>).
–
+
VIN+
VIN-
Output
Output
VIN-
VIN+
Note 1: When reading the PORT register, all pins
configured as analog inputs will read as
‘0’. Pins configured as digital inputs will
convert an analog input according to the
Schmitt Trigger input specification.
2: Analog levels on any pin defined as a
digital input may cause the input buffer to
consume more current than is specified.
PIC18F85J90 FAMILY
DS39770C-page 284 2010 Microchip Technology Inc.
FIGURE 21-3: COMPARATOR OUTPUT BLOCK DIAGRAM
21.6 Comparator Interrupts
The comparator interrupt flag is set whenever there is
a change in the output value of either comparator.
Software will need to maintain information about the
status of the output bits, as read from CMCON<7:6>, to
determine the actual change that occurred. The CMIF
bit (PIR2<6>) is the Comparator Interrupt Flag. The
CMIF bit must be reset by clearing it. Since it is also
possible to write a ‘1’ to this register, a simulated
interrupt may be initiated.
Both the CMIE bit (PIE2<6>) and the PEIE bit
(INTCON<6>) must be set to enable the interrupt. In
addition, the GIE bit (INTCON<7>) must also be set. If
any of these bits are clear, the interrupt is not enabled,
though the CMIF bit will still be set if an interrupt
condition occurs.
The user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
a) Any read or write of CMCON will end the
mismatch condition.
b) Clear flag bit, CMIF.
A mismatch condition will continue to set flag bit CMIF.
Reading CMCON will end the mismatch condition and
allow flag bit CMIF to be cleared.
21.7 Comparator Operation
During Sleep
When a comparator is active and the device is placed
in Sleep mode, the comparator remains active and the
interrupt is functional, if enabled. This interrupt will
wake-up the device from Sleep mode, when enabled.
Each operational comparator will consume additional
current, as shown in the comparator specifications. To
minimize power consumption while in Sleep mode, turn
off the comparators (CM<2:0> = 111) before entering
Sleep. If the device wakes up from Sleep, the contents
of the CMCON register are not affected.
21.8 Effects of a Reset
A device Reset forces the CMCON register to its Reset
state, causing the comparator modules to be turned off
(CM<2:0> = 111). However, the input pins (RF3
through RF6) are configured as analog inputs by
default on device Reset. The I/O configuration for these
pins is determined by the setting of the PCFG<3:0> bits
(ADCON1<3:0>). Therefore, device current is
minimized when analog inputs are present at Reset
time.
DQ
EN
To RF1 or
RF2 Pin
Bus
Data
Set
MULTIPLEX
CMIF
bit
-+
Port Pins
Read CMCON
Reset
From
Other
Comparator
CxINV
DQ
EN CL
Note: If a change in the CMCON register
(C1OUT or C2OUT) should occur when a
read operation is being executed (start of
the Q2 cycle), then the CMIF (PIR2<6>)
interrupt flag may not get set.
2010 Microchip Technology Inc. DS39770C-page 285
PIC18F85J90 FAMILY
21.9 Analog Input Connection
Considerations
A simplified circuit for an analog input is shown in
Figure 21-4. Since the analog pins are connected to a
digital output, they have reverse biased diodes to VDD
and VSS. The analog input, therefore, must be between
VSS and VDD. If the input voltage deviates from this
range by more than 0.6V in either direction, one of the
diodes is forward biased and a latch-up condition may
occur. A maximum source impedance of 10 k is
recommended for the analog sources. Any external
component connected to an analog input pin, such as
a capacitor or a Zener diode, should have very little
leakage current.
FIGURE 21-4: COMPARATOR ANALOG INPUT MODEL
TABLE 21-1: REGISTERS ASSOCIATED WITH COMPARATOR MODULE
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 57
PIR2 OSCFIF CMIF — — BCLIF LVDIF TMR3IF —60
PIE2 OSCFIE CMIE — — BCLIE LVDIE TMR3IE —60
IPR2 OSCFIP CMIP — — BCLIP LVDIP TMR3IP —60
CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 59
CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 59
PORTF RF7 RF6 RF5 RF4 RF3 RF2 RF1 —60
LATF LATF7 LATF6 LATF5 LATF4 LATF3 LATF2 LATF1 —60
TRISF TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 —60
Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the comparator module.
VA
RS < 10k
AIN
CPIN
5 pF
VDD
VT = 0.6V
VT = 0.6V
RIC
ILEAKAGE
±500 nA
VSS
Legend: CPIN = Input Capacitance
VT= Threshold Voltage
ILEAKAGE = Leakage Current at the pin due to various junctions
RIC = Interconnect Resistance
RS= Source Impedance
VA = Analog Voltage
Comparator
Input
PIC18F85J90 FAMILY
DS39770C-page 286 2010 Microchip Technology Inc.
NOTES:
2010 Microchip Technology Inc. DS39770C-page 287
PIC18F85J90 FAMILY
22.0 COMPARATOR VOLTAGE
REFERENCE MODULE
The comparator voltage reference is a 16-tap resistor
ladder network that provides a selectable reference
voltage. Although its primary purpose is to provide a
reference for the analog comparators, it may also be
used independently of them.
A block diagram of the module is shown in Figure 22-1.
The resistor ladder is segmented to provide two ranges
of CVREF values and has a power-down function to
conserve power when the reference is not being used.
The module’s supply reference can be provided from
either device VDD/VSS or an external voltage reference.
22.1 Configuring the Comparator
Voltage Reference
The comparator voltage reference module is controlled
through the CVRCON register (Register 22-1). The
comparator voltage reference provides two ranges of
output voltage, each with 16 distinct levels.
The range to be used is selected by the CVRR bit
(CVRCON<5>). The primary difference between the
ranges is the size of the steps selected by the CVREF
Selection bits (CVR<3:0>), with one range offering finer
resolution. The equations used to calculate the output
of the comparator voltage reference are as follows:
If CVRR = 1:
CVREF = ((CVR<3:0>)/24) x (CVRSRC)
If CVRR = 0:
CVREF =(CVRSRC/4) + ((CVR<3:0>)/32) x
(CVRSRC)
The comparator reference supply voltage can come
from either VDD and VSS, or the external VREF+ and
VREF- that are multiplexed with RA2 and RA3. The
voltage source is selected by the CVRSS bit
(CVRCON<4>).
The settling time of the comparator voltage reference
must be considered when changing the CVREF
output (see Table 26-3 in Section 26.0 “Electrical
Characteristics”).
REGISTER 22-1: CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CVREN CVROE(1) CVRR CVRSS CVR3 CVR2 CVR1 CVR0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 CVREN: Comparator Voltage Reference Enable bit
1 =CV
REF circuit powered on
0 =CV
REF circuit powered down
bit 6 CVROE: Comparator VREF Output Enable bit(1)
1 =CVREF voltage level is also output on the RF5/AN10/CVREF/SEG23 pin
0 =CV
REF voltage is disconnected from the RF5/AN10/CVREF/SEG23 pin
bit 5 CVRR: Comparator VREF Range Selection bit
1 = 0 to 0.667 CVRSRC, with CVRSRC/24 step size (low range)
0 = 0.25 CVRSRC to 0.75 CVRSRC, with CVRSRC/32 step size (high range)
bit 4 CVRSS: Comparator VREF Source Selection bit
1 = Comparator reference source, CVRSRC = (VREF+) – (VREF-)
0 = Comparator reference source, CVRSRC = VDD – VSS
bit 3-0 CVR3:CVR0: Comparator VREF Value Selection bits (0 (CVR<3:0>) 15)
When CVRR = 1:
CVREF = ((CVR<3:0>)/24) (CVRSRC)
When CVRR = 0:
CVREF = (CVRSRC/4) + ((CVR<3:0>)/32) (CVRSRC)
Note 1: CVROE overrides the TRISF<5> bit setting.
PIC18F85J90 FAMILY
DS39770C-page 288 2010 Microchip Technology Inc.
FIGURE 22-1: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM
22.2 Voltage Reference Accuracy/Error
The full range of voltage reference cannot be realized
due to the construction of the module. The transistors
on the top and bottom of the resistor ladder network
(Figure 22-1) keep CVREF from approaching the refer-
ence source rails. The voltage reference is derived
from the reference source; therefore, the CVREF output
changes with fluctuations in that source. The tested
absolute accuracy of the voltage reference can be
found in Section 26.0 “Electrical Characteristics”.
22.3 Operation During Sleep
When the device wakes up from Sleep through an
interrupt or a Watchdog Timer time-out, the contents of
the CVRCON register are not affected. To minimize
current consumption in Sleep mode, the voltage
reference should be disabled.
22.4 Effects of a Reset
A device Reset disables the voltage reference by
clearing bit, CVREN (CVRCON<7>). This Reset also
disconnects the reference from the RA2 pin by clearing
bit, CVROE (CVRCON<6>) and selects the high-voltage
range by clearing bit, CVRR (CVRCON<5>). The CVR
value select bits are also cleared.
22.5 Connection Considerations
The voltage reference module operates independently
of the comparator module. The output of the reference
generator may be connected to the RF5 pin if the
CVROE bit is set. Enabling the voltage reference out-
put onto RA2 when it is configured as a digital input will
increase current consumption. Connecting RF5 as a
digital output with CVRSS enabled will also increase
current consumption.
The RF5 pin can be used as a simple D/A output with
limited drive capability. Due to the limited current drive
capability, a buffer must be used on the voltage
reference output for external connections to VREF.
Figure 22-2 shows an example buffering technique.
16-to-1 MUX
CVR<3:0>
8R
R
CVREN
CVRSS = 0
VDD
VREF+CVRSS = 1
8R
CVRSS = 0
VREF-CVRSS = 1
R
R
R
R
R
R
16 Steps
CVRR
CVREF
2010 Microchip Technology Inc. DS39770C-page 289
PIC18F85J90 FAMILY
FIGURE 22-2: COMPARATOR VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE
TABLE 22-1: REGISTERS ASSOCIATED WITH COMPARATOR VOLTAGE REFERENCE
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 59
CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 59
TRISF TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 —60
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used with the comparator voltage reference.
CVREF Output
+
–
CVREF
Module
Voltage
Reference
Output
Impedance
R(1)
RF5
Note 1: R is dependent upon the Comparator Voltage Reference bits, CVRCON<5> and CVRCON<3:0>.
PIC18F85J90
PIC18F85J90 FAMILY
DS39770C-page 290 2010 Microchip Technology Inc.
NOTES:
2010 Microchip Technology Inc. DS39770C-page 291
PIC18F85J90 FAMILY
23.0 SPECIAL FEATURES OF THE
CPU
PIC18F85J90 family devices include several features
intended to maximize reliability and minimize cost
through elimination of external components. These are:
• Oscillator Selection
• Resets:
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Brown-out Reset (BOR)
• Interrupts
• Watchdog Timer (WDT)
• Fail-Safe Clock Monitor
• Two-Speed Start-up
• Code Protection
• In-Circuit Serial Programming
The oscillator can be configured for the application
depending on frequency, power, accuracy and cost. All
of the options are discussed in detail in Section 3.0
“Oscillator Configurations”.
A complete discussion of device Resets and interrupts
is available in previous sections of this data sheet.
In addition to their Power-up and Oscillator Start-up
Timers provided for Resets, the PIC18F85J90 family
family of devices have a configurable Watchdog Timer
which is controlled in software.
The inclusion of an internal RC oscillator also provides
the additional benefits of a Fail-Safe Clock Monitor
(FSCM) and Two-Speed Start-up. FSCM provides for
background monitoring of the peripheral clock and
automatic switchover in the event of its failure.
Two-Speed Start-up enables code to be executed
almost immediately on start-up, while the primary clock
source completes its start-up delays.
All of these features are enabled and configured by
setting the appropriate Configuration register bits.
23.1 Configuration Bits
The Configuration bits can be programmed (read as
‘0’), or left unprogrammed (read as ‘1’), to select
various device configurations. These bits are mapped
starting at program memory location 300000h. A
complete list is shown in Table 23-2. A detailed
explanation of the various bit functions is provided in
Register 23-1 through Register 23-5.
23.1.1 CONSIDERATIONS FOR
CONFIGURING THE PIC18F85J90
FAMILY DEVICES
Unlike some previous PIC18 microcontrollers,
PIC18F85J90 family devices do not use persistent
memory registers to store configuration information.
The Configuration registers, CONFIG1L through
CONFIG4H, are implemented as volatile memory.
Immediately after power-up, or after a device Reset, the
microcontroller hardware automatically loads the
CONFIG1L through CONFIG4L registers with configura-
tion data stored in nonvolatile Flash program memory.
The last four words of Flash program memory, known as
the Flash Configuration Words (FCW), are used to store
the configuration data.
Table 23-1 provides the Flash program memory
mapping, which will be loaded into the corresponding
Configuration register.
When creating applications for these devices, users
should always specifically allocate the location of the
Flash Configuration Word for configuration data. This is
to make certain that program code is not stored in this
address when the code is compiled.
The volatile memory cells used for the Configuration
bits always reset to ‘1’ on Power-on Resets. For all
other types of Reset events, the previously
programmed values are maintained and used without
reloading from program memory.
The four Most Significant bits of CONFIG1H,
CONFIG2H and CONFIG3H in program memory
should also be ‘1111’. This makes these Configuration
Words appear to be NOP instructions in the remote
event that their locations are ever executed by
accident. Since Configuration bits are not implemented
in the corresponding locations, writing ‘1’s to these
locations has no effect on device operation.
To prevent inadvertent configuration changes during
code execution, all programmable Configuration bits
are write-once. After a bit is initially programmed during
a power cycle, it cannot be written to again. Changing
a device configuration requires that power to the device
be cycled.
TABLE 23-1: MAPPING OF THE FLASH
CONFIGURATION WORDS TO
THE CONFIGURATION
REGISTERS
Configuration
Byte
Code Space
Address
Configuration
Register Address
CONFIG1L XXXF8h 300000h
CONFIG1H XXXF9h 300001h
CONFIG2L XXXFAh 300002h
CONFIG2H XXXFBh 300003h
CONFIG3L XXXFCh 300004h
CONFIG3H XXXFDh 300005h
Legend: Unimplemented in PIC18F85J90 family
devices.
PIC18F85J90 FAMILY
DS39770C-page 292 2010 Microchip Technology Inc.
TABLE 23-2: CONFIGURATION BITS AND DEVICE IDs
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Default/
Unprogrammed
Value(1)
300000h CONFIG1L DEBUG XINST STVREN ————WDTEN111- ---1
300001h CONFIG1H —(2) —(2) —(2) —(2) —(3) CP0 — — ---- 01--
300002h CONFIG2L IESO FCMEN — — — FOSC2 FOSC1 FOSC0 11-- -111
300003h CONFIG2H —(2) —(2) —(2) —(2) WDTPS3 WDTPS2 WDTPS1 WDTPS0 ---- 1111
300005h CONFIG3H —(2) —(2) —(2) —(2) — — — CCP2MX ---- ---1
3FFFFEh DEVID1 DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 xxxx xxxx(4)
3FFFFFh DEVID2 DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 0000 10x1(4)
Legend: x = unknown, - = unimplemented. Shaded cells are unimplemented, read as ‘0’.
Note 1: Values reflect the unprogrammed state as received from the factory and following Power-on Resets. In all other Reset
states, the configuration bytes maintain their previously programmed states.
2: The value of these bits in program memory should always be ‘1’. This ensures that the location is executed as a NOP if it
is accidentally executed.
3: This bit should always be maintained as ‘0’.
4: See Register 23-6 and Register 23-7 for DEVID values. These registers are read-only and cannot be programmed by
the user.
2010 Microchip Technology Inc. DS39770C-page 293
PIC18F85J90 FAMILY
REGISTER 23-1: CONFIG1L: CONFIGURATION REGISTER 1 LOW (BYTE ADDRESS 300000h)
R/WO-1 R/WO-1 R/WO-1 U-0 U-0 U-0 U-0 R/WO-1
DEBUG XINST STVREN ————WDTEN
bit 7 bit 0
Legend:
R = Readable bit WO = Write-Once bit U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed ‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7 DEBUG: Background Debugger Enable bit
1 = Background debugger disabled; RB6 and RB7 configured as general purpose I/O pins
0 = Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug
bit 6 XINST: Extended Instruction Set Enable bit
1 = Instruction set extension and Indexed Addressing mode enabled
0 = Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
bit 5 STVREN: Stack Overflow/Underflow Reset Enable bit
1 = Reset on stack overflow/underflow enabled
0 = Reset on stack overflow/underflow disabled
bit 4-1 Unimplemented: Read as ‘0’
bit 0 WDTEN: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled (control is placed on the SWDTEN bit)
REGISTER 23-2: CONFIG1H: CONFIGURATION REGISTER 1 HIGH (BYTE ADDRESS 300001h)
U-0 U-0 U-0 U-0 U-0 R/WO-1 U-0 U-0
—(1) —(1) —(1) —(1) —(2) CP0 — —
bit 7 bit 0
Legend:
R = Readable bit WO = Write-Once bit U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed ‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-3 Unimplemented: Read as ‘0’
bit 2 CP0: Code Protection bit
1 = Program memory is not code-protected
0 = Program memory is code-protected
bit 1-0 Unimplemented: Read as ‘0’
Note 1: The value of these bits in program memory should always be ‘1’. This ensures that the location is
executed as a NOP if it is accidentally executed.
2: This bit should always be maintained as ‘0’.
PIC18F85J90 FAMILY
DS39770C-page 294 2010 Microchip Technology Inc.
REGISTER 23-3: CONFIG2L: CONFIGURATION REGISTER 2 LOW (BYTE ADDRESS 300002h)
R/WO-1 R/WO-1 U-0 U-0 U-0 R/WO-1 R/WO-1 R/WO-1
IESO FCMEN — — — FOSC2 FOSC1 FOSC0
bit 7 bit 0
Legend:
R = Readable bit WO = Write-Once bit U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed ‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7 IESO: Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit
1 = Two-Speed Start-up is enabled
0 = Two-Speed Start-up is disabled
bit 6 FCMEN: Fail-Safe Clock Monitor Enable bit
1 = Fail-Safe Clock Monitor is enabled
0 = Fail-Safe Clock Monitor is disabled
bit 5-3 Unimplemented: Read as ‘0’
bit 2-0 FOSC<2:0>: Oscillator Selection bits
111 = OSC1/OSC2 as primary; EC oscillator with CLKO function and software controlled
PLL (EC+PLL)
110 = OSC1/OSC2 as primary; EC oscillator with CLKO function (EC)
101 = OSC1/OSC2 as primary; HS oscillator with software controlled PLL (HS+PLL)
100 = OSC1/OSC2 as primary; HS oscillator (HS)
011 = INTOSC with CLKO as primary; port function on RA7; EC oscillator with CLKO function and
software controlled PLL (EC+PLL)
010 = INTOSC with CLKO as primary; port function on RA7; EC oscillator with CLKO function
001 = INTOSC as primary with port function on RA6/RA7; HS oscillator with software controlled
PLL (HS+PLL)
000 = INTOSC as primary with port function on RA6/RA7; HS oscillator (HS)
2010 Microchip Technology Inc. DS39770C-page 295
PIC18F85J90 FAMILY
REGISTER 23-4: CONFIG2H: CONFIGURATION REGISTER 2 HIGH (BYTE ADDRESS 300003h)
U-0 U-0 U-0 U-0 R/WO-1 R/WO-1 R/WO-1 R/WO-1
—(1) —(1) —(1) —(1) WDTPS3 WDTPS2 WDTPS1 WDTPS0
bit 7 bit 0
Legend:
R = Readable bit WO = Write-Once bit U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed ‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-4 Unimplemented: Read as ‘0’
bit 3-0 WDTPS<3:0>: Watchdog Timer Postscale Select bits
1111 = 1:32,768
1110 = 1:16,384
1101 = 1:8,192
1100 = 1:4,096
1011 = 1:2,048
1010 = 1:1,024
1001 = 1:512
1000 = 1:256
0111 = 1:128
0110 = 1:64
0101 = 1:32
0100 = 1:16
0011 = 1:8
0010 = 1:4
0001 = 1:2
0000 = 1:1
Note 1: The value of these bits in program memory should always be ‘1’. This ensures that the location is
executed as a NOP if it is accidentally executed.
REGISTER 23-5: CONFIG3H: CONFIGURATION REGISTER 3 HIGH (BYTE ADDRESS 300005h)
U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/WO-1
—(1) —(1) —(1) —(1) — — — CCP2MX
bit 7 bit 0
Legend:
R = Readable bit WO = Write-Once bit U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed ‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-1 Unimplemented: Read as ‘0’
bit 0 CCP2MX: CCP2 MUX bit
1 = CCP2 is multiplexed with RC1
0 = CCP2 is multiplexed with RE7
Note 1: The value of these bits in program memory should always be ‘1’. This ensures that the location is
executed as a NOP if it is accidentally executed.
PIC18F85J90 FAMILY
DS39770C-page 296 2010 Microchip Technology Inc.
REGISTER 23-6: DEVID1: DEVICE ID REGISTER 1 FOR PIC18F85J90 FAMILY DEVICES
RRRRRRRR
DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0
bit 7 bit 0
Legend:
R = Read-only bit
bit 7-5 DEV<2:0>: Device ID bits
111 = PIC18F85J90
101 = PIC18F84J90
100 = PIC18F83J90
011 = PIC18F65J90
001 = PIC18F64J90
000 = PIC18F63J90
bit 4-0 REV<4:0>: Revision ID bits
These bits are used to indicate the device revision.
REGISTER 23-7: DEVID2: DEVICE ID REGISTER 2 FOR PIC18F85J90 FAMILY DEVICES
RRRRRRRR
DEV10(1) DEV9(1) DEV8(1) DEV7(1) DEV6(1) DEV5(1) DEV4(1) DEV3(1)
bit 7 bit 0
Legend:
R = Read-only bit
bit 7-0 DEV<10:3>: Device ID bits(1)
These bits are used with the DEV<2:0> bits in the Device ID Register 1 to identify the part number.
0011 1000 = PIC18F6XJ90/8XJ90 devices
Note 1: The values for DEV<10:3> may be shared with other device families. The specific device is always
identified by using the entire DEV<10:0> bit sequence.
2010 Microchip Technology Inc. DS39770C-page 297
PIC18F85J90 FAMILY
23.2 Watchdog Timer (WDT)
For PIC18F85J90 family devices, the WDT is driven by
the INTRC oscillator. When the WDT is enabled, the
clock source is also enabled. The nominal WDT period is
4 ms and has the same stability as the INTRC oscillator.
The 4 ms period of the WDT is multiplied by a 16-bit
postscaler. Any output of the WDT postscaler is
selected by a multiplexor, controlled by the WDTPS bits
in Configuration Register 2H. Available periods range
from 4 ms to 131.072 seconds (2.18 minutes). The
WDT and postscaler are cleared whenever a SLEEP or
CLRWDT instruction is executed, or a clock failure
(primary or Timer1 oscillator) has occurred.
23.2.1 CONTROL REGISTER
The WDTCON register (Register 23-8) is a readable
and writable register. The SWDTEN bit enables or dis-
ables WDT operation. This allows software to override
the WDTEN Configuration bit and enable the WDT only
if it has been disabled by the Configuration bit.
FIGURE 23-1: WDT BLOCK DIAGRAM
Note 1: The CLRWDT and SLEEP instructions
clear the WDT and postscaler counts
when executed.
2: When a CLRWDT instruction is executed,
the postscaler count will be cleared.
INTRC Oscillator
WDT
Wake-up from
Reset
WDT
WDT Counter
Programmable Postscaler
1:1 to 1:32,768
Enable WDT
WDTPS<3:0>
SWDTEN
CLRWDT
4
Power-Managed
Reset
All Device Resets
Sleep
INTRC Control
128 Modes
PIC18F85J90 FAMILY
DS39770C-page 298 2010 Microchip Technology Inc.
TABLE 23-3: SUMMARY OF WATCHDOG TIMER REGISTERS
REGISTER 23-8: WDTCON: WATCHDOG TIMER CONTROL REGISTER
R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0
REGSLP(1) — — — — — —SWDTEN
(2)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 REGSLP: Voltage Regulator Low-Power Operation Enable bit(1)
1 = On-chip regulator enters low-power operation when device enters Sleep mode
0 = On-chip regulator continues to operate normally in Sleep mode
bit 6-1 Unimplemented: Read as ‘0’
bit 0 SWDTEN: Software Controlled Watchdog Timer Enable bit(2)
1 = Watchdog Timer is on
0 = Watchdog Timer is off
Note 1: The REGSLP bit is automatically cleared when a Low-Voltage Detect condition occurs.
2: This bit has no effect if the Configuration bit, WDTEN, is enabled.
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values
on page
RCON IPEN —CM RI TO PD POR BOR 58
WDTCON REGSLP — — — — — —SWDTEN 58
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Watchdog Timer.
2010 Microchip Technology Inc. DS39770C-page 299
PIC18F85J90 FAMILY
23.3 On-Chip Voltage Regulator
All of the PIC18F85J90 family devices power their core
digital logic at a nominal 2.5V. For designs that are
required to operate at a higher typical voltage, such as
3.3V, all devices in the PIC18F85J90 family incorporate
an on-chip regulator that allows the device to run its
core logic from VDD.
The regulator is controlled by the ENVREG pin. Tying
VDD to the pin enables the regulator, which in turn, pro-
vides power to the core from the other VDD pins. When
the regulator is enabled, a low-ESR filter capacitor
must be connected to the VDDCORE/VCAP pin
(Figure 23-2). This helps to maintain the stability of the
regulator. The recommended value for the filter capac-
itor is provided in Section 26.3 “DC Characteristics:
PIC18F84J90 Family (Industrial)”.
If ENVREG is tied to VSS, the regulator is disabled. In
this case, separate power for the core logic at a nomi-
nal 2.5V must be supplied to the device on the
VDDCORE/VCAP pin to run the I/O pins at higher voltage
levels, typically 3.3V. Alternatively, the VDDCORE/VCAP
and VDD pins can be tied together to operate at a lower
nominal voltage. Refer to Figure 23-2 for possible
configurations.
23.3.1 VOLTAGE REGULATION AND
LOW-VOLTAGE DETECTION
When it is enabled, the on-chip regulator provides a
constant voltage of 2.5V nominal to the digital core
logic. The regulator can provide this level from a VDD of
about 2.5V, all the way up to the device’s VDDMAX. It
does not have the capability to boost VDD levels below
2.5V.
In order to prevent “brown-out” conditions, when the
voltage drops too low for the regulator, the regulator
enters Tracking mode. In Tracking mode, the regulator
output follows VDD, with a typical voltage drop of
100 mV.
The on-chip regulator includes a simple Low-Voltage
Detect (LVD) circuit. If VDD drops too low to maintain
approximately 2.45V on VDDCORE, the circuit sets the
Low-Voltage Detect Interrupt Flag, LVDIF (PIR2<2>),
and clears the REGSLP (WDTCON<7>) bit if it was set.
This can be used to generate an interrupt and put the
application into a low-power operational mode, or trig-
ger an orderly shutdown. Low-Voltage Detection is only
available when the regulator is enabled.
FIGURE 23-2: CONNECTIONS FOR THE
ON-CHIP REGULATOR
VDD
ENVREG
VDDCORE/VCAP
VSS
PIC18F85J90
3.3V(1)
2.5V(1)
VDD
ENVREG
VDDCORE/VCAP
VSS
PIC18F85J90
CF
3.3V
Regulator Enabled (ENVREG tied to VDD):
Regulator Disabled (ENVREG tied to ground):
VDD
ENVREG
VDDCORE/VCAP
VSS
PIC18F85J90
2.5V(1)
Regulator Disabled (VDD tied to VDDCORE):
Note 1: These are typical operating voltages. Refer
to Section 26.1 “DC Characteristics:
Supply Voltage” for the full operating
ranges of VDD and VDDCORE.
PIC18F85J90 FAMILY
DS39770C-page 300 2010 Microchip Technology Inc.
23.3.2 ON-CHIP REGULATOR AND BOR
When the on-chip regulator is enabled, PIC18F85J90
family devices also have a simple Brown-out Reset
capability. If the voltage supplied to the regulator falls to
a level that is inadequate to maintain a regulated output
for full-speed operation, the regulator Reset circuitry
will generate a Brown-out Reset. This event is captured
by the BOR flag bit (RCON<0>).
The operation of the BOR is described in more detail in
Section 5.4 “Brown-out Reset (BOR)” and
Section 5.4.1 “Detecting BOR”.
23.3.3 POWER-UP REQUIREMENTS
The on-chip regulator is designed to meet the power-up
requirements for the device. If the application does not
use the regulator, then strict power-up conditions must
be adhered to. While powering up, VDDCORE must
never exceed VDD by 0.3 volts.
23.3.4 OPERATION IN SLEEP MODE
When enabled, the on-chip regulator always consumes
a small incremental amount of current over IDD. This
includes when the device is in Sleep mode, even
though the core digital logic does not require power. To
provide additional savings in applications where power
resources are critical, the regulator can be configured
to automatically disable itself whenever the device
goes into Sleep mode. This feature is controlled by the
REGSLP bit (WDTCON<7>). Setting this bit disables
the regulator in Sleep mode, and reduces its current
consumption to a minimum.
Substantial Sleep mode power savings can be
obtained by setting the REGSLP bit, but device
wake-up time will increase in order to ensure the
regulator has enough time to stabilize.
The REGSLP bit is automatically cleared by hardware
when a Low-Voltage Detect condition occurs. The
REGSLP bit can be set again in software, which would
continue to keep the voltage regulator in Low-Power
mode. This, however, is not recommended if any write
operations to the Flash will be performed.
23.4 Two-Speed Start-up
The Two-Speed Start-up feature helps to minimize the
latency period, from oscillator start-up to code execu-
tion, by allowing the microcontroller to use the INTRC
oscillator as a clock source until the primary clock
source is available. It is enabled by setting the IESO
Configuration bit.
Two-Speed Start-up should be enabled only if the
primary oscillator mode is HS or HSPLL
(Crystal-Based) modes. Since the EC and ECPLL
modes do not require an OST start-up delay,
Two-Speed Start-up should be disabled.
When enabled, Resets and wake-ups from Sleep mode
cause the device to configure itself to run from the inter-
nal oscillator block as the clock source, following the
time-out of the Power-up Timer after a Power-on Reset
is enabled. This allows almost immediate code
execution while the primary oscillator starts and the
OST is running. Once the OST times out, the device
automatically switches to PRI_RUN mode.
In all other power-managed modes, Two-Speed
Start-up is not used. The device will be clocked by the
currently selected clock source until the primary clock
source becomes available. The setting of the IESO bit
is ignored.
FIGURE 23-3: TIMING TRANSITION FOR TWO-SPEED START-UP (INTRC TO HSPLL)
Q1 Q3 Q4
OSC1
Peripheral
Program PC PC + 2
INTRC
PLL Clock
Q1
PC + 6
Q2
Output
Q3 Q4 Q1
CPU Clock
PC + 4
Clock
Counter
Q2 Q2 Q3
Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
Wake from Interrupt Event
TPLL(1)
12 n-1n
Clock
OSTS bit Set
Transition
TOST(1)
2010 Microchip Technology Inc. DS39770C-page 301
PIC18F85J90 FAMILY
23.4.1 SPECIAL CONSIDERATIONS FOR
USING TWO-SPEED START-UP
While using the INTRC oscillator in Two-Speed
Start-up, the device still obeys the normal command
sequences for entering power-managed modes,
including serial SLEEP instructions (refer to
Section 4.1.4 “Multiple Sleep Commands”). In prac-
tice, this means that user code can change the
SCS<1:0> bit settings or issue SLEEP instructions
before the OST times out. This would allow an applica-
tion to briefly wake-up, perform routine “housekeeping”
tasks and return to Sleep before the device starts to
operate from the primary oscillator.
User code can also check if the primary clock source is
currently providing the device clocking by checking the
status of the OSTS bit (OSCCON<3>). If the bit is set,
the primary oscillator is providing the clock. Otherwise,
the internal oscillator block is providing the clock during
wake-up from Reset or Sleep mode.
23.5 Fail-Safe Clock Monitor
The Fail-Safe Clock Monitor (FSCM) allows the
microcontroller to continue operation in the event of an
external oscillator failure by automatically switching the
device clock to the internal oscillator block. The FSCM
function is enabled by setting the FCMEN Configuration
bit.
When FSCM is enabled, the INTRC oscillator runs at
all times to monitor clocks to peripherals and provides
a backup clock in the event of a clock failure. Clock
monitoring (shown in Figure 23-4) is accomplished by
creating a sample clock signal which is the INTRC out-
put divided by 64. This allows ample time between
FSCM sample clocks for a peripheral clock edge to
occur. The peripheral device clock and the sample
clock are presented as inputs to the Clock Monitor latch
(CM). The CM is set on the falling edge of the device
clock source but cleared on the rising edge of the
sample clock.
FIGURE 23-4: FSCM BLOCK DIAGRAM
Clock failure is tested for on the falling edge of the
sample clock. If a sample clock falling edge occurs
while CM is still set, a clock failure has been detected
(Figure 23-5). This causes the following:
• the FSCM generates an oscillator fail interrupt by
setting bit, OSCFIF (PIR2<7>);
• the device clock source is switched to the internal
oscillator block (OSCCON is not updated to show
the current clock source – this is the fail-safe
condition); and
• the WDT is reset.
During switchover, the postscaler frequency from the
internal oscillator block may not be sufficiently stable
for timing-sensitive applications. In these cases, it may
be desirable to select another clock configuration and
enter an alternate power-managed mode. This can be
done to attempt a partial recovery or execute a
controlled shutdown. See Section 4.1.4 “Multiple
Sleep Commands” and Section 23.4.1 “Special
Considerations for Using Two-Speed Start-up” for
more details.
The FSCM will detect failures of the primary or secondary
clock sources only. If the internal oscillator block fails, no
failure would be detected, nor would any action be
possible.
23.5.1 FSCM AND THE WATCHDOG TIMER
Both the FSCM and the WDT are clocked by the
INTRC oscillator. Since the WDT operates with a
separate divider and counter, disabling the WDT has
no effect on the operation of the INTRC oscillator when
the FSCM is enabled.
As already noted, the clock source is switched to the
INTRC clock when a clock failure is detected; this may
mean a substantial change in the speed of code execu-
tion. If the WDT is enabled with a small prescale value,
a decrease in clock speed allows a WDT time-out to
occur and a subsequent device Reset. For this reason,
Fail-Safe Clock Monitor events also reset the WDT and
postscaler, allowing it to start timing from when execu-
tion speed was changed and decreasing the likelihood
of an erroneous time-out.
If the interrupt is disabled, subsequent interrupts while
in Idle mode will cause the CPU to begin executing
instructions while being clocked by the INTRC source.
Peripheral
INTRC ÷ 64
S
C
Q
(32 s) 488 Hz
(2.048 ms)
Clock Monitor
Latch (CM)
(edge-triggered)
Clock
Failure
Detected
Source
Clock
Q
PIC18F85J90 FAMILY
DS39770C-page 302 2010 Microchip Technology Inc.
FIGURE 23-5: FSCM TIMING DIAGRAM
23.5.2 EXITING FAIL-SAFE OPERATION
The fail-safe condition is terminated by either a device
Reset or by entering a power-managed mode. On
Reset, the controller starts the primary clock source
specified in Configuration Register 2H (with any
required start-up delays that are required for the oscil-
lator mode, such as OST or PLL timer). The INTRC
oscillator provides the device clock until the primary
clock source becomes ready (similar to a Two-Speed
Start-up). The clock source is then switched to the
primary clock (indicated by the OSTS bit in the
OSCCON register becoming set). The Fail-Safe Clock
Monitor then resumes monitoring the peripheral clock.
The primary clock source may never become ready
during start-up. In this case, operation is clocked by the
INTOSC multiplexor. The OSCCON register will remain
in its Reset state until a power-managed mode is
entered.
23.5.3 FSCM INTERRUPTS IN
POWER-MANAGED MODES
By entering a power-managed mode, the clock
multiplexor selects the clock source selected by the
OSCCON register. Fail-Safe Clock Monitoring of the
power-managed clock source resumes in the
power-managed mode.
If an oscillator failure occurs during power-managed
operation, the subsequent events depend on whether
or not the oscillator failure interrupt is enabled. If
enabled (OSCFIF = 1), code execution will be clocked
by the INTRC multiplexor. An automatic transition back
to the failed clock source will not occur.
23.5.4 POR OR WAKE-UP FROM SLEEP
The FSCM is designed to detect oscillator failure at any
point after the device has exited Power-on Reset
(POR) or low-power Sleep mode. When the primary
device clock is either EC or INTRC mode, monitoring
can begin immediately following these events.
For HS or HSPLL modes, the situation is somewhat dif-
ferent. Since the oscillator may require a start-up time
considerably longer than the FSCM sample clock time,
a false clock failure may be detected. To prevent this,
the internal oscillator block is automatically configured
as the device clock and functions until the primary clock
is stable (the OST and PLL timers have timed out). This
is identical to Two-Speed Start-up mode. Once the
primary clock is stable, the INTRC returns to its role as
the FSCM source.
As noted in Section 23.4.1 “Special Considerations
for Using Two-Speed Start-up”, it is also possible to
select another clock configuration and enter an alternate
power-managed mode while waiting for the primary
clock to become stable. When the new power-managed
mode is selected, the primary clock is disabled.
OSCFIF
CM Output
Device
Clock
Output
Sample Clock
Failure
Detected
Oscillator
Failure
Note: The device clock is normally at a much higher frequency than the sample clock. The relative frequencies in
this example have been chosen for clarity.
(Q)
CM Test CM Test CM Test
Note: The same logic that prevents false
oscillator failure interrupts on POR, or
wake from Sleep, will also prevent the
detection of the oscillator’s failure to start
at all following these events. This can be
avoided by monitoring the OSTS bit and
using a timing routine to determine if the
oscillator is taking too long to start. Even
so, no oscillator failure interrupt will be
flagged.
2010 Microchip Technology Inc. DS39770C-page 303
PIC18F85J90 FAMILY
23.6 Program Verification and
Code Protection
For all devices in the PIC18F85J90 family of devices,
the on-chip program memory space is treated as a
single block. Code protection for this block is controlled
by one Configuration bit, CP0. This bit inhibits external
reads and writes to the program memory space. It has
no direct effect in normal execution mode.
23.6.1 CONFIGURATION REGISTER
PROTECTION
The Configuration registers are protected against
untoward changes or reads in two ways. The primary
protection is the write-once feature of the Configuration
bits which prevents reconfiguration once the bit has
been programmed during a power cycle. To safeguard
against unpredictable events, Configuration bit
changes resulting from individual cell-level disruptions
(such as ESD events) will cause a parity error and
trigger a device Reset.
The data for the Configuration registers is derived from
the Flash Configuration Words in program memory.
When the CP0 bit set, the source data for device
configuration is also protected as a consequence.
23.7 In-Circuit Serial Programming
PIC18F85J90 family microcontrollers can be serially
programmed while in the end application circuit. This is
simply done with two lines for clock and data and three
other lines for power, ground and the programming
voltage. This allows customers to manufacture boards
with unprogrammed devices and then program the
microcontroller just before shipping the product. This
also allows the most recent firmware or a custom
firmware to be programmed.
23.8 In-Circuit Debugger
When the DEBUG Configuration bit is programmed to
a ‘0’, the In-Circuit Debugger functionality is enabled.
This function allows simple debugging functions when
used with MPLAB® IDE. When the microcontroller has
this feature enabled, some resources are not available
for general use. Table 23-4 shows which resources are
required by the background debugger.
TABLE 23-4: DEBUGGER RESOURCES
I/O pins: RB6, RB7
Stack: 2 levels
Program Memory: 512 bytes
Data Memory: 10 bytes
PIC18F85J90 FAMILY
DS39770C-page 304 2010 Microchip Technology Inc.
NOTES:
2010 Microchip Technology Inc. DS39770C-page 305
PIC18F85J90 FAMILY
24.0 INSTRUCTION SET SUMMARY
The PIC18F85J90 family of devices incorporate the
standard set of 75 PIC18 core instructions, as well as
an extended set of 8 new instructions for the optimiza-
tion of code that is recursive or that utilizes a software
stack. The extended set is discussed later in this
section.
24.1 Standard Instruction Set
The standard PIC18 instruction set adds many
enhancements to the previous PIC® MCU instruction
sets, while maintaining an easy migration from these
PIC MCU instruction sets. Most instructions are a
single program memory word (16 bits), but there are
four instructions that require two program memory
locations.
Each single-word instruction is a 16-bit word divided
into an opcode, which specifies the instruction type and
one or more operands, which further specify the
operation of the instruction.
The instruction set is highly orthogonal and is grouped
into four basic categories:
•Byte-oriented operations
•Bit-oriented operations
•Literal operations
•Control operations
The PIC18 instruction set summary in Table 24-2 lists
byte-oriented, bit-oriented, literal and control
operations. Table 24-1 shows the opcode field
descriptions.
Most byte-oriented instructions have three operands:
1. The file register (specified by ‘f’)
2. The destination of the result (specified by ‘d’)
3. The accessed memory (specified by ‘a’)
The file register designator, ‘f’, specifies which file reg-
ister is to be used by the instruction. The destination
designator, ‘d’, specifies where the result of the
operation is to be placed. If ‘d’ is zero, the result is
placed in the WREG register. If ‘d’ is one, the result is
placed in the file register specified in the instruction.
All bit-oriented instructions have three operands:
1. The file register (specified by ‘f’)
2. The bit in the file register (specified by ‘b’)
3. The accessed memory (specified by ‘a’)
The bit field designator, ‘b’, selects the number of the bit
affected by the operation, while the file register desig-
nator, ‘f’, represents the number of the file in which the
bit is located.
The literal instructions may use some of the following
operands:
• A literal value to be loaded into a file register
(specified by ‘k’)
• The desired FSR register to load the literal value
into (specified by ‘f’)
• No operand required
(specified by ‘—’)
The control instructions may use some of the following
operands:
• A program memory address (specified by ‘n’)
• The mode of the CALL or RETURN instructions
(specified by ‘s’)
• The mode of the table read and table write
instructions (specified by ‘m’)
• No operand required
(specified by ‘—’)
All instructions are a single word, except for four
double-word instructions. These instructions were
made double-word to contain the required information
in 32 bits. In the second word, the 4 MSbs are ‘1’s. If
this second word is executed as an instruction (by
itself), it will execute as a NOP.
All single-word instructions are executed in a single
instruction cycle, unless a conditional test is true or the
program counter is changed as a result of the instruc-
tion. In these cases, the execution takes two instruction
cycles with the additional instruction cycle(s) executed
as a NOP.
The double-word instructions execute in two instruction
cycles.
One instruction cycle consists of four oscillator periods.
Thus, for an oscillator frequency of 4 MHz, the normal
instruction execution time is 1 s. If a conditional test is
true, or the program counter is changed as a result of
an instruction, the instruction execution time is 2 s.
Two-word branch instructions (if true) would take 3 s.
Figure 24-1 shows the general formats that the instruc-
tions can have. All examples use the convention ‘nnh’
to represent a hexadecimal number.
The Instruction Set Summary, shown in Table 24-2,
lists the standard instructions recognized by the
Microchip MPASMTM Assembler.
Section 24.1.1 “Standard Instruction Set” provides
a description of each instruction.
PIC18F85J90 FAMILY
DS39770C-page 306 2010 Microchip Technology Inc.
TABLE 24-1: OPCODE FIELD DESCRIPTIONS
Field Description
aRAM access bit:
a = 0: RAM location in Access RAM (BSR register is ignored)
a = 1: RAM bank is specified by BSR register
bbb Bit address within an 8-bit file register (0 to 7).
BSR Bank Select Register. Used to select the current RAM bank.
C, DC, Z, OV, N ALU Status bits: Carry, Digit Carry, Zero, Overflow, Negative.
dDestination select bit:
d = 0: store result in WREG
d = 1: store result in file register f
dest Destination: either the WREG register or the specified register file location.
f8-bit Register file address (00h to FFh), or 2-bit FSR designator (0h to 3h).
fs12-bit Register file address (000h to FFFh). This is the source address.
fd12-bit Register file address (000h to FFFh). This is the destination address.
GIE Global Interrupt Enable bit.
kLiteral field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value).
label Label name.
mm The mode of the TBLPTR register for the table read and table write instructions.
Only used with table read and table write instructions:
*No Change to register (such as TBLPTR with table reads and writes)
*+ Post-Increment register (such as TBLPTR with table reads and writes)
*- Post-Decrement register (such as TBLPTR with table reads and writes)
+* Pre-Increment register (such as TBLPTR with table reads and writes)
nThe relative address (2’s complement number) for relative branch instructions or the direct address for
Call/Branch and Return instructions.
PC Program Counter.
PCL Program Counter Low Byte.
PCH Program Counter High Byte.
PCLATH Program Counter High Byte Latch.
PCLATU Program Counter Upper Byte Latch.
PD Power-Down bit.
PRODH Product of Multiply High Byte.
PRODL Product of Multiply Low Byte.
sFast Call/Return mode select bit:
s = 0: do not update into/from shadow registers
s = 1: certain registers loaded into/from shadow registers (Fast mode)
TBLPTR 21-bit Table Pointer (points to a Program Memory location).
TABLAT 8-bit Table Latch.
TO Time-out bit.
TOS Top-of-Stack.
uUnused or Unchanged.
WDT Watchdog Timer.
WREG Working register (accumulator).
xDon’t care (‘0’ or ‘1’). The assembler will generate code with x = 0. It is the recommended form of use for
compatibility with all Microchip software tools.
zs7-bit offset value for Indirect Addressing of register files (source).
zd7-bit offset value for Indirect Addressing of register files (destination).
{ } Optional argument.
[text] Indicates an Indexed Address.
(text) The contents of text.
[expr]<n> Specifies bit n of the register indicated by the pointer expr.
Assigned to.
< > Register bit field.
In the set of.
italics User-defined term (font is Courier).
2010 Microchip Technology Inc. DS39770C-page 307
PIC18F85J90 FAMILY
FIGURE 24-1: GENERAL FORMAT FOR INSTRUCTIONS
Byte-oriented file register operations
15 10 9 8 7 0
d = 0 for result destination to be WREG register
OPCODE d a f (FILE #)
d = 1 for result destination to be file register (f)
a = 0 to force Access Bank
Bit-oriented file register operations
15 12 11 9 8 7 0
OPCODE b (BIT #) a f (FILE #)
b = 3-bit position of bit in file register (f)
Literal operations
15 8 7 0
OPCODE k (literal)
k = 8-bit immediate value
Byte to Byte move operations (2-word)
15 12 11 0
OPCODE f (Source FILE #)
CALL, GOTO and Branch operations
15 8 7 0
OPCODE n<7:0> (literal)
n = 20-bit immediate value
a = 1 for BSR to select bank
f = 8-bit file register address
a = 0 to force Access Bank
a = 1 for BSR to select bank
f = 8-bit file register address
15 12 11 0
1111 n<19:8> (literal)
15 12 11 0
1111 f (Destination FILE #)
f = 12-bit file register address
Control operations
Example Instruction
ADDWF MYREG, W, B
MOVFF MYREG1, MYREG2
BSF MYREG, bit, B
MOVLW 7Fh
GOTO Label
15 8 7 0
OPCODE S n<7:0> (literal)
15 12 11 0
1111 n<19:8> (literal)
CALL MYFUNC
15 11 10 0
OPCODE n<10:0> (literal)
S = Fast bit
BRA MYFUNC
15 8 7 0
OPCODE n<7:0> (literal) BC MYFUNC
PIC18F85J90 FAMILY
DS39770C-page 308 2010 Microchip Technology Inc.
TABLE 24-2: PIC18F85J90 FAMILY INSTRUCTION SET
Mnemonic,
Operands Description Cycles
16-Bit Instruction Word Status
Affected Notes
MSb LSb
BYTE-ORIENTED OPERATIONS
ADDWF
ADDWFC
ANDWF
CLRF
COMF
CPFSEQ
CPFSGT
CPFSLT
DECF
DECFSZ
DCFSNZ
INCF
INCFSZ
INFSNZ
IORWF
MOVF
MOVFF
MOVWF
MULWF
NEGF
RLCF
RLNCF
RRCF
RRNCF
SETF
SUBFWB
SUBWF
SUBWFB
SWAPF
TSTFSZ
XORWF
f, d, a
f, d, a
f, d, a
f, a
f, d, a
f, a
f, a
f, a
f, d, a
f, d, a
f, d, a
f, d, a
f, d, a
f, d, a
f, d, a
f, d, a
fs, fd
f, a
f, a
f, a
f, d, a
f, d, a
f, d, a
f, d, a
f, a
f, d, a
f, d, a
f, d, a
f, d, a
f, a
f, d, a
Add WREG and f
Add WREG and Carry bit to f
AND WREG with f
Clear f
Complement f
Compare f with WREG, Skip =
Compare f with WREG, Skip >
Compare f with WREG, Skip <
Decrement f
Decrement f, Skip if 0
Decrement f, Skip if Not 0
Increment f
Increment f, Skip if 0
Increment f, Skip if Not 0
Inclusive OR WREG with f
Move f
Move fs (source) to 1st word
fd (destination) 2nd word
Move WREG to f
Multiply WREG with f
Negate f
Rotate Left f through Carry
Rotate Left f (No Carry)
Rotate Right f through Carry
Rotate Right f (No Carry)
Set f
Subtract f from WREG with
Borrow
Subtract WREG from f
Subtract WREG from f with
Borrow
Swap Nibbles in f
Test f, Skip if 0
Exclusive OR WREG with f
1
1
1
1
1
1 (2 or 3)
1 (2 or 3)
1 (2 or 3)
1
1 (2 or 3)
1 (2 or 3)
1
1 (2 or 3)
1 (2 or 3)
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1 (2 or 3)
1
0010
0010
0001
0110
0001
0110
0110
0110
0000
0010
0100
0010
0011
0100
0001
0101
1100
1111
0110
0000
0110
0011
0100
0011
0100
0110
0101
0101
0101
0011
0110
0001
01da
00da
01da
101a
11da
001a
010a
000a
01da
11da
11da
10da
11da
10da
00da
00da
ffff
ffff
111a
001a
110a
01da
01da
00da
00da
100a
01da
11da
10da
10da
011a
10da
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
C, DC, Z, OV, N
C, DC, Z, OV, N
Z, N
Z
Z, N
None
None
None
C, DC, Z, OV, N
None
None
C, DC, Z, OV, N
None
None
Z, N
Z, N
None
None
None
C, DC, Z, OV, N
C, Z, N
Z, N
C, Z, N
Z, N
None
C, DC, Z, OV, N
C, DC, Z, OV, N
C, DC, Z, OV, N
None
None
Z, N
1, 2
1, 2
1,2
2
1, 2
4
4
1, 2
1, 2, 3, 4
1, 2, 3, 4
1, 2
1, 2, 3, 4
4
1, 2
1, 2
1
1, 2
1, 2
1, 2
1, 2
4
1, 2
Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that
value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is
driven low by an external device, the data will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if
assigned.
3: If the Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The
second cycle is executed as a NOP.
4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP
unless the first word of the instruction retrieves the information embedded in these 16-bits. This ensures that all
program memory locations have a valid instruction.
2010 Microchip Technology Inc. DS39770C-page 309
PIC18F85J90 FAMILY
BIT-ORIENTED OPERATIONS
BCF
BSF
BTFSC
BTFSS
BTG
f, b, a
f, b, a
f, b, a
f, b, a
f, b, a
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
Bit Toggle f
1
1
1 (2 or 3)
1 (2 or 3)
1
1001
1000
1011
1010
0111
bbba
bbba
bbba
bbba
bbba
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
None
None
None
None
None
1, 2
1, 2
3, 4
3, 4
1, 2
CONTROL OPERATIONS
BC
BN
BNC
BNN
BNOV
BNZ
BOV
BRA
BZ
CALL
CLRWDT
DAW
GOTO
NOP
NOP
POP
PUSH
RCALL
RESET
RETFIE
RETLW
RETURN
SLEEP
n
n
n
n
n
n
n
n
n
n, s
—
—
n
—
—
—
—
n
s
k
s
—
Branch if Carry
Branch if Negative
Branch if Not Carry
Branch if Not Negative
Branch if Not Overflow
Branch if Not Zero
Branch if Overflow
Branch Unconditionally
Branch if Zero
Call Subroutine 1st word
2nd word
Clear Watchdog Timer
Decimal Adjust WREG
Go to Address 1st word
2nd word
No Operation
No Operation
Pop Top of Return Stack (TOS)
Push Top of Return Stack (TOS)
Relative Call
Software Device Reset
Return from Interrupt Enable
Return with Literal in WREG
Return from Subroutine
Go into Standby mode
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
2
1 (2)
2
1
1
2
1
1
1
1
2
1
2
2
2
1
1110
1110
1110
1110
1110
1110
1110
1101
1110
1110
1111
0000
0000
1110
1111
0000
1111
0000
0000
1101
0000
0000
0000
0000
0000
0010
0110
0011
0111
0101
0001
0100
0nnn
0000
110s
kkkk
0000
0000
1111
kkkk
0000
xxxx
0000
0000
1nnn
0000
0000
1100
0000
0000
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
kkkk
kkkk
0000
0000
kkkk
kkkk
0000
xxxx
0000
0000
nnnn
1111
0001
kkkk
0001
0000
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
kkkk
kkkk
0100
0111
kkkk
kkkk
0000
xxxx
0110
0101
nnnn
1111
000s
kkkk
001s
0011
None
None
None
None
None
None
None
None
None
None
TO, PD
C
None
None
None
None
None
None
All
GIE/GIEH,
PEIE/GIEL
None
None
TO, PD
4
TABLE 24-2: PIC18F85J90 FAMILY INSTRUCTION SET (CONTINUED)
Mnemonic,
Operands Description Cycles
16-Bit Instruction Word Status
Affected Notes
MSb LSb
Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that
value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is
driven low by an external device, the data will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if
assigned.
3: If the Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The
second cycle is executed as a NOP.
4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP
unless the first word of the instruction retrieves the information embedded in these 16-bits. This ensures that all
program memory locations have a valid instruction.
PIC18F85J90 FAMILY
DS39770C-page 310 2010 Microchip Technology Inc.
LITERAL OPERATIONS
ADDLW
ANDLW
IORLW
LFSR
MOVLB
MOVLW
MULLW
RETLW
SUBLW
XORLW
k
k
k
f, k
k
k
k
k
k
k
Add Literal and WREG
AND Literal with WREG
Inclusive OR Literal with WREG
Move Literal (12-bit) 2nd word
to FSR(f) 1st word
Move Literal to BSR<3:0>
Move Literal to WREG
Multiply Literal with WREG
Return with Literal in WREG
Subtract WREG from Literal
Exclusive OR Literal with WREG
1
1
1
2
1
1
1
2
1
1
0000
0000
0000
1110
1111
0000
0000
0000
0000
0000
0000
1111
1011
1001
1110
0000
0001
1110
1101
1100
1000
1010
kkkk
kkkk
kkkk
00ff
kkkk
0000
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
C, DC, Z, OV, N
Z, N
Z, N
None
None
None
None
None
C, DC, Z, OV, N
Z, N
DATA MEMORY PROGRAM MEMORY OPERATIONS
TBLRD*
TBLRD*+
TBLRD*-
TBLRD+*
TBLWT*
TBLWT*+
TBLWT*-
TBLWT+*
Table Read
Table Read with Post-Increment
Table Read with Post-Decrement
Table Read with Pre-Increment
Table Write
Table Write with Post-Increment
Table Write with Post-Increment
Table Write with Pre-Increment
2
2
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
1000
1001
1010
1011
1100
1101
1110
1111
None
None
None
None
None
None
None
None
TABLE 24-2: PIC18F85J90 FAMILY INSTRUCTION SET (CONTINUED)
Mnemonic,
Operands Description Cycles
16-Bit Instruction Word Status
Affected Notes
MSb LSb
Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that
value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is
driven low by an external device, the data will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if
assigned.
3: If the Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The
second cycle is executed as a NOP.
4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP
unless the first word of the instruction retrieves the information embedded in these 16-bits. This ensures that all
program memory locations have a valid instruction.
2010 Microchip Technology Inc. DS39770C-page 311
PIC18F85J90 FAMILY
24.1.1 STANDARD INSTRUCTION SET
ADDLW ADD Literal to W
Syntax: ADDLW k
Operands: 0 k 255
Operation: (W) + k W
Status Affected: N, OV, C, DC, Z
Encoding: 0000 1111 kkkk kkkk
Description: The contents of W are added to the
8-bit literal ‘k’ and the result is placed in
W.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
literal ‘k’
Process
Data
Write to
W
Example: ADDLW 15h
Before Instruction
W = 10h
After Instruction
W = 25h
ADDWF ADD W to f
Syntax: ADDWF f {,d {,a}}
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (W) + (f) dest
Status Affected: N, OV, C, DC, Z
Encoding: 0010 01da ffff ffff
Description: Add W to register ‘f’. If ‘d’ is ‘0’, the
result is stored in W. If ‘d’ is ‘1’, the
result is stored back in register ‘f’.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’
Process
Data
Write to
destination
Example: ADDWF REG, 0, 0
Before Instruction
W = 17h
REG = 0C2h
After Instruction
W = 0D9h
REG = 0C2h
Note: All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in
symbolic addressing. If a label is used, the instruction format then becomes: {label} instruction argument(s).
PIC18F85J90 FAMILY
DS39770C-page 312 2010 Microchip Technology Inc.
ADDWFC ADD W and Carry bit to f
Syntax: ADDWFC f {,d {,a}}
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (W) + (f) + (C) dest
Status Affected: N,OV, C, DC, Z
Encoding: 0010 00da ffff ffff
Description: Add W, the Carry flag and data memory
location ‘f’. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed in data memory location ‘f’.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’
Process
Data
Write to
destination
Example: ADDWFC REG, 0, 1
Before Instruction
Carry bit = 1
REG = 02h
W=4Dh
After Instruction
Carry bit = 0
REG = 02h
W = 50h
ANDLW AND Literal with W
Syntax: ANDLW k
Operands: 0 k 255
Operation: (W) .AND. k W
Status Affected: N, Z
Encoding: 0000 1011 kkkk kkkk
Description: The contents of W are ANDed with the
8-bit literal ‘k’. The result is placed in W.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read literal
‘k’
Process
Data
Write to
W
Example: ANDLW 05Fh
Before Instruction
W=A3h
After Instruction
W = 03h
2010 Microchip Technology Inc. DS39770C-page 313
PIC18F85J90 FAMILY
ANDWF AND W with f
Syntax: ANDWF f {,d {,a}}
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (W) .AND. (f) dest
Status Affected: N, Z
Encoding: 0001 01da ffff ffff
Description: The contents of W are ANDed with
register ‘f’. If ‘d’ is ‘0’, the result is stored
in W. If ‘d’ is ‘1’, the result is stored back
in register ‘f’.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’
Process
Data
Write to
destination
Example: ANDWF REG, 0, 0
Before Instruction
W = 17h
REG = C2h
After Instruction
W = 02h
REG = C2h
BC Branch if Carry
Syntax: BC n
Operands: -128 n 127
Operation: if Carry bit is ‘1’,
(PC) + 2 + 2n PC
Status Affected: None
Encoding: 1110 0010 nnnn nnnn
Description: If the Carry bit is ’1’, then the program
will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
Words: 1
Cycles: 1(2)
Q Cycle Activity:
If Jump:
Q1 Q2 Q3 Q4
Decode Read literal
‘n’
Process
Data
Write to
PC
No
operation
No
operation
No
operation
No
operation
If No Jump:
Q1 Q2 Q3 Q4
Decode Read literal
‘n’
Process
Data
No
operation
Example: HERE BC 5
Before Instruction
PC = address (HERE)
After Instruction
If Carry = 1;
PC = address (HERE + 12)
If Carry = 0;
PC = address (HERE + 2)
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BCF Bit Clear f
Syntax: BCF f, b {,a}
Operands: 0 f 255
0 b 7
a [0,1]
Operation: 0 f<b>
Status Affected: None
Encoding: 1001 bbba ffff ffff
Description: Bit ‘b’ in register ‘f’ is cleared.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’
Process
Data
Write
register ‘f’
Example: BCF FLAG_REG, 7, 0
Before Instruction
FLAG_REG = C7h
After Instruction
FLAG_REG = 47h
BN Branch if Negative
Syntax: BN n
Operands: -128 n 127
Operation: if Negative bit is ‘1’,
(PC) + 2 + 2n PC
Status Affected: None
Encoding: 1110 0110 nnnn nnnn
Description: If the Negative bit is ‘1’, then the
program will branch.
The 2’s complement number, ‘2n’, is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
Words: 1
Cycles: 1(2)
Q Cycle Activity:
If Jump:
Q1 Q2 Q3 Q4
Decode Read literal
‘n’
Process
Data
Write to
PC
No
operation
No
operation
No
operation
No
operation
If No Jump:
Q1 Q2 Q3 Q4
Decode Read literal
‘n’
Process
Data
No
operation
Example: HERE BN Jump
Before Instruction
PC = address (HERE)
After Instruction
If Negative = 1;
PC = address (Jump)
If Negative = 0;
PC = address (HERE + 2)
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BNC Branch if Not Carry
Syntax: BNC n
Operands: -128 n 127
Operation: if Carry bit is ‘0’,
(PC) + 2 + 2n PC
Status Affected: None
Encoding: 1110 0011 nnnn nnnn
Description: If the Carry bit is ‘0’, then the program
will branch.
The 2’s complement number, ‘2n’, is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
Words: 1
Cycles: 1(2)
Q Cycle Activity:
If Jump:
Q1 Q2 Q3 Q4
Decode Read literal
‘n’
Process
Data
Write to
PC
No
operation
No
operation
No
operation
No
operation
If No Jump:
Q1 Q2 Q3 Q4
Decode Read literal
‘n’
Process
Data
No
operation
Example: HERE BNC Jump
Before Instruction
PC = address (HERE)
After Instruction
If Carry = 0;
PC = address (Jump)
If Carry = 1;
PC = address (HERE + 2)
BNN Branch if Not Negative
Syntax: BNN n
Operands: -128 n 127
Operation: if Negative bit is ‘0’,
(PC) + 2 + 2n PC
Status Affected: None
Encoding: 1110 0111 nnnn nnnn
Description: If the Negative bit is ‘0’, then the
program will branch.
The 2’s complement number, ‘2n’, is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
Words: 1
Cycles: 1(2)
Q Cycle Activity:
If Jump:
Q1 Q2 Q3 Q4
Decode Read literal
‘n’
Process
Data
Write to
PC
No
operation
No
operation
No
operation
No
operation
If No Jump:
Q1 Q2 Q3 Q4
Decode Read literal
‘n’
Process
Data
No
operation
Example: HERE BNN Jump
Before Instruction
PC = address (HERE)
After Instruction
If Negative = 0;
PC = address (Jump)
If Negative = 1;
PC = address (HERE + 2)
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BNOV Branch if Not Overflow
Syntax: BNOV n
Operands: -128 n 127
Operation: if Overflow bit is ‘0’,
(PC) + 2 + 2n PC
Status Affected: None
Encoding: 1110 0101 nnnn nnnn
Description: If the Overflow bit is ‘0’, then the
program will branch.
The 2’s complement number, ‘2n’, is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
Words: 1
Cycles: 1(2)
Q Cycle Activity:
If Jump:
Q1 Q2 Q3 Q4
Decode Read literal
‘n’
Process
Data
Write to
PC
No
operation
No
operation
No
operation
No
operation
If No Jump:
Q1 Q2 Q3 Q4
Decode Read literal
‘n’
Process
Data
No
operation
Example: HERE BNOV Jump
Before Instruction
PC = address (HERE)
After Instruction
If Overflow = 0;
PC = address (Jump)
If Overflow = 1;
PC = address (HERE + 2)
BNZ Branch if Not Zero
Syntax: BNZ n
Operands: -128 n 127
Operation: if Zero bit is ‘0’,
(PC) + 2 + 2n PC
Status Affected: None
Encoding: 1110 0001 nnnn nnnn
Description: If the Zero bit is ‘0’, then the program
will branch.
The 2’s complement number, ‘2n’, is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
Words: 1
Cycles: 1(2)
Q Cycle Activity:
If Jump:
Q1 Q2 Q3 Q4
Decode Read literal
‘n’
Process
Data
Write to
PC
No
operation
No
operation
No
operation
No
operation
If No Jump:
Q1 Q2 Q3 Q4
Decode Read literal
‘n’
Process
Data
No
operation
Example: HERE BNZ Jump
Before Instruction
PC = address (HERE)
After Instruction
If Zero = 0;
PC = address (Jump)
If Zero = 1;
PC = address (HERE + 2)
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BRA Unconditional Branch
Syntax: BRA n
Operands: -1024 n 1023
Operation: (PC) + 2 + 2n PC
Status Affected: None
Encoding: 1101 0nnn nnnn nnnn
Description: Add the 2’s complement number, ‘2n’,
to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is a
two-cycle instruction.
Words: 1
Cycles: 2
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read literal
‘n’
Process
Data
Write to
PC
No
operation
No
operation
No
operation
No
operation
Example: HERE BRA Jump
Before Instruction
PC = address (HERE)
After Instruction
PC = address (Jump)
BSF Bit Set f
Syntax: BSF f, b {,a}
Operands: 0 f 255
0 b 7
a [0,1]
Operation: 1 f<b>
Status Affected: None
Encoding: 1000 bbba ffff ffff
Description: Bit ‘b’ in register ‘f’ is set.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’
Process
Data
Write
register ‘f’
Example: BSF FLAG_REG, 7, 1
Before Instruction
FLAG_REG = 0Ah
After Instruction
FLAG_REG = 8Ah
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BTFSC Bit Test File, Skip if Clear
Syntax: BTFSC f, b {,a}
Operands: 0 f 255
0 b 7
a [0,1]
Operation: skip if (f<b>) = 0
Status Affected: None
Encoding: 1011 bbba ffff ffff
Description: If bit ‘b’ in register ‘f’ is ‘0’, then the next
instruction is skipped. If bit ‘b’ is ‘0’, then
the next instruction fetched during the
current instruction execution is discarded
and a NOP is executed instead, making
this a two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected. If
‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction set
is enabled, this instruction operates in
Indexed Literal Offset Addressing mode
whenever f 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’
Process
Data
No
operation
If skip:
Q1 Q2 Q3 Q4
No
operation
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Example: HERE
FALSE
TRUE
BTFSC
:
:
FLAG, 1, 0
Before Instruction
PC = address (HERE)
After Instruction
If FLAG<1> = 0;
PC = address (TRUE)
If FLAG<1> = 1;
PC = address (FALSE)
BTFSS Bit Test File, Skip if Set
Syntax: BTFSS f, b {,a}
Operands: 0 f 255
0 b < 7
a [0,1]
Operation: skip if (f<b>) = 1
Status Affected: None
Encoding: 1010 bbba ffff ffff
Description: If bit ‘b’ in register ‘f’ is ‘1’, then the next
instruction is skipped. If bit ‘b’ is ‘1’, then
the next instruction fetched during the
current instruction execution is discarded
and a NOP is executed instead, making
this a two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected. If
‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates in
Indexed Literal Offset Addressing mode
whenever f 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’
Process
Data
No
operation
If skip:
Q1 Q2 Q3 Q4
No
operation
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Example: HERE
FALSE
TRUE
BTFSS
:
:
FLAG, 1, 0
Before Instruction
PC = address (HERE)
After Instruction
If FLAG<1> = 0;
PC = address (FALSE)
If FLAG<1> = 1;
PC = address (TRUE)
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BTG Bit Toggle f
Syntax: BTG f, b {,a}
Operands: 0 f 255
0 b < 7
a [0,1]
Operation: (f<b>) f<b>
Status Affected: None
Encoding: 0111 bbba ffff ffff
Description: Bit ‘b’ in data memory location ‘f’ is
inverted.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’
Process
Data
Write
register ‘f’
Example: BTG PORTC, 4, 0
Before Instruction:
PORTC = 0111 0101 [75h]
After Instruction:
PORTC = 0110 0101 [65h]
BOV Branch if Overflow
Syntax: BOV n
Operands: -128 n 127
Operation: if Overflow bit is ‘1’,
(PC) + 2 + 2n PC
Status Affected: None
Encoding: 1110 0100 nnnn nnnn
Description: If the Overflow bit is ‘1’, then the
program will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
Words: 1
Cycles: 1(2)
Q Cycle Activity:
If Jump:
Q1 Q2 Q3 Q4
Decode Read literal
‘n’
Process
Data
Write to PC
No
operation
No
operation
No
operation
No
operation
If No Jump:
Q1 Q2 Q3 Q4
Decode Read literal
‘n’
Process
Data
No
operation
Example: HERE BOV Jump
Before Instruction
PC = address (HERE)
After Instruction
If Overflow = 1;
PC = address (Jump)
If Overflow = 0;
PC = address (HERE + 2)
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BZ Branch if Zero
Syntax: BZ n
Operands: -128 n 127
Operation: if Zero bit is ‘1’,
(PC) + 2 + 2n PC
Status Affected: None
Encoding: 1110 0000 nnnn nnnn
Description: If the Zero bit is ‘1’, then the program
will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
Words: 1
Cycles: 1(2)
Q Cycle Activity:
If Jump:
Q1 Q2 Q3 Q4
Decode Read literal
‘n’
Process
Data
Write to
PC
No
operation
No
operation
No
operation
No
operation
If No Jump:
Q1 Q2 Q3 Q4
Decode Read literal
‘n’
Process
Data
No
operation
Example: HERE BZ Jump
Before Instruction
PC = address (HERE)
After Instruction
If Zero = 1;
PC = address (Jump)
If Zero = 0;
PC = address (HERE + 2)
CALL Subroutine Call
Syntax: CALL k {,s}
Operands: 0 k 1048575
s [0,1]
Operation: (PC) + 4 TOS,
k PC<20:1>;
if s = 1
(W) WS,
(STATUS) STATUSS,
(BSR) BSRS
Status Affected: None
Encoding:
1st word (k<7:0>)
2nd word(k<19:8>)
1110
1111 110s
k19kkk k7kkk
kkkk kkkk0
kkkk8
Description: Subroutine call of entire 2-Mbyte
memory range. First, return address
(PC+ 4) is pushed onto the return stack.
If ‘s’ = 1, the W, STATUS and BSR
registers are also pushed into their
respective shadow registers, WS,
STATUSS and BSRS. If ‘s’ = 0, no
update occurs. Then, the 20-bit value ‘k’
is loaded into PC<20:1>. CALL is a
two-cycle instruction.
Words: 2
Cycles: 2
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read literal
‘k’<7:0>,
Push PC to
stack
Read literal
’k’<19:8>,
Write to PC
No
operation
No
operation
No
operation
No
operation
Example: HERE CALL THERE,1
Before Instruction
PC = address (HERE)
After Instruction
PC = address (THERE)
TOS = address (HERE + 4)
WS = W
BSRS = BSR
STATUSS = STATUS
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CLRF Clear f
Syntax: CLRF f {,a}
Operands: 0 f 255
a [0,1]
Operation: 000h f,
1 Z
Status Affected: Z
Encoding: 0110 101a ffff ffff
Description: Clears the contents of the specified
register.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’
Process
Data
Write
register ‘f’
Example: CLRF FLAG_REG,1
Before Instruction
FLAG_REG = 5Ah
After Instruction
FLAG_REG = 00h
CLRWDT Clear Watchdog Timer
Syntax: CLRWDT
Operands: None
Operation: 000h WDT,
000h WDT postscaler,
1 TO,
1 PD
Status Affected: TO, PD
Encoding: 0000 0000 0000 0100
Description: CLRWDT instruction resets the
Watchdog Timer. It also resets the
postscaler of the WDT. Status bits, TO
and PD, are set.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode No
operation
Process
Data
No
operation
Example: CLRWDT
Before Instruction
WDT Counter = ?
After Instruction
WDT Counter = 00h
WDT Postscaler = 0
TO =1
PD =1
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COMF Complement f
Syntax: COMF f {,d {,a}}
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: f dest
Status Affected: N, Z
Encoding: 0001 11da ffff ffff
Description: The contents of register ‘f’ are
complemented. If ‘d’ is ‘0’, the result is
stored in W. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’
Process
Data
Write to
destination
Example: COMF REG, 0, 0
Before Instruction
REG = 13h
After Instruction
REG = 13h
W=ECh
CPFSEQ Compare f with W, Skip if f = W
Syntax: CPFSEQ f {,a}
Operands: 0 f 255
a [0,1]
Operation: (f) – (W),
skip if (f) = (W)
(unsigned comparison)
Status Affected: None
Encoding: 0110 001a ffff ffff
Description: Compares the contents of data memory
location ‘f’ to the contents of W by
performing an unsigned subtraction.
If ‘f’ = W, then the fetched instruction is
discarded and a NOP is executed
instead, making this a two-cycle
instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’
Process
Data
No
operation
If skip:
Q1 Q2 Q3 Q4
No
operation
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Example: HERE CPFSEQ REG, 0
NEQUAL :
EQUAL :
Before Instruction
PC Address = HERE
W=?
REG = ?
After Instruction
If REG = W;
PC = Address (EQUAL)
If REG W;
PC = Address (NEQUAL)
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CPFSGT Compare f with W, Skip if f > W
Syntax: CPFSGT f {,a}
Operands: 0 f 255
a [0,1]
Operation: (f) –W),
skip if (f) > (W)
(unsigned comparison)
Status Affected: None
Encoding: 0110 010a ffff ffff
Description: Compares the contents of data memory
location ‘f’ to the contents of the W by
performing an unsigned subtraction.
If the contents of ‘f’ are greater than the
contents of WREG, then the fetched
instruction is discarded and a NOP is
executed instead, making this a
two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’
Process
Data
No
operation
If skip:
Q1 Q2 Q3 Q4
No
operation
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Example: HERE CPFSGT REG, 0
NGREATER :
GREATER :
Before Instruction
PC = Address (HERE)
W= ?
After Instruction
If REG W;
PC = Address (GREATER)
If REG W;
PC = Address (NGREATER)
CPFSLT Compare f with W, Skip if f < W
Syntax: CPFSLT f {,a}
Operands: 0 f 255
a [0,1]
Operation: (f) –W),
skip if (f) < (W)
(unsigned comparison)
Status Affected: None
Encoding: 0110 000a ffff ffff
Description: Compares the contents of data memory
location ‘f’ to the contents of W by
performing an unsigned subtraction.
If the contents of ‘f’ are less than the
contents of W, then the fetched
instruction is discarded and a NOP is
executed instead, making this a
two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
Words: 1
Cycles: 1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’
Process
Data
No
operation
If skip:
Q1 Q2 Q3 Q4
No
operation
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Example: HERE CPFSLT REG, 1
NLESS :
LESS :
Before Instruction
PC = Address (HERE)
W= ?
After Instruction
If REG < W;
PC = Address (LESS)
If REG W;
PC = Address (NLESS)
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DAW Decimal Adjust W Register
Syntax: DAW
Operands: None
Operation: If [W<3:0> > 9] or [DC = 1], then
(W<3:0>) + 6 W<3:0>;
else
(W<3:0>) W<3:0>
If [W<7:4> > 9] or [C = 1], then
(W<7:4>) + 6 W<7:4>;
C =1;
else
(W<7:4>) W<7:4>
Status Affected: C
Encoding: 0000 0000 0000 0111
Description: DAW adjusts the eight-bit value in W,
resulting from the earlier addition of two
variables (each in packed BCD format)
and produces a correct packed BCD
result.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register W
Process
Data
Write
W
Example 1: DAW
Before Instruction
W=A5h
C=0
DC = 0
After Instruction
W = 05h
C=1
DC = 0
Example 2:
Before Instruction
W=CEh
C=0
DC = 0
After Instruction
W = 34h
C=1
DC = 0
DECF Decrement f
Syntax: DECF f {,d {,a}}
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (f) – 1 dest
Status Affected: C, DC, N, OV, Z
Encoding: 0000 01da ffff ffff
Description: Decrement register ‘f’. If ‘d’ is ‘0’, the
result is stored in W. If ‘d’ is ‘1’, the
result is stored back in register ‘f’.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’
Process
Data
Write to
destination
Example: DECF CNT, 1, 0
Before Instruction
CNT = 01h
Z=0
After Instruction
CNT = 00h
Z=1
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DECFSZ Decrement f, Skip if 0
Syntax: DECFSZ f {,d {,a}}
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (f) – 1 dest,
skip if result = 0
Status Affected: None
Encoding: 0010 11da ffff ffff
Description: The contents of register ‘f’ are
decremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’.
If the result is ‘0’, the next instruction
which is already fetched is discarded
and a NOP is executed instead, making
it a two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’
Process
Data
Write to
destination
If skip:
Q1 Q2 Q3 Q4
No
operation
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Example: HERE DECFSZ CNT, 1, 1
GOTO LOOP
CONTINUE
Before Instruction
PC = Address (HERE)
After Instruction
CNT = CNT – 1
If CNT = 0;
PC = Address (CONTINUE)
If CNT 0;
PC = Address (HERE + 2)
DCFSNZ Decrement f, Skip if Not 0
Syntax: DCFSNZ f {,d {,a}}
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (f) – 1 dest,
skip if result 0
Status Affected: None
Encoding: 0100 11da ffff ffff
Description: The contents of register ‘f’ are
decremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’.
If the result is not ‘0’, the next
instruction which is already fetched is
discarded and a NOP is executed
instead, making it a two-cycle
instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’
Process
Data
Write to
destination
If skip:
Q1 Q2 Q3 Q4
No
operation
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Example: HERE DCFSNZ TEMP, 1, 0
ZERO :
NZERO :
Before Instruction
TEMP = ?
After Instruction
TEMP = TEMP – 1,
If TEMP = 0;
PC = Address (ZERO)
If TEMP 0;
PC = Address (NZERO)
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GOTO Unconditional Branch
Syntax: GOTO k
Operands: 0 k 1048575
Operation: k PC<20:1>
Status Affected: None
Encoding:
1st word (k<7:0>)
2nd word(k<19:8>)
1110
1111 1111
k19kkk k7kkk
kkkk kkkk0
kkkk8
Description: GOTO allows an unconditional branch
anywhere within entire 2-Mbyte memory
range. The 20-bit value ‘k’ is loaded into
PC<20:1>. GOTO is always a two-cycle
instruction.
Words: 2
Cycles: 2
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read literal
‘k’<7:0>,
No
operation
Read literal
‘k’<19:8>,
Write to PC
No
operation
No
operation
No
operation
No
operation
Example: GOTO THERE
After Instruction
PC = Address (THERE)
INCF Increment f
Syntax: INCF f {,d {,a}}
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (f) + 1 dest
Status Affected: C, DC, N, OV, Z
Encoding: 0010 10da ffff ffff
Description: The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’
Process
Data
Write to
destination
Example: INCF CNT, 1, 0
Before Instruction
CNT = FFh
Z=0
C=?
DC = ?
After Instruction
CNT = 00h
Z=1
C=1
DC = 1
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INCFSZ Increment f, Skip if 0
Syntax: INCFSZ f {,d {,a}}
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (f) + 1 dest,
skip if result = 0
Status Affected: None
Encoding: 0011 11da ffff ffff
Description: The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’.
If the result is ‘0’, the next instruction
which is already fetched is discarded
and a NOP is executed instead, making
it a two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’
Process
Data
Write to
destination
If skip:
Q1 Q2 Q3 Q4
No
operation
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Example: HERE INCFSZ CNT, 1, 0
NZERO :
ZERO :
Before Instruction
PC = Address (HERE)
After Instruction
CNT = CNT + 1
If CNT = 0;
PC = Address (ZERO)
If CNT 0;
PC = Address (NZERO)
INFSNZ Increment f, Skip if Not 0
Syntax: INFSNZ f {,d {,a}}
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (f) + 1 dest,
skip if result 0
Status Affected: None
Encoding: 0100 10da ffff ffff
Description: The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’.
If the result is not ‘0’, the next
instruction which is already fetched is
discarded and a NOP is executed
instead, making it a two-cycle
instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’
Process
Data
Write to
destination
If skip:
Q1 Q2 Q3 Q4
No
operation
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Example: HERE INFSNZ REG, 1, 0
ZERO
NZERO
Before Instruction
PC = Address (HERE)
After Instruction
REG = REG + 1
If REG 0;
PC = Address (NZERO)
If REG = 0;
PC = Address (ZERO)
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IORLW Inclusive OR Literal with W
Syntax: IORLW k
Operands: 0 k 255
Operation: (W) .OR. k W
Status Affected: N, Z
Encoding: 0000 1001 kkkk kkkk
Description: The contents of W are ORed with the
eight-bit literal ‘k’. The result is placed
in W.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
literal ‘k’
Process
Data
Write to
W
Example: IORLW 35h
Before Instruction
W=9Ah
After Instruction
W=BFh
IORWF Inclusive OR W with f
Syntax: IORWF f {,d {,a}}
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (W) .OR. (f) dest
Status Affected: N, Z
Encoding: 0001 00da ffff ffff
Description: Inclusive OR W with register ‘f’. If ‘d’ is
‘0’, the result is placed in W. If ‘d’ is ‘1’,
the result is placed back in register ‘f’.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’
Process
Data
Write to
destination
Example: IORWF RESULT, 0, 1
Before Instruction
RESULT = 13h
W = 91h
After Instruction
RESULT = 13h
W = 93h
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LFSR Load FSR
Syntax: LFSR f, k
Operands: 0 f 2
0 k 4095
Operation: k FSRf
Status Affected: None
Encoding: 1110
1111 1110
0000 00ff
k7kkk k11kkk
kkkk
Description: The 12-bit literal ‘k’ is loaded into the
file select register pointed to by ‘f’.
Words: 2
Cycles: 2
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read literal
‘k’ MSB
Process
Data
Write
literal ‘k’
MSB to
FSRfH
Decode Read literal
‘k’ LSB
Process
Data
Write literal
‘k’ to FSRfL
Example: LFSR 2, 3ABh
After Instruction
FSR2H = 03h
FSR2L = ABh
MOVF Move f
Syntax: MOVF f {,d {,a}}
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: f dest
Status Affected: N, Z
Encoding: 0101 00da ffff ffff
Description: The contents of register ‘f’ are moved to
a destination dependent upon the
status of ‘d’. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’. Location ‘f’
can be anywhere in the
256-byte bank.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’
Process
Data
Write
W
Example: MOVF REG, 0, 0
Before Instruction
REG = 22h
W=FFh
After Instruction
REG = 22h
W = 22h
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MOVFF Move f to f
Syntax: MOVFF fs,fd
Operands: 0 fs 4095
0 fd 4095
Operation: (fs) fd
Status Affected: None
Encoding:
1st word (source)
2nd word (destin.)
1100
1111 ffff
ffff ffff
ffff ffffs
ffffd
Description: The contents of source register ‘fs’ are
moved to destination register ‘fd’.
Location of source ‘fs’ can be anywhere
in the 4096-byte data space (000h to
FFFh) and location of destination ‘fd’
can also be anywhere from 000h to
FFFh.
Either source or destination can be W
(a useful special situation).
MOVFF is particularly useful for
transferring a data memory location to a
peripheral register (such as the transmit
buffer or an I/O port).
The MOVFF instruction cannot use the
PCL, TOSU, TOSH or TOSL as the
destination register
Words: 2
Cycles: 2
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’
(src)
Process
Data
No
operation
Decode No
operation
No dummy
read
No
operation
Write
register ‘f’
(dest)
Example: MOVFF REG1, REG2
Before Instruction
REG1 = 33h
REG2 = 11h
After Instruction
REG1 = 33h
REG2 = 33h
MOVLB Move Literal to Low Nibble in BSR
Syntax: MOVLW k
Operands: 0 k 255
Operation: k BSR
Status Affected: None
Encoding: 0000 0001 kkkk kkkk
Description: The eight-bit literal ‘k’ is loaded into the
Bank Select Register (BSR). The value
of BSR<7:4> always remains ‘0’
regardless of the value of k7:k4.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
literal ‘k’
Process
Data
Write literal
‘k’ to BSR
Example: MOVLB 5
Before Instruction
BSR Register = 02h
After Instruction
BSR Register = 05h
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MOVLW Move Literal to W
Syntax: MOVLW k
Operands: 0 k 255
Operation: k W
Status Affected: None
Encoding: 0000 1110 kkkk kkkk
Description: The eight-bit literal ‘k’ is loaded into W.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
literal ‘k’
Process
Data
Write to
W
Example: MOVLW 5Ah
After Instruction
W=5Ah
MOVWF Move W to f
Syntax: MOVWF f {,a}
Operands: 0 f 255
a [0,1]
Operation: (W) f
Status Affected: None
Encoding: 0110 111a ffff ffff
Description: Move data from W to register ‘f’.
Location ‘f’ can be anywhere in the
256-byte bank.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’
Process
Data
Write
register ‘f’
Example: MOVWF REG, 0
Before Instruction
W=4Fh
REG = FFh
After Instruction
W=4Fh
REG = 4Fh
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MULLW Multiply Literal with W
Syntax: MULLW k
Operands: 0 k 255
Operation: (W) x k PRODH:PRODL
Status Affected: None
Encoding: 0000 1101 kkkk kkkk
Description: An unsigned multiplication is carried
out between the contents of W and the
8-bit literal ‘k’. The 16-bit result is
placed in the PRODH:PRODL register
pair. PRODH contains the high byte.
W is unchanged.
None of the Status flags are affected.
Note that neither Overflow nor Carry is
possible in this operation. A Zero result
is possible but not detected.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
literal ‘k’
Process
Data
Write
registers
PRODH:
PRODL
Example: MULLW 0C4h
Before Instruction
W=E2h
PRODH = ?
PRODL = ?
After Instruction
W=E2h
PRODH = ADh
PRODL = 08h
MULWF Multiply W with f
Syntax: MULWF f {,a}
Operands: 0 f 255
a [0,1]
Operation: (W) x (f) PRODH:PRODL
Status Affected: None
Encoding: 0000 001a ffff ffff
Description: An unsigned multiplication is carried out
between the contents of W and the
register file location ‘f’. The 16-bit result is
stored in the PRODH:PRODL register
pair. PRODH contains the high byte. Both
W and ‘f’ are unchanged.
None of the Status flags are affected.
Note that neither Overflow nor Carry is
possible in this operation. A Zero result is
possible but not detected.
If ‘a’ is ‘0’, the Access Bank is selected. If
‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction set
is enabled, this instruction operates in
Indexed Literal Offset Addressing mode
whenever f 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’
Process
Data
Write
registers
PRODH:
PRODL
Example: MULWF REG, 1
Before Instruction
W=C4h
REG = B5h
PRODH = ?
PRODL = ?
After Instruction
W=C4h
REG = B5h
PRODH = 8Ah
PRODL = 94h
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NEGF Negate f
Syntax: NEGF f {,a}
Operands: 0 f 255
a [0,1]
Operation: (f) + 1 f
Status Affected: N, OV, C, DC, Z
Encoding: 0110 110a ffff ffff
Description: Location ‘f’ is negated using two’s
complement. The result is placed in the
data memory location ‘f’.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’
Process
Data
Write
register ‘f’
Example: NEGF REG, 1
Before Instruction
REG = 0011 1010 [3Ah]
After Instruction
REG = 1100 0110 [C6h]
NOP No Operation
Syntax: NOP
Operands: None
Operation: No operation
Status Affected: None
Encoding: 0000
1111 0000
xxxx 0000
xxxx 0000
xxxx
Description: No operation.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode No
operation
No
operation
No
operation
Example:
None.
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POP Pop Top of Return Stack
Syntax: POP
Operands: None
Operation: (TOS) bit bucket
Status Affected: None
Encoding: 0000 0000 0000 0110
Description: The TOS value is pulled off the return
stack and is discarded. The TOS value
then becomes the previous value that
was pushed onto the return stack.
This instruction is provided to enable
the user to properly manage the return
stack to incorporate a software stack.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode No
operation
POP TOS
value
No
operation
Example: POP
GOTO NEW
Before Instruction
TOS = 0031A2h
Stack (1 level down) = 014332h
After Instruction
TOS = 014332h
PC = NEW
PUSH Push Top of Return Stack
Syntax: PUSH
Operands: None
Operation: (PC + 2) TOS
Status Affected: None
Encoding: 0000 0000 0000 0101
Description: The PC + 2 is pushed onto the top of
the return stack. The previous TOS
value is pushed down on the stack.
This instruction allows implementing a
software stack by modifying TOS and
then pushing it onto the return stack.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode PUSH
PC + 2 onto
return stack
No
operation
No
operation
Example: PUSH
Before Instruction
TOS = 345Ah
PC = 0124h
After Instruction
PC = 0126h
TOS = 0126h
Stack (1 level down) = 345Ah
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RCALL Relative Call
Syntax: RCALL n
Operands: -1024 n 1023
Operation: (PC) + 2 TOS,
(PC) + 2 + 2n PC
Status Affected: None
Encoding: 1101 1nnn nnnn nnnn
Description: Subroutine call with a jump up to 1K
from the current location. First, return
address (PC + 2) is pushed onto the
stack. Then, add the 2’s complement
number ‘2n’ to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is a
two-cycle instruction.
Words: 1
Cycles: 2
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read literal
‘n’
PUSH PC
to stack
Process
Data
Write to PC
No
operation
No
operation
No
operation
No
operation
Example: HERE RCALL Jump
Before Instruction
PC = Address (HERE)
After Instruction
PC = Address (Jump)
TOS = Address (HERE + 2)
RESET Reset
Syntax: RESET
Operands: None
Operation: Reset all registers and flags that are
affected by a MCLR Reset.
Status Affected: All
Encoding: 0000 0000 1111 1111
Description: This instruction provides a way to
execute a MCLR Reset in software.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Start
reset
No
operation
No
operation
Example: RESET
After Instruction
Registers = Reset Value
Flags* = Reset Value
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RETFIE Return from Interrupt
Syntax: RETFIE {s}
Operands: s [0,1]
Operation: (TOS) PC,
1 GIE/GIEH or PEIE/GIEL;
if s = 1
(WS) W,
(STATUSS) STATUS,
(BSRS) BSR,
PCLATU, PCLATH are unchanged
Status Affected: GIE/GIEH, PEIE/GIEL.
Encoding: 0000 0000 0001 000s
Description: Return from interrupt. Stack is popped
and Top-of-Stack (TOS) is loaded into
the PC. Interrupts are enabled by
setting either the high or low-priority
global interrupt enable bit. If ‘s’ = 1, the
contents of the shadow registers WS,
STATUSS and BSRS are loaded into
their corresponding registers W,
STATUS and BSR. If ‘s’ = 0, no update
of these registers occurs.
Words: 1
Cycles: 2
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode No
operation
No
operation
POP PC
from stack
Set GIEH or
GIEL
No
operation
No
operation
No
operation
No
operation
Example: RETFIE 1
After Interrupt
PC = TOS
W=WS
BSR = BSRS
STATUS = STATUSS
GIE/GIEH, PEIE/GIEL = 1
RETLW Return Literal to W
Syntax: RETLW k
Operands: 0 k 255
Operation: k W,
(TOS) PC,
PCLATU, PCLATH are unchanged
Status Affected: None
Encoding: 0000 1100 kkkk kkkk
Description: W is loaded with the eight-bit literal ‘k’.
The program counter is loaded from the
top of the stack (the return address).
The high address latch (PCLATH)
remains unchanged.
Words: 1
Cycles: 2
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
literal ‘k’
Process
Data
POP PC
from stack,
write to W
No
operation
No
operation
No
operation
No
operation
Example:
CALL TABLE ; W contains table
; offset value
; W now has
; table value
:
TABLE
ADDWF PCL ; W = offset
RETLW k0 ; Begin table
RETLW k1 ;
:
:RETLW kn ; End of table
Before Instruction
W = 07h
After Instruction
W = value of kn
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RETURN Return from Subroutine
Syntax: RETURN {s}
Operands: s [0,1]
Operation: (TOS) PC;
if s = 1
(WS) W,
(STATUSS) STATUS,
(BSRS) BSR,
PCLATU, PCLATH are unchanged
Status Affected: None
Encoding: 0000 0000 0001 001s
Description: Return from subroutine. The stack is
popped and the top of the stack (TOS)
is loaded into the program counter. If
‘s’= 1, the contents of the shadow
registers WS, STATUSS and BSRS are
loaded into their corresponding
registers W, STATUS and BSR. If
‘s’ = 0, no update of these registers
occurs.
Words: 1
Cycles: 2
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode No
operation
Process
Data
POP PC
from stack
No
operation
No
operation
No
operation
No
operation
Example: RETURN
After Instruction:
PC = TOS
RLCF Rotate Left f through Carry
Syntax: RLCF f {,d {,a}}
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (f<n>) dest<n + 1>,
(f<7>) C,
(C) dest<0>
Status Affected: C, N, Z
Encoding: 0011 01da ffff ffff
Description: The contents of register ‘f’ are rotated
one bit to the left through the Carry flag.
If ‘d’ is ‘0’, the result is placed in W. If ‘d’
is ‘1’, the result is stored back in register
‘f’.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’
Process
Data
Write to
destination
Example: RLCF REG, 0, 0
Before Instruction
REG = 1110 0110
C=0
After Instruction
REG = 1110 0110
W=1100 1100
C=1
Cregister f
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RLNCF Rotate Left f (No Carry)
Syntax: RLNCF f {,d {,a}}
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (f<n>) dest<n + 1>,
(f<7>) dest<0>
Status Affected: N, Z
Encoding: 0100 01da ffff ffff
Description: The contents of register ‘f’ are rotated
one bit to the left. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’
Process
Data
Write to
destination
Example: RLNCF REG, 1, 0
Before Instruction
REG = 1010 1011
After Instruction
REG = 0101 0111
register f
RRCF Rotate Right f through Carry
Syntax: RRCF f {,d {,a}}
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (f<n>) dest<n – 1>,
(f<0>) C,
(C) dest<7>
Status Affected: C, N, Z
Encoding: 0011 00da ffff ffff
Description: The contents of register ‘f’ are rotated
one bit to the right through the Carry
flag. If ‘d’ is ‘0’, the result is placed in W.
If ‘d’ is ‘1’, the result is placed back in
register ‘f’.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’
Process
Data
Write to
destination
Example: RRCF REG, 0, 0
Before Instruction
REG = 1110 0110
C=0
After Instruction
REG = 1110 0110
W=0111 0011
C=0
Cregister f
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RRNCF Rotate Right f (No Carry)
Syntax: RRNCF f {,d {,a}}
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (f<n>) dest<n – 1>,
(f<0>) dest<7>
Status Affected: N, Z
Encoding: 0100 00da ffff ffff
Description: The contents of register ‘f’ are rotated
one bit to the right. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’.
If ‘a’ is ‘0’, the Access Bank will be
selected, overriding the BSR value. If ‘a’
is ‘1’, then the bank will be selected as
per the BSR value.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’
Process
Data
Write to
destination
Example 1: RRNCF REG, 1, 0
Before Instruction
REG = 1101 0111
After Instruction
REG = 1110 1011
Example 2: RRNCF REG, 0, 0
Before Instruction
W=?
REG = 1101 0111
After Instruction
W=1110 1011
REG = 1101 0111
register f
SETF Set f
Syntax: SETF f {,a}
Operands: 0 f 255
a [0,1]
Operation: FFh f
Status Affected: None
Encoding: 0110 100a ffff ffff
Description: The contents of the specified register
are set to FFh.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’
Process
Data
Write
register ‘f’
Example: SETF REG,1
Before Instruction
REG = 5Ah
After Instruction
REG = FFh
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SLEEP Enter Sleep Mode
Syntax: SLEEP
Operands: None
Operation: 00h WDT,
0 WDT postscaler,
1 TO,
0 PD
Status Affected: TO, PD
Encoding: 0000 0000 0000 0011
Description: The Power-Down status bit (PD) is
cleared. The Time-out status bit (TO)
is set. The Watchdog Timer and its
postscaler are cleared.
The processor is put into Sleep mode
with the oscillator stopped.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode No
operation
Process
Data
Go to
Sleep
Example: SLEEP
Before Instruction
TO =?
PD =?
After Instruction
TO =1 †
PD =0
† If WDT causes wake-up, this bit is cleared.
SUBFWB Subtract f from W with Borrow
Syntax: SUBFWB f {,d {,a}}
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (W) – (f) – (C) dest
Status Affected: N, OV, C, DC, Z
Encoding: 0101 01da ffff ffff
Description: Subtract register ‘f’ and Carry flag
(borrow) from W (2’s complement
method). If ‘d’ is ‘0’, the result is stored in
W. If ‘d’ is ‘1’, the result is stored in
register ‘f’.
If ‘a’ is ‘0’, the Access Bank is selected. If
‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates in
Indexed Literal Offset Addressing mode
whenever f 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’
Process
Data
Write to
destination
Example 1: SUBFWB REG, 1, 0
Before Instruction
REG = 3
W=2
C=1
After Instruction
REG = FF
W=2
C=0
Z=0
N = 1 ; result is negative
Example 2: SUBFWB REG, 0, 0
Before Instruction
REG = 2
W=5
C=1
After Instruction
REG = 2
W=3
C=1
Z=0
N = 0 ; result is positive
Example 3: SUBFWB REG, 1, 0
Before Instruction
REG = 1
W=2
C=0
After Instruction
REG = 0
W=2
C=1
Z = 1 ; result is zero
N=0
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SUBLW Subtract W from Literal
Syntax: SUBLW k
Operands: 0 k 255
Operation: k – (W) W
Status Affected: N, OV, C, DC, Z
Encoding: 0000 1000 kkkk kkkk
Description: W is subtracted from the eight-bit
literal ‘k’. The result is placed in W.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
literal ‘k’
Process
Data
Write to
W
Example 1: SUBLW 02h
Before Instruction
W = 01h
C=?
After Instruction
W = 01h
C=1 ; result is positive
Z=0
N=0
Example 2: SUBLW 02h
Before Instruction
W = 02h
C=?
After Instruction
W = 00h
C=1 ; result is zero
Z=1
N=0
Example 3: SUBLW 02h
Before Instruction
W = 03h
C=?
After Instruction
W = FFh ; (2’s complement)
C=0 ; result is negative
Z=0
N=1
SUBWF Subtract W from f
Syntax: SUBWF f {,d {,a}}
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (f) – (W) dest
Status Affected: N, OV, C, DC, Z
Encoding: 0101 11da ffff ffff
Description: Subtract W from register ‘f’ (2’s
complement method). If ‘d’ is ‘0’, the
result is stored in W. If ‘d’ is ‘1’, the result
is stored back in register ‘f’.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’
Process
Data
Write to
destination
Example 1: SUBWF REG, 1, 0
Before Instruction
REG = 3
W=2
C=?
After Instruction
REG = 1
W=2
C = 1 ; result is positive
Z=0
N=0
Example 2: SUBWF REG, 0, 0
Before Instruction
REG = 2
W=2
C=?
After Instruction
REG = 2
W=0
C = 1 ; result is zero
Z=1
N=0
Example 3: SUBWF REG, 1, 0
Before Instruction
REG = 1
W=2
C=?
After Instruction
REG = FFh ;(2’s complement)
W=2
C = 0 ; result is negative
Z=0
N=1
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SUBWFB Subtract W from f with Borrow
Syntax: SUBWFB f {,d {,a}}
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (f) – (W) – (C) dest
Status Affected: N, OV, C, DC, Z
Encoding: 0101 10da ffff ffff
Description: Subtract W and the Carry flag (borrow)
from register ‘f’ (2’s complement
method). If ‘d’ is ‘0’, the result is stored
in W. If ‘d’ is ‘1’, the result is stored back
in register ‘f’.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’
Process
Data
Write to
destination
Example 1: SUBWFB REG, 1, 0
Before Instruction
REG = 19h (0001 1001)
W=0Dh (0000 1101)
C=1
After Instruction
REG = 0Ch (0000 1011)
W=0Dh (0000 1101)
C=1
Z=0
N=0 ; result is positive
Example 2: SUBWFB REG, 0, 0
Before Instruction
REG = 1Bh (0001 1011)
W=1Ah (0001 1010)
C=0
After Instruction
REG = 1Bh (0001 1011)
W = 00h
C=1
Z=1 ; result is zero
N=0
Example 3: SUBWFB REG, 1, 0
Before Instruction
REG = 03h (0000 0011)
W=0Eh (0000 1101)
C=1
After Instruction
REG = F5h (1111 0100)
; [2’s comp]
W=0Eh (0000 1101)
C=0
Z=0
N=1 ; result is negative
SWAPF Swap f
Syntax: SWAPF f {,d {,a}}
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (f<3:0>) dest<7:4>,
(f<7:4>) dest<3:0>
Status Affected: None
Encoding: 0011 10da ffff ffff
Description: The upper and lower nibbles of register
‘f’ are exchanged. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, the result is
placed in register ‘f’.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’
Process
Data
Write to
destination
Example: SWAPF REG, 1, 0
Before Instruction
REG = 53h
After Instruction
REG = 35h
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TBLRD Table Read
Syntax: TBLRD ( *; *+; *-; +*)
Operands: None
Operation: if TBLRD *,
(Prog Mem (TBLPTR)) TABLAT;
TBLPTR – No Change
if TBLRD *+,
(Prog Mem (TBLPTR)) TABLAT;
(TBLPTR) + 1 TBLPTR
if TBLRD *-,
(Prog Mem (TBLPTR)) TABLAT;
(TBLPTR) – 1 TBLPTR
if TBLRD +*,
(TBLPTR) + 1 TBLPTR;
(Prog Mem (TBLPTR)) TABLAT
Status Affected: None
Encoding: 0000 0000 0000 10nn
nn=0 *
=1 *+
=2 *-
=3 +*
Description: This instruction is used to read the contents
of Program Memory (P.M.). To address the
program memory, a pointer called Table
Pointer (TBLPTR) is used.
The TBLPTR (a 21-bit pointer) points to
each byte in the program memory. TBLPTR
has a 2-Mbyte address range.
TBLPTR[0] = 0: Least Significant Byte of
Program Memory Word
TBLPTR[0] = 1: Most Significant Byte of
Program Memory Word
The TBLRD instruction can modify the value
of TBLPTR as follows:
• no change
• post-increment
• post-decrement
• pre-increment
Words: 1
Cycles: 2
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode No
operation
No
operation
No
operation
No
operation
No operation
(Read Program
Memory)
No
operation
No operation
(Write
TABLAT)
TBLRD Table Read (Continued)
Example 1: TBLRD *+ ;
Before Instruction
TABLAT = 55h
TBLPTR = 00A356h
MEMORY(00A356h) = 34h
After Instruction
TABLAT = 34h
TBLPTR = 00A357h
Example 2: TBLRD +* ;
Before Instruction
TABLAT = AAh
TBLPTR = 01A357h
MEMORY(01A357h) = 12h
MEMORY(01A358h) = 34h
After Instruction
TABLAT = 34h
TBLPTR = 01A358h
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TBLWT Table Write
Syntax: TBLWT ( *; *+; *-; +*)
Operands: None
Operation: if TBLWT*,
(TABLAT) Holding Register;
TBLPTR – No Change
if TBLWT*+,
(TABLAT) Holding Register;
(TBLPTR) + 1 TBLPTR
if TBLWT*-,
(TABLAT) Holding Register;
(TBLPTR) – 1 TBLPTR
if TBLWT+*,
(TBLPTR) + 1 TBLPTR;
(TABLAT) Holding Register
Status Affected: None
Encoding: 0000 0000 0000 11nn
nn=0 *
=1 *+
=2 *-
=3 +*
Description: This instruction uses the 3 LSBs of
TBLPTR to determine which of the
8 holding registers the TABLAT is written
to. The holding registers are used to
program the contents of Program Memory
(P.M.). (Refer to Section 6.0 “Memory
Organization” for additional details on
programming Flash memory.)
The TBLPTR (a 21-bit pointer) points to
each byte in the program memory.
TBLPTR has a 2-Mbyte address range.
The LSb of the TBLPTR selects which
byte of the program memory location to
access.
TBLPTR[0] = 0: Least Significant Byte
of Program Memory
Word
TBLPTR[0] = 1: Most Significant Byte
of Program Memory
Word
The TBLWT instruction can modify the
value of TBLPTR as follows:
• no change
• post-increment
• post-decrement
• pre-increment
Words: 1
Cycles: 2
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode No
operation
No
operation
No
operation
No
operation
No
operation
(Read
TABLAT)
No
operation
No
operation
(Write to
Holding
Register)
TBLWT Table Write (Continued)
Example 1: TBLWT *+;
Before Instruction
TABLAT = 55h
TBLPTR = 00A356h
HOLDING REGISTER
(00A356h) = FFh
After Instructions (table write completion)
TABLAT = 55h
TBLPTR = 00A357h
HOLDING REGISTER
(00A356h) = 55h
Example 2: TBLWT +*;
Before Instruction
TABLAT = 34h
TBLPTR = 01389Ah
HOLDING REGISTER
(01389Ah) = FFh
HOLDING REGISTER
(01389Bh) = FFh
After Instruction (table write completion)
TABLAT = 34h
TBLPTR = 01389Bh
HOLDING REGISTER
(01389Ah) = FFh
HOLDING REGISTER
(01389Bh) = 34h
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TSTFSZ Test f, Skip if 0
Syntax: TSTFSZ f {,a}
Operands: 0 f 255
a [0,1]
Operation: skip if f = 0
Status Affected: None
Encoding: 0110 011a ffff ffff
Description: If ‘f’ = 0, the next instruction fetched
during the current instruction execution
is discarded and a NOP is executed,
making this a two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’
Process
Data
No
operation
If skip:
Q1 Q2 Q3 Q4
No
operation
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Example: HERE TSTFSZ CNT, 1
NZERO :
ZERO :
Before Instruction
PC = Address (HERE)
After Instruction
If CNT = 00h,
PC = Address (ZERO)
If CNT 00h,
PC = Address (NZERO)
XORLW Exclusive OR Literal with W
Syntax: XORLW k
Operands: 0 k 255
Operation: (W) .XOR. k W
Status Affected: N, Z
Encoding: 0000 1010 kkkk kkkk
Description: The contents of W are XORed with
the 8-bit literal ‘k’. The result is placed
in W.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
literal ‘k’
Process
Data
Write to
W
Example: XORLW 0AFh
Before Instruction
W=B5h
After Instruction
W=1Ah
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XORWF Exclusive OR W with f
Syntax: XORWF f {,d {,a}}
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (W) .XOR. (f) dest
Status Affected: N, Z
Encoding: 0001 10da ffff ffff
Description: Exclusive OR the contents of W with
register ‘f’. If ‘d’ is ‘0’, the result is stored
in W. If ‘d’ is ‘1’, the result is stored back
in the register ‘f’.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’
Process
Data
Write to
destination
Example: XORWF REG, 1, 0
Before Instruction
REG = AFh
W=B5h
After Instruction
REG = 1Ah
W=B5h
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24.2 Extended Instruction Set
In addition to the standard 75 instructions of the PIC18
instruction set, the PIC18F85J90 family family of
devices also provide an optional extension to the core
CPU functionality. The added features include eight
additional instructions that augment Indirect and
Indexed Addressing operations and the implementa-
tion of Indexed Literal Offset Addressing for many of
the standard PIC18 instructions.
The additional features of the extended instruction set
are enabled by default on unprogrammed devices.
Users must properly set or clear the XINST Configura-
tion bit during programming to enable or disable these
features.
The instructions in the extended set can all be
classified as literal operations, which either manipulate
the File Select Registers, or use them for Indexed
Addressing. Two of the instructions, ADDFSR and
SUBFSR, each have an additional special instantiation
for using FSR2. These versions (ADDULNK and
SUBULNK) allow for automatic return after execution.
The extended instructions are specifically implemented
to optimize re-entrant program code (that is, code that
is recursive or that uses a software stack) written in
high-level languages, particularly C. Among other
things, they allow users working in high-level
languages to perform certain operations on data
structures more efficiently. These include:
• Dynamic allocation and deallocation of software
stack space when entering and leaving
subroutines
• Function Pointer invocation
• Software Stack Pointer manipulation
• Manipulation of variables located in a software
stack
A summary of the instructions in the extended instruc-
tion set is provided in Table 24-3. Detailed descriptions
are provided in Section 24.2.2 “Extended Instruction
Set”. The opcode field descriptions in Table 24-1
(page 306) apply to both the standard and extended
PIC18 instruction sets.
24.2.1 EXTENDED INSTRUCTION SYNTAX
Most of the extended instructions use indexed argu-
ments, using one of the File Select Registers and some
offset to specify a source or destination register. When
an argument for an instruction serves as part of
Indexed Addressing, it is enclosed in square brackets
(“[ ]”). This is done to indicate that the argument is used
as an index or offset. The MPASM™ Assembler will
flag an error if it determines that an index or offset value
is not bracketed.
When the extended instruction set is enabled, brackets
are also used to indicate index arguments in
byte-oriented and bit-oriented instructions. This is in
addition to other changes in their syntax. For more
details, see Section 24.2.3.1 “Extended Instruction
Syntax with Standard PIC18 Commands”.
TABLE 24-3: EXTENSIONS TO THE PIC18 INSTRUCTION SET
Note: The instruction set extension and the
Indexed Literal Offset Addressing mode
were designed for optimizing applications
written in C; the user may likely never use
these instructions directly in assembler.
The syntax for these commands is
provided as a reference for users who may
be reviewing code that has been
generated by a compiler.
Note: In the past, square brackets have been
used to denote optional arguments in the
PIC18 and earlier instruction sets. In this
text and going forward, optional
arguments are denoted by braces (“{ }”).
Mnemonic,
Operands Description Cycles
16-Bit Instruction Word Status
Affected
MSb LSb
ADDFSR
ADDULNK
CALLW
MOVSF
MOVSS
PUSHL
SUBFSR
SUBULNK
f, k
k
zs, fd
zs, zd
k
f, k
k
Add Literal to FSR
Add Literal to FSR2 and return
Call Subroutine Using WREG
Move zs (source) to 1st word
fd (destination) 2nd word
Move zs (source) to 1st word
zd (destination) 2nd word
Store Literal at FSR2,
Decrement FSR2
Subtract Literal from FSR
Subtract Literal from FSR2 and
Return
1
2
2
2
2
1
1
2
1110
1110
0000
1110
1111
1110
1111
1110
1110
1110
1000
1000
0000
1011
ffff
1011
xxxx
1010
1001
1001
ffkk
11kk
0001
0zzz
ffff
1zzz
xzzz
kkkk
ffkk
11kk
kkkk
kkkk
0100
zzzz
ffff
zzzz
zzzz
kkkk
kkkk
kkkk
None
None
None
None
None
None
None
None
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24.2.2 EXTENDED INSTRUCTION SET
ADDFSR Add Literal to FSR
Syntax: ADDFSR f, k
Operands: 0 k 63
f [ 0, 1, 2 ]
Operation: FSR(f) + k FSR(f)
Status Affected: None
Encoding: 1110 1000 ffkk kkkk
Description: The 6-bit literal ‘k’ is added to the
contents of the FSR specified by ‘f’.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
literal ‘k’
Process
Data
Write to
FSR
Example: ADDFSR 2, 23h
Before Instruction
FSR2 = 03FFh
After Instruction
FSR2 = 0422h
ADDULNK Add Literal to FSR2 and Return
Syntax: ADDULNK k
Operands: 0 k 63
Operation: FSR2 + k FSR2,
(TOS) PC
Status Affected: None
Encoding: 1110 1000 11kk kkkk
Description: The 6-bit literal ‘k’ is added to the
contents of FSR2. A RETURN is then
executed by loading the PC with the
TOS.
The instruction takes two cycles to
execute; a NOP is performed during
the second cycle.
This may be thought of as a special
case of the ADDFSR instruction,
where f = 3 (binary ‘11’); it operates
only on FSR2.
Words: 1
Cycles: 2
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
literal ‘k’
Process
Data
Write to
FSR
No
Operation
No
Operation
No
Operation
No
Operation
Example: ADDULNK 23h
Before Instruction
FSR2 = 03FFh
PC = 0100h
After Instruction
FSR2 = 0422h
PC = (TOS)
Note: All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in
symbolic addressing. If a label is used, the instruction format then becomes: {label} instruction argument(s).
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CALLW Subroutine Call Using WREG
Syntax: CALLW
Operands: None
Operation: (PC + 2) TOS,
(W) PCL,
(PCLATH) PCH,
(PCLATU) PCU
Status Affected: None
Encoding: 0000 0000 0001 0100
Description First, the return address (PC + 2) is
pushed onto the return stack. Next, the
contents of W are written to PCL; the
existing value is discarded. Then, the
contents of PCLATH and PCLATU are
latched into PCH and PCU,
respectively. The second cycle is
executed as a NOP instruction while the
new next instruction is fetched.
Unlike CALL, there is no option to
update W, STATUS or BSR.
Words: 1
Cycles: 2
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
WREG
Push PC to
stack
No
operation
No
operation
No
operation
No
operation
No
operation
Example: HERE CALLW
Before Instruction
PC = address (HERE)
PCLATH = 10h
PCLATU = 00h
W = 06h
After Instruction
PC = 001006h
TOS = address (HERE + 2)
PCLATH = 10h
PCLATU = 00h
W = 06h
MOVSF Move Indexed to f
Syntax: MOVSF [zs], fd
Operands: 0 zs 127
0 fd 4095
Operation: ((FSR2) + zs) fd
Status Affected: None
Encoding:
1st word (source)
2nd word (destin.)
1110
1111 1011
ffff 0zzz
ffff zzzzs
ffffd
Description: The contents of the source register are
moved to destination register ‘fd’. The
actual address of the source register is
determined by adding the 7-bit literal
offset ‘zs’, in the first word, to the value
of FSR2. The address of the destination
register is specified by the 12-bit literal
‘fd’ in the second word. Both addresses
can be anywhere in the 4096-byte data
space (000h to FFFh).
The MOVSF instruction cannot use the
PCL, TOSU, TOSH or TOSL as the
destination register.
If the resultant source address points to
an Indirect Addressing register, the
value returned will be 00h.
Words: 2
Cycles: 2
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Determine
source addr
Determine
source addr
Read
source reg
Decode No
operation
No dummy
read
No
operation
Write
register ‘f’
(dest)
Example: MOVSF [05h], REG2
Before Instruction
FSR2 = 80h
Contents
of 85h = 33h
REG2 = 11h
After Instruction
FSR2 = 80h
Contents
of 85h = 33h
REG2 = 33h
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MOVSS Move Indexed to Indexed
Syntax: MOVSS [zs], [zd]
Operands: 0 zs 127
0 zd 127
Operation: ((FSR2) + zs) ((FSR2) + zd)
Status Affected: None
Encoding:
1st word (source)
2nd word (dest.)
1110
1111 1011
xxxx 1zzz
xzzz zzzzs
zzzzd
Description The contents of the source register are
moved to the destination register. The
addresses of the source and destination
registers are determined by adding the
7-bit literal offsets, ‘zs’ or ‘zd’,
respectively, to the value of FSR2. Both
registers can be located anywhere in
the 4096-byte data memory space
(000h to FFFh).
The MOVSS instruction cannot use the
PCL, TOSU, TOSH or TOSL as the
destination register.
If the resultant source address points to
an Indirect Addressing register, the
value returned will be 00h. If the
resultant destination address points to
an Indirect Addressing register, the
instruction will execute as a NOP.
Words: 2
Cycles: 2
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Determine
source addr
Determine
source addr
Read
source reg
Decode Determine
dest addr
Determine
dest addr
Write
to dest reg
Example: MOVSS [05h], [06h]
Before Instruction
FSR2 = 80h
Contents
of 85h = 33h
Contents
of 86h = 11h
After Instruction
FSR2 = 80h
Contents
of 85h = 33h
Contents
of 86h = 33h
PUSHL Store Literal at FSR2, Decrement FSR2
Syntax: PUSHL k
Operands: 0k 255
Operation: k (FSR2),
FSR2 – 1 FSR2
Status Affected: None
Encoding: 1111 1010 kkkk kkkk
Description: The 8-bit literal ‘k’ is written to the data
memory address specified by FSR2.
FSR2 is decremented by 1 after the
operation.
This instruction allows users to push
values onto a software stack.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read ‘k’ Process
data
Write to
destination
Example: PUSHL 08h
Before Instruction
FSR2H:FSR2L = 01ECh
Memory (01ECh) = 00h
After Instruction
FSR2H:FSR2L = 01EBh
Memory (01ECh) = 08h
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SUBFSR Subtract Literal from FSR
Syntax: SUBFSR f, k
Operands: 0 k 63
f [ 0, 1, 2 ]
Operation: FSRf – k FSRf
Status Affected: None
Encoding: 1110 1001 ffkk kkkk
Description: The 6-bit literal ‘k’ is subtracted from
the contents of the FSR specified
by ‘f’.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’
Process
Data
Write to
destination
Example: SUBFSR 2, 23h
Before Instruction
FSR2 = 03FFh
After Instruction
FSR2 = 03DCh
SUBULNK Subtract Literal from FSR2 and Return
Syntax: SUBULNK k
Operands: 0 k 63
Operation: FSR2 – k FSR2,
(TOS) PC
Status Affected: None
Encoding: 1110 1001 11kk kkkk
Description: The 6-bit literal ‘k’ is subtracted from the
contents of the FSR2. A RETURN is then
executed by loading the PC with the
TOS.
The instruction takes two cycles to
execute; a NOP is performed during the
second cycle.
This may be thought of as a special case
of the SUBFSR instruction, where f = 3
(binary ‘11’); it operates only on FSR2.
Words: 1
Cycles: 2
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’
Process
Data
Write to
destination
No
Operation
No
Operation
No
Operation
No
Operation
Example: SUBULNK 23h
Before Instruction
FSR2 = 03FFh
PC = 0100h
After Instruction
FSR2 = 03DCh
PC = (TOS)
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24.2.3 BYTE-ORIENTED AND
BIT-ORIENTED INSTRUCTIONS IN
INDEXED LITERAL OFFSET MODE
In addition to eight new commands in the extended set,
enabling the extended instruction set also enables
Indexed Literal Offset Addressing (Section 6.6.1
“Indexed Addressing with Literal Offset”). This has
a significant impact on the way that many commands of
the standard PIC18 instruction set are interpreted.
When the extended set is disabled, addresses embed-
ded in opcodes are treated as literal memory locations:
either as a location in the Access Bank (a = 0) or in a
GPR bank designated by the BSR (a = 1). When the
extended instruction set is enabled and a = 0, however,
a file register argument of 5Fh or less is interpreted as
an offset from the pointer value in FSR2 and not as a
literal address. For practical purposes, this means that
all instructions that use the Access RAM bit as an
argument – that is, all byte-oriented and bit-oriented
instructions, or almost half of the core PIC18 instruc-
tions – may behave differently when the extended
instruction set is enabled.
When the content of FSR2 is 00h, the boundaries of the
Access RAM are essentially remapped to their original
values. This may be useful in creating
backward-compatible code. If this technique is used, it
may be necessary to save the value of FSR2 and
restore it when moving back and forth between C and
assembly routines in order to preserve the Stack
Pointer. Users must also keep in mind the syntax
requirements of the extended instruction set (see
Section 24.2.3.1 “Extended Instruction Syntax with
Standard PIC18 Commands”).
Although the Indexed Literal Offset mode can be very
useful for dynamic stack and pointer manipulation, it
can also be very annoying if a simple arithmetic opera-
tion is carried out on the wrong register. Users who are
accustomed to the PIC18 programming must keep in
mind that, when the extended instruction set is
enabled, register addresses of 5Fh or less are used for
Indexed Literal Offset Addressing.
Representative examples of typical byte-oriented and
bit-oriented instructions in the Indexed Literal Offset
mode are provided on the following page to show how
execution is affected. The operand conditions shown in
the examples are applicable to all instructions of these
types.
24.2.3.1 Extended Instruction Syntax with
Standard PIC18 Commands
When the extended instruction set is enabled, the file
register argument, ‘f’, in the standard byte-oriented and
bit-oriented commands is replaced with the literal offset
value, ‘k’. As already noted, this occurs only when ‘f’ is
less than or equal to 5Fh. When an offset value is used,
it must be indicated by square brackets (“[ ]”). As with
the extended instructions, the use of brackets indicates
to the compiler that the value is to be interpreted as an
index or an offset. Omitting the brackets, or using a
value greater than 5Fh within the brackets, will
generate an error in the MPASM Assembler.
If the index argument is properly bracketed for Indexed
Literal Offset Addressing, the Access RAM argument is
never specified; it will automatically be assumed to be
‘0’. This is in contrast to standard operation (extended
instruction set disabled), when ‘a’ is set on the basis of
the target address. Declaring the Access RAM bit in
this mode will also generate an error in the MPASM
Assembler.
The destination argument, ‘d’, functions as before.
In the latest versions of the MPASM Assembler,
language support for the extended instruction set must
be explicitly invoked. This is done with either the
command line option, /y, or the PE directive in the
source listing.
24.2.4 CONSIDERATIONS WHEN
ENABLING THE EXTENDED
INSTRUCTION SET
It is important to note that the extensions to the instruc-
tion set may not be beneficial to all users. In particular,
users who are not writing code that uses a software
stack may not benefit from using the extensions to the
instruction set.
Additionally, the Indexed Literal Offset Addressing
mode may create issues with legacy applications
written to the PIC18 assembler. This is because
instructions in the legacy code may attempt to address
registers in the Access Bank below 5Fh. Since these
addresses are interpreted as literal offsets to FSR2
when the instruction set extension is enabled, the
application may read or write to the wrong data
addresses.
When porting an application to the PIC18F85J90 family
family, it is very important to consider the type of code. A
large, re-entrant application that is written in C and would
benefit from efficient compilation will do well when using
the instruction set extensions. Legacy applications that
heavily use the Access Bank will most likely not benefit
from using the extended instruction set.
Note: Enabling the PIC18 instruction set exten-
sion may cause legacy applications to
behave erratically or fail entirely.
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ADDWF ADD W to Indexed
(Indexed Literal Offset mode)
Syntax: ADDWF [k] {,d}
Operands: 0 k 95
d [0,1]
Operation: (W) + ((FSR2) + k) dest
Status Affected: N, OV, C, DC, Z
Encoding: 0010 01d0 kkkk kkkk
Description: The contents of W are added to the
contents of the register indicated by
FSR2, offset by the value ‘k’.
If ‘d’ is ‘0’, the result is stored in W. If ‘d’
is ‘1’, the result is stored back in
register ‘f’.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read ‘k’ Process
Data
Write to
destination
Example: ADDWF [OFST] ,0
Before Instruction
W = 17h
OFST = 2Ch
FSR2 = 0A00h
Contents
of 0A2Ch = 20h
After Instruction
W = 37h
Contents
of 0A2Ch = 20h
BSF Bit Set Indexed
(Indexed Literal Offset mode)
Syntax: BSF [k], b
Operands: 0 f 95
0 b 7
Operation: 1 ((FSR2) + k)<b>
Status Affected: None
Encoding: 1000 bbb0 kkkk kkkk
Description: Bit ‘b’ of the register indicated by FSR2,
offset by the value ‘k’, is set.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’
Process
Data
Write to
destination
Example: BSF [FLAG_OFST], 7
Before Instruction
FLAG_OFST = 0Ah
FSR2 = 0A00h
Contents
of 0A0Ah = 55h
After Instruction
Contents
of 0A0Ah = D5h
SETF Set Indexed
(Indexed Literal Offset mode)
Syntax: SETF [k]
Operands: 0 k 95
Operation: FFh ((FSR2) + k)
Status Affected: None
Encoding: 0110 1000 kkkk kkkk
Description: The contents of the register indicated by
FSR2, offset by ‘k’, are set to FFh.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read ‘k’ Process
Data
Write
register
Example: SETF [OFST]
Before Instruction
OFST = 2Ch
FSR2 = 0A00h
Contents
of 0A2Ch = 00h
After Instruction
Contents
of 0A2Ch = FFh
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24.2.5 SPECIAL CONSIDERATIONS WITH
MICROCHIP MPLAB® IDE TOOLS
The latest versions of Microchip’s software tools have
been designed to fully support the extended instruction
set for the PIC18F85J90 family family. This includes
the MPLAB C18 C Compiler, MPASM assembly
language and MPLAB Integrated Development
Environment (IDE).
When selecting a target device for software
development, MPLAB IDE will automatically set default
Configuration bits for that device. The default setting for
the XINST Configuration bit is ‘1’, enabling the
extended instruction set and Indexed Literal Offset
Addressing. For proper execution of applications
developed to take advantage of the extended
instruction set, XINST must be set during
programming.
To develop software for the extended instruction set,
the user must enable support for the instructions and
the Indexed Addressing mode in their language tool(s).
Depending on the environment being used, this may be
done in several ways:
• A menu option or dialog box within the
environment that allows the user to configure the
language tool and its settings for the project
• A command line option
• A directive in the source code
These options vary between different compilers,
assemblers and development environments. Users are
encouraged to review the documentation accompany-
ing their development systems for the appropriate
information.
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25.0 DEVELOPMENT SUPPORT
The PIC® microcontrollers and dsPIC® digital signal
controllers are supported with a full range of software
and hardware development tools:
• Integrated Development Environment
- MPLAB® IDE Software
• Compilers/Assemblers/Linkers
- MPLAB C Compiler for Various Device
Families
- HI-TECH C for Various Device Families
- MPASMTM Assembler
-MPLINK
TM Object Linker/
MPLIBTM Object Librarian
- MPLAB Assembler/Linker/Librarian for
Various Device Families
• Simulators
- MPLAB SIM Software Simulator
•Emulators
- MPLAB REAL ICE™ In-Circuit Emulator
• In-Circuit Debuggers
- MPLAB ICD 3
- PICkit™ 3 Debug Express
• Device Programmers
- PICkit™ 2 Programmer
- MPLAB PM3 Device Programmer
• Low-Cost Demonstration/Development Boards,
Evaluation Kits, and Starter Kits
25.1 MPLAB Integrated Development
Environment Software
The MPLAB IDE software brings an ease of software
development previously unseen in the 8/16/32-bit
microcontroller market. The MPLAB IDE is a Windows®
operating system-based application that contains:
• A single graphical interface to all debugging tools
- Simulator
- Programmer (sold separately)
- In-Circuit Emulator (sold separately)
- In-Circuit Debugger (sold separately)
• A full-featured editor with color-coded context
• A multiple project manager
• Customizable data windows with direct edit of
contents
• High-level source code debugging
• Mouse over variable inspection
• Drag and drop variables from source to watch
windows
• Extensive on-line help
• Integration of select third party tools, such as
IAR C Compilers
The MPLAB IDE allows you to:
• Edit your source files (either C or assembly)
• One-touch compile or assemble, and download to
emulator and simulator tools (automatically
updates all project information)
• Debug using:
- Source files (C or assembly)
- Mixed C and assembly
- Machine code
MPLAB IDE supports multiple debugging tools in a
single development paradigm, from the cost-effective
simulators, through low-cost in-circuit debuggers, to
full-featured emulators. This eliminates the learning
curve when upgrading to tools with increased flexibility
and power.
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25.2 MPLAB C Compilers for Various
Device Families
The MPLAB C Compiler code development systems
are complete ANSI C compilers for Microchip’s PIC18,
PIC24 and PIC32 families of microcontrollers and the
dsPIC30 and dsPIC33 families of digital signal control-
lers. These compilers provide powerful integration
capabilities, superior code optimization and ease of
use.
For easy source level debugging, the compilers provide
symbol information that is optimized to the MPLAB IDE
debugger.
25.3 HI-TECH C for Various Device
Families
The HI-TECH C Compiler code development systems
are complete ANSI C compilers for Microchip’s PIC
family of microcontrollers and the dsPIC family of digital
signal controllers. These compilers provide powerful
integration capabilities, omniscient code generation
and ease of use.
For easy source level debugging, the compilers provide
symbol information that is optimized to the MPLAB IDE
debugger.
The compilers include a macro assembler, linker, pre-
processor, and one-step driver, and can run on multiple
platforms.
25.4 MPASM Assembler
The MPASM Assembler is a full-featured, universal
macro assembler for PIC10/12/16/18 MCUs.
The MPASM Assembler generates relocatable object
files for the MPLINK Object Linker, Intel® standard HEX
files, MAP files to detail memory usage and symbol
reference, absolute LST files that contain source lines
and generated machine code and COFF files for
debugging.
The MPASM Assembler features include:
• Integration into MPLAB IDE projects
• User-defined macros to streamline
assembly code
• Conditional assembly for multi-purpose
source files
• Directives that allow complete control over the
assembly process
25.5 MPLINK Object Linker/
MPLIB Object Librarian
The MPLINK Object Linker combines relocatable
objects created by the MPASM Assembler and the
MPLAB C18 C Compiler. It can link relocatable objects
from precompiled libraries, using directives from a
linker script.
The MPLIB Object Librarian manages the creation and
modification of library files of precompiled code. When
a routine from a library is called from a source file, only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
The object linker/library features include:
• Efficient linking of single libraries instead of many
smaller files
• Enhanced code maintainability by grouping
related modules together
• Flexible creation of libraries with easy module
listing, replacement, deletion and extraction
25.6 MPLAB Assembler, Linker and
Librarian for Various Device
Families
MPLAB Assembler produces relocatable machine
code from symbolic assembly language for PIC24,
PIC32 and dsPIC devices. MPLAB C Compiler uses
the assembler to produce its object file. The assembler
generates relocatable object files that can then be
archived or linked with other relocatable object files and
archives to create an executable file. Notable features
of the assembler include:
• Support for the entire device instruction set
• Support for fixed-point and floating-point data
• Command line interface
• Rich directive set
• Flexible macro language
• MPLAB IDE compatibility
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25.7 MPLAB SIM Software Simulator
The MPLAB SIM Software Simulator allows code
development in a PC-hosted environment by simulat-
ing the PIC MCUs and dsPIC® DSCs on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a comprehensive stimulus controller. Registers can be
logged to files for further run-time analysis. The trace
buffer and logic analyzer display extend the power of
the simulator to record and track program execution,
actions on I/O, most peripherals and internal registers.
The MPLAB SIM Software Simulator fully supports
symbolic debugging using the MPLAB C Compilers,
and the MPASM and MPLAB Assemblers. The soft-
ware simulator offers the flexibility to develop and
debug code outside of the hardware laboratory envi-
ronment, making it an excellent, economical software
development tool.
25.8 MPLAB REAL ICE In-Circuit
Emulator System
MPLAB REAL ICE In-Circuit Emulator System is
Microchip’s next generation high-speed emulator for
Microchip Flash DSC and MCU devices. It debugs and
programs PIC® Flash MCUs and dsPIC® Flash DSCs
with the easy-to-use, powerful graphical user interface of
the MPLAB Integrated Development Environment (IDE),
included with each kit.
The emulator is connected to the design engineer’s PC
using a high-speed USB 2.0 interface and is connected
to the target with either a connector compatible with in-
circuit debugger systems (RJ11) or with the new high-
speed, noise tolerant, Low-Voltage Differential Signal
(LVDS) interconnection (CAT5).
The emulator is field upgradable through future firmware
downloads in MPLAB IDE. In upcoming releases of
MPLAB IDE, new devices will be supported, and new
features will be added. MPLAB REAL ICE offers signifi-
cant advantages over competitive emulators including
low-cost, full-speed emulation, run-time variable
watches, trace analysis, complex breakpoints, a rugge-
dized probe interface and long (up to three meters) inter-
connection cables.
25.9 MPLAB ICD 3 In-Circuit Debugger
System
MPLAB ICD 3 In-Circuit Debugger System is Micro-
chip's most cost effective high-speed hardware
debugger/programmer for Microchip Flash Digital Sig-
nal Controller (DSC) and microcontroller (MCU)
devices. It debugs and programs PIC® Flash microcon-
trollers and dsPIC® DSCs with the powerful, yet easy-
to-use graphical user interface of MPLAB Integrated
Development Environment (IDE).
The MPLAB ICD 3 In-Circuit Debugger probe is con-
nected to the design engineer's PC using a high-speed
USB 2.0 interface and is connected to the target with a
connector compatible with the MPLAB ICD 2 or MPLAB
REAL ICE systems (RJ-11). MPLAB ICD 3 supports all
MPLAB ICD 2 headers.
25.10 PICkit 3 In-Circuit Debugger/
Programmer and
PICkit 3 Debug Express
The MPLAB PICkit 3 allows debugging and program-
ming of PIC® and dsPIC® Flash microcontrollers at a
most affordable price point using the powerful graphical
user interface of the MPLAB Integrated Development
Environment (IDE). The MPLAB PICkit 3 is connected
to the design engineer's PC using a full speed USB
interface and can be connected to the target via an
Microchip debug (RJ-11) connector (compatible with
MPLAB ICD 3 and MPLAB REAL ICE). The connector
uses two device I/O pins and the reset line to imple-
ment in-circuit debugging and In-Circuit Serial Pro-
gramming™.
The PICkit 3 Debug Express include the PICkit 3, demo
board and microcontroller, hookup cables and CDROM
with user’s guide, lessons, tutorial, compiler and
MPLAB IDE software.
PIC18F85J90 FAMILY
DS39770C-page 358 2010 Microchip Technology Inc.
25.11 PICkit 2 Development
Programmer/Debugger and
PICkit 2 Debug Express
The PICkit™ 2 Development Programmer/Debugger is
a low-cost development tool with an easy to use inter-
face for programming and debugging Microchip’s Flash
families of microcontrollers. The full featured
Windows® programming interface supports baseline
(PIC10F, PIC12F5xx, PIC16F5xx), midrange
(PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30,
dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bit
microcontrollers, and many Microchip Serial EEPROM
products. With Microchip’s powerful MPLAB Integrated
Development Environment (IDE) the PICkit™ 2
enables in-circuit debugging on most PIC® microcon-
trollers. In-Circuit-Debugging runs, halts and single
steps the program while the PIC microcontroller is
embedded in the application. When halted at a break-
point, the file registers can be examined and modified.
The PICkit 2 Debug Express include the PICkit 2, demo
board and microcontroller, hookup cables and CDROM
with user’s guide, lessons, tutorial, compiler and
MPLAB IDE software.
25.12 MPLAB PM3 Device Programmer
The MPLAB PM3 Device Programmer is a universal,
CE compliant device programmer with programmable
voltage verification at VDDMIN and VDDMAX for
maximum reliability. It features a large LCD display
(128 x 64) for menus and error messages and a modu-
lar, detachable socket assembly to support various
package types. The ICSP™ cable assembly is included
as a standard item. In Stand-Alone mode, the MPLAB
PM3 Device Programmer can read, verify and program
PIC devices without a PC connection. It can also set
code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MPLAB PM3 has high-speed communications and
optimized algorithms for quick programming of large
memory devices and incorporates an MMC card for file
storage and data applications.
25.13 Demonstration/Development
Boards, Evaluation Kits, and
Starter Kits
A wide variety of demonstration, development and
evaluation boards for various PIC MCUs and dsPIC
DSCs allows quick application development on fully func-
tional systems. Most boards include prototyping areas for
adding custom circuitry and provide application firmware
and source code for examination and modification.
The boards support a variety of features, including LEDs,
temperature sensors, switches, speakers, RS-232
interfaces, LCD displays, potentiometers and additional
EEPROM memory.
The demonstration and development boards can be
used in teaching environments, for prototyping custom
circuits and for learning about various microcontroller
applications.
In addition to the PICDEM™ and dsPICDEM™ demon-
stration/development board series of circuits, Microchip
has a line of evaluation kits and demonstration software
for analog filter design, KEELOQ® security ICs, CAN,
IrDA®, PowerSmart battery management, SEEVAL®
evaluation system, Sigma-Delta ADC, flow rate
sensing, plus many more.
Also available are starter kits that contain everything
needed to experience the specified device. This usually
includes a single application and debug capability, all
on one board.
Check the Microchip web page (www.microchip.com)
for the complete list of demonstration, development
and evaluation kits.
2010 Microchip Technology Inc. DS39770C-page 359
PIC18F85J90 FAMILY
26.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings(†)
Ambient temperature under bias.............................................................................................................-40°C to +100°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on any digital only I/O pin or MCLR with respect to VSS (except VDD) ........................................... -0.3V to 5.6V
Voltage on any combined digital and analog pin with respect to VSS (except VDD and MCLR)...... -0.3V to (VDD + 0.3V)
Voltage on VDDCORE with respect to VSS ................................................................................................... -0.3V to 2.75V
Voltage on VDD with respect to VSS ........................................................................................................... -0.3V to 3.6V
Total power dissipation (Note 1) ...............................................................................................................................1.0W
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin ..............................................................................................................................250 mA
Maximum output current sunk by PORTA<7:6> and any PORTB and PORTC I/O pins.........................................25 mA
Maximum output current sunk by any PORTD, PORTE and PORTJ I/O pins ..........................................................8 mA
Maximum output current sunk by PORTA<5:0> and any PORTF, PORTG and PORTH I/O pins ............................2 mA
Maximum output current sourced by PORTA<7:6> and any PORTB and PORTC I/O pins ...................................25 mA
Maximum output current sourced by any PORTD, PORTE and PORTJ I/O pins.....................................................8 mA
Maximum output current sourced by PORTA<5:0> and any PORTF, PORTG and PORTH I/O pins .......................2 mA
Maximum current sunk byall ports combined.......................................................................................................200 mA
Note 1: Power dissipation is calculated as follows:
Pdis = VDD x {IDD – IOH} + {(VDD – VOH) x IOH} + (VOL x IOL)
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
PIC18F85J90 FAMILY
DS39770C-page 360 2010 Microchip Technology Inc.
FIGURE 26-1: PIC18F85J90 FAMILY VOLTAGE-FREQUENCY GRAPH,
REGULATOR ENABLED (INDUSTRIAL)(1)
FIGURE 26-2: PIC18F85J90 FAMILY VOLTAGE-FREQUENCY GRAPH,
REGULATOR DISABLED (INDUSTRIAL)(1,2)
Frequency
Voltage (VDD)
4.0V
2.0V
40 MHz
3.5V
3.0V
2.5V
3.6V
PIC18F6XJ90/8XJ90
2.35V
0
Note 1: When the on-chip regulator is enabled, its BOR circuit will automatically trigger a device Reset
before VDD reaches a level at which full-speed operation is not possible.
8 MHz
Frequency
Voltage (VDDCORE)
3.00V
2.00V
40 MHz
2.75V
2.50V
2.25V
2.7V
8 MHz
2.35V
Note 1: For frequencies between 4 MHz and 40 MHz, FMAX = (51.42 MHz/V) * (VDDCORE – 2V) + 4 MHz.
2: When the on-chip voltage regulator is disabled, VDD and VDDCORE must be maintained so that
VDDCORE VDD 3.6V.
PIC18F6XJ90/8XJ90
2010 Microchip Technology Inc. DS39770C-page 361
PIC18F85J90 FAMILY
26.1 DC Characteristics: Supply Voltage
PIC18F85J90 Family (Industrial)
PIC18F85J90 Family
(Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
Param
No. Symbol Characteristic Min Typ Max Units Conditions
D001 VDD Supply Voltage VDDCORE
2.0
—
—
3.6
3.6
V
V
ENVREG tied to VSS
ENVREG tied to VDD
D001B VDDCORE External Supply for
Microcontroller Core
2.0 — 2.70 V ENVREG tied to VSS
D001C AVDD Analog Supply Voltage VDD – 0.3 — VDD + 0.3 V
D001D AVSS Analog Ground Potential VSS – 0.3 — VSS + 0.3 V
D002 VDR RAM Data Retention
Voltage(1)
1.5 — — V
D003 VPOR VDD Start Voltage
to Ensure Internal
Power-on Reset signal
——0.7VSee Section 5.3 “Power-on
Reset (POR)” for details
D004 SVDD VDD Rise Rate
to Ensure Internal
Power-on Reset signal
0.05 — — V/ms See Section 5.3 “Power-on
Reset (POR)” for details
D005 VBOR Brown-out Reset Voltage —1.9—V
Note 1: This is the limit to which VDD can be lowered in Sleep mode, or during a device Reset, without losing RAM data.
PIC18F85J90 FAMILY
DS39770C-page 362 2010 Microchip Technology Inc.
26.2 DC Characteristics: Power-Down and Supply Current
PIC18F85J90 Family (Industrial)
PIC18F85J90 Family
(Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
Param
No. Device Typ Max Units Conditions
Power-Down Current (IPD)(1)
All devices 0.2 0.9 µA -40°C
VDD = 2.0V,
VDDCORE = 2.0V
(Sleep mode)(4)
0.1 0.9 µA +25°C
0.3 3 µA +60°C
2.4 5 µA +85°C
All devices 0.5 0.9 µA -40°C
VDD = 2.5V,
VDDCORE = 2.5V
(Sleep mode)(4)
0.1 0.9 µA +25°C
0.4 3 µA +60°C
2.7 5 µA +85°C
All devices 2.7 6 µA -40°C
VDD = 3.3V
(Sleep mode)(5)
3.5 6 µA +25°C
4.1 8 µA +60°C
6.7 12 µA +85°C
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in a high-impedance state and tied to VDD or VSS, and all features that add delta
current disabled (such as WDT, Timer1 oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature
crystals are available at a much higher cost.
4: Voltage regulator is disabled (ENVREG tied to VSS).
5: Voltage regulator is enabled (ENVREG tied to VDD).
6: Resistor ladder current is not included.
7: Connecting an actual display will increase the current consumption depending on the size of the LCD.
2010 Microchip Technology Inc. DS39770C-page 363
PIC18F85J90 FAMILY
Supply Current (IDD)(2)
All devices 6.5 16 µA -40°C
VDD = 2.0V,
VDDCORE = 2.0V(4)
FOSC = 31 kHz
(INTRC_RUN mode,
internal oscillator source)
7 16 µA +25°C
9.5 20 µA +85°C
All devices 10 18 µA -40°C
VDD = 2.5V,
VDDCORE = 2.5V(4)
10.5 18 µA +25°C
12.5 24 µA +85°C
All devices 41 100 µA -40°C
VDD = 3.3V(5)
52 100 µA +25°C
71 110 µA +85°C
All devices 359 750 µA -40°C
VDD = 2.0V,
VDDCORE = 2.0V(4)
FOSC = 1 MHz
(INTOSC_RUN mode,
internal oscillator source)
387 750 µA +25°C
407 840 µA +85°C
All devices 438 850 µA -40°C
VDD = 2.5V,
VDDCORE = 2.5V(4)
470 850 µA +25°C
491 910 µA +85°C
All devices 486 900 µA -40°C
VDD = 3.3V(5)
526 900 µA +25°C
564 990 µA +85°C
All devices 0.76 1.45 mA -40°C
VDD = 2.0V,
VDDCORE = 2.0V(4)
FOSC = 4 MHz
(INTOSC_RUN mode,
internal oscillator source)
0.84 1.45 mA +25°C
0.9 1.6 mA +85°C
All devices 1.1 1.63 mA -40°C
VDD = 2.5V,
VDDCORE = 2.5V(4)
1.18 1.63 mA +25°C
1.24 1.75 mA +85°C
All devices 1.25 1.86 mA -40°C
VDD = 3.3V(5)
1.29 1.86 mA +25°C
1.37 1.94 mA +85°C
26.2 DC Characteristics: Power-Down and Supply Current
PIC18F85J90 Family (Industrial) (Continued)
PIC18F85J90 Family
(Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
Param
No. Device Typ Max Units Conditions
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in a high-impedance state and tied to VDD or VSS, and all features that add delta
current disabled (such as WDT, Timer1 oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature
crystals are available at a much higher cost.
4: Voltage regulator is disabled (ENVREG tied to VSS).
5: Voltage regulator is enabled (ENVREG tied to VDD).
6: Resistor ladder current is not included.
7: Connecting an actual display will increase the current consumption depending on the size of the LCD.
PIC18F85J90 FAMILY
DS39770C-page 364 2010 Microchip Technology Inc.
Supply Current (IDD)(2)
All devices 2.4 8 µA -40°C
VDD = 2.0V,
VDDCORE = 2.0V(4)
FOSC = 31 kHz
(INTRC_IDLE mode,
internal oscillator source)
2.5 8 µA +25°C
4.8 12 µA +85°C
All devices 3.2 9 µA -40°C
VDD = 2.5V,
VDDCORE = 2.5V(4)
3.2 9 µA +25°C
6 14 µA +85°C
All devices 62 82 µA -40°C
VDD = 3.3V(5)
42 82 µA +25°C
59 97 µA +85°C
All devices 251 570 µA -40°C
VDD = 2.0V,
VDDCORE = 2.0V(4)
FOSC = 1 MHz
(INTOSC_IDLE mode,
internal oscillator source)
264 570 µA +25°C
272 590 µA +85°C
All devices 284 610 µA -40°C
VDD = 2.5V,
VDDCORE = 2.5V(4)
284 610 µA +25°C
293 650 µA +85°C
All devices 295 710 µA -40°C
VDD = 3.3V(5)
323 710 µA +25°C
392 790 µA +85°C
All devices 368 760 µA -40°C
VDD = 2.0V,
VDDCORE = 2.0V(4)
FOSC = 4 MHz
(INTOSC_IDLE mode,
internal oscillator source)
362 760 µA +25°C
370 800 µA +85°C
All devices 400 850 µA -40°C
VDD = 2.5V,
VDDCORE = 2.5V(4)
410 850 µA +25°C
418 900 µA +85°C
All devices 460 950 µA -40°C
VDD = 3.3V(5)
462 950 µA +25°C
486 1000 µA +85°C
26.2 DC Characteristics: Power-Down and Supply Current
PIC18F85J90 Family (Industrial) (Continued)
PIC18F85J90 Family
(Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
Param
No. Device Typ Max Units Conditions
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in a high-impedance state and tied to VDD or VSS, and all features that add delta
current disabled (such as WDT, Timer1 oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature
crystals are available at a much higher cost.
4: Voltage regulator is disabled (ENVREG tied to VSS).
5: Voltage regulator is enabled (ENVREG tied to VDD).
6: Resistor ladder current is not included.
7: Connecting an actual display will increase the current consumption depending on the size of the LCD.
2010 Microchip Technology Inc. DS39770C-page 365
PIC18F85J90 FAMILY
Supply Current (IDD)(2)
All devices 165 490 µA -40°C
VDD = 2.0V,
VDDCORE = 2.0V(4)
FOSC = 1 MHZ
(PRI_RUN mode,
EC oscillator)
180 490 µA +25°C
200 490 µA +85°C
All devices 256 670 µA -40°C
VDD = 2.5V,
VDDCORE = 2.5V(4)
260 670 µA +25°C
280 670 µA +85°C
All devices 460 850 µA -40°C
VDD = 3.3V(5)
456 850 µA +25°C
482 850 µA +85°C
All devices 0.632 2.2 mA -40°C
VDD = 2.0V,
VDDCORE = 2.0V(4)
FOSC = 4 MHz
(PRI_RUN mode,
EC oscillator)
0.681 2.2 mA +25°C
0.738 2.2 mA +85°C
All devices 0.912 2.5 mA -40°C
VDD = 2.5V,
VDDCORE = 2.5V(4)
1.04 2.5 mA +25°C
1.04 2.5 mA +85°C
All devices 1.32 3.0 mA -40°C
VDD = 3.3V(5)
1.32 3.0 mA +25°C
1.41 3.0 mA +85°C
All devices 7.47 14 mA -40°C
VDD = 2.5V,
VDDCORE = 2.5V(4)
FOSC = 40 MHZ
(PRI_RUN mode,
EC oscillator)
5.81 14 mA +25°C
6.32 13 mA +85°C
All devices 8.84 18 mA -40°C
VDD = 3.3V(5)
8.66 18 mA +25°C
7.97 16 mA +85°C
26.2 DC Characteristics: Power-Down and Supply Current
PIC18F85J90 Family (Industrial) (Continued)
PIC18F85J90 Family
(Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
Param
No. Device Typ Max Units Conditions
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in a high-impedance state and tied to VDD or VSS, and all features that add delta
current disabled (such as WDT, Timer1 oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature
crystals are available at a much higher cost.
4: Voltage regulator is disabled (ENVREG tied to VSS).
5: Voltage regulator is enabled (ENVREG tied to VDD).
6: Resistor ladder current is not included.
7: Connecting an actual display will increase the current consumption depending on the size of the LCD.
PIC18F85J90 FAMILY
DS39770C-page 366 2010 Microchip Technology Inc.
Supply Current (IDD)(2)
All devices 2.8 3.8 mA -40°C
VDD = 2.0V,
VDDCORE = 2.0V(4)
FOSC = 4 MHZ,
16 MHz internal
(PRI_RUN mode,
HSPLL oscillator)
3.02 3.8 mA +25°C
3.01 4.5 mA +85°C
All devices 4.5 5.4 mA -40°C
VDD = 2.5V,
VDDCORE = 2.5V(4)
FOSC = 4 MHZ,
16 MHz internal
(PRI_RUN mode,
HSPLL oscillator)
4.8 5.6 mA +25°C
4.54 5.6 mA +85°C
All devices 5.72 6.7 mA -40°C
VDD = 3.3V(5)
FOSC = 4 MHZ,
16 MHz internal
(PRI_RUN mode,
HSPLL oscillator)
5.55 6.5 mA +25°C
5.3 6.5 mA +85°C
All devices 7.4 8.5 mA -40°C
VDD = 2.5V,
VDDCORE = 2.5V(4)
FOSC = 10 MHZ,
40 MHz internal
(PRI_RUN mode,
HSPLL oscillator)
7.23 8.5 mA +25°C
6.55 7.5 mA +85°C
All devices 9.74 11.6 mA -40°C
VDD = 3.3V(5)
FOSC = 10 MHZ,
40 MHz internal
(PRI_RUN mode,
HSPLL oscillator)
9.43 11.6 mA +25°C
8.89 10.5 mA +85°C
26.2 DC Characteristics: Power-Down and Supply Current
PIC18F85J90 Family (Industrial) (Continued)
PIC18F85J90 Family
(Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
Param
No. Device Typ Max Units Conditions
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in a high-impedance state and tied to VDD or VSS, and all features that add delta
current disabled (such as WDT, Timer1 oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature
crystals are available at a much higher cost.
4: Voltage regulator is disabled (ENVREG tied to VSS).
5: Voltage regulator is enabled (ENVREG tied to VDD).
6: Resistor ladder current is not included.
7: Connecting an actual display will increase the current consumption depending on the size of the LCD.
2010 Microchip Technology Inc. DS39770C-page 367
PIC18F85J90 FAMILY
Supply Current (IDD)(2)
All devices 50 120 µA -40°C
VDD = 2.0V,
VDDCORE = 2.0V(4)
FOSC = 1 MHz
(PRI_IDLE mode,
EC oscillator)
51 120 µA +25°C
54 130 µA +85°C
All devices 223 480 µA -40°C
VDD = 2.5V,
VDDCORE = 2.5V(4)
133 300 µA +25°C
110 270 µA +85°C
All devices 307 550 µA -40°C
VDD = 3.3V(5)
254 500 µA +25°C
194 460 µA +85°C
All devices 307 850 µA -40°C
VDD = 2.0V,
VDDCORE = 2.0V(4)
FOSC = 4 MHz
(PRI_IDLE mode,
EC oscillator)
200 850 µA +25°C
202 800 µA +85°C
All devices 483 950 µA -40°C
VDD = 2.5V,
VDDCORE = 2.5V(4)
318 950 µA +25°C
343 900 µA +85°C
All devices 0.52 1.3 mA -40°C
VDD = 3.3V(5)
0.48 1.2 mA +25°C
0.47 1.2 mA +85°C
All devices 2.38 8 mA -40°C
VDD = 2.5V,
VDDCORE = 2.5V(4)
FOSC = 40 MHz
(PRI_IDLE mode,
EC oscillator)
2.04 8 mA +25°C
2.52 9 mA +85°C
All devices 3.02 10 mA -40°C
VDD = 3.3V(5)
2.99 10 mA +25°C
4.23 11 mA +85°C
26.2 DC Characteristics: Power-Down and Supply Current
PIC18F85J90 Family (Industrial) (Continued)
PIC18F85J90 Family
(Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
Param
No. Device Typ Max Units Conditions
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in a high-impedance state and tied to VDD or VSS, and all features that add delta
current disabled (such as WDT, Timer1 oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature
crystals are available at a much higher cost.
4: Voltage regulator is disabled (ENVREG tied to VSS).
5: Voltage regulator is enabled (ENVREG tied to VDD).
6: Resistor ladder current is not included.
7: Connecting an actual display will increase the current consumption depending on the size of the LCD.
PIC18F85J90 FAMILY
DS39770C-page 368 2010 Microchip Technology Inc.
Supply Current (IDD)(2)
All devices 10.5 22 µA -40°C
VDD = 2.0V,
VDDCORE = 2.0V(4)
FOSC = 32 kHz(3)
(SEC_RUN mode,
Timer1 as clock)
13.4 28 µA +25°C
17.6 40 µA +85°C
All devices 13.2 30 µA -40°C
VDD = 2.5V,
VDDCORE = 2.5V(4)
16.2 35 µA +25°C
20.7 50 µA +85°C
All devices 39 120 µA -40°C
VDD = 3.3V(5)
58 150 µA +25°C
75 190 µA +85°C
All devices 5.7 15 µA -40°C
VDD = 2.0V,
VDDCORE = 2.0V(4)
FOSC = 32 kHz(3)
(SEC_IDLE mode,
Timer1 as clock)
8.9 20 µA +25°C
12.8 26 µA +85°C
All devices 6.6 17 µA -40°C
VDD = 2.5V,
VDDCORE = 2.5V(4)
9.7 24 µA +25°C
13.7 30 µA +85°C
All devices 39 115 µA -40°C
VDD = 3.3V(5)
52.8 145 µA +25°C
72.7 185 µA +85°C
26.2 DC Characteristics: Power-Down and Supply Current
PIC18F85J90 Family (Industrial) (Continued)
PIC18F85J90 Family
(Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
Param
No. Device Typ Max Units Conditions
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in a high-impedance state and tied to VDD or VSS, and all features that add delta
current disabled (such as WDT, Timer1 oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature
crystals are available at a much higher cost.
4: Voltage regulator is disabled (ENVREG tied to VSS).
5: Voltage regulator is enabled (ENVREG tied to VDD).
6: Resistor ladder current is not included.
7: Connecting an actual display will increase the current consumption depending on the size of the LCD.
2010 Microchip Technology Inc. DS39770C-page 369
PIC18F85J90 FAMILY
D022
(IWDT)
Module Differential Currents (IWDT, ILCD, IOSCB, IAD)
Watchdog Timer 1.6 4 µA -40°C VDD = 2.0V,
VDDCORE = 2.0V(4)
1.7 4 µA +25°C
1.6 4 µA +85°C
2.5 5 µA -40°C VDD = 2.5V,
VDDCORE = 2.5V(4)
2.5 5 µA +25°C
2.3 5 µA +85°C
3.8 6 µA -40°C
VDD = 3.3V(5)
2.6 6 µA +25°C
2.4 6 µA +85°C
D024
(ILCD)
LCD Module 2(6,7) 5 µA +25°C VDD = 2.0V Resistive Ladder
CPEN = 0;
CKSEL<1:0> = 00;
CS<1:0> = 10;
LP<3:0> = 0100
2.7(6,7) 5 µA +25°C VDD = 2.5V
3.5(6,7) 7 µA +25°C VDD = 3.0V
16(7) 25 µA +25°C VDD = 2.0V Charge Pump
BIAS<2:0> = 111;
CPEN = 1;
CKSEL<1:0> = 11;
CS<1:0> = 10
17(7) 25 µA +25°C VDD = 2.5V
24(7) 40 µA +25°C VDD = 3.0V
D025
(IOSCB)
Timer1 Oscillator 6.6 12.5 µA -40°C VDD = 2.0V,
VDDCORE = 2.0V(4) 32 kHz on Timer1(3)
7.9 12.5 µA +25°C
11.5 18.5 µA +85°C
7.2 12.5 µA -40°C VDD = 2.5V,
VDDCORE = 2.5V(4) 32 kHz on Timer1(3)
8.1 12.5 µA +25°C
11.9 18.5 µA +85°C
7 12.5 µA -40°C
VDD = 3.3V(5) 32 kHz on Timer1(3)
9 12.5 µA +25°C
11 18.5 µA +85°C
D026
(IAD)
A/D Converter 1 1.5 µA -40°C to +85°C VDD = 2.0V,
VDDCORE = 2.0V(4)
A/D on, not converting1 1.5 µA -40°C to +85°C VDD = 2.5V,
VDDCORE = 2.5V(4)
1 1.5 µA -40°C to +85°C VDD = 3.3V(5)
26.2 DC Characteristics: Power-Down and Supply Current
PIC18F85J90 Family (Industrial) (Continued)
PIC18F85J90 Family
(Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
Param
No. Device Typ Max Units Conditions
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in a high-impedance state and tied to VDD or VSS, and all features that add delta
current disabled (such as WDT, Timer1 oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature
crystals are available at a much higher cost.
4: Voltage regulator is disabled (ENVREG tied to VSS).
5: Voltage regulator is enabled (ENVREG tied to VDD).
6: Resistor ladder current is not included.
7: Connecting an actual display will increase the current consumption depending on the size of the LCD.
PIC18F85J90 FAMILY
DS39770C-page 370 2010 Microchip Technology Inc.
26.3 DC Characteristics:PIC18F84J90 Family (Industrial)
DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
Param
No. Symbol Characteristic Min Max Units Conditions
VIL Input Low Voltage
All I/O Ports:
D030 with TTL Buffer VSS 0.15 VDD VVDD < 3.3V
D30A — 0.8 V 3.3V VDD 3.6V
D031 with Schmitt Trigger Buffer VSS 0.2 VDD V
D031A RC3 and RC4 VSS 0.3 VDD VI
2C™ enabled
D031B VSS 0.8 V SMBus enabled
D032 MCLR VSS 0.2 VDD V
D033 OSC1 VSS 0.3 VDD V HS, HSPLL modes
D033A
D034
OSC1
T13CKI
VSS
VSS
0.2 VDD
0.3
V
V
EC, ECPLL modes
VIH Input High Voltage
I/O Ports with non 5.5V Tolerance:(2)
D040 with TTL Buffer 0.25 VDD + 0.8V VDD VVDD < 3.3V
D040A 2.0 VDD V3.3V VDD 3.6V
D041 with Schmitt Trigger Buffer 0.8 VDD VDD V
D041A RC3 and RC4 0.7 VDD VDD VI
2C™ enabled
D041B 2.1 VDD V SMBus enabled,
VDD < 3.3V
I/O Ports with 5.5V Tolerance:(2)
with TTL Buffer 0.25 VDD + 0.8V 5.5 V VDD < 3.3V
2.0 5.5 V 3.3V VDD 3.6V
with Schmitt Trigger Buffer 0.8 VDD 5.5 V
D042 MCLR 0.8 VDD VDD V
D043 OSC1 0.7 VDD VDD V HS, HSPLL modes
D043A
D044
OSC1
T13CKI
0.8 VDD
1.6
VDD
VDD
V
V
EC, ECPLL modes
IIL Input Leakage Current(1)
D060 I/O Ports with non 5.5V tolerance:(2) — 200 nA VSS VPIN VDD,
Pin at high-impedance
I/O Ports with 5.5V tolerance:(2) — 200 nA VSS VPIN 5.5V,
Pin at high-impedance
D061 MCLR —1AVSS VPIN VDD
D063 OSC1 — 1AVSS VPIN VDD
IPU Weak Pull-up Current
D070 IPURB PORTB Weak Pull-up Current 30 400 AVDD = 3.3V, VPIN = VSS
Note 1: Negative current is defined as current sourced by the pin.
2: Refer to Table 10-1 for the pins that have corresponding tolerance limits.
2010 Microchip Technology Inc. DS39770C-page 371
PIC18F85J90 FAMILY
VOL Output Low Voltage
D080 I/O Ports:
PORTA, PORTF, PORTG,
PORTH
—0.4VI
OL = 3.4 mA, VDD = 3.3V,
-40C to +85C
PORTD, PORTE, PORTJ — 0.4 V IOL = 3.4 mA, VDD = 3.3V,
-40C to +85C
PORTB, PORTC — 0.4 V IOL = 8.5 mA, VDD = 3.3V,
-40C to +85C
D083 OSC2/CLKO
(EC, ECPLL modes)
—0.4VI
OL = 1.6 mA, VDD = 3.3V,
-40C to +85C
VOH Output High Voltage(1)
D090 I/O Ports: V
PORTA, PORTF, PORTG,
PORTH
2.4 — V IOH = -2 mA, VDD = 3.3V,
-40C to +85C
PORTD, PORTE, PORTJ 2.4 — V IOH = -2 mA, VDD = 3.3V,
-40C to +85C
PORTB, PORTC 2.4 — V IOH = -6 mA, VDD = 3.3V,
-40C to +85C
D092 OSC2/CLKO
(INTOSC, EC, ECPLL modes)
2.4 — V IOH = -1 mA, VDD = 3.3V,
-40C to +85C
Capacitive Loading Specs
on Output Pins
D100 COSC2 OSC2 Pin — 15 pF In HS mode when
external clock is used to
drive OSC1
D101 CIO All I/O Pins and OSC2 — 50 pF To meet the AC Timing
Specifications
D102 CBSCL, SDA — 400 pF I2C™ Specification
26.3 DC Characteristics:PIC18F84J90 Family (Industrial) (Continued)
DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
Param
No. Symbol Characteristic Min Max Units Conditions
Note 1: Negative current is defined as current sourced by the pin.
2: Refer to Table 10-1 for the pins that have corresponding tolerance limits.
PIC18F85J90 FAMILY
DS39770C-page 372 2010 Microchip Technology Inc.
TABLE 26-1: MEMORY PROGRAMMING REQUIREMENTS
TABLE 26-2: COMPARATOR SPECIFICATIONS
DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C T
A +85°C for industrial
Param
No. Sym Characteristic Min Typ† Max Units Conditions
Program Flash Memory
D130 EPCell Endurance 100 1K — E/W -40C to +85C
D131 VPR VDD for Read VMIN —3.6VVMIN = Minimum operating
voltage
D132 VPEW Voltage for Self-Timed Erase or
Write:
VDD 2.35 — 3.6 V ENVREG tied to VDD
VDDCORE 2.25 — 2.7 V ENVREG tied to VSS
D133A TIW Self-Timed Write Cycle Time — 2.8 — ms
D133B TIE Self-Timed Block Erased Cycle
Time
—33—ms
D134 TRETD Characteristic Retention 20 — — Year Provided no other
specifications are violated
D135 IDDP Supply Current during
Programming
—3 7mA
D1xxx TWE Writes per Erase Cycle — — 1 Per one physical word
address
† Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Operating Conditions: 3.0V VDD 3.6V, -40°C TA +85°C (unless otherwise stated)
Param
No. Sym Characteristics Min Typ Max Units Comments
D300 VIOFF Input Offset Voltage — ±5.0 ±25 mV
D301 VICM Input Common Mode Voltage 0 — AVDD – 1.5 V
D302 CMRR Common Mode Rejection Ratio 55 — — dB
D303 TRESP Response Time(1) — 150 400 ns
D304 TMC2OV Comparator Mode Change to
Output Valid*
—— 10 s
D305 VIRV Internal Reference Voltage — 1.2 — V
Note 1: Response time measured with one comparator input at (AVDD – 1.5)/2, while the other input transitions
from VSS to VDD.
2010 Microchip Technology Inc. DS39770C-page 373
PIC18F85J90 FAMILY
TABLE 26-3: VOLTAGE REFERENCE SPECIFICATIONS
TABLE 26-4: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS
TABLE 26-5: INTERNAL LCD VOLTAGE REGULATOR SPECIFICATIONS
Operating Conditions: 3.0V VDD 3.6V, -40°C TA +85°C (unless otherwise stated)
Param
No. Sym Characteristics Min Typ Max Units Comments
D310 VRES Resolution VDD/24 — VDD/32 LSb
D311 VRAA Absolute Accuracy — — 1/2 LSb
D312 VRUR Unit Resistor Value (R) — 2k —
D313 TSET Settling Time(1) — — 10 s
Note 1: Settling time measured while CVRR = 1 and CVR<3:0> transitions from ‘0000’ to ‘1111’.
Operating Conditions: -40°C TA +85°C (unless otherwise stated)
Param
No. Sym Characteristics Min Typ Max Units Comments
VRGOUT Regulator Output Voltage — 2.5 — V
CEFC External Filter Capacitor Value 4.7 10 — FCapacitor must be low
series resistance
(<5 Ohms)
Operating Conditions: 2.0V VDD 3.6V, -40°C TA +85°C (unless otherwise stated)
Param
No. Sym Characteristics Min Typ Max Units Comments
CFLY Fly Back Capacitor 0.47 4.7 — F Capacitor must be low-ESR
VBIAS VPK-PK between LCDBIAS0
and LCDBIAS3
— 3.40 3.6 V BIAS<2:0> = 111
— 3.27 — V BIAS<2:0> = 110
— 3.14 — V BIAS<2:0> = 101
— 3.01 — V BIAS<2:0> = 100
— 2.88 — V BIAS<2:0> = 011
— 2.75 — V BIAS<2:0> = 010
— 2.62 — V BIAS<2:0> = 001
— 2.49 — V BIAS<2:0> = 000
PIC18F85J90 FAMILY
DS39770C-page 374 2010 Microchip Technology Inc.
26.4 AC (Timing) Characteristics
26.4.1 TIMING PARAMETER SYMBOLOGY
The timing parameter symbols have been created
following one of the following formats:
1. TppS2ppS 3. TCC:ST (I2C specifications only)
2. TppS 4. Ts (I2C specifications only)
T
F Frequency T Time
Lowercase letters (pp) and their meanings:
pp
cc CCP1 osc OSC1
ck CLKO rd RD
cs CS rw RD or WR
di SDI sc SCK
do SDO ss SS
dt Data in t0 T0CKI
io I/O port t1 T13CKI
mc MCLR wr WR
Uppercase letters and their meanings:
S
F Fall P Period
HHigh RRise
I Invalid (High-Impedance) V Valid
L Low Z High-Impedance
I2C only
AA output access High High
BUF Bus free Low Low
T
CC:ST (I2C specifications only)
CC
HD Hold SU Setup
ST
DAT DATA input hold STO Stop condition
STA Start condition
2010 Microchip Technology Inc. DS39770C-page 375
PIC18F85J90 FAMILY
26.4.2 TIMING CONDITIONS
The temperature and voltages specified in Table 26-6
apply to all timing specifications unless otherwise
noted. Figure 26-3 specifies the load conditions for the
timing specifications.
TABLE 26-6: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC
FIGURE 26-3: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
AC CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
Operating voltage VDD range as described in Section 26.1 and Section 26.3.
VDD/2
CL
RL
Pin Pin
VSS VSS
CL
RL= 464
CL= 50 pF for all pins except OSC2/CLKO/RA6
and including D and E outputs as ports
CL= 15 pF for OSC2/CLKO/RA6
Load Condition 1 Load Condition 2
PIC18F85J90 FAMILY
DS39770C-page 376 2010 Microchip Technology Inc.
26.4.3 TIMING DIAGRAMS AND SPECIFICATIONS
FIGURE 26-4: EXTERNAL CLOCK TIMING
TABLE 26-7: EXTERNAL CLOCK TIMING REQUIREMENTS
Param.
No. Symbol Characteristic Min Max Units Conditions
1A FOSC External CLKI Frequency(1) DC 40 MHz ECPLL Oscillator mode
Oscillator Frequency(1) DC 40 MHz HSPLL Oscillator mode
1TOSC External CLKI Period(1) 25 — ns EC Oscillator mode
Oscillator Period(1) 25 250 ns HS Oscillator mode
2T
CY Instruction Cycle Time(1) 100 — ns TCY = 4/FOSC, Industrial
3TOSL,
T
OSH
External Clock in (OSC1)
High or Low Time
10 — ns EC Oscillator mode
4T
OSR,
T
OSF
External Clock in (OSC1)
Rise or Fall Time
— 7.5 ns EC Oscillator mode
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period for all configurations
except PLL. All specified values are based on characterization data for that particular oscillator type under
standard operating conditions with the device executing code. Exceeding these specified limits may result
in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested
to operate at “min.” values with an external clock applied to the OSC1/CLKI pin. When an external clock
input is used, the “max.” cycle time limit is “DC” (no clock) for all devices.
OSC1
CLKO
Q4 Q1 Q2 Q3 Q4 Q1
1
2
3344
2010 Microchip Technology Inc. DS39770C-page 377
PIC18F85J90 FAMILY
TABLE 26-8: PLL CLOCK TIMING SPECIFICATIONS (VDD = 2.15V TO 3.6V)
TABLE 26-9: INTERNAL RC ACCURACY (INTOSC AND INTRC SOURCES)
Param
No. Sym Characteristic Min Typ† Max Units Conditions
F10 FOSC Oscillator Frequency Range 4 — 10 MHz HS mode only
F11 FSYS On-Chip VCO System Frequency 16 — 40 MHz HS mode only
F12 trc PLL Start-up Time (Lock Time) — — 2 ms
F13 CLK CLKO Stability (Jitter) -2 — +2 %
† Data in “Typ” column is at 3.3V, 25C, unless otherwise stated. These parameters are for design guidance
only and are not tested.
PIC18F85J90 Family
(Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C T
A +85°C for industrial
Param
No. Device Min Typ Max Units Conditions
INTOSC Accuracy @ Freq = 8 MHz, 4 MHz, 2 MHz, 1 MHz, 500 kHz, 250 kHz, 125 kHz, 31 kHz(1)
All Devices -2 ±1 2 % +25°C VDD = 2.7-3.3V
-5 — 5 % -10°C to +85°C VDD = 2.0-3.3V
-10 ±1 10 % -40°C to +85°C VDD = 2.0-3.3V
INTRC Accuracy @ Freq = 31 kHz(1)
All Devices 26.562 — 35.938 kHz -40°C to +85°C VDD = 2.0-3.3V
Note 1: The accuracy specification of the 31 kHz clock is determined by which source is providing it at a given
time. When INTSRC (OSCTUNE<7>) is ‘1’, use the INTOSC accuracy specification. When INTSRC is ‘0’,
use the INTRC accuracy specification.
PIC18F85J90 FAMILY
DS39770C-page 378 2010 Microchip Technology Inc.
FIGURE 26-5: CLKO AND I/O TIMING
TABLE 26-10: CLKO AND I/O TIMING REQUIREMENTS
Param
No. Symbol Characteristic Min Typ Max Units Conditions
10 TOSH2CKLOSC1 to CLKO —75200ns(Note 1)
11 TOSH2CKHOSC1 to CLKO —75200ns(Note 1)
12 TCKRCLKO Rise Time — 15 30 ns(Note 1)
13 TCKF CLKO Fall Time — 15 30 ns (Note 1)
14 TCKL2IOVCLKO to Port Out Valid — — 0.5 TCY + 20 ns
15 TIOV2CKH Port In Valid before CLKO 0.25 TCY + 25 — — ns
16 TCKH2IOI Port In Hold after CLKO 0——ns
17 TOSH2IOVOSC1 (Q1 cycle) to Port Out Valid — 50 150 ns
18 TOSH2IOIOSC1 (Q2 cycle) to Port Input Invalid
(I/O in hold time)
100 — — ns
19 TIOV2OSH Port Input Valid to OSC1
(I/O in setup time)
0——ns
20 TIOR Port Output Rise Time — — 6 ns
21 TIOF Port Output Fall Time — — 5 ns
22† TINP INTx Pin High or Low Time TCY ——ns
23† TRBP RB<7:4> Change INTx High or Low Time TCY ——ns
† These parameters are asynchronous events not related to any internal clock edges.
Note 1: Measurements are taken in EC mode, where CLKO output is 4 x TOSC.
Note: Refer to Figure 26-3 for load conditions.
OSC1
CLKO
I/O pin
(Input)
I/O pin
(Output)
Q4 Q1 Q2 Q3
10
13
14
17
20, 21
19 18
15
11
12
16
Old Value New Value
2010 Microchip Technology Inc. DS39770C-page 379
PIC18F85J90 FAMILY
FIGURE 26-6: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND
POWER-UP TIMER TIMING
TABLE 26-11: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET REQUIREMENTS
Param.
No. Symbol Characteristic Min Typ Max Units Conditions
30 TMCLMCLR Pulse Width (low) 2 TCY 10 TCY —(Note 1)
31 TWDT Watchdog Timer Time-out Period
(no postscaler)
3.4 4.0 4.6 ms
32 T
OST Oscillation Start-up Timer Period 1024 TOSC — 1024 TOSC —TOSC = OSC1 period
33 TPWRT Power-up Timer Period 45.8 65.5 85.2 ms
34 TIOZ I/O High-Impedance from MCLR
Low or Watchdog Timer Reset
—2—s
38 T
CSD CPU Start-up Time — 10 — s
—200— s Voltage regulator
enabled and put to
Sleep
39 TIOBST Time for INTOSC to Stabilize — 1 — s
Note 1: To ensure device Reset, MCLR must be low for at least 2 TCY or 400 µs, whichever is lower.
VDD
MCLR
Internal
POR
PWRT
Time-out
Oscillator
Time-out
Internal
Reset
Watchdog
Timer
Reset
33
32
30
31
34
I/O pins
34
Note: Refer to Figure 26-3 for load conditions.
PIC18F85J90 FAMILY
DS39770C-page 380 2010 Microchip Technology Inc.
FIGURE 26-7: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
TABLE 26-12: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Param
No. Symbol Characteristic Min Max Units Conditions
40 TT0H T0CKI High Pulse Width No prescaler 0.5 TCY + 20 — ns
With prescaler 10 — ns
41 TT0L T0CKI Low Pulse Width No prescaler 0.5 TCY + 20 — ns
With prescaler 10 — ns
42 TT0P T0CKI Period No prescaler TCY + 10 — ns
With prescaler Greater of:
20 ns or
(TCY + 40)/N
—nsN = prescale
value
(1, 2, 4,..., 256)
45 TT1H T13CKI High
Time
Synchronous, no prescaler 0.5 TCY + 20 — ns
Synchronous, with prescaler 10 — ns
Asynchronous 30 — ns
46 TT1L T13CKI Low
Time
Synchronous, no prescaler 0.5 TCY + 5 — ns
Synchronous, with prescaler 10 — ns
Asynchronous 30 — ns
47 TT1P T13CKI Input
Period
Synchronous Greater of:
20 ns or
(TCY + 40)/N
—nsN = prescale
value
(1, 2, 4, 8)
Asynchronous 60 — ns
FT1 T13CKI Oscillator Input Frequency Range DC 50 kHz
48 T
CKE2TMRI Delay from External T13CKI Clock Edge to
Timer Increment
2 TOSC 7 TOSC —
Note: Refer to Figure 26-3 for load conditions.
46
47
45
48
41
42
40
T0CKI
T1OSO/T13CKI
TMR0 or
TMR1
2010 Microchip Technology Inc. DS39770C-page 381
PIC18F85J90 FAMILY
FIGURE 26-8: CAPTURE/COMPARE/PWM TIMINGS (CCP1, CCP2 MODULES)
TABLE 26-13: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1, CCP2 MODULES)
Param
No. Symbol Characteristic Min Max Units Conditions
50 TCCL CCPx Input Low
Time
No prescaler 0.5 TCY + 20 — ns
With prescaler 10 — ns
51 TCCH CCPx Input
High Time
No prescaler 0.5 TCY + 20 — ns
With prescaler 10 — ns
52 TCCP CCPx Input Period 3 TCY + 40
N
— ns N = prescale
value (1, 4 or 16)
53 TCCR CCPx Output Fall Time — 25 ns
54 TCCF CCPx Output Fall Time — 25 ns
Note: Refer to Figure 26-3 for load conditions.
CCPx
(Capture Mode)
50 51
52
CCPx
53 54
(Compare or PWM Mode)
PIC18F85J90 FAMILY
DS39770C-page 382 2010 Microchip Technology Inc.
FIGURE 26-9: EXAMPLE SPI MASTER MODE TIMING (CKE = 0)
TABLE 26-14: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0)
Param
No. Symbol Characteristic Min Max Units Conditions
73 TDIV2SCH,
TDIV2SCL
Setup Time of SDI Data Input to SCK Edge 20 — ns
73A TB2BLast Clock Edge of Byte 1 to the 1st Clock Edge
of Byte 2
1.5 TCY + 40 — ns (Note 1)
74 T
SCH2DIL,
T
SCL2DIL
Hold Time of SDI Data Input to SCK Edge 40 — ns
75 TDOR SDO Data Output Rise Time — 25 ns
76 TDOF SDO Data Output Fall Time — 25 ns
78 T
SCR SCK Output Rise Time (Master mode) — 25 ns
79 T
SCF SCK Output Fall Time (Master mode) — 25 ns
80 TSCH2DOV,
T
SCL2DOV
SDO Data Output Valid after SCK Edge — 50 ns
Note 1: Only if Parameter #71A and #72A are used.
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
70
71 72
73
74
75, 76
78
79
80
79
78
MSb LSb
bit 6 - - - - - - 1
LSb In
bit 6 - - - - 1
Note: Refer to Figure 26-3 for load conditions.
MSb In
2010 Microchip Technology Inc. DS39770C-page 383
PIC18F85J90 FAMILY
FIGURE 26-10: EXAMPLE SPI MASTER MODE TIMING (CKE = 1)
TABLE 26-15: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1)
Param.
No. Symbol Characteristic Min Max Units Conditions
73 TDIV2SCH,
TDIV2SCL
Setup Time of SDI Data Input to SCK Edge 20 — ns
73A TB2BLast Clock Edge of Byte 1 to the 1st Clock Edge
of Byte 2
1.5 TCY + 40 — ns (Note 1)
74 T
SCH2DIL,
T
SCL2DIL
Hold Time of SDI Data Input to SCK Edge 40 — ns
75 TDOR SDO Data Output Rise Time — 25 ns
76 TDOF SDO Data Output Fall Time — 25 ns
78 T
SCR SCK Output Rise Time (Master mode) — 25 ns
79 T
SCF SCK Output Fall Time (Master mode) — 25 ns
80 T
SCH2DOV,
T
SCL2DOV
SDO Data Output Valid after SCK Edge — 50 ns
81 TDOV2SCH,
TDOV2SCL
SDO Data Output Setup to SCK Edge T
CY —ns
Note 1: Only if Parameter #71A and #72A are used.
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
81
71 72
74
75, 76
78
80
MSb
79
73
bit 6 - - - - - - 1
LSb In
bit 6 - - - - 1
LSb
Note: Refer to Figure 26-3 for load conditions.
MSb In
PIC18F85J90 FAMILY
DS39770C-page 384 2010 Microchip Technology Inc.
FIGURE 26-11: EXAMPLE SPI SLAVE MODE TIMING (CKE = 0)
TABLE 26-16: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING, CKE = 0)
Param
No. Symbol Characteristic Min Max Units Conditions
70 T
SSL2SCH,
T
SSL2SCL
SS to SCK or SCK Input 3 TCY —ns
70A T
SSL2WB SS to Write to SSPBUF 3 TCY —ns
71 T
SCH SCK Input High Time (Slave mode) Continuous 1.25 TCY + 30 — ns
71A Single byte 40 — ns (Note 1)
72 TSCL SCK Input Low Time (Slave mode) Continuous 1.25 TCY + 30 — ns
72A Single byte 40 — ns (Note 1)
73 TDIV2SCH,
TDIV2SCL
Setup Time of SDI Data Input to SCK Edge 20 — ns
73A TB2BLast Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40 — ns (Note 2)
74 T
SCH2DIL,
T
SCL2DIL
Hold Time of SDI Data Input to SCK Edge 40 — ns
75 TDOR SDO Data Output Rise Time — 25 ns
76 TDOF SDO Data Output Fall Time — 25 ns
77 T
SSH2DOZSS to SDO Output High-Impedance 10 50 ns
78 T
SCR SCK Output Rise Time (Master mode) — 25 ns
79 T
SCF SCK Output Fall Time (Master mode) — 25 ns
80 T
SCH2DOV,
T
SCL2DOV
SDO Data Output Valid after SCK Edge — 50 ns
83 T
SCH2SSH,
T
SCL2SSH
SS after SCK Edge 1.5 TCY + 40 — ns
Note 1: Requires the use of Parameter #73A.
2: Only if Parameter #71A and #72A are used.
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
70
71 72
73
74
75, 76 77
78
79
80
79
78
MSb LSb
bit 6 - - - - - - 1
bit 6 - - - - 1 LSb In
83
Note: Refer to Figure 26-3 for load conditions.
MSb In
2010 Microchip Technology Inc. DS39770C-page 385
PIC18F85J90 FAMILY
FIGURE 26-12: EXAMPLE SPI SLAVE MODE TIMING (CKE = 1)
TABLE 26-17: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1)
Param
No. Symbol Characteristic Min Max Units Conditions
70 T
SSL2SCH,
T
SSL2SCL
SS to SCK or SCK Input 3 TCY —ns
70A TSSL2WB SS to Write to SSPBUF 3 TCY —ns
71 TSCH SCK Input High Time
(Slave mode)
Continuous 1.25 TCY + 30 — ns
71A Single byte 40 — ns (Note 1)
72 T
SCL SCK Input Low Time
(Slave mode)
Continuous 1.25 TCY + 30 — ns
72A Single byte 40 — ns (Note 1)
73A TB2BLast Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40 — ns (Note 2)
74 T
SCH2DIL,
T
SCL2DIL
Hold Time of SDI Data Input to SCK Edge 40 — ns
75 TDOR SDO Data Output Rise Time — 25 ns
76 TDOF SDO Data Output Fall Time — 25 ns
77 T
SSH2DOZSS to SDO Output High-Impedance 10 50 ns
78 T
SCR SCK Output Rise Time (Master mode) — 25 ns
79 T
SCF SCK Output Fall Time (Master mode) — 25 ns
80 T
SCH2DOV,
T
SCL2DOV
SDO Data Output Valid after SCK Edge — 50 ns
82 T
SSL2DOV SDO Data Output Valid after SS Edge — 50 ns
83 T
SCH2SSH,
T
SCL2SSH
SS after SCK Edge 1.5 TCY + 40 — ns
Note 1: Requires the use of Parameter #73A.
2: Only if Parameter #71A and #72A are used.
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
70
71 72
82
74
75, 76
MSb bit 6 - - - - - - 1 LSb
77
bit 6 - - - - 1 LSb In
80
83
Note: Refer to Figure 26-3 for load conditions.
MSb In
PIC18F85J90 FAMILY
DS39770C-page 386 2010 Microchip Technology Inc.
FIGURE 26-13: I2C™ BUS START/STOP BITS TIMING
TABLE 26-18: I2C™ BUS START/STOP BITS REQUIREMENTS (SLAVE MODE)
FIGURE 26-14: I2C™ BUS DATA TIMING
Param.
No. Symbol Characteristic Min Max Units Conditions
90 TSU:STA Start Condition 100 kHz mode 4700 — ns Only relevant for Repeated
Start condition
Setup Time 400 kHz mode 600 —
91 THD:STA Start Condition 100 kHz mode 4000 — ns After this period, the first
clock pulse is generated
Hold Time 400 kHz mode 600 —
92 TSU:STO Stop Condition 100 kHz mode 4700 — ns
Setup Time 400 kHz mode 600 —
93 THD:STO Stop Condition 100 kHz mode 4000 — ns
Hold Time 400 kHz mode 600 —
Note: Refer to Figure 26-3 for load conditions.
91
92
93
SCL
SDA
Start
Condition
Stop
Condition
90
Note: Refer to Figure 26-3 for load conditions.
90
91 92
100
101
103
106 107
109 109
110
102
SCL
SDA
In
SDA
Out
2010 Microchip Technology Inc. DS39770C-page 387
PIC18F85J90 FAMILY
TABLE 26-19: I2C™ BUS DATA REQUIREMENTS (SLAVE MODE)
Param.
No. Symbol Characteristic Min Max Units Conditions
100 THIGH Clock High Time 100 kHz mode 4.0 — s
400 kHz mode 0.6 — s
MSSP Module 1.5 TCY —s
101 TLOW Clock Low Time 100 kHz mode 4.7 — s
400 kHz mode 1.3 — s
MSSP Module 1.5 TCY —s
102 TRSDA and SCL Rise Time 100 kHz mode — 1000 ns
400 kHz mode 20 + 0.1 CB300 ns CB is specified to be from
10 to 400 pF
103 TFSDA and SCL Fall Time 100 kHz mode — 300 ns
400 kHz mode 20 + 0.1 CB300 ns CB is specified to be from
10 to 400 pF
90 TSU:STA Start Condition Setup Time 100 kHz mode 4.7 — s Only relevant for Repeated
Start condition
400 kHz mode 0.6 — s
91 THD:STA Start Condition Hold Time 100 kHz mode 4.0 — s After this period, the first clock
pulse is generated
400 kHz mode 0.6 — s
106 THD:DAT Data Input Hold Time 100 kHz mode 0 — ns
400 kHz mode 0 0.9 s
107 TSU:DAT Data Input Setup Time 100 kHz mode 250 — ns (Note 2)
400 kHz mode 100 — ns
92 TSU:STO Stop Condition Setup Time 100 kHz mode 4.7 — s
400 kHz mode 0.6 — s
109 TAA Output Valid from Clock 100 kHz mode — 3500 ns (Note 1)
400 kHz mode — — ns
110 TBUF Bus Free Time 100 kHz mode 4.7 — s Time the bus must be free before
a new transmission can start
400 kHz mode 1.3 — s
D102 CBBus Capacitive Loading — 400 pF
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of
the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
2: A Fast mode I2C™ bus device can be used in a Standard mode I2C bus system, but the requirement, TSU:DAT 250 ns,
must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If
such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line,
TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification), before the SCL line
is released.
PIC18F85J90 FAMILY
DS39770C-page 388 2010 Microchip Technology Inc.
FIGURE 26-15: MSSP I2C™ BUS START/STOP BITS TIMING WAVEFORMS
TABLE 26-20: MSSP I2C™ BUS START/STOP BITS REQUIREMENTS
FIGURE 26-16: MSSP I2C™ BUS DATA TIMING
Param.
No. Symbol Characteristic Min Max Units Conditions
90 TSU:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) — Only relevant for
Repeated Start
condition
Setup Time 400 kHz mode 2(TOSC)(BRG + 1) —
1 MHz mode(1,2) 2(TOSC)(BRG + 1) —
91 THD:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) — After this period, the
first clock pulse is
generated
Hold Time 400 kHz mode 2(TOSC)(BRG + 1) —
1 MHz mode(1,2) 2(TOSC)(BRG + 1) —
92 TSU:STO Stop Condition 100 kHz mode 2(TOSC)(BRG + 1) —
Setup Time 400 kHz mode 2(TOSC)(BRG + 1) —
1 MHz mode(1,2) 2(TOSC)(BRG + 1) —
93 THD:STO Stop Condition 100 kHz mode 2(TOSC)(BRG + 1) —
Hold Time 400 kHz mode 2(TOSC)(BRG + 1) —
1 MHz mode(1,2) 2(TOSC)(BRG + 1) —
Note 1: Maximum pin capacitance = 10 pF for all I2C™ pins.
2: A minimum 16 MHz FOSC is required for 1 MHz I2C.
Note: Refer to Figure 26-3 for load conditions.
91 93
SCL
SDA
Start
Condition
Stop
Condition
90 92
Note: Refer to Figure 26-3 for load conditions.
90 91 92
100
101
103
106 107
109 109 110
102
SCL
SDA
In
SDA
Out
2010 Microchip Technology Inc. DS39770C-page 389
PIC18F85J90 FAMILY
TABLE 26-21: MSSP I2C™ BUS DATA REQUIREMENTS
Param.
No. Symbol Characteristic Min Max Units Conditions
100 THIGH Clock High
Time
100 kHz mode 2(TOSC)(BRG + 1) —
400 kHz mode 2(TOSC)(BRG + 1) —
1 MHz mode(1,2) 2(TOSC)(BRG + 1) —
101 TLOW Clock Low Time 100 kHz mode 2(TOSC)(BRG + 1) —
400 kHz mode 2(TOSC)(BRG + 1) —
1 MHz mode(1,2) 2(TOSC)(BRG + 1) —
102 TRSDA and SCL
Rise Time
100 kHz mode — 1000 ns CB is specified to be from
10 to 400 pF
400 kHz mode 20 + 0.1 CB300 ns
1 MHz mode(1,2) — 300 ns
103 TFSDA and SCL
Fall Time
100 kHz mode — 300 ns CB is specified to be from
10 to 400 pF
400 kHz mode 20 + 0.1 CB 300 ns
1 MHz mode(1,2) — 100 ns
90 T
SU:STA Start Condition
Setup Time
100 kHz mode 2(TOSC)(BRG + 1) — Only relevant for Repeated
Start condition
400 kHz mode 2(TOSC)(BRG + 1) —
1 MHz mode(1,2) 2(TOSC)(BRG + 1) —
91 THD:STA Start Condition
Hold Time
100 kHz mode 2(TOSC)(BRG + 1) — After this period, the first
clock pulse is generated
400 kHz mode 2(TOSC)(BRG + 1) —
1 MHz mode(1,2) 2(TOSC)(BRG + 1) —
106 THD:DAT Data Input
Hold Time
100 kHz mode 0 — ns
400 kHz mode 0 0.9 s
1 MHz mode(1,2) ——ns
107 TSU:DAT Data Input
Setup Time
100 kHz mode 250 — ns (Note 3)
400 kHz mode 100 — ns
1 MHz mode(1,2) ——ns
92 TSU:STO Stop Condition
Setup Time
100 kHz mode 2(TOSC)(BRG + 1) —
400 kHz mode 2(TOSC)(BRG + 1) —
1 MHz mode(1,2) 2(TOSC)(BRG + 1) —
109 TAA Output Valid
from Clock
100 kHz mode — 3500 ns
400 kHz mode — 1000 ns
1 MHz mode(1,2) ——ns
110 TBUF Bus Free Time 100 kHz mode 4.7 — s Time the bus must be free
before a new transmission
can start
400 kHz mode 1.3 — s
1 MHz mode(1,2) ——s
D102 CBBus Capacitive Loading — 400 pF
Note 1: Maximum pin capacitance = 10 pF for all I2C™ pins.
2: A minimum 16 MHz FOSC is required for 1 MHz I2C.
3: A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but parameter
#107 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW
period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the
next data bit to the SDA line, parameter #102 + parameter #107 = 1000 + 250 = 1250 ns (for 100 kHz
mode), before the SCL line is released.
PIC18F85J90 FAMILY
DS39770C-page 390 2010 Microchip Technology Inc.
FIGURE 26-17: EUSART/AUSART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
TABLE 26-22: EUSART/AUSART SYNCHRONOUS TRANSMISSION REQUIREMENTS
FIGURE 26-18: EUSART/AUSART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
TABLE 26-23: EUSART/AUSART SYNCHRONOUS RECEIVE REQUIREMENTS
Param
No. Symbol Characteristic Min Max Units Conditions
120 T
CKH2DTV SYNC XMIT (MASTER and SLAVE)
Clock High to Data Out Valid — 40 ns
121 TCKRF Clock Out Rise Time and Fall Time (Master mode) — 20 ns
122 TDTRF Data Out Rise Time and Fall Time — 20 ns
Param.
No. Symbol Characteristic Min Max Units Conditions
125 TDTV2CKL SYNC RCV (MASTER and SLAVE)
Data Hold before CKx (DTx hold time) 10 — ns
126 TCKL2DTL Data Hold after CKx (DTx hold time) 15 — ns
121 121
120 122
TXx/CKx
RXx/DTx
pin
pin
Note: Refer to Figure 26-3 for load conditions.
125
126
TXx/CKx
RXx/DTx
pin
pin
Note: Refer to Figure 26-3 for load conditions.
2010 Microchip Technology Inc. DS39770C-page 391
PIC18F85J90 FAMILY
TABLE 26-24: A/D CONVERTER CHARACTERISTICS: PIC18F85J90 FAMILY (INDUSTRIAL)
Param
No. Symbol Characteristic Min Typ Max Units Conditions
A01 NRResolution — — 10 bits
A03 EIL Integral Linearity Error — — <±1 LSb VREF 3.0V
A04 EDL Differential Linearity Error — — <±1 LSb VREF 3.0V
A06 EOFF Offset Error — — <±3 LSb VREF 3.0V
A07 EGN Gain Error — — <±3 LSb VREF 3.0V
A10 — Monotonicity Guaranteed(1) —VSS VAIN VREF
A20 VREF Reference Voltage Range
(VREFH – VREFL)
2.0
3
—
—
—
—
V
V
VDD 3.0V
VDD 3.0V
A21 VREFH Reference Voltage High VSS + VREF —VDD V
A22 VREFL Reference Voltage Low VSS – 0.3V — VDD – 3.0V V
A25 VAIN Analog Input Voltage VREFL —VREFH V
A30 ZAIN Recommended Impedance of
Analog Voltage Source
——2.5k
A50 IREF VREF Input Current(2) —
—
—
—
5
150
A
A
During VAIN acquisition.
During A/D conversion
cycle.
Note 1: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.
2: VREFH current is from RA3/AN3/VREF+ pin or VDD, whichever is selected as the VREFH source.
VREFL current is from RA2/AN2/VREF- pin or VSS, whichever is selected as the VREFL source.
PIC18F85J90 FAMILY
DS39770C-page 392 2010 Microchip Technology Inc.
FIGURE 26-19: A/D CONVERSION TIMING
TABLE 26-25: A/D CONVERSION REQUIREMENTS
Param
No. Symbol Characteristic Min Max Units Conditions
130 TAD A/D Clock Period 0.7 25.0(1) sTOSC based, VREF 3.0V
—1s A/D RC mode
131 TCNV Conversion Time
(not including acquisition time)(2)
11 12 TAD
132 TACQ Acquisition Time(3) 1.4 — s-40C to +85C
135 TSWC Switching Time from Convert Sample — (Note 4)
137 TDIS Discharge Time 0.2 — s
Note 1: The time of the A/D clock period is dependent on the device frequency and the TAD clock divider.
2: ADRES registers may be read on the following TCY cycle.
3: The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale
after the conversion (VDD to VSS or VSS to VDD). The source impedance (RS) on the input channels is 50.
4: On the following cycle of the device clock.
131
130
132
BSF ADCON0, GO
Q4
A/D CLK
A/D DATA
ADRES
ADIF
GO
SAMPLE
OLD_DATA
SAMPLING STOPPED
DONE
NEW_DATA
(Note 2)
987 21 0
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction
to be executed.
2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.
. . . . . .
TCY (Note 1)
2010 Microchip Technology Inc. DS39770C-page 393
PIC18F85J90 FAMILY
27.0 PACKAGING INFORMATION
27.1 Package Marking Information
3
e
3
e
64-Lead TQFP
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
Example
18F65J90
-I/PT
1010017
80-Lead TQFP
XXXXXXXXXXXX
XXXXXXXXXXXX
YYWWNNN
Example
PIC18F85J90
-I/PT
1010017
Legend: XX...X Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
*This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e
PIC18F85J90 FAMILY
DS39770C-page 394 2010 Microchip Technology Inc.
27.2 Package Details
The following sections give the technical details of the
packages.
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2010 Microchip Technology Inc. DS39770C-page 395
PIC18F85J90 FAMILY
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DS39770C-page 396 2010 Microchip Technology Inc.
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2010 Microchip Technology Inc. DS39770C-page 397
PIC18F85J90 FAMILY
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PIC18F85J90 FAMILY
DS39770C-page 398 2010 Microchip Technology Inc.
NOTES:
2010 Microchip Technology Inc. DS39770C-page 399
PIC18F85J90 FAMILY
APPENDIX A: REVISION HISTORY
Revision A (July 2006)
Original data sheet for PIC18F85J90 family devices.
Revision B (March 2007)
Updated power-down and supply current electrical
characteristics and package details illustrations.
Revision C (January 2010)
Updated electrical characteristics and package detail
illustrations. Minor text edits throughout document.
PIC18F85J90 FAMILY
DS39770C-page 400 2010 Microchip Technology Inc.
APPENDIX B: MIGRATION
BETWEEN HIGH-END
DEVICE FAMILIES
Devices in the PIC18F85J90 and PIC18F8490 families
are very similar in their functions and feature sets.
However, there are some potentially important differ-
ences which should be considered when migrating an
application across device families to achieve a new
design goal. These are summarized in Table B-1. The
areas of difference, which could be a major impact on
migration, are discussed in greater detail later in this
section.
TABLE B-1: NOTABLE DIFFERENCES BETWEEN PIC18F8490 AND PIC18F85J90 FAMILIES
Characteristic PIC18F85J90 Family PIC18F8490 Family
Operating Frequency 40 MHz @ 2.35V 40 MHz @ 4.2V
Supply Voltage 2.0V-3.6V, Dual Voltage Requirement 2.0V-5.5V
Operating Current Low Lower
Program Memory Size (maximum) 32 Kbytes 16 Kbytes
Program Memory Endurance 1,000 Write/Erase Cycles (typical) 100,000 Write/Erase Cycles (typical)
Program Memory Retention 20 Years (minimum) 40 Years (minimum)
Programming Time (Normalized) 43.8 s/byte (2.8 ms/64-byte block) 15.6 s/byte (1 ms/64-byte block)
I/O Sink/Source at 25 mA PORTB and PORTC Only All Ports
Input Voltage Tolerance on I/O Pins 5.5V on Digital Only Pins VDD on All I/O Pins
I/O 67 66
LCD Outputs (maximum pixels,
segments x commons)
192 192
LCD Bias Generation 4 Modes 1 Mode
LCD Voltage Regulator Implemented; Includes Voltage Boost Not Available
Pull-ups PORTB, PORTD, PORTE
and PORTJ
PORTB
Open-Drain Output Option Available on USARTs, SPI and CCP
Output Pins
Not Available
Oscillator Options Limited Primary Options (EC, HS,
PLL); Flexible Internal Oscillator
(INTOSC and INTRC)
More Primary Options (EC, HS, XT,
LP, RC, PLL); Flexible Internal
Oscillator (INTOSC and INTRC)
Programming Entry Low Voltage, Key Sequence VPP and LVP
Code Protection Single Block, All or Nothing Multiple Code Protection Blocks
Configuration Words Stored in Last 4 Words of
Program Memory space
Stored in Configuration Space,
Starting at 300000h
Start-up Time from Sleep
200 s (typical)
10 s (typical)
10 s (typical) with
Voltage Regulator Disabled
Power-up Timer Always on Configurable
Data EEPROM Use Self-Programming Not Available
BOR Simple BOR with Voltage Regulator Separate Programmable BOR
LVD Integrated with Voltage Regulator Separate Programmable Module
A/D Channels 12 12
A/D Calibration Self-Calibration Feature Software Look-up Table
In-Circuit Emulation Not available Available
2010 Microchip Technology Inc. DS39770C-page 401
PIC18F85J90 FAMILY
B.1 Power Requirement Differences
The most significant difference between the
PIC18F85J90 and PIC18F8490 device families is the
power requirements. PIC18F85J90 family devices are
designed on a smaller process. This results in lower
maximum voltage and higher leakage current.
The operating voltage range for PIC18F85J90 devices
is 2.0V to 3.6V. In addition, these devices have split
power requirements: one for the core logic and one for
the I/O. One of the VDD pins is separated for the core
logic supply (VDDCORE). This pin has specific voltage
and capacitor requirements as described in
Section 26.0 “Electrical Characteristics”.
B.2 Oscillator Differences
PIC18F8490 and PIC18F85J90 family devices share a
similar range of oscillator options. The major difference
is that PIC18F85J90 family devices support a smaller
number of primary (external) oscillator options, namely
HS and EC Oscillator modes.
While both device families have an internal PLL that
can be used with the primary oscillators, the PLL for the
PIC18F85J90 family is not enabled as a device
configuration option. Instead, it must be enabled in
software.
The clocking differences should be considered when
making a conversion between the PIC18F8490 and
PIC18F85J90 device families.
B.3 LCD Module
When converting an LCD application between the
PIC18F85J90 and the PIC18F8490 families, the
following things must be considered:
•Available Segments: The module for
PIC18F65J90 devices supports 33 segments, as
opposed to 32 segments in PIC18F6490 devices.
(The 80-pin devices of both families support
48 segments. All devices support 4 commons.)
•Bias Generation: The PIC18F85J90 version of
the module also incorporates its own independent
voltage regulator, which supports 4 circuit configu-
rations for bias generation, voltage boost to
support displays that operate above device VDD
and software contrast control.
•Additional LCD Function Pins: The
PIC18F85J90 family of devices adds 3 additional
LCD function pins in comparison to the
PIC18F8490 family. The additional pins are
associated with LCD bias generation:
- LCDBIAS0 (RG0)
-V
LCAP1 (RG2)
-V
LCPA2 (RG3)
•Segment Assignments: Eight of the LCD
segment functions have been relocated to differ-
ent I/O pins than in PIC18F8490 devices. These
segments are listed in Table B-2.
•Other Considerations: In all LCD applications,
the connections of PIC18F85J90 devices to
external components for LCD bias generation are
different than PIC18F8490 devices. The addition
of the LCDBIAS0 output requires that this pin be
included in bias component configurations. A
more complete discussion is provided in
Section 16.3 “LCD Bias Generation”.
The simultaneous use of the external Timer1
oscillator and Segment 32 is not allowed in
PIC18F85J90 devices, since these functions are
shared on the same pin.
TABLE B-2: ASSIGNMENTS OF MOVED
LCD SEGMENTS
LCD Segment PIC18F8490 PIC18F85J90
SEG16 RA2 RC4
SEG17 RA3 RC3
SEG18 RF0 RA1
SEG27 RG3 RC6
SEG28 RG2 RC7
SEG29 RG0 RB5
SEG30 RG0 RB0
SEG32 RJ0 RC1
Note: Refer to the pinout diagrams for pin
locations of I/O ports.
PIC18F85J90 FAMILY
DS39770C-page 402 2010 Microchip Technology Inc.
B.4 Pin Differences
Besides the LCD pinout differences already described,
there are other differences in the pinouts between the
PIC18F85J90 and the PIC18F8490 families:
• Input voltage tolerance
• Output current capabilities
• Available I/O
Pins on the PIC18F85J90 that have digital only input
capability will tolerate voltages up to 5.5V, and are thus,
tolerant to voltages above VDD. Table 10-1 in
Section 10.1 “I/O Port Pin Capabilities” contains the
complete list.
In addition to input differences, there are output differ-
ences as well. PIC18F85J90 devices have three
classes of pin output current capability: high, medium
and low. Not all I/O pins can source or sink equal levels
of current. Only PORTB and PORTC support the
25 mA source/sink capability that is supported by all
output pins on the PIC18F8490. Table 10-1 in
Section 10.1 “I/O Port Pin Capabilities” contains the
complete list of output capabilities.
Finally, the pins associated with the CCP,
EUSART/AUSART and SPI peripherals can be config-
ured by the user as open-drain outputs. This allows for
simpler interfacing with external devices operating at
higher voltages. This capability is not directly
equivalent to any feature on the PIC18F8490 family.
There are also differences in the implementation of
some ports on PIC18F85J90 devices. While the total
number of general purpose I/O pins are very similar
(67 vs. 66), the implementation of individual pins has
notable differences:
•The MCLR
pin is dedicated only to MCLR and
cannot be configured as an input (RG5) as it can
on PIC18F8490 devices.
• RF0 does not exist on PIC18F85J90 devices.
• RE0, RE1 and RE3 are implemented on
PIC18F85J90 devices, but not PIC18F8490
devices.
All of these pin differences (including power pin
differences) should be accounted for when making a
conversion between PIC18F8490 and PIC18F85J90
devices.
B.5 Other Peripherals
Peripherals must also be considered when making a
conversion between the PIC18F85J90 and the
PIC18F8490 families:
•A/D Converter: The converter for PIC18F85J90
devices require a calibration step prior to normal
operation.
•Data EEPROM: PIC18F85J90 devices do not
have this module but offer self-programming
capability.
•BOR: PIC18F85J90 devices do not have a
programmable BOR. Simple brown-out capability
is provided through the use of the internal voltage
regulator.
•LVD: PIC18F85J90 devices do not have this
module. A limited, fixed setpoint capability is
provided through the use of the internal voltage
regulator.
2010 Microchip Technology Inc. DS39770C-page 403
PIC18F85J90 FAMILY
INDEX
A
A/D ................................................................................... 271
A/D Converter Interrupt, Configuring ....................... 275
Acquisition Requirements ........................................ 276
ADCAL Bit ................................................................ 279
ADCON0 Register .................................................... 271
ADCON1 Register .................................................... 271
ADCON2 Register .................................................... 271
ADRESH Register ............................................ 271, 274
ADRESL Register .................................................... 271
Analog Port Pins, Configuring .................................. 277
Associated Registers ............................................... 279
Automatic Acquisition Time ...................................... 277
Calibration ................................................................ 279
Configuring the Module ............................................ 275
Conversion Clock (TAD) ........................................... 277
Conversion Requirements ....................................... 392
Conversion Status (GO/DONE Bit) .......................... 274
Conversions ............................................................. 278
Converter Characteristics ........................................ 391
Operation in Power-Managed Modes ...................... 279
Special Event Trigger (CCP) .................................... 278
Use of the CCP2 Trigger .......................................... 278
Absolute Maximum Ratings ............................................. 359
AC (Timing) Characteristics ............................................. 374
Load Conditions for Device Timing
Specifications ................................................... 375
Parameter Symbology ............................................. 374
Temperature and Voltage Specifications ................. 375
Timing Conditions .................................................... 375
ACKSTAT ........................................................................ 225
ACKSTAT Status Flag ..................................................... 225
ADCAL Bit ........................................................................ 279
ADCON0 Register ............................................................ 271
GO/DONE Bit ........................................................... 274
ADCON1 Register ............................................................ 271
ADCON2 Register ............................................................ 271
ADDFSR .......................................................................... 348
ADDLW ............................................................................ 311
Addressable Universal Synchronous Asynchronous
Receiver Transmitter (AUSART). See AUSART.
ADDULNK ........................................................................ 348
ADDWF ............................................................................ 311
ADDWFC ......................................................................... 312
ADRESH Register ............................................................ 271
ADRESL Register .................................................... 271, 274
Analog-to-Digital Converter. See A/D.
ANDLW ............................................................................ 312
ANDWF ............................................................................ 313
Assembler
MPASM Assembler .................................................. 356
AUSART
Asynchronous Mode ................................................ 262
Associated Registers, Receive ........................ 265
Associated Registers, Transmit ....................... 263
Receiver ........................................................... 264
Setting up 9-Bit Mode with Address Detect ..... 264
Transmitter ....................................................... 262
Baud Rate Generator (BRG) ................................... 260
Associated Registers ....................................... 260
Baud Rate Error, Calculating ........................... 260
Baud Rates, Asynchronous Modes ................. 261
High Baud Rate Select (BRGH Bit) ................. 260
Operation in Power-Managed Modes .............. 260
Sampling ......................................................... 260
Synchronous Master Mode ...................................... 266
Associated Registers, Receive ........................ 268
Associated Registers, Transmit ....................... 267
Reception ........................................................ 268
Transmission ................................................... 266
Synchronous Slave Mode ........................................ 269
Associated Registers, Receive ........................ 270
Associated Registers, Transmit ....................... 269
Reception ........................................................ 270
Transmission ................................................... 269
Auto-Wake-up on Sync Break Character ......................... 249
B
Baud Rate Generator ...................................................... 221
BC .................................................................................... 313
BCF ................................................................................. 314
BF .................................................................................... 225
BF Status Flag ................................................................. 225
Bias Generation (LCD)
Charge Pump Design Considerations ..................... 173
Block Diagrams
A/D ........................................................................... 274
Analog Input Model .................................................. 275
AUSART Receive .................................................... 264
AUSART Transmit ................................................... 262
Baud Rate Generator .............................................. 221
Capture Mode Operation ......................................... 156
Comparator Analog Input Model .............................. 285
Comparator I/O Operating Modes ........................... 282
Comparator Output .................................................. 284
Comparator Voltage Reference ............................... 288
Comparator Voltage Reference Output
Buffer Example ................................................ 289
Compare Mode Operation ....................................... 157
Connections for On-Chip Voltage Regulator ........... 299
Device Clock .............................................................. 35
EUSART Receive .................................................... 247
EUSART Transmit ................................................... 245
External Power-on Reset Circuit
(Slow VDD Power-up) ........................................ 53
Fail-Safe Clock Monitor ........................................... 301
Generic I/O Port Operation ...................................... 115
Interrupt Logic .......................................................... 100
LCD Clock Generation ............................................. 168
LCD Driver Module .................................................. 163
LCD Regulator Connections (M0 and M1) .............. 170
MSSP (I2C Master Mode) ........................................ 219
MSSP (I2C Mode) .................................................... 200
MSSP (SPI Mode) ................................................... 191
On-Chip Reset Circuit ................................................ 51
PIC18F6XJ90 ............................................................ 12
PIC18F8XJ90 ............................................................ 13
PLL ............................................................................ 40
PWM Operation (Simplified) .................................... 159
PIC18F85J90 FAMILY
DS39770C-page 404 2010 Microchip Technology Inc.
Reads from Flash Program Memory .......................... 91
Resistor Ladder Configurations for M2 .................... 171
Resistor Ladder Configurations for M3 .................... 172
Single Comparator ...................................................283
SPI Master/Slave Connection .................................. 195
Table Read Operation ................................................ 87
Table Write Operation ................................................ 88
Table Writes to Flash Program Memory .................... 93
Timer0 in 16-Bit Mode .............................................. 138
Timer0 in 8-Bit Mode ................................................ 138
Timer1 (16-Bit Read/Write Mode) ............................ 142
Timer1 (8-Bit Mode) .................................................142
Timer2 ...................................................................... 148
Timer3 (16-Bit Read/Write Mode) ............................ 150
Timer3 (8-Bit Mode) .................................................150
Watchdog Timer ....................................................... 297
BN ....................................................................................314
BNC .................................................................................. 315
BNN .................................................................................. 315
BNOV ............................................................................... 316
BNZ .................................................................................. 316
BOR. See Brown-out Reset.
BOV .................................................................................. 319
BRA .................................................................................. 317
Break Character (12-Bit) Transmit and Receive .............. 250
BRG. See Baud Rate Generator.
BRGH Bit
TXSTA1 Register ..................................................... 239
TXSTA2 Register ..................................................... 260
Brown-out Reset (BOR) ..................................................... 53
and On-Chip Voltage Regulator ............................... 300
Detecting .................................................................... 53
BSF .................................................................................. 317
BTFSC .............................................................................318
BTFSS .............................................................................. 318
BTG .................................................................................. 319
BZ ..................................................................................... 320
C
C Compilers
MPLAB C18 ............................................................. 356
Calibration (A/D Converter) .............................................. 279
CALL ................................................................................320
CALLW .............................................................................349
Capture (CCP Module) ..................................................... 156
Associated Registers ............................................... 158
CCP Pin Configuration ............................................. 156
CCPR2H:CCPR2L Registers ................................... 156
Software Interrupt .................................................... 156
Timer1/Timer3 Mode Selection ................................ 156
Capture/Compare/PWM (CCP) ........................................ 153
Capture Mode. See Capture.
CCP Mode and Timer Resources ............................154
CCPRxH Register .................................................... 154
CCPRxL Register ..................................................... 154
Compare Mode. See Compare.
Configuration ............................................................ 154
Interaction of CCP1 and CCP2 for
Timer Resources .............................................. 155
Interconnect Configurations ..................................... 154
Clock Sources ....................................................................37
Default System Clock on Reset .................................38
Selection Using OSCCON Register ........................... 38
CLRF ................................................................................321
CLRWDT ..........................................................................321
Code Examples
16 x 16 Signed Multiply Routine ................................ 98
16 x 16 Unsigned Multiply Routine ............................ 98
8 x 8 Signed Multiply Routine .................................... 97
8 x 8 Unsigned Multiply Routine ................................ 97
Changing Between Capture Prescalers ................... 156
Computed GOTO Using an Offset Value ................... 67
Erasing a Flash Program Memory Block ................... 92
Fast Register Stack ................................................... 67
How to Clear RAM (Bank 1) Using
Indirect Addressing ............................................ 80
Implementing a Real-Time Clock Using
a Timer1 Interrupt Service ............................... 145
Initializing PORTA .................................................... 116
Initializing PORTB .................................................... 118
Initializing PORTC ................................................... 121
Initializing PORTD ................................................... 124
Initializing PORTE .................................................... 126
Initializing PORTF .................................................... 128
Initializing PORTG ................................................... 131
Initializing PORTH ................................................... 133
Initializing PORTJ .................................................... 135
Loading the SSPBUF (SSPSR) Register ................. 194
Reading a Flash Program Memory Word .................. 91
Saving STATUS, WREG and BSR
Registers in RAM ............................................. 114
Writing to Flash Program Memory ............................. 94
Code Protection ............................................................... 291
COMF .............................................................................. 322
Comparator ...................................................................... 281
Analog Input Connection Considerations ................ 285
Associated Registers ............................................... 285
Configuration ........................................................... 282
Effects of a Reset .................................................... 284
Interrupts ................................................................. 284
Operation ................................................................. 283
Operation During Sleep ........................................... 284
Outputs .................................................................... 283
Reference ................................................................ 283
External Signal ................................................ 283
Internal Signal .................................................. 283
Response Time ........................................................ 283
Comparator Specifications ............................................... 372
Comparator Voltage Reference ....................................... 287
Accuracy and Error .................................................. 288
Associated Registers ............................................... 289
Configuring .............................................................. 287
Connection Considerations ...................................... 288
Effects of a Reset .................................................... 288
Operation During Sleep ........................................... 288
Compare (CCP Module) .................................................. 157
Associated Registers ............................................... 158
CCP Pin Configuration ............................................. 157
CCPR2 Register ...................................................... 157
Software Interrupt .................................................... 157
Special Event Trigger .............................. 151, 157, 278
Timer1/Timer3 Mode Selection ................................ 157
Computed GOTO ............................................................... 67
Configuration Bits ............................................................ 291
Configuration Mismatch (CM) ............................................ 53
Configuration Register Protection .................................... 303
2010 Microchip Technology Inc. DS39770C-page 405
PIC18F85J90 FAMILY
Core Features
Easy Migration ............................................................. 9
Extended Instruction Set .............................................. 9
Memory Options ........................................................... 9
nanoWatt Technology .................................................. 9
Oscillator Options and Features .................................. 9
CPFSEQ .......................................................................... 322
CPFSGT .......................................................................... 323
CPFSLT ........................................................................... 323
Crystal Oscillator/Ceramic Resonator ................................ 39
Customer Change Notification Service ............................ 413
Customer Notification Service .......................................... 413
Customer Support ............................................................ 413
D
Data Addressing Modes ..................................................... 80
Comparing Addressing Modes with
the Extended Instruction Set Enabled ............... 84
Direct .......................................................................... 80
Indexed Literal Offset ................................................. 83
BSR ................................................................... 85
Instructions Affected .......................................... 83
Mapping Access Bank ....................................... 85
Indirect ....................................................................... 80
Inherent and Literal .................................................... 80
Data Memory ..................................................................... 70
Access Bank .............................................................. 73
Bank Select Register (BSR) ....................................... 70
Extended Instruction Set ............................................ 83
General Purpose Registers ........................................ 73
Memory Maps
PIC18FX3J90/X4J90 Devices ........................... 71
PIC18FX5J90 Devices ....................................... 72
Special Function Registers ................................ 74
Special Function Registers ........................................ 74
DAW ................................................................................. 324
DC Characteristics ........................................................... 370
Power-Down and Supply Current ............................ 362
Supply Voltage ......................................................... 361
DCFSNZ .......................................................................... 325
DECF ............................................................................... 324
DECFSZ ........................................................................... 325
Default System Clock ......................................................... 38
Details on Individual Family Members ............................... 10
Development Support ...................................................... 355
Device Overview .................................................................. 9
Features (64-Pin Devices) ......................................... 11
Features (80-Pin Devices) ......................................... 11
Direct Addressing ............................................................... 81
E
Effect on Standard PIC18 Instructions ............................. 352
Effects of Power-Managed Modes on
Various Clock Sources ............................................... 42
Electrical Characteristics .................................................. 359
Enhanced Universal Synchronous Asynchronous Receiver
Transmitter (EUSART). See EUSART.
ENVREG Pin .................................................................... 299
Equations
16 x 16 Signed Multiplication Algorithm ..................... 98
16 x 16 Unsigned Multiplication Algorithm ................. 98
A/D Acquisition Time ............................................... 276
A/D Minimum Charging Time .................................. 276
Calculating the Minimum Required
Acquisition Time .............................................. 276
LCD Static and Dynamic Current ............................ 173
Errata ................................................................................... 7
EUSART
Asynchronous Mode ................................................ 245
12-Bit Break Transmit and Receive ................. 250
Associated Registers, Receive ........................ 248
Associated Registers, Transmit ....................... 246
Auto-Wake-up on Sync Break ......................... 249
Receiver .......................................................... 247
Setting up 9-Bit Mode with Address Detect ..... 247
Transmitter ...................................................... 245
Baud Rate Generator (BRG) ................................... 239
Associated Registers ....................................... 240
Auto-Baud Rate Detect .................................... 243
Baud Rate Error, Calculating ........................... 240
Baud Rates, Asynchronous Modes ................. 241
High Baud Rate Select (BRGH Bit) ................. 239
Operation in Power-Managed Modes .............. 239
Sampling ......................................................... 239
Synchronous Master Mode ...................................... 251
Associated Registers, Receive ........................ 253
Associated Registers, Transmit ....................... 252
Reception ........................................................ 253
Transmission ................................................... 251
Synchronous Slave Mode ........................................ 254
Associated Registers, Receive ........................ 255
Associated Registers, Transmit ....................... 254
Reception ........................................................ 255
Transmission ................................................... 254
Extended Instruction Set
ADDFSR .................................................................. 348
ADDULNK ............................................................... 348
CALLW .................................................................... 349
MOVSF .................................................................... 349
MOVSS .................................................................... 350
PUSHL ..................................................................... 350
SUBFSR .................................................................. 351
SUBULNK ................................................................ 351
External Oscillator Modes .................................................. 39
EC Modes .................................................................. 40
HS Modes .................................................................. 39
F
Fail-Safe Clock Monitor ........................................... 291, 301
Exiting Fail-Safe Operation ...................................... 302
Interrupts in Power-Managed Modes ...................... 302
POR or Wake-up From Sleep .................................. 302
WDT During Oscillator Failure ................................. 301
Fast Register Stack ........................................................... 67
Firmware Instructions ...................................................... 305
PIC18F85J90 FAMILY
DS39770C-page 406 2010 Microchip Technology Inc.
Flash Program Memory ...................................................... 87
Associated Registers .................................................95
Control Registers ....................................................... 88
EECON1 and EECON2 ..................................... 88
TABLAT (Table Latch) Register .........................90
TBLPTR (Table Pointer) Register ...................... 90
Erase Sequence ........................................................ 92
Erasing ....................................................................... 92
Operation During Code-Protect ................................. 95
Reading ......................................................................91
Table Pointer
Boundaries Based on Operation ........................ 90
Table Pointer Boundaries .......................................... 90
Table Reads and Table Writes .................................. 87
Write Sequence ......................................................... 93
Writing ........................................................................ 93
Unexpected Termination ....................................95
Write Verify ........................................................ 95
FSCM. See Fail-Safe Clock Monitor.
G
GOTO ............................................................................... 326
H
Hardware Multiplier ............................................................ 97
Introduction ................................................................ 97
Operation ...................................................................97
Performance Comparison .......................................... 97
I
I/O Ports ........................................................................... 115
Input Voltage Considerations ................................... 115
Open-Drain Outputs .................................................116
Output Pin Drive ....................................................... 115
Pin Capabilities ........................................................ 115
Pull-up Configuration ...............................................116
I2C Mode (MSSP) ............................................................ 200
Acknowledge Sequence Timing ............................... 228
Associated Registers ............................................... 234
Baud Rate Generator ............................................... 221
Bus Collision
During a Repeated Start Condition .................. 232
During a Stop Condition ................................... 233
Clock Arbitration .......................................................222
Clock Stretching ....................................................... 214
10-Bit Slave Receive Mode (SEN = 1) ............. 214
10-Bit Slave Transmit Mode .............................214
7-Bit Slave Receive Mode (SEN = 1) ............... 214
7-Bit Slave Transmit Mode ...............................214
Clock Synchronization and the CKP Bit ................... 215
Effects of a Reset ..................................................... 229
General Call Address Support ................................. 218
I2C Clock Rate w/BRG ............................................. 221
Master Mode ............................................................ 219
Baud Rate Generator ....................................... 221
Operation ......................................................... 220
Reception ......................................................... 225
Repeated Start Condition Timing ..................... 224
Start Condition Timing ..................................... 223
Transmission .................................................... 225
Multi-Master Communication, Bus Collision
and Arbitration .................................................. 229
Multi-Master Mode ................................................... 229
Operation ................................................................. 205
Read/Write Bit Information (R/W Bit) ............... 205, 207
Registers .................................................................. 200
Serial Clock (SCK/SCL) ........................................... 207
Slave Mode .............................................................. 205
Addressing ....................................................... 205
Addressing Masking ........................................ 206
Reception ........................................................ 207
Transmission ................................................... 207
Sleep Operation ....................................................... 229
Stop Condition Timing ............................................. 228
INCF ................................................................................ 326
INCFSZ ............................................................................ 327
In-Circuit Debugger .......................................................... 303
In-Circuit Serial Programming (ICSP) ...................... 291, 303
Indexed Literal Offset Addressing
and Standard PIC18 Instructions ............................. 352
Indexed Literal Offset Mode ............................................. 352
Indirect Addressing ............................................................ 81
INFSNZ ............................................................................ 327
Initialization Conditions for all Registers ...................... 57–59
Instruction Cycle ................................................................ 68
Clocking Scheme ....................................................... 68
Flow/Pipelining ........................................................... 68
Instruction Set .................................................................. 305
ADDLW .................................................................... 311
ADDWF .................................................................... 311
ADDWF (Indexed Literal Offset Mode) .................... 353
ADDWFC ................................................................. 312
ANDLW .................................................................... 312
ANDWF .................................................................... 313
BC ............................................................................ 313
BCF ......................................................................... 314
BN ............................................................................ 314
BNC ......................................................................... 315
BNN ......................................................................... 315
BNOV ...................................................................... 316
BNZ ......................................................................... 316
BOV ......................................................................... 319
BRA ......................................................................... 317
BSF .......................................................................... 317
BSF (Indexed Literal Offset Mode) .......................... 353
BTFSC ..................................................................... 318
BTFSS ..................................................................... 318
BTG ......................................................................... 319
BZ ............................................................................ 320
CALL ........................................................................ 320
CLRF ....................................................................... 321
CLRWDT ................................................................. 321
COMF ...................................................................... 322
CPFSEQ .................................................................. 322
CPFSGT .................................................................. 323
CPFSLT ................................................................... 323
DAW ........................................................................ 324
DCFSNZ .................................................................. 325
DECF ....................................................................... 324
DECFSZ .................................................................. 325
Extended Instructions .............................................. 347
Considerations when Enabling ........................ 352
Syntax .............................................................. 347
Use with MPLAB IDE Tools ............................. 354
General Format ........................................................ 307
GOTO ...................................................................... 326
INCF ........................................................................ 326
INCFSZ .................................................................... 327
INFSNZ .................................................................... 327
IORLW ..................................................................... 328
IORWF ..................................................................... 328
2010 Microchip Technology Inc. DS39770C-page 407
PIC18F85J90 FAMILY
LFSR ........................................................................ 329
MOVF ....................................................................... 329
MOVFF .................................................................... 330
MOVLB .................................................................... 330
MOVLW ................................................................... 331
MOVWF ................................................................... 331
MULLW .................................................................... 332
MULWF .................................................................... 332
NEGF ....................................................................... 333
NOP ......................................................................... 333
Opcode Field Descriptions ....................................... 306
POP ......................................................................... 334
PUSH ....................................................................... 334
RCALL ..................................................................... 335
RESET ..................................................................... 335
RETFIE .................................................................... 336
RETLW .................................................................... 336
RETURN .................................................................. 337
RLCF ........................................................................ 337
RLNCF ..................................................................... 338
RRCF ....................................................................... 338
RRNCF .................................................................... 339
SETF ........................................................................ 339
SETF (Indexed Literal Offset Mode) ........................ 353
SLEEP ..................................................................... 340
Standard Instructions ............................................... 305
SUBFWB .................................................................. 340
SUBLW .................................................................... 341
SUBWF .................................................................... 341
SUBWFB .................................................................. 342
SWAPF .................................................................... 342
TBLRD ..................................................................... 343
TBLWT ..................................................................... 344
TSTFSZ ................................................................... 345
XORLW .................................................................... 345
XORWF .................................................................... 346
INTCON Register
RBIF Bit .................................................................... 118
INTCON Registers ........................................................... 101
Inter-Integrated Circuit. See I2C Mode.
Internal Oscillator Block ..................................................... 41
Adjustment ................................................................. 41
INTOSC Frequency Drift ............................................ 41
INTOSC Output Frequency ........................................ 41
OSC1, OSC2 Pin Configuration ................................. 41
Internal RC Oscillator
Use with WDT .......................................................... 297
Internal Voltage Regulator Specifications ........................ 373
Internet Address ............................................................... 413
Interrupt Sources ............................................................. 291
A/D Conversion Complete ....................................... 275
Capture Complete (CCP) ......................................... 156
Compare Complete (CCP) ....................................... 157
Interrupt-on-Change (RB7:RB4) .............................. 118
TMR0 Overflow ........................................................ 139
TMR1 Overflow ........................................................ 141
TMR2 to PR2 Match (PWM) .................................... 159
TMR3 Overflow ................................................ 149, 151
Interrupts ............................................................................ 99
During, Context Saving ............................................ 114
INTx Pin ................................................................... 114
PORTB, Interrupt-on-Change .................................. 114
TMR0 ....................................................................... 114
Interrupts, Flag Bits
Interrupt-on-Change (RB7:RB4) Flag (RBIF Bit) ..... 118
INTOSC, INTRC. See Internal Oscillator Block.
IORLW ............................................................................. 328
IORWF ............................................................................. 328
IPR Registers ................................................................... 110
L
LCD
Associated Registers ............................................... 189
Bias Generation ....................................................... 169
Bias Configurations ......................................... 170
M0 and M1 .............................................. 170
M2 ........................................................... 171
M3 ........................................................... 172
Bias Types ....................................................... 169
LCD Voltage Regulator .................................... 169
Charge Pump .................................................. 170, 173
Clock Source Selection ........................................... 168
Configuring the Module ........................................... 188
Frame Frequency .................................................... 174
Interrupts ................................................................. 186
LCDCON Register ................................................... 164
LCDDATA Registers ................................................ 164
LCDPS Register ...................................................... 164
LCDREG Register ................................................... 164
LCDSE Registers .................................................... 164
Multiplex Types ........................................................ 173
Operation During Sleep ........................................... 187
Pixel Control ............................................................ 173
Segment Enables .................................................... 173
Waveform Generation ............................................. 174
LCD Driver ......................................................................... 10
LCDCON Register ........................................................... 164
LCDDATA Registers ........................................................ 164
LCDPS Register .............................................................. 164
LCDREG Register ........................................................... 164
LCDSE Registers ............................................................. 164
LFSR ............................................................................... 329
Liquid Crystal Display (LCD) Driver ................................. 163
Low-Voltage Detection ..................................................... 299
M
Master Clear (MCLR) ......................................................... 53
Master Synchronous Serial Port (MSSP). See MSSP.
Memory Organization ........................................................ 63
Data Memory ............................................................. 70
Program Memory ....................................................... 63
Memory Programming Requirements .............................. 372
Microchip Internet Web Site ............................................. 413
MOVF .............................................................................. 329
MOVFF ............................................................................ 330
MOVLB ............................................................................ 330
MOVLW ........................................................................... 331
MOVSF ............................................................................ 349
MOVSS ............................................................................ 350
MOVWF ........................................................................... 331
MPLAB ASM30 Assembler, Linker, Librarian .................. 356
MPLAB Integrated Development
Environment Software ............................................. 355
MPLAB PM3 Device Programmer ................................... 358
MPLAB REAL ICE In-Circuit Emulator System ............... 357
MPLINK Object Linker/MPLIB Object Librarian ............... 356
PIC18F85J90 FAMILY
DS39770C-page 408 2010 Microchip Technology Inc.
MSSP
ACK Pulse ........................................................ 205, 207
Control Registers (general) ...................................... 191
Module Overview ..................................................... 191
SSPBUF Register .................................................... 196
SSPSR Register ...................................................... 196
MULLW ............................................................................ 332
MULWF ............................................................................ 332
N
NEGF ............................................................................... 333
NOP ................................................................................. 333
Notable Differences Between PIC18F8490
and PIC18F85J90 Families ...................................... 400
LCD Module ............................................................. 401
Oscillator Options ..................................................... 401
Other Peripherals ..................................................... 402
Pin Differences ......................................................... 402
Power Requirements ............................................... 401
O
Oscillator Configuration ...................................................... 35
EC ..............................................................................35
ECPLL ........................................................................ 35
HS ..............................................................................35
HSPLL ........................................................................ 35
Internal Oscillator Block ............................................. 41
INTOSC .....................................................................35
INTRC ........................................................................35
Oscillator Selection .......................................................... 291
Oscillator Start-up Timer (OST) ......................................... 42
Oscillator Switching ............................................................37
Oscillator Transitions ..........................................................38
Oscillator, Timer1 ..................................................... 141, 151
Oscillator, Timer3 ............................................................. 149
P
Packaging ........................................................................393
Details ......................................................................394
Marking ....................................................................393
PIE Registers ...................................................................107
Pin Functions
AVDD .......................................................................... 29
AVDD .......................................................................... 20
AVSS .......................................................................... 29
AVSS .......................................................................... 20
ENVREG .............................................................. 20, 29
LCDBIAS3 ............................................................ 18, 25
MCLR ................................................................... 14, 21
OSC1/CLKI/RA7 .................................................. 14, 21
OSC2/CLKO/RA6 ................................................ 14, 21
RA0/AN0 .............................................................. 14, 21
RA1/AN1/SEG18 ................................................. 14, 21
RA2/AN2/VREF- .................................................... 14, 21
RA3/AN3/VREF+ ................................................... 14, 21
RA4/T0CKI/SEG14 .............................................. 14, 21
RA5/AN4/SEG15 ................................................. 14, 21
RB0/INT0/SEG30 ................................................. 15, 22
RB1/INT1/SEG8 ................................................... 15, 22
RB2/INT2/SEG9 ................................................... 15, 22
RB3/INT3/SEG10 ................................................. 15, 22
RB4/KBI0/SEG11 ................................................. 15, 22
RB5/KBI1/SEG29 ................................................. 15, 22
RB6/KBI2/PGC .................................................... 15, 22
RB7/KBI3/PGD .................................................... 15, 22
RC0/T1OSO/T13CKI ...........................................16, 23
RC1/T1OSI/CCP2/SEG32 ................................... 16, 23
RC2/CCP1/SEG13 .............................................. 16, 23
RC3/SCK/SCL/SEG17 ......................................... 16, 23
RC4/SDI/SDA/SEG16 .......................................... 16, 23
RC5/SDO/SEG12 ................................................ 16, 23
RC6/TX1/CK1/SEG27 ......................................... 16, 23
RC7/RX1/DT1/SEG28 ......................................... 16, 23
RD0/SEG0 ........................................................... 17, 24
RD0/SEG1 ........................................................... 17, 24
RD2/SEG2 ........................................................... 17, 24
RD3/SEG3 ........................................................... 17, 24
RD4/SEG4 ........................................................... 17, 24
RD5/SEG5 ........................................................... 17, 24
RD6/SEG6 ........................................................... 17, 24
RD7/SEG7 ........................................................... 17, 24
RE0/LCDBIAS1 ................................................... 18, 25
RE1/LCDBIAS2 ................................................... 18, 25
RE3/COM0 .......................................................... 18, 25
RE4/COM1 .......................................................... 18, 25
RE5/COM2 .......................................................... 18, 25
RE6/COM3 .......................................................... 18, 25
RE7/CCP2/SEG31 ............................................... 18, 25
RF1/AN6/C2OUT/SEG19 .................................... 19, 26
RF2/AN7/C1OUT/SEG20 .................................... 19, 26
RF3/AN8/SEG21 ................................................. 19, 26
RF4/AN9/SEG22 ................................................. 19, 26
RF5/AN10/CVREF/SEG23 .................................... 19, 26
RF6/AN11/SEG24 ............................................... 19, 26
RF7/AN5/SS/SEG25 ............................................ 19, 26
RG0/LCDBIAS0 ................................................... 20, 27
RG1/TX2/CK2 ...................................................... 20, 27
RG2/RX2/DT2/VLCAP1 ......................................... 27, 20
RG3/VLCAP2 ........................................................ 20, 27
RG4/SEG26 ......................................................... 20, 27
RH0/SEG47 ............................................................... 28
RH1/SEG46 ............................................................... 28
RH2/SEG45 ............................................................... 28
RH3/SEG44 ............................................................... 28
RH4/SEG40 ............................................................... 28
RH5/SEG41 ............................................................... 28
RH6/SEG42 ............................................................... 28
RH7/SEG43 ............................................................... 28
RJ0 ............................................................................ 29
RJ1/SEG33 ................................................................ 29
RJ2/SEG34 ................................................................ 29
RJ3/SEG35 ................................................................ 29
RJ4/SEG39 ................................................................ 29
RJ5/SEG38 ................................................................ 29
RJ6/SEG37 ................................................................ 29
RJ7/SEG36 ................................................................ 29
VDD ............................................................................ 29
VDD ............................................................................ 20
VDDCORE/VCAP ..................................................... 29, 20
VSS ............................................................................ 20
VSS ............................................................................ 29
Pinout I/O Descriptions
PIC18F6XJ90 ............................................................ 14
PIC18F8XJ90 ............................................................ 21
PIR Registers ................................................................... 104
PLL .................................................................................... 40
ECPLL Oscillator Mode ............................................. 40
HSPLL Oscillator Mode ............................................. 40
POP ................................................................................. 334
POR. See Power-on Reset.
2010 Microchip Technology Inc. DS39770C-page 409
PIC18F85J90 FAMILY
PORTA
Associated Registers ............................................... 117
LATA Register .......................................................... 116
PORTA Register ...................................................... 116
TRISA Register ........................................................ 116
PORTB
Associated Registers ............................................... 120
LATB Register .......................................................... 118
PORTB Register ...................................................... 118
RB7:RB4 Interrupt-on-Change Flag
(RBIF Bit) ......................................................... 118
TRISB Register ........................................................ 118
PORTC
Associated Registers ............................................... 123
LATC Register ......................................................... 121
PORTC Register ...................................................... 121
RC3/SCK/SCL Pin ................................................... 207
TRISC Register ........................................................ 121
PORTD
Associated Registers ............................................... 125
LATD Register ......................................................... 124
PORTD Register ...................................................... 124
TRISD Register ........................................................ 124
PORTE
Associated Registers ............................................... 127
LATE Register .......................................................... 126
PORTE Register ...................................................... 126
TRISE Register ........................................................ 126
PORTF
Associated Registers ............................................... 130
LATF Register .......................................................... 128
PORTF Register ...................................................... 128
TRISF Register ........................................................ 128
PORTG
Associated Registers ............................................... 132
LATG Register ......................................................... 131
PORTG Register ...................................................... 131
TRISG Register ........................................................ 131
PORTH
Associated Registers ............................................... 134
LATH Register ......................................................... 133
PORTH Register ...................................................... 133
TRISH Register ........................................................ 133
PORTJ
Associated Registers ............................................... 136
LATJ Register .......................................................... 135
PORTJ Register ....................................................... 135
TRISJ Register ......................................................... 135
Power-Managed Modes ..................................................... 43
and SPI Operation ................................................... 199
Clock Sources ............................................................ 43
Clock Transitions and Status Indicators ..................... 44
Entering ...................................................................... 43
Exiting Idle and Sleep Modes .................................... 49
By Interrupt ........................................................ 49
By Reset ............................................................ 49
By WDT Time-out .............................................. 49
Without an Oscillator Start-up Delay .................. 49
Idle Modes ................................................................. 47
PRI_IDLE ........................................................... 48
RC_IDLE ............................................................ 49
SEC_IDLE ......................................................... 48
Multiple Sleep Commands ......................................... 44
Run Modes ................................................................ 44
PRI_RUN ........................................................... 44
RC_RUN ............................................................ 46
SEC_RUN ......................................................... 44
Selecting .................................................................... 43
Sleep Mode ............................................................... 47
Summary (table) ........................................................ 43
Power-on Reset (POR) ...................................................... 53
Power-up Delays ............................................................... 42
Power-up Timer (PWRT) ............................................. 42, 54
Time-out Sequence ................................................... 54
Prescaler, Capture ........................................................... 156
Prescaler, Timer0 ............................................................ 139
Prescaler, Timer2 ............................................................ 160
PRI_IDLE Mode ................................................................. 48
PRI_RUN Mode ................................................................. 44
Program Counter ............................................................... 65
PCL, PCH and PCU Registers .................................. 65
PCLATH and PCLATU Registers .............................. 65
Program Memory
Extended Instruction Set ........................................... 82
Flash Configuration Words ........................................ 64
Hard Memory Vectors ................................................ 64
Instructions ................................................................ 69
Two-Word .......................................................... 69
Interrupt Vector .......................................................... 64
Look-up Tables .......................................................... 67
Memory Maps ............................................................ 63
Hard Vectors and Configuration Words ............. 64
Reset Vector .............................................................. 64
Program Verification and Code Protection ...................... 303
Programming, Device Instructions ................................... 305
Pulse-Width Modulation. See PWM (CCP Module).
PUSH ............................................................................... 334
PUSH and POP Instructions .............................................. 66
PUSHL ............................................................................. 350
PWM (CCP Module)
Associated Registers ............................................... 161
Duty Cycle ............................................................... 160
Example Frequencies/Resolutions .......................... 160
Period ...................................................................... 159
Setup for PWM Operation ....................................... 161
TMR2 to PR2 Match ................................................ 159
Q
Q Clock ............................................................................ 160
R
RAM. See Data Memory.
RC_IDLE Mode .................................................................. 49
RC_RUN Mode .................................................................. 46
RCALL ............................................................................. 335
RCON Register
Bit Status During Initialization .................................... 56
Reader Response ............................................................ 414
Register File ....................................................................... 73
Register File Summary ................................................ 75–78
Registers
ADCON0 (A/D Control 0) ......................................... 271
ADCON1 (A/D Control 1) ......................................... 272
ADCON2 (A/D Control 2) ......................................... 273
BAUDCON1 (Baud Rate Control 1) ......................... 238
CCPxCON (CCPx Control, CCP1/CCP2) ................ 153
CMCON (Comparator Control) ................................ 281
CONFIG1H (Configuration 1 High) .......................... 293
CONFIG1L (Configuration 1 Low) ........................... 293
PIC18F85J90 FAMILY
DS39770C-page 410 2010 Microchip Technology Inc.
CONFIG2H (Configuration 2 High) .......................... 295
CONFIG2L (Configuration 2 Low) ............................ 294
CONFIG3H (Configuration 3 High) .......................... 295
CVRCON (Comparator Voltage
Reference Control) ........................................... 287
DEVID1 (Device ID Register 1) ................................296
DEVID2 (Device ID Register 2) ................................296
EECON1 (EEPROM Control 1) .................................. 89
INTCON (Interrupt Control) ......................................101
INTCON2 (Interrupt Control 2) ................................. 102
INTCON3 (Interrupt Control 3) ................................. 103
IPR1 (Peripheral Interrupt Priority 1) ........................ 110
IPR2 (Peripheral Interrupt Priority 2) ........................ 111
IPR3 (Peripheral Interrupt Priority 3) ........................ 112
LCDCON (LCD Control) ........................................... 164
LCDDATAx (LCD Data) ...........................................167
LCDPS (LCD Phase) ...............................................165
LCDREG (LCD Voltage Regulator Control) ............. 169
LCDSEx (LCD Segment Enable) ............................. 166
OSCCON (Oscillator Control) ....................................36
OSCTUNE (Oscillator Tuning) ................................... 37
PIE1 (Peripheral Interrupt Enable 1) ........................ 107
PIE2 (Peripheral Interrupt Enable 2) ........................ 108
PIE3 (Peripheral Interrupt Enable 3) ........................ 109
PIR1 (Peripheral Interrupt Request (Flag) 1) ........... 104
PIR2 (Peripheral Interrupt Request (Flag) 2) ........... 105
PIR3 (Peripheral Interrupt Request (Flag) 3) ........... 106
RCON (Reset Control) ....................................... 52, 113
RCSTA1 (EUSART Receive Status and Control) .... 237
RCSTA2 (AUSART Receive Status and Control) .... 259
SSPCON1 (MSSP Control 1, I2C Mode) ................. 202
SSPCON1 (MSSP Control 1, SPI Mode) ................. 193
SSPCON2 (MSSP Control 2, I2C Master Mode) ..... 203
SSPCON2 (MSSP Control 2, I2C Slave Mode) ....... 204
SSPSTAT (MSSP Status, I2C Mode) ....................... 201
SSPSTAT (MSSP Status, SPI Mode) ...................... 192
STATUS .....................................................................79
STKPTR (Stack Pointer) ............................................66
T0CON (Timer0 Control) .......................................... 137
T1CON (Timer1 Control) .......................................... 141
T2CON (Timer2 Control) .......................................... 147
T3CON (Timer3 Control) .......................................... 149
TXSTA1 (EUSART Transmit
Status and Control) .......................................... 236
TXSTA2 (AUSART Transmit
Status and Control) .......................................... 258
WDTCON (Watchdog Timer Control) ....................... 298
RESET ............................................................................. 335
Reset .................................................................................. 51
Brown-out Reset (BOR) ............................................. 51
MCLR Reset, During Power-Managed Modes ........... 51
MCLR Reset, Normal Operation ................................ 51
Power-on Reset (POR) ..............................................51
RESET Instruction .....................................................51
Stack Full Reset .........................................................51
Stack Underflow Reset .............................................. 51
Watchdog Timer (WDT) Reset ................................... 51
Resets .............................................................................. 291
Brown-out Reset (BOR) ........................................... 291
Oscillator Start-up Timer (OST) ............................... 291
Power-on Reset (POR) ............................................ 291
Power-up Timer (PWRT) .........................................291
RETFIE ............................................................................336
RETLW ............................................................................ 336
RETURN .......................................................................... 337
Return Address Stack ........................................................ 65
Return Stack Pointer (STKPTR) ........................................ 66
Revision History ............................................................... 399
RLCF ............................................................................... 337
RLNCF ............................................................................. 338
RRCF ............................................................................... 338
RRNCF ............................................................................ 339
S
SCK ................................................................................. 191
SDI ................................................................................... 191
SDO ................................................................................. 191
SEC_IDLE Mode ............................................................... 48
SEC_RUN Mode ................................................................ 44
Serial Clock, SCK ............................................................ 191
Serial Data In (SDI) .......................................................... 191
Serial Data Out (SDO) ..................................................... 191
Serial Peripheral Interface. See SPI Mode.
SETF ................................................................................ 339
Slave Select (SS) ............................................................. 191
SLEEP ............................................................................. 340
Sleep
OSC1 and OSC2 Pin States ...................................... 42
Software Simulator (MPLAB SIM) ................................... 357
Special Event Trigger. See Compare (CCP Module).
Special Features of the CPU ........................................... 291
SPI Mode (MSSP)
Associated Registers ............................................... 199
Bus Mode Compatibility ........................................... 199
Effects of a Reset .................................................... 199
Enabling SPI I/O ...................................................... 195
Master Mode ............................................................ 196
Operation ................................................................. 194
Operation in Power-Managed Modes ...................... 199
Serial Clock .............................................................. 191
Serial Data In ........................................................... 191
Serial Data Out ........................................................ 191
Slave Mode .............................................................. 197
Slave Select ............................................................. 191
Slave Select Synchronization .................................. 197
SPI Clock ................................................................. 196
Typical Connection .................................................. 195
SS .................................................................................... 191
SSPOV ............................................................................ 225
SSPOV Status Flag ......................................................... 225
SSPSTAT Register
R/W Bit ............................................................ 205, 207
Stack Full/Underflow Resets .............................................. 67
SUBFSR .......................................................................... 351
SUBFWB ......................................................................... 340
SUBLW ............................................................................ 341
SUBULNK ........................................................................ 351
SUBWF ............................................................................ 341
SUBWFB ......................................................................... 342
SWAPF ............................................................................ 342
T
Table Pointer Operations (table) ........................................ 90
Table Reads/Table Writes ................................................. 67
TBLRD ............................................................................. 343
TBLWT ............................................................................. 344
2010 Microchip Technology Inc. DS39770C-page 411
PIC18F85J90 FAMILY
Timer0 .............................................................................. 137
Associated Registers ............................................... 139
Clock Source Select (T0CS Bit) ............................... 138
Operation ................................................................. 138
Overflow Interrupt .................................................... 139
Prescaler .................................................................. 139
Switching Assignment ...................................... 139
Prescaler Assignment (PSA Bit) .............................. 139
Prescaler Select (T0PS2:T0PS0 Bits) ..................... 139
Prescaler. See Prescaler, Timer0.
Reads and Writes in 16-Bit Mode ............................ 138
Source Edge Select (T0SE Bit) ................................ 138
Timer1 .............................................................................. 141
16-Bit Read/Write Mode ........................................... 143
Associated Registers ............................................... 145
Interrupt .................................................................... 144
Operation ................................................................. 142
Oscillator .......................................................... 141, 143
Layout Considerations ..................................... 144
Oscillator, as Secondary Clock .................................. 37
Overflow Interrupt .................................................... 141
Resetting, Using the CCP Special
Event Trigger ................................................... 144
TMR1H Register ...................................................... 141
TMR1L Register ....................................................... 141
Use as a Clock Source ............................................ 143
Use as a Real-Time Clock ....................................... 144
Timer2 .............................................................................. 147
Associated Registers ............................................... 148
Interrupt .................................................................... 148
Operation ................................................................. 147
Output ...................................................................... 148
PR2 Register ............................................................ 159
TMR2 to PR2 Match Interrupt .................................. 159
Timer3 .............................................................................. 149
16-Bit Read/Write Mode ........................................... 151
Associated Registers ............................................... 151
Operation ................................................................. 150
Oscillator .......................................................... 149, 151
Overflow Interrupt ............................................ 149, 151
Special Event Trigger (CCP) .................................... 151
TMR3H Register ...................................................... 149
TMR3L Register ....................................................... 149
Timing Diagrams
A/D Conversion ........................................................ 392
Acknowledge Sequence .......................................... 228
Asynchronous Reception ................................. 248, 265
Asynchronous Transmission ............................ 246, 263
Asynchronous Transmission
(Back to Back) ......................................... 246, 263
Automatic Baud Rate Calculation ............................ 244
Auto-Wake-up Bit (WUE) During
Normal Operation ............................................ 249
Auto-Wake-up Bit (WUE) During Sleep ................... 249
Baud Rate Generator with Clock Arbitration ............ 222
BRG Overflow Sequence ......................................... 244
BRG Reset Due to SDA Arbitration During Start
Condition .......................................................... 231
Bus Collision During a Repeated Start
Condition (Case 1) ........................................... 232
Bus Collision During a Repeated Start
Condition (Case 2) ........................................... 232
Bus Collision During a Start Condition
(SCL = 0) ......................................................... 231
Bus Collision During a Stop Condition (Case 1) ...... 233
Bus Collision During a Stop Condition (Case 2) ...... 233
Bus Collision During Start Condition (SDA Only) .... 230
Bus Collision for Transmit and Acknowledge .......... 229
Capture/Compare/PWM (CCP1,CCP2) ................... 381
CLKO and I/O .......................................................... 378
Clock Synchronization ............................................. 215
Clock/Instruction Cycle .............................................. 68
EUSART/AUSART Synchronous Receive
(Master/Slave) ................................................. 390
EUSART/AUSART Synchronous Transmission
(Master/Slave) ................................................. 390
Example SPI Master Mode (CKE = 0) ..................... 382
Example SPI Master Mode (CKE = 1) ..................... 383
Example SPI Slave Mode (CKE = 0) ....................... 384
Example SPI Slave Mode (CKE = 1) ....................... 385
External Clock (All Modes Except PLL) ................... 376
Fail-Safe Clock Monitor ........................................... 302
First Start Bit Timing ................................................ 223
I2C Bus Data ............................................................ 386
I2C Bus Start/Stop Bits ............................................ 386
I2C Master Mode (7 or 10-Bit Transmission) ........... 226
I2C Master Mode (7-Bit Reception) ......................... 227
I2C Slave Mode (10-Bit Reception, SEN = 0,
ADMSK = 01001) ............................................ 212
I2C Slave Mode (10-Bit Reception, SEN = 0) .......... 211
I2C Slave Mode (10-Bit Reception, SEN = 1) .......... 217
I2C Slave Mode (10-Bit Transmission) .................... 213
I2C Slave Mode (7-Bit Reception, SEN = 0,
ADMSK = 01011) ............................................ 209
I2C Slave Mode (7-Bit Reception, SEN = 0) ............ 208
I2C Slave Mode (7-Bit Reception, SEN = 1) ............ 216
I2C Slave Mode (7-Bit Transmission) ...................... 210
I2C Slave Mode General Call Address
Sequence (7 or 10-Bit Address Mode) ............ 218
I2C Stop Condition Receive or Transmit Mode ........ 228
LCD Interrupt in Quarter Duty Cycle Drive .............. 186
LCD Sleep Entry/Exit When SLPEN = 1 or
CS1:CS0 = 00 ................................................. 187
MSSP I2C Bus Data ................................................ 388
MSSP I2C Bus Start/Stop Bits ................................. 388
PWM Output ............................................................ 159
Repeated Start Condition ........................................ 224
Reset, Watchdog Timer (WDT), Oscillator Start-up
Timer (OST) and Power-up Timer (PWRT) ..... 379
Send Break Character Sequence ............................ 250
Slave Synchronization ............................................. 197
Slow Rise Time (MCLR Tied to VDD,
VDD Rise > TPWRT) ............................................ 55
SPI Mode (Master Mode) ........................................ 196
SPI Mode (Slave Mode, CKE = 0) ........................... 198
SPI Mode (Slave Mode, CKE = 1) ........................... 198
Synchronous Reception
(Master Mode, SREN) ............................. 253, 268
Synchronous Transmission ............................. 251, 266
Synchronous Transmission
(Through TXEN) ...................................... 252, 267
Time-out Sequence on Power-up
(MCLR Not Tied to VDD), Case 1 ...................... 54
Time-out Sequence on Power-up
(MCLR Not Tied to VDD), Case 2 ...................... 55
Time-out Sequence on Power-up
(MCLR Tied to VDD, VDD Rise TPWRT) .............. 54
Timer0 and Timer1 External Clock .......................... 380
Transition for Entry to Idle Mode ............................... 48
PIC18F85J90 FAMILY
DS39770C-page 412 2010 Microchip Technology Inc.
Transition for Entry to SEC_RUN Mode .................... 45
Transition for Entry to Sleep Mode ............................ 47
Transition for Two-Speed Start-up
(INTRC to HSPLL) ........................................... 300
Transition for Wake From Idle to Run Mode .............. 48
Transition for Wake From Sleep (HSPLL) ................. 47
Transition From RC_RUN Mode to
PRI_RUN Mode ................................................. 46
Transition From SEC_RUN Mode to
PRI_RUN Mode (HSPLL) .................................. 45
Transition to RC_RUN Mode ..................................... 46
Type-A in 1/2 MUX, 1/2 Bias Drive .......................... 176
Type-A in 1/2 MUX, 1/3 Bias Drive .......................... 178
Type-A in 1/3 MUX, 1/2 Bias Drive .......................... 180
Type-A in 1/3 MUX, 1/3 Bias Drive .......................... 182
Type-A in 1/4 MUX, 1/3 Bias Drive .......................... 184
Type-A/Type-B in Static Drive ..................................175
Type-B in 1/2 MUX, 1/2 Bias Drive .......................... 177
Type-B in 1/2 MUX, 1/3 Bias Drive .......................... 179
Type-B in 1/3 MUX, 1/2 Bias Drive .......................... 181
Type-B in 1/3 MUX, 1/3 Bias Drive .......................... 183
Type-B in 1/4 MUX, 1/3 Bias Drive .......................... 185
Timing Diagrams and Specifications
Capture/Compare/PWM Requirements
(CCP1, CCP2) .................................................381
CLKO and I/O Requirements ................................... 378
EUSART/AUSART Synchronous Receive
Requirements ................................................... 390
EUSART/AUSART Synchronous Transmission
Requirements ................................................... 390
Example SPI Mode Requirements
(Master Mode, CKE = 0) ................................. 382
Example SPI Mode Requirements
(Master Mode, CKE = 1) ................................. 383
Example SPI Mode Requirements
(Slave Mode, CKE = 0) .................................... 384
Example SPI Slave Mode
Requirements (CKE = 1) .................................. 385
External Clock Requirements .................................. 376
I2C Bus Data Requirements (Slave Mode) .............. 387
I2C Bus Start/Stop Bits Requirements
(Slave Mode) .................................................... 386
Internal RC Accuracy ...............................................377
MSSP I2C Bus Data Requirements ......................... 389
MSSP I2C Bus Start/Stop Bits Requirements .......... 388
PLL Clock ................................................................ 377
Reset, Watchdog Timer, Oscillator Start-up
Timer, Power-up Timer and Brown-out
Reset Requirements ........................................ 379
Timer0 and Timer1 External Clock
Requirements .................................................. 380
Top-of-Stack Access .......................................................... 65
TSTFSZ ........................................................................... 345
Two-Speed Start-up ................................................. 291, 300
Two-Word Instructions
Example Cases .......................................................... 69
V
VDDCORE/VCAP Pin .......................................................... 299
Voltage Reference Specifications .................................... 373
Voltage Regulator (On-Chip) ........................................... 299
Brown-out Reset (BOR) ........................................... 300
Low-Voltage Detection (LVD) .................................. 299
Operation in Sleep Mode ......................................... 300
Power-up Requirements .......................................... 300
W
Watchdog Timer (WDT) ........................................... 291, 297
Associated Registers ............................................... 298
Control Register ....................................................... 297
During Oscillator Failure .......................................... 301
Programming Considerations .................................. 297
WCOL ...................................................... 223, 224, 225, 228
WCOL Status Flag ................................... 223, 224, 225, 228
WWW Address ................................................................ 413
WWW, On-Line Support ...................................................... 7
X
XORLW ............................................................................ 345
XORWF ........................................................................... 346
2010 Microchip Technology Inc. DS39770C-page 413
PIC18F85J90 FAMILY
THE MICROCHIP WEB SITE
Microchip provides online support via our WWW site at
www.microchip.com. This web site is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the web site contains the following informa-
tion:
•Product Support – Data sheets and errata, appli-
cation notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software
•General Technical Support – Frequently Asked
Questions (FAQ), technical support requests,
online discussion groups, Microchip consultant
program member listing
•Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of Micro-
chip sales offices, distributors and factory repre-
sentatives
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a spec-
ified product family or development tool of interest.
To register, access the Microchip web site at
www.microchip.com, click on Customer Change
Notification and follow the registration instructions.
CUSTOMER SUPPORT
Users of Microchip products can receive assistance
through several channels:
• Distributor or Representative
• Local Sales Office
• Field Application Engineer (FAE)
• Technical Support
Customers should contact their distributor, representa-
tive or field application engineer (FAE) for support.
Local sales offices are also available to help custom-
ers. A listing of sales offices and locations is included in
the back of this document.
Technical support is available through the web site
at: http://support.microchip.com
PIC18F85J90 FAMILY
DS39770C-page 414 2010 Microchip Technology Inc.
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-
uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this document.
To: Technical Publications Manager
RE: Reader Response
Total Pages Sent ________
From: Name
Company
Address
City / State / ZIP / Country
Telephone: (_______) _________ - _________
Application (optional):
Would you like a reply? Y N
Device: Literature Number:
Questions:
FAX: (______) _________ - _________
DS39770CPIC18F85J90 Family
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
2010 Microchip Technology Inc. DS39770C-page 415
PIC18F85J90 FAMILY
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. X/XX XXX
PatternPackageTemperature
Range
Device
Device PIC18F63J90/64J90/65J90(1),
PIC18F83J90/84J90/85J90(1),
PIC18F63J90/64J90/65J90T(2),
PIC18F83J90/84J90/85J90T(2)
Temperature Range I = -40C to +85C (Industrial)
Package PT = TQFP (Thin Quad Flatpack)
Pattern QTP, SQTP, Code or Special Requirements
(blank otherwise)
Examples:
a) PIC18F85J90-I/PT 301 = Industrial temp.,
TQFP package, QTP pattern #301.
b) PIC18F63J90T-I/PT = Tape and reel, Industrial
temp., TQFP package.
Note 1: F = Standard Voltage Range
2: T = in tape and reel
DS39770C-page 416 2010 Microchip Technology Inc.
AMERICAS
Corporate Office
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ASIA/PACIFIC
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Tel: 91-80-3090-4444
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82-2-558-5934
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EUROPE
Austria - Wels
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Fax: 44-118-921-5820
WORLDWIDE SALES AND SERVICE
01/05/10
