RF Agile Transceiver AD9364 Data Sheet FUNCTIONAL BLOCK DIAGRAM AD9364 RXB_P, RXB_N RXA_P, RXA_N ADC RXC_P, RXC_N Rx LO TX_MON Tx LO TXA_P, TXA_N DAC P0_[D11:D0]/ TX_[D5:D0] P1_[D11:D0]/ RX_[D5:D0] DAC CTRL AUXADC AUXDACx GPO RADIO SWITCHING PLLs CLK_OUT XTALN NOTES 1. SPI, CTRL, P0_[D11:D0]/TX_[D5:D0], P1_[D11:D0]/RX_[D5:D0], AND RADIO SWITCHING CONTAIN MULTIPLE PINS. 11846-001 SPI CTRL DAC TXB_P, TXB_N ADC RF 1 x 1 transceiver with integrated 12-bit DACs and ADCs Band: 70 MHz to 6.0 GHz Supports time division duplex (TDD) and frequency division duplex (FDD) operation Tunable channel bandwidth (BW): <200 kHz to 56 MHz 3-band receiver: 3 differential or 6 single-ended inputs Superior receiver sensitivity with a noise figure of <2.5 dB Rx gain control Real-time monitor and control signals for manual gain Independent automatic gain control 2-band differential output transmitter Highly linear broadband transmitter Tx EVM: -40 dB Tx noise: -157 dBm/Hz noise floor Tx monitor: 66 dB dynamic range with 1 dB accuracy Integrated fractional-N synthesizers 2.4 Hz maximum local oscillator (LO) step size Multichip synchronization CMOS/LVDS digital interface DATA INTERFACE FEATURES Figure 1. APPLICATIONS Point to point communication systems Femtocell/picocell/microcell base stations General-purpose radio systems GENERAL DESCRIPTION The AD9364 is a high performance, highly integrated radio frequency (RF) Agile TransceiverTM designed for use in 3G and 4G base station applications. Its programmability and wideband capability make it ideal for a broad range of transceiver applications. The device combines an RF front end with a flexible mixed-signal baseband section and integrated frequency synthesizers, simplifying design-in by providing a configurable digital interface to a processor. The AD9364 operates in the 70 MHz to 6.0 GHz range, covering most licensed and unlicensed bands. Channel bandwidths from less than 200 kHz to 56 MHz are supported. The direct conversion receiver has state-of-the-art noise figure and linearity. The receive (Rx) subsystem includes independent automatic gain control (AGC), dc offset correction, quadrature correction, and digital filtering, thereby eliminating the need for these functions in the digital baseband. The AD9364 also has flexible manual gain modes that can be externally controlled. Two high dynamic range ADCs digitize the received I and Q signals and pass them through configurable decimation filters Rev. C and 128-tap FIR filters to produce a 12-bit output signal at the appropriate sample rate. The transmitter uses a direct conversion architecture that achieves high modulation accuracy with ultralow noise. This transmitter design produces a Tx EVM of -40 dB, allowing significant system margin for the external power amplifier (PA) selection. The onboard transmit (Tx) power monitor can be used as a power detector, enabling highly accurate Tx power measurements. The fully integrated phase-locked loops (PLLs) provide low power fractional-N frequency synthesis for all Rx and Tx channels. All VCO and loop filter components are integrated. The core of the AD9364 can be powered directly from a 1.3 V regulator. The IC is controlled via a standard 4-wire serial port and four real-time input control pins. Comprehensive power-down modes are included to minimize power consumption during normal use. The AD9364 is packaged in a 10 mm x 10 mm, 144-ball chip scale package ball grid array (CSP_BGA). Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. 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Technical Support www.analog.com AD9364 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 5.5 GHz Frequency Band .......................................................... 24 Applications ....................................................................................... 1 Theory of Operation ...................................................................... 28 Functional Block Diagram .............................................................. 1 General......................................................................................... 28 General Description ......................................................................... 1 Receiver........................................................................................ 28 Revision History ............................................................................... 2 Transmitter .................................................................................. 28 Specifications..................................................................................... 3 Clock Input Options .................................................................. 28 Current Consumption--VDD_Interface .................................. 7 Synthesizers ................................................................................. 29 Current Consumption--VDDD1P3_DIG and VDDAx (Combination of All 1.3 V Supplies) ......................................... 8 Digital Data Interface................................................................. 29 Enable State Machine ..................................................................... 29 Absolute Maximum Ratings ..................................................... 10 SPI Interface ................................................................................ 30 Reflow Profile .............................................................................. 10 Control Pins ................................................................................ 30 Thermal Resistance .................................................................... 10 GPO Pins (GPO_3 to GPO_0) ................................................. 30 ESD Caution ................................................................................ 10 Auxiliary Converters.................................................................. 30 Pin Configuration and Function Descriptions ........................... 11 Powering the AD9364................................................................ 30 Typical Performance Characteristics ........................................... 15 Packaging and Ordering Information ......................................... 31 800 MHz Frequency Band......................................................... 15 Outline Dimensions ................................................................... 31 2.4 GHz Frequency Band .......................................................... 20 Ordering Guide .......................................................................... 31 REVISION HISTORY 7/14--Rev. B to Rev. C Changed CMOS VDD_INTERFACE from 1.2 V (min)/2.5 V (max) to 1.14 V (min)/2.625 V (max); and Changed LVDS VDD_INTERFACE from 1.8 V (min)/2.5 V (max) to 1.71 V (min)/2.625 V (max); Table 1......................................... 7 Added Powering the AD9364 Section ......................................... 30 2/14--Revision B: Initial Version Rev. C | Page 2 of 32 Data Sheet AD9364 SPECIFICATIONS Electrical characteristics at VDD_GPO = 3.3 V, VDD_INTERFACE = 1.8 V, and all other VDDx pins = 1.3 V, TA = 25C, unless otherwise noted. Table 1. Parameter1 RECEIVER, GENERAL Center Frequency Gain Minimum Maximum Gain Step Received Signal Strength Indicator Range Accuracy RECEIVER, 800 MHz Noise Figure Third-Order Input Intermodulation Intercept Point Second-Order Input Intermodulation Intercept Point Local Oscillator (LO) Leakage Quadrature Gain Error Phase Error Modulation Accuracy (EVM) Input S11 RECEIVER, 2.4 GHz Noise Figure Third-Order Input Intermodulation Intercept Point Second-Order Input Intermodulation Intercept Point Local Oscillator (LO) Leakage Quadrature Gain Error Phase Error Modulation Accuracy (EVM) Input S11 RECEIVER, 5.5 GHz Noise Figure Third-Order Input Intermodulation Intercept Point Second-Order Input Intermodulation Intercept Point Local Oscillator (LO) Leakage Quadrature Gain Error Phase Error Modulation Accuracy (EVM) Input S11 TRANSMITTER--GENERAL Center Frequency Power Control Range Power Control Resolution Symbol Min Typ 70 Max Unit 6000 MHz Test Conditions/Comments 0 74.5 73.0 72.0 65.5 1 dB dB dB dB dB dB 100 2 dB dB NF IIP3 2 -18 dB dBm Maximum Rx gain Maximum Rx gain IIP2 40 dBm Maximum Rx gain -122 dBm At Rx front-end input 0.2 0.2 -42 -10 % Degrees dB dB NF IIP3 3 -14 dB dBm Maximum Rx gain Maximum Rx gain IIP2 45 dBm Maximum Rx gain -110 dBm At Rx front-end input 0.2 0.2 -42 -10 % Degrees dB dB NF IIP3 3.8 -17 dB dBm Maximum Rx gain Maximum Rx gain IIP2 42 dBm Maximum Rx gain -95 dBm At Rx front-end input 0.2 0.2 -37 % Degrees dB -10 dB At 800 MHz At 2300 MHz, RXA At 2300 MHz, RXB, RXC At 5500 MHz, RXA RSSI 70 6000 90 0.25 Rev. C | Page 3 of 32 MHz dB dB 19.2 MHz reference clock 40 MHz reference clock 40 MHz reference clock (doubled internally for RF synthesizer) AD9364 Parameter1 TRANSMITTER, 800 MHz Output S22 Maximum Output Power Modulation Accuracy (EVM) Third-Order Output Intermodulation Intercept Point Carrier Leakage Data Sheet Unit Test Conditions/Comments -10 8 -40 23 dB dBm dB dBm 1 MHz tone into 50 load 19.2 MHz reference clock -50 -32 -157 dBc dBc dBm/Hz 0 dB attenuation 40 dB attenuation 90 MHz offset -10 7.5 -40 19 dB dBm dB dBm 1 MHz tone into 50 load 40 MHz reference clock -50 -32 -156 dBc dBc dBm/Hz 0 dB attenuation 40 dB attenuation 90 MHz offset -10 6.5 -36 dB dBm dB 17 dBm -50 -30 -151.5 dBc dBc dBm/Hz 4 66 1 dBm dB dB 2.4 Hz 2.4 GHz, 40 MHz reference clock 0.13 rms 2.4 GHz 0.37 rms 5.5 GHz 0.59 rms 100 Hz to 100 MHz, 30.72 MHz reference clock (doubled internally for RF synthesizer) 100 Hz to 100 MHz, 40 MHz reference clock 100 Hz to 100 MHz, 40 MHz reference clock (doubled internally for RF synthesizer) REF_CLK is either the input to the XTALP/XTALN pins or a line directly to the XTALN pin 1.3 MHz MHz V p-p Crystal input External oscillator AC-coupled external oscillator 12 Bits 0.05 VDDA1P3_BB - 0.05 V V 10 Bits Noise Floor TRANSMITTER, 2.4 GHz Output S22 Maximum Output Power Modulation Accuracy (EVM) Third-Order Output Intermodulation Intercept Point Carrier Leakage Symbol Min OIP3 OIP3 Noise Floor TRANSMITTER, 5.5 GHz Output S22 Maximum Output Power Modulation Accuracy (EVM) Third-Order Output Intermodulation Intercept Point Carrier Leakage OIP3 Noise Floor TX MONITOR INPUT (TX_MON) Maximum Input Level Dynamic Range Accuracy LO SYNTHESIZER LO Frequency Step Integrated Phase Noise 800 MHz Typ Max REFERENCE CLOCK (REF_CLK) Input Frequency Range Signal Level AUXILIARY CONVERTERS ADC Resolution Input Voltage Minimum Maximum DAC Resolution 19 10 50 80 Rev. C | Page 4 of 32 7 MHz tone into 50 load 40 MHz reference clock (doubled internally for RF synthesizer) 0 dB attenuation 40 dB attenuation 90 MHz offset Data Sheet Parameter1 Output Voltage Minimum Maximum Output Current DIGITAL SPECIFICATIONS (CMOS) Logic Inputs Input Voltage High Low Input Current High Low Logic Outputs Output Voltage High Low DIGITAL SPECIFICATIONS (LVDS) Logic Inputs Input Voltage Range AD9364 Symbol Bus Turnaround Time, Read Typ Max 0.5 VDD_GPO - 0.3 10 Unit Test Conditions/Comments V V mA VDD_INTERFACE x 0.8 0 VDD_INTERFACE VDD_INTERFACE x 0.2 V V -10 -10 +10 +10 A A VDD_INTERFACE x 0.2 V V 825 1575 mV -100 +100 mV VDD_INTERFACE x 0.8 Input Differential Voltage Threshold Receiver Differential Input Impedance Logic Outputs Output Voltage High Low Output Differential Voltage Output Offset Voltage GENERAL-PURPOSE OUTPUTS Output Voltage High Low Output Current SPI TIMING SPI_CLK Period Pulse Width SPI_ENB Setup to First SPI_CLK Rising Edge Last SPI_CLK Falling Edge to SPI_ENB Hold SPI_DI Data Input Setup to SPI_CLK Data Input Hold to SPI_CLK SPI_CLK Rising Edge to Output Data Delay 4-Wire Mode 3-Wire Mode Bus Turnaround Time, Read Min 100 Each differential input in the pair 1375 1025 150 1200 mV mV mV Programmable in 75 mV steps mV VDD_GPO x 0.8 VDD_GPO x 0.2 10 V V mA VDD_INTERFACE = 1.8 V tCP tMP tSC 20 9 1 ns ns ns tHC 0 ns tS 2 ns tH 1 ns tCO tCO tHZM 3 3 tH 8 8 tCO (max) ns ns ns tHZS 0 tCO (max) ns Rev. C | Page 5 of 32 After baseband processor (BBP) drives the last address bit After the AD9364 drives the last data bit AD9364 Parameter1 DIGITAL DATA TIMING (CMOS), VDD_INTERFACE = 1.8 V DATA_CLK Clock Period DATA_CLK and FB_CLK Pulse Width Tx Data Setup to FB_CLK Hold to FB_CLK DATA_CLK to Data Bus Output Delay DATA_CLK to RX_FRAME Delay Pulse Width ENABLE TXNRX TXNRX Setup to ENABLE Bus Turnaround Time Before Rx After Rx Capacitive Load Capacitive Input DIGITAL DATA TIMING (CMOS), VDD_INTERFACE = 2.5 V DATA_CLK Clock Period DATA_CLK and FB_CLK Pulse Width Tx Data Setup to FB_CLK Hold to FB_CLK DATA_CLK to Data Bus Output Delay DATA_CLK to RX_FRAME Delay Pulse Width ENABLE TXNRX TXNRX Setup to ENABLE Bus Turnaround Time Before Rx After Rx Capacitive Load Capacitive Input DIGITAL DATA TIMING (LVDS) DATA_CLK Clock Period DATA_CLK and FB_CLK Pulse Width Tx Data Setup to FB_CLK Hold to FB_CLK DATA_CLK to Data Bus Output Delay DATA_CLK to RX_FRAME Delay Pulse Width ENABLE TXNRX TXNRX Setup to ENABLE Data Sheet Symbol Min tCP tMP 16.276 45% of tCP tSTX tHTX tDDRX Typ Max Unit Test Conditions/Comments ns ns 61.44 MHz 55% of tCP 1 0 0 1.5 ns ns ns tDDDV 0 1.0 ns tENPW tTXNRXPW tCP tCP ns ns tTXNRXSU 0 ns tRPRE tRPST 2 x tCP 2 x tCP ns ns pF pF TDD mode TDD mode ns ns 61.44 MHz 55% of tCP TX_FRAME, P0_D, and P1_D 3 3 FDD independent ENSM mode TDD ENSM mode tCP tMP 16.276 45% of tCP tSTX tHTX tDDRX 1 0 0 1.2 ns ns ns tDDDV 0 1.0 ns tENPW tTXNRXPW tCP tCP ns ns tTXNRXSU 0 ns tRPRE tRPST 2 x tCP 2 x tCP ns ns pF pF TDD mode TDD mode ns ns 245.76 MHz 55% of tCP TX_FRAME, P0_D, and P1_D 3 3 tCP tMP 4.069 45% of tCP tSTX tHTX tDDRX 1 0 0.25 1.25 ns ns ns tDDDV 0.25 1.25 ns tENPW tTXNRXPW tCP tCP ns ns tTXNRXSU 0 ns FDD independent ENSM mode TDD ENSM mode TX_FRAME and TX_D Rev. C | Page 6 of 32 FDD independent ENSM mode TDD ENSM mode Data Sheet Parameter1 Bus Turnaround Time Before Rx After Rx Capacitive Load Capacitive Input SUPPLY CHARACTERISTICS 1.3 V Main Supply Voltage VDD_INTERFACE Supply Nominal Settings CMOS LVDS VDD_INTERFACE Tolerance AD9364 Symbol Min tRPRE tRPST 2 x tCP 2 x tCP VDD_GPO Supply Nominal Setting VDD_GPO Tolerance Typ 1.267 Unit Test Conditions/Comments ns ns pF pF 3 3 1.3 1.33 V 1.14 1.71 -5 2.625 2.625 +5 V V % 1.3 3.3 V -5 +5 % Current Consumption VDDx, Sleep Mode VDD_GPO 1 Max 180 50 A A Tolerance is applicable to any voltage setting When unused, must be set to 1.3 V Tolerance is applicable to any voltage setting Sum of all input currents No load When referencing a single function of a multifunction pin in the parameters, only the portion of the pin name that is relevant to the specification is listed. For full pin names of multifunction pins, refer to the Pin Configuration and Function Descriptions section. CURRENT CONSUMPTION--VDD_INTERFACE Table 2. VDD_INTERFACE = 1.2 V Parameter SLEEP MODE RX AND TX, DOUBLE DATA RATE (DDR) LTE 10 MHz Single Port Dual Port LTE 20 MHz Dual Port Min Typ 45 Max Unit A Test Conditions/Comments Power applied, device disabled 2.9 2.7 mA mA 30.72 MHz data clock, CMOS 15.36 MHz data clock, CMOS 5.2 mA 30.72 MHz data clock, CMOS Unit A Test Conditions/Comments Power applied, device disabled 4.5 4.1 mA mA 30.72 MHz data clock, CMOS 15.36 MHz data clock, CMOS 8.0 mA 30.72 MHz data clock, CMOS Unit A Test Conditions/Comments Power applied, device disabled 6.5 6.0 mA mA 30.72 MHz data clock, CMOS 15.36 MHz data clock, CMOS 11.5 mA 30.72 MHz data clock, CMOS Table 3. VDD_INTERFACE = 1.8 V Parameter SLEEP MODE RX AND TX, DDR LTE 10 MHz Single Port Dual Port LTE 20 MHz Dual Port Min Typ 84 Max Table 4. VDD_INTERFACE = 2.5 V Parameter SLEEP MODE RX AND TX, DDR LTE 10 MHz Single Port Dual Port LTE 20 MHz Dual Port Min Typ 150 Max Rev. C | Page 7 of 32 AD9364 Data Sheet CURRENT CONSUMPTION--VDDD1P3_DIG AND VDDAx (COMBINATION OF ALL 1.3 V SUPPLIES) Table 5. 800 MHz, TDD Mode Parameter RX 5 MHz Bandwidth 10 MHz Bandwidth 20 MHz Bandwidth TX 5 MHz Bandwidth 7 dBm -27 dBm 10 MHz Bandwidth 7 dBm -27 dBm 20 MHz Bandwidth 7 dBm -27 dBm Min Typ Max Unit Test Conditions/Comments 180 210 260 mA mA mA Continuous Rx Continuous Rx Continuous Rx 340 190 mA mA Continuous Tx Continuous Tx 360 220 mA mA Continuous Tx Continuous Tx 400 250 mA mA Continuous Tx Continuous Tx Table 6. TDD Mode, 2.4 GHz Parameter RX 5 MHz Bandwidth 10 MHz Bandwidth 20 MHz Bandwidth TX 5 MHz Bandwidth 7 dBm -27 dBm 10 MHz Bandwidth 7 dBm -27 dBm 20 MHz Bandwidth 7 dBm -27 dBm Min Typ Max Unit Test Conditions/Comments 175 200 240 mA mA mA Continuous Rx Continuous Rx Continuous Rx 350 160 mA mA Continuous Tx Continuous Tx 380 220 mA mA Continuous Tx Continuous Tx 410 260 mA mA Continuous Tx Continuous Tx Unit Test Conditions/Comments 175 275 mA mA Continuous Rx Continuous Rx 400 240 mA mA Continuous Tx Continuous Tx 490 385 mA mA Continuous Tx Continuous Tx Table 7. TDD Mode, 5.5 GHz Parameter RX 5 MHz Bandwidth 40 MHz Bandwidth TX 5 MHz Bandwidth 7 dBm -27 dBm 40 MHz Bandwidth 7 dBm -27 dBm Min Typ Max Rev. C | Page 8 of 32 Data Sheet AD9364 Table 8. FDD Mode, 800 MHz Parameter RX AND TX 5 MHz Bandwidth 7 dBm -27 dBm 10 MHz Bandwidth 7 dBm -27 dBm 20 MHz Bandwidth 7 dBm -27 dBm Min Typ Max Unit 490 345 mA mA 540 395 mA mA 615 470 mA mA Test Conditions/Comments Table 9. FDD Mode, 2.4 GHz Parameter RX AND TX 5 MHz Bandwidth 7 dBm -27 dBm 10 MHz Bandwidth 7 dBm -27 dBm 20 MHz Bandwidth 7 dBm -27 dBm Min Typ Max Unit 500 350 mA mA 540 390 mA mA 620 475 mA mA Test Conditions/Comments Table 10. FDD Mode, 5.5 GHz Parameter RX AND TX 5 MHz Bandwidth 7 dBm -27 dBm Min Typ 550 385 Max Unit mA mA Rev. C | Page 9 of 32 Test Conditions/Comments AD9364 Data Sheet ABSOLUTE MAXIMUM RATINGS REFLOW PROFILE Table 11. The AD9364 reflow profile is in accordance with the JEDEC JESD20 criteria for Pb-free devices. The maximum reflow temperature is 260C. Parameter VDDx to VSSx VDD_INTERFACE to VSSx VDD_GPO to VSSx Logic Inputs and Outputs to VSSx Input Current to Any Pin Except Supplies RF Inputs (Peak Power) Tx Monitor Input Power (Peak Power) Package Power Dissipation Maximum Junction Temperature (TJMAX) Operating Temperature Range Storage Temperature Range Rating -0.3 V to +1.4 V -0.3 V to +3.0 V -0.3 V to +3.9 V -0.3 V to VDD_INTERFACE + 0.3 V THERMAL RESISTANCE JA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. 10 mA Table 12. Thermal Resistance 2.5 dBm 9 dBm Package Type 144-Ball CSP_BGA (TJMAX - TA)/JA 110C Airflow Velocity (m/sec) 0 1.0 2.5 1 JA1, 2 32.3 29.6 27.8 JC1, 3 9.6 JB1, 4 20.2 Per JEDEC JESD51-7, plus JEDEC JESD51-5 2S2P test board. Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air). 3 Per MIL-STD 883, Method 1012.1. 4 Per JEDEC JESD51-8 (still air). -40C to +85C -65C to +150C 2 Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ESD CAUTION Rev. C | Page 10 of 32 JT1, 2 0.27 0.43 0.57 Unit C/W C/W C/W Data Sheet AD9364 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 11 A VSSA VSSA NC VSSA VSSA VSSA VDDA1P3_ RX_TX VDDA1P3_ RX_TX VDDA1P3_ RX_TX VDDA1P3_ RX_TX VDDA1P1_ TX_VCO TX_EXT_ LO_IN B VSSA VSSA AUXDAC1 GPO_3 GPO_2 GPO_1 GPO_0 VDD_GPO VDDA1P3_ TX_LO VDDA1P3_ TX_VCO_ LDO TX_VCO_ LDO_OUT VSSA C VSSA VSSA AUXDAC2 TEST/ ENABLE CTRL_IN0 CTRL_IN1 VSSA VSSA VSSA VSSA VSSA VSSA D VSSA VDDA1P3_ RX_RF VDDA1P3_ RX_TX CTRL_OUT0 CTRL_IN3 CTRL_IN2 P0_D9/ TX_D4_P P0_D7/ TX_D3_P P0_D5/ TX_D2_P P0_D3/ TX_D1_P P0_D1/ TX_D0_P VSSD E VSSA VDDA1P3_ RX_LO VDDA1P3_ TX_LO_ BUFFER CTRL_OUT1 CTRL_OUT2 CTRL_OUT3 P0_D11/ TX_D5_P P0_D8/ TX_D4_N P0_D6/ TX_D3_N P0_D4/ TX_D2_N P0_D2/ TX_D1_N P0_D0/ TX_D0_N F VSSA VDDA1P3_ RX_VCO_ LDO VSSA CTRL_OUT6 CTRL_OUT5 CTRL_OUT4 VSSD P0_D10/ TX_D5_N VSSD FB_CLK_P VSSD VDDD1P3_ DIG G RX_EXT_ LO_IN RX_VCO_ LDO_OUT VDDA1P1_ RX_VCO CTRL_OUT7 EN_AGC ENABLE RX_ FRAME_N RX_ FRAME_P TX_ FRAME_P FB_CLK_N DATA_ CLK_P VSSD H RXB_P VSSA VSSA TXNRX SYNC_IN VSSA VSSD P1_D11/ RX_D5_P TX_ FRAME_N VSSD DATA_ CLK_N VDD_ INTERFACE J RXB_N VSSA VDDA1P3_ RX_SYNTH SPI_DI SPI_CLK CLK_OUT P1_D10/ RX_D5_N P1_D9/ RX_D4_P P1_D7/ RX_D3_P P1_D5/ RX_D2_P P1_D3/ RX_D1_P P1_D1/ RX_D0_P K RXC_P VSSA VDDA1P3_ TX_SYNTH VDDA1P3_ BB RESETB SPI_ENB P1_D8/ RX_D4_N P1_D6/ RX_D3_N P1_D4/ RX_D2_N P1_D2/ RX_D1_N P1_D0/ RX_D0_N VSSD L RXC_N VSSA VSSA RBIAS AUXADC SPI_DO VSSA VSSA VSSA VSSA VSSA VSSA M RXA_P RXA_N NC VSSA TX_MON VSSA TXA_P TXA_N TXB_P TXB_N XTALP XTALN DC POWER GROUND 11846-002 ANALOG I/O DIGITAL I/O NO CONNECT 12 Figure 2. Pin Configuration, Top View Table 13. Pin Function Descriptions Pin No. A1, A2, A4 to A6, B1, B2, B12, C1, C2, C7 to C12, D1, E1, F1, F3, H2, H3, H6, J2, K2, L2, L3, L7 to L12, M4, M6 A3, M3 A7 to A10, D3 A11 A12 Type1 I Mnemonic VSSA Description Analog Ground. Tie these pins directly to the VSSD digital ground on the printed circuit board (one ground plane). NC I I I NC VDDA1P3_RX_TX VDDA1P1_TX_VCO TX_EXT_LO_IN B3 B4 to B7 B8 O O I AUXDAC1 GPO_3 to GPO_0 VDD_GPO B9 B10 B11 I I O VDDA1P3_TX_LO VDDA1P3_TX_VCO_LDO TX_VCO_LDO_OUT C3 C4 O I AUXDAC2 TEST/ENABLE No Connect. Do not connect to these pins. 1.3 V Supply Input. Transmit VCO Supply Input. Connect to B11. External Transmit Local Oscillator (LO) Input. When this pin is unused, tie it to ground. Auxiliary DAC 1 Output. 3.3 V Capable General-Purpose Outputs. 2.5 V to 3.3 V Supply for the Auxiliary DAC and General-Purpose Output Pins. When the VDD_GPO supply is not used, this supply must be set to 1.3 V. Transmit LO 1.3 V Supply Input. Transmit VCO LDO 1.3 V Supply Input. Connect to B9. Transmit VCO LDO Output. Connect B11 to A11 and a 1 F bypass capacitor in series with a 1 resistor to ground. Auxiliary DAC 2 Output. Test Input. Ground this pin for normal operation. Rev. C | Page 11 of 32 AD9364 Data Sheet Pin No. C5, C6, D6, D5 Type1 I Mnemonic CTRL_IN0 to CTRL_IN3 D2 D4, E4 to E6, F4 to F6, G4 I O D7 I/O VDDA1P3_RX_RF CTRL_OUT0, CTRL_OUT1 to CTRL_OUT3, CTRL_OUT6 to CTRL_OUT4, CTRL_OUT7 P0_D9/TX_D4_P D8 I/O P0_D7/TX_D3_P D9 I/O P0_D5/TX_D2_P D10 I/O P0_D3/TX_D1_P D11 I/O P0_D1/TX_D0_P D12, F7, F9, F11, G12, H7, H10, K12 E2 E3 E7 I VSSD I I I/O VDDA1P3_RX_LO VDDA1P3_TX_LO_BUFFER P0_D11/TX_D5_P E8 I/O P0_D8/TX_D4_N E9 I/O P0_D6/TX_D3_N E10 I/O P0_D4/TX_D2_N E11 I/O P0_D2/TX_D1_N E12 I/O P0_D0/TX_D0_N F2 I VDDA1P3_RX_VCO_LDO Description Control Inputs. Use C5, C6, D5, and D6 for manual Rx gain and Tx attenuation control. Receiver 1.3 V Supply Input. Connect to D3. Control Outputs. These pins are multipurpose outputs that have programmable functionality. Digital Data Port P0/Transmit Differential Input Bus. This is a dual function pin. As P0_D9, it functions as part of the 12-bit, bidirectional, parallel CMOS level Data Port 0. Alternatively, this pin (TX_D4_P) can function as part of the LVDS 6bit Tx differential input bus with internal LVDS termination. Digital Data Port P0/Transmit Differential Input Bus. This is a dual function pin. As P0_D7, it functions as part of the 12-bit bidirectional parallel CMOS level Data Port 0. Alternatively, this pin (TX_D3_P) can function as part of the LVDS 6-bit Tx differential input bus with internal LVDS termination. Digital Data Port P0/Transmit Differential Input Bus. This is a dual function pin. As P0_D5, it functions as part of the 12-bit, bidirectional, parallel CMOS level Data Port 0. Alternatively, this pin (TX_D2_P) can function as part of the LVDS 6-bit Tx differential input bus with internal LVDS termination. Digital Data Port P0/Transmit Differential Input Bus. This is a dual function pin. As P0_D3, it functions as part of the 12-bit, bidirectional, parallel CMOS level Data Port 0. Alternatively, this pin (TX_D1_P) can function as part of the LVDS 6-bit Tx differential input bus with internal LVDS termination. Digital Data Port P0/Transmit Differential Input Bus. This is a dual function pin. As P0_D1, it functions as part of the 12-bit bidirectional parallel CMOS level Data Port 0. Alternatively, this pin (TX_D0_P) can function as part of the LVDS 6-bit Tx differential input bus with internal LVDS termination. Digital Ground. Tie these pins directly to the VSSA analog ground on the printed circuit board (one ground plane). Receive LO 1.3 V Supply Input. 1.3 V Supply Input. Digital Data Port P0/Transmit Differential Input Bus. This is a dual function pin. As P0_D11, it functions as part of the 12-bit, bidirectional, parallel CMOS level Data Port 0. Alternatively, this pin (TX_D5_P) can function as part of the LVDS 6-bit Tx differential input bus with internal LVDS termination. Digital Data Port P0/Transmit Differential Input Bus. This is a dual function pin. As P0_D8, it functions as part of the 12-bit, bidirectional, parallel CMOS level Data Port 0. Alternatively, this pin (TX_D4_N) can function as part of the LVDS 6-bit Tx differential input bus with internal LVDS termination. Digital Data Port P0/Transmit Differential Input Bus. This is a dual function pin. As P0_D6, it functions as part of the 12-bit, bidirectional, parallel CMOS level Data Port 0. Alternatively, this pin (TX_D3_N) can function as part of the LVDS 6-bit Tx differential input bus with internal LVDS termination. Digital Data Port P0/Transmit Differential Input Bus. This is a dual function pin. As P0_D4, it functions as part of the 12-bit, bidirectional, parallel CMOS level Data Port 0. Alternatively, this pin (TX_D2_N) can function as part of the LVDS 6-bit Tx differential input bus with internal LVDS termination. Digital Data Port P0/Transmit Differential Input Bus. This is a dual function pin. As P0_D2, it functions as part of the 12-bit, bidirectional, parallel CMOS level Data Port 0. Alternatively, this pin (TX_D1_N) can function as part of the LVDS 6-bit Tx differential input bus with internal LVDS termination. Digital Data Port P0/Transmit Differential Input Bus. This is a dual function pin. As P0_D0, it functions as part of the 12-bit, bidirectional, parallel CMOS level Data Port 0. Alternatively, this pin (TX_D0_N) can function as part of the LVDS 6-bit Tx differential input bus with internal LVDS termination. Receive VCO LDO 1.3 V Supply Input. Connect F2 to E2. Rev. C | Page 12 of 32 Data Sheet AD9364 Pin No. F8 Type1 I/O Mnemonic P0_D10/TX_D5_N F10, G10 I FB_CLK_P, FB_CLK_N F12 G1 G2 I I O VDDD1P3_DIG RX_EXT_LO_IN RX_VCO_LDO_OUT G3 G5 G6 G7, G8 I I I O VDDA1P1_RX_VCO EN_AGC ENABLE RX_FRAME_N, RX_FRAME_P G9, H9 I TX_FRAME_P, TX_FRAME_N G11, H11 O DATA_CLK_P, DATA_CLK_N H1, J1 I RXB_P, RXB_N H4 I TXNRX H5 I SYNC_IN H8 I/O P1_D11/RX_D5_P H12 J3 J4 J5 J6 I I I I O VDD_INTERFACE VDDA1P3_RX_SYNTH SPI_DI SPI_CLK CLK_OUT J7 I/O P1_D10/RX_D5_N J8 I/O P1_D9/RX_D4_P J9 I/O P1_D7/RX_D3_P J10 I/O P1_D5/RX_D2_P J11 I/O P1_D3/RX_D1_P Description Digital Data Port P0/Transmit Differential Input Bus. This is a dual function pin. As P0_D10, it functions as part of the 12-bit, bidirectional, parallel CMOS level Data Port 0. Alternatively, this pin (TX_D5_N) can function as part of the LVDS 6-bit Tx differential input bus with internal LVDS termination. Feedback Clock. These pins receive the FB_CLK signal that clocks in Tx data. In CMOS mode, use FB_CLK_P as the input and tie FB_CLK_N to ground. 1.3 V Digital Supply Input. External Receive LO Input. When this pin is unused, tie it to ground. Receive VCO LDO Output. Connect this pin directly to G3 and a 1 F bypass capacitor in series with a 1 resistor to ground. Receive VCO Supply Input. Connect this pin directly to G2 only. Manual Control Input for Automatic Gain Control (AGC). Control Input. This pin moves the device through various operational states. Receive Digital Data Framing Output Signal. These pins transmit the RX_FRAME signal that indicates whether the Rx output data is valid. In CMOS mode, use RX_FRAME_P as the output and leave RX_FRAME_N unconnected. Transmit Digital Data Framing Input Signal. These pins receive the TX_FRAME signal that indicates when Tx data is valid. In CMOS mode, use TX_FRAME_P as the input and tie TX_FRAME_N to ground. Receive Data Clock Output. These pins transmit the DATA_CLK signal that is used by the BBP to clock Rx data. In CMOS mode, use DATA_CLK_P as the output and leave DATA_CLK_N unconnected. Receive Channel Differential Input B. Alternatively, each pin can be used as a single-ended input. These inputs experience degraded performance above 3 GHz. Unused pins must be tied to ground. Enable State Machine Control Signal. This pin controls the data port bus direction. Logic low selects the Rx direction; logic high selects the Tx direction. Input to Synchronize Digital Clocks Between Multiple AD9364 Devices. If this pin is unused, it must be tied to ground. Digital Data Port P1/Receive Differential Output Bus. This is a dual function pin. As P1_D11, it functions as part of the 12-bit bidirectional parallel CMOS level Data Port 1. Alternatively, this pin (RX_D5_P) can function as part of the LVDS 6-bit Rx differential output bus with internal LVDS termination. 1.2 V to 2.5 V Supply for Digital I/O Pins (1.8 V to 2.5 V in LVDS Mode). 1.3 V Supply Input. SPI Serial Data Input. SPI Clock Input. Output Clock. This pin can be configured to output either a buffered version of the external input clock, the DCXO, or a divided-down version of the internal ADC_CLK. Digital Data Port P1/Receive Differential Output Bus. This is a dual function pin. As P1_D10, it functions as part of the 12-bit bidirectional parallel CMOS level Data Port 1. Alternatively, this pin (RX_D5_N) can function as part of the LVDS 6-bit Rx differential output bus with internal LVDS termination. Digital Data Port P1/Receive Differential Output Bus. This is a dual function pin. As P1_D9, it functions as part of the 12-bit bidirectional parallel CMOS level Data Port 1. Alternatively, this pin (RX_D4_P) can function as part of the LVDS 6-bit Rx differential output bus with internal LVDS termination. Digital Data Port P1/Receive Differential Output Bus. This is a dual function pin. As P1_D7, it functions as part of the 12-bit bidirectional parallel CMOS level Data Port 1. Alternatively, this pin (RX_D3_P) can function as part of the LVDS 6-bit Rx differential output bus with internal LVDS termination. Digital Data Port P1/Receive Differential Output Bus. This is a dual function pin. As P1_D5, it functions as part of the 12-bit bidirectional parallel CMOS level Data Port 1. Alternatively, this pin (RX_D2_P) can function as part of the LVDS 6-bit Rx differential output bus with internal LVDS termination. Digital Data Port P1/Receive Differential Output Bus. This is a dual function pin. As P1_D3, it functions as part of the 12-bit bidirectional parallel CMOS level Data Port 1. Alternatively, this pin (RX_D1_P) can function as part of the LVDS 6-bit Rx differential output bus with internal LVDS termination. Rev. C | Page 13 of 32 AD9364 Data Sheet Pin No. J12 Type1 I/O Mnemonic P1_D1/RX_D0_P K1, L1 I RXC_P, RXC_N K3 K4 K5 K6 K7 I I I I I/O VDDA1P3_TX_SYNTH VDDA1P3_BB RESETB SPI_ENB P1_D8/RX_D4_N K8 I/O P1_D6/RX_D3_N K9 I/O P1_D4/RX_D2_N K10 I/O P1_D2/RX_D1_N K11 I/O P1_D0/RX_D0_N L4 I RBIAS L5 L6 M1, M2 I O I AUXADC SPI_DO RXA_P, RXA_N M5 M7, M8 M9, M10 M11, M12 I O O I TX_MON TXA_P, TXA_N TXB_P, TXB_N XTALP, XTALN 1 Description Digital Data Port P1/Receive Differential Output Bus. This is a dual function pin. As P1_D1, it functions as part of the 12-bit bidirectional parallel CMOS level Data Port 1. Alternatively, this pin (RX_D0_P) can function as part of the LVDS 6-bit Rx differential output bus with internal LVDS termination. Receive Channel Differential Input C. Alternatively, each pin can be used as a single-ended input. These inputs experience degraded performance above 3 GHz. Unused pins must be tied to ground. 1.3 V Supply Input. 1.3 V Supply Input. Asynchronous Reset. Logic low resets the device. SPI Enable Input. Set this pin to logic low to enable the SPI bus. Digital Data Port P1/Receive Differential Output Bus. This is a dual function pin. As P1_D8, it functions as part of the 12-bit bidirectional parallel CMOS level Data Port 1. Alternatively, this pin (RX_D4_N) can function as part of the LVDS 6-bit Rx differential output bus with internal LVDS termination. Digital Data Port P1/Receive Differential Output Bus. This is a dual function pin. As P1_D6, it functions as part of the 12-bit bidirectional parallel CMOS level Data Port 1. Alternatively, this pin (RX_D3_N) can function as part of the LVDS 6-bit Rx differential output bus with internal LVDS termination. Digital Data Port P1/Receive Differential Output Bus. This is a dual function pin. As P1_D4, it functions as part of the 12-bit bidirectional parallel CMOS level Data Port 1. Alternatively, this pin (RX_D2_N) can function as part of the LVDS 6-bit Rx differential output bus with internal LVDS termination. Digital Data Port P1/Receive Differential Output Bus. This is a dual function pin. As P1_D2, it functions as part of the 12-bit bidirectional parallel CMOS level Data Port 1. Alternatively, this pin (RX_D1_N) can function as part of the LVDS 6-bit Rx differential output bus with internal LVDS termination. Digital Data Port P1/Receive Differential Output Bus. This is a dual function pin. As P1_D0, it functions as part of the 12-bit bidirectional parallel CMOS level Data Port 1. Alternatively, this pin (RX_D0_N) can function as part of the LVDS 6-bit Rx differential output bus with internal LVDS termination. Bias Input Reference. Connect this pin through a 14.3 k (1% tolerance) resistor to ground. Auxiliary ADC Input. If this pin is unused, tie it to ground. SPI Serial Data Output in 4-Wire Mode, High-Z in 3-Wire Mode. Receive Channel Differential Input A. Alternatively, each pin can be used as a single-ended input. Unused pins must be tied to ground. Transmit Channel Power Monitor Input. If this pin is unused, tie it to ground. Transmit Channel Differential Output A. Unused pins must be tied to 1.3 V. Transmit Channel Differential Output B. Unused pins must be tied to 1.3 V. Reference Frequency Crystal Connections. When a crystal is used, connect it between these two pins. When an external clock source is used, connect it to XTALN and leave XTALP unconnected. I is input, O is output, I/O is input/output, NC is not connected. Rev. C | Page 14 of 32 Data Sheet AD9364 TYPICAL PERFORMANCE CHARACTERISTICS 800 MHZ FREQUENCY BAND 0 4.0 -40C +25C +85C -15 Rx EVM (dB) 2.5 2.0 1.5 -25 -35 0.5 -40 750 800 850 900 -45 -75 -60 -55 -50 -45 -40 -35 -30 -25 Figure 6. Rx EVM vs. Input Power, 64 QAM LTE 10 MHz Mode, 19.2 MHz REF_CLK 0 -40C +25C +85C 4 -65 INPUT POWER (dBm) Figure 3. Rx Noise Figure vs. Frequency 5 -70 11846-006 -30 FREQUENCY (MHz) -5 -10 3 -40C +25C +85C -15 2 Rx EVM (dB) 1 0 -20 -25 -30 -1 -35 -2 -90 -80 -70 -60 -50 -40 -30 -20 -10 INPUT POWER (dBm) Figure 4. RSSI Error vs. Input Power, LTE 10 MHz Modulation (Referenced to -50 dBm Input Power at 800 MHz) 3 -45 -90 11846-004 -3 -100 -5 1 -10 Rx EVM (dB) 2 0 -20 -2 -25 -60 -50 -40 -30 -20 INPUT POWER (dBm) Figure 5. RSSI Error vs. Input Power, EDGE Modulation (Referenced to -50 dBm Input Power at 800 MHz) -10 -30 -72 11846-005 -70 -50 -40 -30 -20 -10 -40C +25C +85C -15 -1 -80 -60 Figure 7. Rx EVM vs. Input Power, GSM Mode, 30.72 MHz REF_CLK (Doubled Internally for RF Synthesizer) 0 -90 -70 INPUT POWER (dBm) -40C +25C +85C -3 -110 -100 -80 11846-007 -40 -68 -64 -60 -56 -52 -48 -44 -40 INTERFERER POWER LEVEL (dBm) -36 -32 11846-008 RSSI ERROR (dB) -20 1.0 0 700 RSSI ERROR (dB) -40C +25C +85C -10 3.0 11846-003 Rx NOISE FIGURE (dB) 3.5 -5 Figure 8. Rx EVM vs. Interferer Power Level, LTE 10 MHz Signal of Interest with PIN = -82 dBm, 5 MHz OFDM Blocker at 7.5 MHz Offset Rev. C | Page 15 of 32 AD9364 0 Data Sheet 20 -40C +25C +85C 15 10 -4 IIP3 (dBm) Rx EVM (dB) 5 -8 0 -5 -40C +25C +85C -10 -12 -15 -54 -52 -50 -48 -46 -44 -42 -40 -38 -36 INTERFERER POWER LEVEL (dBm) -25 11846-009 -16 -56 20 14 44 52 Rx GAIN INDEX 60 68 76 100 -40C +25C +85C 90 80 10 70 IIP2 (dBm) Rx NOISE FIGURE (dB) 36 Figure 12. Third-Order Input Intercept Point (IIP3) vs. Rx Gain Index, f1 = 1.45 MHz, f2 = 2.89 MHz, GSM Mode Figure 9. Rx EVM vs. Interferer Power Level, LTE 10 MHz Signal of Interest with PIN = -90 dBm, 5 MHz OFDM Blocker at 17.5 MHz Offset 12 28 11846-012 -20 8 6 -40C +25C +85C 60 50 40 30 4 20 2 -39 -35 -31 -27 -23 INTERFERER POWER LEVEL (dBm) Figure 10. Rx Noise Figure vs. Interferer Power Level, EDGE Signal of Interest with PIN = -90 dBm, CW Blocker at 3 MHz Offset, Gain Index = 64 80 28 36 44 52 60 68 76 Figure 13. Second-Order Input Intercept Point (IIP2) vs. Rx Gain Index, f1 = 2.00 MHz, f2 = 2.01 MHz, GSM Mode -100 -40C +25C +85C Rx LO LEAKAGE (dBm) -105 76 74 72 70 -110 -115 -120 800 FREQUENCY (MHz) 850 900 11846-011 750 Figure 11. Rx Gain vs. Frequency, Gain Index = 76 (Maximum Setting) Rev. C | Page 16 of 32 -130 700 750 800 850 900 FREQUENCY (MHz) Figure 14. Rx Local Oscillator (LO) Leakage vs. Frequency 11846-014 -125 68 66 700 20 Rx GAIN INDEX -40C +25C +85C 78 Rx GAIN (dB) 0 11846-010 -43 11846-013 10 0 -47 Data Sheet AD9364 0 0 ATT 0dB ATT 3dB ATT 6dB -20 Tx OUTPUT POWER (dBm/100kHz) POWER AT LNA INPUT (dBm/750kHz) -10 -40 -60 -80 -100 -20 -30 -40 -50 -60 -70 -80 2000 4000 6000 8000 10000 11846-015 12000 FREQUENCY (MHz) Figure 15. Rx Emission at LNA Input, DC to 12 GHz, fLO_RX = 800 MHz, LTE 10 MHz, fLO_TX = 860 MHz -60 -80 6.5 1.4 1.6 1.2 1.0 0.8 0.4 0.6 0 FREQUENCY OFFSET (MHz) Figure 16. Tx Output Power vs. Frequency, Attenuation Setting = 0 dB, Single Tone Output 0.5 20 Tx OUTPUT POWER (dBm/30kHz) 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 ATT 0dB ATT 3dB ATT 6dB -20 -40 -60 -80 0 10 20 30 40 50 ATTENUATION SETTING (dB) Figure 17. Tx Power Control Linearity Error vs. Attenuation Setting -120 -6 -4 -2 0 2 FREQUENCY OFFSET (MHz) 4 6 11846-020 -0.5 0 -100 -0.4 11846-017 STEP LINEARITY ERROR (dB) Figure 19. Tx Spectrum vs. Frequency Offset from Carrier Frequency, fLO_TX = 800 MHz, GSM Downlink (Digital Attenuation Variations Shown), 3 MHz Range -40C +25C +85C 0.4 11846-019 FREQUENCY (MHz) -100 0.2 900 -0.2 850 -1.6 800 11846-016 750 -0.4 7.0 -0.8 7.5 -40 -0.6 8.0 -20 -1.0 8.5 ATT 0dB ATT 3dB ATT 6dB 0 Tx OUTPUT POWER (dBm/30kHz) Tx OUTPUT POWER (dBm) 15 20 9.0 6.0 700 10 Figure 18. Tx Spectrum vs. Frequency Offset from Carrier Frequency, fLO_TX = 800 MHz, LTE 10 MHz Downlink (Digital Attenuation Variations Shown) -40C +25C +85C 9.5 5 0 -5 FREQUENCY OFFSET (MHz) -1.4 10.0 -10 -1.2 0 -100 -15 11846-018 -90 -120 Figure 20. Tx Spectrum vs. Frequency Offset from Carrier Frequency, fLO_TX = 800 MHz, GSM Downlink (Digital Attenuation Variations Shown), 12 MHz Range Rev. C | Page 17 of 32 AD9364 0.30 -40C +25C +85C INTEGRATED PHASE NOISE (rms) -25 -35 -40 -50 0 5 10 15 20 25 30 35 40 ATTENUATION SETTING (dB) Figure 21. Tx EVM vs. Transmitter Attenuation Setting, fLO_TX = 800 MHz, LTE 10 MHz, 64 QAM Modulation, 19.2 MHz REF_CLK 0.10 0.05 -35 Tx CARRIER AMPLITUDE (dBc) -40C +25C +85C -30 -35 -40 -45 800 850 900 ATT 0, -40C ATT 25, -40C ATT 50, -40C ATT 0, +25C ATT 25, +25C ATT 50, +25C ATT 0, +85C ATT 25, +85C ATT 50, +85C -40 -45 -50 -55 -60 10 20 30 40 50 -70 700 11846-022 0 0.4 0.3 0.2 0 700 750 800 FREQUENCY (MHz) 850 900 11846-023 0.1 Figure 23. Integrated Tx LO Phase Noise vs. Frequency, 19.2 MHz REF_CLK 850 900 Figure 25. Tx Carrier Rejection vs. Frequency Tx SECOND-ORDER HARMONIC DISTORTION (dBc) -40C +25C +85C 800 FREQUENCY (MHz) Figure 22. Tx EVM vs. Transmitter Attenuation Setting, fLO_TX = 800 MHz, GSM Modulation, 30.72 MHz REF_CLK (Doubled Internally for RF Synthesizer) 0.5 750 11846-025 -65 ATTENUATION SETTING (dB) INTEGRATED PHASE NOISE (RMS) 750 Figure 24. Integrated Tx LO Phase Noise vs. Frequency, 30.72 MHz REF_CLK (Doubled Internally for RF Synthesizer) -30 -25 Tx EVM (dB) 0.15 FREQUENCY (MHz) -20 -50 0.20 0 700 11846-021 -45 -40C +25C +85C -50 ATT 0, -40C ATT 25, -40C ATT 50, -40C ATT 0, +25C ATT 25, +25C ATT 50, +25C ATT 0, +85C ATT 25, +85C ATT 50, +85C -55 -60 -65 -70 -75 -80 700 750 800 FREQUENCY (MHz) 850 900 11846-026 Tx EVM (dB) -30 0.25 11846-024 -20 Data Sheet Figure 26. Tx Second-Order Harmonic Distortion (HD2) vs. Frequency Rev. C | Page 18 of 32 Data Sheet AD9364 Tx THIRD-ORDER HARMONIC DISTORTION (dBc) -20 ATT 0, -40C ATT 25, -40C ATT 50, -40C -25 ATT 0, +25C ATT 25, +25C ATT 50, +25C 170 ATT 0, +85C ATT 25, +85C ATT 50, +85C 165 Tx SNR (dB/Hz) -30 -35 -40 -45 160 -40C +25C +85C 155 150 -50 145 800 850 900 FREQUENCY (MHz) Figure 27. Tx Third-Order Harmonic Distortion (HD3) vs. Frequency 30 15 10 12 16 20 ATTENUATION SETTING (dB) 11846-028 5 8 Figure 28. Tx Third-Order Output Intercept Point (OIP3) vs. Attenuation Setting 170 -40C +25C +85C Tx SNR (dB/Hz) 160 155 150 3 6 9 ATTENUATION SETTING (dB) 12 15 11846-029 145 0 20 -35 ATT 0, -40C ATT 25, -40C ATT 50, -40C ATT 0, +25C ATT 25, +25C ATT 50, +25C ATT 0, +85C ATT 25, +85C ATT 50, +85C -40 -45 -50 -55 -60 -65 -70 700 750 800 850 900 FREQUENCY (MHz) Figure 31. Tx Single Sideband (SSB) Rejection vs. Frequency, 1.5375 MHz Offset 165 140 16 12 ATTENUATION SETTING (dB) Tx SINGLE SIDEBAND AMPLITUDE (dBc) Tx OIP3 (dBm) 20 4 8 4 -30 -40C +25C +85C 0 0 Figure 30. Tx Signal-to-Noise Ratio (SNR) vs. Transmitter Attenuation Setting, GSM Signal of Interest with Noise Measured at 20 MHz Offset 25 0 140 Figure 29. Tx Signal-to-Noise Ratio (SNR) vs. Transmitter Attenuation Setting, LTE 10 MHz Signal of Interest with Noise Measured at 90 MHz Offset Rev. C | Page 19 of 32 11846-031 750 11846-027 -60 700 11846-030 -55 AD9364 Data Sheet 2.4 GHZ FREQUENCY BAND 0 4.0 3.5 -40C +25C +85C -10 2.5 Rx EVM (dB) Rx NOISE FIGURE (dB) -5 3.0 2.0 1.5 -15 -20 1.0 1900 2000 2100 2200 2300 2400 2500 2600 2700 FREQUENCY (MHz) Figure 32. Rx Noise Figure vs. Frequency 5 4 -30 -72 11846-032 0 1800 -40C +25C +85C -68 -64 -60 -56 -52 -48 -44 -40 -36 -32 -28 INTERFERER POWER LEVEL (dBm) 11846-035 -25 0.5 Figure 35. Rx EVM vs. Interferer Power Level, LTE 20 MHz Signal of Interest with PIN = -75 dBm, LTE 20 MHz Blocker at 20 MHz Offset 0 -40C +25C +85C -40C +25C +85C -5 -10 2 Rx EVM (dB) RSSI ERROR (dB) 3 1 0 -15 -20 -1 -25 -90 -80 -70 -60 -50 -40 -30 -20 -10 INPUT POWER (dBm) Figure 33. RSSI Error vs. Input Power, Referenced to -50 dBm Input Power at 2.4 GHz 0 -5 -30 -60 11846-033 -3 -100 -55 -50 -45 -40 -35 -30 -25 -20 INTERFERER POWER LEVEL (dBm) 11846-036 -2 Figure 36. Rx EVM vs. Interferer Power Level, LTE 20 MHz Signal of Interest with PIN = -75 dBm, LTE 20 MHz Blocker at 40 MHz Offset 80 -40C +25C +85C 78 -40C +25C +85C -10 76 Rx GAIN (dB) -20 -25 74 72 -30 70 -35 -45 -75 -70 -65 -60 -55 -50 -45 -40 -35 -30 -25 INPUT POWER (dBm) Figure 34. Rx EVM vs. Input Power, 64 QAM LTE 20 MHz Mode, 40 MHz REF_CLK 66 1800 1900 2000 2100 2200 2300 2400 FREQUENCY (MHz) 2500 2600 2700 11846-037 68 -40 11846-034 Rx EVM (dB) -15 Figure 37. Rx Gain vs. Frequency, Gain Index = 76 (Maximum Setting) Rev. C | Page 20 of 32 Data Sheet 15 0 -40C +25C +85C POWER AT LNA INPUT (dBm/750kHz) 20 AD9364 10 IIP3 (dBm) 5 0 -5 -10 -15 -20 -40 -60 -80 -100 28 36 44 52 60 76 68 Rx GAIN INDEX -120 11846-038 -25 20 4000 6000 8000 10000 12000 Figure 41. Rx Emission at LNA Input, DC to 12 GHz, fLO_RX = 2.4 GHz, LTE 20 MHz, fLO_TX = 2.46 GHz 10.0 -40C +25C +85C -40C +25C +85C 9.5 Tx OUTPUT POWER (dBm) 70 60 IIP2 (dBm) 2000 FREQUENCY (MHz) Figure 38. Third-Order Input Intercept Point (IIP3) vs. Rx Gain Index, f1 = 30 MHz, f2 = 61 MHz 80 0 11846-041 -20 50 40 9.0 8.5 8.0 7.5 7.0 30 28 36 44 52 60 68 76 Rx GAIN INDEX Figure 39. Second-Order Input Intercept Point (IIP2) vs. Rx Gain Index, f1 = 60 MHz, f2 = 61 MHz -100 6.0 1800 11846-039 20 20 STEP LINEARITY ERROR (dB) -105 -125 2300 2400 2500 2600 2700 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 1900 2000 2100 2200 2300 2400 2500 2600 2700 FREQUENCY (MHz) -0.5 0 10 20 30 40 50 ATTENUATION SETTING (dB) Figure 43. Tx Power Control Linearity Error vs. Attenuation Setting Figure 40. Rx Local Oscillator (LO) Leakage vs. Frequency Rev. C | Page 21 of 32 11846-043 -0.4 -130 1800 11846-040 Rx LO LEAKAGE (dBm) 2200 -40C +25C +85C 0.4 -120 2100 Figure 42. Tx Output Power vs. Frequency, Attenuation Setting = 0 dB, Single Tone Output 0.5 -115 2000 FREQUENCY (MHz) -40C +25C +85C -110 1900 11846-042 6.5 AD9364 -30 ATT 0dB ATT 3dB ATT 6dB -35 -20 Tx CARRIER AMPLITUDE (dBc) Tx OUTPUT POWER (dBm/100kHz) 0 Data Sheet -40 -60 -80 ATT 0, +85C ATT 25, +85C ATT 50, +85C ATT 0, +25C ATT 25, +25C ATT 50, +25C ATT 0, -40C ATT 25, -40C ATT 50, -40C -40 -45 -50 -55 -60 -100 -10 -5 0 5 10 15 20 25 FREQUENCY OFFSET (MHz) -70 1800 -25 Tx EVM (dB) -30 -35 -40 -50 0 5 10 15 20 25 30 35 40 ATTENUATION SETTING (dB) 11846-045 -45 -40C +25C +85C 0.4 0.3 0.2 0.1 0 1800 1900 2000 2100 2200 2300 2400 FREQUENCY (MHz) 2500 2600 2700 2300 2400 2500 2600 2700 -50 ATT 0, -40C ATT 25, -40C ATT 50, -40C ATT 0, +25C ATT 25, +25C ATT 50, +25C ATT 0, +85C ATT 25, +85C ATT 50, +85C -55 -60 -65 -70 -75 -80 1800 1900 2000 2100 2200 2300 2400 2500 2600 2700 Figure 48. Tx Second-Order Harmonic Distortion (HD2) vs. Frequency 11846-046 INTEGRATED PHASE NOISE (rms) 0.5 2200 FREQUENCY (MHz) Tx THIRD-ORDER HARMONIC DISTORTION (dBc) Figure 45. Tx EVM vs. Transmitter Attenuation Setting, 40 MHz REF_CLK, LTE 20 MHz, 64 QAM Modulation 2100 Figure 47. Tx Carrier Rejection vs. Frequency Tx SECOND-ORDER HARMONIC DISTORTION (dBc) -40C +25C +85C 2000 FREQUENCY (MHz) Figure 44. Tx Spectrum vs. Frequency Offset from Carrier Frequency, fLO_TX = 2.3 GHz, LTE 20 MHz Downlink (Digital Attenuation Variations Shown) -20 1900 11846-048 -15 Figure 46. Integrated Tx LO Phase Noise vs. Frequency, 40 MHz REF_CLK Rev. C | Page 22 of 32 -20 -25 ATT 0, -40C ATT 25, -40C ATT 50, -40C ATT 0, +25C ATT 25, +25C ATT 50, +25C ATT 0, +85C ATT 25, +85C ATT 50, +85C -30 -35 -40 -45 -50 -55 -60 1800 1900 2000 2100 2200 2300 2400 2500 2600 2700 FREQUENCY (MHz) Figure 49. Tx Third-Order Harmonic Distortion (HD3) vs. Frequency 11846-049 -20 11846-044 -120 -25 11846-047 -65 Data Sheet -30 Tx SINGLE SIDEBAND AMPLITUDE (dBc) -40C +25C +85C Tx OIP3 (dBm) 25 20 15 10 0 0 4 8 12 16 20 ATTENUATION SETTING (dB) 11846-050 5 Figure 50. Tx Third-Order Output Intercept Point (OIP3) vs. Attenuation Setting 160 156 Tx SNR (dB/Hz) 154 152 150 148 146 144 0 3 6 9 ATTENUATION SETTING (dB) 12 15 11846-051 142 140 ATT 0, +25C ATT 25, +25C ATT 50, +25C ATT 0, +85C ATT 25, +85C ATT 50, +85C -40 -45 -50 -55 -60 -65 -70 1800 1900 2000 2100 2200 2300 2400 2500 2600 2700 FREQUENCY (MHz) Figure 52. Tx Single Sideband (SSB) Rejection vs. Frequency, 3.075 MHz Offset -40C +25C +85C 158 -35 ATT 0, -40C ATT 25, -40C ATT 50, -40C Figure 51. Tx Signal-to-Noise Ratio (SNR) vs. Transmitter Attenuation Setting, LTE 20 MHz Signal of Interest with Noise Measured at 90 MHz Offset Rev. C | Page 23 of 32 11846-052 30 AD9364 AD9364 Data Sheet 6 5 5 0 4 -5 Rx EVM (dB) 3 -40C +25C +85C 2 -40C +25C +85C -15 1 -20 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 6.0 FREQUENCY (GHz) -25 -72 11846-053 0 5.0 -10 Figure 53. Rx Noise Figure vs. Frequency -67 -62 -57 -52 -47 -42 -37 -32 INTERFERER POWER LEVEL (dBm) 11846-056 Rx NOISE FIGURE (dB) 5.5 GHZ FREQUENCY BAND Figure 56. Rx EVM vs. Interferer Power Level, WiMAX 40 MHz Signal of Interest with PIN = -74 dBm, WiMAX 40 MHz Blocker at 40 MHz Offset 5 5 4 0 2 -40C +25C +85C -5 Rx EVM (dB) RSSI ERROR (dB) 3 1 0 -10 -40C +25C +85C -15 -1 -20 -80 -70 -60 -50 -40 -30 -20 -10 INPUT POWER (dBm) -25 -60 11846-054 -3 -90 Figure 54. RSSI Error vs. Input Power, Referenced to -50 dBm Input Power at 5.8 GHz -55 -50 -45 -40 -35 -30 -25 INTERFERER POWER LEVEL (dBm) 11846-057 -2 Figure 57. Rx EVM vs. Interferer Power Level, WiMAX 40 MHz Signal of Interest with PIN = -74 dBm, WiMAX 40 MHz Blocker at 80 MHz Offset 0 70 -5 -20 -25 66 64 -30 -40C +25C +85C 62 -35 -40 -74 -68 -62 -56 -50 -44 -38 -32 -26 -20 INPUT POWER (dBm) Figure 55. Rx EVM vs. Input Power, 64 QAM WiMAX 40 MHz Mode, 40 MHz REF_CLK (Doubled Internally for RF Synthesizer) 60 5.0 5.1 5.2 5.3 5.4 5.5 5.6 FREQUENCY (GHz) 5.7 5.8 5.9 6.0 11846-058 Rx GAIN (dB) -15 11846-055 Rx EVM (dB) 68 -40C +25C +85C -10 Figure 58. Rx Gain vs. Frequency, Gain Index = 76 (Maximum Setting) Rev. C | Page 24 of 32 Data Sheet AD9364 20 0 POWER AT LNA INPUT (dBm/150kHz) 5 -40C +25C +85C 0 -5 -10 -20 6 16 26 36 46 56 66 76 Rx GAIN INDEX -80 -100 0 15 20 25 30 FREQUENCY (GHz) 10 70 9 Tx OUTPUT POWER (dBm) 80 -40C +25C +85C 50 10 5 Figure 62. Rx Emission at LNA Input, DC to 26 GHz, fLO_RX = 5.8 GHz, WiMAX 40 MHz 60 40 30 -40C +25C +85C 8 7 6 5 20 28 36 44 52 60 68 76 Rx GAIN INDEX 4 5.0 11846-060 20 Figure 60. Second-Order Input Intercept Point (IIP2) vs. Rx Gain Index, f1 = 70 MHz, f2 = 71 MHz 0.4 -94 0.3 STEP LINEARITY ERROR (dB) -92 -98 -40C +25C +85C -102 -104 -106 5.3 5.4 5.5. 5.6 5.7 5.8 5.9 6.0 Figure 63. Tx Output Power vs. Frequency, Attenuation Setting = 0 dB, Single Tone 0.5 -100 5.2 FREQUENCY (GHz) -90 -96 5.1 11846-063 IIP2 (dBm) -60 -120 Figure 59. Third-Order Input Intercept Point (IIP3) vs. Rx Gain Index, f1 = 50 MHz, f2 = 101 MHz -108 0.2 0.1 0.0 -0.1 -0.2 -40C +25C +85C -0.3 -0.4 -110 5.0 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 FREQUENCY (GHz) 6.0 11846-061 Rx LO LEAKAGE (dBm) -40 11846-059 -15 -20 Figure 61. Rx Local Oscillator (LO) Leakage vs. Frequency -0.5 0 10 20 30 40 50 60 70 80 90 ATTENUATION SETTING (dB) Figure 64. Tx Power Control Linearity Error vs. Attenuation Setting Rev. C | Page 25 of 32 11846-064 IIP3 (dBm) 10 11846-062 15 AD9364 Data Sheet 0 0 -10 ATT 0dB ATT 3dB ATT 6dB -20 Tx CARRIER AMPLITUDE (dBc) -30 -40 -50 -60 -70 ATT 0, +85C ATT 25, +85C ATT 50, +85C -20 -30 -40 -50 -20 -10 0 10 20 30 40 50 FREQUENCY OFFSET (MHz) -70 5.0 -34 -36 -38 -40 0 2 4 6 8 10 ATTENUATION SETTING (dB) 11846-066 -40C +25C +85C Figure 66. Tx EVM vs. Transmitter Attenuation Setting, WiMAX 40 MHz, 64 QAM Modulation, fLO_TX = 5.495 GHz, 40 MHz REF_CLK (Doubled Internally for RF Synthesizer) 0.7 0.6 0.5 0.4 -40C +25C +85C 0.3 0.2 0 5.0 5.1 5.2 5.3 5.4 5.5 5.6 FREQUENCY (GHz) 5.7 5.8 5.9 6.0 5.5 5.6 5.7 5.8 5.9 6.0 ATT 0, -40C ATT 25, -40C ATT 50, -40C -55 ATT 0, +25C ATT 25, +25C ATT 50, +25C ATT 0, +85C ATT 25, +85C ATT 50, +85C -60 -65 -70 -75 -80 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 6.0 FREQUENCY (GHz) Figure 69. Tx Second-Order Harmonic Distortion (HD2) vs. Frequency 11846-067 0.1 5.4 -50 5.0 Tx THIRD-ORDER HARMONIC DISTORTION (dBc) 0.8 5.3 Figure 68. Tx Carrier Rejection vs. Frequency Tx SECOND-ORDER HARMONIC DISTORTION (dBc) -32 5.2 FREQUENCY (GHz) Figure 65. Tx Spectrum vs. Frequency Offset from Carrier Frequency, fLO_TX = 5.8 GHz, WiMAX 40 MHz Downlink (Digital Attenuation Variations Shown) -30 5.1 11846-068 -30 11846-069 -40 11846-065 -90 -50 Tx EVM (dB) ATT 0, +25C ATT 25, +25C ATT 50, +25C -60 -80 INTEGRATED PHASE NOISE (RMS) ATT 0, -40C ATT 25, -40C ATT 50, -40C Figure 67. Integrated Tx LO Phase Noise vs. Frequency, 40 MHz REF_CLK (Doubled Internally for RF Synthesizer) Rev. C | Page 26 of 32 -10 -15 ATT 0, -40C ATT 25, -40C ATT 50, -40C ATT 0, +25C ATT 25, +25C ATT 50, +25C ATT 0, +85C ATT 25, +85C ATT 50, +85C -20 -25 -30 -35 -40 -45 -50 5.0 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 6.0 FREQUENCY (GHz) Figure 70. Tx Third-Order Harmonic Distortion (HD3) vs. Frequency 11846-070 Tx OUTPUT POWER (dBm/1MHz) -10 Data Sheet AD9364 20 Tx OIP3 (dBm) 16 12 -40C +25C +85C 8 4 -4 0 4 8 12 16 20 ATTENUATION SETTING (dB) Figure 71. Tx Third-Order Output Intercept Point (OIP3) vs. Attenuation Setting, fLO_TX = 5.8 GHz Tx SNR (dB/Hz) 148 147 146 -40C +25C +85C 144 142 6 9 ATTENUATION SETTING (dB) 12 15 11846-072 143 3 -50 -55 -60 -65 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 6.0 Figure 73. Tx Single Sideband (SSB) Rejection vs. Frequency, 7 MHz Offset 149 0 ATT 0, +85C ATT 25, +85C ATT 50, +85C -45 FREQUENCY (GHz) 150 145 ATT 0, +25C ATT 25, +25C ATT 50, +25C -40 -70 5.0 11846-071 0 ATT 0, -40C ATT 25, -40C ATT 50, -40C -35 11846-073 Tx SINGLE SIDEBAND AMPLITUDE (dBc) -30 Figure 72. Tx Signal-to-Noise Ratio (SNR) vs. Transmitter Attenuation Setting, WiMAX 40 MHz Signal of Interest with Noise Measured at 90 MHz Offset, fLO_TX = 5.745 GHz Rev. C | Page 27 of 32 AD9364 Data Sheet THEORY OF OPERATION GENERAL TRANSMITTER The AD9364 is a highly integrated radio frequency (RF) transceiver capable of being configured for a wide range of applications. The device integrates all RF, mixed signal, and digital blocks necessary to provide all transceiver functions in a single device. Programmability allows this broadband transceiver to be adapted for use with multiple communication standards, including frequency division duplex (FDD) and time division duplex (TDD) systems. This programmability also allows the device to be interfaced to various baseband processors (BBPs) using a single 12-bit parallel data port, dual 12-bit parallel data ports, or a 12-bit low voltage differential signaling (LVDS) interface. The transmitter section consists of two differential output stages that can be multiplexed to the transmit channel. The transmit channel provides all digital processing, mixed signal, and RF blocks necessary to implement a direct conversion system. The digital data received from the BBP passes through a fully programmable 128-tap FIR filter with interpolation options. The FIR output is sent to a series of interpolation filters that provide additional filtering and data rate interpolation prior to reaching the DAC. Each 12-bit DAC has an adjustable sampling rate. Both the I and Q channels are fed to the RF block for upconversion. The AD9364 also provides self calibration and automatic gain control (AGC) systems to maintain a high performance level under varying temperatures and input signal conditions. In addition, the device includes several test modes that allow system designers to insert test tones and create internal loopback modes that can be used by designers to debug their designs during prototyping and optimize their radio configuration for a specific application. RECEIVER The receiver section contains all blocks necessary to receive RF signals and convert them to digital data that is usable by a BBP. It has three inputs that can be multiplexed to the signal chain, making the AD9364 suitable for use in multiband systems with multiple antenna inputs. The receiver is a direct conversion system that contains a low noise amplifier (LNA), followed by matched in-phase (I) and quadrature (Q) amplifiers, mixers, and band shaping filters that downconvert received signals to baseband for digitization. External LNAs can also be interfaced to the device, allowing designers the flexibility to customize the receiver front end for their specific application. Gain control is achieved by following a preprogrammed gain index map that distributes gain among the blocks for optimal performance at each level. This can be achieved by enabling the internal AGC in either fast or slow mode or by using manual gain control, allowing the BBP to make the gain adjustments as needed. Additionally, each channel contains independent RSSI measurement capability, dc offset tracking, and all circuitry necessary for self calibration. The receiver includes 12-bit, - ADCs and adjustable sample rates that produce data streams from the received signals. The digitized signals can be conditioned further by a series of decimation filters and a fully programmable 128-tap FIR filter with additional decimation settings. The sample rate of each digital filter block is adjustable by changing decimation factors to produce the desired output data rate. When converted to baseband analog signals, the I and Q signals are filtered to remove sampling artifacts and fed to the upconversion mixers. At this point, the I and Q signals are recombined and modulated on the carrier frequency for transmission to the output stage. The combined signal also passes through analog filters that provide additional band shaping, and then the signal is transmitted to the output amplifier. The transmit channel provides a wide attenuation adjustment range with fine granularity to help designers optimize signal-to-noise ratio (SNR). Self calibration circuitry is built into each transmit channel to provide automatic real-time adjustment. The transmitter block also provides a Tx monitor block. This block monitors the transmitter output and routes it back through the receiver channel to the BBP for signal monitoring. The Tx monitor block is available only in TDD mode operation while the receiver is idle. CLOCK INPUT OPTIONS The AD9364 operates using a reference clock that can be provided by two different sources. The first option is to use a dedicated crystal with a frequency between 19 MHz and 50 MHz connected between the XTALP and XTALN pins. The second option is to connect an external oscillator or clock distribution device (such as the AD9548) to the XTALN pin (with the XTALP pin remaining unconnected). If an external oscillator is used, the frequency can vary between 10 MHz and 80 MHz. This reference clock is used to supply the synthesizer blocks that generate all data clocks, sample clocks, and local oscillators inside the device. Errors in the crystal frequency can be removed by using the digitally programmable digitally controlled crystal oscillator (DCXO) function to adjust an on-chip variable capacitor. This capacitor can tune the crystal frequency variance out of the system, resulting in a more accurate reference clock from which all other frequency signals are generated. This function can also be used with on-chip temperature sensing to provide oscillator frequency temperature compensation during normal operation. Rev. C | Page 28 of 32 Data Sheet AD9364 SYNTHESIZERS RX_FRAME Signal RF PLLs The device generates an RX_FRAME output signal whenever the receiver outputs valid data. This signal has two modes: level mode (RX_FRAME stays high as long as the data is valid) and pulse mode (RX_FRAME pulses with a 50% duty cycle). Similarly, the BBP must provide a TX_FRAME signal that indicates the beginning of a valid data transmission with a rising edge. Similar to the RX_FRAME signal, the TX_FRAME signal can remain high throughout the burst or it can be pulsed with a 50% duty cycle. The AD9364 contains two identical synthesizers to generate the required LO signals for the RF signal paths--one for the receiver and one for the transmitter. Phase-locked loop (PLL) synthesizers are fractional-N designs incorporating completely integrated voltage controlled oscillators (VCOs) and loop filters. In TDD mode, the synthesizers turn on and off as appropriate for the Rx and Tx frames. In FDD mode, the Tx PLL and the Rx PLL can be activated at the same time. These PLLs require no external components. BB PLL The AD9364 also contains a baseband PLL (BB PLL) synthesizer that is used to generate all baseband related clock signals. These include the ADC and DAC sampling clocks, the DATA_CLK signal (see the Digital Data Interface section), and all data framing signals. This PLL is programmed from 700 MHz to 1400 MHz based on the data rate and sample rate requirements of the system. DIGITAL DATA INTERFACE The AD9364 data interface uses parallel data ports (P0 and P1) to transfer data between the device and the BBP. The data ports can be configured in either single-ended CMOS format or differential LVDS format. Both formats can be configured in multiple arrangements to match system requirements for data ordering and data port connections. These arrangements include single port data bus, dual port data bus, single data rate, and double data rate. Bus transfers are controlled using simple hardware handshake signaling. The two ports can be operated in either bidirectional (half-duplex) mode or in full duplex mode where half the bits are used for transmitting data and half are used for receiving data. The interface can also be configured to use only one of the data ports for applications that do not require high data rates and prefer to use fewer interface pins. DATA_CLK Signal The AD9364 supplies the DATA_CLK signal that the BBP uses when receiving the data. The DATA_CLK signal can be set to a rate that provides single data rate (SDR) timing where data is sampled on each rising clock edge, or it can be set to provide double data rate (DDR) timing where data is captured on both rising and falling edges. SDR or DDR timing applies to operation using either a single port or both ports. FB_CLK Signal For transmit data, the interface uses the FB_CLK signal as the timing reference. FB_CLK allows source synchronous timing with rising edge capture for burst control signals and either rising edge (SDR mode) or both edge capture (DDR mode) for transmit signal bursts. The FB_CLK signal must have the same frequency and duty cycle as DATA_CLK. ENABLE STATE MACHINE The AD9364 transceiver includes an enable state machine (ENSM) that allows real-time control over the current state of the device. The device can be placed in several different states during normal operation, including * * * * * * Wait--power save, synthesizers disabled Sleep--wait with all clocks/BB PLL disabled Tx--Tx signal chain enabled Rx--Rx signal chain enabled FDD--Tx and Rx signal chains enabled Alert--synthesizers enabled The ENSM has two possible control methods: SPI control and pin control. SPI Control Mode In SPI control mode, the ENSM is controlled asynchronously by writing SPI registers to advance the current state to the next state. SPI control is considered asynchronous to the DATA_CLK because the SPI_CLK can be derived from a different clock reference and can still function properly. The SPI control ENSM method is recommended when real-time control of the synthesizers is not necessary. SPI control can be used for realtime control as long as the BBP has the ability to perform timed SPI writes accurately. Pin Control Mode In pin control mode, the enable function of the ENABLE pin and the TXNRX pin allow real-time control of the current state. The ENSM allows TDD or FDD operation depending on the configuration of the corresponding SPI register. The ENABLE and TXNRX pin control method is recommended if the BBP has extra control outputs that can be controlled in real time, allowing a simple 2-wire interface to control the state of the device. To advance the current state of the ENSM to the next state, the enable function of the ENABLE pin can be driven by either a pulse (edge detected internally) or a level. When a pulse is used, it must have a minimum pulse width of one FB_CLK cycle. In level mode, the ENABLE and TXNRX pins are also edge detected by the AD9364 and must meet the same minimum pulse width requirement of one FB_CLK cycle. In FDD mode, the ENABLE and TXNRX pins can be remapped to serve as real-time Rx and Tx data transfer control signals. In this mode, the enable function of the ENABLE pin assumes the RXON Rev. C | Page 29 of 32 AD9364 Data Sheet function (controlling when the Rx path is enabled and disabled), and the TXNRX pin assumes the TXON function (controlling when the Tx path is enabled and disabled). In this mode, the ENSM is removed from the system for control of all data flow by these pins. SPI INTERFACE The AD9364 uses a serial peripheral interface (SPI) to communicate with the BBP. The SPI can be configured as a 4-wire interface with dedicated receive and transmit ports, or it can be configured as a 3-wire interface with a bidirectional data communication port. This bus allows the BBP to set all device control parameters using a simple address data serial bus protocol. AUXILIARY CONVERTERS AUXADC The AD9364 contains an auxiliary ADC that can be used to monitor system functions such as temperature or power output. The converter is 12 bits wide and has an input range of 0.05 V to VDDA1P3_BB - 0.05 V. When enabled, the ADC is free running. SPI reads provide the last value latched at the ADC output. A multiplexer in front of the ADC allows the user to select between the AUXADC input pin and a built-in temperature sensor. AUXDAC1 and AUXDAC2 The AD9364 contains two identical auxiliary DACs that can provide power amplifier (PA) bias or other system functionality. The auxiliary DACs are 10 bits wide, have an output voltage range of 0.5 V to VDD_GPO - 0.3 V, a current drive of 10 mA, and can be directly controlled by the internal enable state machine. Write commands follow a 24-bit format. The first six bits are used to set the bus direction and number of bytes to transfer. The next 10 bits set the address where data is to be written. The final eight bits are the data to be transferred to the specified register address (MSB to LSB). The AD9364 also supports an LSB-first format that allows the commands to be written in LSB to MSB format. In this mode, the register addresses are incremented for multibyte writes. The AD9364 must be powered by the following three supplies: the analog supply (VDDD1P3_DIG/VDDAx = 1.3 V), the interface supply (VDD_INTERFACE = 1.8 V), and the GPO supply (VDD_GPO = 3.3 V). Read commands follow a similar format with the exception that the first 16 bits are transferred on the SPI_DI pin and the final eight bits are read from the AD9364, either on the SPI_DO pin in 4-wire mode or on the SPI_DI pin in 3-wire mode. For applications requiring optimal noise performance, it is recommended that the 1.3 V analog supply be split and sourced from low noise, low dropout (LDO) regulators. Figure 74 shows the recommended method. POWERING THE AD9364 3.3V CONTROL PINS ADP2164 ADP1755 1.3V_A ADP1755 1.3V_B Figure 74. Low Noise Power Solution for the AD9364 For applications where board space is at a premium, and optimal noise performance is not an absolute requirement, the 1.3 V analog rail can be provided directly from a switcher, and a more integrated power management unit (PMU) approach can be adopted. Figure 75 shows this approach. Control Inputs (CTRL_IN3 to CTRL_IN0) ADP5040 The AD9364 provides four edge detected control input pins. In manual gain mode, the BBP can use these pins to change the gain table index in real time. In transmit mode, the BBP can use two of the pins to change the transmit gain in real time. GPO PINS (GPO_3 TO GPO_0) The AD9364 provides four, 3.3 V capable general-purpose logic output pins: GPO_3, GPO_2, GPO_1, and GPO_0. These pins can be used to control other peripheral devices such as regulators and switches via the AD9364 SPI bus, or they can function as slaves for the internal AD9364 state machine. Rev. C | Page 30 of 32 1.2A BUCK ADP1755 1.3V LDO VDDD1P3_DIG/VDDAx AD9364 300mA LDO 1.8V 300mA LDO 3.3V VDD_INTERFACE VDD_GPO Figure 75. Space-Optimized Power Solution for the AD9364 11846-075 The AD9364 provides eight simultaneous real-time output signals for use as interrupts to the BBP. These outputs can be configured to output a number of internal settings and measurements that the BBP can use when monitoring transceiver performance in different situations. The control output pointer register selects what information is output to these pins, and the control output enable register determines which signals are activated for monitoring by the BBP. Signals used for manual gain mode, calibration flags, state machine states, and the ADC output are among the outputs that can be monitored on these pins. 1.8V 11846-074 Control Outputs (CTRL_OUT7 to CTRL_OUT0) Data Sheet AD9364 PACKAGING AND ORDERING INFORMATION OUTLINE DIMENSIONS A1 BALL CORNER 10.10 10.00 SQ 9.90 A1 BALL CORNER 12 11 10 9 8 7 6 5 4 3 2 1 A B C D 8.80 SQ E F G H 0.80 J K L M TOP VIEW 0.60 REF BOTTOM VIEW DETAIL A 1.70 MAX DETAIL A 1.00 MIN 0.32 MIN COMPLIANT TO JEDEC STANDARDS MO-275-EEAB-1. 11-18-2011-A 0.50 COPLANARITY 0.45 0.12 0.40 BALL DIAMETER SEATING PLANE Figure 76. 144-Ball Chip Scale Package Ball Grid Array [CSP_BGA] (BC-144-7) Dimensions shown in millimeters ORDERING GUIDE Model1 AD9364BBCZ AD9364BBCZREEL 1 Temperature Range -40C to +85C -40C to +85C Package Description 144-Ball CSP_BGA 144-Ball CSP_BGA Z = RoHS Compliant Part. Rev. C | Page 31 of 32 Package Option BC-144-7 BC-144-7 AD9364 Data Sheet NOTES (c)2013-2014 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D11846-0-7/14(C) Rev. C | Page 32 of 32