FDB060AN08A0 / FDP060AN08A0 Rev. C2©2002 Fairchild Semiconductor Corporation
November 2002
FDB060AN08A0 / FDP060AN08A0
FDB060AN08A0 / FDP060AN 08A0
N-Channel PowerTrench® MOSFET
75V, 80A, 6.0mΩ
Features
•r
DS(ON) = 4.8mΩ (Typ.), VGS = 10 V, ID = 80A
•Q
g(tot) = 73 nC (Typ.), VGS = 10V
• Low Miller Charge
•Low Q
RR Body Diode
• UIS Capability (Single Pulse and Repetitive Pulse)
Formerly developmental type 82680
Applications
• E le c tr on ic Valve Tr ai n Sys tem s
• DC-DC conv erters and Off-line UPS
• Distri buted Power Architectures and VRMs
• Primary Switch for 24V and 48V systems
MOSFET Maximu m Ratings TC = 25°C unless otherwise no ted
Thermal Characteristics
Reliability data can be found at: http://www.fairchildsemi.com/products/discrete/reliability/index.html.
Symbol Parameter Ratings Units
VDSS Drai n t o Sou r c e Vo lta ge 75 V
VGS Gate to Sourc e Vo lta ge ±20 V
ID
Drain Cur rent 80 A
Continuous (TC < 127oC, VGS = 10V)
Continuous (Tamb = 25oC, VGS = 10V, with RθJA = 43oC/W) 16 A
Pulsed Figure 4 A
EAS Single Pulse Av alanche Energ y (Note 1) 350 mJ
PDPow er dissipation 255 W
Derate above 25oC1.7W/
oC
TJ, TSTG Operating and Storage Temperature -55 to 175 oC
RθJC Thermal Resistance Junction to Case TO-220,TO-263 0.58 oC/W
RθJA Thermal Resista nce Junc tio n to Ambient TO-220,TO-263 (N ote 2) 62 oC/W
RθJA Thermal Resist ance J unction to Ambient TO-263, 1in2 copp er pad a rea 43 oC/W
D
G
S
TO-263AB
FDB SERIES
GATE
SOURCE DRAIN
(FLANGE)
TO-220AB
FDP SERIES
DRAIN
DRAIN
GATE
SOURCE
(FLANGE)
FDB060AN08A0 / FDP060AN08A0 Rev. C2©2002 Fairchild Semic onductor Corporation
FDB060AN08A0 / FDP060AN08A0
Package Marking and Ordering Informatio n
Electrical Characteristics TC = 25°C unless otherwise noted
Off Characteri stics
On Characteristics
Dynamic Characteristic s
Switching Characteri stics (VGS = 10V )
Drain-Source Diode Character istics
Notes:
1: Starting TJ = 25°C, L = 109µH, IAS = 80A.
2: Pulse width = 100s
Device Marking Device Package Reel Size Tape Width Quantity
FDB060AN 08A0 FDB060AN0 8A0 TO-263AB 330mm 24mm 800 units
FDP060AN08A0 FDP060AN08A0 TO-220AB Tube N/A 50 units
Symbol Param eter Test Con ditions Min Typ Max Unit s
BVDSS Drain to S ou rc e B rea k dow n Voltag e I D = 250µA, VGS = 0V 75 - - V
IDSS Zero Gate Voltage Drain Current VDS = 60V - - 1 µA
VGS = 0V TC = 150oC- -250
IGSS Gate to Source Leakage Current VGS = ±20V - - ±100 nA
VGS(TH) Gate to Source Threshold Voltage VGS = VDS, ID = 250µA2-4V
rDS(ON) D r ai n to S ou r c e On Re si stan ce
ID = 80A, VGS = 10V - 0.0048 0.006
Ω
ID = 40A, VGS = 6V - 0.0066 0.010
ID = 80A, VGS = 10V,
TJ = 1 75 oC- 0.010 0.013
CISS Input Capacitance VDS = 25V, VGS = 0V,
f = 1MHz
- 5150 - pF
COSS Out put Capacitance - 800 - pF
CRSS Reverse Transfer Capacitance - 230 - pF
Qg(TOT) Total Gate Charge at 10V VGS = 0V to 10V
VDD = 40V
ID = 80A
Ig = 1.0mA
73 95 nC
Qg(TH) Threshold Gate Charge VGS = 0V to 2V - 10 13 nC
Qgs Ga te to Sourc e Gate Charg e - 29 - nC
Qgs2 Gate Charge Threshold to Plateau - 19 - nC
Qgd Gate to Drain “Miller” Charge - 16 - nC
tON Turn-On Time
VDD = 40V, ID = 80A
VGS = 10V, RGS = 3.9Ω
--147ns
td(ON) Turn-On Delay Time - 19 - ns
trRise Time - 79 - ns
td(OFF) Turn-Off Delay Time - 37 - ns
tfFall Time - 38 - ns
tOFF Turn-O f f Time - - 113 ns
VSD Source to Drain Diode Voltage ISD = 80A - - 1.2 5 V
ISD = 40A - - 1.0 V
trr Reverse Recovery Time ISD = 75A, dISD/dt = 100A/µs- -37ns
QRR Reverse Recovered Charge ISD = 75A, dISD/dt = 100A/µs- -38nC
FDB060AN08A0 / FDP060AN08A0 Rev. C2©2002 Fairchild Semic onductor Corporation
FDB060AN08A0 / FDP060AN08A0
Typical Characteristics TC = 25°C unless otherwis e noted
Figure 1. Normalized Powe r Dissipation vs
Ambient Temperature Figure 2. Maxi mum Continuous Drai n Current vs
Case Temperature
Figure 3. Normalized M aximum Transient Thermal Impedance
Figure 4. Peak Current Capability
TC, CASE TEMPERATURE (oC)
POWER DISSIPATION MULTIPLIER
00255075100 175
0.2
0.4
0.6
0.8
1.0
1.2
125 150 0
25
50
75
100
125
150
25 50 75 100 125 150 175
ID, DRAIN CURRENT (A)
TC, CASE TEMPERATURE (oC)
CURRENT LIMITED
BY PACKAGE
0.1
1
10-5 10-4 10-3 10-2 10-1 100101
0.01
2
t, RECTANGULAR PULSE DURATION (s)
ZθJC, NORMALIZED
THERMAL IMPEDANCE
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC x RθJC + TC
PDM
t1t2
0.5
0.2
0.1
0.05
0.01
0.02
DUTY CYCLE - DESCENDING ORDER
SINGLE PULSE
100
1000
2000
70
IDM, PEAK CURRENT (A)
t, PULSE WIDTH (s)
10-5 10-4 10-3 10-2 10-1 100101
TC = 25oC
I = I25 175 - TC
150
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
VGS = 10V
FDB060AN08A0 / FDP060AN08A0 Rev. C2©2002 Fairchild Semic onductor Corporation
FDB060AN08A0 / FDP060AN08A0
Figure 5. Forward Bias Safe Oper ating Area NOTE: Refer to Fairchild Application Notes AN7514 and AN7515
Figure 6. Unclamped Inductive Switching
Capability
Figure 7. Transfer Characterist ics Figure 8. Sa turation Characteris tics
Figur e 9 . Dr ain t o So urce On Resis tance v s Dr ain
Current Figure 10. Normalized Drain to Source On
Resistance vs Junction Temperature
Typical Characteristics TC = 25°C unless otherwis e noted
0.1
1
10
100
1000
110100
VDS, DRAIN TO SOURCE VOLTAGE (V)
ID, DRAIN CURRENT (A)
TJ = MAX RATED
TC = 25oC
SINGLE PULSE
LIMITED BY rDS(ON)
AREA MAY BE
OPERATION IN THIS
10µs
1ms
DC
100µs
10ms
1
10
100
0.01 0.1 1 10 100
500
IAS, AVALANCHE CURRENT (A)
tAV, TIME IN AVALANCHE (ms)
STARTING TJ = 25oC
STARTING TJ = 150oC
tAV = (L)( IAS)/(1.3*RATED BVDSS - VDD)
If R = 0
If R ≠ 0
tAV = (L/R)ln[(IAS*R)/(1.3 *RATED BVDSS - VDD) +1]
0
25
50
75
100
125
150
175
3.5 4.0 4.5 5.0 5.5 6.0
ID, DRAIN CURRENT (A)
VGS, GATE TO SOURCE VOLTAGE (V)
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDD = 15V
TJ = 175oC
TJ = 25oC TJ = -55oC
0
25
50
75
100
125
150
175
0 0.5 1.0 1.5 2.0
ID, DRAIN CURRENT (A)
VDS, DRAIN TO SOURCE VOLTAGE (V)
VGS = 6V
PULSE DURATIO N = 80µs
DUTY CYCLE = 0.5% MAX
VGS = 5V
TC = 25oC
VGS = 10V VGS = 7V
4.0
4.5
5.0
5.5
6.0
6.5
7.0
7.5
0 20406080
ID, DRAIN CURRENT (A)
VGS = 6V
VGS = 10V
DRAIN TO SOURCE ON RESISTANCE(mΩ)
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
0.5
1.0
1.5
2.0
2.5
-80 -40 0 40 80 120 160 200
NORMALIZED DRAIN TO SOURCE
TJ, JUNCTION TEMPERATURE (oC)
ON RESISTANCE
VGS = 10V, ID = 80A
PULSE DURATIO N = 80µs
DUTY CYCLE = 0.5% MAX
FDB060AN08A0 / FDP060AN08A0 Rev. C2©2002 Fairchild Semic onductor Corporation
FDB060AN08A0 / FDP060AN08A0
Figur e 11. Normalized Gate Threshol d Voltage vs
Junction Temper ature Figure 12. Normalized Drain to Source
Breakdown Voltage vs Junction Temperature
Figure 13. Capacitance vs Drain to Sour ce
Voltage Figure 14. Gate Charge W aveforms for Constant
Gate Current
Typical Characteristics TC = 25°C unless otherwis e noted
0.4
0.6
0.8
1.0
1.2
-80 -40 0 40 80 120 160 200
VGS = VDS, ID = 250µA
NORMALIZED GATE
TJ, JUNCTION TEMPERATURE (oC)
THRESHOLD VOLTAGE
0.9
1.0
1.1
1.2
-80 -40 0 40 80 120 160 200
TJ, JUNCTION TEMPERATURE (oC)
NORMALIZED DRAIN TO SOURCE
ID = 250µA
BREAKDOWN VOLTAGE
100
1000
0.1 1 10
7000
75
C, CAPACITANCE (pF)
VDS, DRAIN TO SOURCE VOLTAGE (V)
VGS = 0V, f = 1MHz
CISS = CGS + CGD
COSS ≅ CDS + CGD
CRSS = CGD
0
2
4
6
8
10
0 20406080
VGS, GATE TO SOURCE VOLTAGE (V)
Qg, GATE CHARGE (nC)
VDD = 40V
ID = 80A
ID = 16A
WAVEFORMS IN
DESCENDING ORDER:
FDB060AN08A0 / FDP060AN08A0 Rev. C2©2002 Fairchild Semic onductor Corporation
FDB060AN08A0 / FDP060AN08A0
Test Circuits and Waveforms
Figure 15. Unclamped Energy Test Circui t Figure 16. Unclamped Energy Waveforms
Figure 17. Gate Charge Test Circuit Figure 18. Gate Charge Waveforms
Figure 19. Switching Time Test Circuit Figure 20. Switching Time Waveforms
tP
VGS
0.01Ω
L
IAS
+
-
VDS
VDD
RG
DUT
VARY tP TO OBTAIN
REQUIRED PEAK IAS
0V
VDD
VDS
BVDSS
tP
IAS
tAV
0
VGS +
-
VDS
VDD
DUT
Ig(REF)
L
VDD
Qg(TH)
VGS = 2V
Qgs2
Qg(TOT)
VGS = 10V
VDS VGS
Ig(REF)
0
0
Qgs Qgd
VGS
RL
RGS
DUT
+
-VDD
VDS
VGS
tON
td(ON)
tr
90%
10%
VDS 90%
10%
tf
td(OFF)
tOFF
90%
50%50%
10% PULSE WI DT H
VGS
0
0
FDB060AN08A0 / FDP060AN08A0 Rev. C2©2002 Fairchild Semic onductor Corporation
FDB060AN08A0 / FDP060AN08A0
Thermal Resistance vs. Mounting Pad Area
The maximum rated junction temperature, TJM, and the
thermal resistance of the heat dissipating path determines
the maximum allowable device power dissipation, PDM, in an
application. Therefore the application’s ambient
temperature, TA (oC), and thermal resistance RθJA (oC/W)
must be reviewed to ensure that TJM is never exceeded.
Equation 1 mathematically represents the relationship and
s erve s as the basis for establishing the rating of the part.
In using surface mount devices such as the TO-263
package, the environment in which it is applied will have a
significant influence on the part’s current and maximum
power dissipation ratings. Precise determination of PDM is
c omplex and inf luenced by many facto rs:
1. Mounting pad area onto which the device is attached and
wh ethe r the re is copp er on on e sid e or b oth si des o f the
board.
2. The number of copper layers and the thickness of the
board.
3. The use of external he at sinks.
4. The use of thermal vias.
5. Ai r flow and board orientation.
6. For non steady state applications, the pulse width, the
duty cycle and the transi ent ther mal respon se of the part,
the board and the environment they are i n.
Fairchild provides thermal information to assist the
designer’s preliminary application evaluation. Figure 21
defines the RθJA for the device as a function of the top
copper (component side) area. This is for a horizontally
position ed FR -4 board with 1 oz c opp er af t er 100 0 sec on ds
of stea dy st ate powe r w ith n o air flow . Th is gr aph prov ides
the necessary information for calculation o f th e steady state
junction temperature or power dissipation. Pulse
applications can be evaluated using the Fairchild device
Spice thermal model or manually utilizing the normalized
maximum transient thermal impedance curve.
Thermal resistances corresponding to other copper areas
can be obtained from Figure 21 or by calculation using
Equation 2 or 3. Equation 2 is used for copper area defined
in in ches square and equation 3 is for area in centimet ers
square. The area, in square inches or square centimeters is
the top copper ar ea including the gate and source pads.
(EQ. 1)
PDM
TJM TA
–()
RθJA
-----------------------------=
Area in Inches Squared
(EQ. 2)
RθJA 26.51 19.84
0.262 Area+()
-------------------------------------+
=
(EQ. 3)
RθJA 26.51 128
1.69 Area+()
----------------------------------+
=
Area in Centimeters Squared
Figure 21. Thermal Resistance vs Mounting
Pad Area
20
40
60
80
1100.1
RθJA = 26.51+ 19.84/(0.262+Area) EQ.2
RθJA (oC/W)
AREA, TOP COPPER AREA in2 (cm2)
(0.645) (6.45) (64.5)
RθJA = 26.51+ 128/(1.69+Area) EQ.3
FDB060AN08A0 / FDP060AN08A0 Rev. C2©2002 Fairchild Semic onductor Corporation
FDB060AN08A0 / FDP060AN08A0
PSPICE Electr ical Model
.SU BC K T F DP060AN08A0 2 1 3 ; rev October 200 2
Ca 1 2 8 2. 5e-9
Cb 1 5 14 2. 1e-9
Cin 6 8 4.7e-9
D bo dy 7 5 Dbod yMOD
Dbreak 5 11 D break MOD
Dplc ap 10 5 Dplcap M O D
Ebreak 11 7 17 18 82.1
Ed s 14 8 5 8 1
Eg s 13 8 6 8 1
Esg 6 10 6 8 1
Evthres 6 21 19 8 1
Evtem p 20 6 18 22 1
It 8 17 1
Lgate 1 9 5.3e- 9
Ldrai n 2 5 1.0e -9
Ls o urce 3 7 5e -9
RLgate 1 9 53
R Ld rain 2 5 10
RLsourc e 3 7 50
Mm e d 16 6 8 8 M medMOD
Mstro 16 6 8 8 MstroM OD
Mwe ak 16 21 8 8 MweakMO D
Rbreak 17 18 Rbreak M O D 1
Rdrain 50 16 RdrainMOD 9e-4
Rgate 9 20 1.4
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
Rsource 8 7 RsourceMOD 3e-3
Rvthre s 22 8 RvthresMOD 1
Rvtemp 18 19 RvtempMOD 1
S1a 6 12 13 8 S1AMOD
S1b 13 12 13 8 S1B M OD
S2a 6 15 14 13 S2A M OD
S2b 13 15 14 13 S2B M OD
Vbat 22 19 DC 1
ESL C 51 50 VALUE = {(V(5,5 1)/AB S(V(5, 51)))*(PWR(V (5,51 )/ (1e-6*350),5))}
.MODEL DbodyMOD D (IS=2E-11 N=1.04 RS=1.76e-3 TRS1=2.7e-3 TRS2=1e-6
+ CJO=3. 2e-9 M= 5.6e-1 TT= 3e-10 XT I=3.9)
.MO DE L DbreakMOD D (RS=3e-1 TRS 1=1e-3 TRS2=-8.9e-6)
.MODEL DplcapMOD D (CJO=1.56e-9 IS=1e-30 N=10 M=0.53)
.MODEL MmedMOD NMOS (VTO=3.6 KP=6 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=1.4)
.MO DE L Mst roMOD NMOS (VTO=4.22 K P = 220 IS=1e -30 N=10 T OX = 1 L=1u W=1u )
.MODEL MweakMOD NMOS (VTO=3 KP=0.03 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=14 RS=0.1)
.MODEL RbreakMOD RES (TC1=9.4e-4 TC2=-9e-7)
.MO DE L RdrainMOD RES (TC1=2. 2e-2 TC2=6e -5)
.MODEL RSLCMOD RES (TC1=2e-3 TC2=1e-5)
.MO DE L Rsou rceMOD RES (TC1=1e-3 TC 2=1e-6 )
.MO DEL Rvthre sM OD RE S (T C1=-6e-3 TC2=-1 .6e-5 )
.MO DE L Rvte m pM OD RE S (T C1=-2. 4e-3 TC2=1e -6)
.M ODEL S1AMOD VSWITC H (RON= 1e- 5 ROFF =0. 1 VON=- 8 VOF F=-5 )
.M ODEL S1BMOD VSWITC H (RON= 1e- 5 ROFF =0. 1 VON=- 5 VOF F=-8 )
.M ODEL S2AMOD VSWITC H (RON= 1e- 5 ROFF = 0.1 VON= - 4 VOFF =-3 .5 )
.M ODEL S2BMOD VSWITC H (RON= 1e- 5 ROFF =0. 1 VON=- 3. 5 VOF F=-4 )
.ENDS
Note: For further discussion of the PSPICE model, consult A N ew PSPICE Sub-Circuit for the Power MOSFET Featuring G lobal
Temperature Options; IE EE P ower E le ct ronics Spec i a l i st Conference Records, 1991, wri tten by William J. Hepp and C. F rank
Wheatley.
18
22
+-
6
8
+
-
5
51
+
-
19
8
+-
17
18
6
8
+
-
5
8+
-
RBREAK
RVTEMP
VBAT
RVTHRES
IT
17 18
19
22
12
13
15
S1A
S1B
S2A
S2B
CA CB
EGS EDS
14
8
13
814
13
MWEAK
EBREAK DBODY
RSOURCE
SOURCE
11
73
LSOURCE
RLSOURCE
CIN
RDRAIN
EVTHRES 16
21
8
MMED
MSTRO
DRAIN
2
LDRAIN
RLDRAIN
DBREAK
DPLCAP
ESLC
RSLC1
10
5
51
50
RSLC2
1
GATE RGATE EVTEMP
9
ESG
LGATE
RLGATE 20
+
-
+
-
+
-
6
FDB060AN08A0 / FDP060AN08A0 Rev. C2©2002 Fairchild Semic onductor Corporation
FDB060AN08A0 / FDP060AN08A0
SABER Electrical Model
rev October 2002
tem pl ate FDP060AN08A 0 n2,n1 ,n 3
electrical n2,n1,n3
{
var i iscl
dp..model dbodymod = (isl=2e-11,nl=1.04,rs=1.76e-3,trs1=2.7e-3,trs2=1e-6,cjo=3.2e-9,m=5.6e-1,tt=3e-10,xti=3.9)
dp.. m odel dbreakmo d = (rs=3e -1, trs1=1e-3 ,t rs 2=-8. 9e-6)
dp..model dplcapmod = (cjo=1.56e-9,isl=10e-30,nl=10,m=0.53)
m..model mmedmod = (type=_n,vto=3.6,kp=6,is=1e-30, tox=1)
m..model mstrongmod = (type=_n,vto=4.22,kp=220,is=1e-30, tox=1)
m..model mweakmod = (type=_n,vto=3,kp=0.03,is=1e-30, tox=1,rs=0.1)
sw_v cs p..mo del s1amod = (ron= 1e-5,roff=0. 1,von=-8,vof f=-5 )
sw_v cs p..mo del s1bmod = (ron= 1e-5,roff=0. 1,von=-5,vof f=-8 )
sw_v cs p..mo del s2amod = (ron= 1e-5,roff=0. 1,von=-4,vof f=-3 .5)
sw_v cs p..mo del s2bmod = (ron= 1e-5,roff=0. 1,von=-3.5,voff =-4)
c . ca n1 2 n8 = 2.5e -9
c.cb n15 n14 = 2. 1e-9
c.c in n6 n8 = 4.7e -9
dp.dbody n7 n5 = model =dbody m od
dp.dbrea k n5 n11 = model=dbr eakmod
dp.dplca p n10 n5 = model =dplcapmod
spe. ebreak n11 n7 n17 n1 8 = 82.1
spe. eds n14 n8 n5 n8 = 1
spe. egs n13 n8 n6 n8 = 1
spe. esg n6 n10 n6 n8 = 1
spe.evthres n6 n21 n19 n8 = 1
spe. evtemp n20 n6 n18 n2 2 = 1
i.it n8 n17 = 1
l.lg ate n1 n9 = 5.3e-9
l.ldrain n2 n5 = 1.0e-9
l.lsource n3 n7 = 5e-9
res. rl gate n1 n9 = 53
res. rl drain n2 n5 = 10
res. rl sour ce n3 n7 = 50
m.mmed n16 n6 n8 n8 = m odel=m m edmod, l=1u, w=1u
m.ms t rong n16 n6 n8 n8 = mod el = m strongmod, l= 1u, w=1u
m.mw eak n16 n21 n8 n8 = model=m wea kmod, l=1u, w=1u
res. rbreak n17 n18 = 1, tc1 = 9. 4e-4,tc 2=-9e-7
res. rdrain n50 n16 = 9e-4, tc1=2 .2e-2 ,tc2=6e -5
r e s .rgat e n9 n2 0 = 1. 4
res. rslc1 n5 n51 = 1e-6, tc1 =2e-3,tc2= 1e-5
res. rslc2 n5 n50 = 1e3
res. rsour ce n8 n7 = 3e-3 , tc1=1e- 3,tc2=1e- 6
res. rvthres n22 n8 = 1, tc1=-6e- 3,tc2=-1.6e-5
res.rvtemp n18 n19 = 1, tc1=-2.4e-3,tc2=1e-6
sw_v cs p.s1a n6 n12 n13 n8 = mo del =s1a m od
sw_v cs p.s1b n13 n12 n1 3 n8 = model = s1 bmod
sw_v cs p.s2a n6 n15 n14 n13 = mode l = s2 amod
sw_v cs p.s2b n13 n15 n1 4 n13 = model = s 2bmod
v.vbat n22 n19 = dc =1
equations {
i (n51->n50) +=iscl
iscl : v (n51, n50) = ((v(n5, n51)/(1e-9+abs(v(n5 ,n51))))*((abs(v(n5 ,n51)* 1e6/ 350))** 5))
}
}
18
22
+-
6
8
+
-
19
8
+-
17
18
6
8
+
-
5
8+
-
RBREAK
RVTEMP
VBAT
RVTHRES
IT
17 18
19
22
12
13
15
S1A
S1B
S2A
S2B
CA CB
EGS EDS
14
8
13
814
13
MWEAK
EBREAK
DBODY
RSOURCE
SOURCE
11
73
LSOURCE
RLSOURCE
CIN
RDRAIN
EVTHRES 16
21
8
MMED
MSTRO
DRAIN
2
LDRAIN
RLDRAIN
DBREAK
DPLCAP
ISCL
RSLC1
10
5
51
50
RSLC2
1
GATE RGATE EVTEMP
9
ESG
LGATE
RLGATE 20
+
-
+
-
+
-
6
FDB060AN08A0 / FDP060AN08A0 Rev. C2©2002 Fairchild Semic onductor Corporation
FDB060AN08A0 / FDP060AN08A0
PSPICE Thermal Model
REV 23 October 2002
FDP060AN08A0T
CTHERM1 TH 6 9.6e-3
CTH ERM2 6 5 9. 7e-3
CTH ERM3 5 4 9. 8e-3
CTH ERM4 4 3 1e-2
CTH ERM5 3 2 3e-2
CTH ERM6 2 TL 9e-2
RTHERM1 TH 6 3.2e-3
RTH ERM2 6 5 8. 1e-3
RTH ERM3 5 4 2. 3e-2
RTH ERM4 4 3 1. 2e-1
RTH ERM5 3 2 1. 5e-1
RTH ERM6 2 TL 1.6e -1
SABER Thermal Mod el
SABE R t hermal m odel F DP060A N08A0T
template thermal_model th tl
the r m al_ c th , tl
{
cth er m.cther m1 th 6 =9.6e -3
ctherm.ctherm2 6 5 =9.7e-3
ctherm.ctherm3 5 4 =9.8e-3
cthe rm .ctherm4 4 3 =1e-2
cthe rm .ctherm5 3 2 =3e-2
ctherm.ctherm6 2 tl =9e-2
rtherm.r th erm 1 th 6 =3 .2e-3
r therm.rthe rm2 6 5 =8. 1 e-3
r therm.rthe rm3 5 4 =2. 3 e-2
r therm.rthe rm4 4 3 =1. 2 e-1
r therm.rthe rm5 3 2 =1. 5 e-1
r the rm .rthe rm6 2 tl =1 . 6 e-1
}
RTHERM4
RTHERM6
RTHERM5
RTHERM3
RTHERM2
RTHERM1
CTHERM4
CTHERM6
CTHERM5
CTHERM3
CTHERM2
CTHERM1
tl
2
3
4
5
6
th JUNCTION
CASE
Rev. I1
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