1
FEATURES
1
2
3
4
8
7
6
5
CLKIN
OE
1Y0
GND
1Y3
1Y2
VDD
1Y1
TSSOP
PW PACKAGE
(TOP VIEW)
DESCRIPTION
3
5
7
8
1Y0
1Y1
1Y2
1Y3
Logic
Control
2
1
OE
CLKIN
CDCV304
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................................................................................................................................................ SCAS643F SEPTEMBER 2000 REVISED APRIL 2009
200-MHz GENERAL-PURPOSE CLOCK BUFFER, PCI-X COMPLIANT
General-Purpose and PCI-X 1:4 Clock BufferOperating Frequency 0 MHz to 200 MHz General-PurposeLow Output Skew: < 100 psDistributes One Clock Input to One Bank ofFour OutputsOutput Enable Control that Drives OutputsLow when OE is LowOperates from Single 3.3-V Supply or 2.5-VSupply
PCI-X Compliant
8-Pin TSSOP Package
The CDCV304 is a high-performance, low-skew, general-purpose PCI-X compliant clock buffer. It distributes oneinput clock signal (CLKIN) to the output clocks (1Y[0:3]). It is specifically designed for use with PCI-Xapplications. The CDCV304 operates at 3.3 V and 2.5 V and is therefore compliant to the 3.3-V PCI-Xspecifications.
The CDCV304 is characterized for operation from 40 ° C to 85 ° C for automotive and industrial applications.
FUNCTIONAL BLOCK DIAGRAM
FUNCTION TABLE
INPUTS OUTPUTS
CLKIN OE 1Y[0:3]
L L LH L LL H LH H H
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2000 2009, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
THERMAL INFORMATION
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
CDCV304
SCAS643F SEPTEMBER 2000 REVISED APRIL 2009 ................................................................................................................................................
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.
TERMINAL FUNCTIONS
TERMINAL
I/O DESCRIPTIONNAME NO.
1Y[0:3] 3, 5, 7, 8 O Buffered output clocksCLKIN 1 I Input reference frequencyGND 4 Power GroundOE 2 I Output enable controlV
DD
6 Power Supply
THERMAL AIR FLOW (CFM)CDCV304PW 8-PIN TSSOP UNIT0 150 250 500
R
θJA
High K 149 142 138 132 ° C/WR
θJA
Low K 230 185 170 150 ° C/WR
θJC
High K 65 ° C/WR
θJC
High K 69 ° C/W
over operating free-air temperature range (unless otherwise noted)
(1)
UNIT
Supply voltage range, V
DD
0.5 V to 4.3 VInput voltage range, V
I
(2) (3)
0.5 V to V
DD
+ 0.5 VOutput voltage range, V
O
(2) (3)
0.5 V to V
DD
+ 0.5 VInput clamp current, I
IK
(V
I
< 0 or V
I
> V
DD
) ± 50 mAOutput clamp current, I
OK
(V
O
< 0 or V
O
> V
DD
) ± 50 mAContinuous total output current, I
O
(V
O
= 0 to V
DD
) ± 50 mAPackage thermal impedance, θ
JA
: PW package 230.5 ° C/WStorage temperature range T
stg
65 ° C to 150 ° C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under recommended operatingconditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed.(3) This value is limited to 4.6 V maximum.
MIN NOM MAX UNIT
Supply voltage, V
DD
2.3 3.6 VLow-level input voltage, V
IL
0.3 x V
DD
VHigh-level input voltage, V
IH
0.7 x V
DD
VInput voltage, V
I
0 V
DD
VV
DD
= 2.5 V 12High-level output current, I
OH
mAV
DD
= 3.3 V 24V
DD
= 2.5 V 12Low-level output current, I
OL
mAV
DD
= 3.3 V 24Operating free-air temperature, T
A
40 85 ° C
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Product Folder Link(s): CDCV304
TIMING REQUIREMENTS
ELECTRICAL CHARACTERISTICS
SWITCHING CHARACTERISTICS
CDCV304
www.ti.com
................................................................................................................................................ SCAS643F SEPTEMBER 2000 REVISED APRIL 2009
over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f
clk
Clock frequency 0 200 MHz
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
V
IK
Input voltage V
DD
= 3 V, I
I
= 18 mA 1.2 VV
DD
= 2.3 V, I
OH
= 8 mA 1.8V
DD
= 2.3 V, I
OH
= 16 mA 1.5V
OH
High-level output voltage V
DD
= min to max, I
OH
= 1 mA V
DD
0.2 VV
DD
= 3 V, I
OH
= 24 mA 2V
DD
= 3 V, I
OH
= 12 mA 2.4V
DD
= 2.3 V, I
OL
= 8 mA 0.5V
DD
= 2.3 V, I
OL
= 16 mA 0.7V
OL
Low-level output voltage V
DD
= min to max, I
OL
= 1 mA 0.2 VV
DD
= 3 V, I
OL
= 24 mA 0.8V
DD
= 3 V, I
OL
= 12 mA 0.55V
DD
= 3 V, V
O
= 1 V 50I
OH
High-level output current mAV
DD
= 3.3 V, V
O
= 1.65 V 55V
DD
= 3 V, V
O
= 2 V 60I
OL
Low-level output current mAV
DD
= 3.3 V, V
O
= 1.65 V 70I
I
Input current V
I
= V
O
or V
DD
± 5 µAf = 67 MHz, V
DD
= 2.7 V 28I
DD
Dynamic current, see Figure 5 mAf = 67 MHz, V
DD
= 3.6 V 37C
I
Input capacitance V
DD
= 3.3 V, V
I
= 0 V or V
DD
3 pFC
O
Output capacitance V
DD
= 3.3 V, V
I
= 0 V or V
DD
3.2 pF
(1) All typical values are with respect to nominal V
DD
and T
A
= 25 ° C.
V
DD
= 2.5 V ± 10%, C
L
= 10 pF (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
t
PLH
Low-to-high propagation delay 2 2.9 4.5See Figure 1 and Figure 2 nst
PHL
High-to-low propagation delay 2 3 4.5t
sk(o)
Output skew
(2)
See Figure 3 50 150 pst
r
Output rise slew rate 1.5 2.2 4 V/nst
f
Output fall slew rate 1.5 2.2 4 V/ns
(1) All typical values are with respect to nominal V
DD
.(2) The t
sk(o)
specification is only valid for equal loading of all outputs.
Copyright © 2000 2009, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Link(s): CDCV304
SWITCHING CHARACTERISTICS
CDCV304
SCAS643F SEPTEMBER 2000 REVISED APRIL 2009 ................................................................................................................................................
www.ti.com
V
DD
= 3.3 V ± 10%, C
L
= 10 pF (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
t
PLH
Low-to-high propagation delay 1.8 2.4 3See Figure 1 and Figure 2 nst
PHL
High-to-low propagation delay 1.8 2.5 3t
sk(o)
Output skew
(2)
50 100 ps12 kHz to 5 MHz, f
out
= 30.72 MHz 63t
jitter
Additive phase jitter from input to output 1Y0 fs rms12 kHz to 20 MHz, f
out
= 125 MHz 56t
sk(p)
Pulse skew V
IH
= V
DD
, V
IL
= 0 V 150 pst
sk(pr)
Process skew 0.2 0.3 nst
sk(pp)
Part-to-part skew 0.25 0.4 ns66 MHz 6t
high
Clock high time, see Figure 4 ns140 MHz 366 MHz 6t
low
Clock low time, see Figure 4 ns140 MHz 3t
r
Output rise slew rate
(3)
V
O
= 0.4 V to 2 V 1.5 2.7 4 V/nst
f
Output fall slew rate
(3)
V
O
= 2 V to 0.4 V 1.5 2.7 4 V/ns
(1) All typical values are with respect to nominal V
DD
.(2) The t
sk(o)
specification is only valid for equal loading of all outputs.(3) This symbol is according to PCI-X terminology.
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Product Folder Link(s): CDCV304
PARAMETER MEASUREMENT INFORMATION
140
Yn
VDD
10 pF
140
0.6 VDD
1Y0 − 1Y3
50% VDD
0.2 VDD
tf
VOL
VOH
tr
CLKIN 0 V
VDD
tPHL
50% VDD
tPLH
0.6 VDD
50% VDD
0.2 VDD
50% VDD
Any Y
Any Y
tsk(0)
50% VDD
thigh
VIH(Min)
Vtest
VIL(Max)
tlow
tcyc
0.4 VDD
Peak to Peak (Minimum)
0.2 VDD
0.6 VDD
PARAMETER VALUE UNIT
VIH(Min)
VIL(Max)
Vtest
0.5 VDD
0.35 VDD
0.4 VDD
V
V
V
CDCV304
www.ti.com
................................................................................................................................................ SCAS643F SEPTEMBER 2000 REVISED APRIL 2009
Figure 1. Test Load Circuit
Figure 2. Voltage Waveforms Propagation Delay (t
pd
) Measurements
Figure 3. Output Skew
A. All parameters in Figure 4 are according to PCI-X 1.0 specifications.
Figure 4. Clock Waveform
Copyright © 2000 2009, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Link(s): CDCV304
f − Frequency − MHz
20
30
40
50
60
0 20 40 60 80 100 120 140 160
TA = 85°C
Output Load: as in Figure 1
ICC − Supply Current − mA
VDD = 2.7V
VDD = 3.6V
IOH − High-Level Output Current − mA
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
−100 −90 −80 −70 −60 −50 −40 −30 −20 −10 0
VDD = 3.3 V
TA = 25°C
VOH − High-Level Output Voltage − V
CDCV304
SCAS643F SEPTEMBER 2000 REVISED APRIL 2009 ................................................................................................................................................
www.ti.com
SUPPLY CURRENT
vsFREQUENCY
Figure 5.
HIGH-LEVEL OUTPUT VOLTAGE
vsHIGH-LEVEL OUTPUT CURRENT
Figure 6.
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Product Folder Link(s): CDCV304
IOL − Low-Level Output Current − mA
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
−20 0 20 40 60 80 100 120
VDD = 3.3 V
TA = 25°C
OL
V− Low-Level Output Voltage − V
CDCV304
www.ti.com
................................................................................................................................................ SCAS643F SEPTEMBER 2000 REVISED APRIL 2009
LOW-LEVEL OUTPUT VOLTAGE
vsLOW-LEVEL OUTPUT CURRENT
Figure 7.
Copyright © 2000 2009, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Link(s): CDCV304
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
CDCV304PW ACTIVE TSSOP PW 8 150 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CDCV304PWG4 ACTIVE TSSOP PW 8 150 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CDCV304PWR ACTIVE TSSOP PW 8 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CDCV304PWRG4 ACTIVE TSSOP PW 8 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 6-Apr-2009
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0 (mm) B0 (mm) K0 (mm) P1
(mm) W
(mm) Pin1
Quadrant
CDCV304PWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 6-Apr-2009
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
CDCV304PWR TSSOP PW 8 2000 346.0 346.0 29.0
PACKAGE MATERIALS INFORMATION
www.ti.com 6-Apr-2009
Pack Materials-Page 2
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,65 M
0,10
0,10
0,25
0,50
0,75
0,15 NOM
Gage Plane
28
9,80
9,60
24
7,90
7,70
2016
6,60
6,40
4040064/F 01/97
0,30
6,60
6,20
80,19
4,30
4,50
7
0,15
14
A
1
1,20 MAX
14
5,10
4,90
8
3,10
2,90
A MAX
A MIN
DIM PINS **
0,05
4,90
5,10
Seating Plane
0°–8°
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,and other changes to its products and services at any time and to discontinue any product or service without notice. Customers shouldobtain the latest relevant information before placing orders and should verify that such information is current and complete. All products aresold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standardwarranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except wheremandated by government requirements, testing of all parameters of each product is not necessarily performed.TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products andapplications using TI components. To minimize the risks associated with customer products and applications, customers should provideadequate design and operating safeguards.TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right,or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Informationpublished by TI regarding third-party products or services does not constitute a license from TI to use such products or services or awarranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectualproperty of the third party, or a license from TI under the patents or other intellectual property of TI.Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompaniedby all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptivebusiness practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additionalrestrictions.
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