CD4027BM - National Semiconductor

TL/F/5958

CD4027BM/CD4027BC Dual J-K Master/Slave Flip-Flop with Set and Reset

February 1988

CD4027BM/CD4027BC Dual J-K Master/Slave

Flip-Flop with Set and Reset

General Description

These dual J-K flip-flops are monolithic complementary

MOS (CMOS) integrated circuits constructed with N- and P-

channel enhancement mode transistors. Each flip-flop has

independent J, K, set, reset, and clock inputs and buffered

Q and Q outputs. These flip-flops are edge sensitive to the

clock input and change state on the positive-going transition

of the clock pulses. Set or reset is independent of the clock

and is accomplished by a high level on the respective input.

All inputs are protected against damage due to static dis-

charge by diode clamps to VDD and VSS.

Features

YWide supply voltage range 3.0V to 15V

YHigh noise immunity 0.45 VDD (typ.)

YLow power TTL Fan out of 2 driving 74L

compatibility or 1 driving 74LS

YLow power 50 nW (typ.)

YMedium speed operation 12 MHz (typ.)

with 10V supply

Schematic and Connection Diagrams

TL/F/5958–1

Dual-In-Line Package

TL/F/5958–2

Top View

Order Number CD4027B

C1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.

Absolute Maximum Ratings (Note 1 and 2)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales

Office/Distributors for availability and specifications.

DC Supply Voltage (VDD)b0.5 VDC to a18 VDC

Input Voltage (VIN)b0.5V to VDD a0.5 VDC

Storage Temperature Range (TS)b65§Ctoa

150§C

Power Dissipation (PD)

Dual-In-Line 700 mW

Small Outline 500 mW

Lead Temperature (TL)

(Soldering, 10 seconds) 260§C

Recommended Operating

Conditions (Note 2)

DC Supply Voltage (VDD) 3Vto15V

Input Voltage (VIN) 0VtoV

DD VDC

Operating Temperature Range (TA)

CD4027BM b55§Ctoa

125§C

CD4027BC b40§Ctoa

85§C

DC Electrical Characteristics CD4027BM (Note 2)

Symbol Parameter Conditions b55§Ca25§Ca125§CUnits

Min Max Min Typ Max Min Max

IDD Quiescent Device Current VDD e5V, VIN eVDD or VSS 1130mA

DD e10V, VIN eVDD or VSS 2260mA

DD e15V, VIN eVDD or VSS 4 4 120 mA

VOL Low Level

k1mA

Output Voltage VDD e5V 0.05 0 0.05 0.05 V

VDD e10V 0.05 0 0.05 0.05 V

VDD e15V 0.05 0 0.05 0.05 V

VOH High Level

k1mA

Output Voltage VDD e5V 4.95 4.95 5 4.95 V

VDD e10V 9.95 9.95 10 9.95 V

VDD e15V 14.95 14.95 15 14.95 V

VIL Low Level VDD e5V, VOe0.5V or 4.5V 1.5 1.5 1.5 V

Input Voltage VDD e10V, VOe1V or 9V 3.0 3.0 3.0 V

VDD e15V, VOe1.5V or 13.5V 4.0 4.0 4.0 V

VIH High Level VDD e5V, VOe0.5V or 4.5V 3.5 3.5 3.5 V

Input Voltage VDD e10V, VOe1V or 9V 7.0 7.0 7.0 V

VDD e15V, VOe1.5V or 13.5V 11.0 11.0 11.0 V

IOL Low Level Output VDD e5V, VOe0.4V 0.64 0.51 0.88 0.36 mA

Current (Note 3) VDD e10V, VOe0.5V 1.6 1.3 2.25 0.9 mA

VDD e15V, VOe1.5V 4.2 3.4 8.8 2.4 mA

IOH High Level Output VDD e5V, VOe4.6V b0.64 b0.51 b0.88 b0.36 mA

Current (Note 3) VDD e10V, VOe9.5V b1.6 b1.3 b2.25 b0.9 mA

VDD e15V, VOe13.5V b4.2 b3.4 b8.8 b2.4 mA

IIN Input Current VDD e15V, VIN e0V b0.1 b10b5b0.1 b1.0 mA

VDD e15V, VIN e15V 0.1 10b50.1 1.0 mA

Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices

should be operated at these limits. The table of ‘‘Recommended Operating Conditions’’ and ‘‘Electrical Characteristics’’ provides conditions for actual device

operation.

Note 2: VSS e0V unless otherwise specified.

Note 3: IOH and IOL are tested one output at a time.

DC Electrical Characteristics CD4027BC (Note 2)

Symbol Parameter Conditions b40§Ca25§Ca85§CUnits

Min Max Min Typ Max Min Max

IDD Quiescent Device Current VDD e5V, VIN eVDD or VSS 4430mA

DD e10V, VIN eVDD or VSS 8860mA

DD e15V, VIN eVDD or VSS 16 16 120 mA

VOL Low Level

k1mA

Output Voltage VDD e5V 0.05 0 0.05 0.05 V

VDD e10V 0.05 0 0.05 0.05 V

VDD e15V 0.05 0 0.05 0.05 V

VOH High Level

k1mA

Output Voltage VDD e5V 4.95 4.95 5 4.95 V

VDD e10V 9.95 9.95 10 9.95 V

VDD e15V 14.95 14.95 15 14.95 V

VIL Low Level VDD e5V, VOe0.5V or 4.5V 1.5 1.5 1.5 V

Input Voltage VDD e10V, VOe1V or 9V 3.0 3.0 3.0 V

VDD e15V, VOe1.5V or 13.5V 4.0 4.0 4.0 V

VIH High Level VDD e5V, VOe0.5V or 4.5V 3.5 3.5 3.5 V

Input Voltage VDD e10V, VOe1V or 9V 7.0 7.0 7.0 V

VDD e15V, VOe1.5V or 13.5V 11.0 11.0 11.0 V

IOL Low Level Output VDD e5V, VOe0.4V 0.52 0.44 0.88 0.36 mA

Current (Note 3) VDD e10V, VOe0.5V 1.3 1.1 2.25 0.9 mA

VDD e15V, VOe1.5V 3.6 3.0 8.8 2.4 mA

IOH High Level Output VDD e5V, VOe4.6V b0.52 b0.44 b0.88 b0.36 mA

Current (Note 3) VDD e10V, VOe9.5V b1.3 b1.1 b2.25 b0.9 mA

VDD e15V, VOe13.5V b3.6 b3.0 b8.8 b2.4 mA

IIN Input Current VDD e15V, VIN e0V b0.3 b10b5b0.3 b1.0 mA

VDD e15V, VIN e15V 0.3 10b50.3 1.0 mA

Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices

should be operated at these limits. The table of ‘‘Recommended Operating Conditions’’ and ‘‘Electrical Characteristics’’ provides conditions for actual device

operation.

Note 2: VSS e0V unless otherwise specified.

Note 3: IOH and IOL are tested one output at a time.

AC Electrical Characteristics*TAe25§C, CLe50 pF, trCL etfCL e20 ns, unless otherwise specified

Symbol Parameter Conditions Min Typ Max Units

tPHL or tPLH Propagation Delay Time VDD e5V 200 400 ns

from Clock to Q or Q VDD e10V 80 160 ns

VDD e15V 65 130 ns

tPHL or tPLH Propagation Delay Time VDD e5V 170 340 ns

from Set to Q or Reset to Q VDD e10V 70 140 ns

VDD e15V 55 110 ns

tPHL or tPLH Propagation Delay Time VDD e5V 110 220 ns

from Set to Q or VDD e10V 50 100 ns

Reset to Q VDD e15V 40 80 ns

tSMinimum Data Setup Time VDD e5V 135 270 ns

VDD e10V 55 110 ns

VDD e15V 45 90 ns

tTHL or tTLH Transition Time VDD e5V 100 200 ns

VDD e10V 50 100 ns

VDD e15V 40 80 ns

fCL Maximum Clock Frequency VDD e5V 2.5 5 MHz

(Toggle Mode) VDD e10V 6.2 12.5 MHz

VDD e15V 7.6 15.5 MHz

trCL or tfCL Maximum Clock Rise VDD e5V 15 ms

and Fall Time VDD e10V 10 ms

VDD e15V 5 ms

tWMinimum Clock Pulse VDD e5V 100 200 ns

Width (tWH etWL)V

DD e10V 40 80 ns

VDD e15V 32 65 ns

tWH Minimum Set and VDD e5V 80 160 ns

Reset Pulse Width VDD e10V 30 60 ns

VDD e15V 25 50 ns

CIN Average Input Capacitance Any Input 5 7.5 pF

CPD Power Dissipation Capacity Per Flip-Flop 35 pF

(Note 4)

*AC Parameters are guaranteed by DC correlated testing.

Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the

devices should be operated at these limits. The table of ‘‘Recommended Operating Conditions’’ and ‘‘Electrical Characteristics’’ provides conditions for actual

device operation.

Note 2: VSS e0V unless otherwise specified.

Note 3: IOH and IOL are tested one output at a time.

Note 4: CPD determines the no load AC power consumption of any CMOS device. For complete explanation, see 54C/74C Family Characteristics application

note, AN-90.

Typical Applications

Ripple Binary Counters

TL/F/5958–3

Shift Registers

TL/F/5958–4

Truth Table

#tnb1Inputs XtnOutputs

CLUJKSRQQ Q

LI XOOO I O

LXOOO I I O

LOXOOOO I

LXIOOIO I

KX X O O X (No Change)

XXXIOXI O

XXXOIXO I

XXXIIXI I

Where: I eHigh Level

OeLow Level

UeLevel Change

XeDon’t Care

#etnb1refers to the time interval prior to the positive clock pulse transition

Xetnrefers to the time intervals after the positive clock pulse transition

CD4027BM/CD4027BC Dual J-K Master/Slave Flip-Flop with Set and Reset

Physical Dimensions inches (millimeters)

Ceramic Dual-In-Line Package (J)

Order Number CD4027BMJ or CD4027BCJ

NS Package Number J16A

Molded Dual-In-Line Package (N)

Order Number CD4027BMN or CD4027BCN

NS Package Number N16E

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DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL

SEMICONDUCTOR CORPORATION. As used herein:

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systems which, (a) are intended for surgical implant support device or system whose failure to perform can

into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life

failure to perform, when properly used in accordance support device or system, or to affect its safety or

with instructions for use provided in the labeling, can effectiveness.

be reasonably expected to result in a significant injury

to the user.

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