AD8132ARZ-REEL7 - Analog Devices, Inc.

Low Cost, High Speed

Differential Amplifier

AD8132

Rev. D

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However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

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registered trademarks are the property of their respective owners.

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FEATURES

High speed

350 MHz −3 dB bandwidth

1200 V/µs slew rate

Resistor settable gain

Internal common-mode feedback to improve gain and

phase balance −68 dB @ 10 MHz

Separate input to set the common-mode output voltage

Low distortion: −99 dBc SFDR @ 5 MHz 800 Ω Load

Low power: 10.7 mA @ 5 V

Power supply range: +2.7 V to ±5.5 V

APPLICATIONS

Low power differential ADC drivers

Differential gain and differential filtering

Video line drivers

Differential in/out level shifting

Single-ended input to differential output drivers

Active transformers

GENERAL DESCRIPTION

The AD8132 is a low cost differential or single-ended input to

differential output amplifier with resistor settable gain. The

AD8132 is a major advancement over op amps for driving

differential input ADCs or for driving signals over long lines.

The AD8132 has a unique internal feedback feature that

provides output gain and phase matching balanced to −68 dB at

10 MHz, suppressing harmonics and reducing radiated EMI.

Manufactured using ADI’s next generation XFCB bipolar

process, the AD8132 has a −3 dB bandwidth of 350 MHz and

delivers a differential signal with −99 dBc SFDR at 5 MHz,

despite its low cost. The AD8132 eliminates the need for a

transformer with high performance ADCs, preserving the low

frequency and dc information. The common-mode level of the

differential output is adjustable by applying a voltage on the

VOCM pin, easily level shifting the input signals for driving

single-supply ADCs. Fast overload recovery preserves sampling

accuracy.

FUNCTIONAL BLOCK DIAGRAM

–IN

OCM 2

V+

+OUT

+IN

V–

–OUT

NC = NO CONNECT

AD8132

01035-001

Figure 1.

The AD8132 can also be used as a differential driver for the

transmission of high speed signals over low cost twisted pair or

coaxial cables. The feedback network can be adjusted to boost

the high frequency components of the signal. The AD8132 can

be used for either analog or digital video signals or for other

high speed data transmission. The AD8132 is capable of driving

either cat3 or cat5 twisted pair or coaxial with minimal line

attenuation. The AD8132 has considerable cost and

performance improvements over discrete line driver solutions.

Differential signal processing reduces the effects of ground

noise that plagues ground referenced systems. The AD8132 can

be used for differential signal processing (gain and filtering)

throughout a signal chain, easily simplifying the conversion

between differential and single-ended components.

The AD8132 is available in both SOIC and MSOP packages for

operation over −40°C to +125°C temperatures.

FREQUENCY (MHz)

GAIN (dB)

–3

–6

–9

–12 10 100 1k

= ±5V

G = +1

O, dm

= 2V p-p

L, dm

= 499Ω

01035-002

Figure 2. Large Signal Frequency Response

AD8132

Rev. D | Page 2 of 32

TABLE OF CONTENTS

Specifications..................................................................................... 3

±DIN to ±OUT Specifications...................................................... 3

VOCM to ±OUT Specifications ..................................................... 4

±DIN to ±OUT Specifications...................................................... 5

VOCM to ±OUT Specifications ..................................................... 6

±DIN to ±OUT Specifications...................................................... 7

VOCM to ±OUT Specifications ..................................................... 7

Absolute Maximum Ratings............................................................ 8

ESD Caution.................................................................................. 8

Pin Configuration and Function Descriptions............................. 9

Typical Performance Characteristics ........................................... 10

Test Circuits..................................................................................... 19

Operational Description................................................................ 20

Definition of Terms.................................................................... 20

Basic Circuit Operation............................................................. 20

Theory of Operation ...................................................................... 21

General Usage of the AD8132................................................... 21

Resistorless Differential Amplifier (High Input Impedance

Inverting Amplifier)................................................................... 21

Other β2 = 1 Circuits ................................................................. 22

Varying β2 ................................................................................... 22

β1 = 0............................................................................................ 22

Estimating the Output Noise Voltage ...................................... 22

Calculating an Application Circuit’s Input Impedance ......... 23

Input Common-Mode Voltage Range in Single-Supply

Applications ................................................................................ 23

Setting the Output Common-Mode Voltage .......................... 23

Driving a Capacitive Load......................................................... 23

Layout, Grounding, and Bypassing .............................................. 24

Circuits......................................................................................... 24

Applications..................................................................................... 25

A/D Driver .................................................................................. 25

Balanced Cable Driver............................................................... 25

Transmit Equalizer..................................................................... 26

Low-Pass Differential Filter ...................................................... 26

High Common-Mode Output Impedance Amplifier............ 27

Full-Wave Rectifier .................................................................... 27

Outline Dimensions....................................................................... 29

Ordering Guide .......................................................................... 29

REVISION HISTORY

12/04—Rev. C to Rev. D.

Changes to the General Description.............................................. 1

Changes to the Specifications ......................................................... 2

Changes to the Absolute Maximum Ratings................................. 8

Updated the Outline Dimensions................................................. 29

Changes to the Ordering Guide.................................................... 29

2/03—Rev. B to Rev. C.

Changes to SPECIFICATIONS .......................................................2

Addition to Estimating the Output Noise Voltage section ....... 15

Updated OUTLINE DIMENSIONS ............................................ 21

1/02—Rev. A to Rev. B.

Edits to TRANSMITTER EQUALIZER section ...........................18

AD8132

Rev. D | Page 3 of 32

SPECIFICATIONS

±DIN TO ±OUT SPECIFICATIONS

At 25°C, VS = ±5 V, VOCM = 0 V, G = 1, RL, dm = 499 Ω, RF = RG = 348 Ω, unless otherwise noted. For G = 2, RL, dm = 200 Ω, RF = 1000 Ω,

RG = 499 Ω. Refer to Figure 56 and Figure 57 for test setup and label descriptions. All specifications refer to single-ended input and

differential outputs, unless otherwise noted.

Table 1.

Parameter Conditions Min Typ Max Unit

DYNAMIC PERFORMANCE

−3 dB Large Signal Bandwidth VOUT = 2 V p-p 300 350 MHz

OUT = 2 V p-p, G = 2 190 MHz

−3 dB Small Signal Bandwidth VOUT = 0.2 V p-p 360 MHz

OUT = 0.2 V p-p, G = 2 160 MHz

Bandwidth for 0.1 dB Flatness VOUT = 0.2 V p-p 90 MHz

OUT = 0.2 V p-p, G = 2 50 MHz

Slew Rate VOUT = 2 V p-p 1000 1200 V/µs

Settling Time 0.1%, VOUT = 2 V p-p 15 ns

Overdrive Recovery Time VIN = 5 V to 0 V Step, G = 2 5 ns

NOISE/HARMONIC PERFORMANCE

Second Harmonic VOUT = 2 V p-p, 1 MHz, RL, dm = 800 Ω −96 dBc

OUT = 2 V p-p, 5 MHz, RL, dm = 800 Ω −83 dBc

OUT = 2 V p-p, 20 MHz, RL, dm = 800 Ω −73 dBc

Third Harmonic VOUT = 2 V p-p, 1 MHz, RL, dm = 800 Ω −102 dBc

OUT = 2 V p-p, 5 MHz, RL, dm = 800 Ω −98 dBc

OUT = 2 V p-p, 20 MHz, RL, dm = 800 Ω −67 dBc

IMD 20 MHz, RL, dm = 800 Ω −76 dBc

IP3 20 MHz, RL, dm = 800 Ω 40 dBm

Input Voltage Noise (RTI) f = 0.1 MHz to 100 MHz 8 nV/√Hz

Input Current Noise f = 0.1 MHz to 100 MHz 1.8 pA/√Hz

Differential Gain Error NTSC, G = 2, RL, dm = 150 Ω 0.01 %

Differential Phase Error NTSC, G = 2, RL, dm = 150 Ω 0.10 Degrees

INPUT CHARACTERISTICS

Offset Voltage (RTI) VOS, dm = VOUT, dm/2; VDIN+ = VDIN− = VOCM = 0 V ±1.0 ±3.5 mV

MIN to TMAX Variation 10 µV/°C

Input Bias Current 3 7 µA

Input Resistance Differential 12 MΩ

Common-Mode 3.5 MΩ

Input Capacitance 1 pF

Input Common-Mode Voltage −4 to +3 V

CMRR ∆VOUT, dm/∆VIN, cm; ∆VIN, cm = ±1 V; Resistors Matched to 0.01% −70 −60 dB

OUTPUT CHARACTERISTICS

Output Voltage Swing Maximum ∆VOUT; Single-Ended Output −3.6 to +3.6 V

Output Current 70 mA

Output Balance Error ∆VOUT, cm/∆VOUT, dm; ∆VOUT, dm = 1 V −70 dB

AD8132

Rev. D | Page 4 of 32

VOCM TO ±OUT SPECIFICATIONS

At 25°C, VS = ±5 V, VOCM = 0 V, G = 1, RL, dm = 499 Ω, RF = RG = 348 Ω, unless otherwise noted. For G = 2, RL, dm = 200 Ω, RF = 1000 Ω,

RG = 499 Ω. Refer to Figure 56 and Figure 57 for test setup and label descriptions. All specifications refer to single-ended input and

differential outputs, unless otherwise noted.

Table 2.

Parameter Conditions Min Typ Max Unit

DYNAMIC PERFORMANCE

−3 dB Bandwidth ∆VOCM = 600 mV p-p 210 MHz

Slew Rate ∆VOCM = −1 V to +1 V 400 V/µs

Input Voltage Noise (RTI) f = 0.1 MHz to 100 MHz 12 nV/√Hz

DC PERFORMANCE

Input Voltage Range ±3.6 V

Input Resistance 50 kΩ

Input Offset Voltage VOS, cm = VOUT, cm; VDIN+ = VDIN− = VOCM = 0 V ±1.5 ±7 mV

Input Bias Current 0.5 µA

VOCM CMRR ∆VOUT, dm/∆VOCM; ∆VOCM = ±1 V; Resistors Matched to 0.01% −68 dB

Gain ∆VOUT, cm/∆VOCM; ∆VOCM = ±1 V 0.985 1 1.015 V/V

POWER SUPPLY

Operating Range ±1.35 ±5.5 V

Quiescent Current VDIN+ = VDIN− = VOCM = 0 V 11 12 13 mA

MIN to TMAX Variation 16 µA/°C

Power Supply Rejection Ratio ∆VOUT, dm/∆VS; ∆VS = ±1 V −70 −60 dB

OPERATING TEMPERATURE RANGE −40 +125 °C

AD8132

Rev. D | Page 5 of 32

±DIN TO ±OUT SPECIFICATIONS

At 25°C, VS = 5 V, VOCM = 2.5 V, G = 1, RL, dm = 499 Ω, RF = RG = 348 Ω, unless otherwise noted. For G = 2, RL, dm = 200 Ω, RF = 1000 Ω,

RG = 499 Ω. Refer to Figure 56 and Figure 57 for test setup and label descriptions. All specifications refer to single-ended input and

differential outputs, unless otherwise noted.

Table 3.

Parameter Conditions Min Typ Max Unit

DYNAMIC PERFORMANCE

−3 dB Large Signal Bandwidth VOUT = 2 V p-p 250 300 MHz

OUT = 2 V p-p, G = 2 180 MHz

−3 dB Small Signal Bandwidth VOUT = 0.2 V p-p 360 MHz

OUT = 0.2 V p-p, G = 2 155 MHz

Bandwidth for 0.1 dB Flatness VOUT = 0.2 V p-p 65 MHz

OUT = 0.2 V p-p, G = 2 50 MHz

Slew Rate VOUT = 2 V p-p 800 1000 V/µs

Settling Time 0.1%, VOUT = 2 V p-p 20 ns

Overdrive Recovery Time VIN = 2.5 V to 0 V Step, G = 2 5 ns

NOISE/HARMONIC PERFORMANCE

Second Harmonic VOUT = 2 V p-p, 1 MHz, RL, dm = 800 Ω −97 dBc

OUT = 2 V p-p, 5 MHz, RL, dm = 800 Ω −100 dBc

OUT = 2 V p-p, 20 MHz, RL, dm = 800 Ω −74 dBc

Third Harmonic VOUT = 2 V p-p, 1 MHz, RL, dm = 800 Ω −100 dBc

OUT = 2 V p-p, 5 MHz, RL, dm = 800 Ω −99 dBc

OUT = 2 V p-p, 20 MHz, RL, dm = 800 Ω −67 dBc

IMD 20 MHz, RL, dm = 800 Ω −76 dBc

IP3 20 MHz, RL, dm = 800 Ω 40 dBm

Input Voltage Noise (RTI) f = 0.1 MHz to 100 MHz 8 nV/√Hz

Input Current Noise f = 0.1 MHz to 100 MHz 1.8 pA/√Hz

Differential Gain Error NTSC, G = 2, RL, dm = 150 Ω 0.025 %

Differential Phase Error NTSC, G = 2, RL, dm = 150 Ω 0.15 Degree

INPUT CHARACTERISTICS

Offset Voltage (RTI) VOS, dm = VOUT, dm/2; VDIN+ = VDIN− = VOCM = 2.5 V ±1.0 ±3.5 mV

MIN to TMAX Variation 6 µV/°C

Input Bias Current 3 7 µA

Input Resistance Differential 10 MΩ

Common-Mode 3 MΩ

Input Capacitance 1 pF

Input Common-Mode Voltage 1 to 3 V

CMRR ∆VOUT, dm/∆VIN, cm; ∆VIN, cm = ±1 V; Resistors Matched to 0.01% −70 −60 dB

OUTPUT CHARACTERISTICS

Output Voltage Swing Maximum ∆VOUT; Single-Ended Output 1.0 to 4.0 V

Output Current 50 mA

Output Balance Error ∆VOUT, cm/∆VOUT, dm; ∆VOUT, dm = 1 V −68 dB

AD8132

Rev. D | Page 6 of 32

VOCM TO ±OUT SPECIFICATIONS

At 25°C, VS = 5 V, VOCM = 2.5 V, G = 1, RL, dm = 499 Ω, RF = RG = 348 Ω, unless otherwise noted. For G = 2, RL, dm = 200 Ω, RF = 1000 Ω,

RG = 499 Ω. Refer to Figure 56 and Figure 57 for test setup and label descriptions. All specifications refer to single-ended input and

differential outputs, unless otherwise noted.

Table 4.

Parameter Conditions Min Typ Max Unit

DYNAMIC PERFORMANCE

−3 dB Bandwidth ∆VOCM = 600 mV p-p 210 MHz

Slew Rate ∆VOCM = 1.5 V to 3.5 V 340 V/µs

Input Voltage Noise (RTI) f = 0.1 MHz to 100 MHz 12 nV/√Hz

DC PERFORMANCE

Input Voltage Range 1.0 to 3.7 V

Input Resistance 30 kΩ

Input Offset Voltage VOS, cm = VOUT, cm; VDIN+ = VDIN− = VOCM = 2.5 V ±5 ±11 mV

Input Bias Current 0.5 µA

VOCM CMRR ∆VOUT, dm/∆VOCM; ∆VOCM = 2.5 V ±1 V; Resistors Matched to 0.01% −66 dB

Gain ∆VOUT, cm/∆VOCM; ∆VOCM = 2.5 V ±1 V 0.985 1 1.015 V/V

POWER SUPPLY

Operating Range 2.7 11 V

Quiescent Current VDIN+ = VDIN− = VOCM = 2.5 V 9.4 10.7 12 mA

MIN to TMAX Variation 10 µA/°C

Power Supply Rejection Ratio ∆VOUT, dm/∆VS; ∆VS = ±1 V −70 −60 dB

OPERATING TEMPERATURE RANGE −40 +125 °C

AD8132

Rev. D | Page 7 of 32

±DIN TO ±OUT SPECIFICATIONS

At 25°C, VS = 3 V, VOCM = 1.5 V, G = 1, RL, dm = 499 Ω, RF = RG = 348 Ω unless otherwise noted. For G = 2, RL, dm = 200 Ω, RF = 1000 Ω,

RG = 499 Ω. Refer to Figure 56 and Figure 57 for test setup and label descriptions. All specifications refer to single-ended input and

differential outputs, unless otherwise noted.

Table 5.

Parameter Conditions Min Typ Max Unit

DYNAMIC PERFORMANCE

−3 dB Large Signal Bandwidth VOUT = 1 V p-p 350 MHz

OUT = 1 V p-p, G = 2 165 MHz

−3 dB Small Signal Bandwidth VOUT = 0.2 V p-p 350 MHz

OUT = 0.2 V p-p, G = 2 150 MHz

Bandwidth for 0.1 dB Flatness VOUT = 0.2 V p-p 45 MHz

OUT = 0.2 V p-p, G = 2 50 MHz

NOISE/HARMONIC PERFORMANCE

Second Harmonic VOUT = 1 V p-p, 1 MHz, RL, dm = 800 Ω −100 dBc

OUT = 1 V p-p, 5 MHz, RL, dm = 800 Ω −94 dBc

OUT = 1 V p-p, 20 MHz, RL, dm = 800 Ω −77 dBc

Third Harmonic VOUT = 1 V p-p, 1 MHz, RL, dm = 800 Ω −90 dBc

OUT = 1 V p-p, 5 MHz, RL, dm = 800 Ω −85 dBc

OUT = 1 V p-p, 20 MHz, RL, dm = 800 Ω −66 dBc

INPUT CHARACTERISTICS

Offset Voltage (RTI) VOS, dm = VOUT, dm/2; VDIN+ = VDIN− = VOCM = 1.5 V ±10 mV

Input Bias Current 3 µA

CMRR ∆VOUT, dm/∆VIN, cm; ∆VIN, cm = ±0.5 V; Resistors Matched to 0.01% −60 dB

VOCM TO ±OUT SPECIFICATIONS

At 25°C, VS = 3 V, VOCM = 1.5 V, G = 1, RL, dm = 499 Ω, RF = RG = 348 Ω unless otherwise noted. For G = 2, RL, dm = 200 Ω, RF = 1000 Ω,

RG = 499 Ω. Refer to Figure 56 and Figure 57 for test setup and label descriptions. All specifications refer to single-ended input and

differential outputs, unless otherwise noted.

Table 6.

Parameter Conditions Min Typ Max Unit

DC PERFORMANCE

Input Offset Voltage VOS, cm = VOUT, cm; VDIN+ = VDIN− = VOCM = 1.5 V ±7 mV

Gain ∆VOUT, cm/∆VOCM; ∆VOCM = ±0.5 V 1 V/V

POWER SUPPLY

Operating Range 2.7 11 V

Quiescent Current VDIN+ = VDIN− = VOCM = 0 V 7.25 mA

Power Supply Rejection Ratio ∆VOUT, dm/∆VS; ∆VS = ±0.5 V −70 dB

OPERATING TEMPERATURE RANGE −40 +125 °C

AD8132

Rev. D | Page 8 of 32

ABSOLUTE MAXIMUM RATINGS

Table 7. 1

Parameter Ratings

Supply Voltage ±5.5 V

VOCM ±VS

Internal Power Dissipation 250 mW

Operating Temperature Range −40°C to +125°C

Storage Temperature Range −65°C to +150°C

Lead Temperature (Soldering 10 sec) 300°C

1 Thermal resistance measured on SEMI-standard, 4-layer board.

8-Lead SOIC: θJA = 121°C/W

8-Lead MSOP: θJA = 142°C/W

Stresses above those listed under absolute maximum ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those listed in the operational section of

this specification is not implied. Exposure to Absolute

Maximum Ratings for extended periods may affect device

reliability.

AMBIENT TEMPERATURE (°C)

–50

= 150°C

2.0

1.5

1.0

MAXIMUM POWER DISSIPATION (W)

8-LEAD SOIC

PACKAGE

–40 –30 0 102030405060708090

8-LEAD

MSOP

PACKAGE

0.5

–20 –10

01035-003

Figure 3. Plot of Maximum Power Dissipation vs. Temperature

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate

on the human body and test equipment and can discharge without detection. Although this product features

proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy

electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance

degradation or loss of functionality.

AD8132

Rev. D | Page 9 of 32

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

–IN

OCM 2

V+

+OUT

+IN

V–

–OUT

NC = NO CONNECT

AD8132

01035-004

Figure 4. Pin Configuration

Table 8. Pin Function Descriptions

No. Mnemonic Description

1 −IN Negative Input.

2 VOCM Voltage applied to this pin sets the

common-mode output voltage with

a ratio of 1:1. For example, 1 V dc on

VOCM sets the dc bias level on +OUT and

−OUT to 1 V.

3 V+ Positive Supply Voltage.

4 +OUT Positive Output. Note that the voltage at

−DIN is inverted at +OUT (see Figure 64).

5 −OUT Negative Output. Note that the voltage at

+DIN is inverted at −OUT (see Figure 64).

6 V− Negative Supply Voltage.

7 NC No Connect.

8 +IN Positive Input.

AD8132

Rev. D | Page 10 of 32

TYPICAL PERFORMANCE CHARACTERISTICS

01035-006

FREQUENCY (MHz)

GAIN (dB)

–1

–2

–3

–4

–510 100 1k

G = +1

O, dm

= 0.2V p-p

L, dm

= 499Ω

= +3V V

= +5V

= ±5V

Figure 5. Small Signal Frequency Response (See Figure 56)

FREQUENCY (MHz)

GAIN (dB)

1 10 100 1k

0.4

0.3

0.2

0.1

–0.1

–0.2

–0.3

–0.4

–0.5

0.5 G = +1

O, dm

= 0.2V p-p

L, dm

= 499Ω

= +3V

= +5V

= ±5V

01035-007

Figure 6. 0.1 dB Flatness vs. Frequency CF = 0 pF (See Figure 56)

FREQUENCY (MHz)

GAIN (dB)

1 10 100 1k

G = +1

O, dm

= 0.2V p-p

L, dm

= 499Ω

0.2

0.1

–0.1

–0.2

–0.3

–0.4

–0.5

= +3V V

= +5V

= ±5V

01035-008

Figure 7. 0.1 dB Flatness vs. Frequency CF = 0.5 pF (See Figure 56)

FREQUENCY (MHz)

GAIN (dB)

1 10 100 1k

–1

–2

–3

–4

–5

G = +1

O, dm

= 2V p-p FOR V

= ±5V, +5V

O, dm

= 1V p-p FOR V

= +3V

L, dm

= 499Ω

= +3V

= +5V

= ±5V

01035-009

= +3V

Figure 8. Large Signal Frequency Response; CF = 0 pF (See Figure 56)

FREQUENCY (MHz)

GAIN (dB)

1 10 100 1k

–1

–2

–3

–4

–5

G = +1

O, dm

= 2V p-p FOR V

= ±5V, +5V

O, dm

= 1V p-p FOR V

= +3V

L, dm

= 499Ω

= +3V

= +5V

= ±5V

= +3V

01035-010

Figure 9. Large Signal Frequency Response; CF = 0.5 pF (See Figure 56)

FREQUENCY (MHz)

GAIN (dB)

1 10 100 1k

–1

–2

–3

–4

–5

= ±5V

G = +1

O, dm

= 2V p-p

L, dm

= 499Ω

–40°C

+85°C

+25°C

01035-011

Figure 10. Large Signal Response vs. Temperature (See Figure 56)

AD8132

Rev. D | Page 11 of 32

FREQUENCY (MHz)

GAIN (dB)

1 10 100 1k

–1

–2

–3

–4

–5

= ±5V

G = +1

O, dm

= 2V p-p

L, dm

= 499Ω

= 348Ω

= 249Ω

01035-012

Figure 11. Large Signal Frequency Response vs. RF (See Figure 56)

FREQUENCY (MHz)

IMPEDANCE (Ω)

100

0.1 10 100

= +5V

= ±5V

01035-013

Figure 12. Closed-Loop Single-Ended ZOUT vs. Frequency; G = 1 (See Figure 56)

FREQUENCY (MHz)

GAIN (dB)

110 100 1k

G = +2

O, dm

= 0.2V p-p

L, dm

= 200Ω

= +3V

= ±5V, +5V

01035-015

Figure 13. Small Signal Frequency Response (See Figure 57)

FREQUENCY (MHz)

GAIN (dB)

1 10 100 1k

= +3V, +5V, ±5V

G = +2

O, dm

= 0.2V p-p

L, dm

= 200Ω

6.1

6.0

5.9

5.8

5.7

5.6

5.5

01035-016

Figure 14. 0.1 dB Flatness vs. Frequency (See Figure 57)

FREQUENCY (MHz)

GAIN (dB)

1 10 100 1k

= +5V, ±5V

= +3V

G = +2

O, dm

= 2V p-p FOR

= ±5V, +5V

O, dm

= 1V p-p FOR

= +3V

L, dm

= 200Ω

01035-017

Figure 15. Large Signal Frequency Response (See Figure 57)

FREQUENCY (MHz)

GAIN (dB)

1 10 100 1k

= ±5V

G = +2

O, dm

= 0.2V p-p

L, dm

= 200Ω

= 1.0kΩ

= 499Ω

= 1.5kΩ

01035-018

Figure 16. Small Signal Frequency Response vs. RF (See Figure 57)

AD8132

Rev. D | Page 12 of 32

FREQUENCY (MHz)

GAIN (dB)

1 10 100 1k

–5 V

= ±5V

O, dm

= 2V p-p

L, dm

= 200Ω

= 499Ω

–10

–15

G = +10, R

= 4.99kΩ

G = +5, R

= 2.49kΩ

G = +2, R

= 1kΩ

G = +1, R

= 499Ω

01035-020

Figure 17. Large Signal Response for Various Gains (See Figure 58)

FREQUENCY (MHz)

RTI BALANCE ERROR (dB)

1 10 100 1k

–

–30

–35

–40

–45

–50

–55

VS = ±5V

∆VO, dm = 2V p-p

∆VO, cm/∆VO, dm

–60

–65

G = +1

G = +2

–70

–75

01035-022

Figure 18. RTI Output Balance Error vs. Frequency (See Figure 59)

FREQUENCY (MHz)

DISTORTION (dBc)

0 50607

–40

–50

–60

–70

–80

–90

–100

020 30 4010

–110

L, dm

= 800Ω

O, dm

= 1V p-p

HD3 (V

= 3V)

HD2 (V

= 3V)

HD2 (V

= 5V)

HD3 (V

= 5V)

01035-024

Figure 19. Harmonic Distortion vs. Frequency, G = 1 (See Figure 62)

FREQUENCY (MHz)

DISTORTION (dBc)

–40

–50

–60

–70

–80

–90

–100

20 30 4010

–110 06070

L, dm

= 800Ω

O, dm

= 2V p-p HD3 (V

= +5V)

HD2 (V

= ±5V)

HD2 (V

= +5V)

HD3 (V

= ±5V)

–30

01035-025

Figure 20. Harmonic Distortion vs. Frequency, G = 1 (See Figure 62)

DIFFERENTIAL OUTPUT VOLTAGE (V p-p)

DISTORTION (dBc)

0.25 1.50 1.75

–40

–50

–60

–70

–80

–90

–100

0.75 1.00 1.250.50

–110

= 3V

L, dm

= 800ΩHD3 (F = 20MHz)

HD2 (F = 20MHz)

HD2 (F = 5MHz) HD3 (F = 5MHz)

01035-026

Figure 21. Harmonic Distortion vs.

Differential Output Voltage, G = 1 (See Figure 62)

DIFFERENTIAL OUTPUT VOLTAGE (V p-p)

DISTORTION (dBc)

–

–50

–60

–70

–80

–90

–100

231

–110 4

= 5V

L, dm

= 800Ω

HD3 (F = 20MHz)

HD2 (F = 20MHz)

HD2 (F = 5MHz)

HD3 (F = 5MHz)

01035-027

Figure 22. Harmonic Distortion vs.

Differential Output Voltage, G = 1 (See Figure 62)

AD8132

Rev. D | Page 13 of 32

DIFFERENTIAL OUTPUT VOLTAGE (V p-p)

DISTORTION (dBc)

–40

–50

–60

–70

–80

–90

–100

2341

–110

= ±5V

L, dm

= 800ΩHD3 (F = 20MHz)

HD2 (F = 20MHz)

HD2 (F = 5MHz)

HD3 (F = 5MHz)

01035-028

Figure 23. Harmonic Distortion vs.

Differential Output Voltage, G = 1 (See Figure 62)

LOAD

(Ω)

DISTORTION (dBc)

200 700 800

–

–60

–70

–80

–90

–100

400 500 600300

–110

= 3V

O, dm

= 1V p-p

900 1000

HD3 (F = 20MHz)

HD2 (F = 20MHz)

HD2 (F = 5MHz)

HD3 (F = 5MHz)

01035-029

Figure 24. Harmonic Distortion vs. RLOAD, G = 1 (See Figure 62)

LOAD

(Ω)

DISTORTION (dBc)

200 700 800

–

–60

–70

–80

–90

–100

400 500 600300

–110

= 5V

O, dm

= 2V p-p

900 1000

HD3 (F = 20MHz)

HD2 (F = 20MHz)

HD2 (F = 5MHz)

HD3 (F = 5MHz)

01035-030

Figure 25. Harmonic Distortion vs. RLOAD, G = 1 (See Figure 62)

LOAD

(Ω)

DISTORTION (dBc)

200 700 800

–50

–60

–70

–80

–90

–100

400 500 600300

–110

= ±5V

O, dm

= 2V p-p HD3 (F = 20MHz)

HD2 (F = 20MHz)

HD2 (F = 5MHz)

HD3 (F = 5MHz)

900 1000

01035-031

Figure 26. Harmonic Distortion vs. RLOAD, G = 1 (See Figure 62)

FREQUENCY (MHz)

DISTORTION (dBc)

40 50

–50

–60

–70

–80

–90

–100

10 20 300

–110

HD3 (V

= 3V)

60 70

L,dm

= 800Ω

O, dm

= 1V p-p

–

HD3 (V

= 5V)

HD2 (V

= 5V)

HD2 (V

= 3V)

01035-033

Figure 27. Harmonic Distortion vs. Frequency, G = 2 (See Figure 63)

FREQUENCY (MHz)

DISTORTION (dBc)

40 50

–50

–60

–70

–80

–90

–100 10 20 300

HD3 (VS = ±5V)

60 70

RL, dm = 800Ω

VO,dm = 4V p-p

–40

HD3 (VS = +5V)

HD2 (VS = +5V)

–30

–20

HD2 (VS = ±5V)

01035-034

Figure 28. Harmonic Distortion vs. Frequency, G = 2 (See Figure 63)

AD8132

Rev. D | Page 14 of 32

DIFFERENTIAL OUTPUT VOLTAGE (V p-p)

DISTORTION (dBc)

–50

–60

–70

–80

–90

–100

103

= 5V

L, dm

= 800Ω

–

HD3 (F = 20MHz)

–110

–120

HD2 (F = 20MHz)

HD2 (F = 5MHz)

HD3 (F = 5MHz)

01035-035

Figure 29. Harmonic Distortion vs.

Differential Output Voltage, G = 2 (See Figure 63)

DIFFERENTIAL OUTPUT VOLTAGE (V p-p)

DISTORTION (dBc)

–50

–60

–70

–80

–90

–100

103

= 5V

L, dm

= 800Ω

–40 HD3 (F = 20MHz)

–110

HD2 (F = 20MHz)

HD2 (F = 5MHz)

HD3 (F = 5MHz)

01035-036

Figure 30. Harmonic Distortion vs.

Differential Output Voltage, G = 2 (See Figure 63)

LOAD

(Ω)

DISTORTION (dBc)

400

–50

–60

–70

–80

–90

–100

300200 500

HD3 (F = 20MHz)

600

–110

HD2 (F = 20MHz)

HD2 (F = 5MHz)

HD3 (F = 5MHz)

700 800

= 5V

O, dm

= 2V p-p

900 1000

01035-037

Figure 31. Harmonic Distortion vs. RLOAD, G = 2 (See Figure 63)

RLOAD (Ω)

DISTORTION (dBc)

400

–50

–60

–70

–80

–90

–100

300200 500

HD3 (F = 20MHz)

600

–110

HD2 (F = 20MHz)

HD2 (F = 5MHz)

HD3 (F = 5MHz)

700 800

VS = ±5V

VO, dm = 2V p-p

900 1000

01035-038

Figure 32. Harmonic Distortion vs. RLOAD, G = 2 (See Figure 63)

FREQUENCY (MHz)

OUT

(dBm [Re: 50

Ω

])

19.5

–10

–20

–30

–40

–50

–60

–70

–80

–90 20.0 20.5

= 20MHz

= ±5V

L, dm

= 800Ω

01035-039

Figure 33. Intermodulation Distortion, G = 1

FREQUENCY (MHz)

15 010 70

20 30 40 50 60

= ±5V, +5V

L, dm

= 800Ω

INTERCEPT (dBm [Re: 50

Ω

])

01035-040

Figure 34. Third-Order Intercept vs. Frequency, G = 1

AD8132

Rev. D | Page 15 of 32

01035-041

= ±5V, +5V, +3V

40mV 5ns

Figure 35. Small Signal Transient Response, G = 1

300mV 5ns

= 3V

O, dm

= 1.5V p-p

= 0pF

= 0.5pF

01035-042

Figure 36. Large Signal Transient Response, G = 1

01035-043

400mV 5ns

= 5V

O, dm

= 2V p-p

= 0pF

= 0.5pF

Figure 37. Large Signal Transient Response, G = 1

01035-044

= ±5V

O,dm

= 2V p-p

400mV 5ns

= 0pF

= 0.5pF

Figure 38. Large Signal Transient Response, G = 1

01035-045

1V 5ns

–OUT

+OUT

+DIN

O, dm

Figure 39. Large Signal Transient Response, G = 1

01035-046

40mV 5ns

VS = ±5V, +5V, +3V

Figure 40. Small Signal Transient Response, G = 2

AD8132

Rev. D | Page 16 of 32

01035-047

300mV 5ns

VS = 3V

Figure 41. Large Signal Transient Response, G = 2

01035-048

400mV 5ns

VS = +5V, ±5V

Figure 42. Large Signal Transient Response, G = 2

01035-049

1V 5ns

= ±5V

O, dm

–OUT

+OUT

+DIN

Figure 43. Large Signal Transient Response, G = 2

2mV 5ns

VS = ±5V

G = +1

VO, dm = 2V p-p

RL, dm = 499Ω

5ns/DIV

0.1%/DIV

0 5 10 15 20 25 30 35 40

01035-050

Figure 44. 0.1% Settling Time

01035-052

5ns

= 5pF

= 0pF

= 20pF

400mV

Figure 45. Large Signal Transient Response

for Various Capacitor Loads (See Figure 60)

FREQUENCY (MHz)

PSRR (dB)

0.1 1 10 100

–10

–20

–30

–40

–50

–60

–70

–80

–90 1k

∆

O, dm

∆

+PSRR

–PSRR

+PSRR (V

5V, +5V)

–PSRR (V

5V)

01035-053

Figure 46. PSRR vs. Frequency

AD8132

Rev. D | Page 17 of 32

FREQUENCY (MHz)

CMRR (dB)

1 10 100 1000

–70

–80

–50

–60

–30

–40

–

∆V

O, dm

∆V

IN, cm

∆V

O, cm

∆V

IN, cm

= ±5V

IN, cm

= 2V p-p

01035-055

Figure 47. CMRR vs. Frequency (See Figure 61)

FREQUENCY (MHz)

OCM

GAIN (dB)

1 10 100 1000

–9

–12

–3

–6

∆V

O,cm

∆V

OCM

∆V

OCM

= 600mV p-p

∆V

OCM

= 2V p-p

–15

= ±5V

01035-056

Figure 48. VOCM Gain Response

= ±5V

OCM

= –1V TO +1V

400mV 5ns

O, cm

01035-057

Figure 49. VOCM Transient Response

FREQUENCY (MHz)

OCM

CMRR (dB)

1 10 100 1000

–70

–80

–50

–60

–30

–40

–20

∆V

OCM

= 2V p-p

∆V

OCM

= 600mV p-p

∆V

O, dm

∆V

OCM

–10

01035-058

Figure 50. VOCM CMRR vs. Frequency

FREQUENCY (Hz)

INPUT VOLTAGE NOISE (nV/ Hz)

100

1100 1k 10k 100k 1M 10M

8nV/ Hz

100M

01035-059

Figure 51. Input Voltage Noise vs. Frequency

FREQUENCY (Hz)

100

1100 1k 10k 100k 1M 10M 100M

INPUT CURRENT NOISE (pA/ Hz)

01035-060

1.8pA/ Hz

Figure 52. Input Current Noise vs. Frequency

AD8132

Rev. D | Page 18 of 32

5ns

O, dm

(0.5V/DIV)

IN, sm

(1V/DIV)

= 5V

= 2.5V STEP

G = +2

= 1kΩ

L, dm

= 200Ω

01035-061

Figure 53. Overdrive Recovery

TEMPERATURE (°C)

SUPPLY CURRENT (mA)

5–50 –30 90

–10 10 30 50 70

= ±5V

= +5V

01035-062

Figure 54. Quiescent Current vs. Temperature

TEMPERATURE (°C)

DIFFERENTIAL OUTPUT OFFSET (mV)

–0.5

–2.5–40 –20 100

020406080

–1.0

–1.5

–2.0

VS = ±5V

VS = +5V

01035-063

Figure 55. Differential Offset Voltage vs. Temperature

AD8132

Rev. D | Page 19 of 32

TEST CIRCUITS

0.1µF

348Ω

49.9Ω

24.9Ω

348Ω

499Ω

01035-005

Figure 56. Basic Test Circuit, G = 1

0.1µF

499Ω

49.9Ω

24.9Ω

1000Ω

200Ω

01035-014

Figure 57. Basic Test Circuit, G = 2

0.1µF

499Ω

49.9Ω

24.9Ω

200Ω

01035-019

Figure 58. Test Circuit for Various Gains

0.1µF

49.9Ω

24.9Ω

G = +1: R

= R

= 348Ω, R

= 249Ω (R

L, dm

= 498Ω)

G = +2: R

= 1000Ω, R

= 499Ω, R

= 100Ω(R

L, dm

= 200Ω)

01035-021

Figure 59. Test Circuit for Output Balance

0.1µF

348Ω

49.9Ω

24.9Ω

348Ω

453Ω

24.9Ω

01035-051

Figure 60. Test Circuit for Capacitor Load Drive

348Ω

49.9Ω

348Ω

249Ω

O, dm

O, cm

NOTE: RESISTORS MATCHED TO 0.01%.

01035-054

Figure 61. CMRR Test Circuit

0.1µF

348Ω

49.9Ω

24.9Ω

348

Ω

348Ω

300Ω

2:1 TRANSFORMER

01035-023

LPF HPF

= 50Ω

Figure 62. Harmonic Distortion Test Circuit, G = 1, RL, dm = 800 Ω

0.1µF

499Ω

49.9Ω

24.9Ω

1000

Ω

1000Ω

300Ω

2:1 TRANSFORMER

01035-032

LPF HPF

= 50Ω

Figure 63. Harmonic Distortion Test Circuit, G = 2, RL, dm = 800 Ω

AD8132

Rev. D | Page 20 of 32

OPERATIONAL DESCRIPTION

DEFINITION OF TERMS

Differential Voltage

The difference between two node voltages. For example, the

output differential voltage (or equivalently output differential-

mode voltage) is defined as

VOUT, dm = (V+OUT − V−OUT)

where V+OUT and V−OUT refer to the voltages at the +OUT and

−OUT terminals with respect to a common reference.

Common-Mode Voltage

The average of two node voltages. The output common-mode

voltage is defined as

VOUT, cm = (V+OUT − V−OUT)/2

AD8132

+IN

–IN

OCM

–D

L, dm

+OUT

O, dm

–OUT

01035-064

Figure 64. Circuit Definitions

BASIC CIRCUIT OPERATION

One of the more useful and easy to understand ways to use the

AD8132 is to provide two equal-ratio feedback networks. To

match the effect of parasitics, these networks should actually be

comprised of two equal-value feedback resistors, RF, and two

equal-value gain resistors, RG. This circuit is shown in Figure 64.

Like a conventional op amp, the AD8132 has two differential

inputs that can be driven with both a differential-mode input

voltage, VIN, dm, and a common-mode input voltage, VIN, cm.

There is another input, VOCM, that is not present on conventional

op amps but provides another input to consider on the AD8132.

It is totally separate from the above inputs.

There are two complementary outputs whose response can be

defined by a differential-mode output, VOUT, dm, and a common-

mode output, VOUT, cm.

Table 9 indicates the gain from any type of input to either type

of output.

Table 9. Differential- and Common-Mode Gains

Input VOUT, dm V

OUT, cm

VIN, dm R

F/RG 0 (By Design)

VIN, cm 0 0 (By Design)

VOCM 0 1 (By Design)

The differential output (VOUT, dm) is equal to the differential

input voltage (VIN, dm) times RF/RG. In this case, it does not

matter if both differential inputs are driven, or only one output

is driven and the other is tied to a reference voltage, such as

ground. As is seen from the two zero entries in the first column,

neither of the common-mode inputs has any effect on this gain.

The gain from VIN, dm to VOUT, cm is 0, and first-order does not

depend on the ratio matching of the feedback networks. The

common-mode feedback loop within the AD8132 provides a

corrective action to keep this gain term minimized. The term

balance error describes the degree to which this gain term

differs from 0.

The gain from VIN, cm to VOUT, dm directly depends on the

matching of the feedback networks. The analogous term for this

transfer function, which is used in conventional op amps, is

common-mode rejection ratio (CMRR). Therefore, if it has a

high CMRR, the feedback ratios must be well matched.

The gain from VIN, cm to VOUT, cm is also ideally 0 and is first-order

independent of the feedback ratio matching. As in the case of

VIN, dm to VOUT, cm, the common-mode feedback loop keeps this

term minimized.

The gain from VOCM to VOUT, dm is ideally 0 when the feedback

ratios are matched only. The amount of differential output

signal that is created by varying VOCM is related to the degree of

mismatch in the feedback networks.

VOCM controls the output common-mode voltage VOUT, cm with a

unity-gain transfer function. With equal-ratio feedback

networks (as assumed above), its effect on each output is the

same, which is another way of saying that the gain from VOCM to

VOUT, dm is 0. If not driven, the output common-mode is at

midsupply. It is recommended that a 0.1 µF bypass capacitor be

connected to VOCM.

When unequal feedback ratios are used, the two gains

associated with VOUT, dm become nonzero. This significantly

complicates the mathematical analysis along with any intuitive

understanding of how the part operates.

AD8132

Rev. D | Page 21 of 32

THEORY OF OPERATION

The AD8132 differs from conventional op amps by the external

presence of an additional input and output. The additional

input, VOCM, controls the output common-mode voltage. The

additional output is the analog complement of the single

output of a conventional op amp. For its operation, the AD8132

uses two feedback loops as compared to the single loop of

conventional op amps. While this provides significant freedom

to create various novel circuits, basic op amp theory can still be

used to analyze the operation.

One of the feedback loops controls the output common-mode

voltage, VOUT, cm. Its input is VOCM (Pin 2) and the output is the

common-mode, or average voltage, of the two differential

outputs (+OUT and −OUT). The gain of this circuit is

internally set to unity. When the AD8132 is operating in its

linear region, this establishes one of the operational constraints:

VOUT, cm = VOCM.

The second feedback loop controls the differential operation.

Similar to an op amp, the gain and gain-shaping of the transfer

function can be controlled by adding passive feedback

networks. However, only one feedback network is required to

close the loop and fully constrain the operation, but depending

on the function desired, two feedback networks can be used.

This is possible as a result of having two outputs that are each

inverted with respect to the differential inputs.

GENERAL USAGE OF THE AD8132

Several assumptions are made here for a first-order analysis;

they are the typical assumptions used for the analysis of op

amps:

• The input bias currents are sufficiently small so they can be

neglected.

• The output impedances are arbitrarily low.

• The open-loop gain is arbitrarily large, which drives the

amplifier to a state where the input differential voltage is

effectively 0.

• Offset voltages are assumed to be 0.

While it is possible to operate the AD8132 with a purely

differential input, many of its applications call for a circuit that

has a single-ended input with a differential output.

For a single-ended-to-differential circuit, the RG of the undriven

input is tied to a reference voltage. This is ground and other

conditions are discussed later. Also, the voltage at VOCM, and

therefore VOUT, cm, is assumed to be ground for now. Figure 65

shows a generalized schematic of such a circuit using an

AD8132 with two feedback paths.

For each feedback network, a feedback factor can be defined as

the fraction of the output signal that is fed back to the opposite

sign input. These terms are:

(

)

G1G1 RRR

β1

(

)

G2G2 RRR

β2

The feedback factor β1 is for the side that is driven, while the

feedback factor β2 is for the side that is tied to a reference

voltage (ground for now). Note also that each feedback factor

can vary anywhere between 0 and 1.

A single-ended-to-differential gain equation can be derived,

which is true for all values of β1 and β2.

(

)

(

)

β2β1β112G

−

This expression is not very intuitive, but some further examples

can provide better understanding of its implications. One

observation that can be made right away is that a tolerance

error in β1 does not have the same effect on gain as the same

tolerance error in β2.

RESISTORLESS DIFFERENTIAL AMPLIFIER (HIGH

INPUT IMPEDANCE INVERTING AMPLIFIER)

The simplest closed-loop circuit that can be made does not

require any resistors and is shown in Figure 68. In this circuit,

β1 is equal to 0, and β2 is equal to 1. The gain is equal to 2.

A more intuitive means to figure the gain is by simple

inspection. +OUT is connected to −IN, whose voltage is equal

to the voltage at +IN under equilibrium conditions. Thus, +VOUT

is equal to VIN, and there is unity gain in this path. Because

−OUT has to swing in the opposite direction from +OUT due

to the common-mode constraint, its effect doubles the output

signal and produces a gain of 2.

One useful function that this circuit provides is a high input

impedance inverter. If +OUT is ignored, there is a unity-gain,

high input impedance amplifier formed from +IN to −OUT.

Most traditional op amp inverters have relatively low input

impedances, unless they are buffered with another amplifier.

VOCM has been assumed to be at midsupply. Because there is still

the constraint from the above discussion that +VOUT must equal

VIN, changing the VOCM voltage does not change +VOUT (= VIN).

Therefore, the effect of changing VOCM must show up at −OUT.

For example, if VOCM is raised by 1 V, then −VOUT must go up by

2 V. This makes VOUT, cm also go up by 1 V, since it is defined as

the average of the two differential output voltages. This means

that the gain from VOCM to the differential output is 2.

AD8132

Rev. D | Page 22 of 32

OTHER β2 = 1 CIRCUITS

The preceding simple configuration with β2 = 1 and its gain of

2 is the highest gain circuit that can be made under this

condition. Since β1 was equal to 0, only higher β1 values are

possible. The circuits with higher values of β1 have gains lower

than 2. However, circuits with β1 equal to 1 are not practical

because they have no effective input and result in a gain of 0.

To increase β1 from 0, it is necessary to add two resistors in a

feedback network. A generalized circuit that has β1 with a value

higher than 0 is shown in Figure 67. A couple of different

convenient gains that can be created are a gain of 1, when β1 is

equal to 1/3, and a gain of 0.5, when β1 equals 0.6.

With β2 equal to 1 in these circuits, VOCM serves as the reference

voltage from which to measure the input voltage and the

individual output voltages. In general, when VOCM is varied in

these circuits, a differential output signal generates in addition

to VOUT, cm changing the same amount as the voltage change of

VOCM.

VARYING β2

While the circuit above sets β2 to 1, another class of simple

circuits can be made that sets β2 equal to 0. This means that

there is no feedback from +OUT to −IN. This class of circuits is

very similar to a conventional inverting op amp. However, the

AD8132 circuits have an additional output and common-mode

input that can be analyzed separately (see Figure 69).

With −IN connected to ground, +IN becomes a virtual ground

in the sense that the term is used for conventional op amps.

Both inputs must maintain the same voltage for equilibrium

operation; therefore, if one is set to ground, the other is driven

to ground. The input impedance can also be seen to be equal to

RG, just as in a conventional op amp.

In this case, however, the positive input and negative output are

used for the feedback network. Because a conventional op amp

does not have a negative output, only its inverting input can be

used for the feedback network. The AD8132 is symmetrical,

therefore, the feedback network on either side can be used to

produce the same results.

Because +IN is a summing junction, by analog-to-conventional

op amps, the gain from VIN to −OUT is −RF/RG. This holds true

regardless of the voltage on VOCM, and since +OUT moves the

same amount in the opposite direction from −OUT, the overall

gain is −2(RF/RG).

VOCM still governs VOUT, cm, so +OUT must be the only output

that moves when VOCM is varied. Because VOUT, cm is the average

of the two outputs, +OUT must move twice as far and in the

same direction as VOCM to create the proper VOUT, cm. Therefore,

the gain from VOCM to +OUT must be 2.

With β2 equal to 0 in these circuits, the gain can theoretically be

set to any value from close to 0 to infinity, just as it can with a

conventional op amp in the inverting mode. However, practical

real-world limitations and parasitics limit the range of

acceptable gain to more modest values.

β1 = 0

There is yet another class of circuits where there is no feedback

from −OUT to +IN. This is the case where β1 = 0. The

resistorless differential amplifier described above meets this

condition, but it was presented only with the condition that

β2 = 1. Recall that this circuit had a gain equal to 2.

If β2 decreases in this circuit from unity, a smaller part of

+VOUT is fed back to −IN and the gain increases (see

Figure 66). This circuit is very similar to a noninverting op

amp configuration, except for the presence of the additional

complementary output. Therefore, the overall gain is twice that

of a noninverting op amp or 2 × (1 + RF2/RG2) or 2 × (1/β2).

Once again, varying VOCM does not affect both outputs in the

same way; therefore, in addition to varying VOUT, cm with unity

gain, there is also an effect on VOUT, dm by changing VOCM.

ESTIMATING THE OUTPUT NOISE VOLTAGE

Similar to the case of a conventional op amp, the differential

output errors (noise and offset voltages) can be estimated by

multiplying the input referred terms, at +IN and −IN, by the

circuit noise gain. The noise gain is defined as

⎟

⎠

⎞

⎜

⎝

⎛

To compute the total output referred noise for the circuit of

Figure 64, consideration must also be given to the contribution

of the resistors RF and RG. Refer to Table 10 for estimated output

noise voltage densities at various closed-loop gains.

Table 10. Recommended Resistor Values and Noise

Performance for Specific Gains

Gain

(Ω)

Bandwidth

−3 dB

(MHz)

Output

Noise

AD8132

Only

(nV/√Hz)

Output

Noise

AD8132 +

RG, RF

(nV/√Hz)

1 499 499 360 16 17

2 499 1.0 k 160 24.1 26.1

5 499 2.49 k 65 48.4 53.3

10 499 4.99 k 20 88.9 98.6

AD8132

Rev. D | Page 23 of 32

When using the AD8132 in gain configurations where β1 ≠ β2,

differential output noise appears due to input-referred voltage

noise in the VOCM circuitry according to the formula

⎥

⎦

⎤

⎢

⎣

⎡

−

=β2β1

β2β1

2NOCMOND VV

where VOND is the output differential noise, and VNOCM is the

input-referred voltage noise on VOCM.

CALCULATING AN APPLICATION CIRCUIT’S INPUT

IMPEDANCE

The effective input impedance of a circuit, such as that in

Figure 64, at +DIN and −DIN, depends on whether the amplifier

is being driven by a single-ended or differential signal source.

For balanced differential input signals, the input impedance

(RIN, dm) between the inputs (+DIN and −DIN) is simply

dmIN, RR ×= 2

In the case of a single-ended input signal (for example, if −DIN is

grounded and the input signal is applied to +DIN), the input

impedance becomes

()

⎟

⎠

⎞

⎜

⎝

⎛

+×

−

dmIN,

The circuit’s input impedance is effectively higher than it would

be for a conventional op amp connected as an inverter because

a fraction of the differential output voltage appears at the inputs

as a common-mode signal, partially bootstrapping the voltage

across the input resistor, RG.

INPUT COMMON-MODE VOLTAGE RANGE IN

SINGLE-SUPPLY APPLICATIONS

The AD8132 is optimized for level-shifting ground referenced

input signals. For a single-ended input this would imply, for

example, that the voltage at −DIN in Figure 64 would be 0 V

when the amplifier’s negative power supply voltage (at V−) was

also set to 0 V.

SETTING THE OUTPUT COMMON-MODE VOLTAGE

The AD8132’s VOCM pin is internally biased at a voltage

approximately equal to the midsupply point (average value of

the voltage on V+ and V−). Relying on this internal bias results

in an output common-mode voltage that is within

approximately 100 mV of the expected value.

In cases where more accurate control of the output common-

mode level is required, it is recommended that an external

source or resistor divider (with RSOURCE < 10 kΩ) be used. The

output common-mode offset values in the Specifications

section assume the VOCM input is driven by a low impedance

voltage source.

DRIVING A CAPACITIVE LOAD

A purely capacitive load can react with the pin and bond-wire

inductance of the AD8132, resulting in high frequency ringing

in the pulse response. One way to minimize this effect is to

place a small capacitor across each of the feedback resistors. The

added capacitance should be small to avoid destabilizing the

amplifier. An alternative technique is to place a small resistor in

series with the amplifier’s outputs, as shown in Figure 60.

AD8132

Rev. D | Page 24 of 32

LAYOUT, GROUNDING, AND BYPASSING

As a high speed part, the AD8132 is sensitive to the PCB

environment in which it operates. Realizing its superior

specifications requires attention to various details of good high

speed PCB design.

The first requirement is a good solid ground plane that covers

as much of the board area around the AD8132 as possible. The

only exception to this is that the two input pins (Pins 1 and 8)

should be kept a few millimeters from the ground plane, and

ground should be removed from inner layers and the opposite

side of the board under the input pins. This minimizes the stray

capacitance on these nodes and helps preserve the gain flatness

vs. the frequency.

The power supply pins should be bypassed as close as possible

to the device to the nearby ground plane. Good high frequency

ceramic chip capacitors should be used. This bypassing should

be done with a capacitance value of 0.01 µF to 0.1 µF for each

supply. Further away, low frequency bypassing should be

provided with 10 µF tantalum capacitors from each supply to

ground.

The signal routing should be short and direct in order to avoid

parasitic effects. Wherever there are complementary signals, a

symmetrical layout should be provided to the extent possible to

maximize the balance performance. When running differential

signals over a long distance, the traces on the PCB should be

close together or any differential wiring should be twisted

together to minimize the area of the loop that is formed. This

reduces the radiated energy and makes the circuit less

susceptible to interference.

CIRCUITS

01035-065

Figure 65. Typical Four-Resistor Feedback Circuit

01035-066

Figure 66. Typical Circuit with β1 = 0

01035-067

Figure 67. Typical Circuit with β2 = 1

01035-068

Figure 68. Resistorless G = 2 Circuit with β1 = 0

01035-069

Figure 69. Typical Circuit with β2 = 0

AD8132

Rev. D | Page 25 of 32

APPLICATIONS

A/D DRIVER

Many of the newer high speed ADCs are single-supply and have

differential inputs. Thus, the driver for these devices should be

able to convert from a single-ended to a differential signal and

provide output common-mode level-shifting in addition to

having low distortion and noise. The AD8132 conveniently

performs these functions when driving the AD9203, a 10-bit,

40 MSPS ADC.

In Figure 71, a 1 V p-p signal drives the input of an AD8132

configured for unity gain. Both the AD8132 and the AD9203

are powered from a single 3 V supply. A voltage divider biases

VOCM at midsupply, which in turn drives VOUT, cm to half of the

supply voltage. This is within the common-mode range of the

AD9203.

Between the A/D and the driver is a 1-pole, differential filter

that helps to filter some of the noise and assists the switched-

capacitor inputs of the A/D. Each of the A/D inputs is driven by

a 0.5 V p-p signal that ranges from 1.25 V dc to 1.75 V dc.

Figure 70 is an FFT plot of the performance of the circuit when

running at a clock rate of 40 MSPS and an input frequency of

2.5 MHz.

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0

FUND

2ND

3RD 4TH

5TH 7TH

8TH

9TH

6TH

= 40MHz

= 2.5MHz

INPUT FREQUENCY (MHz)

OUTPUT (dBc)

01035-071

Figure 70. FTT Response for AD8132 Driving AD9203

BALANCED CABLE DRIVER

When driving a twisted pair cable, it is desirable to drive only a

pure differential signal onto the line. If the signal is purely

differential (i.e., fully balanced), and the transmission line is

twisted and balanced, there is a minimum radiation of any

signal.

The complementary electrical fields are mostly confined to the

space between the two twisted conductors and does not

significantly radiate out from the cable. The current in the cable

creates magnetic fields that radiate to some degree. However,

the amount of radiation is mitigated by the twists, because for

each twist, the two adjacent twists have an opposite polarity

magnetic field. If the twist pitch is tight enough, these small

magnetic field loops contain most of the magnetic flux, and the

magnetic far-field strength is negligible.

0.1µF 10µF

348Ω

0.1µF

348Ω

49.9Ω

348Ω

24.9Ω

10kΩ

1V p-p

348Ω

60.4Ω

20pF

AINN

AINP

AVDD DRVDD

AVSS DRVSS

AD9203

DIGITAL

OUTPUTS

0.1µF0.1µF

AD8132

27 1

01035-070

Figure 71. AD8132 Driving AD9203, a 10-Bit, 40 MSPS ADC

AD8132

Rev. D | Page 26 of 32

499Ω

523Ω

1kΩ

10µF

+5V

AD8132

0.1µF

49.9Ω

50Ω

OURCE

0.1µF

+0.1µF

10µF

–5V

49.9Ω

TWISTED

PAIR

100Ω

AD830

+0.1µF

10µF

–5V

10µF

+5V

0.1µF

OUT

01035-072

Figure 72. Balanced Line Driver and Receiver Using AD8132 and AD830

Any imbalance in the differential drive signal appears as a

common-mode signal on the cable. This is the equivalent of a

single wire that is driven with the common-mode signal. In this

case, the wire acts as an antenna and radiates. Thus, in order to

minimize radiation when driving differential twisted pair

cables, the differential drive signal should be very well-

balanced.

The common-mode feedback loop in the AD8132 helps to

minimize the amount of common-mode voltage at the output,

and can therefore be used to create a well-balanced differential

line driver. Figure 72 shows an application that uses an AD8132

as a balanced line driver and an AD830 as a differential receiver

configured for unity gain. This circuit was operated with 10 m

of Category 5 cable.

TRANSMIT EQUALIZER

Any length of transmission line attenuates the signals it carries.

This effect is worse at higher frequencies than at low

frequencies. One way to compensate for this is to provide an

equalizer circuit that boosts the higher frequencies in the

transmitter circuit, so that at the receive end of the cable, the

attenuation effects are diminished.

By lowering the impedance of the RG component of the

feedback network at a higher frequency, the gain can be

increased at a high frequency. Figure 73 shows the gain of a two

line driver that has its RG resistors shunted by 10 pF capacitors.

The effect of this is shown in the frequency response plot of

Figure 74.

249Ω

49.9Ω

10pF 499Ω

10pF

249Ω

24.9Ω

49.9Ω

499Ω

49.9Ω

100ΩV

OUT

01035-073

Figure 73. Frequency Boost Circuit

11000

–10

–20

–30

–40

–50

–60

–70

–80

OUT

(dB)

10 100

FREQUENCY (MHz)

01035-074

Figure 74. Frequency Response for transmit Boost Circuit

LOW-PASS DIFFERENTIAL FILTER

Similar to an op amp, various types of active filters can be

created with the AD8132. These can have single-ended inputs

and differential outputs, which can provide an antialias function

when driving a differential ADC.

Figure 75 is a schematic of a low-pass, multiple feedback filter.

The active section contains two poles, and an additional pole is

added at the output. The filter was designed to have a −3 dB

frequency of 1 MHz. The actual −3 dB frequency was measured

to be 1.12 MHz, as shown in Figure 76.

33pF

2.15kΩ

953Ω

33pF

2.15kΩ

100pF

2kΩ

24.9Ω

49.9Ω

549Ω

200pF

OUT

01035-075

Figure 75. 1 MHz, 3-Pole Differential Output,

Low-Pass, Multiple Feedback Filter

AD8132

Rev. D | Page 27 of 32

FREQUENCY (Hz)

10k

–10

–20

–30

–40

–50

–60

–70

–80

–90 100k 1M 10M 100M

OUT

(dB)

01035-076

Figure 76. Frequency Response of 1 MHz Low-Pass Filter

HIGH COMMON-MODE OUTPUT IMPEDANCE

AMPLIFIER

Changing the connection to VOCM (Pin 2) can change the

common-mode from low impedance to high impedance. If

VOCM is actively set to a particular voltage, the AD8132 tries to

force VOUT, cm to the same voltage with a relatively low output

impedance. All the previous analysis assumed that this output

impedance is arbitrarily low enough to drive the load condition

in the circuit.

However, there are some applications that benefit from a high

common-mode output impedance. This can be accomplished

with the circuit shown in Figure 77.

348Ω

10Ω

1kΩ

49.9Ω

01035-077

Figure 77. High Common-Mode, Output Impedance, Differential Amplifier

VOCM is driven by a resistor divider that measures the output

common-mode voltage. Thus, the common-mode output

voltage takes on the value that is set by the driven circuit. In this

case, it comes from the center point of the termination at the

receive end of a 10 m length of Category 5 twisted pair cable.

If the receive end, common-mode voltage is set to ground, it is

well-defined at the receive end. Any common-mode signal that

is picked up over the cable length due to noise appears at the

transmit end and must be absorbed by the transmitter. Thus, it

is important that the transmitter have adequate common-mode

output range to absorb the full amplitude of the common-mode

signal coupled onto the cable and therefore prevent clipping.

Another way to look at this is that the circuit performs what is

sometimes called transformer action. One main difference is

that the AD8132 passes dc while transformers do not.

A transformer can also be easily configured to have either a

high or low common-mode output impedance. If the

transformer’s center tap is connected to a solid voltage

reference, it sets the common-mode voltage on the secondary

side of the transformer. In this case, if one of the differential

outputs is grounded, the other output will have only half of the

differential output signal. This keeps the common-mode voltage

at ground, where it is required to be due to the center tap

connection. This is analogous to the AD8132 operating with a

low output impedance common-mode (see Figure 78).

DIFF

OCM

01035-078

Figure 78. Transformer Whose Low Output

Impedance Secondary Is Set at VOCM

If the center tap of the secondary of a transformer is allowed to

float as shown in Figure 79 (or if there is no center tap), the

transformer will have a high common-mode output impedance.

This means that the common mode of the secondary is

determined by what it is connected to and not by anything to do

with the transformer itself.

If one of the differential ends of the transformer is grounded,

the other end swings with the full output voltage. This means

that the common-mode of the output voltage is one-half of the

differential output voltage. However, this shows that the

common-mode is not forced via a low impedance to a given

voltage. The common-mode output voltage can be changed

easily to any voltage through its other output terminals.

The AD8132 can exhibit the same performance when one of the

outputs in Figure 77 is grounded. The other output swings at the

full differential output voltage. The common-mode signal is

measured by the voltage divider across the outputs and input to

VOCM. This then drives VOUT, cm to the same level. At higher

frequencies, it is important to minimize the capacitance on the

VOCM node or else phase shifts can compromise the

performance. The voltage divider resistances can also be

lowered for better frequency response.

DIFF

01035-079

Figure 79. Transformer with High Output Impedance Secondary

FULL-WAVE RECTIFIER

The balanced outputs of the AD8132, along with a couple of

Schottky diodes, can create a very high speed, full-wave rectifier.

Such circuits are useful for measuring ac voltages and other

computational tasks.

AD8132

Rev. D | Page 28 of 32

Figure 80 shows the configuration of such a circuit. Each of the

AD8132 outputs drives the anode of an HP2835 Schottky diode.

These Schottky diodes were chosen for their high speed

operation. At lower frequencies (approximately lower than

10 MHz), a silicon signal diode, such as a 1N4148, can be used.

The cathodes of the two diodes are connected together, and this

output node is connected to ground by a 100 Ω resistor.

348

Ω

348

Ω

348

Ω

348

Ω

+5V

–5V

100

Ω

24.9

Ω

49.9

Ω

HP2835 V

OUT

+5V

CR1

10k

Ω

01035-080

Figure 80. Full-Wave Rectifier

The diodes should be operated such that they are slightly

forward-biased when the differential output voltage is 0. For the

Schottky diodes, this is approximately 400 mV. The forward

biasing can be conveniently adjusted by CR1, which, in this

circuit, raises and lowers VOUT, cm without creating a differential

output voltage.

One advantage of this circuit is that the feedback loop is never

momentarily opened while the diodes reverse their polarity

within the loop. This is the scheme that is sometimes used for

full-wave rectifiers that use conventional op amps. These

conventional circuits do not work well at frequencies above

approximately 1 MHz.

If there is not enough forward-bias (VOUT, cm too low), the lower

sharp cusps of the full-wave rectified output waveform will be

rounded off. Also, as the frequency increases, there tends to be

some rounding of the lower cusps. The forward bias can be

increased to yield sharper cusps at higher frequencies.

There is not a reliable, entirely quantifiable means to measure

the performance of a full-wave rectifier. Since the ideal

waveform has periodic sharp discontinuities, it should have

(mostly even) harmonics that have no upper bound on the

frequency. However, for a practical circuit, as the frequency

increases, the higher harmonics become attenuated and the

sharp cusps that are present at low frequencies become

significantly rounded.

The circuit was run at a frequency up to 300 MHz and, while it

was still functional, the major harmonic that remained in the

output was the second. This made it look like a sine wave at

600 MHz. Figure 81 is an oscilloscope plot of the output when

driven by a 100 MHz, 2.5 V p-p input.

Sometimes a second harmonic generator is actually useful for

creating a clock to oversample a DAC by a factor of two. If the

output of this circuit is run through a low-pass filter, it can be

used as a second harmonic generator.

100mV 2ns

01035-081

Figure 81. Full-Wave Rectifier Response with 100 MHz Input

AD8132

Rev. D | Page 29 of 32

OUTLINE DIMENSIONS

0.25 (0.0098)

0.17 (0.0067)

1.27 (0.0500)

0.40 (0.0157)

0.50 (0.0196)

0.25 (0.0099)× 45°

8°

0°

1.75 (0.0688)

1.35 (0.0532)

SEATING

PLANE

0.25 (0.0098)

0.10 (0.0040)

5.00 (0.1968)

4.80 (0.1890)

4.00 (0.1574)

3.80 (0.1497)

1.27 (0.0500)

BSC

6.20 (0.2440)

5.80 (0.2284)

0.51 (0.0201)

0.31 (0.0122)

COPLANARITY

0.10

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

COMPLIANT TO JEDEC STANDARDS MS-012AA

Figure 82. 8-Lead Standard Small Outline Package [SOIC]

Narrow Body (R-8)

Dimensions shown in millimeters and (inches)

0.80

0.60

0.40

8°

0°

4.90

BSC

PIN 1 0.65 BSC

3.00

BSC

SEATING

PLANE

0.15

0.00

0.38

0.22

1.10 MAX

3.00

BSC

COPLANARITY

0.10

0.23

0.08

COMPLIANT TO JEDEC STANDARDS MO-187AA

Figure 83. 8-Lead Mini Small Outline Package [MSOP]

(RM-8)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Package Description Package Option Branding

AD8132AR −40°C to +125°C 8-Lead SOIC R-8

AD8132AR-REEL −40°C to +125°C 8-Lead SOIC, 13" Tape and Reel of 2,500 R-8

AD8132AR-REEL7 −40°C to +125°C 8-Lead SOIC, 7" Tape and Reel of 1,000 R-8

AD8132ARZ1 −40°C to +125°C 8-Lead SOIC R-8

AD8132ARZ-REEL1 −40°C to +125°C 8-Lead SOIC, 13" Tape and Reel of 2,500 R-8

AD8132ARZ-REEL71 −40°C to +125°C 8-Lead SOIC, 7" Tape and Reel of 1,000 R-8

AD8132ARM −40°C to +125°C 8-Lead MSOP RM-8 HMA

AD8132ARM-REEL −40°C to +125°C 8-Lead MSOP, 13" Tape and Reel of 3,000 RM-8 HMA

AD8132ARM-REEL7 −40°C to +125°C 8-Lead MSOP, 7" Tape and Reel of 1,000 RM-8 HMA

AD8132ARMZ1 −40°C to +125°C 8-Lead MSOP RM-8 HMA

AD8132ARMZ-REEL1 −40°C to +125°C 8-Lead MSOP, 13" Tape and Reel of 3,000 RM-8 HMA

AD8132ARMZ-REEL71 −40°C to +125°C 8-Lead MSOP, 7" Tape and Reel of 1,000 RM-8 HMA

1 Z = Pb-free part

AD8132

Rev. D | Page 30 of 32

NOTES

AD8132

Rev. D | Page 31 of 32

NOTES

AD8132

Rev. D | Page 32 of 32

NOTES

registered trademarks are the property of their respective owners.

C01035–0–12/04(D)