1
Data sheet acquired from Harris Semiconductor
SCHS047G
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
CD4051B, CD4052B, CD4053B
Features
• Wide Range of Digital and Analog Signal Levels
- Digital . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3V to 20V
- Analog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤20VP-P
• Low ON Resistance, 125Ω(Typ) Over 15VP-P Signal Input
Range for VDD-VEE = 18V
• High OFF Resistance, Channel Leakage of ±100pA (Typ)
at VDD-VEE = 18V
• Logic-Level Conversion for Digital Addressing Signals of
3V to 20V (VDD-VSS = 3V to 20V) to Switch Analog
Signals to 20VP-P (VDD-VEE = 20V)
• Matched Switch Characteristics, rON = 5Ω (Typ) for
VDD-VEE = 15V
• Very Low Quiescent Power Dissipation Under All Digital-
Control Input and Supply Conditions, 0.2µW (Typ) at
VDD-VSS = VDD-VEE = 10V
• Binary Address Decoding on Chip
• 5V, 10V, and 15V Parametric Ratings
• 100% Tested for Quiescent Current at 20V
• Maximum Input Current of 1µA at 18V Over Full Package
Temperature Range, 100nA at 18V and 25oC
• Break-Before-Make Switching Eliminates Channel
Overlap
Applications
• Analog and Digital Multiplexing and Demultiplexing
• A/D and D/A Conversion
• Signal Gating
CMOS Analog Multiplex ers/Dem ultiple x ers
with Logic Level Conversion
The CD4051B, CD4052B , and CD4053B analog m ultiple xers
are digitally-controlled analog switches having low ON
impedance and very low OFF leakage current. Control of
analog signals up to 20VP-P can be achieved by digital
signal amplitudes of 4.5V to 20V (if VDD-VSS = 3V, a
VDD-VEE of up to 13V can be controlled; for VDD-VEE level
differences above 13V, a VDD-VSS of at least 4.5V is
required). For example, if VDD = +4.5V, VSS = 0V, and
VEE = -13.5V, analog signals from -13.5V to +4.5V can be
controlled by digital inputs of 0V to 5V. These multiplexer
circuits dissipate extremely low quiescent power over the
full VDD-VSS and VDD-VEE supply-voltage ranges,
independent of the logic state of the control signals. When
a logic “1” is present at the inhibit input terminal, all
channels are off.
The CD4051B is a single 8-Channel multiplexer having three
binary control inputs, A, B, and C, and an inhibit input. The
three binary signals select 1 of 8 channels to be turned on,
and connect one of the 8 inputs to the output.
The CD4052B is a differential 4-Channel multiplexer having
two binary control inputs, A and B, and an inhibit input. The
two binary input signals select 1 of 4 pairs of channels to be
turned on and connect the analog inputs to the outputs.
The CD4053B is a triple 2-Channel multiplexer having three
separate digital control inputs, A, B, and C, and an inhibit
input. Each control input selects one of a pair of channels
which are connected in a single-pole, double-throw
configuration.
When these devices are used as demultiplexers, the
“CHANNEL IN/OUT” terminals are the outputs and the
“COMMON OUT/IN” terminals are the inputs.
NOTE: When ordering, use the entire part number. The suffixes 96
and R denote tape and reel. The suffix T denotes a small-quantity
reel of 250.
Ordering Information
PART NUMBER TEMP. RANGE
(oC) PACKAGE
CD4051BF3A, CD4052BF3A,
CD4053BF3A -55 to 125 16 Ld CERAMIC
DIP
CD4051BE, CD4052BE,
CD4053BE -55 to 125 16 Ld PDIP
CD4051BM, CD4051BMT,
CD4051BM96
CD4052BM, CD4052BMT,
CD4052BM96
CD4053BM, CD4053BMT,
CD4053BM96
-55 to 125 16 Ld SOIC
CD4051BNSR, CD4052BNSR,
CD4053BNSR -55 to 125 16 Ld SOP
CD4051BPW, CD4051BPWR,
CD4052BPW, CD4052BPWR
CD4053BPW, CD4053BPWR
-55 to 125 16 Ld TSSOP
August 1998 - Revised October 2003
[ /Title
(CD405
1B,
CD4052
B,
CD4053
B)
/Sub-
ject
(CMOS
Analog
Multi-
plex-
ers/Dem
ultiplex-
ers with
Logic
Level
Conver-
sion)
/Author
()
/Key-
words
(Harris
Semi-
conduc-
tor,
CD4000
2
Pinouts
CD4051B (PDIP, CDIP, SOIC, SOP, TSSOP)
TOP VIEW CD4052B (PDIP, CDIP, SOP, TSSOP)
TOP VIEW
CD4053B (PDIP, CDIP, SOP, TSSOP)
TOP VIEW
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
4
6
COM OUT/IN
7
5
INH
VSS
VEE
VDD
1
0
3
A
B
C
2
CHANNELS IN/OU
T
CHANNELS
IN/OUT
CHANNELS
IN/OUT
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
0
2
COMMON “Y” OUT/IN
3
1
INH
VSS
VEE
VDD
1
COMMON “X” OUT/IN
0
3
A
B
2
Y CHANNELS
IN/OUT
Y CHANNELS
IN/OUT
X CHANNELS
IN/OUT
X CHANNELS
IN/OUT
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
by
bx
cy
OUT/IN CX OR CY
IN/OUT CX
INH
VSS
VEE
VDD
OUT/IN ax OR ay
ay
ax
A
B
C
OUT/IN bx OR by
IN/OUT
IN/OUT
Functional Block Diagrams
CD4051B
11
10
9
6
A †
B †
C †
INH †
134 2 5 1 12 15 14
TG
TG
TG
TG
TG
TG
TG
TG
3
COMMON
OUT/IN
01234567
BINARY
TO
1 OF 8
DECODER
WITH
INHIBIT
LOGIC
LEVEL
CONVERSION
8 7
VSS VEE
16 VDD
CHANNEL IN/OUT
†All inputs are protected by standard CMOS protection network.
CD4051B, CD4052B, CD4053B
3
CD4052B
CD4053B
Functional Block Diagrams (Continued)
1211 15 14
0123
3210
X CHANNELS IN/OUT
Y CHANNELS IN/OUT
BINARY
TO
1 OF 4
DECODER
WITH
INHIBIT
13
3
COMMON Y
OUT/IN
COMMON X
OUT/IN
78
16
6
9
10
A †
B †
INH †
VSS VEE
VDD
TG
TG
TG
TG
TG
TG
TG
TG
4251
LOGIC
LEVEL
CONVERSION
11
10
9
6
A †
B †
C †
INH †
123 5 1 2 13
TG
TG
TG
TG
TG
TG
4
COMMON
OUT/IN
axaybxbycxcy
87
VSS VEE
16 VDD
IN/OUT
15
14
BINARY TO
1 OF 2
DECODERS
WITH
INHIBIT
LOGIC
LEVEL
CONVERSION
VDD
†All inputs are protected by standard CMOS protection network.
COMMON
OUT/IN
COMMON
OUT/IN
ax OR ay
bx OR by
cx OR cy
CD4051B, CD4052B, CD4053B
4
TRUTH TABLES
INPUT STATES
“ON” CHANNEL(S)INHIBIT C B A
CD4051B
0000 0
0001 1
0010 2
0011 3
0100 4
0101 5
0110 6
0111 7
1 X X X None
CD4052B
INHIBIT B A
0 0 0 0x, 0y
0 0 1 1x, 1y
0 1 0 2x, 2y
0 1 1 3x, 3y
1 X X None
CD4053B
INHIBIT A OR B OR C
0 0 ax or bx or cx
0 1 ay or by or cy
1 X None
X = Don’t Care
CD4051B, CD4052B, CD4053B
5
Absolute Maximum Ratings Thermal Information
Supply Voltage (V+ to V-)
Voltages Referenced to VSS Terminal . . . . . . . . . . . -0.5V to 20V
DC Input Voltage Range . . . . . . . . . . . . . . . . . . -0.5V to VDD +0.5V
DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . . ±10mA
Operating Conditions
Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Package Thermal Impedance, θJA (see Note 1):
E (PDIP) package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67oC/W
M (SOIC) package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73oC/W
NS (SOP) package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64oC/W
PW (TSSOP) package. . . . . . . . . . . . . . . . . . . . . . . . . . 108oC/W
Maximum Junction Temperature (Ceramic Package) . . . . . . . . .175oC
Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC
Maximum Storage Temperature Range. . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .265oC
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.
Electrical Specifications Common Conditions Here: If Whole Table is For the Full Temp. Range, VSUPPLY = ±5V, AV = +1,
RL = 100Ω, Unless Otherwise Specified (Note 3)
PARAMETER
CONDITIONS LIMITS AT INDICATED TEMPERATURES (oC)
UNITSVIS (V) VEE (V) VSS (V) VDD (V) -55 -40 85 125
25
MIN TYP MAX
SIGNAL INPUTS (VIS) AND OUTPUTS (VOS)
Quiescent Device
Current, IDD Max - - - 5 5 5 150 150 - 0.04 5 µA
- - - 10 10 10 300 300 - 0.04 10 µA
- - - 15 20 20 600 600 - 0.04 20 µA
- - - 20 100 100 3000 3000 - 0.08 100 µA
Drain to Source ON
Resistance rON Max
0≤ VIS ≤ VDD
- 0 0 5 800 850 1200 1300 - 470 1050 Ω
- 0 0 10 310 330 520 550 - 180 400 Ω
- 0 0 15 200 210 300 320 - 125 240 Ω
Change in ON
Resistance (Between
Any Two Channels),
∆rON
- 0 0 5 -----15 - Ω
- 0 010-----10 - Ω
- 0 015----- 5 - Ω
OFF Channel Leakage
Current: Any Channel
OFF (Max) or ALL
ChannelsOFF (Common
OUT/IN) (Max)
-0018±100 (Note 2) ±1000 (Note 2) - ±0.01 ±100
(Note 2) nA
Capacitance: - -5 5- 5
Input, CIS ----- 5 - pF
Output, COS
CD4051 -----30 - pF
CD4052 -----18 - pF
CD4053 ----- 9 - pF
Feedthrough
CIOS -----0.2 - pF
Propagation Delay Time
(Signal Input to Output VDD RL = 200kΩ,
CL = 50pF,
tr, tf = 20ns
5 -----3060ns
10-----1530ns
15-----1020ns
CD4051B, CD4052B, CD4053B
6
CONTROL (ADDRESS OR INHIBIT), VC
Input Low Voltage, VIL,
Max VIL = VDD
through
1kΩ;
VIH = VDD
through
1kΩ
VEE = VSS,
RL = 1kΩ to VSS,
IIS < 2µA on All
OFF Channels
5 1.5 1.5 1.5 1.5 - - 1.5 V
103333 - - 3 V
154444 - - 4 V
Input High Voltage, VIH,
Min 5 3.5 3.5 3.5 3.5 3.5 - - V
1077777 - - V
15 11 11 11 11 11 - - V
Input Current, IIN (Max) VIN = 0, 18 18 ±0.1 ±0.1 ±1±1-±10-5 ±0.1 µA
Propagation Delay Time:
Address-to-Signal
OUT(ChannelsONor
OFF) See Figures 10,
11, 14
tr, tf = 20ns,
CL = 50pF,
RL = 10kΩ
0 0 5 -----450720ns
0 010-----160320ns
0 015-----120240ns
-5 0 5 -----225450ns
Propagation Delay Time:
Inhibit-to-Signal OUT
(Channel Turning ON)
See Figure 11
tr, tf = 20ns,
CL = 50pF,
RL = 1kΩ
0 0 5 -----400720ns
0 010-----160320ns
0 015-----120240ns
-100 5 -----200400ns
Propagation Delay Time:
Inhibit-to-Signal OUT
(Channel Turning
OFF) See Figure 15
tr, tf = 20ns,
CL = 50pF,
RL = 10kΩ
0 0 5 -----200450ns
0 010-----90210ns
0 015-----70160ns
-100 5 -----130300ns
Input Capacitance, CIN
(Any Address or Inhibit
Input)
----- 5 7.5pF
NOTE:
2. Determined by minimum feasible leakage measurement for automatic testing.
Electrical Specifications
PARAMETER
TEST CONDITIONS LIMITS
UNITSVIS (V) VDD (V) RL (kΩ) TYP
Cutoff (-3dB) Frequency Chan-
nel ON (Sine Wave Input) 5 (Note 3) 10 1 VOS at Common OUT/IN CD4053 30 MHz
VEE = VSS, CD4052 25 MHz
CD4051 20 MHz
VOS at Any Channel 60 MHz
Electrical Specifications Common Conditions Here: If Whole Table is For the Full Temp. Range, VSUPPLY = ±5V, AV = +1,
RL = 100Ω, Unless Otherwise Specified (Continued) (Note 3)
PARAMETER
CONDITIONS LIMITS AT INDICATED TEMPERATURES (oC)
UNITSVIS (V) VEE (V) VSS (V) VDD (V) -55 -40 85 125
25
MIN TYP MAX
20LogVOS
VIS
------------3dB–=
CD4051B, CD4052B, CD4053B
7
Total Harmonic Distortion, THD 2 (Note 3) 5 10 0.3 %
3 (Note 3) 10 0.2 %
5 (Note 3) 15 0.12 %
VEE = VSS, fIS = 1kHz Sine Wa v e %
-40dB Feedthrough Frequency
(All Channels OFF) 5 (Note 3) 10 1 VOS at Common OUT/IN CD4053 8 MHz
VEE = VSS, CD4052 10 MHz
CD4051 12 MHz
VOS at Any Channel 8 MHz
-40dB Signal Crosstalk
Frequency 5 (Note 3) 10 1 Between Any 2 Channels 3 MHz
VEE = VSS, Between Sections,
CD4052 Only Measured on Common 6 MHz
Measured on Any Chan-
nel 10 MHz
Between Any Two
Sections, CD4053
Only
In Pin 2, Out Pin 14 2.5 MHz
In Pin 15, Out Pin 14 6 MHz
Address-or-Inhibit-to-Signal
Crosstalk -1010
(Note 4) 65 mVPEAK
VEE =0,VSS =0,tr,tf=20ns, VCC
= VDD - VSS (Square Wave) 65 mVPEAK
NOTES:
3. Peak-to-Peak voltage symmetrical about
4. Both ends of channel.
Typical Performance Curves
FIGURE 1. CHANNEL ON RESISTANCE vs INPUT SIGNAL
VOLTAGE (ALL TYPES) FIGURE 2. CHANNEL ON RESISTANCE vs INPUT SIGNAL
VOLTAGE (ALL TYPES)
Electrical Specifications
PARAMETER
TEST CONDITIONS LIMITS
UNITSVIS (V) VDD (V) RL (kΩ) TYP
20LogVOS
VIS
------------40d
B
–=
20LogVOS
VIS
------------40dB–=
VDD VEE
–
2
-----------------------------
-4 -3 -2 -1 0 1 2 3 4
0
100
200
300
400
500
600
VIS, INPUT SIGNAL VOLTAGE (V)
rON, CHANNEL ON RESISTANCE (Ω)
TA = 125oC
TA = -55oC
TA = 25oC
VDD - VEE = 5V
5
-10 -7.5 -5 -2.5 0 2.5 5 7.5 1
0
0
50
100
150
200
250
300
VIS, INPUT SIGNAL VOLTAGE (V)
rON, CHANNEL ON RESISTANCE (Ω)
TA = 125oC
TA = 25oC
TA = -55oC
VDD - VEE = 10V
CD4051B, CD4052B, CD4053B
8
FIGURE 3. CHANNEL ON RESISTANCE vs INPUT SIGNAL
VOLTAGE (ALL TYPES) FIGURE 4. CHANNEL ON RESISTANCE vs INPUT SIGNAL
VOLTAGE (ALL TYPES)
FIGURE 5. ON CHARACTERISTICS FOR 1 OF 8 CHANNELS
(CD4051B) FIGURE 6. DYNAMIC POWER DISSIPATION vs SWITCHING
FREQUENCY (CD4051B)
FIGURE 7. DYNAMIC POWER DISSIPATION vs SWITCHING
FREQUENCY (CD4052B) FIGURE 8. DYNAMIC POWER DISSIPATION vs SWITCHING
FREQUENCY (CD4053B)
Typical Performance Curves (Continued)
-10 -7.5 -5 -2.5 0 2.5 5 7.5 10
0
100
200
300
400
600
500
VIS, INPUT SIGNAL VOLTAGE (V)
rON, CHANNEL ON RESISTANCE (Ω)
TA = 25oC
15V
10V
VDD - VEE = 5V
-10 -7.5 -5 -2.5 0 2.5 5 7.5 10
0
50
100
150
200
250
VIS, INPUT SIGNAL VOLTAGE (V)
rON, CHANNEL ON RESISTANCE (Ω)
VDD - VEE = 15V
TA = 125oC
TA = 25oC
TA = -55oC
-6 -4 -2 0 2 4 6
VIS, INPUT SIGNAL VOLTAGE (V)
VOS, OUTPUT SIGNAL VOLTAGE (V)
-6
-4
-2
0
2
4
6VDD = 5V
VSS = 0V
VEE = -5V
TA = 25oC
RL = 100kΩ, RL = 10kΩ
100Ω
500Ω
1kΩTA = 25oC
ALTERNATING “O”
CL = 50pF
AND “I” PATTERN
105
104
103
10
VDD = 15V
VDD = 5V
CL = 15pF
102
102
10
103
104
105
SWITCHING FREQUENCY (kHz)
PD, POWER DISSIPATION PACKAGE (µW)
1
TEST CIRCUIT
VDD
3
5
1011
6
7
8
14
15
1
2
13
12
4CL
CD4051
f
100Ω
100Ω
B/D
CD4029
VDD
ABC
9
Ι
VDD = 10V
10
5
104
103
10 102
102
10
103
104
105
SWITCHING FREQUENCY (kHz)
P
D
, POWER DISSIPATION PACKAGE (
µ
W)
1
VDD = 15V
VDD = 5V
TA = 25oC
ALTERNATING “O”
CL = 50pF
AND “I” PATTERN
VDD
3
5
10
11
6
78
14
15
1
213
12
4
CL
CD4052
f
100Ω
100Ω
B/D
CD4029
VDD
AB
9
Ι
TEST CIRCUIT
VDD = 10V
CL = 15pF
10
5
104
103
10
VDD = 15V
VDD = 10V
VDD = 5V
TA = 25oC
ALTERNATING “O”
CL = 50pF
AND “I” PATTERN
CL = 15pF
102
102
10
103
104
105
SWITCHING FREQUENCY (kHz)
P
D
, POWER DISSIPATION PACKAGE (
µ
W)
Ι
TEST CIRCUIT
VDD 9
3
5
10
11
6
78
14
15
1
2
13
12
4CL
CD4053
f
100Ω
100Ω
1
CD4051B, CD4052B, CD4053B
9
Test Circuits and Waveforms
FIGURE 9. TYPICAL BIAS VOLTAGES
FIGURE 10. WAVEFORMS, CHANNEL BEING TURNED ON
(RL = 1kΩ)FIGURE 11. WAVEFORMS, CHANNEL BEING TURNED OFF
(RL = 1kΩ)
FIGURE 12. OFF CHANNEL LEAKAGE CURRENT - ANY CHANNEL OFF
VDD = 5V
VSS = 0V
VEE = -7.5V 7
8
(B) (C) (D)
(A)
VDD = 7.5V
7.5V 1616 1616
7
87
8
VDD = 5V
VDD = 15V
VSS = 0V
VEE = 0V 7
8
5V
VEE = -10V
VSS = 0V VSS = 0V
5V
VEE = -5V
NOTE: The ADDRESS (digital-control inputs) and INHIBIT logic levels
are: “0” = VSS and “1” = VDD. The analog signal (through the TG) may
swing from VEE to VDD.
tf = 20ns
10%
10%
90%
50%
10%
50%
90%
10%
50%
90%
tr = 20ns
TURN-OFF TIME
TURN-ON TIME
tf = 20ns
10%
90%
50% 10%
50%
90%
10%
90%
tr = 20ns
TURN-OFF TIME TURN-ON
tPHZ TIME
VDD
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
IDD IDD IDD
VDD VDD
CD4053
CD4052
CD4051
CD4051B, CD4052B, CD4053B
10
FIGURE 13. OFF CHANNEL LEAKAGE CURRENT - ALL CHANNELS OFF
FIGURE 14. PROPAGATION DELAY - ADDRESS INPUT TO SIGNAL OUTPUT
FIGURE 15. PROPAGATION DELAY - INHIBIT INPUT TO SIGNAL OUTPUT
FIGURE 16. INPUT VOLTAGE TEST CIRCUITS (NOISE IMMUNITY)
Test Circuits and Waveforms (Continued)
VDD
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CD4052
IDD
VDD
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CD4051
IDD
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CD4053
IDD
VDD
VDD
CD4051
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VEE
VEE
VEE VEE VEE
VEE
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS CD4052 CD4053
CLOCK
IN
CLOCK
IN
CLOCK
IN
RL
RLRLCL
CL
CL
OUTPUT OUTPUT OUTPUT
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDD
VEE
tPHL AND tPLH
VSS CLOCK
IN
RL
OUTPUT
CD4051
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CD4052
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CD4053
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDD
VDD
VDD VDD
VDD
VDD VDD
VDD
OUTPUT OUTPUT
tPHL AND tPLH
tPHL AND tPLH
RLRL
VSS
CLOCK
IN
CLOCK
IN
VSS
VSS
VEE
VEE
50pF 50pF
VEE
VSS VSS
VSS VSS
VSS
VEE
VEE
50pF
CD4051B
VIL
VIH
VDD
VIH
VIL
1K
1K
µA
MEASURE < 2µA ON ALL
“OFF” CHANNELS (e.g., CHANNEL 6)
1
2
3
4
5
6
7
89
10
11
12
13
14
15
16 µA
VIL VIL
VIH VIH
1K 1K
VDD
MEASURE < 2µA ON ALL
“OFF” CHANNELS (e.g., CHANNEL by)
CD4053B
1
2
3
4
5
6
7
89
10
11
12
13
14
15
16
VIH
VIH
VIL
1K
1K
VDD
µA
MEASURE < 2µA ON ALL
“OFF” CHANNELS (e.g., CHANNEL 2x)
VIL
CD4052B
1
2
3
4
5
6
7
89
10
11
12
13
14
15
16
CD4051B, CD4052B, CD4053B
11
FIGURE 17. QUIESCENT DEVICE CURRENT FIGURE 18. CHANNEL ON RESISTANCE MEASUREMENT
CIRCUIT
FIGURE 19. INPUT CURRENT
FIGURE 20. FEEDTHROUGH (ALL TYPES) FIGURE 21. CROSSTALK BETWEEN ANY TWO CHANNELS
(ALL TYPES)
FIGURE 22. CROSSTALK BETWEEN DUALS OR TRIPLETS (CD4052B, CD4053B)
Test Circuits and Waveforms (Continued)
CD4051
CD4053
Ι
1
2
3
4
5
6
7
89
10
11
12
13
14
15
16
CD4052
Ι
1
2
3
4
5
6
7
89
10
11
12
13
14
15
16
VDD
VDD
X-Y
PLOTTER
X
Y
1kΩ
RANGE
TG
“ON”
KEITHLEY
160 DIGITAL
MULTIMETER
H.P.
MOSELEY
7030A
VSS
VDD
10kΩ
VDD
Ι
VDD
VSS CD4051
CD4053
VSS
NOTE: Measureinputssequentially,
to both VDD and VSS connect all
unused inputs to either VDD or VSS.
1
2
3
4
5
6
7
89
10
11
12
13
14
15
16
VDD
Ι
VDD
VSS CD4052 VSS
NOTE: Measureinputssequentially,
to both VDD and VSS connect all
unused inputs to either VDD or VSS.
1
2
3
4
5
6
7
89
10
11
12
13
14
15
16
RF
VM
VDD
OFF
CHANNEL
6
7
8
1K
5VP-P
OFF
CHANNEL
RL
COMMON
ON
CHANNEL
RL
RF
VM ON
CHANNEL RL
5VP-P
OFF
CHANNEL
RL
R
F
VM
5VP-P RF
VM
ON OR OFF
CHANNEL IN Y
RL
RL
ON OR OFF
CHANNEL IN X
CD4051B, CD4052B, CD4053B
12
Special Considerations
In applications where separate power sources are used to
drive VDD and the signal inputs, the VDD current capability
should exceed VDD/RL(RL= effective external load). This
provision avoids permanent current flow or clamp action on
the VDD supply when power is applied or removed from the
CD4051B, CD4052B or CD4053B.
FIGURE 23. TYPICAL TIME-DIVISION APPLICATION OF THE CD4052B
Test Circuits and Waveforms (Continued)
COMMUNICATIONS
LINK
DIFF.
AMPLIFIER/
LINE DRIVER
DIFF.
RECEIVER
DEMULTIPLEXING
DIFF.
MULTIPLEXING
DIFFERENTIAL
SIGNALS CD4052 CD4052
FIGURE 24. 24-TO-1 MUX ADDRESSING
A
B
E
1/2
CD4556
A
B
CCD4051B
INH
A
B
CCD4051B
INH
A
B
CCD4051B
INH
A
B
C
D
E
Q0
Q1
Q2
COMMON
OUTPUT
CD4051B, CD4052B, CD4053B
PACKAGE OPTION ADDENDUM
www.ti.com 5-Sep-2011
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
7901502EA ACTIVE CDIP J 16 1 TBD Call TI Call TI
8101801EA ACTIVE CDIP J 16 1 TBD Call TI Call TI
CD4051BE ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
CD4051BEE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
CD4051BF ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type
CD4051BF3A ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type
CD4051BF3AS2283 OBSOLETE CDIP J 16 TBD Call TI Call TI
CD4051BM ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD4051BM96 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD4051BM96E4 ACTIVE SOIC D 16 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD4051BM96G3 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM
CD4051BM96G4 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD4051BME4 ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD4051BMG4 ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD4051BMT ACTIVE SOIC D 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD4051BMTE4 ACTIVE SOIC D 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD4051BMTG4 ACTIVE SOIC D 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD4051BNSR ACTIVE SO NS 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD4051BNSRE4 ACTIVE SO NS 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD4051BNSRG4 ACTIVE SO NS 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 5-Sep-2011
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
CD4051BPW ACTIVE TSSOP PW 16 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD4051BPWE4 ACTIVE TSSOP PW 16 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD4051BPWG4 ACTIVE TSSOP PW 16 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD4051BPWR ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD4051BPWRE4 ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD4051BPWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD4052BE ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
CD4052BEE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
CD4052BF ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type
CD4052BF3A ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type
CD4052BM ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD4052BM96 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD4052BM96E4 ACTIVE SOIC D 16 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD4052BM96G3 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM
CD4052BM96G4 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD4052BME4 ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD4052BMG4 ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD4052BMT ACTIVE SOIC D 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD4052BMTE4 ACTIVE SOIC D 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 5-Sep-2011
Addendum-Page 3
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
CD4052BMTG4 ACTIVE SOIC D 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD4052BNSR ACTIVE SO NS 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD4052BNSRE4 ACTIVE SO NS 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD4052BNSRG4 ACTIVE SO NS 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD4052BPW ACTIVE TSSOP PW 16 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD4052BPWE4 ACTIVE TSSOP PW 16 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD4052BPWG4 ACTIVE TSSOP PW 16 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD4052BPWR ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD4052BPWRE4 ACTIVE TSSOP PW 16 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD4052BPWRG3 ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM
CD4052BPWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD4053BE ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
CD4053BEE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
CD4053BF ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type
CD4053BF3A ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type
CD4053BF3AS2283 OBSOLETE CDIP J 16 TBD Call TI Call TI
CD4053BM ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD4053BM96 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD4053BM96E4 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD4053BM96G3 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 5-Sep-2011
Addendum-Page 4
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
CD4053BM96G4 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD4053BME4 ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD4053BMG4 ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD4053BMT ACTIVE SOIC D 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD4053BMTE4 ACTIVE SOIC D 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD4053BMTG4 ACTIVE SOIC D 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD4053BNSR ACTIVE SO NS 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD4053BNSRE4 ACTIVE SO NS 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD4053BNSRG4 ACTIVE SO NS 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD4053BPW ACTIVE TSSOP PW 16 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD4053BPWE4 ACTIVE TSSOP PW 16 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD4053BPWG4 ACTIVE TSSOP PW 16 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD4053BPWR ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD4053BPWRE4 ACTIVE TSSOP PW 16 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD4053BPWRG3 ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM
CD4053BPWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PACKAGE OPTION ADDENDUM
www.ti.com 5-Sep-2011
Addendum-Page 5
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF CD4051B, CD4051B-MIL, CD4052B, CD4052B-MIL, CD4053B, CD4053B-MIL :
•Catalog: CD4051B, CD4052B, CD4053B
•Automotive: CD4051B-Q1, CD4051B-Q1, CD4053B-Q1, CD4053B-Q1
•Military: CD4051B-MIL, CD4052B-MIL, CD4053B-MIL
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•Military - QML certified for Military and Defense Applications
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
CD4051BM96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
CD4051BM96G4 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
CD4051BM96G4 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
CD4051BNSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
CD4051BPWR TSSOP PW 16 2000 330.0 12.4 7.0 5.6 1.6 8.0 12.0 Q1
CD4051BPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
CD4051BPWRG4 TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
CD4052BM96G4 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
CD4052BNSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
CD4052BPWR TSSOP PW 16 2000 330.0 12.4 7.0 5.6 1.6 8.0 12.0 Q1
CD4052BPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
CD4052BPWRG3 TSSOP PW 16 2000 330.0 12.4 7.0 5.6 1.6 8.0 12.0 Q1
CD4052BPWRG4 TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
CD4053BM96G4 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
CD4053BNSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
CD4053BPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
CD4053BPWR TSSOP PW 16 2000 330.0 12.4 7.0 5.6 1.6 8.0 12.0 Q1
CD4053BPWRG3 TSSOP PW 16 2000 330.0 12.4 7.0 5.6 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 19-Jul-2012
Pack Materials-Page 1
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
CD4053BPWRG4 TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
CD4051BM96 SOIC D 16 2500 333.2 345.9 28.6
CD4051BM96G4 SOIC D 16 2500 333.2 345.9 28.6
CD4051BM96G4 SOIC D 16 2500 367.0 367.0 38.0
CD4051BNSR SO NS 16 2000 367.0 367.0 38.0
CD4051BPWR TSSOP PW 16 2000 364.0 364.0 27.0
CD4051BPWR TSSOP PW 16 2000 367.0 367.0 35.0
CD4051BPWRG4 TSSOP PW 16 2000 367.0 367.0 35.0
CD4052BM96G4 SOIC D 16 2500 333.2 345.9 28.6
CD4052BNSR SO NS 16 2000 367.0 367.0 38.0
CD4052BPWR TSSOP PW 16 2000 364.0 364.0 27.0
CD4052BPWR TSSOP PW 16 2000 367.0 367.0 35.0
CD4052BPWRG3 TSSOP PW 16 2000 364.0 364.0 27.0
CD4052BPWRG4 TSSOP PW 16 2000 367.0 367.0 35.0
CD4053BM96G4 SOIC D 16 2500 333.2 345.9 28.6
CD4053BNSR SO NS 16 2000 367.0 367.0 38.0
CD4053BPWR TSSOP PW 16 2000 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 19-Jul-2012
Pack Materials-Page 2
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
CD4053BPWR TSSOP PW 16 2000 364.0 364.0 27.0
CD4053BPWRG3 TSSOP PW 16 2000 364.0 364.0 27.0
CD4053BPWRG4 TSSOP PW 16 2000 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 19-Jul-2012
Pack Materials-Page 3
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