71V321L25TFG8 - IDT, Integrated Device Technology Inc

JANUARY 2018

DSC-3026/13

HIGH SPEED 3.3V

2K X 8 DUAL-PORT

STATIC RAM WITH

INTERRUPTS

IDT71V321S/L

Features

◆◆

◆High-speed access

– Commercial & Industrial: 25/35/55ns (max.)

◆◆

◆Low-power operation

– IDT71V321S

—Active: 325mW (typ.)

—Standby: 5mW (typ.)

– IDT71V321L

—Active: 325mW (typ.)

—Standby: 1mW (typ.)

◆◆

◆Two INT flags for port-to-port communications

Functional Block Diagram

NOTES:

1. IDT71V321 (MASTER): BUSY is an output

2. BUSY and INT are totem-pole outputs.

◆◆

◆On-chip port arbitration logic (IDT71V321 only)

◆◆

◆BUSY output flag

◆◆

◆Fully asynchronous operation from either port

◆◆

◆Battery backup operation—2V data retention (L only)

◆◆

◆TTL-compatible, single 3.3V power supply

◆◆

◆Available in 52-pin PLCC, 64-pin TQFP and STQFP

packages

◆◆

◆Industrial temperature range (–40°C to +85°C) is available

for selected speeds

◆◆

◆Green parts available, see ordering information

I/O

Control

Address

Decoder MEMORY

ARRAY

ARBITRATION

and

INTERRUPT

LOGIC

Address

Decoder

I/O

Control

R/W

BUSY

10L

3026 drw 01

I/O

-I/O

R/W

INT

BUSY

I/O

-I/O

10R

INT

(2)

(1,2) (1,2)

(2)

R/W

LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018

6.42

IDT71V321S/L

High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges

IDT71V321J

J52

(4)

52-Pin PLCC

Top View

(5)

INDEX

I/O

GND

I/O

10L

INT

BUSY

R/W

BUSY

INT

10R

234567474849505152

20 27262524232221 333231302928

3026 drw 02

Pin Configurations(1,2,3)

Description

The IDT71V321 is a high-speed 2K x 8 Dual-Port Static RAMs with

internal interrupt logic for interprocessor communications. The

IDT71V321 is designed to be used as a stand-alone 8-bit Dual-Port

RAM.

The device provides two independent ports with separate control,

address, and I/O pins that permit independent, asynchronous access

for reads or writes to any location in memory. An automatic power

down feature, controlled by CE, permits the on chip circuitry of each

port to enter a very low standby power mode.

Fabricated using CMOS high-performance technology, these de-

vices typically operate on only 325mW of power. Low-power (L) ver-

sions offer battery backup data retention capability, with each Dual-Port

typically consuming 200µW from a 2V battery.

The IDT71V321 devices are packaged in a 52-pin PLCC, a 64-pin

TQFP (thin quad flatpack), and a 64-pin STQFP (super thin quad

flatpack).

INDEX

IDT71V321PF or TF

PP64

(4)

PN64

(4)

64-Pin STQFP

64-Pin TQFP

Top View

(5)

I/O

N/C

I/O

N/C

I/O

N/C

GND

I/O

N/C

GND

N/C

10R

BUSY

R/W

BUSY

N/C

10L

N/C

INT

3026 drw 03

NOTES:

1. All VCC pins must be connected to power supply.

2. All GND pins must be connected to ground supply.

3. J52-1 package body is approximately .75 in x .75 in x .17 in.

PP64-1 package body is approximately 10mm x 10mm x 1.4mm.

PN64-1 package body is approximately 14mm x 14mm x 1.4mm.

4. This package code is used to reference the package diagram.

5. This text does not indicate orientation of the actual part-marking.

6.42

IDT71V321S/L

High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges

Recommended DC Operating

Conditions

Absolute Maximum Ratings(1) Recommended Operating

Temperature and Supply Voltage(1,2)

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS

may cause permanent damage to the device. This is a stress rating only

and functional operation of the device at these or any other conditions

above those indicated in the operational sections of the specification is not

implied. Exposure to absolute maximum rating conditions for extended

periods may affect reliability.

2. VTERM must not exceed VCC + 10% for more than 25% of the cycle time or 10ns

maximum, and is limited to < 20mA for the period of VTERM > VCC + 10%.

NOTES:

1. VIL (min.) = -1.5V for pulse width less than 20ns.

2. VTERM must not exceed Vcc + 0.3V.

NOTES:

1. This is the parameter TA. This is the "instant on" case temperature.

2. Industrial temperature: for specific speeds, packages and powers contact your

sales office.

Symbol Rating Commercial

& Industrial Unit

TERM

(2)

Terminal Voltage

with Re sp e ct

to GND

-0. 5 to +4.6 V

Operating

Temperature 0 to +70 °C

BIAS

Temperature

Under Bias -55 to +125

STG

Storage

Temperature -65 to +150

OUT

DC Outp ut

Current 50 mA

3026 tbl 01

Grade Ambient

Temperature GND Vcc

Commercial 0

C to +70

C0V3.3V

0. 3V

Industrial -40

C to + 85

C0V 3.3V

0. 3V

3026 tbl 02

Symbol Parameter Min. Typ. Max. Unit

Sup p ly Vo ltag e 3.0 3.3 3.6 V

GND Ground 0 0 0 V

Inp ut Hi g h Vo l tage 2. 0

____

+0.3

(2)

Input Lo w Vo ltag e -0.3

(1)

____

0.8 V

3026 tbl 03

Capacitance(1)

(TA = +25°C, f = 1.0MHz) TQFP Only

Symbol Parameter Conditions

(2)

Max. Unit

CIN Inp ut Cap aci tanc e V IN = 3dV 9 pF

COUT Ou tp ut Cap ac itanc e V OUT = 3dV 10 pF

3026 tbl 04

NOTES:

1. This parameter is determined by device characterization but is not production

tested.

2 . 3dv references the interpolated capacitance when the input and output signals

switch from 0V to 3V or from 3V to 0V.

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range (VCC = 3.3V ± 0.3V)

Symbol Parameter Test Conditions

71V321S 71V321L

UnitMin. Max. Min. Max.

|Input Leakage Current

(1)

= 3.6V,

= 0V to V

___

5µA

| Output Leakage Current CE = V

, V

OUT

= 0V to V

= 3.6V

___

5µA

Output Low Voltage I

= 4mA

___

0.4

___

0.4 V

Output High Voltage I

= -4mA 2.4

___

2.4

___

3026 tbl 05

NOTE:

1. At VCC < 2.0V input leakages are undefined.

6.42

IDT71V321S/L

High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range(1,2) (VCC = 3.3V ± 0.3V)

NOTES:

1. 'X' in part numbers indicates power rating (S or L).

2. VCC = 3.3V, TA = +25°C, and are not production tested. ICCDC = 70mA (Typ.).

3 . At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC and using "AC Test Conditions" of input levels

of GND to 3V.

4. f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby.

5. Port "A" may be either left or right port. Port "B" is opposite from port "A".

Symbol Parameter Test Condition Version

71V321X25

Com'l & Ind 71V321X35

Com'l & Ind 71V321X55

Com'l & Ind

Unit

Typ. Max. Typ. Max. Typ. Max.

Dynamic Operating

Current

(Both Ports Active)

CE = V

, Outputs Disabled

SEM = V

f = f

MAX

(3)

COM'L S

L55

55 130

100 55

55 125

95 55

55 115

85 mA

IND L 55 130 55 125 55 115

SB1

Standby Current

(Both Ports - TTL

Level Inputs)

= CE

= V

SEM

= SEM

= V

f = f

MAX

(3)

COM'L S

L15

15 35

20 15

15 35

20 15

15 35

20 mA

IND L 15 35 15 35 15 35

SB2

Standby Current

(One Port - TTL

Level Inputs)

"A"

= V

and CE

"B"

= V

(5)

Active Port Outputs Disabled,

f=f

MAX

(3)

SEM

= SEM

= V

COM'L S

L25

25 75

55 25

25 70

50 25

25 60

40 mA

IND L 25 75 25 70 25 60

SB3

Full Standby Current

(Both Ports - All

CMOS Level Inputs)

Both Ports CE

and

> V

- 0.2V

> V

- 0.2V or

< 0.2V, f = 0

(4)

SEM

= SEM

> V

- 0.2V

COM'L S

L1.0

0.2 5

31.0

0.2 5

31.0

0.2 5

3mA

IND L 0.2 6 1.0 5 1.0 5

SB4

Full Standby Current

(One Port - All

CMOS Level Inputs)

"A"

< 0.2V and

"B"

> V

- 0.2V

(5)

SEM

= SEM

> V

- 0.2V

> V

- 0.2V or V

< 0.2V

Active Port Outputs Disabled

f = f

MAX

(3)

COM'L S

L25

25 70

55 25

25 65

50 25

25 55

40 mA

IND L 25 70 25 65 25 55

3026 tbl 06

Data Retention Characteristics (L Version Only)

Symbol Parameter Test Condition Min. Typ.

(1)

Max. Unit

fo r Data Rete nti o n 2. 0

___

CCDR

Data Re te ntio n Cu rre nt V

= 2

CE > V

- 0.2V COM' L.

___

100 500 µA

CDR

(3)

Chip De se lec t to Data

Re te ntio n Tim e V

> V

- 0. 2V o r V

< 0. 2V IND.

___

100 1000 µA

___ ___

(3)

Op e ratio n Reco ve ry Time t

(2)

___ ___

3026 tbl 07

NOTES:

1. VCC = 2V, TA = +25°C, and is not production tested.

2. tRC = Read Cycle Time.

3. This parameter is guaranteed by device characterization but not production tested.

6.42

IDT71V321S/L

High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges

Data Retention Waveform

3.0V 3.0V

DATA RETENTION MODE

CDR

≥2.0V

3026 drw 04

AC Test Conditions

590Ω

30pF

435Ω

DATA

OUT

590Ω

435Ω5pF

DATA

OUT

3026 drw 05

3.3V 3.3V

BUSY

INT

Figure 1. AC Output Test Load Figure 2. Output Test Load

(for tHZ, tLZ, tWZ, and tOW)

* Including scope and jig.

Inp ut Puls e Le v e ls

Inp ut Ri se / Fa ll Tim e s

Inp ut Timing Re fe re nc e Le v e ls

Outp ut Reference Leve ls

Outp ut Lo ad

GND to 3.0V

5ns

1.5V

Fig ures 1 and 2

3026 tbl 08

AC Electrical Characteristics Over the

Operating Temperature Supply Voltage Range(2)

71V321X25

Com'l & Ind 71V321X35

Com'l & Ind 71V321X55

Com'l & Ind

UnitSymbol Parameter Min. Max. Min. Max. Min. Max.

READ CYCLE

tRC Read Cycle Time 25

____

tAA Address Access Time

____

55 ns

tACE Chip Enable Access Time

____

55 ns

tAOE Output Enable Access Time

____

25 ns

tOH Output Hold from Address Change 3

____

tLZ Output Low-Z Time

(1,2)

____

tHZ Output High-Z Time

(1,2)

____

30 ns

tPU Chip Enable to Power Up Time

(2)

____

tPD Chip Disable to Power Down Time

(2)

____

50 ns

3026 tbl 09

NOTES:

1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).

2. This parameter is guaranteed by device characterization, but is not production tested.

3. 'X' in part numbers indicates power rating (S or L).

6.42

IDT71V321S/L

High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges

ACE

VALID DATA

50%

DATA

OUT

CURRENT

50%

3026 drw 07

(4)

(1)

(1) (2)

(2)

(4)

AOE

Timing Wa vef orm of Read Cy cle No . 2, Either Side (3)

NOTES:

1. Timing depends on which signal is asserted last, OE or CE.

2. Timing depends on which signal is de-asserted first, OE or CE.

3. R/W = VIH and the address is valid prior to or coincidental with CE transition LOW.

4 . Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA, and tBDD.

Timing Wa veform of Read Cy cle No . 1, Either Side(1)

NOTES:

1. R/W = VIH, CE = VIL, and is OE = VIL. Address is valid prior to the coincidental with CE transition LOW.

2. tBDD delay is required only in the case where the opposite port is completing a write operation to the same address location. For simultaneous read operations

BUSY has no relationship to valid output data.

3. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA, and tBDD.

ADDRESS

DATA

OUT

PREVIOUS DATA VALID

DATA VALID

3026 drw 06

BDD

(2,3)

BUSY

OUT

6.42

IDT71V321S/L

High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges

AC Electrical Characteristics Over the

Operating Temperature and Supply Voltage Range(4)

NOTES:

1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).

2. This parameter is guaranteed by device characterization but is not production tested.

3. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over

voltage and temperature, the actual tDH will always be smaller than the actual tOW.

4. 'X' in part numbers indicates power rating (S or L).

Symbol Parameter

71V321X25

Com'l & Ind 71V321X35

Com'l & Ind 71V321X55

Com'l & Ind

UnitMin. Max. Min. Max. Min. Max.

WRITE CYCLE

Write Cycle Time 25 ____ 35 ____ 55 ____ ns

Chip Enable to End-of-Write 20 ____ 30 ____ 40 ____ ns

Addr ess Valid to End-of-Write 20 ____ 30 ____ 40 ____ ns

Address Set-up Time 0 ____ 0____ 0____ ns

Write Pulse Width 20 ____ 30 ____ 40 ____ ns

Write Recovery Time 0 ____ 0____ 0____ ns

Data Valid to End-of-Write 12 ____ 20 ____ 20 ____ ns

Output High-Z Time(1,2) ____ 12 ____ 15 ____ 30 ns

Data Hold Time(3) 0____ 0____ 0____ ns

Write Enable to Output in High-Z(1,2) ____ 15 ____ 15 ____ 30 ns

Output Active from End -of-Write(1,2) 0____ 0____ 0____ ns

3026 tbl 10

6.42

IDT71V321S/L

High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges

Timing Wa vef orm of Write Cyc le No. 2, (CE Controlled Timing)(1,5)

Timing Wa vef orm of Write Cy cle No . 1, (R/W Controlled Timing)(1,5,8)

NOTES:

1. R/W or CE must be HIGH during all address transitions.

2 . A write occurs during the overlap (tEW or tWP) of CE = VIL and R/W= VIL.

3. tWR is measured from the earlier of CE or R/W going HIGH to the end of the write cycle.

4. During this period, the l/O pins are in the output state and input signals must not be applied.

5. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.

6. Timing depends on which enable signal (CE or R/W) is asserted last.

7. This parameter is determined to be device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test

Load (Figure 2).

8. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers toturn off data to be

placed on the bus for the required tDW. If OE is HIGH during a R/W controlled write cycle, this requirement does not apply and the write pulse can be as short

as the specified tWP.

ADDRESS

R/W

DATA

OUT

DATA

(2)

(4) (4)

3026 drw 08

(6)

(7)

(3) (7)

ADDRESS

R/W

DATA

3026 drw 09

(6) (2) (3)

6.42

IDT71V321S/L

High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges

AC Electrical Characteristics Over the

Operating Temperature and Supply Voltage Range(6)

NOTES:

1. Port-to-port delay through RAM cells from the writing port to the reading port, refer to “Timing Waveform of Write with Port-to-Port Read and BUSY."

2. To ensure that the earlier of the two ports wins.

3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual).

4. To ensure that a write cycle is inhibited on port "B" during contention on port "A".

5. To ensure that a write cycle is completed on port "B" after contention on port "A".

6. 'X' in part numbers indicates power rating (S or L).

71V321X25

Com'l & Ind 71V321X35

Com'l & Ind 71V321X55

Com'l & Ind

Symbol Parameter Min. Max. Min. Max. Min. Max. Unit

BUSY Timing

tBAA BUSY Access Time from Address ____ 20 ____ 20 ____ 30 ns

tBDA BUSY Disable Time from Address ____ 20 ____ 20 ____ 30 ns

tBAC BUSY Access Time from Chip Enable ____ 20 ____ 20 ____ 30 ns

tBDC BUSY Disable Time from Chip Enable ____ 20 ____ 20 ____ 30 ns

tWH Write Hold After BUSY(5) 12 ____ 15 ____ 20 ____ ns

tWDD Write Pulse to Data Delay(1) ____ 50 ____ 60 ____ 80 ns

tDDD Write Data Valid to Read Data Delay(1) ____ 35 ____ 45 ____ 65 ns

tAPS Arbitration Priority Set-up Time(2) 5____ 5____ 5____ ns

tBDD BUSY Disable to Valid Data(3) ____ 30 ____ 30 ____ 45 ns

3026 tbl 11

Timing Waveform of Write with Port-to-Port Read and BUSY(2,3,4)

NOTES:

1. To ensure that the earlier of the two ports wins.

2. CEL = CER = VIL

3. OE = VIL for the reading port.

4. All timing is the same for the left and right ports. Port “A” may be either the left or right port. Port “B” is opposite from port “A”.

BDD

DDD

BDA

WDD

ADDR

"B"

DATA

OUT"B"

DATA

IN"A"

ADDR

"A"

MATCH

VALID

MATCH

VALID

R/W

"A"

BUSY

"B"

APS

3026 drw 10

(1)

BAA

6.42

IDT71V321S/L

High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges

Timing Waveform of BUSY Arbitration Controlled by CE Timing(1)

Timing Waveform of BUSY Arbitration Controlled

by Address Match Timing(1)

NOTES:

1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.

2. If tAPS is not satisfied, the BUSY will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted.

NOTES:

1. tWH must be met for BUSY output 71V321.

2. BUSY is asserted on port 'B' blocking R/W'B', until BUSY'B' goes HIGH.

3. All timing is the same for the left and right ports. Port "A" may be either the left or right port. Port "B" is opposite from port "A".

Timing Waveform of Write with BUSY(3)

BUSY

"B"

3026 drw 11

R/W

"A"

R/W

"B" (2)

(1)

APS

(2)

ADDR

"A" AND "B" ADDRESSES MATCH

BAC

BDC

"B"

"A"

BUSY

"A"

3026 drw 12

BUSY

"B"

ADDRESSES DO NOT MATCH

ADDRESSES MATCH

APS

ADDR

"A"

ADDR

"B"

RC OR

3026 drw 13

(2)

BAA

BDA

6.42

IDT71V321S/L

High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges

AC Electrical Characteristics Over the

Operating Temperature and Supply Voltage Range(1)

NOTES:

1. 'X' in part numbers indicates power rating (S or L).

71V321X25

Com'l & Ind 71V321X35

Com'l & Ind 71V321X55

Com'l & Ind

Symbol Parameter Min. Max. Min. Max. Min. Max. Unit

INTERRUPT TIMING

Address Set-up Time 0

____

Write Recovery Time 0

____

INS

Interrupt Set Time

____

45 ns

INR

Interrupt Reset Time

____

45 ns

3026 tbl 12

Timing Waveform of Interrupt Mode(1)

SET INT

CLEAR INT

NOTES:.

1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.

2. See Interrupt Truth Table.

3. Timing depends on which enable signal (CE or R/W) is asserted last.

4. Timing depends on which enable signal (CE or R/W) is de-asserted first.

INS

ADDR

"A"

INT

"B"

INTERRUPT ADDRESS

R/W

"A"

3026 drw 14

(3)

(2)

(4)

INTERRUPT CLEAR ADDRESS

ADDR

"B"

INR

INT

"B"

3026 drw 15

(3)

(2)

6.42

IDT71V321S/L

High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges

Table III — Address BUSY Arbitration

Table I

—

Non-Contention

Read/Write Control(4)

NOTES:

1 . Pins BUSYL and BUSYR are both outputs. BUSYX outputs on the IDT71V321 are totem-

pole.

2. 'L' if the inputs to the opposite port were stable prior to the address and enable inputs of this

port. 'H' if the inputs to the opposite port became stable after the address and enable inputs

of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR

outputs can not be LOW simultaneously.

3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW

regardless of actual logic level on the pin. Writes to the right port are internally

ignored when BUSYR outputs are driving LOW regardless of actual logic level

on the pin.

Truth Tables

T able II

—

Interrupt Flag(1,4)

NOTES:

1. A0L – A10L ≠ A0R – A10R.

2. If BUSY = L, data is not written.

3. If BUSY = L, data may not be valid, see tWDD and tDDD timing.

4. 'H' = VIH, 'L' = VIL, 'X' = DON’T CARE, 'Z' = High-impedance.

NOTES:

1. Assumes BUSYL = BUSYR = VIH

2. If BUSYL = VIL, then No Change.

3. If BUSYR = VIL, then No Change.

4. 'H' = HIGH, 'L' = LOW, 'X' = DON’T CARE

Left Port Right Port

FunctionR/W

10L

-A

INT

R/W

10R

-A

INT

LLX7FFXXXX X L

(2)

S e t Rig h t INT

Flag

XXXXXXLL7FFH

(3)

Re s et R ight INT

Flag

XXX X L

(3)

LLX7FEXSet Left INT

Flag

XLL7FEH

(2)

XXX X XReset Left INT

Flag

3 026 tbl 14

Inputs Outputs

Function

-A

10L

-A

10R

BUSY

(1)

BUSY

(1)

XX NO MATCH H H Normal

HX MATCH H H Normal

XH MATCH H H Normal

L L MATCH (2) (2) Write Inhib it

(3)

3026 tbl 15

Left or Right Port(1)

R/WCE OE D

0-7

Function

XHX Z Port Deselecte d and in Powe r-

Do wn Mo d e. I

SB2

or I

SB4

XHX Z CE

= CE

= V

IH,

Powe r-Down Mo d e I

SB1

or I

SB3

LLXDATA

Data o n P o rt Wr itte n Into M e mory (2)

HLLDATA

OUT

Data in Me mo ry O utp ut o n P o rt(3)

H L H Z High-impedance Outputs

3026 tbl 13

6.42

IDT71V321S/L

High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges

Busy Logic

Busy Logic provides a hardware indication that both ports of the RAM

have accessed the same location at the same time. It also allows one of the

two accesses to proceed and signals the other side that the RAM is “Busy”.

The BUSY pin can then be used to stall the access until the operation on

the other side is completed. If a write operation has been attempted from

the side that receives a busy indication, the write signal is gated internally

to prevent the write from proceeding.

The use of BUSY Logic is not required or desirable for all applications.

In some cases it may be useful to logically OR the BUSY outputs together

and use any BUSY indication as an interrupt source to flag the event of

an illegal or illogical operation.

Depth Expansion

The BUSY arbitration, is based on the chip enable and address

signals only. It ignores whether an access is a read or write.

The BUSY outputs on the IDT71V321 are totem-pole type outputs and

do not require pull-up resistors to operate. If these RAMs are being

expanded in depth, then the BUSY indication for the resulting array

requires the use of an external AND gate

Functional Description

The IDT7V1321 provides two ports with separate control, address

and I/O pins that permit independent access for reads or writes to any

location in memory. The IDT71V321 has an automatic power down

feature controlled by CE. The CE controls on-chip power down circuitry

that permits the respective port to go into a standby mode when not

selected (CE = VIH). When a port is enabled, access to the entire memory

array is permitted.

Interrupts

If the user chooses the interrupt function, a memory location (mail box

or message center) is assigned to each port. The left port interrupt flag

(INTL) is asserted when the right port writes to memory location 7FE

(HEX), where a write is defined as the CER = R/WR = VIL per Truth Table

II. The left port clears the interrupt by accessing address location 7FE when

CEL = OEL = VIL, R/W is a "don't care". Likewise, the right port interrupt

flag (INTR) is asserted when the left port writes to memory location 7FF

(HEX) and to clear the interrupt flag (INTR), the right port must access the

memory location 7FF. The message (8 bits) at 7FE or 7FF is user-defined,

since it is an addressable SRAM location. If the interrupt function is not used,

address locations 7FE and 7FF are not used as mail boxes, but as part

of the random access memory. Refer to Truth Table II for the interrupt

operation.

3026 drw 16

DECODER

BUSY

MASTER

Dual Port

RAM

BUSY

MASTER

Dual Port

RAM

BUSY

Figure 3. Busy and chip enable routing for depth

expansion with IDT71V321.

6.42

IDT71V321S/L

High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges

Ordering Information

NOTES:

1. Contact your sales office Industrial temperature range is available for selected speeds, packages and powers.

2. Green parts available. For specific speeds, packages and powers contact your local sales office.

LEAD FINISH (SnPb) parts are in EOL process. Product Discontinuation Notice - PDN# SP-17-02

Power 999

Speed A

Package A

Process/

Temperature

Range

Blank

I(1) Commercial (0°C to +70°C)

Industrial (-40°C to +85°C)

52-pin PLCC

64-pin TQFP

64-pin STQFP

XXXXX

Device

Type

Speed in nanoseconds

3026 drw 17

SLow Power

Standard Power

71V321 16K (2K x 8-Bit) MASTER 3.3V Dual-Port RAM w/Interrupt

Commercial & Industrial

Blank

8 Tube of Tray

Tape and Reel

G(2) Green

(J52)

(PN64)

(PP64)

Datasheet Document History

03/24/99: Initiated datasheet document history

Converted to new format

Cosmetic and typographical corrections

Page 2 Added additional notes to pin configurations

06/15/99: Changed drawing format

10/15/99: Page 12 Changed open drain to totem-pole in Table III, note 1

10/21/99: Page 13 Deleted 'does not' in copy from Busy Logic

11/12/99: Replaced IDT logo

01/12/01: Pages 1 & 2 Moved full "Description" to page 2 and adjusted page layouts

Page 3 Increased storage temperature parameters

Clarified TA parameter

Page 4 DC Electrical parameters–changed wording from "open" to "disabled"

Changed ±200mV to 0mV in notes

08/22/01: Pages 4, 5, 7, Industrial temp range offering removed from DC & AC Electrical Characteristics for 35 and 55ns

9 & 11

01/17/06: Page 1 Added green availability to features

Page 14 Added green indicator to ordering information

Page 1 & 14 Replaced old IDTTM with new IDTTM logo

Datasheet document history continued on page 15

6.42

IDT71V321S/L

High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

CORPORATE HEADQUARTERS for SALES: for Tech Support:

6024 Silver Creek Valley Road 800-345-7015 or 408-284-8200 408-284-2794

San Jose, CA 95138 fax: 408-284-2775 DualPortHelp@idt.com

www.idt.com

Datasheet Document History (con't)

08/25/06: Page 11 Changed INT"A" to INT"B" in the CLEAR INT drawing in the Timing Waveform of Interrupt Mode

10/23/08: Page 14 Removed "IDT" from orderable part number

01/25/10: Page 4 In order to correct the DC Chars table for the 71V321/71V421L35 speed grade and the Data Retention Chars

table, I Temp values have been added to each table respectively. In addition, all of the AC Chars tables and the

ordering information also now reflect this I temp correction

Page 2 Removed IDT in reference to fabrication

Page 2 & 14 The package codes J52-1, PN64-1 & PP64-1 changed to J52, PN64 & PP64 respectively to match standard

package codes

Page 14 Added Tape and Reel indicator to Ordering Information

Page 1 -15 Removed 71V421S/L from the part number, in the pin configurations and throughout the datasheet

Page 1 - 15 Removed all references to Master/Slave throughout the datasheet

Page 1 -15 Updated the Com'l and Ind speeds for the 25/35/55ns offerings in Features , in the DC & AC Chars tables, in the

Ordering Information and throughout the datasheet

Page 13 Removed Width Expansion with Busy Logic Master/Slave Arrays diagram for part numbers 71V321/71V421S/ L

and updated with a Depth Expansion diagram for the single part number 71V321S/L

Updated the corresponding Depth Expansion descriptive text in the Depth Expansion section of the datasheet

Product Discontinuation Notice - PDN# SP-17-02

Last time buy expires June 15, 2018

01/12/18:

10/14/15:

06/25/15: