SN74ALVC7806-25DLR - Texas Instruments

SN74ALVC7806

256 × 18

LOW-POWER FIRST-IN, FIRST-OUT MEMORY

SCAS591A – OCTOBER 1997 – REVISED APRIL 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Member of the Texas Instruments

Widebus Family

Low-Power Advanced CMOS Technology

Operates From 3-V to 3.6-V VCC

Load Clock and Unload Clock Can Be

Asynchronous or Coincident

Full, Empty, and Half-Full Flags

Programmable Almost-Full/Almost-Empty

Flag

Fast Access Times of 18 ns With a 50-pF

Load and All Data Outputs Switching

Simultaneously

Data Rates up to 40 MHz

3-State Outputs

Pin-to-Pin Compatible With SN74ACT7804,

SN74ACT7806, and SN74ACT7814

Packaged in Shrink Small-Outline 300-mil

Package Using 25-mil Center-to-Center

Spacing

description

A FIFO memory is a storage device that allows

data to be written into and read from its array at

independent data rates. The SN74ALVC7806 is

an 18-bit FIFO with high speed and fast access

times. Data is processed at rates up to 40 MHz

with access times of 18 ns in a bit-parallel format.

These memories are designed for 3-V to 3.6-V

VCC operation.

Data is written into memory on a low-to-high

transition of the load clock (LDCK) and is read out

on a low-to-high transition of the unload clock

(UNCK). The memory is full when the number of words clocked in exceeds the number of words clocked out

by 256. When the memory is full, LDCK has no effect on the data residing in memory. When the memory is

empty, UNCK has no effect.

Status of the FIFO memory is monitored by the full (FULL), empty (EMPTY), half-full (HF), and almost-

full/almost-empty (AF/AE) flags. The FULL output is low when the memory is full and high when the memory

is not full. The EMPTY output is low when the memory is empty and high when it is not empty. The HF output

is high whenever the FIFO contains 128 or more words and low when it contains 127 or fewer words. The AF/AE

status flag is a programmable flag. The first one or two low-to-high transitions of LDCK after reset are used to

program the almost-empty offset value (X) and the almost-full of fset value (Y) if program enable (PEN) is low.

The AF/AE flag is high when the FIFO contains X or fewer words or (256 – Y) or more words. The AF/AE flag

is low when the FIFO contains between (X + 1) and (255 – Y) words.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Widebus is a trademark of Texas Instruments Incorporated.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

RESET

D17

D16

D15

D14

D13

D12

D11

D10

VCC

GND

PEN

AF/AE

LDCK

FULL

Q17

Q16

Q15

GND

Q14

VCC

Q13

Q12

Q11

Q10

GND

VCC

GND

UNCK

EMPTY

DL PACKAGE

(TOP VIEW)

NC – No internal connection

SN74ALVC7806

256 × 18

LOW-POWER FIRST-IN, FIRST-OUT MEMORY

SCAS591A – OCTOBER 1997 – REVISED APRIL 1998

2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

description (continued)

A low level on the reset (RESET) resets the internal stack pointers and sets FULL high, AF/AE high, HF low,

and EMPTY low. The Q outputs are not reset to any specific logic level. The FIFO must be reset on power up.

The first word loaded into empty memory causes EMPTY to go high and the data to appear on the Q outputs.

The data outputs are in the high-impedance state when the output-enable (OE) is high.

The SN74ALVC7806 is characterized for operation from 0°C to 70°C.

logic symbol†

EMPTY

FULL

FIFO 256 × 18

D0 20

D1 19

D2 18

D3 17

D4 16

D5 15

D6 14

D7 12

Full

Half-Full

AF/AE

Almost Full/Empty 29

Empty

Data 1

D9 9

D10 8

D11 7

D12 6

D13 5

D14 4

D15 3

D16

D17

Q10

Q11

Q12

Q13

Q14

Q15

Q16

Q17

RESET

PEN

RESET

LDCK LDCK

Data

Program Enable

23 EN1

UNCK UNCK

†This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

SN74ALVC7806

256 × 18

LOW-POWER FIRST-IN, FIRST-OUT MEMORY

SCAS591A – OCTOBER 1997 – REVISED APRIL 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

functional block diagram

Q0–Q17

AF/AE

D0–D17

UNCK

LDCK

RESET

PEN

EMPTY

FULL

Status-

Flag

Logic

Read

Pointer

Reset

Logic

256 ×18

Write

Pointer

RAM

Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME NO.

I/O

DESCRIPTION

AF/AE 24 O Almost full/almost empty flag. Depth-of fset values can be programmed for this flag or the default value

of 64 can be used for both the almost empty offset (X) and the almost full of fset (Y). AF/AE is high when

memory contains X or fewer words or (256 – Y) or more words. AF/AE is high after reset.

D0–D17 2–9, 11–12,

14–21 I18-bit data input port

EMPTY 29 O Empty flag. EMPTY is low when the FIFO is empty. A FIFO reset also causes EMPTY to go low.

FULL 28 O Full flag. FULL is low when the FIFO is full. A FIFO reset causes FULL to go high.

HF 22 O Half-full flag. HF is high when the FIFO memory contains 128 or more words. HF is low after reset.

LDCK 25 I Load clock. Data is written to the FIFO on the rising edge of LDCK when FULL is high.

OE 56 I Output enable. When OE is high, the data outputs are in the high-impedance state.

PEN 23 I Program enable. After reset and before the first word is written to the FIFO, the binary value on D0–D7

is latched as an AF/AE offset value when PEN is low and WRTCLK is high.

Q0–Q17 33–34, 36–38,

40–43, 45–49,

51, 53–55 O18-bit data output port

RESET 1 I Reset. A low level on RESET resets the FIFO and drives AF/AE and FULL high and HF and EMPTY low .

UNCK 32 I Unload clock. Data is read from the FIFO on the rising edge of UNCK when EMPTY is high.

SN74ALVC7806

256 × 18

LOW-POWER FIRST-IN, FIRST-OUT MEMORY

SCAS591A – OCTOBER 1997 – REVISED APRIL 1998

4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ÉÉ

FULL

EMPTY

D0–D17

RESET

PEN

Q0–Q17

AF/AE

W2 DE

LDCK

UNCK

W1 W2

H I

ÉÉ

G F

(Y+2)

(Y+1)

(X+1) B

Define the AF/AE Flag Using the Default Value of X and Y

Don’t Care

Figure 1. Write, Read, and Flag Timing Reference

SN74ALVC7806

256 × 18

LOW-POWER FIRST-IN, FIRST-OUT MEMORY

SCAS591A – OCTOBER 1997 – REVISED APRIL 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

DATA-WORD NUMBERS FOR FLAG TRANSITIONS

DEVICE

TRANSITION WORD

DEVICE

A B C D E F G H I

SN74ALVC7806 W128 W(256 – Y) W256 W129 W130 W(256 – X) W(257 – X) W255 W256

Figure 1. Write, Read, and Flag Timing Reference (Continued)

offset values for AF/AE

The AF/AE flag has two programmable limits: the almost-empty offset value (X) and the almost-full offset

value (Y). They can be programmed after the FIFO is reset and before the first word is written to memory. The

AF/AE flag is high when the FIFO contains X or fewer words or (256 – Y) or more words.

To program the offset values, PEN can be brought low after reset. On the following low-to-high transition of

LDCK, the binary value on D0–D7 is stored as the almost-empty offset value (X) and the almost-full offset

value (Y). Holding PEN low for another low-to-high transition of LDCK reprograms Y to the binary value on

D0–D7 at the time of the second LDCK low-to-high transition. Writes to the FIFO memory are disabled while

the offsets are programmed. A maximum value of 127 can be programmed for either X or Y (see Figure 2). To

use the default values of X = Y = 32, PEN must be held high.

ÌÌÌÌÌÌÌÌÌÌÌ

ÎÎÎÎÎÎÎÎ

ÎÎÎÎÎ

LDCK

RESET

X and Y Y

PEN

D0–D17

EMPTY

Don’t Care

Figure 1. Programming X and Y Separately

SN74ALVC7806

256 × 18

LOW-POWER FIRST-IN, FIRST-OUT MEMORY

SCAS591A – OCTOBER 1997 – REVISED APRIL 1998

6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†

Supply voltage range, VCC –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, VI (see Note 1) –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output voltage range, VO (see Notes 1 and 2) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage range applied to a disabled 3-state output –0.5 V to 3.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input clamp current, IIK (VI < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output clamp current, IOK (VO < 0 or VO > VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous output current, IO (VO = 0 to VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous current through VCC or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Package thermal impedance, θJA (see Note 3) 74°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.

NOTES: 1. The input and output voltage ratings can be exceeded if the input and output clamp-current ratings are observed.

2. This value is limited to 4.6 V maximum.

3. The package thermal impedance is calculated in accordance with JESD 51.

recommended operating conditions

’ALVC7806-25 ’ALVC7806-40

UNIT

MIN MAX MIN MAX

UNIT

VCC Supply Voltage 3 3.6 3 3.6 V

VIH High-level input voltage 2 2 V

VIL Low-level input voltage 0.8 0.8 V

VIInput voltage 0 VCC 0 VCC V

VOOutput voltage 0 VCC 0 VCC V

IOH High-level output current, Q outputs, flags VCC = 3 V –8 –8 mA

IOL Low-level output current, Q outputs, flags VCC = 3 V 16 16 mA

TAOperating free-air temperature 0 70 0 70 °C

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP‡MAX UNIT

VOH

Flags Q out

uts

VCC = 3 V to 3.6 V, IOH = –100 µA VCC–0.2

Flags

VCC = 3 V, IOH = –8 mA 2.4

Flags, Q outputs VCC = 3 V to 3.6 V, IOL = 100 µA 0.2

VOL Flags VCC = 3 V, IOL = 8 mA 0.4 V

Q outputs VCC = 3 V, IOL = 16 mA 0.55

IIVCC = 3.6 V, VI = VCC or GND ±5µA

IOZ VCC = 3.6 V, VO = VCC or GND ±10 µA

ICC VCC = 3.6 V, VI = VCC or GND and IO = 0 40 µA

∆ICC§VCC = 3.6 V, One input at VCC–0.6 V, Other inputs at VCC or GND 500 µA

CiVCC = 3.3 V, VI = VCC or GND 3 pF

CoVCC = 3.3 V, VO = VCC or GND 6 pF

‡All typical values are at VCC = 3.3 V, TA = 25°C.

§This is the supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.

SN74ALVC7806

256 × 18

LOW-POWER FIRST-IN, FIRST-OUT MEMORY

SCAS591A – OCTOBER 1997 – REVISED APRIL 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

timing requirements over recommended operating conditions (see Figures 1 through 3)

’ALVC7806-25 ’ALVC7806-40

UNIT

MIN MAX MIN MAX

UNIT

fclock Clock frequency 40 25 MHz

D0–D17 high or low 8 12

LDCK high or low 8 12

twPulse duration UNCK high or low 8 12 ns

PEN low 8 12

RESET low 10 12

D0–D17 before LDCK↑5 5

tsu Setup time LDCK inactive before RESET high 6 6 ns

PEN before LDCK↑8 8

D0–D17 after LDCK↑0 0

Hold time

PEN high after LDCK low 0 0

Hold

time

PEN low after LDCK↑3 3

LDCK inactive after RESET high 6 6

switching characteristics over recommended ranges of supply voltage and operating free-air

temperature, CL = 50 pF (unless otherwise noted) (see Figure 3)

PARAMETER

FROM TO ’ALVC7806-25 ’ALVC7806-40

UNIT

PARAMETER

(INPUT) (OUTPUT) MIN MAX MIN MAX

UNIT

fmax LDCK or UNCK 40 25 MHz

LDCK↑

Any Q

9 22 9 24

pd UNCK↑

6 18 6 20

tPLH LDCK↑EMPTY 6 17 6 19 ns

UNCK↑

EMPTY

6 17 6 19

tPHL RESET low

EMPTY

4 18 4 20 ns

PHL

LDCK↑FULL 6 17 6 19

tPLH

UNCK↑

FULL

6 17 6 19

PLH RESET low

FULL

4 20 4 22

LDCK↑

AF/AE

7 20 7 22

pd UNCK↑

AF/AE

7 20 7 22

tPLH

RESET low AF/AE 2 12 2 14

PLH LDCK↑HF 5 20 5 22

tPHL

UNCK↑

7 20 7 22

PHL RESET low

3 14 3 16

ten OE Any Q 2 10 2 11 ns

tdis OE Any Q 2 11 2 12 ns

operating characteristics, VCC = 3.3 V, TA = 25°C

PARAMETER TEST CONDITIONS TYP UNIT

Cpd Power dissipation capacitance per FIFO channel Outputs enabled CL = 50 pF, f = 5 MHz 53 pF

SN74ALVC7806

256 × 18

LOW-POWER FIRST-IN, FIRST-OUT MEMORY

SCAS591A – OCTOBER 1997 – REVISED APRIL 1998

8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

VOH

VOL

tsu

From Output

Under Test

CL = 50 pF

(see Note A)

LOAD CIRCUIT FOR OUTPUTS

S1 6 V

Open

GND

500 Ω

tPLH tPHL

Output

Control

(low-level

enabling)

Output

W aveform 1

S1 at 6 V

(see Note B)

Output

W aveform 2

S1 at GND

(see Note B)

tPZL

tPZH

tPLZ

tPHZ

1.5 V1.5 V

1.5 V 1.5 V 3 V

0 V

1.5 V 1.5 V VOH

VOL

0 V

1.5 V VOL + 0.3 V

1.5 V VOH – 0.3 V

0 V

1.5 V 3 V

0 V

1.5 V 1.5 V 0 V

3 V

0 V

1.5 V 1.5 V

Input

(see Note C)

3 V 3 V

3 V

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

VOLTAGE WAVEFORMS

PULSE DURATION

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

Timing

Input

Data

Input

Output

Input

NOTES: A. CL includes probe and jig capacitance.

B. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

W aveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤2.5 ns.

tPLH/tPHL

tpd

tPZH

tPZL

tPHZ

tPLZ

GND

6 V

GND

6 V

PARAMETER S1

ten

tdis

Open

Figure 2. Standard CMOS Outputs (FULL, EMPTY, HF, AF/AE)

SN74ALVC7806

256 × 18

LOW-POWER FIRST-IN, FIRST-OUT MEMORY

SCAS591A – OCTOBER 1997 – REVISED APRIL 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

100

120

140

0 102030405060708090

SUPPLY CURRENT

CLOCK FREQUENCY

fclock – Clock Frequency – MHz

VCC = 3.6 V

VCC = 3.3 V

VCC = 3 V

fdata = 1/2 fclock

TA = 75°C

CL = 0 pF

– Supply Current – mA

CC(f)

Figure 3

APPLICATION INFORMATION

SN74ALVC7806

D0–D17

D18–D35

Q0–Q17

Q18–Q35

D0–D17 Q0–Q17

LDCK UNCKLDCK

FULL EMPTY

SN74ALVC7806

FULL EMPTY

LDCK UNCK

UNCK

OE OE

Q0–Q17

Figure 4. Word-Width Expansion: 256

36 Bits

PACKAGING INFORMATION

Orderable Device Status (1) Package

Type Package

Drawing Pins Package

Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)

SN74ALVC7806-25DL ACTIVE SSOP DL 56 20 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

SN74ALVC7806-40DL ACTIVE SSOP DL 56 20 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

PACKAGE OPTION ADDENDUM

www.ti.com 28-Aug-2008

Addendum-Page 1

MECHANICAL DATA

MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

DL (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

4040048/E 12/01

48 PINS SHOWN

0.730

(18,54)

0.720

(18,29)

4828

0.370

(9,40)

(9,65)

0.380

Gage Plane

DIM

0.420 (10,67)

0.395 (10,03)

A MIN

A MAX

0.010 (0,25)

PINS **

0.630

(16,00)

(15,75)

0.620

0.010 (0,25)

Seating Plane

0.020 (0,51)

0.040 (1,02)

0.008 (0,203)

0.0135 (0,343)

0.008 (0,20) MIN

0.110 (2,79) MAX

0.299 (7,59)

0.291 (7,39)

0.004 (0,10)

0.005 (0,13)

0.025 (0,635)

0°–ā8°

0.005 (0,13)

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).

D. Falls within JEDEC MO-118

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