SN74ALVC7806 256 x 18 LOW-POWER FIRST-IN, FIRST-OUT MEMORY SCAS591A - OCTOBER 1997 - REVISED APRIL 1998 D D D D D D D D D D D Member of the Texas Instruments Widebus Family Low-Power Advanced CMOS Technology Operates From 3-V to 3.6-V VCC Load Clock and Unload Clock Can Be Asynchronous or Coincident Full, Empty, and Half-Full Flags Programmable Almost-Full/Almost-Empty Flag Fast Access Times of 18 ns With a 50-pF Load and All Data Outputs Switching Simultaneously Data Rates up to 40 MHz 3-State Outputs Pin-to-Pin Compatible With SN74ACT7804, SN74ACT7806, and SN74ACT7814 Packaged in Shrink Small-Outline 300-mil Package Using 25-mil Center-to-Center Spacing description A FIFO memory is a storage device that allows data to be written into and read from its array at independent data rates. The SN74ALVC7806 is an 18-bit FIFO with high speed and fast access times. Data is processed at rates up to 40 MHz with access times of 18 ns in a bit-parallel format. These memories are designed for 3-V to 3.6-V VCC operation. DL PACKAGE (TOP VIEW) RESET D17 D16 D15 D14 D13 D12 D11 D10 VCC D9 D8 GND D7 D6 D5 D4 D3 D2 D1 D0 HF PEN AF/AE LDCK NC NC FULL 1 56 2 55 3 54 4 53 5 52 6 51 7 50 8 49 9 48 10 47 11 46 12 45 13 44 14 43 15 42 16 41 17 40 18 39 19 38 20 37 21 36 22 35 23 34 24 33 25 32 26 31 27 30 28 29 OE Q17 Q16 Q15 GND Q14 VCC Q13 Q12 Q11 Q10 Q9 GND Q8 Q7 Q6 Q5 VCC Q4 Q3 Q2 GND Q1 Q0 UNCK NC NC EMPTY Data is written into memory on a low-to-high NC - No internal connection transition of the load clock (LDCK) and is read out on a low-to-high transition of the unload clock (UNCK). The memory is full when the number of words clocked in exceeds the number of words clocked out by 256. When the memory is full, LDCK has no effect on the data residing in memory. When the memory is empty, UNCK has no effect. Status of the FIFO memory is monitored by the full (FULL), empty (EMPTY), half-full (HF), and almostfull/almost-empty (AF/AE) flags. The FULL output is low when the memory is full and high when the memory is not full. The EMPTY output is low when the memory is empty and high when it is not empty. The HF output is high whenever the FIFO contains 128 or more words and low when it contains 127 or fewer words. The AF/AE status flag is a programmable flag. The first one or two low-to-high transitions of LDCK after reset are used to program the almost-empty offset value (X) and the almost-full offset value (Y) if program enable (PEN) is low. The AF/AE flag is high when the FIFO contains X or fewer words or (256 - Y) or more words. The AF/AE flag is low when the FIFO contains between (X + 1) and (255 - Y) words. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus is a trademark of Texas Instruments Incorporated. Copyright 1998, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 SN74ALVC7806 256 x 18 LOW-POWER FIRST-IN, FIRST-OUT MEMORY SCAS591A - OCTOBER 1997 - REVISED APRIL 1998 description (continued) A low level on the reset (RESET) resets the internal stack pointers and sets FULL high, AF/AE high, HF low, and EMPTY low. The Q outputs are not reset to any specific logic level. The FIFO must be reset on power up. The first word loaded into empty memory causes EMPTY to go high and the data to appear on the Q outputs. The data outputs are in the high-impedance state when the output-enable (OE) is high. The SN74ALVC7806 is characterized for operation from 0C to 70C. logic symbol FIFO 256 x 18 1 RESET LDCK UNCK OE D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 23 21 Full LDCK 32 56 PEN RESET 25 Half-Full UNCK Almost Full/Empty EN1 Empty 22 24 FULL HF AF/AE 29 EMPTY Program Enable 0 0 33 20 34 19 36 18 3