V62/04710-01XE - Texas Instruments

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FEATURES

DGG PACKAGE

(TOP VIEW)

1OEAB

1CLKAB

1SAB

GND

1A1

1A2

VCC

1A3

1A4

1A5

GND

1A6

1A7

1A8

2A1

2A2

2A3

GND

2A4

2A5

2A6

VCC

2A7

2A8

GND

2SAB

2CLKAB

2OEAB

1OEBA

1CLKBA

1SBA

GND

1B1

1B2

VCC

1B3

1B4

1B5

GND

1B6

1B7

1B8

2B1

2B2

2B3

GND

2B4

2B5

2B6

VCC

2B7

2B8

GND

2SBA

2CLKBA

2OEBA

DESCRIPTION/ORDERING INFORMATION

SN74LVCH16652A-EP16-BIT BUS TRANSCEIVER AND REGISTERWITH 3-STATE OUTPUTS

SCAS743A – DECEMBER 2003 – REVISED AUGUST 2005

•Controlled Baseline– One Assembly/Test Site, One FabricationSite•Enhanced Diminishing ManufacturingSources (DMS) Support•Enhanced Product-Change Notification•Qualification Pedigree

(1)

•Member of the Texas Instruments Widebus™Family

•Operates From 1.65 V to 3.6 V•Inputs Accept Voltages to 5.5 V•Max t

of 6.3 ns at 3.3 V•Typical V

OLP

(Output Ground Bounce) <0.8 Vat V

= 3.3 V, T

= 25 °C•Typical V

OHV

(Output V

Undershoot) >2 V atV

= 3.3 V, T

= 25 °C•Supports Mixed-Mode Signal Operation on AllPorts (5-V Input/Output Voltage With3.3-V V

)•I

off

Supports Partial-Power-Down ModeOperation

•Bus Hold on Data Inputs Eliminates the Needfor External Pullup/Pulldown Resistors•Latch-Up Performance Exceeds 250 mA PerJESD 17•ESD Protection Exceeds JESD 22– 2000-V Human-Body Model (A114-A)– 200-V Machine Model (A115-A)– 1000-V Charged-Device Model (C101)(1) Component qualification in accordance with JEDEC andindustry standards to ensure reliable operation over anextended temperature range. This includes, but is not limitedto, Highly Accelerated Stress Test (HAST) or biased 85/85,temperature cycle, autoclave or unbiased HAST,electromigration, bond intermetallic life, and mold compoundlife. Such qualification testing should not be viewed asjustifying use of this component beyond specifiedperformance and environmental limits.

This 16-bit bus transceiver and register is designed for 1.65-V to 3.6-V V

operation.

The SN74LVCH16652A consists of D-type flip-flops and control circuitry arranged for multiplexed transmission ofdata directly from the data bus or from the internal storage registers. The device can be used as two 8-bittransceivers or one 16-bit transceiver.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.Widebus is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Copyright © 2003–2005, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.

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DESCRIPTION/ORDERING INFORMATION (CONTINUED)

SN74LVCH16652A-EP

16-BIT BUS TRANSCEIVER AND REGISTERWITH 3-STATE OUTPUTS

SCAS743A – DECEMBER 2003 – REVISED AUGUST 2005

Complementary output-enable (OEAB and OEBA) inputs control the transceiver functions. Select-control (SABand SBA) inputs select whether real-time or stored data is transferred. A low input level selects real-time data,and a high input level selects stored data. The circuitry used for select control eliminates the typical decodingglitch that occurs in a multiplexer during the transition between stored and real-time data. Figure 1 illustrates thefour fundamental bus-management functions that can be performed with the SN74LVCH16652A.

Data on the A or B bus, or both, can be stored in the internal D flip-flops by low-to-high transitions at theappropriate clock (CLKAB or CLKBA) inputs, regardless of the levels on the select-control or output-enableinputs. When SAB and SBA are in the real-time transfer mode, it also is possible to store data without using theinternal D-type flip-flops by simultaneously enabling OEAB and OEBA. In this configuration, each outputreinforces its input. When all other data sources to the two sets of bus lines are at high impedance, each set ofbus lines remains at its last-level configuration.

To ensure the high-impedance state during power up or power down, OEBA should be tied to V

through apullup resistor and OEAB should be tied to GND through a pulldown resistor; the minimum value of the resistor isdetermined by the current-sinking/current-sourcing capability of the driver.

Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translatorsin a mixed 3.3-V/5-V system environment.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. Use of pullup orpulldown resistors with the bus-hold circuitry is not recommended. The bus-hold circuitry is part of the inputcircuit and is not disabled by OE or DIR.

ORDERING INFORMATION

PACKAGE

(1)

ORDERABLE PART NUMBER TOP-SIDE MARKING

–40 °C to 85 °C TSSOP – DGG Tape and reel CLVCH16652AIDGGREP CH16652AEP

(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available atwww.ti.com/sc/package.

FUNCTION TABLE

INPUTS DATA I/O

(1)

OPERATION OR FUNCTIONOEAB OEBA CLKAB CLKBA SAB SBA A1–A8 B1–B8

L H H or L H or L X X Input Input IsolationL H ↑ ↑ X X Input Input Store A and B dataX H ↑H or L X X Input Unspecified

(2)

Store A, hold BH H ↑ ↑ X

(2)

X Input Output Store A in both registersL X H or L ↑X X Unspecified

(2)

Input Hold A, store BL L ↑ ↑ X X

(2)

Output Input Store B in both registersL L X X X L Output Input Real-time B data to A busL L X H or L X H Output Input Stored B data to A busH H X X L X Input Output Real-time A data to B busH H H or L X H X Input Output Stored A data to B busStored A data to B bus andH L H or L H or L H H Output Output

stored B data to A bus

(1) The data-output functions can be enabled or disabled by a variety of level combinations at OEAB or OEBA. Data-input functions alwaysare enabled; i.e., data at the bus terminals is stored on every low-to-high transition of the clock inputs.(2) Select control = L, clocks can occur simultaneously. Select control = H, clocks must be staggered to load both registers.

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REAL-TIME TRANSFER

BUS B TO BUS A REAL-TIME TRANSFER

BUS A TO BUS B

STORAGE FROM

A, B, OR A AND B TRANSFER STORED DATA

TO A AND/OR B

BUS B

BUS A

BUS B

BUS A

BUS B

BUS A

BUS B

BUS A

OEAB

L L CLKAB

XCLKBA

XSAB

XSBA

LCLKAB

XCLKBA

XSAB

LSBA

HCLKAB CLKBA

XSAB

XSBA

XCLKAB CLKBA SAB SBA

HX X

H L H or L H H

↑↑

OEBA

H H

OEAB OEBA

OEAB OEBA H or L

SN74LVCH16652A-EP16-BIT BUS TRANSCEIVER AND REGISTERWITH 3-STATE OUTPUTS

SCAS743A – DECEMBER 2003 – REVISED AUGUST 2005

Figure 1. Bus-Management Functions

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1A1 1B1

One of Eight Channels

1SAB

1CLKAB

1SBA

1CLKBA

1OEAB

1OEBA

To Seven Other Channels

2A1 2B1

One of Eight Channels

2SAB

2CLKAB

2SBA

2CLKBA

2OEAB

2OEBA

To Seven Other Channels

SN74LVCH16652A-EP

16-BIT BUS TRANSCEIVER AND REGISTERWITH 3-STATE OUTPUTS

SCAS743A – DECEMBER 2003 – REVISED AUGUST 2005

LOGIC DIAGRAM (POSITIVE LOGIC)

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Absolute Maximum Ratings

(1)

Recommended Operating Conditions

(1)

SN74LVCH16652A-EP16-BIT BUS TRANSCEIVER AND REGISTERWITH 3-STATE OUTPUTS

SCAS743A – DECEMBER 2003 – REVISED AUGUST 2005

over operating free-air temperature range (unless otherwise noted)

MIN MAX UNIT

Supply voltage range –0.5 6.5 VV

Input voltage range

(2)

–0.5 6.5 VV

Voltage range applied to any output in the high-impedance or power-off state

(2)

–0.5 6.5 VV

Voltage range applied to any output in the high or low state

(2) (3)

–0.5 V

+ 0.5 VI

Input clamp current V

< 0 –50 mAI

Output clamp current V

< 0 –50 mAI

Continuous output current ±50 mAContinuous current through V

or GND ±100 mAθ

Package thermal impedance

(4)

64 °C/WT

stg

Storage temperature range –65 150 °C

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operatingconditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.(3) The value of V

is provided in the recommended operating conditions table.(4) The package thermal impedance is calculated in accordance with JESD 51-7.

MIN MAX UNIT

Operating 1.65 3.6V

Supply voltage VData retention only 1.5V

= 1.65 V to 1.95 V 0.65 ×V

High-level input voltage V

= 2.3 V to 2.7 V 1.7 VV

= 2.7 V to 3.6 V 2V

= 1.65 V to 1.95 V 0.35 ×V

Low-level input voltage V

= 2.3 V to 2.7 V 0.7 VV

= 2.7 V to 3.6 V 0.8V

Input voltage 0 5.5 VHigh or low state 0 V

CCV

Output voltage V3-state 0 5.5V

= 1.65 V –4V

= 2.3 V –8I

High-level output current mAV

= 2.7 V –12V

= 3 V –24V

= 1.65 V 4V

= 2.3 V 8I

Low-level output current mAV

= 2.7 V 12V

= 3 V 24∆t/ ∆v Input transition rise or fall rate 10 ns/VT

Operating free-air temperature –40 85 °C

(1) All unused control inputs of the device must be held at V

or GND to ensure proper device operation. Refer to the TI application report,Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

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Electrical Characteristics

Timing Requirements

SN74LVCH16652A-EP

16-BIT BUS TRANSCEIVER AND REGISTERWITH 3-STATE OUTPUTS

SCAS743A – DECEMBER 2003 – REVISED AUGUST 2005

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS V

MIN TYP

(1)

MAX UNIT

= –100 µA 1.65 V to 3.6 V V

– 0.2I

= –4 mA 1.65 V 1.2I

= -8 mA 2.3 V 1.7V

V2.7 V 2.2I

= –12 mA

3 V 2.4I

= –24 mA 3 V 2.2I

= 100 µA 1.65 V to 3.6 V 0.2I

= 4 mA 1.65 V 0.45V

= 8 mA 2.3 V 0.7 VI

= 12 mA 2.7 V 0.4I

= 24 mA 3 V 0.55Control in-I

= 0 to 5.5 V 3.6 V ±5µAputs

= 0.58 V

(2)1.65 VV

= 1.07 V

(2)

= 0.7 V 452.3 VI

I(hold)

A or B port V

= 1.7 V –45 µAV

= 0.8 V 753 VV

= 2 V –75V

= 0 to 3.6 V

(3)

3.6 V ±500I

off

or V

= 5.5 V 0 ±10 µAI

(4)

= 0 V or (V

to 5.5 V) 3.6 V ±10 µAV

= V

or GND 20I

= 0 3.6 V µA3.6 V ≤V

≤5.5 V

(5)

20∆I

One input at V

– 0.6 V, Other inputs at V

or GND 2.7 V to 3.6 V 500 µAControl in-C

= V

or GND 3.3 V 5 pFputsC

A or B port V

= V

or GND 3.3 V 8 pF

(1) All typical values are at V

= 3.3 V, T

= 25 °C.(2) This information was not available at the time of publication.(3) This is the bus-hold maximum dynamic current required to switch the input from one state to another.(4) For the total leakage current in an I/O port, please consult the I

I(hold)

specification for the input voltage condition 0 V < V

< V

, and theI

specification for the input voltage conditions V

= 0 V or V

= V

to 5.5 V. The bus-hold current, at input voltage greater than V

, isnegligible.

(5) This applies in the disabled state only.

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2 )

= 1.8 V V

= 2.5 V V

= 3.3 VV

= 2.7 V±0.15 V ±0.2 V ±0.3 V

UNITMIN MAX MIN MAX MIN MAX MIN MAX

clock

Clock frequency

(1) (1)

150 150 MHzt

Pulse duration, CLK high or low

(1) (1)

3.3 3.3 nst

Setup time, A or B before CLKAB ↑or CLKBA ↑

(1) (1)

3.4 3 nst

Hold time, A or B after CLKAB ↑or CLKBA ↑

(1) (1)

0 0.2 ns

(1) This information was not available at the time of publication.

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Switching Characteristics

Operating Characteristics

SN74LVCH16652A-EP16-BIT BUS TRANSCEIVER AND REGISTERWITH 3-STATE OUTPUTS

SCAS743A – DECEMBER 2003 – REVISED AUGUST 2005

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2 )

= 1.8 V V

= 2.5 V V

= 3.3 VV

= 2.7 VFROM TO

±0.15 V ±0.2 V ±0.3 VPARAMETER UNIT(INPUT) (OUTPUT)

MIN MAX MIN MAX MIN MAX MIN MAX

max

(1) (1)

150 150 MHzA or B B or A

(1) (1) (1) (1)

6.4 1.4 6.3t

CLKAB or CLKBA A or B

(1) (1) (1) (1)

7.3 2.4 6.4 nsSAB or SBA B or A

(1) (1) (1) (1)

8.8 1.9 7.4t

OE or OE A or B

(1) (1) (1) (1)

6.6 1.6 6.3 nst

dis

OE or OE A or B

(1) (1) (1) (1)

6.6 1.2 6.2 ns

(1) This information was not available at the time of publication.

= 25 °C

= 1.8 V V

= 2.5 V V

= 3.3 VTEST

±0.15 V ±0.2 V ±0.3 VPARAMETER UNITCONDITIONS

TYP TYP TYP

Outputs enabled

(1) (1)

55Power dissipation capacitanceC

f = 10 MHz pFper transceiver

Outputs disabled

(1) (1)

(1) This information was not available at the time of publication.

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PARAMETER MEASUREMENT INFORMATION

From Output

Under Test

(see Note A)

LOAD CIRCUIT

S1 VLOAD

Open

GND

Data Input

Timing Input VI

0 V

Input

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

INVERTING AND NONINVERTING OUTPUTS

VOLTAGE WAVEFORMS

PULSE DURATION

tPLH

tPHL

tPLH

VOH

VOL

0 V

Input

Output

Waveform 1

S1 at VLOAD

(see Note B)

Output

Waveform 2

S1 at GND

(see Note B)

VOL

VOH

tPZL

tPZH

tPLZ

tPHZ

VLOAD/2

0 V

VOL + V∆

VOH - V∆≈0 V

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

Output

tPLH/tPHL

tPLZ/tPZL

tPHZ/tPZH

Open

VLOAD

GND

TEST S1

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.

D. The outputs are measured one at a time, with one transition per measurement.

E. tPLZ and tPHZ are the same as tdis.

F. tPZL and tPZH are the same as ten.

G. tPLH and tPHL are the same as tpd.

H. All parameters and waveforms are not applicable to all devices.

Output

Control

VMVM

1.8 V ± 0.15 V

2.5 V ± 0.2 V

2.7 V

3 V ± 0.3 V

1 kΩ

500 Ω

VCC RL

2 × VCC

6 V

VLOAD CL

30 pF

50 pF

0.15 V

0.3 V

V∆

VCC

2.7 V

VCC/2

1.5 V

tr/tf

≤2 ns

≤2.5 ns

INPUTS

tsu th

SN74LVCH16652A-EP

16-BIT BUS TRANSCEIVER AND REGISTERWITH 3-STATE OUTPUTS

SCAS743A – DECEMBER 2003 – REVISED AUGUST 2005

Figure 2. Load Circuit and Voltage Waveforms

PACKAGING INFORMATION

Orderable Device Status (1) Package

Type Package

Drawing Pins Package

Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)

CLVCH16652AIDGGREP ACTIVE TSSOP DGG 56 2000 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

V62/04710-01XE ACTIVE TSSOP DGG 56 2000 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF SN74LVCH16652A-EP :

•Catalog: SN74LVCH16652A

NOTE: Qualified Version Definitions:

•Catalog - TI's standard catalog product

PACKAGE OPTION ADDENDUM

www.ti.com 18-Sep-2008

Addendum-Page 1

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

A0 (mm) B0 (mm) K0 (mm) P1

(mm) W

(mm) Pin1

Quadrant

CLVCH16652AIDGGREP TSSOP DGG 56 2000 330.0 24.4 8.6 15.6 1.8 12.0 24.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 5-Aug-2008

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

CLVCH16652AIDGGREP TSSOP DGG 56 2000 346.0 346.0 41.0

PACKAGE MATERIALS INFORMATION

www.ti.com 5-Aug-2008

Pack Materials-Page 2

MECHANICAL DATA

MTSS003D – JANUARY 1995 – REVISED JANUAR Y 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

4040078/F 12/97

48 PINS SHOWN

0,25

0,15 NOM

Gage Plane

6,00

6,20 8,30

7,90

0,75

0,50

Seating Plane

0,27

0,17

1,20 MAX

0,08

0,10

0,50

0°–8°

14,10

13,90

DIM

A MAX

A MIN

PINS **

12,40

12,60

17,10

16,90

0,15

0,05

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold protrusion not to exceed 0,15.

D. Falls within JEDEC MO-153

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