3
2
4
51
D VCC
Q
CLK
GND
DCK PACKAGE
(TOP VIEW)
3
2
4
51
D VCC
Q
CLK
GND
DRL PACKAGE
(TOP VIEW)
DBV PACKAGE
(TOP VIEW)
3
2
4
51
D VCC
Q
CLK
GND
DRY PACKAGE
(TOP VIEW)
CLK N.C.
D6
5
4
2
3
GND Q
VCC
1
GND Q
34
CLK 25
D6
1
N.C.
VCC
DSF PACKAGE
(TOP VIEW)
YZP PACKAGE
(TOP VIEW)
GND
D
Q
VCC
CLK
3
5
2
1
4
A1
B1
C1
A2
C2
YFP PACKAGE
(TOP VIEW)
GND
D
Q
VCC
CLK
3
6
2
1
4
5N.C.
A1
B1
C1
A2
B2
C2
SN74AUP1G79
www.ti.com
SCES592G –JULY 2004–REVISED MAY 2010
LOW-POWER SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
Check for Samples: SN74AUP1G79
1FEATURES
• Available in the Texas Instruments NanoStar™ • Wide Operating VCC Range of 0.8 V to 3.6 V
Package • Optimized for 3.3-V Operation
• Low Static-Power Consumption: • 3.6-V I/O Tolerant to Support Mixed-Mode
ICC = 0.9 mA Max Signal Operation
• Low Dynamic-Power Consumption: • tpd = 4 ns Max at 3.3 V
Cpd = 3 pF Typ at 3.3 V • Suitable for Point-to-Point Applications
• Low Input Capacitance: • Latch-Up Performance Exceeds 100 mA Per
Ci= 1.5 pF Typ JESD 78, Class II
• Low Noise: Overshoot and Undershoot • ESD Performance Tested Per JESD 22
<10% of VCC – 2000-V Human-Body Model
• Ioff Supports Partial Power-Down-Mode (A114-B, Class II)
Operation – 1000-V Charged-Device Model (C101)
• Input Hysteresis Allows Slow Input Transition
and Better Switching Noise Immunity at the
Input (Vhys = 250 mV Typ at 3.3 V)
N.C. – No internal connection
See mechanical drawings for dimensions.
DESCRIPTION/ORDERING INFORMATION
The AUP family is TI's premier solution to the industry's low-power needs in battery-powered portable
applications. This family ensures a very low static and dynamic power consumption across the entire VCC range
of 0.8 V to 3.6 V, resulting in an increased battery life. This product also maintains excellent signal integrity (see
Figure 1 and Figure 2).
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright © 2004–2010, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
AUP
LVC
AUP
AUP
LVC
Static-Power Consumption
(µA) Dynamic-Power Consumption
(pF)
†Single, dual, and triple gates
3.3-V
Logic† 3.3-V
Logic†
0%
20%
40%
60%
80%
100%
0%
20%
40%
60%
80%
100%
−0.5
0
0.5
1
1.5
2
2.5
3
3.5
0 5 10 15 20 25 30 35 40 45
Time − ns
Voltage − V
†AUP1G08 data at CL = 15 pF
OutputInput
Switching Characteristics
at 25 MHz†
SN74AUP1G79
SCES592G –JULY 2004–REVISED MAY 2010
www.ti.com
Figure 1. AUP – The Lowest-Power Family Figure 2. Excellent Signal Integrity
This is a single positive-edge-triggered D-type flip-flop. When data at the data (D) input meets the setup time
requirement, the data is transferred to the Q output on the positive-going edge of the clock pulse. Clock
triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the
hold-time interval, data at the D input can be changed without affecting the levels at the outputs.
NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the
package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION(1)
ORDERABLE TOP-SIDE
TAPACKAGE(2) PART NUMBER MARKING(3)
NanoStar – WCSP (DSBGA) Reel of 3000 SN74AUP1G79YFPR _ _ H W _
0.23-mm Large Bump – YFP (Pb-free)
NanoStar – WCSP (DSBGA) Reel of 3000 SN74AUP1G79YZPR _ _ H W _
0.23-mm Large Bump – YZP (Pb-free)
QFN – DRY Reel of 5000 SN74AUP1G79DRYR HW
uQFN – DSF Reel of 5000 SN74AUP1G79DSFR HW
–40°C to 85°C Reel of 3000 SN74AUP1G79DBVR
SOT (SOT-23) – DBV H79_
Reel of 250 SN74AUP1G79DBVT
Reel of 3000 SN74AUP1G79DCKR
SOT (SC-70) – DCK HW_
Reel of 250 SN74AUP1G79DCKT
SOT (SOT-553) – DRL Reel of 4000 SN74AUP1G79DRLR HW_
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(3) DBV/DCK/DRL: The actual top-side marking has one additional character that designates the wafer fab/assembly site.
YFP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the wafer fab/assembly site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).
FUNCTION TABLE
INPUTS OUTPUT
Q
CLK D
↑H H
↑L L
L or H X Q0
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D
CLK
Q
CLK
DQ
SN74AUP1G79
www.ti.com
SCES592G –JULY 2004–REVISED MAY 2010
LOGIC DIAGRAM (POSITIVE LOGIC)
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT
VCC Supply voltage range –0.5 4.6 V
VIInput voltage range(2) –0.5 4.6 V
VOVoltage range applied to any output in the high-impedance or power-off state(2) –0.5 4.6 V
VOOutput voltage range in the high or low state(2) –0.5 VCC + 0.5 V
IIK Input clamp current VI< 0 –50 mA
IOK Output clamp current VO< 0 –50 mA
IOContinuous output current ±20 mA
Continuous current through VCC or GND ±50 mA
DBV package 206
DCK package 252
DRL package 142
qJA Package thermal impedance(3) DRY package 234 °C/W
DSF package 300
YFP package 132
YZP package 132
Tstg Storage temperature range –65 150 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The package thermal impedance is calculated in accordance with JESD 51-7.
Copyright © 2004–2010, Texas Instruments Incorporated Submit Documentation Feedback 3
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SCES592G –JULY 2004–REVISED MAY 2010
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RECOMMENDED OPERATING CONDITIONS(1)
MIN MAX UNIT
VCC Supply voltage 0.8 3.6 V
VCC = 0.8 V VCC
VCC = 1.1 V to 1.95 V 0.65 × VCC
VIH High-level input voltage V
VCC = 2.3 V to 2.7 V 1.6
VCC = 3 V to 3.6 V 2
VCC = 0.8 V 0
VCC = 1.1 V to 1.95 V 0.35 × VCC
VIL Low-level input voltage V
VCC = 2.3 V to 2.7 V 0.7
VCC = 3 V to 3.6 V 0.9
VIInput voltage 0 3.6 V
VOOutput voltage 0 VCC V
VCC = 0.8 V –20 mA
VCC = 1.1 V –1.1
VCC = 1.4 V –1.7
IOH High-level output current VCC = 1.65 V –1.9 mA
VCC = 2.3 V –3.1
VCC = 3 V –4
VCC = 0.8 V 20 mA
VCC = 1.1 V 1.1
VCC = 1.4 V 1.7
IOL Low-level output current VCC = 1.65 V 1.9 mA
VCC = 2.3 V 3.1
VCC = 3 V 4
Δt/Δv Input transition rise or fall rate VCC = 0.8 V to 3.6 V 200 ns/V
TAOperating free-air temperature –40 85 °C
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See the TI application report
Implications of Slow or Floating CMOS Inuts, literature number SCBA004.
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SCES592G –JULY 2004–REVISED MAY 2010
ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
TA= 25°C TA= –40°C to 85°C
PARAMETER TEST CONDITIONS VCC UNIT
MIN TYP MAX MIN MAX
IOH = –20 mA 0.8 V to 3.6 V VCC – 0.1 VCC – 0.1
IOH = –1.1 mA 1.1 V 0.75 × VCC 0.7 × VCC
IOH = –1.7 mA 1.4 V 1.11 1.03
IOH = –1.9 mA 1.65 V 1.32 1.3
VOH V
IOH = –2.3 mA 2.05 1.97
2.3 V
IOH = –3.1 mA 1.9 1.85
IOH = –2.7 mA 2.72 2.67
3 V
IOH = –4 mA 2.6 2.55
IOL = 20 mA 0.8 V to 3.6 V 0.1 0.1
IOL = 1.1 mA 1.1 V 0.3 × VCC 0.3 × VCC
IOL = 1.7 mA 1.4 V 0.31 0.37
IOL = 1.9 mA 1.65 V 0.31 0.35
VOL V
IOL = 2.3 mA 0.31 0.33
2.3 V
IOL = 3.1 mA 0.44 0.45
IOL = 2.7 mA 0.31 0.33
3 V
IOL = 4 mA 0.44 0.45
D or CLK
IIVI= GND to 3.6 V 0 V to 3.6 V 0.1 0.5 mA
input
Ioff VIor VO= 0 V to 3.6 V 0 V 0.2 0.6 mA
ΔIof VIor VO= 0 V to 3.6 V 0 V to 0.2 V 0.2 0.6 mA
f
ICC VI= GND or VCC to 3.6 V, IO= 0 0.8 V to 3.6 V 0.5 0.9 mA
ΔICVI= VCC – 0.6 V,(1) IO= 0 3.3 V 40 50 mA
C0 V 1.5
CiVI= VCC or GND pF
3.6 V 1.5
CoVO= GND 0 V 3 pF
(1) One-input switching
Copyright © 2004–2010, Texas Instruments Incorporated Submit Documentation Feedback 5
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SCES592G –JULY 2004–REVISED MAY 2010
www.ti.com
TIMING REQUIREMENTS
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)TA= –40°C
TA= 25°C to 85°C
VCC UNIT
TYP MIN MAX
0.8 V 20
1.2 V ± 0.1 V 80
1.5 V ± 0.1 V 100
fclock Clock frequency MHz
1.8 V ± 0.15 V 140
2.5 V ± 0.2 V 210
3.3 V ± 0.3 V 260
0.8 V 4.8
1.2 V ± 0.1 V 2.2
1.5 V ± 0.1 V 1.5
twPulse duration, CLK high or low ns
1.8 V ± 0.15 V 1.6
2.5 V ± 0.2 V 1.7
3.3 V ± 0.3 V 1.9
0.8 V 2.9 4.2
1.2 V ± 0.1 V 1.4
1.5 V ± 0.1 V 1
Data high 1.8 V ± 0.15 V 0.9
2.5 V ± 0.2 V 0.7
3.3 V ± 0.3 V 0.6
tsu Setup time before CLK↑ns
0.8 V 3.5 5.3
1.2 V ± 0.1 V 1.8
1.5 V ± 0.1 V 1.2
Data low 1.8 V ± 0.15 V 1.1
2.5 V ± 0.2 V 1
3.3 V ± 0.3 V 1
0.8 V 0 0
1.2 V ± 0.1 V 0
1.5 V ± 0.1 V 0
thHold time, data after CLK↑ns
1.8 V ± 0.15 V 0
2.5 V ± 0.2 V 0
3.3 V ± 0.3 V 0
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SCES592G –JULY 2004–REVISED MAY 2010
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range, CL= 5 pF (unless otherwise noted) (see Figure 3 and Figure 4)
TA= –40°C
TA= 25°C
FROM TO to 85°C
PARAMETER VCC UNIT
(INPUT) (OUTPUT) MIN TYP MAX MIN MAX
0.8 V 93 90
1.2 V ± 0.1 V 199 220
1.5 V ± 0.1 V 250 230
fmax MHz
1.8 V ± 0.15 V 271 240
2.5 V ± 0.2 V 280 250
3.3 V ± 0.3 V 280 260
0.8 V 15.9
1.2 V ± 0.1 V 3.7 6.9 11 2.6 13.1
1.5 V ± 0.1 V 3 4.8 7.6 2 8.8
tpd CLK Q ns
1.8 V ± 0.15 V 2.4 3.8 6.1 1.5 7.1
2.5 V ± 0.2 V 1.8 2.7 4.4 1.1 5
3.3 V ± 0.3 V 1.5 2.1 3.6 0.9 4
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range, CL= 10 pF (unless otherwise noted) (see Figure 3 and Figure 4)
TA= –40°C
TA= 25°C
FROM TO to 85°C
PARAMETER VCC UNIT
(INPUT) (OUTPUT) MIN TYP MAX MIN MAX
0.8 V 62 50
1.2 V ± 0.1 V 147 160
1.5 V ± 0.1 V 189 200
fmax MHz
1.8 V ± 0.15 V 180 240
2.5 V ± 0.2 V 260 250
3.3 V ± 0.3 V 280 260
0.8 V 18
1.2 V ± 0.1 V 4.3 7.8 12.3 3.2 14.4
1.5 V ± 0.1 V 3.5 5.5 8.4 2.5 9.8
tpd CLK Q ns
1.8 V ± 0.15 V 2.8 4.4 6.8 1.9 8
2.5 V ± 0.2 V 2.2 3.2 5 1.5 5.7
3.3 V ± 0.3 V 1.8 2.6 4.1 1.3 4.5
Copyright © 2004–2010, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Link(s): SN74AUP1G79
SN74AUP1G79
SCES592G –JULY 2004–REVISED MAY 2010
www.ti.com
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range, CL= 15 pF (unless otherwise noted) (see Figure 3 and Figure 4)
TA= –40°C
TA= 25°C
FROM TO to 85°C
PARAMETER VCC UNIT
(INPUT) (OUTPUT) MIN TYP MAX MIN MAX
0.8 V 48 30
1.2 V ± 0.1 V 112 120
1.5 V ± 0.1 V 151 160
fmax MHz
1.8 V ± 0.15 V 194 220
2.5 V ± 0.2 V 248 250
3.3 V ± 0.3 V 280 260
0.8 V 20.3
1.2 V ± 0.1 V 5 8.7 13.6 3.9 15.6
1.5 V ± 0.1 V 4.1 6.3 9.3 3.1 10.7
tpd CLK Q ns
1.8 V ± 0.15 V 3.3 4 7.6 2.4 8.7
2.5 V ± 0.2 V 2.6 3.6 5.5 1.9 6.3
3.3 V ± 0.3 V 2.2 3 4.5 1.6 5
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range, CL= 30 pF (unless otherwise noted) (see Figure 3 and Figure 4)
TA= –40°C
TA= 25°C
FROM TO to 85°C
PARAMETER VCC UNIT
(INPUT) (OUTPUT) MIN TYP MAX MIN MAX
0.8 V 24 20
1.2 V ± 0.1 V 72 80
1.5 V ± 0.1 V 100 100
fmax MHz
1.8 V ± 0.15 V 127 140
2.5 V ± 0.2 V 185 210
3.3 V ± 0.3 V 266 260
0.8 V 27.2
1.2 V ± 0.1 V 7 11.5 17.3 5.9 24
1.5 V ± 0.1 V 5.7 8.3 11.8 4.6 15.9
tpd CLK Q ns
1.8 V ± 0.15 V 4.7 6.7 9.6 3.8 13
2.5 V ± 0.2 V 3.7 4.9 7 2.9 9
3.3 V ± 0.3 V 3.2 4.1 5.8 2.6 7.2
OPERATING CHARACTERISTICS
TA= 25°C PARAMETER TEST CONDITIONS VCC TYP UNIT
0.8 V 2.5
1.2 V ± 0.1 V 2.5
1.5 V ± 0.1 V 2.5
Cpd Power dissipation capacitance f = 10 MHz pF
1.8 V ± 0.15 V 2.5
2.5 V ± 0.2 V 3
3.3 V ± 0.3 V 3
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Product Folder Link(s): SN74AUP1G79
VM
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT
1 MΩ
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
VI
0 V
Input
Output
Output
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf = 3 ns.
C. The outputs are measured one at a time, with one transition per measurement.
D. tPLH and tPHL are the same as tpd.
E. All parameters and waveforms are not applicable to all devices.
VMVM
VMVM
VM
5, 10, 15, 30 pF
VCC/2
VCC
VCC = 1.2 V
± 0.1 V
VCC = 0.8 V VCC = 1.5 V
± 0.1 V VCC = 1.8 V
± 0.15 V VCC = 2.5 V
± 0.2 V VCC = 3.3 V
± 0.3 V
5, 10, 15, 30 pF
VCC/2
VCC
5, 10, 15, 30 pF
VCC/2
VCC
5, 10, 15, 30 pF
VCC/2
VCC
CL
VM
VI
5, 10, 15, 30 pF
VCC/2
VCC
5, 10, 15, 30 pF
VCC/2
VCC
th
tsu
Data Input
Timing Input VCC
0 V
VCC
0 V
0 V
tw
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VCC/2 VCC/2
VCC/2
VCC/2
VCC
VCC/2
SN74AUP1G79
www.ti.com
SCES592G –JULY 2004–REVISED MAY 2010
PARAMETER MEASUREMENT INFORMATION
(Propagation Delays, Setup and Hold Times, and Pulse Width)
Figure 3. Load Circuit and Voltage Waveforms
Copyright © 2004–2010, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Link(s): SN74AUP1G79
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf = 3 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. All parameters and waveforms are not applicable to all devices.
5, 10, 15, 30 pF
VCC/2
VCC
0.15 V
VCC = 1.2 V
± 0.1 V
VCC = 0.8 V VCC = 1.5 V
± 0.1 V VCC = 1.8 V
± 0.15 V VCC = 2.5 V
± 0.2 V VCC = 3.3 V
± 0.3 V
5, 10, 15, 30 pF
VCC/2
VCC
0.1 V
5, 10, 15, 30 pF
VCC/2
VCC
0.1 V
5, 10, 15, 30 pF
VCC/2
VCC
0.1 V
CL
VM
VI
V∆
5, 10, 15, 30 pF
VCC/2
VCC
0.15 V
5, 10, 15, 30 pF
VCC/2
VCC
0.3 V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
VCC
0 V
VOL + V∆
VOH − V∆
≈0 V
VCC
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Output
Control VCC/2 VCC/2
VCC/2
VCC/2
tPLZ/tPZL
tPHZ/tPZH
2 × VCC
GND
TEST S1
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT
S1
GND
5 kΩ
5 kΩ
2 × VCC
SN74AUP1G79
SCES592G –JULY 2004–REVISED MAY 2010
www.ti.com
PARAMETER MEASUREMENT INFORMATION
(Enable and Disable Times)
Figure 4. Load Circuit and Voltage Waveforms
10 Submit Documentation Feedback Copyright © 2004–2010, Texas Instruments Incorporated
Product Folder Link(s): SN74AUP1G79
PACKAGE OPTION ADDENDUM
www.ti.com 21-Oct-2011
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
SN74AUP1G79DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AUP1G79DBVRE4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AUP1G79DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AUP1G79DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AUP1G79DBVTE4 ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AUP1G79DBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AUP1G79DCKR ACTIVE SC70 DCK 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AUP1G79DCKRE4 ACTIVE SC70 DCK 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AUP1G79DCKRG4 ACTIVE SC70 DCK 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AUP1G79DCKT ACTIVE SC70 DCK 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AUP1G79DCKTE4 ACTIVE SC70 DCK 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AUP1G79DCKTG4 ACTIVE SC70 DCK 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AUP1G79DRLR ACTIVE SOT DRL 5 4000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AUP1G79DRLRG4 ACTIVE SOT DRL 5 4000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AUP1G79DRYR ACTIVE SON DRY 6 5000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AUP1G79DSFR ACTIVE SON DSF 6 5000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AUP1G79YFPR ACTIVE DSBGA YFP 6 3000 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 21-Oct-2011
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
SN74AUP1G79YZPR ACTIVE DSBGA YZP 5 3000 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74AUP1G79DBVR SOT-23 DBV 5 3000 180.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3
SN74AUP1G79DBVT SOT-23 DBV 5 250 180.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3
SN74AUP1G79DCKR SC70 DCK 5 3000 180.0 9.2 2.3 2.55 1.2 4.0 8.0 Q3
SN74AUP1G79DCKT SC70 DCK 5 250 180.0 8.4 2.25 2.4 1.22 4.0 8.0 Q3
SN74AUP1G79DRLR SOT DRL 5 4000 180.0 8.4 1.98 1.78 0.69 4.0 8.0 Q3
SN74AUP1G79DRYR SON DRY 6 5000 180.0 9.5 1.15 1.6 0.75 4.0 8.0 Q1
SN74AUP1G79DSFR SON DSF 6 5000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q2
SN74AUP1G79YFPR DSBGA YFP 6 3000 178.0 9.2 0.89 1.29 0.62 4.0 8.0 Q1
SN74AUP1G79YZPR DSBGA YZP 5 3000 180.0 8.4 1.02 1.52 0.63 4.0 8.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 29-Aug-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74AUP1G79DBVR SOT-23 DBV 5 3000 202.0 201.0 28.0
SN74AUP1G79DBVT SOT-23 DBV 5 250 202.0 201.0 28.0
SN74AUP1G79DCKR SC70 DCK 5 3000 205.0 200.0 33.0
SN74AUP1G79DCKT SC70 DCK 5 250 202.0 201.0 28.0
SN74AUP1G79DRLR SOT DRL 5 4000 202.0 201.0 28.0
SN74AUP1G79DRYR SON DRY 6 5000 180.0 180.0 30.0
SN74AUP1G79DSFR SON DSF 6 5000 180.0 180.0 30.0
SN74AUP1G79YFPR DSBGA YFP 6 3000 220.0 220.0 35.0
SN74AUP1G79YZPR DSBGA YZP 5 3000 220.0 220.0 34.0
PACKAGE MATERIALS INFORMATION
www.ti.com 29-Aug-2012
Pack Materials-Page 2
X: Max =
Y: Max =
1.202 mm, Min =
0.802 mm, Min =
1.142 mm
0.742 mm
X: Max =
Y: Max =
1.202 mm, Min =
0.802 mm, Min =
1.142 mm
0.742 mm
X: Max =
Y: Max =
1.202 mm, Min =
0.802 mm, Min =
1.142 mm
0.742 mm
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