Si5315 S Y N C H R O N O U S E T H E R N E T / TE LE C O M J I T T E R A T T E N U A T I N G C L O C K M U L T I PL I E R Features Provides jitter attenuation and frequency translation between SONET/PDH and Ethernet Supports ITU-T G.8262 Synchronous Ethernet equipment slave clock (EEC option 1 and 2) requirements with optional Stratum 3 compliant timing card clock source Two clock inputs/two clock outputs Input frequency range: 8 kHz-644 MHz Output frequency range: 8 kHz-644 MHz Ultra low jitter: 0.23 ps RMS (1.875-20 MHz) 0.47 ps RMS (12 kHz-20 MHz) Simple pin control interface Selectable loop bandwidth for jitter attenuation: 60 to 8.4 kHz Automatic/Manual hitless switching and holdover during loss of inputs clock Programmable output clock signal format: LVPECL, LVDS, CML or CMOS 40 MHz crystal or XO reference Single supply: 1.8, 2.5, or 3.3 V On-chip voltage regulator with high PSRR Loss of lock and loss of signal alarms Small size: 6 x 6 mm, 36-QFN Wide temperature range: -40 to +85 C Ordering Information: See page 48. Applications CKOUT1- CKOUT1+ SFOUT1 GND SFOUT0 VDD Description CKOUT2- Pin Assignments Carrier Ethernet switches routers MSAN / DSLAM T1/E1/DS3/E3 line cards NC CKOUT2+ Synchronous Ethernet line cards SONET OC-3/12/48 line cards PON OLT/ONU 36 35 34 33 32 31 30 29 28 27 FRQSEL3 FRQTBL 2 26 FRQSEL2 25 FRQSEL1 LOS1 3 LOS2 4 VDD 5 XA 6 XB 24 FRQSEL0 GND Pad 23 BWSEL1 22 BWSEL0 7 21 CS_CA GND 8 20 GND 19 GND AUTOSEL 9 LOL CKIN1- GND CKIN1+ DBL2_BY CKIN2- CKIN2+ 10 11 12 13 14 15 16 17 18 VDD The Si5315 is a jitter-attenuating clock multiplier for Gb and 10G Synchronous Ethernet, SONET/SDH, and PDH (T1/E1) applications. The Si5315 supports SyncE EEC options 1 and 2 when paired with a timing card that implements the required wander filter. The Si5315 accepts dual clock inputs ranging from 8 kHz to 644.53 MHz and generates two equal frequency-multiplied clock outputs ranging from 8 kHz to 644.53 MHz. The input clock frequency and clock multiplication ratio are selectable from a table of popular SyncE and T1/E1 rates. The Si5315 is based on Silicon Laboratories' third-generation DSPLL(R) technology, which provides any-frequency synthesis and jitter attenuation in a highly integrated PLL solution that eliminates the need for external VCXO and loop filter components. The DSPLL loop bandwidth is user programmable, providing jitter performance optimization at the application level. RST 1 XTAL/CLOCK Functional Block Diagram XTAL/Clock Si5315 Clock Out 1 Clock In 1 (R) Output Signal Format[1:0] DSPLL Clock In 2 Loss of Lock Loss of Signal 1 Loss of Signal 2 Clock Out 2 Clock 2 Disable/PLL Bypass Status/Control VDD (1.8, 2.5, or 3.3 V) GND Frequency Select[3:0] Frequency Table Select Loop Bandwidth Select[1:0] Rev. 1.0 4/12 Manual/Auto Clock Selection Clock Switch/Clock Active Indicator XTAL/Clock Copyright (c) 2012 by Silicon Laboratories Si5315 Si5315 2 Rev. 1.0 Si5315 TABLE O F C ONTENTS Section Page 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 1.1. Three-Level (3L) Input Pins (No External Resistors) . . . . . . . . . . . . . . . . . . . . . . . .11 1.2. Three-Level (3L) Input Pins (With External Resistors) . . . . . . . . . . . . . . . . . . . . . . . 12 2. Typical Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 3. System Level Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.2. PLL Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5. Frequency Plan Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 5.1. Frequency Multiplication Plan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 5.2. PLL Self-Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.3. Input Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.4. Alarms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.5. Holdover Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.6. PLL Bypass Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6. High-Speed I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.1. Input Clock Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.2. Output Clock Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 7. Crystal/Reference Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 7.1. Crystal/Reference Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 8. Power Supply Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 9. Typical Phase Noise Plots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 9.1. 10G LAN SyncE Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 10. Pin Descriptions: Si5315 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 11. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 12. Package Outline: 36-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 13. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 14. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 14.1. Si5315 Top Marking (QFN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 14.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 Rev. 1.0 3 Si5315 1. Electrical Specifications Table 1. Recommended Operating Conditions (VDD = 1.8 5%, 2.5 10%, or 3.3 V 10%, TA = -40 to 85 C) Parameter Symbol Temperature Range Supply Voltage Test Condition Min Typ Max Unit -40 25 85 C 3.3 V nominal 2.97 3.3 3.63 V 2.5 V nominal 2.25 2.5 2.75 V 1.8 V nominal 1.71 1.8 1.89 V TA VDD Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25 C unless otherwise noted. Table 2. DC Characteristics (VDD = 1.8 5%, 2.5 10%, or 3.3 V 10%, TA = -40 to 85 C) Parameter Supply Current (Supply current is independent of VDD) Symbol Test Condition Min Typ Max Units IDD LVPECL Format 644.53125 MHz Out All CKOUTs Enabled1 -- 251 279 mA LVPECL Format 644.53125 MHz Out Only 1 CKOUT Enabled1 -- 217 243 mA CMOS Format 25.00 MHz Out All CKOUTs Enabled2 -- 204 234 mA CMOS Format 25.00 MHz Out Only CKOUT1 Enabled2 -- 194 220 mA 1.8 V 5% 0.9 -- 1.4 V 2.5 V 10% 1.0 -- 1.7 V 3.3 V 10% 1.1 -- 1.95 V Single-ended 20 40 60 k 0 -- VDD V CKINn Input Pins Input Common Mode Voltage (Input Threshold Voltage) VICM Input Resistance CKNRIN Input Voltage Level Limits CKNVIN Notes: 1. Refers to Si5315A speed grade. 2. Refers to Si5315B speed grade. 3. This is the amount of leakage that the 3L inputs can tolerate from an external driver. See Figure 3 on page 11. 4 Rev. 1.0 Si5315 Table 2. DC Characteristics (Continued) (VDD = 1.8 5%, 2.5 10%, or 3.3 V 10%, TA = -40 to 85 C) Parameter Symbol Test Condition Min Typ Max Units VISE fCKIN < 212.5 MHz See Figure 2. 0.2 -- -- VPP fCKIN > 212.5 MHz See Figure 2. 0.25 -- -- VPP fCKIN < 212.5 MHz See Figure 2. 0.2 -- -- VPP fCKIN > 212.5 MHz See Figure 2. 0.25 -- -- VPP VOCM LVPECL 100 load line-to-line VDD - 1.42 -- VDD - 1.25 V Differential Output Swing VOD LVPECL 100 load line-to-line 1.1 -- 1.9 VPP Single Ended Output Swing VSE LVPECL 100 load line-to-line 0.5 -- 0.93 VPP Differential Output Voltage CKOVD CML 100 load line-to-line 350 425 500 mVPP Common Mode Output Voltage CKOVCM CML 100 load line-to-line -- VDD - 0.36 -- V Differential Output Voltage CKOVD LVDS 100 load line-to-line 500 700 900 mVPP Low swing LVDS 100 load line-to-line 350 425 500 mVPP CKOVCM LVDS 100 load line-to-line 1.125 1.2 1.275 V CKORD CML, LVPECL, LVDS, Disable -- 200 -- Output Voltage Low CKOVOLLH CMOS -- -- 0.4 V Output Voltage High CKOVOHLH VDD = 1.71 V CMOS 0.8 x VDD -- -- V Single-ended Input Voltage Swing Differential Input Voltage Swing VID CKOUTn Output Clocks Common Mode Common Mode Output Voltage Differential Output Resistance Notes: 1. Refers to Si5315A speed grade. 2. Refers to Si5315B speed grade. 3. This is the amount of leakage that the 3L inputs can tolerate from an external driver. See Figure 3 on page 11. Rev. 1.0 5 Si5315 Table 2. DC Characteristics (Continued) (VDD = 1.8 5%, 2.5 10%, or 3.3 V 10%, TA = -40 to 85 C) Parameter Output Drive Current Symbol Test Condition Min Typ Max Units CKOIO CMOS Driving into CKOVOL for output low or CKOVOH for output high. CKOUT+ and CKOUT- shorted externally. VDD = 1.71 V 7.5 -- -- mA VDD = 2.97 V 32 -- -- mA VDD = 1.71 V -- -- 0.5 V VDD = 2.25 V -- -- 0.7 V VDD = 2.97 V -- -- 0.8 V VDD = 1.89 V 1.4 -- -- V VDD = 2.25 V 1.8 -- -- V VDD = 3.63 V 2.5 -- -- V 2-Level LVCMOS Input Pins Input Voltage Low Input Voltage High VIL VIH Input Low Current IIL -- -- 50 A Input High Current IIH -- -- 50 A Weak Internal Input Pull-up Resistor RPUP -- 75 -- k Weak Internal Input Pull-down Resistor RPDN -- 75 -- k Input Voltage Low VILL -- -- 0.15 x VDD V Input Voltage Mid VIMM 0.45 x VDD -- 0.55 x VDD V Input Voltage High VIHH 0.85 x VDD -- -- V Input Low Current IILL See note 3. -20 -- -- A Input Mid Current IIMM See note 3. -2 -- 2 A Input High Current IIHH See note 3. -- -- 20 A 3-Level Input Pins Notes: 1. Refers to Si5315A speed grade. 2. Refers to Si5315B speed grade. 3. This is the amount of leakage that the 3L inputs can tolerate from an external driver. See Figure 3 on page 11. 6 Rev. 1.0 Si5315 Table 2. DC Characteristics (Continued) (VDD = 1.8 5%, 2.5 10%, or 3.3 V 10%, TA = -40 to 85 C) Parameter Symbol Test Condition Min Typ Max Units VOL IO = 2 mA VDD = 1.62 V -- -- 0.4 V IO = 2 mA VDD = 2.97 V -- -- 0.4 V IO = -2 mA VDD = 1.62 V VDD - 0.4 -- -- V IO = -2 mA VDD = 2.97 V VDD - 0.4 -- -- V RST = 0 -100 -- 100 A -- 12 -- k LVCMOS Output Pins Output Voltage Low Output Voltage High Disabled Leakage Current VOH IOZ Single-Ended Reference Clock Input Pin XA (XB with Cap to Gnd) Input Resistance XARIN Input Voltage Level Limits XAVIN 0 -- 1.2 V Input Voltage Swing XAVPP 0.5 -- 1.2 VPP -- 12 -- k XTAL/CLOCK = M Differential Reference Clock Input Pins (XA/XB) Input Resistance XA/XBRIN Differential Input Voltage Level Limits XA/XBVIN 0 -- 1.2 V XAVPP/XBVPP 0.5 -- 2.4 VPP Input Voltage Swing XTAL/CLOCK = M Notes: 1. Refers to Si5315A speed grade. 2. Refers to Si5315B speed grade. 3. This is the amount of leakage that the 3L inputs can tolerate from an external driver. See Figure 3 on page 11. Rev. 1.0 7 Si5315 Table 3. AC Characteristics (VDD = 1.8 5%, 2.5 10%, or 3.3 V 10%, TA = -40 to 85 C) Parameter Input Frequency Symbol Test Condition Min Typ Max Units 0.008 -- 644.53 MHz 40 -- 60 % 2 -- -- ns -- -- 3 pF 20-80% See Figure 2 -- -- 11 ns Note 2 0.008 -- 644.53 MHz Note 3 0.008 -- 125 MHz CKNF CKINn Input Pins Input Duty Cycle (Minimum Pulse Width) CKNDC Input Capacitance CKNCIN Input Rise/Fall Time CKNTRF Whichever is smaller1 CKOUTn Output Pins Output Frequency (Output not configured for CMOS or disable) CKOF Maximum Output Frequency in CMOS Format CKOFMC -- -- 161.13 MHz Output Rise/Fall (20-80%) at 644.5313 MHz CKOTRF Output not configured for CMOS or disabled, see Figure 2 -- 230 350 ps CMOS Output VDD = 1.62 Cload = 5 pF -- -- 8 ns CMOS Output VDD = 2.97 Cload = 5 pF -- -- 2 ns 100 Load Line to Line Measured at 50% Point (not for CMOS) -- -- 40 ps -- -- 3 pF Single Ended Output Rise/Fall (20-80%) CKOTRF Output Duty Cycle Differential Uncertainty CKODC LVCMOS Pins Input Capacitance Cin Notes: 1. Assumes N3 does not equal 1. IF N3 = 1, CKNDC = 50 s. 2. Refers to Si5315A speed grade. 3. Refers to Si5315B speed grade. 8 Rev. 1.0 Si5315 Table 3. AC Characteristics (Continued) (VDD = 1.8 5%, 2.5 10%, or 3.3 V 10%, TA = -40 to 85 C) Parameter Symbol Test Condition Min Typ Max Units tRF CLOAD = 20 pf See Figure 2 -- 25 -- ns From last CKINn to internal detection of LOSn -- -- 750 s tCLRLOL LOS to LOL Assume Fold=Fnew, Stable XA-XB reference -- 10 -- ms Output Clock Skew tSKEW of CKOUTn to CKOUTn -- -- 100 ps Phase Change Due to Temperature Variation tTEMP Maximum phase change from -40 to +85 C -- 300 500 ps -- 1200 -- ms -- 0.05 0.1 dB LVCMOS Output Pins Rise/Fall Times LOSn Trigger Window Time to Clear LOL after LOS Cleared LOSTRIG PLL Performance Lock Time Closed Loop Jitter Peaking Jitter Tolerance Minimum Reset Pulse Width Output Clock Initial Phase Step tLOCKHW RST with valid CKIN to LOL; BW = 100 Hz JPK tRSTMIN tP_STEP Holdover Frequency Historical Averaging Time tHISTAVG Holdover Frequency Historical Delay Time tHISTDEL Spurious Noise See 4.2.3. "Jitter Tolerance" on page 18. JTOL SPSPUR During clock switch CKIN > 19.44 MHz Max spur @ n x f3 (n > 1, n x f3 < 100 MHz) ns pkpk 1 -- -- s -- 100 200 ps -- 6.7 -- sec -- 26.2 -- ms -- -75 -- dBc Notes: 1. Assumes N3 does not equal 1. IF N3 = 1, CKNDC = 50 s. 2. Refers to Si5315A speed grade. 3. Refers to Si5315B speed grade. Rev. 1.0 9 Si5315 Table 4. Jitter Generation (VDD = 1.8 5%, 2.5 10%, or 3.3 V 10%, TA = -40 to 85 C) Parameter Symbol Jitter Gen OC-192 JGEN Jitter Gen OC-48 JGEN IEEE 802.3 GbE RMS Jitter JGEN Min Typ Max GR-253 Spec Unit -- -- -- 0.483 0.302 0.467 0.628 0.392 0.607 psrms psrms psrms 167 Hz5 -- 0.470 0.611 111 Hz6 -- 0.565 0.734 N/A N/A 1.0 psrms (0.01 UIrms 4.02 psrms (0.01 UIrms) 4.02 psrms (0.01 UIrms) 83 Hz6 -- 0.232 0.301 Test Condition1,2,3,4 Measuremen DSPLL BW1 t Filter (MHz) 0.02-80 167 Hz5 4-80 167 Hz5 0.05-80 167 Hz5 0.012-20 1.875-20 psrms psrms psrms Notes: 1. BWSEL [1:0] loop bandwidth settings provided in Table 9 on page 20. 2. 40 MHz fundamental mode crystal used as XA/XB input. 3. VDD = 2.5 V 4. TA = 85 C 5. Si5315A test condition: fIN = 19.44 MHz, fOUT = 156.25 MHz, LVPECL clock input: 1.19 Vppd with 0.5 ns rise/fall time (20-80%), LVPECL clock output. 6. Si5315B test condition: fIN =19.44 MHz, fOUT = 125 MHz, LVPECL clock input: 1.19 Vppd with 0.5 ns rise/fall time (2080%), LVPECL clock output. V SIGNAL + Differential I/Os VICM , VOCM SIGNAL - VISE , VOSE (SIGNAL +) - (SIGNAL -) Differential Peak-to-Peak Voltage VID,VOD VICM, VOCM Single-Ended Peak-to-Peak Voltage t SIGNAL + VID = (SIGNAL+) - (SIGNAL-) SIGNAL - Figure 1. CKIN Voltage Characteristics 80% DOUT, CLOUT 20% tF tR Figure 2. Rise/Fall Time Characteristics 10 Rev. 1.0 Si5315 1.1. Three-Level (3L) Input Pins (No External Resistors) Si5315 VDD 75 k Iimm 75 k External Driver Figure 3. Three-Level Input Pins Table 5. Three-Level Input Pins (No External Resistors) Parameter Symbol Min Max Input Voltage Low Vill -- 0.15 x VDD Input Voltage Mid Vimm 0.45 x VDD 0.55 x VDD Input Voltage High Vihh 0.85 x VDD -- Input Low Current Iill -6 A -- Input Mid Current Iimm -2 A 2 A Input High Current Iihh -- 6 A Note: The above currents are the amount of leakage that the 3L inputs can tolerate from an external driver. Rev. 1.0 11 Si5315 1.2. Three-Level (3L) Input Pins (With External Resistors) V DD Iimm External Driver V DD Si5315 18 k 75 k 18 k 75 k One of eight resistors from a Panasonic EXB-D10C183J (or similar) resistor pack Figure 4. Three Level Input Pins Table 6. Three-Level Input Pins (With External Resistors) Parameter Symbol Min Max Input Low Current Iill -30 A -- Input Mid Current Iimm -11 A -11 A Input High Current Iihh -- -30 A Note: The above currents are the amount of leakage that the 3L inputs can tolerate from an external driver. Any resistor pack may be used. The Panasonic EXB-D10C183J is an example. layout is not critical. PCB Resistor packs are only needed if the leakage current of the external driver exceeds the listed currents. If a pin is tied to ground or VDD, no resistors are needed. 12 If a pin is left open (no connect), no resistors are needed. Rev. 1.0 Si5315 Table 7. Thermal Characteristics (VDD = 1.8 5%, 2.5 10%, or 3.3 V 10%, TA = -40 to 85 C) Symbol Test Condition Min Typ Max Unit Thermal Resistance Junction to Ambient JA Still Air -- 32 -- C/W Thermal Resistance Junction to Case JC Still Air -- 14 -- C/W Parameter Table 8. Absolute Maximum Limits Symbol Value Unit DC Supply Voltage VDD -0.5 to 3.8 V LVCMOS Input Voltage VDIG -0.3 to (VDD + 0.3) V CKINn Voltage Level Limits CKNVIN 0 to VDD V XA/XB Voltage Level Limits XAVIN 0 to 1.2 V Operating Junction Temperature TJCT -55 to 150 C Storage Temperature Range TSTG -55 to 150 C 2 kV ESD MM Tolerance; All pins except CKIN+/CKIN- 150 V ESD HBM Tolerance (100 pF, 1.5 k); CKIN+/CKIN- 750 V ESD MM Tolerance; CKIN+/CKIN- 100 V Parameter ESD HBM Tolerance (100 pF, 1.5 k); All pins except CKIN+/CKIN- Latch-Up Tolerance JESD78 Compliant Note: Permanent device damage may occur if the Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operation sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability. Rev. 1.0 13 Si5315 2. Typical Application Circuit C4 1 F System Power Supply C3 0.1 F Ferrite Bead C2 0.1 F VDD = 3.3 V CKIN1- 82 GND Pad CKIN1+ GND 130 VDD 130 C1 0.1 F 0.1 F CKOUT1+ + 100 CKOUT1- 82 - 0.1 F 0.1 F Clock Outputs to Ethernet PHYs CKOUT2+ Backplane or Line Recovered Clock Inputs + 100 VDD = 3.3 V CKOUT2- 130 - 0.1 F 130 CKIN2+ CKIN2- 82 82 Option 1: LOS1 CKIN1 Loss of Signal Indicator LOS2 CKIN2 Loss of Signal Indicator LOL XA PLL Loss of Lock Indicator 40 MHz Crystal XB Option 2: Si5315 0.1 F Ext. Refclk+ XA 0.1 F Ext. Refclk- XB VDD 15 k Crystal/Ref Clk VDD Manual/Automatic Clock 15 k Selection (L) XTAL/Clock2 15 k AUTOSEL2 VDD 15 k 15 k Input Clock Select CS3 VDD Frequency Table Select 15 k FRQTBL2 VDD 15 k 15 k Frequency Select FRQSEL[3:0]2 VDD Bandwidth Select 15 k 15 k 15 k BWSEL[1:0]2 VDD 15 k 15 k Signal Format Select SFOUT[1:0]2 VDD Clock Output 2 Disable/ 15 k Bypass Mode Control 15 k DBL2_BY2 15 k Reset RST Notes: 1. Assumes differential LVPECL termination (3.3 V) on clock inputs. 2. Denotes tri-level input pins with states designated as L (ground), M (VDD/2), and H (VDD). 3. Assumes manual input clock selection. Figure 5. Si5315 Typical Application Circuit 14 Rev. 1.0 Si5315 3. System Level Overview The Si5315 provides clock translation, jitter attenuation, and clock distribution for high-performance Synchronous Ethernet* line card timing applications. *Note: The Si5315 supports SyncE EEC options 1 and 2 when paired with a timing card that implements the required wander filtering and Stratum 3 compliant reference clock. For detailed information, refer to "AN420: SyncE and IEEE 1588: Sync Distribution for a Unified Network". The Si5315 provides clock translation, jitter attenuation, and clock distribution for high-performance Synchronous Ethernet line card timing applications. The device accepts two clock inputs ranging from 8 kHz to 644.53 MHz and generates two equal frequency, low jitter clock outputs ranging from 8 kHz to 644.53 MHz. For ease of use, the Si5315 is pin controlled to enable simple device configuration of frequency plans, PLL loop bandwidth, and input clock selection. The DSPLL locks to one of two input reference clocks and provides over 200 frequency translations to synchronize output clocks for Ethernet, SONET/SDH, and PDH line cards. The Si5315 implements internal state machines to control hitless switching between input clocks and holdover. Status alarms, loss of signal (LOS) and loss of lock (LOL) are provided on output pins to indicate a change in device status. This device is designed for systems with line cards that are synchronized to a redundant, centralized telecom or Ethernet backplane. The Si5315 synchronizes to backplane clocks and generates a multiplied, jitter attenuated Ethernet/SONET/SDH clock or PDH clock. A typical system application is shown in Figure 6. The Si5315 translates a 19.44 MHz clock from the telecom backplane to an Ethernet or SONET/SDH clock frequency to the PHY and filters the jitter to ensure compliance with related ITU-T and Telcordia standards. Telecom or Ethernet Backplane Redundant Timing Cards 10G LAN / WAN SyncE Line Card Tx Timing Path Wander Filtering Hitless Switching Holdover BITS A BITS B Hitless Switching Jitter Filtering Frequency Translation A Network Network Sync Synchronization PLL 10GbE PHY B A Si5315 B 8 kHz 19.44 MHz 25 MHz 155.52 MHz 156.25 MHz 161.1328125 MHz 10GbE PHY Rx Timing Path Line Recovered Clocks 8 kHz 19.44 MHz 25 MHz Line Recovered Timing Multi-Port SONET / SDH / PDH Line Card Tx Timing Path Hitless Switching Jitter Filtering Frequency Translation OC-3 / 12 77.76 / 155.52 MHz A Si5315 B 1.544 / 2.048 MHz T1 / E1 Rx Timing Path 8 kHz 19.44 MHz 25 MHz Line Recovered Clocks Figure 6. Typical Si5315 Application Rev. 1.0 15 Si5315 4. Functional Description Crystal or Reference Clock Xtal/Clock XA XB PLL Bypass 0 CKIN1+ CKIN1- 2 CKIN2+ CKIN2- 2 2 0 f3 DSPLL(R) fOSC 1 CKOUT1+ CKOUT1- SFOUT[1:0] 1 0 1 2 CKOUT2+ CKOUT2- LOS1 LOS2 LOL AUTOSEL DBL2_BY Signal Detect Control CS/CA RST BWSEL[1:0] FRQSEL[3:0] FRQTBL Bandwidth Control VDD (1.8, 2.5, or 3.3 V) Frequency Control GND Figure 7. Detailed Block Diagram 4.1. Overview The Si5315 is a jitter-attenuating precision clock multiplier for Synchronous Ethernet, SONET/SDH, and PDH (T1/E1) applications. The Si5315 accepts dual clock inputs ranging from 8 kHz to 644.53 MHz and generates two frequency-multiplied clock outputs ranging from 8 kHz to 644.53 MHz. The two input clocks are at the same frequency and the two output clocks are at the same frequency. The input clock frequency and clock multiplication ratio are selectable from a look up table of popular SyncE and T1/E1 rates. The Si5315 is based on Silicon Laboratories' 3rd-generation DSPLL(R) technology, which provides any-frequency synthesis and jitter attenuation in a highly integrated PLL solution that eliminates the need for external VCXO and loop filter components. The Si5315 PLL loop bandwidth is selectable via the BWSEL[1:0] pins and supports a range from 60 to 8.4 kHz. The Si5315 supports hitless switching between the two input clocks in compliance with ITU-T G.8262 and Telcordia GR-253-CORE and GR-1244-CORE. This feature greatly minimizes the propagation of phase transients to the clock outputs during an input clock transition (<200 ps typ). Manual and automatic revertive and non-revertive input clock switching options are available via the AUTOSEL input pin. The Si5315 monitors both input clocks for loss-ofsignal and provides a LOS alarm when it detects missing pulses on either input clock. The device monitors the lock status of the PLL. The lock detect algorithm works by continuously monitoring the phase of the input clock in relation to the phase of the feedback clock. The Si5315 provides a holdover capability that allows the device to continue generation of a stable output clock when the selected input reference is lost. The Si5315 has two differential clock outputs. The signal format of the clock outputs is programmable to support LVPECL, LVDS, CML, or CMOS loads. The second clock output can be powered down to minimize power consumption. For system-level debugging, a bypass mode is available which drives the output clock directly from the input clock, bypassing the internal DSPLL. The device operates from a single 1.8, 2.5, or 3.3 V supply. 16 Rev. 1.0 Si5315 4.2. PLL Performance The Si5315 provides extremely low jitter generation, a well-controlled jitter transfer function, and high jitter tolerance due to the high level of integration. 4.2.1. Jitter Generation Jitter generation is defined as the amount of jitter produced at the output of the device with a jitter free input clock. Generated jitter arises from sources within the VCO and other PLL components. Jitter generation is a function of the PLL bandwidth setting. Higher loop bandwidth settings may result in lower jitter generation, but may result in less attenuation of jitter that might be present on the input clock signal. 4.2.2. Jitter Transfer Jitter transfer is defined as the ratio of output signal jitter to input signal jitter for a specified jitter frequency. The jitter transfer characteristic determines the amount of input clock jitter that passes to the outputs. The DSPLL technology used in the Si5315 provides tightly controlled jitter transfer curves because the PLL gain parameters are determined largely by digital circuits which do not vary over supply voltage, process, and temperature. In a system application, a well-controlled transfer curve minimizes the output clock jitter variation from board to board and provides more consistent system level jitter performance. The jitter transfer characteristic is a function of the loop bandwidth setting. Lower bandwidth settings result in more jitter attenuation of the incoming clock, but may result in higher jitter generation. Figure 8 shows the jitter transfer curve mask. Jitter Transfer Jitter Out Jitter In 0 dB Peaking -20 dB/dec. BW fJitter Figure 8. PLL Jitter Transfer Mask/Template Rev. 1.0 17 Si5315 4.2.3. Jitter Tolerance Jitter tolerance is defined as the maximum peak-to-peak sinusoidal jitter that can be present on the incoming clock before the DSPLL loses lock. The tolerance is a function of the jitter frequency, because tolerance improves for lower input jitter frequency. The jitter tolerance of the DSPLL is a function of the loop bandwidth setting. Figure 9 shows the general shape of the jitter tolerance curve versus input jitter frequency. For jitter frequencies above the loop bandwidth, the tolerance is a constant value Aj0. Beginning at the PLL bandwidth, the tolerance increases at a rate of 20 dB/decade for lower input jitter frequencies. Input Jitter Amplitude -20 dB/dec. Excessive Input Jitter Range Aj0 BW/100 BW/10 BW fJitter In Figure 9. Jitter Tolerance Mask/Template The equation for the high frequency jitter tolerance can be expressed as a function of the PLL loop bandwidth (i.e., BW): 5000 A j0 = ------------- ns pk-pk BW For example, the jitter tolerance when fin = 19.44 MHz, fout = 161.13 MHz and the loop bandwidth (BW) is 113 Hz: 5000 A j0 = ------------- = 44.24 ns pk-pk 113 4.2.4. Jitter Attenuation Performance The Internal VCO uses the reference clock on the XA/XB pins as its reference for jitter attenuation. The XA/XB pins support either a crystal input or an input buffer single-ended or differential clock input, such that an external oscillator can become the reference source. In either case, the device accepts a wide margin in absolute frequency of the reference input. (See 5.5. "Holdover Mode" on page 32.) In holdover, the Si5315's output clock stability matches the reference supplied on the XA/XB pins. The external crystal or reference clock must be selected based on the stability requirements of the application if holdover is a key requirement. However, care must be exercised in certain areas for optimum performance. For examples of connections to the XA/XB pins, refer to 7. "Crystal/Reference Clock Input" on page 38. 18 Rev. 1.0 Si5315 5. Frequency Plan Tables For ease of use, the Si5315 is pin controlled to enable simple device configuration of the frequency plan and PLL loop bandwidth via a predefined look up table. The DSPLL has been optimized for each frequency multiplication and PLL loop bandwidth provided in Table 9 on page 20. Many of the control inputs are three levels: High, Low, and Medium. High and Low are standard voltage levels determined by the supply voltage: VDD and Ground. If the input pin is left floating, it is driven to nominally half of VDD. Effectively, this creates three logic levels for these controls. See 1.2. "Three-Level (3L) Input Pins (With External Resistors)" on page 12 and 8. "Power Supply Filtering" on page 41 for additional information. 5.1. Frequency Multiplication Plan The input to output clock multiplication is set by the 3-level FRQSEL[3:0] pins. The device provides a wide range of commonly used SyncE, SONET/SDH, and PDH frequency translations. The CKIN1 and CKIN2 inputs must be the same frequency as specified in Table 9. Both CKOUT1 and CKOUT2 outputs are at the same frequency. 5.1.1. PLL Loop Bandwidth Plan The Si5315's loop bandwidth ranges from 60 Hz to 8.4 kHz. For each frequency multiplication, its corresponding loop bandwidth is provided in a simple look up table. (See Table 9 on page 20.) The loop bandwidth (BW) is digitally programmable using the 3-level BWSEL [1:0] and FRQTBL input pins. Rev. 1.0 19 20 Rev. 1.0 0.008 0.008 0.008 0.008 0.008 0.008 0.008 0.008 0.008 0.008 0.008 0.008 0.008 0.008 0.008 0.008 0.008 1.544 1.544 1.544 1.544 1.544 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 19.44 8.192 2.048 1.544 0.008 622.08 312.5 311.04 156.25 155.52 125 77.76 65.536 51.84 44.736 38.88 34.368 32.768 25 19.44 8.192 2.048 1.544 L L L L L H H H H H M M M M M M M L L L L L L L FRQTBL LMLH LMLM LMLL LLHH LLHM LLMM LLML LLLH LLLM LLLL LLHL LLMH LLMM LLML LLLH LLLM LLLL LLHL LLMH LLMM LLML LLLH LLLM LLLL FRQSEL [3:0] 257 257 257 -- 257 257 257 257 257 257 257 257 257 257 257 257 257 257 257 257 257 257 257 257 LM 60 60 60 -- 60 60 60 60 60 60 60 60 -- 60 60 60 60 60 60 60 60 60 60 60 LH -- -- -- 6047 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- ML -- -- -- 1451 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- MM -- -- -- 359 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- MH -- -- -- 179 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- HL Loop Bandwidth Selection (Hz), BWSEL[1:0] Notes: 1. FIN and FOUT frequency values may be rounded off. For exact multiplication ratios, please contact Silicon Labs. 2. Si5315A supports all frequency plans. 3. Si5315B supports output frequency plans up to 125 MHz. 0.008 2 0.008 (MHz) (MHz) 0.008 fOUT fIN 1 Plan # Table 9. Look Up Tables for Clock Multiplication and Loop Bandwidth Settings -- -- -- 89 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- HH Si5315 Rev. 1.0 1.544 1.544 1.544 1.544 1.544 1.544 1.544 1.544 1.544 1.544 1.544 1.544 2.048 2.048 2.048 2.048 2.048 2.048 2.048 2.048 2.048 2.048 2.048 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 51.84 44.736 38.88 34.368 32.768 25 19.44 8.192 2.048 1.544 0.008 622.08 312.5 311.04 156.25 155.52 125 77.76 65.536 51.84 44.736 38.88 34.368 32.768 M M M M L L L L L L L H H H H H M M M M M M M L L FRQTBL LMHH LMHM LMHL LMMH LHLH LHLM LHLL LMHH LMHM LMHL LMMH LMLL LLHH LLHM LLHL LLMH LMMM LMML LMLH LMLM LMLL LLHH LLHM LMMM LMML FRQSEL [3:0] -- -- -- -- -- 2087 -- -- -- 1037 2089 257 257 257 257 257 257 257 257 257 257 257 257 257 257 LM -- 3983 -- 8163 -- 485 -- -- -- 242 485 60 60 60 60 60 60 60 -- 60 60 60 60 60 60 LH 3946 1944 3946 3935 3947 240 3946 3949 3949 119 240 -- -- -- -- -- -- -- -- -- -- -- -- -- -- ML 958 477 958 958 959 -- 958 959 959 -- 59 -- -- -- -- -- -- -- -- -- -- -- -- -- -- MM 59 118 238 118 118 118 -- 118 118 118 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- HL 118 238 238 238 -- 238 238 238 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- MH Loop Bandwidth Selection (Hz), BWSEL[1:0] Notes: 1. FIN and FOUT frequency values may be rounded off. For exact multiplication ratios, please contact Silicon Labs. 2. Si5315A supports all frequency plans. 3. Si5315B supports output frequency plans up to 125 MHz. 1.544 26 25 (MHz) (MHz) 1.544 fOUT fIN 25 Plan # Table 9. Look Up Tables for Clock Multiplication and Loop Bandwidth Settings (Continued) 59 -- 59 -- 59 -- 59 59 59 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- HH Si5315 21 22 Rev. 1.0 2.048 2.048 2.048 2.048 2.048 2.048 8.192 8.192 8.192 8.192 8.192 8.192 8.192 8.192 8.192 8.192 8.192 8.192 8.192 8.192 19.44 19.44 19.44 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 2.048 1.544 0.008 125 77.76 65.536 51.84 44.736 38.88 34.368 32.768 25 19.44 8.192 2.048 1.544 0.008 622.08 312.5 311.04 156.25 155.52 125 77.76 L L L M M M M M M M L L L L L L L H H H H H M M M FRQTBL MLML MLLH MLLM MLLL LHHH LHHM LHHL LHMH LHMM LHML MLLL LHHH LHHM LHHL LHMH LHMM LHML LMMH LMMM LMML LMLH LMLM LHLH LHLM LHLL FRQSEL [3:0] -- -- 1759 1037 -- -- -- -- -- -- -- 2087 -- -- -- 1037 2089 -- 1037 -- 1037 -- 1037 -- -- LM 3348 2779 409 242 -- -- -- 3983 -- 8163 -- 485 -- -- -- 242 485 -- 242 -- 242 -- 242 -- 8185 LH 1638 1362 202 119 3946 6411 3946 1944 3946 3935 6431 240 3946 6434 6434 119 240 3946 119 3946 119 3946 119 3946 3940 ML 402 335 -- -- 958 1539 958 477 958 958 1541 -- 958 1541 1541 -- 59 958 -- 958 -- 958 -- 958 958 MM -- -- 100 -- -- 118 190 118 59 118 118 190 -- 118 190 190 -- -- 118 -- 118 -- 118 -- 118 118 HL 83 -- -- 238 381 238 118 238 238 381 -- 238 381 381 -- -- 238 -- 238 -- 238 -- 238 238 MH Loop Bandwidth Selection (Hz), BWSEL[1:0] Notes: 1. FIN and FOUT frequency values may be rounded off. For exact multiplication ratios, please contact Silicon Labs. 2. Si5315A supports all frequency plans. 3. Si5315B supports output frequency plans up to 125 MHz. 2.048 51 65.536 (MHz) (MHz) 2.048 fOUT fIN 50 Plan # Table 9. Look Up Tables for Clock Multiplication and Loop Bandwidth Settings (Continued) -- -- -- -- 59 95 59 -- 59 -- 95 -- 59 95 95 -- -- 59 -- 59 -- 59 -- 59 -- HH Si5315 Rev. 1.0 19.44 19.44 19.44 19.44 19.44 19.44 19.44 19.44 19.44 19.44 19.44 19.44 19.44 19.44 19.44 19.44 25 25 25 25 25 25 25 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 32.768 25 19.44 8.192 2.048 1.544 0.008 644.5313 622.08 312.5 311.04 161.1328 156.25 155.52 125 77.76 65.536 51.84 44.736 38.88 34.368 32.768 25 19.44 L L L L L L L H H H H H H H M M M M M M M L L L L FRQTBL MMMH MMMM MMML MMLH MMLM MMLL MLHH LHML LHLH LHLM LHLL LMHH LMHM LMHL MLHM MLHL MLMH MLMM MLML MLLH MLLM MLHM MLHL MLMH MLMM FRQSEL [3:0] 6737 -- -- 6737 1299 6741 -- 103 -- 6003 -- 484 6003 -- 3960 -- 2618 -- -- -- -- -- -- -- -- LM 1529 -- -- 1529 303 1529 -- -- -- 1373 -- 113 1373 -- 913 -- 607 -- 5653 -- 5662 -- 2778 -- 3348 LH 753 7615 6551 753 150 753 7045 -- 7696 677 7696 -- 677 7696 450 7696 300 7696 2747 7703 2749 5022 1362 7706 1638 ML 186 1812 1568 186 -- 186 1681 -- 1832 167 1832 -- 167 1832 111 1832 74 1832 672 1832 672 1215 335 1832 402 MM 223 -- -- 193 -- -- -- 207 -- 225 -- 225 -- -- 225 -- 225 -- 225 83 225 83 150 -- 225 -- HL 447 387 -- -- -- 415 -- 452 -- 452 -- -- 452 -- 452 -- 452 167 452 167 301 83 452 100 MH Loop Bandwidth Selection (Hz), BWSEL[1:0] Notes: 1. FIN and FOUT frequency values may be rounded off. For exact multiplication ratios, please contact Silicon Labs. 2. Si5315A supports all frequency plans. 3. Si5315B supports output frequency plans up to 125 MHz. 19.44 76 8.192 (MHz) (MHz) 19.44 fOUT fIN 75 Plan # Table 9. Look Up Tables for Clock Multiplication and Loop Bandwidth Settings (Continued) -- 111 96 -- -- -- 103 -- 112 -- 112 -- -- 112 -- 112 -- 112 -- 112 -- 75 -- 112 -- HH Si5315 23 24 Rev. 1.0 25 25 25 25 25 25 25 25 25 25 25 25 25 32.768 32.768 32.768 32.768 32.768 32.768 32.768 32.768 32.768 32.768 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 44.736 38.88 34.368 32.768 25 19.44 8.192 2.048 1.544 0.008 644.5313 622.08 312.5 311.04 161.1328 156.25 155.52 125 77.76 65.536 51.84 50 44.736 38.88 M M M L L L L L L L H H H H H H H M M M M H M M M FRQTBL MMHH MMHM MMHL MHML MHLH MHLM MHLL MMHH MMHM MMHL MLLM MLLL LHHH LHHM LHHL LHMH LHMM MMMH MMMM MMML MMLH HMLH MMLM MMLL MLHH FRQSEL [3:0] -- -- -- -- 2087 -- -- -- 1037 2089 -- 1298 -- 1298 -- -- 1298 -- 6706 1298 -- -- 1298 6729 6722 LM 3983 -- 8163 -- 485 -- -- -- 242 485 -- 303 -- 303 -- -- 303 -- 1528 303 7988 -- 303 1529 1528 LH 1944 -- 3935 7632 240 3946 7632 7187 119 240 6106 150 7606 150 6106 7606 150 7606 753 150 3846 7880 150 753 753 ML 477 958 958 1816 -- 958 1816 1714 -- 59 1468 -- 1811 -- 1468 1811 -- 1811 186 -- 936 1880 -- 186 186 MM 118 59 118 118 223 -- 118 223 211 -- -- 181 -- 223 -- 181 223 -- 223 -- -- 116 230 -- -- -- HL 238 238 448 -- 238 448 423 -- -- 363 -- 447 -- 363 447 -- 447 -- -- 232 470 -- -- -- MH Loop Bandwidth Selection (Hz), BWSEL[1:0] Notes: 1. FIN and FOUT frequency values may be rounded off. For exact multiplication ratios, please contact Silicon Labs. 2. Si5315A supports all frequency plans. 3. Si5315B supports output frequency plans up to 125 MHz. 25 101 34.368 (MHz) (MHz) 25 fOUT fIN 100 Plan # Table 9. Look Up Tables for Clock Multiplication and Loop Bandwidth Settings (Continued) -- 59 -- 111 -- 59 111 105 -- -- 90 -- 111 -- 90 111 -- 111 -- -- -- 120 -- -- -- HH Si5315 Rev. 1.0 32.768 32.768 50 50 77.76 77.76 77.76 77.76 77.76 77.76 77.76 77.76 77.76 77.76 77.76 77.76 77.76 77.76 77.76 77.76 77.76 77.76 77.76 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 644.5313 622.08 312.5 311.04 161.1328 156.25 155.52 125 77.76 65.536 51.84 44.736 38.88 34.368 25 19.44 2.048 1.544 0.008 50 25 125 77.76 65.536 H H H H H H H M M M M M M M L L L L L M L M M M M FRQTBL MLHH MLHM MLHL MLMH MLMM MLML MLLH HLLM HLLL MHHH MHHM MHHL MHMH MHMM MHHH MHHM MHHL MHMH MHMM HMLH HHHH MHML MHLH MHLM MHLL FRQSEL [3:0] 484 -- 6003 -- 484 6003 -- 5336 -- -- -- -- -- -- -- -- -- -- 2089 -- -- 1037 -- -- -- LM 113 -- 1373 -- 113 1373 -- 1220 -- 2461 -- -- -- -- 2778 -- -- 2779 485 -- -- 242 -- -- -- LH -- 7905 677 7905 -- 677 7905 602 7905 1208 7905 6756 7905 6798 1362 7905 6804 1362 240 7770 7880 119 3946 7604 3946 ML -- 1879 167 1879 -- 167 1879 148 1879 298 1879 1623 1879 1626 335 1879 1626 335 59 1850 1880 -- 958 1815 958 MM 231 -- -- -- 231 -- -- 231 -- 231 -- 231 200 231 200 -- 231 200 -- -- 230 230 -- 118 223 118 HL 464 -- 464 -- -- 464 -- 464 74 464 402 464 402 83 464 402 83 -- 466 470 -- 238 448 238 MH Loop Bandwidth Selection (Hz), BWSEL[1:0] Notes: 1. FIN and FOUT frequency values may be rounded off. For exact multiplication ratios, please contact Silicon Labs. 2. Si5315A supports all frequency plans. 3. Si5315B supports output frequency plans up to 125 MHz. 32.768 126 51.84 (MHz) (MHz) 32.768 fOUT fIN 125 Plan # Table 9. Look Up Tables for Clock Multiplication and Loop Bandwidth Settings (Continued) -- 115 -- 115 -- -- 115 -- 115 -- 115 100 115 100 -- 115 100 -- -- 110 120 -- 59 111 59 HH Si5315 25 26 Rev. 1.0 125 125 125 125 125 125 125 125 125 125 125 125 125 125 125 125 125 155.52 155.52 155.52 155.52 155.52 155.52 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 77.76 25 19.44 2.048 1.544 0.008 644.5313 622.08 312.5 311.04 161.1328 156.25 155.52 125 77.76 65.536 51.84 44.736 38.88 34.368 25 19.44 2.048 1.544 H L L L L L H H H H H H H M M M M M M M L L L L L FRQTBL MMHM HMLL HLHH HLHM HLHL HLMH MMHL MMMH MMMM MMML MMLH MMLM MMLL HLHH HLHM HLHL HLMH HLMM HLML HLLH HLMM HLML HLLH HLLM HLLL FRQSEL [3:0] -- -- -- -- -- 2089 -- 1298 -- 1298 -- -- 1298 -- 6706 1298 -- 1298 6729 6722 -- -- 1299 6741 -- LM -- 2778 -- -- 2779 485 -- 303 -- 303 -- -- 303 -- 1528 303 7988 303 1529 1528 -- -- 303 1529 -- LH 7905 1362 7905 7606 1362 240 7718 150 7862 150 7718 7862 150 7862 753 150 3846 150 753 753 7862 6551 150 753 7045 ML 1879 335 1879 1809 335 59 1839 -- 1870 -- 1839 1870 -- 1870 186 -- 936 -- 186 186 1870 1568 -- 186 1681 MM -- 231 464 231 223 -- -- 226 -- 230 -- 226 230 -- 230 -- -- 116 -- -- -- 230 193 -- -- 207 HL 83 464 447 83 -- 454 -- 462 -- 454 462 -- 462 -- -- 232 -- -- -- 462 387 -- -- 415 MH Loop Bandwidth Selection (Hz), BWSEL[1:0] Notes: 1. FIN and FOUT frequency values may be rounded off. For exact multiplication ratios, please contact Silicon Labs. 2. Si5315A supports all frequency plans. 3. Si5315B supports output frequency plans up to 125 MHz. 125 151 0.008 (MHz) (MHz) 125 fOUT fIN 150 Plan # Table 9. Look Up Tables for Clock Multiplication and Loop Bandwidth Settings (Continued) 115 -- 115 111 -- -- 113 -- 115 -- 113 115 -- 115 -- -- -- -- -- -- 115 96 -- -- 103 HH Si5315 Rev. 1.0 155.52 155.52 155.52 155.52 155.52 155.52 156.25 156.25 156.25 156.25 156.25 156.25 156.25 156.25 156.25 156.25 156.25 156.25 156.25 156.25 161.1328 161.1328 161.1328 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 2.048 1.544 0.008 644.5313 622.08 312.5 311.04 161.1328 156.25 155.52 125 77.76 25 19.44 2.048 1.544 0.008 644.5313 622.08 312.5 311.04 161.1328 156.25 155.52 L L L H H H H H H H H H L L L L L H H H H H H H H FRQTBL HMHH HMHM HMHL HLHL HLMH HLMM HLML HLLH HLLM HLLL MHHH MHHM HMMH HMMM HMML HMLH HMLM MHHL MHMH MHMM MHML MHLH MHLM MHLL MMHH FRQSEL [3:0] 225 151 225 -- 322 -- 322 -- -- 322 -- 1625 -- -- 322 1627 -- 828 -- 6003 -- 484 6003 -- 5336 LM -- -- -- -- 75 -- 75 -- -- 75 -- 379 -- -- 75 379 -- 193 -- 1373 -- 113 1373 -- 1220 LH -- -- -- 7718 -- 7835 -- 7718 7835 -- 7835 187 7835 4852 -- 187 6123 95 7905 677 7905 -- 677 7905 602 ML -- -- -- 1839 -- 1864 -- 1839 1864 -- 1864 -- 1864 1172 -- -- 1469 -- 1879 167 1879 -- 167 1879 148 MM -- -- -- -- 226 -- 229 -- 226 229 -- 229 -- 229 145 -- -- 181 -- 231 -- 231 -- -- 231 -- HL -- -- 454 -- 460 -- 454 460 -- 460 -- 460 290 -- -- 363 -- 464 -- 464 -- -- 464 -- MH Loop Bandwidth Selection (Hz), BWSEL[1:0] Notes: 1. FIN and FOUT frequency values may be rounded off. For exact multiplication ratios, please contact Silicon Labs. 2. Si5315A supports all frequency plans. 3. Si5315B supports output frequency plans up to 125 MHz. 155.52 176 125 (MHz) (MHz) 155.52 fOUT fIN 175 Plan # Table 9. Look Up Tables for Clock Multiplication and Loop Bandwidth Settings (Continued) -- -- -- 113 -- 114 -- 113 114 -- 114 -- 114 72 -- -- 90 -- 115 -- 115 -- -- 115 -- HH Si5315 27 28 161.1328 161.1328 161.1328 161.1328 161.1328 161.1328 161.1328 644.5313 644.5313 644.5313 644.5313 644.5313 644.5313 644.5313 644.5313 644.5313 644.5313 644.5313 161.1328 644.5313 644.5313 644.5313 644.5313 644.5313 202 203 204 205 206 207 208 209 210 211 212 213 214 Rev. 1.0 215 216 217 218 219 220 221 H H H H H H H H H L L L L L H H H H H H L L FRQTBL HHMM HHML HHLH HHLM HHLL HMHH HMHM HMHL HMMH HHHL HHMH HHMM HHML HHLH HMMM HMML HMLM HMLL HLHH HLHM HHLM HHLL FRQSEL [3:0] -- 120 206 828 -- -- 828 -- 828 -- -- -- 413 880 151 3873 332 -- -- 678 678 679 LM -- -- -- 193 -- -- 193 -- 193 -- 3641 3373 96 206 -- 892 78 -- -- 159 159 159 LH 7895 -- -- 95 7895 7732 95 7732 95 7886 1779 1650 -- 101 -- 440 -- 7019 7179 78 78 78 ML 1880 -- -- -- 1880 1840 -- 1840 -- 1875 437 405 -- -- -- 109 -- 1683 1721 -- -- -- MM -- 231 464 -- -- 231 226 -- 226 -- 231 -- -- -- -- -- -- -- 207 212 -- -- -- HL -- -- -- 464 454 -- 454 -- 463 108 101 -- -- -- -- -- 416 426 -- -- -- MH Loop Bandwidth Selection (Hz), BWSEL[1:0] Notes: 1. FIN and FOUT frequency values may be rounded off. For exact multiplication ratios, please contact Silicon Labs. 2. Si5315A supports all frequency plans. 3. Si5315B supports output frequency plans up to 125 MHz. 622.08 312.5 311.04 156.25 155.52 125 77.76 25 19.44 2.048 1.544 0.008 312.5 156.25 125 77.76 25 161.1328 201 19.44 (MHz) (MHz) 161.1328 fOUT fIN 200 Plan # Table 9. Look Up Tables for Clock Multiplication and Loop Bandwidth Settings (Continued) 115 -- -- -- 115 113 -- 113 -- 115 -- -- -- -- -- -- -- 103 106 -- -- -- HH Si5315 Si5315 5.2. PLL Self-Calibration An internal self-calibration (ICAL) is performed before operation to optimize loop parameters and jitter performance. While the self-calibration is being performed, the DSPLL is being internally controlled by the selfcalibration state machine. The LOL alarm will be active during ICAL. The self-calibration time tLOCKHW is given in Table 3, "AC Characteristics". Any of the following events will trigger a self-calibration: Power-on-reset (POR) Release of the external reset pin RST (transition of RST from 0 to 1) Change in FRQSEL, FRQTBL, BWSEL, or XTAL/CLOCK pins Internal DSPLL registers out-of-range, indicating the need to relock the DSPLL In any of the above cases, an internal self-calibration will be initiated if a valid input clock exists (no input alarm) and is selected as the active clock at that time. The external crystal or reference clock must also be present for the self-calibration to begin. If valid clocks are not present, the self-calibration state machine will wait until they appear, at which time the calibration will start. An output clock will be active while waiting for a valid input clock. The output clock frequency is based on the VCO range determine by FRQSEL and FRQTBL settings. This output clock will vary by 20%. If no output clock is desired prior to an ICAL, then the SFOUT pins should be kept at LM for 1.2 seconds until the output clock is stable. After a successful self-calibration has been performed with a valid input clock, no subsequent self calibrations are performed unless one of the above conditions are met. If the input clock is lost following self-calibration, the device enters holdover mode. When the input clock returns, the device relocks to the input clock without performing a selfcalibration. 5.2.1. Input Clock Stability during Internal Self-Calibration An exit from reset must occur when the selected CKINn clock is stable in frequency with a frequency value that is within the device operating range. The other CKINs must also either be stable in frequency or squelched during a reset. 5.2.2. Self-Calibration caused by Changes in Input Frequency If the selected CKINn varies by 500 ppm or more in frequency since the last calibration, the device may initiate a self-calibration. 5.2.3. Device Reset Upon powerup, the device internally executes a power-on-reset (POR) which resets the internal device logic. The pin RST can also be used to initiate a reset. The device stays in this state until a valid CKINn is present, when it then performs a PLL Self-Calibration (See 5.2. "PLL Self-Calibration"). 5.2.4. Recommended Reset Guidelines Follow the recommended RESET guidelines in Table 10 when reset should be applied to a device. Table 10. Si5315 Pins and Reset Pin # Si5315 Pin Name Must Reset after Changing 2 FRQTBL Yes 11 XTAL/CLOCK Yes 22 BWSEL0 Yes 23 BWSEL1 Yes 24 FRQSEL0 Yes 25 FRQSEL1 Yes 26 FRQSEL2 Yes 27 FRQSEL3 Yes Rev. 1.0 29 Si5315 5.2.5. Hitless Switching with Phase Build-Out Silicon Laboratories switching technology performs "phase build-out" to minimize the propagation of phase transients to the clock outputs during input clock switching. All switching between input clocks occurs within the input multiplexor and phase detector circuitry. The phase detector circuitry continually monitors the phase difference between each input clock and the DSPLL output clock, fOSC. The phase detector circuitry can lock to a clock signal at a specified phase offset relative to fOSC so that the phase offset is maintained by the PLL circuitry. At the time a clock switch occurs, the phase detector circuitry knows both the input-to-output phase relationship for the original input clock and for the new input clock. The phase detector circuitry locks to the new input clock at the new clock's phase offset so that the phase of the output clock is not disturbed. The phase difference between the two input clocks is absorbed in the phase detector's offset value, rather than being propagated to the clock output. The switching technology virtually eliminates the output clock phase transients traditionally associated with clock rearrangement (input clock switching). The Maximum Time Interval Error (MTIE) and maximum slope for clock output phase transients during clock switching are given in (Table 3, "AC Characteristics"). These values fall significantly below the limits specified in the ITU-T G.8262, Telcordia GR-1244-CORE, and GR-253-CORE requirements. 5.3. Input Clock Control This section describes the clock selection capabilities (manual input selection, automatic input selection, hitless switching, and revertive switching). When switching between two clocks, LOL may temporarily go high if the two clocks differ in frequency by more than 100 ppm. 5.3.1. Manual Clock Selection Manual control of input clock selection is chosen via the CS_CA pin according to Table 11 and Table 12. Table 11. Automatic/Manual Clock Selection AUTOSEL Clock Selection Mode L Manual M Automatic non-revertive H Automatic revertive Table 12. Manual Input Clock Selection, AUTOSEL = L CS_CA Si5315 AUTOSEL = L 0 CKIN1 1 CKIN2 5.3.2. Automatic Clock Selection The AUTOSEL input pin sets the input clock selection mode as shown in Table 11. Automatic switching is either revertive or non-revertive. Setting AUTOSEL to M or H, changes the CS_CA pin to an output pin that indicates the state of the automatic clock selection. Table 13. Clock Active Indicators, AUTOSEL = M or H 30 CS_CA Active Clock 0 CKIN1 1 CKIN2 Rev. 1.0 Si5315 The prioritization of clock inputs for automatic switching is shown in Table 14. This priority is hardwired in the devices. Table 14. Input Clock Priority for Auto Switching Priority Input Clocks 1 CKIN1 2 CKIN2 3 Holdover At power-on or reset, the valid CKINn with the highest priority (1 being the highest priority) is automatically selected. If no valid CKINn is available, the device suppresses the output clocks and waits for a valid CKINn signal. If the currently selected CKINn goes into an alarm state, the next valid CKINn in priority order is selected. If no valid CKINn is available, the device enters holdover. Operation in revertive and non- revertive is different when a signal becomes valid: Revertive (AUTOSEL = H): The device constantly monitors all CKINn. If a CKINn with a higher priority than the current active CKINn becomes valid, the active CKINn is changed to the CKINn with the highest priority. Non-revertive (AUTOSEL = M): The active clock does not change until there is an alarm on the active clock. The device will then select the highest priority CKINn that is valid. Once in holdover, the device will switch to the first CKINn that becomes valid. 5.4. Alarms Summary alarms are available to indicate the overall status of the input signals. Alarm outputs stay high until all the alarm conditions for that alarm output are cleared. 5.4.1. Loss-of-Signal The device has loss-of-signal circuitry that continuously monitors CKINn for missing pulses. The LOS circuitry generates an internal LOSn_INT output signal that is processed with other alarms to generate LOS1 and LOS2. An LOS condition on CKIN1 causes the internal LOS1_INT alarm to become active. Similarly, an LOS condition on CKINn causes the LOSn_INT alarm to become active. Once a LOSn_INT alarm is asserted on one of the input clocks, it remains asserted until that input clock is validated over a designated time period. The time to clear LOSn_INT after a valid input clock appears is listed in Table 3, "AC Characteristics". If another error condition on the same input clock is detected during the validation time then the alarm remains asserted and the validation time starts over. 5.4.1.1. LOS Algorithm The LOS circuitry divides down each input clock to produce an 8 kHz to 2 MHz signal. The LOS circuitry over samples this divided down input clock using a 40 MHz clock to search for extended periods of time without input clock transitions. If the LOS monitor detects twice the normal number of samples without a clock edge, a LOSn_INT alarm is declared. Table 3, "AC Characteristics" gives the minimum and maximum amount of time for the LOS monitor to trigger. 5.4.1.2. Lock Detect The PLL lock detection algorithm indicates the lock status on the LOL output pin. The algorithm works by continuously monitoring the phase of the input clock in relation to the phase of the feedback clock. If the time between two consecutive phase cycle slips is greater than the retrigger time, the PLL is in lock. The LOL output has a guaranteed minimum pulse width as shown in (Table 3, "AC Characteristics"). The LOL pin is also held in the active state during an internal PLL calibration. The retrigger time is automatically set based on the PLL closed loop bandwidth (See Table 15). Rev. 1.0 31 Si5315 Table 15. Lock Detect Retrigger Time PLL Bandwidth Setting (BW) Retrigger Time (ms) 60-120 Hz 53 120-240 Hz 26.5 240-480 Hz 13.3 480-960 Hz 6.6 960-1920 Hz 3.3 1920-3840 Hz 1.66 3840-7680 Hz 0.833 5.5. Holdover Mode If an LOS condition exists on the selected input clock, the device enters holdover. In this mode, the device provides a stable output frequency until the input clock returns and is validated. When the device enters holdover, the internal oscillator is initially held to its last frequency value. Next, the internal oscillator slowly transitions to a historical average frequency value that was taken over a time window of 6,711 ms in size that ended 26 ms before the device entered holdover. This frequency value is taken from an internal memory location that keeps a record of previous DSPLL frequency values. By using a historical average frequency, input clock phase and frequency transients that may occur immediately preceding loss of clock or any event causing holdover do not affect the holdover frequency. Also, noise related to input clock jitter or internal PLL jitter is minimized. If a highly stable reference, such as an oven-controlled crystal oscillator, is supplied at XA/XB, an extremely stable holdover can be achieved. If a crystal is supplied at the XA/XB port, the holdover stability will be limited by the stability of the crystal; Table 3, "AC Characteristics" gives the specifications related to the holdover function. 5.5.1. Recovery from Holdover When the input clock signal returns, the device transitions from holdover to the selected input clock. The device performs hitless recovery from holdover. The clock transition from holdover to the returned input clock includes "phase buildout" to absorb the phase difference between the holdover clock phase and the input clock phase. See Table 3, "AC Characteristics" for specifications. 5.6. PLL Bypass Mode The Si5315 supports a PLL bypass mode in which the selected input clock is fed directly to both enabled output buffers, bypassing the DSPLL. Internally, the bypass path is implemented with high-speed differential signaling; however, this path is not a low jitter path and will see significantly higher jitter on CKOUT. In PLL bypass mode, the input and output clocks will be at the same frequency. PLL bypass mode is useful in a laboratory environment to measure system performance with and without the jitter attenuation provided by the DSPLL. The DSBL2_BY pin is used to select the PLL Bypass Mode according to Table 16. Bypass mode is not supported for CMOS clock outputs (SFOUT = LH). Table 16. DSBL2/BYPASS Pin Settings 32 DSBL2/BYPASS Function L CKOUT2 Enabled M CKOUT2 Disabled H PLL Bypass Mode w/ CKOUT2 Enabled Rev. 1.0 Si5315 Crystal or Reference Clock Xtal/Clock XA XB PLL Bypass 0 CKIN1+ CKIN1- 2 2 0 f3 CKIN2+ CKIN2- 2 DSPLL(R) fOSC 1 CKOUT1+ CKOUT1- SFOUT[1:0] 1 0 1 2 CKOUT2+ CKOUT2- LOS1 LOS2 LOL AUTOSEL CS/CA DBL2_BY Signal Detect Control RST BWSEL[1:0] FRQSEL[3:0] FRQTBL Bandwidth Control VDD (1.8, 2.5, or 3.3 V) Frequency Control GND Figure 10. Bypass Signal Rev. 1.0 33 Si5315 6. High-Speed I/O 6.1. Input Clock Buffers The Si5315 provides differential inputs for the CKINn clock inputs. These inputs are internally biased to a common mode voltage [see Table 2, "DC Characteristics"] and can be driven by either a single-ended or differential source. Figure 11 through Figure 14 show typical interface circuits for LVPECL, CML, LVDS, or CMOS input clocks. Note that the jitter generation improves for higher levels on CKINn (within the limits in Table 3, "AC Characteristics"). AC coupling the input clocks is recommended because it removes any issue with common mode input voltages. However, either ac or dc coupling is acceptable. Figures 11 and 12 show various examples of different input termination arrangements. Unused inputs can be left unconnected. 3.3 V Si5315 130 130 C CKIN + 40 k LVPECL Driver 300 40 k CKIN 82 82 VICM _ C Figure 11. Differential LVPECL Termination 3.3 V Si5315 130 C CKIN + Driver 40 k 300 40 k CKIN _ 82 C Figure 12. Single-ended LVPECL Termination 34 Rev. 1.0 VICM Si5315 Si5315 C CKIN + CML/ LVDS Driver 40 k 300 100 40 k VICM CKIN _ C Figure 13. CML/LVDS Termination (1.8, 2.5, 3.3 V) CMOS Driver V DD V DD V DD Si5315 R3 50 R1 R2 150 ohms C1 CKIN+ See Table 33 ohms R4 150 ohms VDD R2 Notes 3.3 V 2.5 V 1.8 V 100 ohm 49.9 ohm 14.7 ohm Locate R1 near CMOS driver Locate other components near Si5317 Recalculate resistor values for other drive strengths V ICM R5 40 kohm 100 nF CKIN- C2 100 nF R6 40 kohm Additional Notes: 1. Attenuation circuit limits overshoot and undershoot. 2. Not to be used with non-square wave input clocks. Figure 14. CMOS Termination (1.8, 2.5, 3.3 V) Rev. 1.0 35 Si5315 6.2. Output Clock Drivers The Si5315 has a flexible output driver structure that can drive a variety of loads, including LVPECL, LVDS, CML, and CMOS formats. The signal format is selected for both CKOUT1 and CKOUT2 outputs using the SFOUT [1:0] pins. This modifies the output common mode and differential signal swing. See Table 2, "DC Characteristics" for output driver specifications. The SFOUT [1:0] pins are three-level input pins, with the states designated as L (ground), M (VDD/2), and H (VDD). Table 17 shows the signal formats based on the supply voltage and the type of load being driven. Table 17. Output Signal Format Selection (SFOUT) Si5315 SFOUT[1:0] Signal Format HL CML HM LVDS LH CMOS LM Disabled MH LVPECL ML Low-swing LVDS All Others Reserved Z0 = 50 100 CKOUTn Z0 = 50 Rcvr Figure 15. Typical Differential Output Circuit Si5315 CMOS Logic CKOUTn Optionally Tie CKOUTn Outputs Together for Greater Strength Figure 16. Typical CMOS Output Circuit (Tie CKOUTn+ and CKOUTn- Together) For the CMOS setting (SFOUT = LH), both output pins drive single-ended in-phase signals. The CKOUT+/- can be externally shorted together for greater drive strength specified in Table 2, "DC Characteristics". 36 Rev. 1.0 Si5315 + SFOUT[1:0] = LM (Output Disable) 100 100 CKOUTn Output from DSPLL Figure 17. Disable CKOUTn Structure The SFOUT [1:0] pins can also be used to disable both outputs. Disabling the output puts the CKOUTn+ and CKOUTn- pins in a high-impedance state relative to VDD (common mode tri-state) while the two outputs remain connected to each other through a 200 on-chip resistance (differential impedance of 200 ). The maximum amount of internal circuitry is powered down, minimizing power consumption and noise generation. Recovery from the disable mode requires additional time as specified in Table 3, "AC Characteristics". Rev. 1.0 37 Si5315 7. Crystal/Reference Clock Input The device can use an external crystal or external clock as a reference. If an external clock is used, it must be ac coupled. With appropriate buffers, the same external reference clock can be applied to CKINn. Although the reference clock input can be driven single ended (See Figure 18), the best performance is with a crystal or low jitter, differential clock source. No external loading capacitors are required for normal crystal operation. 3.3 V 150 3.3 V 130 CMOS buffer, 8 mA output current 0.1 F 150 Si5315 XA 10 k 0.6 V XB 0.1 F For 2.5 V operation, change 130 to 82 . Figure 18. CMOS External Reference Circuit 0 dBm into 50 0.01 F 0.01 F External Clock Source 50 1.2 V Si5315 XA XB 10 pF 10 k 0.6 V 0.1 F Figure 19. Sinewave External Reference Clock Input Example 0.01 F Si5315 1.2 V XA 100 LVPECL, CML, etc. 0.01 F XB 10 k 10 k 0.6 V Figure 20. Differential External Reference Clock Input Example 38 Rev. 1.0 Si5315 7.1. Crystal/Reference Clock Selection The Si5315 requires either a low-jitter external oscillator or a low-cost fundamental mode crystal to be connected to its XA/XB pins. This serves both as a jitter reference for jitter attenuation and as a reference oscillator for stability during holdover. The frequency the reference is not directly related to either the input or the output clock frequencies. The range of the reference frequency is from 37 to 41 MHz. For recommendations on the selection of the reference frequency and a list of approved crystals, see the application note AN591 which can be downloaded from www.silabs.com/timing/. In holdover, the DSPLL remains locked to this external reference. Any changes in the frequency of this reference when the DSPLL is in holdover will be tracked by the output of the device. Note that crystals can have temperature sensitivities. Table 18 shows how the XTAL/CLOCK pin is used to select between a crystal and an external oscillator. Table 18. XA/XB Reference Sources XTAL/CLOCK Type M 37-41 MHz external clock L 40 MHz crystal Because the crystal is used as a jitter reference, rapid changes of the crystal temperature can temporarily disturb the output phase and frequency. For example, it is recommended that the crystal not be placed close to a fan that is being turned off and on. If a situation such as this is unavoidable, the crystal should be thermally isolated with an insulating cover. 7.1.1. Reference Drift During holdover, long-term and temperature related drift of the reference input result in a one-to-one drift of the output frequency. That is, the stability of the any-frequency output is identical to the drift of the reference frequency. This means that for the most demanding applications where the drift of a crystal is not acceptable, an external temperature compensated or ovenized oscillator will be required. Drift is not an issue unless the part is in holdover. Also, the initial accuracy of the reference oscillator (or crystal) is not relevant. Rev. 1.0 39 Si5315 7.1.2. Reference Jitter Jitter on the reference input has a roughly one-to-one transfer function to the output jitter over the bandwidth ranging from 100 Hz up to 30 kHz. If a crystal is used on the XA/XB pins, the reference will have low jitter if a suitable crystal is in use. If the XA/XB pins are connected to an external reference oscillator, the jitter of the external reference oscillator may contribute significantly to the output jitter. A typical reference input-to-output jitter transfer function is shown in Figure 21. Jitter Transfer XA/XB Reference to CKOUT 38.88 MHz XO, 38.88 MHz CKIN, 38.88 MHz CKOUT 5 0 Jitter Transfer (dB) -5 -10 -15 -20 -25 -30 1 10 100 1000 10000 100000 Jitter Frequency (Hz) Figure 21. Typical XA/XB Reference Jitter Transfer Function 40 Rev. 1.0 1000000 Si5315 8. Power Supply Filtering This device incorporates an on-chip voltage regulator with excellent PSRR to power the device from a supply voltage of 1.8, 2.5, or 3.3 V. The device requires minimal supply decoupling and no stringent layout or ground plane islands. Internal core circuitry is driven from the output of this regulator while I/O circuitry uses the external supply voltage directly. Table 3, "AC Characteristics" gives the sensitivity of the on-chip oscillator to changes in the supply voltage. Refer to the Si5315 evaluation board for an example. The center ground pad under the device must be electrically and thermally connected to the ground plane. See Figure 26, "Ground Pad Recommended Layout," on page 50. System Power Supply (1.8, 2.5, or 3.3 V) 0.1 uF C1 - C3 Ferrite Bead 1.0 uF C4 VDD GND & GND Pad Si5315 Figure 22. Typical Power Supply Bypass Network Power Supply Noise to Output Transfer Function -60 Power Supply Noise Rejection Ratio (dB) -65 -70 -75 -80 -85 -90 -95 -100 -105 1 10 100 Frequency of Power Supply Noise (kHz) 1000 Figure 23. Fout = 155 MHz with 112 Hz Loop Bandwidth, 100 mVp-p Supply Noise Rev. 1.0 41 Si5315 9. Typical Phase Noise Plots The following is a typical phase noise plot. The clock input source was a Rohde and Schwarz model SML03 RF Generator. The spectrum analyzer was either an Agilent model E5052B, model E4400A or model JS-500. The Si5315 operates at 3.3 V with an ac coupled differential PECL output and an ac coupled differential sine wave input from the RF generator at 0 dBm. Note that, as with any PLL, the output jitter that is below the loop BW is caused by the jitter at the input clock, not the Si5315. Except as noted, loop BWs of 60 to 240 Hz were in use. 9.1. 10G LAN SyncE Example Si5315TypicalPhaseNoise 0 20 40 Fin=19.44MHz; Fout=125MHz; BW=111Hz 60 Fin=19.44MHz Fout=156.25MHz BW=167Hz 80 100 Fin=25MHz Fout=125MHz BW=111Hz 120 Fin=25MHz Fout=156.25MHz BW=111Hz 140 160 180 100 1,000 10,000 100,000 1,000,000 10,000,000 100,000,000 Frequency Plan Fin=25 MHz Fin=25 MHz Fin=19.44 MHz Fin=19.44 MHz Fout=156.25 MHz Fout=125 MHz Fout=156.25 MHz Fout=125 MHz BW=111 Hz BW=111 Hz BW=111 Hz BW=167 Hz RMS Jitter (fs) Jitter Integration Filter Band IEEE802.3 (1.875 to 20 MHz) 232 240 251 240 SONET OC-192 (20 kHz to 80 MHz) 483 575 525 550 SONET OC-192 (4 to 80 MHz) 302 303 300 294 SONET OC-192 (50 kHz to 80 MHz) 467 564 510 537 SONET OC-48 (12 kHz to 20 MHz) 470 565 517 541 SONET OC-3 (12 kHz to 5 MHz) 422 524 471 503 BroadBand (800 Hz to 80 MHz) 511 584 533 557 42 Rev. 1.0 Si5315 CKOUT1- CKOUT1+ SFOUT1 GND SFOUT0 VDD CKOUT2- CKOUT2+ NC 10. Pin Descriptions: Si5315 36 35 34 33 32 31 30 29 28 RST 1 27 FRQSEL3 FRQTBL 2 26 FRQSEL2 LOS1 3 25 FRQSEL1 LOS2 4 XA 6 XB 24 FRQSEL0 GND Pad VDD 5 23 BWSEL1 22 BWSEL0 7 21 CS_CA GND 8 20 GND AUTOSEL 9 19 GND LOL CKIN1- GND CKIN1+ DBL2_BY CKIN2- CKIN2+ VDD XTAL/CLOCK 10 11 12 13 14 15 16 17 18 Pin assignments are preliminary and subject to change. Table 19. Si5315 Pin Descriptions Pin # 1 Pin Name RST I/O I Signal Level LVCMOS 2 FRQTBL I 3-Level 3 LOS1 O LVCMOS 4 LOS2 O LVCMOS Description External Reset. Active low input that performs external hardware reset of device. Resets all internal logic to a known state. Clock outputs are tristated during reset. After rising edge of RST signal, the Si5315 will perform an internal self-calibration when a valid input signal is present. This pin has a weak pull-up. Frequency Table Select. Selects frequency table. (Table 9 on page 20.) This pin has a weak pull-up and weak pull-down and defaults to M. Some designs may require an external resistor voltage divider when driven by an active device that will tri-state. CKIN1 Loss of Signal. Active high loss-of-signal indicator for CKIN1. Once triggered, the alarm will remain active until CKIN1 is validated. 0 = CKIN1 present 1 = LOS on CKIN1 CKIN2 Loss of Signal. Active high loss-of-signal indicator for CKIN2. Once triggered, the alarm will remain active until CKIN2 is validated. 0 = CKIN2 present 1 = LOS on CKIN2 Rev. 1.0 43 Si5315 Table 19. Si5315 Pin Descriptions (Continued) Pin # 5, 10, 32 Pin Name VDD I/O VDD Signal Level Supply 7 6 XB XA I Analog 8, 15,19, 20,31 GND GND Supply 9 AUTOSEL I 3-Level 11 XTAL/CLOCK I 3-Level 12 13 CKIN2+ CKIN2- I 44 Description Supply. The device operates from a 1.8, 2.5, or 3.3 V supply. Bypass capacitors should be associated with the following VDD pins: 5 0.1 F 10 0.1 F 32 0.1 F A 1.0 F should also be placed as close to device as is practical. External Crystal or Reference Clock. External crystal should be connected to these pins to use internal oscillator based reference. Crystal or reference clock selection is set by the XTAL/CLOCK pin. Ground. Must be connected to system ground. Minimize the ground path impedance for optimal performance of this device. Manual/Automatic Clock Selection. Three level input that selects the method of input clock selection to be used. L = Manual M = Automatic non-revertive H = Automatic revertive This pin has a weak pull-up and weak pull-down and defaults to M. Some designs may require an external resistor voltage divider when driven by an active device that will tri-state. External Crystal or Reference Clock Rate. Three level input that selects the type and rate of external crystal or reference clock to be applied to the XA/XB port. This pin has both a weak pull-up and a weak pull-down and defaults to M. L = Crystal M = Clock (Default) H = Reserved Some designs may require an external resistor voltage divider when driven by an active device that will tri-state. Clock Input 2. Differential input clock. This input can also be driven with a single-ended signal. Input frequency selected from a table of values. The same frequency must be applied to CKIN1 and CKIN2. Rev. 1.0 Si5315 Table 19. Si5315 Pin Descriptions (Continued) Pin # 14 Pin Name DBL2_BY I/O I Signal Level 3-Level 16 17 CKIN1+ CKIN1- I Multi 18 LOL O LVCMOS 21 CS_CA I/O LVCMOS 23 22 BWSEL1 BWSEL0 I 3-Level Description Output 2 Disable/Bypass Mode Control. Controls enable of CKOUT2 divider/output buffer path and PLL bypass mode. L = CKOUT2 enabled M = CKOUT2 disabled H = Bypass mode with CKOUT2 enabled. Bypass mode is not supported with CMOS clock outputs (SFOUT = LH). This pin has a weak pull-up and weak pull-down and defaults to M. Some designs may require an external resistor voltage divider when driven by an active device that will tri-state. Clock Input 1. Differential input clock. This input can also be driven with a single-ended signal. Input frequency selected from a table of values. The same frequency must be applied to CKIN1 and CKIN2. PLL Loss of Lock Indicator. This pin functions as the active high PLL loss of lock indicator. 0 = PLL locked 1 = PLL unlocked Input Clock Select/Active Clock Indicator. Input: If manual clock selection mode is chosen (AUTOSEL = L), this pin functions as the manual input clock selector. This input is internally deglitched to prevent inadvertent clock switching during changes in the CS input state. 0 = Select CKIN1 1 = Select CKIN2 If configured as input, must be set high or low. Output: If automatic clock selection mode is chosen (AUTOSEL = M or H), this pin indicates which of the two input clocks is currently the active clock. If alarms exist on both CKIN1 and CKIN2, indicating that the holdover state has been entered, CA will indicate the last active clock that was used before entering the hold state. 0 = CKIN1 active input clock 1 = CKIN2 active input clock Loop Bandwidth Select. Three level inputs that select the DSPLL closed loop bandwidth. See Table 9 on page 20 for available settings. These pins have both weak pull-ups and weak pull-downs and default to M. Some designs may require an external resistor voltage divider when driven by an active device that will tri-state. Rev. 1.0 45 Si5315 Table 19. Si5315 Pin Descriptions (Continued) Pin # 27 26 25 24 Pin Name FRQSEL3 FRQSEL2 FRQSEL1 FRQSEL0 I/O I Signal Level 3-Level 29 28 CKOUT1- CKOUT1+ O Multi 33 30 SFOUT0 SFOUT1 I 3-Level Description Frequency Select. Three level inputs that select the input clock and clock multiplication ratio, depending on the FRQTBL setting. These pins have both weak pull-ups and weak pull-downs and default to M. Some designs may require an external resistor voltage divider when driven by an active device that will tri-state. Clock Output 1. Differential output clock with a frequency selected from a table of values. Output signal format is selected by SFOUT pins. Output is differential for LVPECL, LVDS, and CML compatible modes. For CMOS format, both output pins drive identical single-ended clock outputs. Signal Format Select. Three level inputs that select the output signal format (common mode voltage and differential swing) for both CKOUT1 and CKOUT2. SFOUT[1:0] 34 35 CKOUT2- CKOUT2+ O Multi 36 NC -- -- GND PAD GND GND Supply 46 Signal Format HH Reserved HM LVDS HL CML MH LVPECL MM Reserved ML LVDS--Low Swing LH CMOS LM Disable LL Reserved These pins have both weak pull-ups and weak pull-downs and default to M. Some designs may require an external resistor voltage divider when driven by an active device that will tri-state. Clock Output 2. Differential output clock with a frequency selected from a table of values. Output signal format is selected by SFOUT pins. Output is differential for LVPECL, LVDS, and CML compatible modes. For CMOS format, both output pins drive identical single-ended clock outputs. No Connect. Leave floating. Make no external connections to this pin for normal operation. Ground Pad. The ground pad must provide a low thermal and electrical impedance to a ground plane. Rev. 1.0 Si5315 Table 20. Si5315 Pull-Up/Pull-Down Pin # Si5315 Pull 1 RST U 2 FRQTBL U, D 9 AUTOSEL U, D 11 XTAL/ CLOCK U, D 14 DBL2_BY U, D 21 CS_CA U, D 22 BWSEL0 U, D 23 BWSEL1 U, D 24 FRQSEL0 U, D 25 FRQSEL1 U, D 26 FRQSEL2 U, D 27 FRQSEL3 U, D 30 SFOUT1 U, D 33 SFOUT0 U, D Rev. 1.0 47 Si5315 11. Ordering Guide Ordering Part Number Output Clock Freq Range Pkg ROHS6, Pb-Free Temp Range Si5315A-C-GM 8 kHz-644.53 MHz 36-Lead 6x6 mm QFN Yes -40 to 85 C Si5315B-C-GM 8 kHz-125 MHz 36-Lead 6x6 mm QFN Yes -40 to 85 C Si5315-EVB 8 kHz-644.53 MHz Evaluation Board Note: Add an "R" at the end of the device to denote tape and reel options (i.e., Si5315A-C-GMR). 48 Rev. 1.0 Si5315 12. Package Outline: 36-Pin QFN Figure 24 illustrates the package details for the Si5315. Table 21 lists the values for the dimensions shown in the illustration. Figure 24. 36-Pin Quad Flat No-Lead (QFN) Table 21. Package Dimensions Symbol Millimeters Symbol Min Nom Max A 0.80 0.85 0.90 A1 0.00 0.02 b 0.18 0.25 D D2 e Nom Max L 0.50 0.60 0.70 0.05 -- -- 12 0.30 aaa -- -- 0.10 bbb -- -- 0.10 4.10 ccc -- -- 0.08 ddd -- -- 0.10 eee -- -- 0.05 4.25 0.50 BSC E E2 Min 6.00 BSC 3.95 6.00 BSC 3.95 4.10 Millimeters 4.25 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to JEDEC outline MO-220, variation VJJD. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. Rev. 1.0 49 Si5315 13. PCB Land Pattern Figure 25 illustrates the PCB land pattern for the Si5315. Figure 26 illustrates the recommended ground pad layout. Table 22 lists the land pattern dimensions. Figure 25. PCB Land Pattern Figure 26. Ground Pad Recommended Layout 50 Rev. 1.0 Si5315 Table 22. PCB Land Pattern Dimensions Dimension Min Max e 0.50 BSC. E 5.42 REF. D 5.42 REF. E2 4.00 4.20 D2 4.00 4.20 GE 4.53 -- GD 4.53 -- X -- 0.28 Y 0.89 REF. ZE -- 6.31 ZD -- 6.31 Notes (General): 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification. 3. This Land Pattern Design is based on IPC-SM-782 guidelines. 4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm. Notes (Solder Mask Design): 1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. Notes (Stencil Design): 1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 2. The stencil thickness should be 0.125 mm (5 mils). 3. The ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads. 4. A 4 x 4 array of 0.80 mm square openings on 1.05 mm pitch should be used for the center ground pad. Notes (Card Assembly): 1. A No-Clean, Type-3 solder paste is recommended. 2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. Rev. 1.0 51 Si5315 14. Top Marking 14.1. Si5315 Top Marking (QFN) 14.2. Top Marking Explanation Mark Method: Laser Font Size: 0.80 mm Right-Justified Line 1 Marking: Si5315Q Customer Part Number Q = Speed Code: A, B See Ordering Guide for options. Line 2 Marking: C-GM C = Product Revision G = Temperature Range -40 to 85 C (RoHS6) M = QFN Package Line 3 Marking: YYWWRF YY = Year WW = Work Week R = Die Revision F = Internal code Assigned by the Assembly House. Corresponds to the year and work week of the mold date. Line 4 Marking: Pin 1 Identifier Circle = 0.75 mm Diameter Lower-Left Justified XXXX Internal Code 52 Rev. 1.0 Si5315 DOCUMENT CHANGE LIST Revision 0.1 to Revision 0.2 Expanded/added numerous operating sections to initial data sheet Revision 0.2 to Revision 0.25 Updated features and application list Updated Section 1. "Electrical Specifications" Added voltage regulator block to Figure 7 Revised footnotes in Table 9 Removed plan #203 from Table 9 Removed Figure 17. Crystal Oscillator with Feedback Resistor diagram from Section 7. "Crystal/Reference Clock Input" Added XA/XB jitter transfer plot to Section 7. "Crystal/Reference Clock Input" Added PSRR transfer function plot to Section 8. "Power Supply Filtering" Updated Typical phase noise plot and RMS jitter table in Section 9. "Typical Phase Noise Plots" Revision 0.25 to Revision 0.26 Corrected Section 11. "Ordering Guide" Output Clock Frequency Range for Si5315B-C-GM to 8 kHz-125 MHz. Revision 0.26 to Revision 1.0 Updated Table 2 on page 4. Updated Table 3 on page 8. Updated Table 7 on page 13. Moved "Typical Application Circuit" to page 14. Added reference to AN591. Bypass mode not supported with CMOS outputs. Changed G.8262 compliance language. Added frequency plans 103, 129, and 130. Rev. 1.0 53 ClockBuilder Pro One-click access to Timing tools, documentation, software, source code libraries & more. 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