18288 BUS CONTROLLER FOR iAPX 86, 88 PROCESSORS INDUSTRIAL a Bipolar Drive Capability a Configurable for Use with an I/O Bus a Provides Advanced Commands a Facilitates Interface to One or Two Multi-Master Busses a Provides Wide Flexibility in System a Configurations a= Industrial Temperature Range: 40C to 85C a 3-State Command Output Drivers The Intel 18288 Bus Controller is a 20-pin bipolar component for use with medium-to-large iAPX 86 processing systems. The bus controller provides command and control timing generation as well.as bipolar bus drive capability while optimizing system performance. A strapping option on the bus controller configures it for use with a multi-master.system bus and separate I/O bus. vos (41 2017] Vee cik [42 19 [3 So si(}3 18) $2 oA C4 170 MceiPOEN ALE L]5 16 |) DEN _ AEN (6 18 TI CEN 08s { = status MRDC Mane L] 7 14 [7 INTA status} 24 DECODER com: (7 MS Amwe [8 13 7 ioR 82 *}4 MANO AMWC | muttiBus mwre C19 AIOWG SIGNAL Tore + COMMAND mwrTc (f 127] Alowc GENER. . | SIGNALS 40 _. ATOR iowc GND 1} iowe ALOWC r : iNtA Figure 2. Pin Configuration GND Vcc DT/R is CONTROL ADORESS LATCH, DATA CONTROL } AEN CONTROL [} SIGNAL DEN TRANSCEIVER, AND INPUT ) CEN Logic || GENER. MCEIPDEN ( INTERRUPT CONTROL '0 ATOR ALE SIGNALS | 50 Alow > Prone fai rae | >| So iOwc F> COMMAND +5V SND MWTC TF 7 Bus MADE b> faceg OR nm Figure 1. Block Diagram ~| AEN iNTA -> CONTROL } 7] CLK INPUT toB oT b> CEN ALE E> | CONTROL MCEIPDEN | ( OUTPUT DEN F> Figure 3, Functional Pin-Out 9-103 intel 18288 ABSOLUTE MAXIMUM RATINGS* Temperature Under Bias ............... ~40C to B5C Storage Temperature ............... ~65C to +150C All Output and Supply Voltages ......... -0.5V to +7V All Input Voltages ..............00 0c eae ~1.0V to 5.5V Power Dissipation .......... ccc cee eee eee 1.5 Watt *NOTICE: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional opera- tion of the device at these or any other conditions above those indicated in the operation sections of this specifica- tion is not implied. Exposure to absolute maximum ratin- ing conditions for extended periods may affect device reliability. D.C. CHARACTERISTICS (Vcc = 5V +10%, Ta = 40C to 85C) Symbol Parameter Min. Max. Unit Test Conditions Vc tnput Clamp Voltage -1 Vv Io = -5 mA lec Power Supply Current 230 mA lr Forward Input Current -0.7 mA Ve = 0.45V In Reverse Input Current 50 pA Va =Voc Output Low Voltage , VoL Command Outputs 0.5 v lol = 20 mA Control Outputs 0.5 Vv Io = 16MA Output High Voltage Vou Command Outputs 2.4 Vv lon = ~5 mA Control Outputs 2.4 v loH = 1mA VIL Input Low Voltage 0.8 Vv Vin Input High Voltage 2.0 Vv loFF Output Off Current 100 BA VorF = 0.4 to 5.25V A.C. CHARACTERISTICS (Vcc = 5V +10%, Ta = 40C to 85C) TIMING REQUIREMENTS Symbol Parameter Min. Max. Unit Test Conditions TCLCL CLK Cycle Period 125 ns TCLCH CLK Low Time 66 ns TCHCL CLK High Time 40 ns TSVCH Status Active Setup Time 35 ns TCHSV Status Active Hold Time 10 ns TSHCL Status Inactive Setup Time 35 ns TCLSH Status Inactive Hold Time 10 ns TILIH Input Rise Time 20 ns From 0.8V to 2.0V TIHIL Input Fall Time 12 ns From 2.0V to 0.8V 9-104 AFN-01400A, o intel 18288 A.C. CHARACTERISTICS (Continued) TIMING RESPONSES Symbol! Parameter Min. Max. Unit Test Conditions TCVNV Control Active Delay 5 45 ns TCVNX Control Inactive Delay 10 50 ns TCLLH, ALE MCE Active Delay (from CLK) 25 ns TCLMCH TSVLH, ALE MCE Active Delay (from Status) 25 ns MRDC TSVMCH IORC : MWTC lo. = 20 mA TCHLL ALE Inactive Delay 4 15 ns IOWC lon = +5 mA TCLML Command Active Delay 10 35 ns INTA C_ = 300 pF TCLMH Command Inactive Delay 10 35 ns AMWC AIOWC TCHDTL Direction Control Active Delay 50 ns TCHDTH Direction Control Inactive Delay 30 ns TAELCH Command Enable Time 40 ns TAEHCZ Command Disable Time 40 ns lot = 16 mA : Other lon = 1 mA TAELCV Enable Delay Time 115 200 ns C. = 80 pF TAEVNV AEN to DEN 20 ns TCEVNV CEN to DEN, PDEN 25 ns TCELRH CEN to Command TCLML ns TOLOH Output Rise Time 20 ns From 0.8V to 2.0V TOHOL Output Fall Time 12 ns From 2.0V to 0.8V A.C. TESTING INPUT, OUTPUT WAVEFORM (INPUT/OUTPUT 2.4 1.5 ~t TEST POINTS 1.5 0.45 AC. TESTING: INPUTS ARE DRIVEN AT 2.4V FOR A LOGIC "1" AND 0.45V FOR A LOGIC "0." TIMING MEASUREMENTS ARE MADE AT 1.5V FOR BOTH A LOGIC "1" AND 0. TEST LOAD CIRCUITS 3-STATE COMMAND OUTPUT TEST LOAD out 1802 32 OUT T 300 pF T pF 3-STATE TO HIGH 3-STATE TO LOW 2.01V 1 pF COMMAND OUTPUT TEST LOAD 2.28V 1149 Out 80 pF CONTROL OUTPUT TEST LOAD 9-105 AFN-01400A I 18288 WAVEFORMS STATE Ta 1 - Tg 7 ne T3- +|+-_T4 oux { Vo wy NX 1 TCHSV} + TSVCH |= TCHCL+ -- TSHCL|+ TCLSH 5.5% xX K # AgDR ADDRESS/DATA . WRITE x VALID x DATA VALID 1) TCLLH et ke TCHLL >| SVLH 2 | TOLMER +{ -TCLML | TCLML MWTC, iOWC + TCVNV ee (READ) (INTA) TCVNX+| BOEN(READ) POEN Ta) Vf TCVNV* | DEN (WRITE) | - TCVNX | POEN (WRITE} i KO | | | TCHDTH> i DT/R (READ) | (NTA) | 7 | -TCHOTL \ ! MCE @ TCHDTH | TCVNX TCLMCH*) _! te TSVMCH 1. ADDAESS/DATA BUS IS SHOWN ONLY FOR REFERENCE PURPOSES. 2. LEADING EDGE OF ALE AND MCE IS DETERMINED BY THE FALLING EDGE OF CLK OR STATUS GOING ACTIVE, WHICHEVER OCCURS LAST. 3. ALL TIMING MEASUREMENTS ARE MADE AT 1.5V UNLESS SPECIFIED OTHERWISE. 9-106 AFN-01400A intel 18288 WAVEFORMS (Continued) DEN, PDEN QUALIFICATION TIMING . x AEN TAEVNV+| DEN h--- TCEVNV. . POEN ADDRESS ENABLE (AEN) TIMING (3-STATE ENABLE/DISABLE) 4 ----TAELCV -. - ~~ AEN 1.5V [TAEHCZ y e 0.5V OH \ Vou OUTPUT XN + COMMAND ~-TCELRH+| CEN TCELRH NOTE: CEN must be low or valid prior to T2 to prevent the command from being generated. 9-107 AFN-01400A