74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output
latches; 3-state
Rev. 10 — 29 April 2021 Product data sheet
1. General description
The 74HC595; 74HCT595 is an 8-bit serial-in/serial or parallel-out shift register with a storage
register and 3-state outputs. Both the shift and storage register have separate clocks. The device
features a serial input (DS) and a serial output (Q7S) to enable cascading and an asynchronous
reset MR input. A LOW on MR will reset the shift register. Data is shifted on the LOW-to-HIGH
transitions of the SHCP input. The data in the shift register is transferred to the storage register
on a LOW-to-HIGH transition of the STCP input. If both clocks are connected together, the shift
register will always be one clock pulse ahead of the storage register. Data in the storage register
appears at the output whenever the output enable input (OE) is LOW. A HIGH on OE causes the
outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the
state of the registers. Inputs include clamp diodes. This enables the use of current limiting resistors
to interface inputs to voltages in excess of VCC.
2. Features and benefits
8-bit serial input
8-bit serial or parallel output
Storage register with 3-state outputs
Shift register with direct clear
100 MHz (typical) shift out frequency
Complies with JEDEC standard no. 7A
Input levels:
For 74HC595: CMOS level
For 74HCT595: TTL level
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
3. Applications
Serial-to-parallel data conversion
Remote control holding register
Nexperia 74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
4. Ordering information
Table 1. Ordering information
PackageType number
Temperature range Name Description Version
74HC595D
74HCT595D
-40 °C to +125 °C SO16 plastic small outline package; 16 leads;
body width 3.9 mm
SOT109-1
74HC595DB
74HCT595DB
-40 °C to +125 °C SSOP16 plastic shrink small outline package; 16 leads;
body width 5.3 mm
SOT338-1
74HC595PW
74HCT595PW
-40 °C to +125 °C TSSOP16 plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
SOT403-1
74HC595BQ
74HCT595BQ
-40 °C to +125 °C DHVQFN16 plastic dual in-line compatible thermal enhanced
very thin quad flat package; no leads; 16 terminals;
body 2.5 × 3.5 × 0.85 mm
SOT763-1
74HC595BZ -40 °C to +125 °C DHXQFN16 plastic, leadless dual in-line compatible thermal
enhanced extreme thin quad flat package;
no leads; 16 terminals; 0.4 mm pitch;
body 2 mm × 2.4 mm × 0.48 mm
SOT8016-1
5. Functional diagram
mna554
3-STATE OUTPUTS
8-BIT STORAGE REGISTER
8-STAGE SHIFT REGISTER
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
Q7S
14
15 1 2 3 4 5 6 7
9
DS
SHCP
STCP
OE
11
10
12
13
MR
Fig. 1. Functional diagram
OEMR
9
15
1
2
3
4
5
6
7
1310
14
11 12
mna552
Q1
Q0
Q2
Q3
Q4
Q5
Q6
Q7
Q7S
DS
STCP
SHCP
Fig. 2. Logic symbol
mna553
15
9
1
2
3
4
5
6
7
1D 2D
C1/
10
11
14
C2
12
13 EN3
SRG8
R
3
Fig. 3. IEC logic symbol
74HC_HCT595 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2021. All rights reserved
Product data sheet Rev. 10 — 29 April 2021 2 / 22
Nexperia 74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
STAGE 0 STAGES 1 TO 6 STAGE 7
FF0
D
CP
Q
R
LATCH
D
CP
Q
FF7
D
CP
Q
R
LATCH
D
CP
Q
mna555
D Q
Q1 Q2 Q3 Q4 Q5 Q6 Q7
Q7S
Q0
DS
STCP
SHCP
OE
MR
Fig. 4. Logic diagram
6. Pinning information
6.1. Pinning
74HC595
74HCT595
Q1 VCC
Q2 Q0
Q3 DS
Q4 OE
Q5 STCP
Q6 SHCP
Q7 MR
GND Q7S
001aao242
1
2
3
4
5
6
7
8
10
9
12
11
14
13
16
15
Fig. 5. Pin configuration for SOT109-1 (SO16),
SOT338-1 (SSOP16) and SOT403-1 (TSSOP16)
001aao243
74HC595
74HCT595
Q7 MR
Q6 SHCP
Q5 STCP
Q4 OE
Q3 DS
Q2 Q0
GND
Q7S
Q
1
V
C
C
Transparent top view
7 10
6 11
5 12
4 13
3 14
2 15
8
9
1
16
terminal 1
index area
GND(1)
(1) This is not a ground pin. There is no electrical or
mechanical requirement to solder the pad. In case
soldered, the solder land should remain floating or
connected to GND.
Fig. 6. Pin configuration for SOT763-1 (DHVQFN16)
74HC_HCT595 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2021. All rights reserved
Product data sheet Rev. 10 — 29 April 2021 3 / 22
Nexperia 74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
74HC595
aaa-032839
Transparent top view
GND(1)
Q2 2
GND 8
V
C
C
1
6
terminal 1
index area
Q7S 9
Q
1
1
Q3 DS
3 14
Q5 5
Q6 6
Q7 7
Q0
15
STCP
12
Q4 4OE
13
SHCP
11
MR
10
(1) This is not a ground pin. There is no electrical or mechanical requirement to solder the pad. In case soldered,
the solder land should remain floating or connected to GND.
Fig. 7. Pin configuration SOT8016-1 (DHXQFN16)
6.2. Pin description
Table 2. Pin description
Symbol Pin Description
Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7 15, 1, 2, 3, 4, 5, 6, 7 parallel data output
GND 8 ground (0 V)
Q7S 9 serial data output
MR 10 master reset (active LOW)
SHCP 11 shift register clock input
STCP 12 storage register clock input
OE 13 output enable input (active LOW)
DS 14 serial data input
Q0 15 parallel data output 0
VCC 16 supply voltage
74HC_HCT595 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2021. All rights reserved
Product data sheet Rev. 10 — 29 April 2021 4 / 22
Nexperia 74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
7. Functional description
Table 3. Function table
H = HIGH voltage state; L = LOW voltage state; ↑ = LOW-to-HIGH transition;
X = don’t care; NC = no change; Z = high-impedance OFF-state.
Control Input Output
SHCP STCP OE MR DS Q7S Qn
Function
X X L L X L NC a LOW-level on MR only affects the shift registers
X L L X L L empty shift register loaded into storage register
X X H L X L Z shift register clear; parallel outputs in high-impedance OFF-state
X L H H Q6S NC logic HIGH-level shifted into shift register stage 0. Contents of all
shift register stages shifted through, e.g. previous state of stage 6
(internal Q6S) appears on the serial output (Q7S).
X L H X NC QnS contents of shift register stages (internal QnS) are transferred to the
storage register and parallel output stages
L H X Q6S QnS contents of shift register shifted through; previous contents of the
shift register is transferred to the storage register and the parallel
output stages
SHCP
DS
STCP
MR
OE
Q0
Q1
Q6
Q7
Q7S
Z-state
Z-state
Z-state
Z-state
mna556
Fig. 8. Timing diagram
74HC_HCT595 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2021. All rights reserved
Product data sheet Rev. 10 — 29 April 2021 5 / 22
Nexperia 74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
8. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage -0.5 +7 V
IIK input clamping current VI < -0.5 V or VI > VCC + 0.5 V - ±20 mA
IOK output clamping current VO < -0.5 V or VO > VCC + 0.5 V - ±20 mA
VO = -0.5 V to (VCC + 0.5 V)
pin Q7S - ±25 mA
IOoutput current
pins Qn - ±35 mA
ICC supply current - 70 mA
IGND ground current -70 - mA
Tstg storage temperature -65 +150 °C
SOT109-1; SOT338-1;
SOT403-1; SOT763-1
[1] - 500 mWPtot total power dissipation
SOT8016-1 - 250 mW
[1] For SOT109-1 (SO16) package: Ptot derates linearly with 12.4 mW/K above 110 °C.
For SOT338-1 (SSOP16) package: Ptot derates linearly with 8.5 mW/K above 91 °C.
For SOT403-1 (TSSOP16) package: Ptot derates linearly with 8.5 mW/K above 91 °C.
For SOT763-1 (DHVQFN16) package: Ptot derates linearly with 11.2 mW/K above 106 °C.
9. Recommended operating conditions
Table 5. Recommended operating conditions
74HC595 74HCT595Symbol Parameter Conditions
Min Typ Max Min Typ Max
Unit
VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V
VIinput voltage 0 - VCC 0 - VCC V
VOoutput voltage 0 - VCC 0 - VCC V
VCC = 2.0 V - - 625 - - - ns/V
VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V
Δt/ΔV input transition rise and fall
rate
VCC = 6.0 V - - 83 - - - ns/V
Tamb ambient temperature -40 +25 +125 -40 +25 +125 °C
74HC_HCT595 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2021. All rights reserved
Product data sheet Rev. 10 — 29 April 2021 6 / 22
Nexperia 74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
10. Static characteristics
Table 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
-40 °C to +85 °C -40 °C to +125 °CSymbol Parameter Conditions
Min Typ Max Min Max
Unit
74HC595
VCC = 2.0 V 1.5 1.2 - 1.5 - V
VCC = 4.5 V 3.15 2.4 - 3.15 - V
VIH HIGH-level
input voltage
VCC = 6.0 V 4.2 3.2 - 4.2 - V
VCC = 2.0 V - 0.8 0.5 - 0.5 V
VCC = 4.5 V - 2.1 1.35 - 1.35 V
VIL LOW-level
input voltage
VCC = 6.0 V - 2.8 1.8 - 1.8 V
VI = VIH or VIL
all outputs
IO = -20 μA; VCC = 2.0 V 1.9 2.0 - 1.9 - V
IO = -20 μA; VCC = 4.5 V 4.4 4.5 - 4.4 - V
IO = -20 μA; VCC = 6.0 V 5.9 6.0 - 5.9 - V
Q7S output
IO = -4 mA; VCC = 4.5 V 3.84 4.32 - 3.7 - V
IO = -5.2 mA; VCC = 6.0 V 5.34 5.81 - 5.2 - V
Qn bus driver outputs
IO = -6 mA; VCC = 4.5 V 3.84 4.32 - 3.7 - V
VOH HIGH-level
output voltage
IO = -7.8 mA; VCC = 6.0 V 5.34 5.81 - 5.2 - V
VI = VIH or VIL
all outputs
IO = 20 μA; VCC = 2.0 V - 0 0.1 - 0.1 V
IO = 20 μA; VCC = 4.5 V - 0 0.1 - 0.1 V
IO = 20 μA; VCC = 6.0 V - 0 0.1 - 0.1 V
Q7S output
IO = 4 mA; VCC = 4.5 V - 0.15 0.33 - 0.4 V
IO = 5.2 mA; VCC = 6.0 V - 0.16 0.33 - 0.4 V
Qn bus driver outputs
IO = 6 mA; VCC = 4.5 V - 0.15 0.33 - 0.4 V
VOL LOW-level
output voltage
IO = 7.8 mA; VCC = 6.0 V - 0.16 0.33 - 0.4 V
IIinput leakage
current
VI = VCC or GND; VCC = 6.0 V - - ±1.0 - ±1.0 μA
IOZ OFF-state
output current
VI = VIH or VIL; VCC = 6.0 V;
VO = VCC or GND
- - ±5.0 - ±10 μA
ICC supply current VI = VCC or GND; IO = 0 A;
VCC = 6.0 V
- - 80 - 160 μA
CIinput
capacitance
- 3.5 - - - pF
74HC_HCT595 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2021. All rights reserved
Product data sheet Rev. 10 — 29 April 2021 7 / 22
Nexperia 74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
-40 °C to +85 °C -40 °C to +125 °CSymbol Parameter Conditions
Min Typ Max Min Max
Unit
74HCT595
VIH HIGH-level
input voltage
VCC = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - V
VIL LOW-level
input voltage
VCC = 4.5 V to 5.5 V - 1.2 0.8 - 0.8 V
VI = VIH or VIL; VCC = 4.5 V
all outputs
IO = -20 μA 4.4 4.5 - 4.4 - V
Q7S output
IO = -4 mA 3.84 4.32 - 3.7 - V
Qn bus driver outputs
VOH HIGH-level
output voltage
IO = -6 mA 3.7 4.32 - 3.7 - V
VI = VIH or VIL; VCC = 4.5 V
all outputs
IO = 20 μA - 0 0.1 - 0.1 V
Q7S output
IO = 4.0 mA - 0.15 0.33 - 0.4 V
Qn bus driver outputs
VOL LOW-level
output voltage
IO = 6.0 mA - 0.16 0.33 - 0.4 V
IIinput leakage
current
VI = VCC or GND; VCC = 5.5 V - - ±1.0 - ±1.0 μA
IOZ OFF-state
output current
VI = VIH or VIL; VCC = 5.5 V;
VO = VCC or GND
- - ±5.0 - ±10 μA
ICC supply current VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
- - 80 - 160 μA
per input pin;
other inputs at VCC or GND;
IO = 0 A; VI = VCC - 2.1 V;
VCC = 4.5 V to 5.5 V
pins MR, SHCP, STCP, OE - 150 675 - 735 μA
ΔICC additional
supply current
pin DS - 25 113 - 123 μA
CIinput
capacitance
- 3.5 - - - pF
74HC_HCT595 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2021. All rights reserved
Product data sheet Rev. 10 — 29 April 2021 8 / 22
Nexperia 74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
11. Dynamic characteristics
Table 7. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 14.
25 °C -40 °C to
+85 °C
-40 °C to
+125 °C
Symbol Parameter Conditions
Min Typ[1] Max Min Max Min Max
Unit
74HC595
SHCP to Q7S; see Fig. 9 [2]
VCC = 2 V - 52 160 - 200 - 240 ns
VCC = 4.5 V - 19 32 - 40 - 48 ns
VCC = 6 V - 15 27 - 34 - 41 ns
STCP to Qn; see Fig. 10 [2]
VCC = 2 V - 55 175 - 220 - 265 ns
VCC = 4.5 V - 20 35 - 44 - 53 ns
tpd propagation
delay
VCC = 6 V - 16 30 - 37 - 45 ns
MR to Q7S; see Fig. 12
VCC = 2 V - 47 175 - 220 - 265 ns
VCC = 4.5 V - 17 35 - 44 - 53 ns
tPHL HIGH to LOW
propagation
delay
VCC = 6 V - 14 30 - 37 - 45 ns
OE to Qn; see Fig. 13 [3]
VCC = 2 V - 47 150 - 190 - 225 ns
VCC = 4.5 V - 17 30 - 38 - 45 ns
ten enable time
VCC = 6 V - 14 26 - 33 - 38 ns
OE to Qn; see Fig. 13 [4]
VCC = 2 V - 41 150 - 190 - 225 ns
VCC = 4.5 V - 15 30 - 38 - 45 ns
tdis disable time
VCC = 6 V - 12 27 - 33 - 38 ns
SHCP HIGH or LOW; see Fig. 9
VCC = 2 V 75 17 - 95 - 110 - ns
VCC = 4.5 V 15 6 - 19 - 22 - ns
VCC = 6 V 13 5 - 16 - 19 - ns
STCP HIGH or LOW;
see Fig. 10
VCC = 2 V 75 11 - 95 - 110 - ns
VCC = 4.5 V 15 4 - 19 - 22 - ns
VCC = 6 V 13 3 - 16 - 19 - ns
MR LOW; see Fig. 12
VCC = 2 V 75 17 - 95 - 110 - ns
VCC = 4.5 V 15 6 - 19 - 22 - ns
tWpulse width
VCC = 6 V 13 5 - 16 - 19 - ns
74HC_HCT595 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2021. All rights reserved
Product data sheet Rev. 10 — 29 April 2021 9 / 22
Nexperia 74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
25 °C -40 °C to
+85 °C
-40 °C to
+125 °C
Symbol Parameter Conditions
Min Typ[1] Max Min Max Min Max
Unit
DS to SHCP; see Fig. 11
VCC = 2 V 50 11 - 65 - 75 - ns
VCC = 4.5 V 10 4 - 13 - 15 - ns
VCC = 6 V 9 3 - 11 - 13 - ns
SHCP to STCP; see Fig. 11
VCC = 2 V 75 22 - 95 - 110 - ns
VCC = 4.5 V 15 8 - 19 - 22 - ns
tsu set-up time
VCC = 6 V 13 7 - 16 - 19 - ns
DS to SHCP; see Fig. 11
VCC = 2 V 3 -6 - 3 - 3 - ns
VCC = 4.5 V 3 -2 - 3 - 3 - ns
thhold time
VCC = 6 V 3 -2 - 3 - 3 - ns
MR to SHCP; see Fig. 12
VCC = 2 V 50 -19 - 65 - 75 - ns
VCC = 4.5 V 10 -7 - 13 - 15 - ns
trec recovery time
VCC = 6 V 9 -6 - 11 - 13 - ns
SHCP or STCP;
see Fig. 9 and Fig. 10
VCC = 2 V 9 30 - 4.8 - 4 - MHz
VCC = 4.5 V 30 91 - 24 - 20 - MHz
fmax maximum
frequency
VCC = 6 V 35 108 - 28 - 24 - MHz
CPD power
dissipation
capacitance
fi = 1 MHz; VI = GND to VCC [5]
[6]
- 115 - - - - - pF
74HCT595; VCC = 4.5 V to 5.5 V
SHCP to Q7S; see Fig. 9 [2] - 25 42 - 53 - 63 nstpd propagation
delay STCP to Qn; see Fig. 10 [2] - 24 40 - 50 - 60 ns
tPHL HIGH to LOW
propagation
delay
MR to Q7S; see Fig. 12 - 23 40 - 50 - 60 ns
ten enable time OE to Qn; see Fig. 13 [3] - 21 35 - 44 - 53 ns
tdis disable time OE to Qn; see Fig. 13 [4] - 18 30 - 38 - 45 ns
SHCP HIGH or LOW; see Fig. 9 16 6 - 20 - 24 - ns
STCP HIGH or LOW;
see Fig. 10
16 5 - 20 - 24 - ns
tWpulse width
MR LOW; see Fig. 12 20 8 - 25 - 30 - ns
DS to SHCP; see Fig. 11 16 5 - 20 - 24 - nstsu set-up time
SHCP to STCP; see Fig. 11 16 8 - 20 - 24 - ns
74HC_HCT595 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2021. All rights reserved
Product data sheet Rev. 10 — 29 April 2021 10 / 22
Nexperia 74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
25 °C -40 °C to
+85 °C
-40 °C to
+125 °C
Symbol Parameter Conditions
Min Typ[1] Max Min Max Min Max
Unit
thhold time DS to SHCP; see Fig. 11 3 -2 - 3 - 3 - ns
trec recovery time MR to SHCP; see Fig. 12 10 -7 - 13 - 15 - ns
fmax maximum
frequency
SHCP and STCP;
see Fig. 9 and Fig. 10
30 52 - 24 - 20 - MHz
CPD power
dissipation
capacitance
fi = 1 MHz;
VI = GND to VCC - 1.5 V
[5]
[6]
- 130 - - - - - pF
[1] Typical values are measured at nominal supply voltage.
[2] tpd is the same as tPHL and tPLH.
[3] ten is the same as tPZL and tPZH.
[4] tdis is the same as tPLZ and tPHZ.
[5] CPD is used to determine the dynamic power dissipation (PD in μW).
PD = CPD × VCC 2 × fi + Σ(CL × VCC 2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
Σ(CL × VCC 2 × fo) = sum of outputs;
CL = output load capacitance in pF;
VCC = supply voltage in V.
[6] All 9 outputs switching.
11.1. Waveforms and test circuit
Measurement points are given in Table 8.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig. 9. Shift clock pulse, maximum frequency and input to output propagation delays
74HC_HCT595 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2021. All rights reserved
Product data sheet Rev. 10 — 29 April 2021 11 / 22
Nexperia 74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
mna558
STCP input
Qn output
tPLH tPHL
tW
tsu 1/fmax
VM
VOH
VI
GND
VOL
VM
SHCP input
VI
GND
VM
Measurement points are given in Table 8.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig. 10. Storage clock to output propagation delays
mna560
GND
GND
th
tsu
th
tsu
VM
VM
VM
VI
VOH
VOL
VI
Q7S output
SHCP input
DS input
Measurement points are given in Table 8.
The shaded areas indicate when the input is permitted to change for predictable output performance.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig. 11. Data set-up and hold times
mna561
MR input
SHCP input
Q7S output
tPHL
tWtrec
VM
VOH
VOL
VI
GND
VI
GND
VM
VM
Measurement points are given in Table 8.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig. 12. Master reset to output propagation delays
74HC_HCT595 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2021. All rights reserved
Product data sheet Rev. 10 — 29 April 2021 12 / 22
Nexperia 74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
msa697
tPLZ
tPHZ
outputs
disabled
outputs
enabled
90 %
10 %
outputs
enabled
OE input VM
tPZL
tPZH
VM
VM
Qn output
LOW-to-OFF
OFF-to-LOW
Qn output
HIGH-to-OFF
OFF-to-HIGH
trtf
90 %
10 %
Measurement points are given in Table 8.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig. 13. Enable and disable times
Table 8. Measurement points
Input OutputType
VMVM
74HC595 0.5VCC 0.5VCC
74HCT595 1.3 V 1.3 V
74HC_HCT595 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2021. All rights reserved
Product data sheet Rev. 10 — 29 April 2021 13 / 22
Nexperia 74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
VMVM
tW
tW
10 %
90 %
0 V
VI
VI
negative
pulse
positive
pulse
0 V
VMVM
90 %
10 %
tf
tr
tr
tf
001aad983
DUT
VCC VCC
VIVO
RT
RLS1
CL
open
G
Test data is given in Table 9.
Definitions for test circuit:
CL = load capacitance including jig and probe capacitance.
RL = load resistance.
RT = termination resistance should be equal to the output impedance Zo of the pulse generator.
S1 = test selection switch.
Fig. 14. Test circuit for measuring switching times
Table 9. Test data
Input Load S1 positionType
VItr, tfCLRLtPHL, tPLH tPZH, tPHZ tPZL, tPLZ
74HC595 VCC 6 ns 50 pF 1 kΩ open GND VCC
74HCT595 3 V 6 ns 50 pF 1 kΩ open GND VCC
74HC_HCT595 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2021. All rights reserved
Product data sheet Rev. 10 — 29 April 2021 14 / 22
Nexperia 74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
12. Package outline
X
w M
θ
A
A
1
A
2
b
p
D
H
E
L
p
Q
detail X
E
Z
e
c
L
v M A
(A )
3
A
8
9
1
16
y
pin 1 index
UNIT A
max. A
1 A
2 A
3 b
p c D
(1) E
(1) (1)
e H
E L L
p Q Z y w v θ
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm
inches
1.75 0.25
0.10
1.45
1.25 0.25 0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8 1.27 6.2
5.8
0.7
0.6
0.7
0.3 8
0
o
o
0.25 0.1
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
1.0
0.4
SOT109-1 99-12-27
03-02-19
076E07 MS-012
0.069 0.010
0.004
0.057
0.049 0.01 0.019
0.014
0.0100
0.0075
0.39
0.38
0.16
0.15 0.05
1.05
0.041
0.244
0.228
0.028
0.020
0.028
0.012
0.01
0.25
0.01 0.004
0.039
0.016
0 2.5 5 mm
scale
SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
Fig. 15. Package outline SOT109-1 (SO16)
74HC_HCT595 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2021. All rights reserved
Product data sheet Rev. 10 — 29 April 2021 15 / 22
Nexperia 74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
UNIT A
1 A
2 A
3 b
p c D
(1) E
(1) e H
E L L
p Q Z y w v θ
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.21
0.05
1.80
1.65 0.25 0.38
0.25
0.20
0.09
6.4
6.0
5.4
5.2 0.65 1.25
7.9
7.6
1.03
0.63
0.9
0.7
1.00
0.55
8
0
o
o
0.13 0.2 0.1
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
SOT338-1 99-12-27
03-02-19
(1)
w M
b
p
D
H
E
E
Z
e
c
v M A
X
A
y
1 8
16 9
θ
A
A
1
A
2
L
p
Q
detail X
L
(A )
3
MO-150
pin 1 index
0 2.5 5 mm
scale
SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1
A
max.
2
Fig. 16. Package outline SOT338-1 (SSOP16)
74HC_HCT595 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2021. All rights reserved
Product data sheet Rev. 10 — 29 April 2021 16 / 22
Nexperia 74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
UNIT A
1 A
2 A
3 b
p c D
(1) E (2) (1)
e H
E L L
p Q Z y w v θ
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3 0.65 6.6
6.2
0.4
0.3
0.40
0.06
8
0
o
o
0.13 0.1 0.2 1
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
0.75
0.50
SOT403-1 MO-153 99-12-27
03-02-18
w M
b
p
D
Z
e
0.25
1 8
16 9
θ
A
A
1
A
2
L
p
Q
detail X
L
(A )
3
H
E
E
c
v M A
X
A
y
0 2.5 5 mm
scale
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1
A
max.
1.1
pin 1 index
Fig. 17. Package outline SOT403-1 (TSSOP16)
74HC_HCT595 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2021. All rights reserved
Product data sheet Rev. 10 — 29 April 2021 17 / 22
Nexperia 74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
terminal 1
index area
0.5 1
A1 Eh
b
UNIT y e
0.2
c
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 3.6
3.4
Dh
2.15
1.85
y1
2.6
2.4
1.15
0.85
e1
2.5
0.30
0.18
0.05
0.00 0.05 0.1
DIMENSIONS (mm are the original dimensions)
SOT763-1 MO-241 - - - - - -
0.5
0.3
L
0.1
v
0.05
w
0 2.5 5 mm
scale
SOT763-1
DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
16 terminals; body 2.5 x 3.5 x 0.85 mm
A(1)
max.
A
A1
c
detail X
y
y1 C
e
L
Eh
Dh
e
e1
b
2 7
15 10
9
8
1
16
X
D
E
C
B A
terminal 1
index area
A C
C
B
v M
w M
E
(1)
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
D
(1)
02-10-17
03-01-27
Fig. 18. Package outline SOT763-1 (DHVQFN16)
74HC_HCT595 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2021. All rights reserved
Product data sheet Rev. 10 — 29 April 2021 18 / 22
Nexperia 74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
References
Outline
version
European
projection Issue date
IEC JEDEC JEITA
SOT8016-1
sot8016-1_po
Dimensions (mm are the original dimensions)
DHXQFN16: plastic, leadless dual in-line compatible thermal enhanced extreme thin quad flat package;
no leads; 16 terminals; 0.4 mm pitch; body 2 mm x 2.4 mm x 0.48 mm SOT8016-1
pin1 I.D.
2 mm0
scale
1
20-09-18
20-09-22
pin 1
index area
15 10
2 7
1
16 9
8
D1AC B
wM
E1
AC Bu M
Cv M
e
(12x)
L
(16x)
AD B
E
pin 1
index area
C
2x
C
2x
z
z
X
A
A1
A3
C
C
y1C
detail X
seating
plane
y
Unit
mm
max
nom
min
0.48
0.45
0.42
0.23
0.18
0.13
2.4
1.40
1.35
1.30
0.4
0.35
0.30
0.250.2
A
0.05
0.02
0.00
A1A3b D D1
0.1
w
0.05
v
0.1
u
0.15
(typ)
keE
2.0
E1
1.00
0.95
0.90
L y1
0.05
y
0.05
z
0.05
b
(16x)
Fig. 19. Package outline SOT8016-1 (DHXQFN16)
74HC_HCT595 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2021. All rights reserved
Product data sheet Rev. 10 — 29 April 2021 19 / 22
Nexperia 74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
13. Abbreviations
Table 10. Abbreviations
Acronym Description
CMOS Complementary Metal-Oxide Semiconductor
DUT Device Under Test
ESD ElectroStatic Discharge
HBM Human Body Model
MM Machine Model
TTL Transistor-Transistor Logic
14. Revision history
Table 11. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74HC_HCT595 v.10 20210429 Product data sheet - 74HC_HCT595 v.9
Modifications: Type number 74HC595BZ (SOT8016-1 / DHXQFN16) added.
Table 4: Derating values for Ptot total power dissipation updated.
74HC_HCT595 v.9 20170228 Product data sheet - 74HC_HCT595 v.8
Modifications: The format of this data sheet has been redesigned to comply with the identity
guidelines of Nexperia.
Legal texts have been adapted to the new company name where appropriate.
74HC_HCT595 v.8 20160225 Product data sheet - 74HC_HCT595 v.7
Modifications: Type numbers 74HC595N and 74HCT595N (SOT38-4) removed.
74HC_HCT595 v.7 20150126 Product data sheet - 74HC_HCT595 v.6
Modifications: Table 7: Power dissipation capacitance condition for 74HCT595 is corrected.
74HC_HCT595 v.6 20111212 Product data sheet - 74HC_HCT595 v.5
Modifications: Legal pages updated.
74HC_HCT595 v.5 20110628 Product data sheet - 74HC_HCT595 v.4
74HC_HCT595 v.4 20030604 Product specification - 74HC_HCT595_CNV v.3
74HC_HCT595_CNV v.3 19980604 Product specification - -
74HC_HCT595 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2021. All rights reserved
Product data sheet Rev. 10 — 29 April 2021 20 / 22
Nexperia 74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
15. Legal information
Data sheet status
Document status
[1][2]
Product
status [3]
Definition
Objective [short]
data sheet
Development This document contains data from
the objective specification for
product development.
Preliminary [short]
data sheet
Qualification This document contains data from
the preliminary specification.
Product [short]
data sheet
Production This document contains the product
specification.
[1] Please consult the most recently issued document before initiating or
completing a design.
[2] The term 'short data sheet' is explained in section "Definitions".
[3] The product status of device(s) described in this document may have
changed since this document was published and may differ in case of
multiple devices. The latest product status information is available on
the internet at https://www.nexperia.com.
Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. Nexperia does not give any representations or
warranties as to the accuracy or completeness of information included herein
and shall have no liability for the consequences of use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is
intended for quick reference only and should not be relied upon to contain
detailed and full information. For detailed and full information see the relevant
full data sheet, which is available on request via the local Nexperia sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
Nexperia and its customer, unless Nexperia and customer have explicitly
agreed otherwise in writing. In no event however, shall an agreement be
valid in which the Nexperia product is deemed to offer functions and qualities
beyond those described in the Product data sheet.
Disclaimers
Limited warranty and liability — Information in this document is believed
to be accurate and reliable. However, Nexperia does not give any
representations or warranties, expressed or implied, as to the accuracy
or completeness of such information and shall have no liability for the
consequences of use of such information. Nexperia takes no responsibility
for the content in this document if provided by an information source outside
of Nexperia.
In no event shall Nexperia be liable for any indirect, incidental, punitive,
special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal
or replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, Nexperia’s aggregate and cumulative liability towards customer
for the products described herein shall be limited in accordance with the
Terms and conditions of commercial sale of Nexperia.
Right to make changes — Nexperia reserves the right to make changes
to information published in this document, including without limitation
specifications and product descriptions, at any time and without notice. This
document supersedes and replaces all information supplied prior to the
publication hereof.
Suitability for use — Nexperia products are not designed, authorized or
warranted to be suitable for use in life support, life-critical or safety-critical
systems or equipment, nor in applications where failure or malfunction
of an Nexperia product can reasonably be expected to result in personal
injury, death or severe property or environmental damage. Nexperia and its
suppliers accept no liability for inclusion and/or use of Nexperia products in
such equipment or applications and therefore such inclusion and/or use is at
the customer’s own risk.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. Nexperia makes no representation
or warranty that such applications will be suitable for the specified use
without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using Nexperia products, and Nexperia accepts no liability for
any assistance with applications or customer product design. It is customer’s
sole responsibility to determine whether the Nexperia product is suitable
and fit for the customer’s applications and products planned, as well as
for the planned application and use of customer’s third party customer(s).
Customers should provide appropriate design and operating safeguards to
minimize the risks associated with their applications and products.
Nexperia does not accept any liability related to any default, damage, costs
or problem which is based on any weakness or default in the customer’s
applications or products, or the application or use by customer’s third party
customer(s). Customer is responsible for doing all necessary testing for the
customer’s applications and products using Nexperia products in order to
avoid a default of the applications and the products or of the application or
use by customer’s third party customer(s). Nexperia does not accept any
liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those
given in the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — Nexperia products are
sold subject to the general terms and conditions of commercial sale, as
published at http://www.nexperia.com/profile/terms, unless otherwise agreed
in a valid written individual agreement. In case an individual agreement is
concluded only the terms and conditions of the respective agreement shall
apply. Nexperia hereby expressly objects to applying the customer’s general
terms and conditions with regard to the purchase of Nexperia products by
customer.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific Nexperia product is automotive qualified, the
product is not suitable for automotive use. It is neither qualified nor tested in
accordance with automotive testing or application requirements. Nexperia
accepts no liability for inclusion and/or use of non-automotive qualified
products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards,
customer (a) shall use the product without Nexperia’s warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
Nexperia’s specifications such use shall be solely at customer’s own risk,
and (c) customer fully indemnifies Nexperia for any liability, damages or failed
product claims resulting from customer design and use of the product for
automotive applications beyond Nexperia’s standard warranty and Nexperia’s
product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Trademarks
Notice: All referenced brands, product names, service names and
trademarks are the property of their respective owners.
74HC_HCT595 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2021. All rights reserved
Product data sheet Rev. 10 — 29 April 2021 21 / 22
Nexperia 74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
Contents
1. General description......................................................1
2. Features and benefits.................................................. 1
3. Applications.................................................................. 1
4. Ordering information....................................................2
5. Functional diagram.......................................................2
6. Pinning information......................................................3
6.1. Pinning.........................................................................3
6.2. Pin description............................................................. 4
7. Functional description................................................. 5
8. Limiting values............................................................. 6
9. Recommended operating conditions..........................6
10. Static characteristics..................................................7
11. Dynamic characteristics.............................................9
11.1. Waveforms and test circuit.......................................11
12. Package outline........................................................ 15
13. Abbreviations............................................................ 20
14. Revision history........................................................20
15. Legal information......................................................21
© Nexperia B.V. 2021. All rights reserved
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release: 29 April 2021
74HC_HCT595 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2021. All rights reserved
Product data sheet Rev. 10 — 29 April 2021 22 / 22