! i tel 27512 512K (64K x 8) PRODUCTION AND UV ERASABLE PROM Software Carrier Capability mg Low Power 125 mA max. Active 170 ns Maximum Access Time 40 mA max. Standby Two-Line Control @ intgligent Programming Algorithm - Intgligent Identifier Mode ell 9 8 8 Automated Programming Operations Available in 28-Pin Cerdip {See packaging spec order #231369) m TTL Compatible The Intel 27512 is a 5V-only, 524,288-bit ultraviolet Erasable and Electrically Programmable Read Only Memo- ry (EPROM) organized as 64K words by 8 bits. This ensures compatibility with high-performance microproces- sors, such as the Intel 8 MHz iAPX 286, allowing full speed operation without the addition of performance-de- grading WAIT states. The 27512 is also directly compatible with Intel's 8051 family of microcontrollers. The 27512 enables implementation of new, advanced systems with firmware intensive architectures. The combination of the 27512s high-density, cost-effective EPROM storage, and new advanced microprocessors having megabyte addressing capability provides designers with opportunities to engineer user-friendly, high-re- liability, high-performance systems. The 27512s large storage capability of 64 K-bytes enables it to function as a high-density software carrier. Entire operating systems, diagnostics, high-level language programs and specialized application software can reside in a 27512 EPROM directly on a systems memory bus. This permits immediate microprocessor access and execution of software and eliminates the need for time-consuming disk accesses and downloads. Two-line control and JEDEC-approved, 28-pin packaging are standard features of all Intel high-density EPROMs. This assures easy microprocessor interfacing and minimum design efforts when upgrading, adding, or choosing between nonvolatile memory alternatives. The 27512 is manufactured using Intels advanced HMOS *lI-E technology. *HMOS is a patented process of Intel Corporation. Vee Dara ourrurs GND o tee, PROGRAM OEVpp OE AND a TE LOGIC =}! ouTPUT BUFFERS Y oy =S]__pecoven | +, Y-GATING Acds J oI AONPUTS = x : 524, 286 ey PRCODER | CELL MATRIX 231088-1 Figure 1. Block Diagram October 1989 4-111 Order Number: 231088-007a intel 27512 Pin Names Ag-Ai5 Addresses ce Chip Enable OE/Vpp Outputs Enable/Vpp Op~-O7 Outputs D.U. Dont Use 27640 27640 27256 27128A . 27128 27256 27064 | 2732A | 2716 271 2732A 7064 27c2se | 270128 27512 6 2 27128A | 270256 e7c64 87064 Vep Vep Vep Voc Voc Vee Are Ate Ara PGM PEM Ais Ar Az A? A7 Ay Veo | Vee NC. Aig Ai3 re Ae Ae Ae Ae As | As Ag Ag As As As As As As Ag | Ag Ag Ag Ag Ng Ag Aa Aa Ag Vep | Ai Ait Ay Any Ag Ag Ag Ag Ag OE | OE/Vpp | OE OE OE Aa Ag Ae Aa Ae Ato | Ato Ato Ato Ato Ay A Ay Ay Ay CE | CE CE ALE/CE |. CE CE Ao Ao Ag Ag Ao O7 | 07 QO; QO, O7 Oo Oo Oo Oo Oo Og | Og 05 O56 O1 O1 oO, oO; O71 Qs | O05 Os O5 Os Oo O2 Oe O2 O2 QO, | O4 O4 O4 O4 GNO GND GND | GND | GND O3 | 03 O3 03 Q3 231088-2 Figure 2. Pin Configurations EXTENDED TEMPERATURE (EXPRESS) EPROMs The Intel EXPRESS EPROM family is a series of electrically programmable read only memories which have received additional processing to enhance product characteristics. EXPRESS processing is available for several densities of EPROM, allowing the choice of appropriate memory size to match sys- tem applications. EXPRESS EPROM products are available with 168 +8 hours, 125C dynamic burn-in using Intels standard bias configuration. This pro- cess exceeds or meets most industry specifications of burn-in. The standard EXPRESS EPROM operat- ing temperature range is 0C to 70C. Extended op- erating temperature range (~40C to + 85C) EX- PRESS products are available. Like all Intel EPROMs, the EXPRESS EPROM family is inspected to 0.1% electrical AQL. This may allow the user to reduce or eliminate incoming inspection testing. EXPRESS EPROM PRODUCT FAMILY PRODUCT DEFINITIONS Type| Operating Temperature| Burn-in 125C (hr) Q 0C to + 70C 168 +8 T 40C to +85C None L 40C to + 85C 168 +8 EXPRESS OPTIONS 27512 VERSIONS Versions -2 -STD, -285, -30 -3 4-1121 intel READ OPERATION D.C. CHARACTERISTICS identical to standard EPROM parameters except for: Electrical parameters of EXPRESS EPROM products are i TD27512 Symbol Parameter LD27512 Co . tho ns Min Max Isp Voc Standby Current (mA) 50 CE = Vin, OE/Vpp = Vit loci) Voc Active Current (mA) 150 OE/Vpp = CE = Vit Voc Active Current at 125 OE/Vpp = CE = Vit High Temperature (mA) Tambient = 85C NOTE: 1. The maximum current value is with outputs 09 to 07 unloaded. Yeo o As 42d a7 4,0 450 a,c asc af AG Mec oO 02 Ce Vss Cj Orn ane un = ~_sa em wo wn o 14 V7 27512 OE/Vep = +5V_R=1KN Voc = +5V Vgg = GND CE = GND 5 Yeo ay FJ Ay; Py Ag Ag CJA) J OF /Vpp J Ayo 1 CE Voc wT wy 6 ay 3 a a N 3 231088-3 Ais Binary sequence from Ag to Ais 231088-4 Burn-in Bias and Timing Diagrams 4-113i intel 27512 ABSOLUTE MAXIMUM RATINGS* Operating Temperature during Read... .0C to 70C Temperature Under Bias......... 10C to + 80C Storage Temperature .......... 658C to + 125C All Input or Output Voltages with Respect to Ground ............ 0.6V to +6.5V Voltage on Pin 24 with Respect to Ground........... 0.6V to + 13.5V OE/Vpp Supply Voltage with Respect to Ground..... aces 0.6V to + 14.0V Voc Supply Voltage with Respect to Ground ...............----- 0.6V to + 7.0V READ OPERATION D.C. CHARACTERISTICS orc < Ty, < +70C *Notice: Stresses above those listed under Abso- lute Maximum Ratings may cause permanent dam- age to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the opera- tional sections of this specification is not implied. Ex- posure to absolute maximum rating conditions for extended periods may affect device reliability. Limits Test Symbol Parameter Min Type Max Units Conditions lu Input Load Current 10 pA Vin = OV to Voc ILo Output Leakage Current 10 pA Vout = OV to Voc ign(4) Voc Current Standby 40 mA CE = Vin loc, 4) Voc Current Active 125 mA CE = OE/Vpp = Vit ViL Input Low Voltage -0.1 +0.8 Vv Vin Input High Voltage 2.0 Voc +1 Vv Vor Output Low Voltage 0.45 Vv lo. = 2.1 mA VoH Output High Voltage 2.4 Vv lon = 400 pA 4-114| 27512 ABO|OUYde} 3-1] SOWH Peyedwoo uo peonpoid eue seynUep! peeds y16ip-g ay) YM syoNpoud |Iy 9 dipsey = xyoud ON :suondo Buibexoey s pepeojun 49-29 syndjno yp si enjeA jUBUND WNWIXeW eu P weafelp Buu aesuaAup ioBudc] Ou si eyeEp aseyM yUIOd Buy SB PEUYyEpP SI JeOL4 INdINC "pe}se} %OO} JOU si pue pajdwes AjuO si JaJQWBIed SIU, 'E -seBey0a Addns jeuwou pue 9,GzZ = V1 410) ave sanjea Bodh! 2 dda /34Q Jeye 10 Ajsnoeueynuis peaowas pue dda 73AQ es0jeq 10 Ajsnoaue\nus paydde eq ysnw ID, 1 SALON }Sdl4 POundsdOC, JeaayoiUM 44 A730 10 30 Wa = ddaygo = 30] su 0 0 0 0 Sesselppy WO PJOH INd\nE (eH Mm=a30] su | sor] o 09 0 gg 0 os 0 | yeO}4 INdING 0} YBIH dda 730 (4% W=39| su | oz ol SL 09 Aejaq nding 01 444/30 30) Wa = 4dayazq| su | ooe osz 002 OLt Aejeq indno 0) 30 ay Wa = 4dAsaO0 = 30] su | O0 ose 002 OL Aejaq indyno 0} sseuppy 994 xew | UIN xew UW xew UW xew UIA s9}OWeIed joquiAs . 7 OLAOOZ-Z1S2Z =929 suonipuog syun OE-eLsie Se-ebsle 02-Z1S22 %OL + ~A 1s0L (9 g)SUOISIBA -ZLGLZ ZLGLZz Z-Z1G2Z SOAOL}-Z1S2Z %GF IA 9004+ 5 VL 59.0 SOLLSIYALOVHVHO OV 4-115CAPACITANCE(2) 1, = 25C, f= 1 MHz Symbol Parameter Typ(1) | Max | Units | Conditions Cin Input Capacitance 4 6 pF | Vin = OV CouTt Output Capacitance 8 12 | pF | Vout = OV CoE/Vpp|OE/Vpp Capacitance} 18 | 25 | pF | Vin = OV A.C. TESTING INPUT/OUTPUT WAVEFORM A.C. TESTING LOAD CIRCUIT 1.3V 2.4 5 5 2.0 . 2.0 note INPUT TEST POINTS OUTPUT x 0.8 = =_{ <i 0.45 45 . 3.3K0 - DEVICE 231088-5 UNDER out TEST CL 100 pF AC. Testing: Inputs are driven at 2.4V for a Logic 1 and 0.45V L for a Logic 0. Timing measurements are made at 2.0V for a = Logic 1 and 0.8V for a Logic 0. 231088-6 CL = 100 pF C, includes Jig Capacitance A.C. WAVEFORMS Vie Vin easeesene VALID Vie Vin je tog) tox) | pr ee veceece 4 HIG VALID OUTPUT SS Hz Z/ OUTPUT HIGH 2 OE/Vpp Vie @) errr, typ?) tog! tacc 231088-7 NOTES: 1. Typical values are for Ta = 25C and nominal supply voltages. 2. This parameter is only sampled and is not 100% tested. 3. OE/Vpp may be delayed up to teto after the falling edge of CE without impact on tce. 4-116! intel 27512 DEVICE OPERATION The modes of operation of the 27512 are listed in Table 1. A single 5V power supply is required in the read mode. All inputs are TTL levels except for OE/Vpp and 12V on AQ for intgligent identifier mode. Read Mode The 27512 has two control functions, both of which must be logically active in order to obtain data at the outputs. Chip Enable (CE) is the power control and should be used for device selection. Output Enable (OE/Vpp) is the output contro! and should be used to gate data from the output pins, independent of device selection. Assuming that addresses are sta- ble, the address access time (tacc) is equal to the delay from CE to output (tce). Data is available at the outputs after a delay of tog from the falling edge of OE, assuming that CE has been low and address- es have been stable for at least tacc-toe. Standby Mode The 27512 has a standby mode which reduces the maximum active current from 125 mA to 40 mA. The 27512 is placed in the standby mode by applying a TTL-high signal to the CE input. When in standby mode, the outputs are in a high impedance state, independent of the OE/Vpp input. Two Line Output Control Because EPROMs are usually used in larger memo- ry arrays, Intel has provided 2 control lines which accommodate this multiple memory connection. The two control lines allow for: a) the lowest possible memory power dissipation, and b) complete assurance that output bus contention will not occur. To use these two control lines most efficiently, CE should be decoded and used as the primary device selecting function, while GE/Vpp Should be made a common connection to all devices in the array and connected to the READ line from the system control bus. This assures that all deselected memory devic- es are in their low power standby mode and that the output pins are active only when data is desired from a particular memory device. SYSTEM CONSIDERATIONS The power switching characteristics of EPROMs re- quire careful decoupling of the devices. The supply current, Icc, has three segments that are of interest to the system designerthe standby current level, the active current level, and the transient current peaks that are produced by the falling and rising edges of Chip Enable. The magnitude of these tran- sient current peaks is dependent on the output ca- pacitive and inductive loading of the device. The as- sociated transient voltage peaks can be suppressed by complying with Intels Two-Line Control and by properly selected decoupling capacitors. It is recom- mended that a 0.1 F ceramic capacitor be used on every device between Voc and GND. This shouid be a high frequency capacitor of low inherent induc- tance and should be placed as close to the device as possible. In addition, a 4.7 F bulk electrolytic capacitor should be used between Vcc and GND for every eight devices. The bulk capacitor should be located near where the power supply is connected to the array. The purpose of the bulk capacitor is to overcome the voltage droop caused by the inductive effects of PC board traces. This inductive effect should be further minimized through special layout considerations such as larger traces and gridding (refer to High Speed Memory System Design Using the 2147H, AP-74). In particular, the Vgs (Ground) plane should be as stable as possible. Table 1. Operating Modes pins | GE OE/Vpp Ag Ay Vec Outputs Mode Read ViL ViL x1) x 5.0V Dout Output Disable Vit Vin X xX ~ Veco High Z Standby Vin X X X Voc High Z Program Vit Vpp(3) x x 6.0V Din Verify Vit Vit x x 6.0V Oout Program Inhibit Vind Vpp(3) x x 6.0V High 2 intgligent Manufacturer VIL ViL Vy (2) Vic 5.0V 89H Identifier(4) Device VIL Vit Vy(2) Vin 5.0V ODH NOTES: 1. X can be Vyq or Vic. 2.VH = 12.0V +0.5V. 3. Vpp = 12.5 +0.5V. 4. Ay-Ag, Ato-A13 = Vit; Ara, Ais = Vin. 4-117intel 27512 PROGRAMMING MODES Caution: Exceeding 14.0V on OE/Vpp will perma- nently damage the device. Initially, and after each erasure, all bits of the EPROM are in the 1 state. Data is introduced by selectively. programming Os into the desired bit lo- cations. Although only 0s will be programmed, both 1s and Os can be present in the data word. The only way to change a 0 to a 1 is by ultravio- let light erasure (Cerdip EPROMs). The EPROM is in the programming mode when the OE/Vpp input is raised to its programming voltage (see Table 2) and CE is at TTL-low. The data to be programmed is applied 8 bits in parallel to the data output pins. The levels required for the address and data inputs are TTL. Program inhibit Programming of multiple 25712s in parallel with dif- ferent data is easily accomplished by using the Pro- gram Inhibit mode. A high-level CE input inhibits the other 27512s from being programmed. Except for CE, all inputs of the parallel 27512s may be common. A TTL low-level pulse applied to the CE input with OE/Vpp at its programming voltage will program the selected 27512. Verify A verify (read) should be performed on the pro- grammed bits to determine that they have been cor- rectly programmed. The verify is performed with OE/ Vpp and CE at Vi_ and Vcc is at its programming voltage. Data should be verified tpy after the falling edge of CE. inteligent Identifier Mode The intgligent identifier Mode allows the reading out of a binary code from an EPROM that will identify its manufacturer and type. This mode is intended for use by programming equipment for the purpose of automatically matching the device to be pro- grammed with its corresponding programming algo- rithm. This mode is functional in the 25C +5C am- bient temperature range that is required when pro- gramming the device. To activate this mode, the programming equipment must force 11.5V to 12.5V on address line AQ of the EPROM. Two identifier bytes may then be se- quenced from the device outputs by toggling ad- dress line AO from Vi, to Vi. All other address lines must be held at Vj, during the intgligent Identifier Mode, except for A14 and A15 which should be held high. Byte 0 (AO = Vj.) represents the manufacturer code and byte 1 (AO = Viz) the device identifier code. These two identifier bytes are given in Table 1. ERASURE CHARACTERISTICS (FOR CERDIP EPROMS) The erasure characteristics are such that erasure begins to occur upon exposure to light with wave- lengths shorter than approximately 4000 Angstroms (A). It should be noted that sunlight and certain types of fluorescent lamps have wavelengths in the 3000-4000A range. Data show that constant expo- sure to room level fluorescent lighting could erase the EPROM in approximately 3 years, while it would take approximately 1 week to cause erasure when exposed to direct sunlight. If the device is to be ex- posed to these types of lighting conditions for ex- tended periods of time, opaque labels should be placed over the window to prevent unintentional era- sure. The recommended erasure procedure is exposure to shortwave ultraviolet light which has a wavelength of 2537 Angstroms (A). The integrated dose (i.e., UV intensity < exposure time) for erasure should be a minimum of 15 Wsec/cm2. The erasure time with this dosage is approximately 15 to 20 minutes using an ultraviolet lamp with a 12000 .W/cm2 power rat- ing. The EPROM should be placed within 1 inch of the lamp tubes during erasure. The maximum inte- grated dose an EPROM can be exposed to without damage is 7258 Wsec/cm2 (1 week @ 12000 p.W/cm2). Exposure of the device to high intensity UV light for longer periods may cause permanent damage. 4-118a intel 27512 START ADOR FIRST LOCATION PROGRAM ONE 1 msec PULSE INCREMENT X NO! VERIFY ONE BYTE PASS PROGRAM ONE PULSE OF 3X msec DURATION INCREMENT ADDR DEVICE FAILED DEVICE FAKEO DEVICE PASSED 231088-8 Figure 5. inteligent Programming Flowchart inteligent Programming Algorithm The intgligent Programming Algorithm programs Intel EPROMs using an efficient and reliable method particularly suited to the production programming environment. Typical programming time for individu- al devices are on the order of six minutes. Actual programming times may vary due to differences in programming equipment. Programming reliability is also ensured as the incremental program margin of each byte is continually monitored to determine when it has been successfully programmed. A flow- chart of the intgligent Programming Algorithm is shown in Figure 4. The intgligent Programming Algorithm utilizes two different pulse types: initial and overprogram. The duration of the initial pulse(s) is one millisecond, which will then be followed by a longer overprogram pulse of length 3X msec. X is an iteration counter and is equal to the number of the initial one millisec- ond pulses applied to a particular location, before a correct verify occurs. Up to 25.one-millisecond puls- es per byte are provided for before the overprogram pulse is. applied. The entire sequence of program pulses and byte verifications is performed at Vcc = 6.0V. When the intgligent Programming cy- cle has been completed, all bytes should be com- pared to the original data with Voc = 5.0V. 4-119i intel 27512 TABLE 2. D.C. PROGRAMMING CHARACTERISTICS Ta = 25 +5C Symbol Parameter Limits Test Conditions Min | Max | Unit (Note 1) ly Input Current (All Inputs) 10 PA | Vin = Vicor Vin ViL input Low Level (All Inputs) 0.1 0.8 Vv Vin Input High Level 2.0 Voc +1 v VoL Output Low Voltage During Verify 0.45 Vv lo, 2.1 mA VoH Output High Voltage During Verify 2.4 Vv lon = 400 pA Iocel4) Vdc Supply Current (Program & Verify) 125 mA Ippo(4) | Vpp Supply Current (Program) 40 mA | CE = Vi, OE/Vpp = Vpp Vio Ag intgligent Identifier Voltage 11.5 12.5 Vv Vpp intgligent Programming Algorithm 12.0 13.0 Vv Voc intgligent Programming Algorithm 5.75 6.25 Vv A.C. PROGRAMMING CHARACTERISTICS Ta = 25 +5C Symbol Parameter Limits Conditions* Min | Typ | Max | Unit (Note 1) tas Address Setup Time 2 ys toes OE/Vpp Setup Time 2 ps tps Data Setup Time 2 a) taH Address Hold Time 0 ws toH Data Hold Time 2 pS toFp Output Enable to Output Float Delay 0 130 ns (Note 3) tvcs Voc Setup Time 2 ps | (Note 1) tpw CE Initial Program 0.95 | 1.0 | 1.05 | ms | intgligent Programming Pulse Width topw CE Overprogram Pulse Width 2.85 78.75 | ms | (Note 2) toEH OE/Vpp Hold Time 2 pS tov Data Valid from CE 1 ps tv OE/Vpp Recovery Time 2 ps tprat OE/Vpp Pulse Rise Time 50 ns During Programming NOTES: *A.C. CONDITIONS OF TEST Input Rise and Falt Times (10% to 90%)...... 20 ns Input Pulse Levels .................. 0.45V to 2.4V Input Timing Reference Level ....... 0.8V and 2.0V Output Timing Reference Level ...... 0.8V and 2.0V 1. Voc must be applied simultaneously or before O E/Vpp and removed simultaneously or after OE/Vpp. 2. The length of the overprogram pulse (intgligent Program- ming Algorithm) may vary from 2.85 msec to 78.75 msec as a function of the iteration counter value X. 3. This parameter is only sampied and is not 100% tested. Output Float is defined as the point where data is no long- er drivensee timing diagram. 4. The maximum current valu is with outputs Oo to O7 un- loaded. 4-120! intel 27512 PROGRAMMING WAVEFORMS Vin ADDRESSES ADDRESS STABLE Vu tas ty DATA OUT | DATA DATA | IN STABLE oe VALID {os > toH i ej 12.5V OE/Vpp 6.0V Vec Vv / | >) pettore 50 Tvcsa| . tors we-tOEH: tVR 231088-9 NOTES: 1. The Input Timing Reference Level is 0.8V for Vi_ and 2.0V for a Vi. 2. tog and tprp are characteristics of the device but must be accommodated by the programmer. REVISION HISTORY Number Description 07 Revised Pin Configuration, Express Options D.C. Characteristics-|_| Test Conditions-Vij = OV to Vcc D.C. Characteristics-l_ Test Conditions-Voyt = OV to Voc Deleted -200V05 Speed Bin 4-121