IRFBA1405P - International Rectifier

HEXFET® Power MOSFET

VDSS = 55V

RDS(on) = 5.0mΩ

ID = 174A

Description

8/14/02

www.irf.com 1

●Advanced Process Technology

●Ultra Low On-Resistance

●Dynamic dv/dt Rating

●175°C Operating Temperature

●Fast Switching

●Repetitive Avalanche Allowed up to Tjmax

Benefits

AUTOMOTIVE MOSFET IRFBA1405P

Typical Applications

●Electric Power Steering (EPS)

●Anti-lock Braking System (ABS)

●Wiper Control

●Climate Control

●Power Door

Super-220

Specifically designed for Automotive applications, this Stripe Planar

design of HEXFET® Power MOSFETs utilizes the latest processing

techniques to achieve extremely low on-resistance per silicon area.

Additional features of this MOSFET are a 175oC junction operating

temperature, fast switching speed and improved ruggedness in

single and repetitive avalanche. The Super-220 TM is a package that

has been designed to have the same mechanical outline and pinout

as the industry standard TO-220 but can house a considerably

larger silicon die. The result is significantly increased current

handling capability over both the TO-220 and the much larger TO-

247 package. The combination of extremely low on-resistance

silicon and the Super-220 TM package makes it ideal to reduce the

component count in multiparalled TO-220 applications, reduce

system power dissipation, upgrade existing designs or have TO-247

performance in a TO-220 outline. This package has been designed

to meet automotive, Q101, qualification standard.

These benefits make this design an extremely efficient and reliable

device for use in Automotive applications and a wide variety of other

applications.

Absolute Maximum Ratings

Parameter Max. Units

ID @ TC = 25°C Continuous Drain Current, VGS @ 10V 174

ID @ TC = 100°C Continuous Drain Current, VGS @ 10V 123A

IDM Pulsed Drain Current 680

PD @TC = 25°C Power Dissipation 330 W

Linear Derating Factor 2.2 W/°C

VGS Gate-to-Source Voltage ± 20 V

EAS Single Pulse Avalanche Energy560 mJ

IAR Avalanche Current See Fig.12a, 12b, 15, 16 A

EAR Repetitive Avalanche EnergymJ

dv/dt Peak Diode Recovery dv/dt 5.0 V/ns

TJOperating Junction and -40 to + 175

TSTG Storage Temperature Range -55 to + 175

Soldering Temperature, for 10 seconds 300 (1.6mm from case )

Recommended clip force 20 N

°C

PD -94111A

http://store.iiic.cc/

IRFBA1405P

2www.irf.com

Parameter Min. Typ. Max. Units Conditions

V(BR)DSS Drain-to-Source Breakdown Voltage 55 ––– ––– V VGS = 0V, ID = 250µA

∆V(BR)DSS/∆TJBreakdown Voltage Temp. Coefficient ––– 0.057 ––– V/°C Reference to 25°C, ID = 1mA

RDS(on) Static Drain-to-Source On-Resistance ––– 4.3 5.0 mΩVGS = 10V, ID = 101A 

VGS(th) Gate Threshold Voltage 2.0 ––– 4.0 V VDS = 10V, ID = 250µA

gfs Forward Transconductance 69 ––– ––– S VDS = 25V, ID = 110A

––– ––– 20 µA VDS = 55V, VGS = 0V

––– ––– 250 VDS = 44V, VGS = 0V, TJ = 150°C

Gate-to-Source Forward Leakage ––– ––– 200 VGS = 20V

Gate-to-Source Reverse Leakage ––– ––– -200 nA VGS = -20V

QgTotal Gate Charge ––– 17 0 260 ID = 101A

Qgs Gate-to-Source Charge ––– 44 66 nC VDS = 44V

Qgd Gate-to-Drain ("Miller") Charge ––– 62 93 VGS = 10V

td(on) Turn-On Delay Time ––– 13 ––– VDD = 38V

trRise Time ––– 190 – –– ID = 110A

td(off) Turn-Off Delay Time ––– 130 ––– RG = 1.1Ω

tfFall Time ––– 110 ––– VGS = 10V 

Between lead,

––– ––– 6mm (0.25in.)

from package

and center of die contact

Ciss Input Capacitance ––– 5480 ––– VGS = 0V

Coss Output Capacitance ––– 1210 ––– pF VDS = 25V

Crss Reverse Transfer Capacitance –– – 280 ––– ƒ = 1.0MHz, See Fig. 5

Coss Output Capacitance ––– 5210 ––– VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz

Coss Output Capacitance ––– 900 ––– VGS = 0V, VDS = 44V, ƒ = 1.0MHz

Coss eff. Effective Output Capacitance ––– 1500 ––– VGS = 0V, VDS = 0V to 44V

Electrical Characteristics @ TJ = 25°C (unless otherwise specified)

LDInternal Drain Inductance

LSInternal Source Inductance ––– –––

IGSS

4.5

7.5

IDSS Drain-to-Source Leakage Current

Parameter Min. Typ. Max. Units Conditions

ISContinuous Source Current MOSFET symbol

(Body Diode) ––– ––– showing the

ISM Pulsed Source Current integral reverse

(Body Diode) ––– ––– p-n junction diode.

VSD Diode Forward Voltage ––– ––– 1.3 V TJ = 25°C, IS = 101A, VGS = 0V 

trr Reverse Recovery Time ––– 88 130 ns TJ = 25°C, IF = 101A

Qrr Reverse RecoveryCharge ––– 25 0 380 nC di/dt = 100A/µs 

ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)

Source-Drain Ratings and Characteristics

174

680

Thermal Resistance Parameter Typ. Max. Units

RθJC Junction-to-Case ––– 0.45 °C/W

RθCS Case-to-Sink, Flat, Greased Surface 0.50 –––

RθJA Junction-to-Ambient ––– 58

http://store.iiic.cc/

IRFBA1405P

www.irf.com 3

Fig 4. Normalized On-Resistance

Vs. Temperature

Fig 2. Typical Output CharacteristicsFig 1. Typical Output Characteristics

Fig 3. Typical Transfer Characteristics

100

1000

0.1 1 10 100

20µs PU LSE WIDTH

T = 25 C

J°

TOP

BOTTOM

VGS

15V

10V

8.0V

7.0V

6.0V

5.5V

5.0V

4.5V

V , Drain-to-Source Voltage (V)

I , Drain-to-Source Current (A)

4.5V

100

1000

0.1 1 10 100

20µs PU LSE WIDTH

T = 175 C

J°

TOP

BOTTOM

VGS

15V

10V

8.0V

7.0V

6.0V

5.5V

5.0V

4.5V

V , Drain-to-Source Voltage (V)

I , Drain-to-Source Current (A)

4.5V

100

1000

4 6 8 10 12

V = 2 5 V

20µs PULSE WIDTH

V , Gate-to-Sou rce Voltage (V)

I , Drain-to-Source Current (A)

T = 25 C

J°

T = 175 C

J°

-60 -40 -20 020 40 60 80 100 120 140 160 180

0.0

0.5

1.0

1.5

2.0

2.5

3.0

T , Junction Temperature ( C)

R , Drain-to-Source On Resistance

(Normalized)

DS(on)

V =

I =

10V

169A

http://store.iiic.cc/

IRFBA1405P

4www.irf.com

Fig 8. Maximum Safe Operating Area

Fig 6. Typical Gate Charge Vs.

Gate-to-Source Voltage

Fig 5. Typical Capacitance Vs.

Drain-to-Source Voltage

Fig 7. Typical Source-Drain Diode

Forward Voltage

060 120 180 240 300

Q , Total G a te C harge (nC)

V , Gate-to-Source Voltage (V)

FOR TEST CIRCUIT

SEE FIGURE

I =

101A

V = 27V

V = 44V

100

1000

0.0 0.5 1.0 1.5 2.0 2.5 3.0

V ,Source-to-Drain Voltage (V)

I , Reverse Drain Current (A)

V = 0 V

T = 25 C

J°

T = 175 C

J°

110 100

VDS, Dr ain-to-Source Voltage (V)

100

1000

10000

100000

C, Capacitance(pF)

Coss

Crss

Ciss

VGS = 0V, f = 1 MHZ

Ciss = C

gs + Cgd, C

ds SHORTED

Crss

= C

Coss

= C

ds + Cgd

100

1000

10000

1 10 100

OPERATION IN THIS AR EA LIMITED

BY RDS(on)

Single Pulse

T = 175 C

= 25 C

°°

V , Drain-to-Source Voltage (V)

I , Drain Current (A)I , Drain Current (A)

10us

100us

1ms

10ms

http://store.iiic.cc/

IRFBA1405P

www.irf.com 5

Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case

Fig 9. Maximum Drain Current Vs.

Case Temperature

VDS

90%

10%

VGS t

d(on)

d(off)

VDS

Pulse Width ≤ 1 µs

Duty Factor ≤ 0.1 %

VGS

D.U.T.

10V

VDD

Fig 10a. Switching Time Test Circuit

Fig 10b. Switching Time Waveforms

25 50 75 100 125 150 175

120

160

200

T , Case Temperature ( C )

I , Drain Current (A)

LIMITED BY PACKAGE

0.001

0.01

0.1

0.00001 0.0001 0.001 0.01 0.1

Notes:

1. D u ty fa c to r D = t / t

2. Peak T =P x Z + T

1 2

JDM thJC C

t , Rectangular Pul se Durati on ( s ec)

Thermal R esponse (Z )

thJC

0.01

0.02

0.05

0.10

0.20

D = 0.50

SINGLE PULSE

(THERMAL RESPONSE)

http://store.iiic.cc/

IRFBA1405P

6www.irf.com

Charge

D.U.T. V

3mA

.3µF

50KΩ

.2µF

12V

Current Regulator

Same Type as D.U.T.

Current Sampling Resistors

10 V

Fig 13b. Gate Charge Test Circuit

Fig 13a. Basic Gate Charge Waveform

Fig 12c. Maximum Avalanche Energy

Vs. Drain Current

Fig 12b. Unclamped Inductive Waveforms

Fig 12a. Unclamped Inductive Test Circuit

(BR)DSS

0.01

Ω

D.U.T

VDS

-V

DRIVER

15V

20V

Fig 14. Threshold Voltage Vs. Temperature

-75 -50 -25 025 50 75 100 125 150 175

TJ , Temperatur e ( ° C )

1.5

2.0

2.5

3.0

3.5

4.0

VGS(th) , Variace ( V )

ID = 250µA

25 50 75 100 125 150 175

200

400

600

800

1000

1200

Start ing T , Junction Temperat ure ( C)

E , Single Pulse Avalanche Energy (mJ)

TOP

BOTTOM

41A

71A

101A

http://store.iiic.cc/

IRFBA1405P

www.irf.com 7

Fig 15. Typical Avalanche Current Vs.Pulsewidth

Fig 16. Maximum Avalanche Energy

Vs. Temperature

Notes on Repetitive Avalanche Curves , Figures 15, 16:

(For further info, see AN-1005 at www.irf.com)

1. Avalanche failures assumption:

Purely a thermal phenomenon and failure occurs at a

temperature far in excess of Tjmax. This is validated for

every part type.

2. Safe operation in Avalanche is allowed as long asTjmax is

not exceeded.

3. Equation below based on circuit and waveforms shown in

Figures 12a, 12b.

4. PD (ave) = Average power dissipation per single

avalanche pulse.

5. BV = Rated breakdown voltage (1.3 factor accounts for

voltage increase during avalanche).

6. Iav = Allowable avalanche current.

7. ∆T = Allowable rise in junction temperature, not to exceed

Tjmax (assumed as 25°C in Figure 15, 16).

tav = Average time in avalanche.

D = Duty cycle in avalanche = t av ·f

ZthJC(D, tav) = Transient thermal resistance, see figure 11)

PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC

Iav = 2DT/ [1.3·BV·Zth]

EAS (AR) = PD (ave)·tav

1.0E-08 1.0E-07 1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01

tav (sec)

100

1000

Avalanche Current (A)

0.05

Dut y Cycle = Single Pulse

0.10

Allowed avalanche Current vs

avalanche pulsewidth, tav

assuming ∆Tj = 25°C due to

avalanche losses

0.01

25 50 75 100 125 150 175

Starting TJ , Junction Temperatur e (°C)

100

200

300

400

500

600

EAR , Avalanche Energy (mJ)

TOP Single Pulse

BOTTOM 10% Duty Cycle

ID = 101A

http://store.iiic.cc/

IRFBA1405P

8www.irf.com

Peak Diode Recovery dv/dt Test Circuit

P.W. Period

di/dt

Diode Recovery

dv/dt

Ripple ≤5%

Body Diode Forward Drop

Re-Applied

Voltage

Reverse

Recovery

Current Body Diode Forward

Current

=10V

Driver Gate Drive

D.U.T. I

Waveform

D.U.T. V

Waveform

Inductor Curent

D = P.W.

Period







VDD

• dv/dt controlled by RG

• ISD controlled by Duty Factor "D"

• D.U.T. - Device Under Test

D.U.T*Circuit Layout Considerations

• Low Stray Inductance

• Ground Plane

• Low Leakage Inductance

Current Transformer



* Reverse Polarity of D.U.T for P-Channel

VGS

[ ]

*** VGS = 5.0V for Logic Level and 3V Drive Devices

[ ] ***

Fig 17. For N-channel HEXFET® power MOSFETs

http://store.iiic.cc/

IRFBA1405P

www.irf.com 9

Super-220 Package Outline

L EAD ASSIGNMENTS

2 - DRAI N

1 - GATE

MOS FET

4 - DRAI N

3 - SOURCE 4 - COLLECTOR

3 - EMITTER

2 - COLLECTOR

1 - GATE

IGBT

 Repetitive rating; pulse width limited by

max. junction temperature. (See fig. 11).

 Starting TJ = 25°C, L = 0.11mH

RG = 25Ω, IAS = 101A. (See Figure 12).

ISD ≤ 101A, di/dt ≤ 210A/µs, VDD ≤ V(BR)DSS,

TJ ≤ 175°C

 Pulse width ≤ 400µs; duty cycle ≤ 2%.

Notes:

 Coss eff. is a fixed capacitance that gives the same charging time

as Coss while VDS is rising from 0 to 80% VDSS .Refer to AN-1001

 Calculated continuous current based on maximum allowable

junction temperature. Package limitation current is 95A.

 Limited by TJmax , see Fig.12a, 12b, 15, 16 for typical repetitive

avalanche performance.

123

0.25 [.010] B A

3.00 [.118]

2.50 [.099]

14.5 0 [ . 570]

13.0 0 [ . 512]

4.00 [.157]

3.50 [.138]

1.30 [.051]

0.90 [.036]

2.5 5 [ . 100]

1.00 [.039]

0.70 [.028]

5.00 [.196]

4.00 [.158]

11.0 0 [. 433]

10.0 0 [. 394]

1.5 0 [ . 059]

0.50 [.020]

15.0 0 [ . 590]

14.0 0 [ . 552]

9.00 [.354]

8.00 [.315]

13. 50 [ . 531 ]

12. 50 [ . 493 ]

1. DIMENSIONING & TOLERANCING PER ASME Y14.5M-1994

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS ARE SHOWN IN MILLIMETERS [INCHES].

NOTES:

4. OU TLINE CONF OR MS TO JEDEC OUTL INE TO-273AA.

Data and specifications subject to change without notice.

This product has been designed and qualified for the automotive [Q101] market.

Qualification Standards can be found on IR’s Web site.

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105

TAC Fax: (310) 252-7903

Visit us at www.irf.com for sales contact information. 8/02

Super-220 not recommended for surface mount application

http://store.iiic.cc/