Arria V SoC Development Board Reference Manual Arria V SoC Development Board Reference Manual 101 Innovation Drive San Jose, CA 95134 www.altera.com MNL-01080-1.1 Feedback Subscribe (c) 2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. April 2014 Altera Corporation ISO 9001:2008 Registered Arria V SoC Development Board Reference Manual Contents Chapter 1. Overview General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Board Component Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Development Board Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 Handling the Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 Chapter 2. Board Components Board Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Featured Device: Arria V SoC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 I/O Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 MAX V CPLD 5M2210 System Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 FPGA Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 FPGA Programming over On-Board USB-Blaster II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 FPGA Programming from Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 FPGA Programming over External USB-Blaster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 Status Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 Setup Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 Board Settings DIP Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 JTAG Chain Control DIP Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17 FPGA Configuration Mode DIP Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17 HPS Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18 CPU Reset Push Button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18 MAX V Reset Push Button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18 Program Configuration Push Button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19 Program Select Push Button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19 General User Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19 User-Defined Push Buttons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19 User-Defined DIP Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20 User-Defined LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20 Character LCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21 Clock Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21 On-Board Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21 Off-Board Input/Output Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22 Components and Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23 PCI Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23 10/100/1000 Ethernet (HPS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25 10/100 Ethernet (FPGA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26 FMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29 RS-232 UART (HPS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-36 Real-Time Clock (HPS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-37 SFP+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-37 I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-38 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-39 DDR3 SDRAM (FPGA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-39 DDR3 SDRAM (HPS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-45 QSPI Flash (HPS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-50 EPCQ Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-50 Synchronous Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-51 April 2014 Altera Corporation Arria V SoC Development Board Reference Manual iv ContentsContents Micro SD Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-52 I2C EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-53 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-53 Power Distribution System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-54 Power Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-55 Chapter 3. Board Components Reference Statement of China-RoHS Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 CE EMI Conformity Caution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 Additional Information Board Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Arria V SoC Development Board Reference Manual Info-1 Info-1 Info-1 Info-2 April 2014 Altera Corporation 1. Overview This document describes the hardware features of the Arria(R) V SoC development board, including the detailed pin-out and component reference information required to create custom FPGA designs that interface with all components of the board. General Description The Arria V SoC development board provides a hardware platform for developing and prototyping low-power, high-performance, and logic-intensive designs using Altera's Arria V SoC. The board provides a wide range of peripherals and memory interfaces to facilitate the development of Arria V SoC designs. f For more information about the Arria V device family, refer to the Arria V Device Handbook. Board Component Blocks The development board features the following major component blocks: One Arria V SoC (5ASTFD5K3F40I3) in a 1517-pin FBGA package FPGA configuration circuitry April 2014 Altera Corporation Active Serial (AS) x1 or x4 configuration (EPCQ256SI16N) MAX(R) V CPLD (5M2210ZF256) in a 256-pin FBGA package as the System Controller Flash fast passive parallel (FPP) configuration MAX II CPLD (EPM570GF100) as part of the on-board USB-BlasterTM II for use with the Quartus(R) II Programmer Clocking circuitry Si570, Si571, and Si5338 programmable oscillators 50-MHz, 66-MHz, 100-MHz, 125-MHz programmable oscillators SMA input (LVCMOS) Arria V SoC Development Board Reference Manual 1-2 Chapter 1: Overview Board Component Blocks Arria V SoC Development Board Reference Manual Memory One 1,024-Mbyte (MB) HPS DDR3 SDRAM with error correction code (ECC) support Two 1,024-MB FPGA DDR3 SDRAM One 512-Megabit (Mb) quad serial peripheral interface (QSPI) flash One 512-Mb CFI synchronous flash One 256-Mb NOR flash (EPCQ device) One 32-Kilobit (Kb) I2C serial electrically erasable PROM (EEPROM) One Micro SD flash memory card Communication Ports One PCI Express x4 Gen1 socket Two FPGA mezzanine card (FMC) ports One USB 2.0 on-the-go (OTG) port One Gigabit Ethernet port Two 10/100 Ethernet ports Two SFP+ ports Two RS-232 UART (through the mini-USB port) One real-time clock April 2014 Altera Corporation Chapter 1: Overview Board Component Blocks 1-3 General user input/output Altera Corporation Eight user LEDs One configuration load LED One configuration done LED One error LED Three configuration select LEDs Four on-board USB-Blaster II status LEDs Two FMC interface LEDs Two UART data transmit and receive LEDs One power on LED One two-line character LCD display Push buttons One CPU reset push button One MAX V reset push button One program select push button One program configuration push button Eight general user push buttons DIP switches One JTAG chain control DIP switch One board settings DIP switch One FPGA configuration mode DIP switch One general user DIP switch 14-20-V (laptop) DC input Mechanical April 2014 Power supply LEDs and displays 7.175" x 9" rectangular form factor Arria V SoC Development Board Reference Manual 1-4 Chapter 1: Overview Development Board Block Diagram Development Board Block Diagram Figure 1-1 shows a block diagram of the Arria V SoC development board. Figure 1-1. Arria V SoC Development Board Block Diagram USB-Blaster II USB 2.0 DDR3 1GB 533 MHz (x32) DDR3 1GB 533 MHz (x32) MAX II CPLD Mictor Connector JTAG JTAG HMC HMC DDR3 1GB 533 MHz + ECC QSPI Flash 256 MB HMC Clock Cleaner Micro SD Card 10/100 Dual Ethernet PHY 10/100/1000 Ethernet PHY FPGA Jitter Clean Up HPS USB 2.0 OTG PHY SFP+ x2 UART to USB FMC x2 UART to USB PCIe Gen2 x4 I2C Serial EPROM MAX V CPLD RTC Parallel Configuration Flash Buttons Switches LEDs Buttons Switches LEDs CSEL BSEL MAC Address Storage 2x16 Character LCD Power Management Measurement Handling the Board When handling the board, it is important to observe the following static discharge precaution: c Without proper anti-static handling, the board can be damaged. Therefore, use anti-static handling precautions when touching the board. Arria V SoC Development Board Reference Manual April 2014 Altera Corporation 2. Board Components This chapter introduces the major components on the Arria V SoC development board. Figure 2-1 illustrates the component locations and Table 2-1 provides a brief description of all component features of the board. 1 A complete set of schematics, a physical layout database, and fabrication files for the development board reside in the Arria V SoC development kit board design files directory. f For information about powering up the board and installing the demonstration software, refer to the Arria V SoC Development Kit User Guide. This chapter consists of the following sections: April 2014 "Board Overview" "Featured Device: Arria V SoC" on page 2-5 "MAX V CPLD 5M2210 System Controller" on page 2-5 "FPGA Configuration" on page 2-10 "General User Input/Output" on page 2-19 "Clock Circuitry" on page 2-21 "Components and Interfaces" on page 2-23 "Memory" on page 2-39 "Power Supply" on page 2-53 Altera Corporation Arria V SoC Development Board Reference Manual 2-2 Chapter 2: Board Components Board Overview Board Overview This section provides an overview of the Arria V SoC development board, including an annotated board image and component descriptions. Figure 2-1 shows an overview of the board features. Figure 2-1. Overview of the Arria V SoC Development Board Table 2-1 describes the components and lists their corresponding board references. Table 2-1. Board Components (Part 1 of 3) Board Reference Type Description Featured Devices U41 FPGA Arria V SoC, 5ASTFD5K3F40I3, 1517-pin FBGA. U27 CPLD MAX V CPLD, 5M2210ZF256, 256-pin FBGA. Configuration, Status, and Setup Elements Provides access to the JTAG chain and disables the On-board USB-Blaster II when using an external USB-Blaster cable. J35 JTAG chain header SW4 JTAG chain control DIP switch Remove or include devices in the active JTAG chain. J50 Mini-USB header Arria V SoC Development Board Reference Manual USB interface for FPGA programming and debugging through the Onboard USB-Blaster II JTAG via a type-B USB cable. April 2014 Altera Corporation Chapter 2: Board Components Board Overview 2-3 Table 2-1. Board Components (Part 2 of 3) Board Reference Type Description SW2 Board settings DIP switch Controls the MAX V CPLD 5M2210 System Controller functions such as clock enable, SMA clock input control, and which image to load from flash memory at power-up. SW3 MSEL DIP switch Controls the configuration scheme on the board. MSEL pins 0, 1, 2, 3, and 4 connects to the DIP switch. S13 Program select push button Toggles the program select LEDs, which selects the program image that loads from flash memory to the FPGA. S12 Configure push button Load image from flash memory to the FPGA based on the settings of the program select LEDs. D38 Configuration done LED Illuminates when the FPGA is configured. D40 Load LED Illuminates when the MAX V CPLD 5M2210 System Controller is actively configuring the FPGA. D39 Error LED Illuminates when the FPGA configuration from flash memory fails. D37 Power LED Illuminates when 5.0-V power is present. D35, D36 JTAG TX/RX LEDs Indicate the transmit or receive activity of the JTAG chain. The TX and RX LEDs would flicker if the link is in use and active. The LEDs are either off when not in use or on when in use but idle. D41-D43 Program select LEDs Illuminates to show which flash memory image loads to the FPGA when you press the program select push button. Refer to Table 2-5 for the LED settings. D8, D20 FMC port present LEDs Illuminates when a daughter card is plugged into the FMC port. D21-D24 UART LEDs Illuminates when UART transmitter and receiver are in use. X2 Programmable oscillator Si570 programmable oscillator with a default frequency of 100 MHz. The frequency is programmable using the clock control GUI running on the MAX V CPLD 5M2210 System Controller. X3 148.5-MHz oscillator Si571 programmable oscillator with a default frequency of 148.5 MHz. The frequency is programmable using the clock control GUI running on the MAX V CPLD 5M2210 System Controller. X4 50-MHz oscillator 50.000-MHz crystal oscillator for general purpose logic. X5 125-MHz oscillator 125.000-MHz crystal oscillator for general purpose logic. J15 Clock input SMA connector Drive LVCMOS-compatible clock input into the dedicated clock pin. J49 HPS SMA clock Drive LVCMOS to HPS clock multiplexer. U35 Multi-output oscillator Si5338A quad-output fixed oscillator with 25M, 25M, 100M, and 100M outputs. Clock Circuitry General User Input/Output D9-D16 User LEDs Four user LEDs and four HPS LEDs. Illuminates when driven low. SW1 User DIP switch User DIP switch. When the switch is ON, a logic 0 is selected. S14 CPU reset push button Reset the FPGA logic. S11 MAX V reset push button Reset the MAX V CPLD 5M2210 System Controller. S1-S8 General user push buttons Four user push buttons and four HPS push buttons. Driven low when pressed. April 2014 Altera Corporation Arria V SoC Development Board Reference Manual 2-4 Chapter 2: Board Components Board Overview Table 2-1. Board Components (Part 3 of 3) Board Reference Type Description Memory Devices U29, U37, U43, U49, DDR3 SDRAM Four 128-MB DDR3 SDRAM with a 16-bit data bus for the FPGA and three 128-MB DDR3 SDRAM with a 16-bit data plus ECC bus for the HPS. U19 QSPI flash 1-Gb serial NOR flash with 4-bit data bus. U28 EPCQ flash U13 Synchronous flash 128-Mb synchronous flash devices with a 16-bit data bus for non-volatile memory. U31 I2C EEPROM 32-Kb I2C serial EEPROM. U38, U44, U51 Communication Ports J42 PCI Express socket PCI Express Gen1 x4 socket. J4, J26 FMC port Two FMC ports J43, J44 SFP+ port Two SFP+ ports U7, J13 Gigabit Ethernet port RJ-45 connectors which provides a 10/100/1000 Ethernet connection via a Micrel KSZ9021RN PHY and the FPGA-based Altera Triple Speed Ethernet MegaCore function in RGMII mode (for HPS). U55, J47, J48 Dual Ethernet port RJ-45 connector which provides a 10/100 Ethernet connection via a Renesas uPD60620 PHY in MII mode (for FPGA). USB-UART ports USB connector with USB-to-UART bridge for serial UART interface. J1, U4 USB OTG port USB 2.0 on-the-go interface. U11 Real-time clock DS1339 device with built-in power sense circuit that detects power failures and automatically switches to backup battery supply, maintaining time. J5 Micro SD card socket Micro SD card interface with 4-bit data line. J22, U25 J27, U36 Video and Display Ports Character LCD Connector that interfaces to a provided 16 character x 2 line LCD module along with two standoffs. J34 DC input jack Accepts 16-V DC power supply. SW5 Power switch Switch to power on or off the board when power is supplied from the DC input jack. J29 Power Supply Arria V SoC Development Board Reference Manual April 2014 Altera Corporation Chapter 2: Board Components Featured Device: Arria V SoC 2-5 Featured Device: Arria V SoC The Arria V SoC development board features a Arria V SoC 5ASTFD5K3F40I3 device (U41) that includes a hard processor system (HPS) with integrated ARM(R) CortexTMA9 MPCore processor. f For more information about Arria V device family, refer to the Arria V Device Handbook. Table 2-2 describes the features of the Arria V SoC device. Table 2-2. Arria V SoC Features Resource 5ASTFD5K3F40I3 LE (K) 462 ALM 174,340 Register Memory (Kb) 697,360 M10K 22,820 MLAB 2,658 18-bit x 18-bit Multiplier PLLs Transceivers 2,180 FPGA 14 HPS 3 6 Gbps 30 10 Gbps 16 I/O Resources The Arria V SoC 5ASTFD5K3F40I3 device has 540 general purpose FPGA I/O pins and 210 general purpose HPS I/O pins. MAX V CPLD 5M2210 System Controller The board utilizes the 5M2210ZF256 System Controller, an Altera MAX V CPLD, for the following purposes: April 2014 FPGA configuration from flash Power measurement Control and status registers (CSR) for remote system update Altera Corporation Arria V SoC Development Board Reference Manual 2-6 Chapter 2: Board Components MAX V CPLD 5M2210 System Controller Figure 2-2 illustrates the MAX V CPLD 5M2210 System Controller's functionality and external circuit connections as a block diagram. Figure 2-2. MAX V CPLD 5M2210 System Controller Block Diagram MAX V CPLD System Controller PC JTAG Control Embedded USB-Blaster II Information Register SLD-HUB SPI Bus FPGA Control Register Virtual-JTAG Encoder Decoder GPIO PFL LTC 2978 Power Controllers Si570, Si571, Si5338 Programmable Oscillator Oscillator Controller I2C Controller Table 2-3 lists the I/O signals present on the MAX V CPLD System Controller. The signal names and functions are relative to the MAX V device. Table 2-3. MAX V CPLD System Controller Device Pin-Out (Part 1 of 5) Board Reference (U27) Schematic Signal Name I/O Standard Description B9 CLK125A_EN 2.5-V 125 MHz oscillator enable E9 CLK50_EN 2.5-V 50 MHz oscillator enable J5 CLK_100M_MAX 2.5-V 100 MHz clock input J12 CLK_50M_MAX 1.8-V 50 MHz clock input D10 CPU_RESETN 2.5-V FPGA reset push button N11 EXTRA_SIG0 1.5-V On-board USB-Blaster II interface. Reserved for future use T13 EXTRA_SIG1 1.5-V On-board USB-Blaster II interface. Reserved for future use T15 EXTRA_SIG2 1.5-V On-board USB-Blaster II interface. Reserved for future use A2 FACTORY_LOAD 2.5-V DIP switch to load factory or user design at power-up R14 FACTORY_REQUEST 1.5-V On-board USB-Blaster II request to send FACTORY command N12 FACTORY_STATUS 1.5-V On-board USB-Blaster II FACTORY command status F11 FLASH_ADVN 1.8-V FSM bus flash memory address valid N14 FLASH_CEN0 1.8-V FSM bus flash memory chip enable D14 FLASH_CLK 1.8-V FSM bus flash memory clock P15 FLASH_OEN 1.8-V FSM bus flash memory output enable P14 FLASH_RDYBSYN 1.8-V FSM bus flash memory ready D13 FLASH_RESETN 1.8-V FSM bus flash memory reset N15 FLASH_WEN 1.8-V FSM bus flash memory write enable E14 FM_A0 1.8-V FM address bus Arria V SoC Development Board Reference Manual April 2014 Altera Corporation Chapter 2: Board Components MAX V CPLD 5M2210 System Controller 2-7 Table 2-3. MAX V CPLD System Controller Device Pin-Out (Part 2 of 5) Board Reference (U27) Schematic Signal Name I/O Standard Description C14 FM_A1 1.8-V FM address bus C15 FM_A2 1.8-V FM address bus E13 FM_A3 1.8-V FM address bus E12 FM_A4 1.8-V FM address bus D15 FM_A5 1.8-V FM address bus F14 FM_A6 1.8-V FM address bus D16 FM_A7 1.8-V FM address bus F13 FM_A8 1.8-V FM address bus E15 FM_A9 1.8-V FM address bus E16 FM_A10 1.8-V FM address bus F15 FM_A11 1.8-V FM address bus G14 FM_A12 1.8-V FM address bus F16 FM_A13 1.8-V FM address bus G13 FM_A14 1.8-V FM address bus G15 FM_A15 1.8-V FM address bus G12 FM_A16 1.8-V FM address bus G16 FM_A17 1.8-V FM address bus H14 FM_A18 1.8-V FM address bus H15 FM_A19 1.8-V FM address bus H13 FM_A20 1.8-V FM address bus H16 FM_A21 1.8-V FM address bus J13 FM_A22 1.8-V FM address bus J16 FM_A23 1.8-V FM address bus K12 FM_A24 1.8-V FM address bus M14 FM_A25 1.8-V FM address bus N13 FM_A26 1.8-V FM address bus J14 FM_D0 1.8-V FM data bus J15 FM_D1 1.8-V FM data bus K16 FM_D2 1.8-V FM data bus K13 FM_D3 1.8-V FM data bus K15 FM_D4 1.8-V FM data bus K14 FM_D5 1.8-V FM data bus L16 FM_D6 1.8-V FM data bus L11 FM_D7 1.8-V FM data bus L15 FM_D8 1.8-V FM data bus L12 FM_D9 1.8-V FM data bus M16 FM_D10 1.8-V FM data bus L13 FM_D11 1.8-V FM data bus M15 FM_D12 1.8-V FM data bus April 2014 Altera Corporation Arria V SoC Development Board Reference Manual 2-8 Chapter 2: Board Components MAX V CPLD 5M2210 System Controller Table 2-3. MAX V CPLD System Controller Device Pin-Out (Part 3 of 5) Board Reference (U27) Schematic Signal Name I/O Standard Description L14 FM_D13 1.8-V FM data bus N16 FM_D14 1.8-V FM data bus M13 FM_D15 1.8-V FM data bus M3 FMC_C2M_PG 2.5-V FMC port A power good output N2 FMCB_C2M_PG 2.5-V FMC port B power good output K1 FPGA_CONF_DONE 2.5-V FPGA configuration done LED D3 FPGA_CONFIG_D0 2.5-V FPGA configuration data C2 FPGA_CONFIG_D1 2.5-V FPGA configuration data C3 FPGA_CONFIG_D2 2.5-V FPGA configuration data E3 FPGA_CONFIG_D3 2.5-V FPGA configuration data D2 FPGA_CONFIG_D4 2.5-V FPGA configuration data E4 FPGA_CONFIG_D5 2.5-V FPGA configuration data D1 FPGA_CONFIG_D6 2.5-V FPGA configuration data E5 FPGA_CONFIG_D7 2.5-V FPGA configuration data F3 FPGA_CONFIG_D8 2.5-V FPGA configuration data E1 FPGA_CONFIG_D9 2.5-V FPGA configuration data F4 FPGA_CONFIG_D10 2.5-V FPGA configuration data F2 FPGA_CONFIG_D11 2.5-V FPGA configuration data F1 FPGA_CONFIG_D12 2.5-V FPGA configuration data F6 FPGA_CONFIG_D13 2.5-V FPGA configuration data G2 FPGA_CONFIG_D14 2.5-V FPGA configuration data G3 FPGA_CONFIG_D15 2.5-V FPGA configuration data N3 FPGA_CVP_CONFDONE 2.5-V FPGA Configuration via Protocol (CvP) done J3 FPGA_DCLK 2.5-V FPGA configuration clock N1 FPGA_NCONFIG 2.5-V FPGA configuration active J4 FPGA_NSTATUS 2.5-V FPGA configuration ready H1 FPGA_PR_DONE 2.5-V FPGA partial reconfiguration done P2 FPGA_PR_ERROR 2.5-V FPGA partial reconfiguration error E2 FPGA_PR_READY 2.5-V FPGA partial reconfiguration ready F5 FPGA_PR_REQUEST 2.5-V FPGA partial reconfiguration request B11 HPS_RESETN 2.5-V HPS reset push button M1 I2C_SCL_MAX 2.5-V Programmable oscillator I2C clock M2 I2C_SDA_MAX 2.5-V Programmable oscillator I2C data L6 JTAG_MAX_TDI 2.5-V JTAG chain data in M5 JTAG_MAX_TDO 2.5-V JTAG chain data out N4 JTAG_MAX_TMS 2.5-V JTAG chain mode P3 JTAG_MUX_TCK 2.5-V JTAG chain clock P11 M570_CLOCK 1.5-V 25-MHz clock to on-board USB-Blaster II for sending FACTORY command Arria V SoC Development Board Reference Manual April 2014 Altera Corporation Chapter 2: Board Components MAX V CPLD 5M2210 System Controller 2-9 Table 2-3. MAX V CPLD System Controller Device Pin-Out (Part 4 of 5) Board Reference (U27) Schematic Signal Name I/O Standard Description L5 M570_PCIE_JTAG_EN 2.5-V PCI Express JTAG enable for the on-board USB-Blaster II H2 MAX_AS_CONF 2.5-V Driven low to enable AS configuration from the EPCQ flash through U13 to the FPGA E11 MAX_CONF_DONE 2.5-V On-board USB-Blaster II configuration done LED A4 MAX_ERROR 2.5-V FPGA configuration error LED G4 MAX_FPGA_MISO 2.5-V FPGA to MAX V SPI bus data output G1 MAX_FPGA_MOSI 2.5-V FPGA to MAX V SPI bus data input H3 MAX_FPGA_SCK 2.5-V FPGA to MAX V SPI bus clock G5 MAX_FPGA_SSEL 2.5-V FPGA to MAX V SPI bus slave select A6 MAX_LOAD 2.5-V FPGA configuration active LED K2 MAX_QSPI_RSTN 2.5-V QSPI reset M9 MAX_RESETN 2.5-V MAX V reset push button B10 MSEL0 2.5-V FPGA MSEL0 setting B3 MSEL1 2.5-V FPGA MSEL1 setting C10 MSEL2 2.5-V FPGA MSEL2 setting C12 MSEL3 2.5-V FPGA MSEL3 setting C6 MSEL4 2.5-V FPGA MSEL4 setting E10 OVERTEMP 2.5-V Temperature monitor fan enable D12 PGM_CONFIG 2.5-V Load the flash memory image identified by the PGM LEDs B14 PGM_LED0 2.5-V Flash memory PGM select indicator 0 C13 PGM_LED1 2.5-V Flash memory PGM select indicator 1 B16 PGM_LED2 2.5-V Flash memory PGM select indicator 2 B13 PGM_SEL 2.5-V Toggles the PGM_LED[2:0] LED sequence P13 RST 1.5-V Reset input R12 SECURITY_MODE 1.5-V DIP switch for the On-board USB-Blaster II to send FACTORY command at power up A10 SI570_EN 2.5-V Si570 programmable clock enable D4 SI571_EN 2.5-V Si571 programmable clock enable R16 TRST 1.5-V Reset output H5 USB_B2_CLK 2.5-V On-board USB-Blaster II interface clock R4 USB_CFG0 1.5-V On-board USB-Blaster II interface (reserved for future use) T4 USB_CFG1 1.5-V On-board USB-Blaster II interface (reserved for future use) P8 USB_CFG2 1.5-V On-board USB-Blaster II interface (reserved for future use) T7 USB_CFG3 1.5-V On-board USB-Blaster II interface (reserved for future use) N8 USB_CFG4 1.5-V On-board USB-Blaster II interface (reserved for future use) R8 USB_CFG5 1.5-V On-board USB-Blaster II interface (reserved for future use) T8 USB_CFG6 1.5-V On-board USB-Blaster II interface (reserved for future use) T9 USB_CFG7 1.5-V On-board USB-Blaster II interface (reserved for future use) R9 USB_CFG8 1.5-V On-board USB-Blaster II interface (reserved for future use) April 2014 Altera Corporation Arria V SoC Development Board Reference Manual 2-10 Chapter 2: Board Components FPGA Configuration Table 2-3. MAX V CPLD System Controller Device Pin-Out (Part 5 of 5) Board Reference (U27) Schematic Signal Name I/O Standard Description P9 USB_CFG9 1.5-V On-board USB-Blaster II interface (reserved for future use) M8 USB_CFG10 1.5-V On-board USB-Blaster II interface (reserved for future use) T10 USB_CFG11 1.5-V On-board USB-Blaster II interface (reserved for future use) A13 USB_FPGA_RESET 2.5-V On-board USB-Blaster II interface FPGA reset A11 USB_RESET 2.5-V On-board USB-Blaster II interface reset FPGA Configuration This section describes the FPGA, flash memory, and MAX V CPLD 5M2210 System Controller device programming methods supported by the Arria V SoC development board. The Arria V SoC development board supports the following configuration methods: JTAG On-board USB-Blaster II is the default method for configuring the FPGA using the Quartus II Programmer in JTAG mode with the supplied USB cable. External Mictor connector for configuring the HPS using the ARM DS-5 Altera Edition software and DSTREAM or Lauterbach cables. External USB-Blaster for configuring the FPGA when you connect the external USB-Blaster to the JTAG header (J35). Flash memory download for configuring the FPGA using stored images from the flash memory on either power-up or pressing the configure push button (S12). FPGA Programming over On-Board USB-Blaster II This configuration method implements a mini-USB connector (J50), a USB 2.0 PHY device (U61), and an Altera MAX II CPLD EPM570GF100I5N (U56) to allow FPGA configuration using a USB cable. This USB cable connects directly between the USB connector on the board and a USB port on a PC running the Quartus II software. The on-board USB-Blaster II in the MAX II CPLD EPM570GF100I5N normally masters the JTAG chain. The on-board USB-Blaster II shares the pins with the external header. and is automatically disabled when you connect an external USB-Blaster to the JTAG chain through the JTAG header (J35). In addition to JTAG interface, the on-board USBBlaster II has trace capabilities for HPS debug purposes. The trace interface from the HPS routes to the on-board USB-Blaster II connection pins through the FPGA. Arria V SoC Development Board Reference Manual April 2014 Altera Corporation Chapter 2: Board Components FPGA Configuration 2-11 Figure 2-3 illustrates the JTAG chain. Figure 2-3. JTAG Chain Trace TRST Cypress On-Board USB-Blaster II TRST Disable Mictor-38 Header 10-Pin JTAG Header TCK TMS TDI TDO TCK TMS TDI TDO TCK TMS TDI TDO Trace 2.5 V TCK TMS TDI TDO 1 TRST Arria V ST HPS 2.5 V TCK TMS TDI TDO 1 TRST Arria V ST FPGA TCK TMS TDI TDO 1 FMC Port A FMC Port B 1 TCK TMS TDI TDO MAX V CPLD 5M2210 System Controller Flash Memory The JTAG chain control DIP switch (SW4) controls the jumpers shown in Figure 2-3. To connect a device or interface to the chain, their corresponding switch must be in the OFF position. Slide all the switches in the ON position to only have the FPGA in the chain. 1 April 2014 The MAX V CPLD 5M2210 System Controller must be in the JTAG chain to use some of the GUI interfaces. Altera Corporation Arria V SoC Development Board Reference Manual 2-12 Chapter 2: Board Components FPGA Configuration The MAX II CPLD (EPM570GF100) is dedicated to the on-board USB-Blaster II functionality only, connecting to the USB 2.0 PHY device on one side and drives JTAG signals out the other side on the GPIO pins. This device's own dedicated JTAG interface are routed to a small surface-mount header only intended for debugging of first article prototypes. A USB 2.0 Cypress EZ-USB CY7C68013A device (U61) in a 56-pin VBGA package interfaces to a mini-USB connector. Table 2-4 lists the USB 2.0 PHY schematic signal names and their corresponding MAX II CPLD pin numbers. Table 2-4. USB 2.0 PHY Schematic Signal Names and Functions (Part 1 of 2) Board Reference (U61) Schematic Signal Name MAX II CPLD Pin Number I/O Standard Description C1 24M_XTALIN -- 3.3-V Crystal oscillator input C2 24M_XTALOUT -- 3.3-V Crystal oscillator output E1 FX2_D_N -- 3.3-V USB 2.0 PHY data E2 FX2_D_P -- 3.3-V USB 2.0 PHY data H7 FX2_FLAGA D1 3.3-V Slave FIFO output status G7 FX2_FLAGB G1 3.3-V Slave FIFO output status H8 FX2_FLAGC C1 3.3-V Slave FIFO output status G6 FX2_PA1 G3 3.3-V USB 2.0 PHY port A interface F8 FX2_PA2 B1 3.3-V USB 2.0 PHY port A interface F7 FX2_PA3 D2 3.3-V USB 2.0 PHY port A interface F6 FX2_PA4 D3 3.3-V USB 2.0 PHY port A interface C8 FX2_PA5 K4 3.3-V USB 2.0 PHY port A interface C7 FX2_PA6 F2 3.3-V USB 2.0 PHY port A interface C6 FX2_PA7 C2 3.3-V USB 2.0 PHY port A interface H3 FX2_PB0 G2 3.3-V USB 2.0 PHY port B interface F4 FX2_PB1 H8 3.3-V USB 2.0 PHY port B interface H4 FX2_PB2 F3 3.3-V USB 2.0 PHY port B interface G4 FX2_PB3 J3 3.3-V USB 2.0 PHY port B interface H5 FX2_PB4 F1 3.3-V USB 2.0 PHY port B interface G5 FX2_PB5 H1 3.3-V USB 2.0 PHY port B interface F5 FX2_PB6 H7 3.3-V USB 2.0 PHY port B interface H6 FX2_PB7 E1 3.3-V USB 2.0 PHY port B interface A8 FX2_PD0 H3 3.3-V USB 2.0 PHY port D interface A7 FX2_PD1 H2 3.3-V USB 2.0 PHY port D interface B6 FX2_PD2 J2 3.3-V USB 2.0 PHY port D interface A6 FX2_PD3 J1 3.3-V USB 2.0 PHY port D interface B3 FX2_PD4 J6 3.3-V USB 2.0 PHY port D interface A3 FX2_PD5 K3 3.3-V USB 2.0 PHY port D interface C3 FX2_PD6 J5 3.3-V USB 2.0 PHY port D interface A2 FX2_PD7 K2 3.3-V USB 2.0 PHY port D interface Arria V SoC Development Board Reference Manual April 2014 Altera Corporation Chapter 2: Board Components FPGA Configuration 2-13 Table 2-4. USB 2.0 PHY Schematic Signal Names and Functions (Part 2 of 2) Board Reference (U61) Schematic Signal Name MAX II CPLD Pin Number I/O Standard Description B8 FX2_RESETN K9 3.3-V On-board USB-Blaster hard reset F3 FX2_SCL J4 3.3-V USB 2.0 PHY serial clock G3 FX2_SDA -- 3.3-V USB 2.0 PHY serial data A1 FX2_SLRDN K1 3.3-V Read strobe for slave FIFO B1 FX2_SLWRN J9 3.3-V Write strobe for slave FIFO B7 FX2_WAKEUP -- 3.3-V USB 2.0 PHY wake signal G2 USB_B2_CLK E2 3.3-V USB 2.0 PHY 48-MHz interface clock FPGA Programming from Flash Memory Flash memory programming is possible through a variety of methods. The default method is to use the factory design--Golden Hardware Reference Design. This design contains an on-board webserver, which serves the Board Update Portal (BUP) web application. The web page allows you to link to SoC-related web pages and to control some user I/O and LCD on the development board. On either power-up or by pressing the program configuration push button, PGM_CONFIG (S12), the MAX V CPLD 5M2210 System Controller's PFL configures the FPGA from the flash memory. The PFL megafunction reads 16-bit data from the flash memory and converts it to fast passive parallel (FPP) format. This 16-bit data is then written to the dedicated configuration pins in the FPGA during configuration. Pressing the PGM_CONFIG push button (S12) loads the FPGA with a hardware page based on which PGM_LED[2:0] (D41, D42, D43) illuminates. Table 2-5 lists the design that loads when you press the PGM_CONFIG push button. Table 2-5. PGM_LED Settings (1) PGM_LED0 (D43) PGM_LED1 (D42) PGM_LED2 (D41) Design ON OFF OFF Factory hardware OFF ON OFF User hardware 1 OFF OFF ON User hardware 2 Note to Table 2-5: (1) ON indicates a setting of '0' while OFF indicates a setting of '1'. A EPCQ device is used for FPGA configuration in Active Serial (AS) mode on powerup. The EPCQ device with non-volatile memory features a simple six-pin interface and a small form factor. The EPCQ supports AS x1 and x4 modes. By default, this board has a FPP configuration scheme setting. The MAX_AS_CONF pin needs to be driven from the MAX V CPLD to enable the bus switch to isolate the EPCQ flash (U28) from the configuration bus. This happens when the MSEL is 10010 or 10011. April 2014 Altera Corporation Arria V SoC Development Board Reference Manual 2-14 Chapter 2: Board Components FPGA Configuration In AS configuration scheme, the data is read from the EPCQ flash and directly sent to the FPGA. The MAX V CPLD 5M2210 System Controller controls the nCS line of the EPCQ to avoid line contention on the data line due to functionality sharing. In order to program non-volatile memory, CFI Flash or EPCQ special programming functionality design should be loaded into the FPGA or MAX V CPLD to allow programming using the Quartus II Programmer. Figure 2-4 shows the PFL configuration. Figure 2-4. PFL Configuration 2.5 V 2.5 V 2.5 V 2.5 V 56.2 56.2 MAX V CPLD 5M2210 System Controller 100 10 k 50 MHz MAX_ERROR FACTORY DIP Switch USB_BLASTER CLK_SEL CLK_ENABLE USER_PGM USB_SELECT CONFIG_RESETn HPS_RESET PGM_SEL 2.5 V 56.2 PGM_LED0 MSEL[4:0] and BOOTSEL[3:0] also connects to the MAX V CPLD Arria V SoC FPGA MAX_LOAD FPGA_CVP_DONE FPGA_INIT_DONE FPGA_nSTATUS FPGA_nCONFIG FPGA_CONF_DONE 100 MHz CVP_CONFDONE INIT_DONE nSTATUS nCONFIG CONF_DONE nCE CVP_CONF_DONE CONF_DONE FPGA_DATA [3:0] FPGA_DATA [4] FPGA_DATA [7:5] FPGA_DCLK PS PORT DATA [3:0] DATA [4] DATA [7:5] DCLK EPCQ_nCS FLASH_A [25:1] FLASH_D [15:0] FLASH_CEn MSEL4 MSEL3 MSEL2 MSEL1 DIP Switch BOOTSEL0 BOOTSEL1 BOOTSEL2 DIP Switch EPCQ DATA [3:0] DCLK nCE FLASH_OEn FLASH_WEn FLASH_RYBSYn PGM_LED1 PGM_LED2 FLASH_CLK FLASH_RSTn FLASH_ADVn 2.5 V CFI Flash FLASH_A [25:0] FLASH_D [15:0] FLASH_CEn FLASH_OEn FLASH_WEn FLASH_RYBSYn FLASH_CLK FLASH_RESETn 10 k FLASH_WPn FLASH_ADVn 10 k f For more information on the following topics, refer to the respective documents: Board Update Portal, PFL design, and flash memory map storage, refer to the Arria V SoC Development Kit User Guide. PFL megafunction, refer to Parallel Flash Loader Megafunction User Guide. Arria V SoC Development Board Reference Manual April 2014 Altera Corporation Chapter 2: Board Components Status Elements 2-15 FPGA Programming over External USB-Blaster The JTAG chain header provides another method for configuring the FPGA using an external USB-Blaster device with the Quartus II Programmer running on a PC. To prevent contention between the JTAG masters, the on-board USB-Blaster is automatically disabled when you connect an external USB-Blaster to the JTAG chain through the JTAG chain header. Status Elements The development board includes status LEDs. This section describes the status elements. Table 2-6 lists the LED board references, names, and functional descriptions. Table 2-6. Board-Specific LEDs Board Reference Schematic Signal Name I/O Standard Description D37 Power 5.0-V Blue LED. Illuminates when 5.0 V power is active. D38 MAX_CONF_DONE 3.3-V Green LED. Illuminates when the FPGA is successfully configured. Driven by the MAX V CPLD 5M2210 System Controller. D39 MAX_ERROR 3.3-V Red LED. Illuminates when the MAX V CPLD 5M2210 System Controller fails to configure the FPGA. Driven by the MAX V CPLD 5M2210 System Controller. D40 MAX_LOAD 3.3-V Green LED. Illuminates when the MAX V CPLD 5M2210 System Controller is actively configuring the FPGA. Driven by the MAX V CPLD 5M2210 System Controller. D43 PGM_LED[0] D42 PGM_LED[1] 3.3-V D41 PGM_LED[2] Green LEDs. Illuminates to indicate which hardware page loads from flash memory when you press the PGM_SEL push button. 2.5-V Green LED. Illuminates when the FMC port has a board or cable plugged-in. Driven by the add-in card. 1.8-V Green LEDs. Illuminates to indicate USB-Blaster II receive and transmit activities. D20, D8 FMC_PRSNTn, FMCB_PRSNTn D35, D36 JTAG_RX, JTAG_TX D34, D33 SC_RX, SC_TX D21, D22 UARTA_RX_LED, UARTA_TX_LED 3.3-V Green LED. Illuminates to indicate UART port A receive and transmit activities. D23, D24 UARTB_RX_LED, UARTB_TX_LED 3.3-V Green LED. Illuminates to indicate UART port B receive and transmit activities. April 2014 Altera Corporation Arria V SoC Development Board Reference Manual 2-16 Chapter 2: Board Components Setup Elements Setup Elements The development board includes several different kinds of setup elements. This section describes the following setup elements: Board settings DIP switch JTAG chain control DIP switch FPGA configuration mode DIP switch HPS jumpers CPU reset push button MAX V reset push button Program configuration push button Program select push button f For more information about the default settings of the DIP switches, refer to the Arria V SoC Development Kit User Guide. Board Settings DIP Switch The board settings DIP switch (SW2) controls various features specific to the board and the MAX V CPLD 5M2210 System Controller logic design. Table 2-7 lists the switch controls and descriptions. Table 2-7. Board Settings DIP Switch Controls Switch Schematic Signal Name 1 CLK125A_EN 2 Si570_EN 3 FACTORY_LOAD Description ON: Enable 125 MHz on-board oscillator OFF: Disable 125 MHz on-board oscillator ON: Disable programmable oscillator OFF: Enable programmable oscillator ON: Load the factory design from flash on power-up 4 Arria V SoC Development Board Reference Manual SECURITY_MODE OFF: PFL disabled. Do not load any design from flash on power-up ON: On-board USB-Blaster II sends FACTORY command on power-up OFF: On-board USB-Blaster II will not send FACTORY command on power-up April 2014 Altera Corporation Chapter 2: Board Components Setup Elements 2-17 JTAG Chain Control DIP Switch The JTAG chain control DIP switch (SW4) either removes or includes devices in the active JTAG chain. Table 2-8 lists the switch controls and its descriptions. Table 2-8. JTAG Chain Control DIP Switch Switch Schematic Signal Name Description ON: Do not Include HPS in the JTAG chain. 1 HPS_JTAG_EN 2 FPGA_JTAG_EN 3 FMC_JTAG_EN 4 MAX_JTAG_EN OFF: Include HPS in the JTAG chain. ON: Do not Include the FPGA in the JTAG chain. OFF: Include the FPGA in the JTAG chain. ON: Do not include the FMCA connector in the JTAG chain. OFF: Include the FMCA connector in the JTAG chain. ON: Do not include the MAX V system controller in the JTAG chain. OFF: Include the MAX V system controller in the JTAG chain. FPGA Configuration Mode DIP Switch The FPGA configuration mode DIP switch (SW3) defines the mode to use to configure the FPGA. Table 2-9 lists the switch controls and its descriptions. All switches at the ON position will select the default FPP x16 mode. Table 2-9. FPGA Configuration Mode DIP Switch Switch April 2014 Altera Corporation Schematic Signal Name 1 MSEL0 2 MSEL1 3 MSEL2 4 MSEL3 5 MSEL4 Description ON: Select logic 0 OFF: Select logic 1 ON: Select logic 0 OFF: Select logic 1 ON: Select logic 0 OFF: Select logic 1 ON: Select logic 0 OFF: Select logic 1 ON: Select logic 0 OFF: Select logic 1 Arria V SoC Development Board Reference Manual 2-18 Chapter 2: Board Components Setup Elements HPS Jumpers The HPS jumpers define the bootstrap options for the HPS--boot source, mode, HPS clocks settings, power-on-reset (POR) mode and peripherals selection. Table 2-10 lists the jumper settings and its descriptions. Table 2-10. HPS Jumpers Board Reference Schematic Signal Name Description Selects the boot mode and source for the HPS. J39, J40, J41 HPS_BSEL[2:0] 0x1--FPGA 0x3--NAND flash (not supported on this board) 0x5--Micro SD card 0x7--QSPI flash All the other modes are reserved. J37, J38 HPS_CSEL[1:0] Selects the HPS clock settings. The actual clock settings are also dependent on the HPS_BSEL[2:0] selection. Selects the source of OSC2 clock. J45, J46 OSC2_CLK_SEL[1:0] 00--Select on-board clock generator. 01--Select external source via SMA connector. 10--Select 33 MHz on-board oscillator HPS in JTAG chain or only connect HPS to MICTOR. Selects the source to control the HPS. J19 JTAG_HPS_SEL ON: Select on-board USB-Blaster II as the JTAG master. OFF: Select MICTOR-based JTAG master, such as DSTREAM or Lauterbach programming cables. Also, sets SW4.1 to ON to remove the on-board USB Blaster II from driving the HPS JTAG input port in this mode. Selects the source of the JTAG chain. J21 JTAG_SEL ON: Select on-board USB-Blaster II as the source. OFF: Select MICTOR as the source. CPU Reset Push Button The CPU reset push button, CPU_RESETn (S4), is an input to the Arria V HPS pin and is an open-drain I/O from the MAX V CPLD System Controller. This push button is the default reset for both the HPS and CPLD logic. The MAX V CPLD 5M2210 also drives this push button during POR mode. MAX V Reset Push Button The MAX V reset push button, MAX_RESETn (S11), is an input to the MAX V CPLD 5M2210 System Controller. This push button is the default reset for the CPLD logic. Arria V SoC Development Board Reference Manual April 2014 Altera Corporation Chapter 2: Board Components General User Input/Output 2-19 Program Configuration Push Button The program configuration push button, PGM_CONFIG (S12), is an input to the MAX V CPLD 5M2210 System Controller. This input forces a FPGA reconfiguration from the flash memory. The location in the flash memory is based on the settings of PGM_LED[2:0], which is controlled by the program select push button, PGM_SEL (S13). Valid settings include PGM_LED0, PGM_LED1, or PGM_LED2 on the three pages in flash memory reserved for FPGA designs. Program Select Push Button The program select push button, PGM_SEL (S13), is an input to the MAX V CPLD System Controller. This push button toggles the PGM_LED[2:0]sequence that selects which location in the flash memory is used to configure the FPGA. Refer to Table 2-5 on page 2-13 for the PGM_LED[2:0] sequence definitions. General User Input/Output This section describes the user I/O interface to the FPGA, including the push buttons, DIP switches, LEDs, expansion header, and character LCD. User-Defined Push Buttons The development board includes eight user-defined push buttons. For information about the system and safe reset push buttons, refer to "Setup Elements" on page 2-16. Board references S1-S8 are push buttons for controlling the FPGA designs that loads into the Arria V SoC device. Push buttons S1-S4 connect to the FPGA while push buttons S5-S8 connect to the HPS. When you press and hold down the switch, the device pin is set to logic 0; when you release the switch, the device pin is set to logic 1. There are no board-specific functions for these general user push buttons. Table 2-11 lists the user-defined push button schematic signal names and their corresponding Arria V SoC pin numbers. Table 2-11. User-Defined Push Button Schematic Signal Names and Functions Board Reference April 2014 Altera Corporation Schematic Signal Name Arria V SoC Pin Number I/O Standard S4 USER_PB_FPGA0 AT23 1.5-V S3 USER_PB_FPGA1 AP24 1.5-V S2 USER_PB_FPGA2 AW24 1.5-V S1 USER_PB_FPGA3 AW23 1.5-V S8 USER_PB_HPS0 E15 2.5-V S7 USER_PB_HPS1 G16 2.5-V S6 USER_PB_HPS2 E16 2.5-V S5 USER_PB_HPS3 H16 2.5-V Arria V SoC Development Board Reference Manual 2-20 Chapter 2: Board Components General User Input/Output User-Defined DIP Switch Board reference SW1 is a eight-pin DIP switch. This switch is user-defined and provides additional FPGA or HPS input control. When the switch is in the OFF position, a logic 1 is selected. When the switch is in the ON position, a logic 0 is selected. There are no board-specific functions for this switch. Table 2-12 lists the user-defined DIP switch schematic signal names and their corresponding Arria V SoC pin numbers. Table 2-12. User-Defined DIP Switch Schematic Signal Names and Functions Board Reference Schematic Signal Name Arria V SoC Pin Number I/O Standard 1 USER_DIPSW_HPS0 L15 3.3-V 2 USER_DIPSW_HPS1 K15 3.3-V 3 USER_DIPSW_HPS2 K14 3.3-V 4 USER_DIPSW_HPS3 C15 3.3-V 5 USER_DIPSW_FPGA0 AL24 2.5-V 6 USER_DIPSW_FPGA1 AF24 2.5-V 7 USER_DIPSW_FPGA2 AE24 2.5-V 8 USER_DIPSW_FPGA3 AU23 2.5-V User-Defined LEDs Board references D1-D8 are eight user-defined LEDs. The status and debugging signals are driven to the LEDs from the FPGA or HPS designs loaded into the Arria V SoC. Driving a logic 0 on the I/O port turns the LED on while driving a logic 1 turns the LED off. There are no board-specific functions for these LEDs. Table 2-13 lists the general LED schematic signal names and their corresponding Arria V SoC pin numbers. Table 2-13. General LED Schematic Signal Names and Functions Board Reference Arria V SoC Development Board Reference Manual Schematic Signal Name Arria V SoC Pin Number I/O Standard D12 USER_LED_FPGA0 AH24 2.5-V D11 USER_LED_FPGA1 AU24 2.5-V D10 USER_LED_FPGA2 AT24 2.5-V D9 USER_LED_FPGA3 AD24 2.5-V D16 USER_LED_HPS0 R17 3.3-V D15 USER_LED_HPS1 F16 3.3-V D14 USER_LED_HPS2 R15 3.3-V D13 USER_LED_HPS3 C16 3.3-V April 2014 Altera Corporation Chapter 2: Board Components Clock Circuitry 2-21 Character LCD The development board includes a single 10-pin 0.1" pitch single-row header that interfaces to a 2 line x 16 character Lumex character LCD using standard I2C interface connected to the HPS. The character LCD has a two headers that mount directly to the board's 10-pin header, so it can be easily removed for access to components under the display. You can also use the header for debugging, I2C expansion, or other purposes. f For more information such as timing, character maps, interface guidelines, and other related documentation, visit www.newhavendisplay.com. Clock Circuitry This section describes the board's clock inputs and outputs. On-Board Oscillators Figure 2-5 shows the default frequencies of all external clocks going to the Arria V SoC development board. Figure 2-5. Arria V SoC Development Board Clocks FMCA CLK16-19pFMC Si571 FMCB CLK_OSC1 25 MHz 4 4 CLK20-23pFMCB Bank 8 HPS Peripherals REFCLKL2 HPS Core Arria V ST I3 Bank R1 REFCLKL3 FMCA Bank 2L REFCLKL4 Bank 1L 148.5 MHz/I2C HPS Memory Interface REFCLKL5 Si5338 25 MHz 33 MHz CLK_OSC2 SMA Si570 REFCLKR3 REFCLKR2 REFCLKL0 Bank R0 FMCB Bank 0L 100 MHz/I2C REFCLKL1 Si52112 REFCLKR0 100 MHz CLK11p SMA CLK8p SYSREF CLK10p 100 MHz CLK6p CLEAN_CLK CLK3p 50 MHz CLK1p 156.25 MHz SMA Bank 4 CLK4p CLK_ENET_FPGA 125 MHz LMK04828 Cleaner CLK2p CLK_ENET_PHY 25 MHz CLK0p 100 MHz Bank 3 PCIe Socket SMA 125 MHz Si5335 MAX V, 100 MHz Dual ENET PHY, 25 MHz SMA FMCA FMCB SL 18860C 125 MHz April 2014 Altera Corporation MAX V 50 MHz Arria V SoC Development Board Reference Manual 2-22 Chapter 2: Board Components Clock Circuitry Off-Board Input/Output Clock The development board has input and output clocks which can be driven onto the board. The output clocks can be programmed to different levels and I/O standards according to the FPGA device's specification. Table 2-14 lists the clock inputs for the development board. Table 2-14. Off-Board Clock Inputs Source Schematic Signal Name I/O Standard Arria V SoC Pin Number SMA SMA_CLKIN 2.5-V CMOS -- SMA OSC2_CLK_SMA 2.5-V CMOS -- FMC_CLK_M2C_P[1:0] LVDS B22, A22 FMC_CLK_M2C_N[1:0] LVDS C22, A21 FMC_LA_RX_CLK_P LVDS H21 FMC_LA_RX_CLK_N LVDS J21 FMC_LA_RX_P7 LVDS C20 FMC_LA_RX_N7 LVDS D20 FMC_GBTCLK_M2C_P[1:0] LVDS AC31, AA31 FMC_GBTCLK_M2C_N[1:0] LVDS AC32, AA32 FMCB_CLK_M2C_P[1:0] LVDS C34, G34 FMCB_CLK_M2C_N[1:0] LVDS D34, H34 FMCB_LA_RX_CLK_P LVDS E34 FMCB_LA_RX_CLK_N LVDS F34 FMCB_LA_RX_P7 LVDS N34 FMCB_LA_RX_N7 LVDS N33 FMCB_GBTCLK_M2C_P[1:0] LVDS AG32, AE31 FMCB_GBTCLK_M2C_N[1:0] LVDS AG33, AE32 FMC Port A FMC Port A FMC Port A FMC Port A FMC Port B FMC Port B FMC Port B FMC Port B Description Clock input to the global clock network. Multiplexed clock input to OSC2 of the HPS. LVDS input from the installed FMC card to global clock inputs. LVDS input from the installed FMC card to global clock inputs. LVDS input from the installed FMC card to global clock inputs. LVDS input from the installed FMC card to dedicated reference clock inputs. LVDS input from the installed FMC card to global clock inputs. LVDS input from the installed FMC card to global clock inputs. LVDS input from the installed FMC card to global clock inputs. LVDS input from the installed FMC card to dedicated reference clock inputs. Table 2-15 lists the clock outputs for the development board. Table 2-15. Off-Board Clock Outputs Source FMC Port A FMC Port B PCI Express Socket Schematic Signal Name I/O Standard Arria V SoC Pin Number FMC_LA_TX_CLK_P LVDS M23 FMC_LA_TX_CLK_N LVDS N23 FMCB_LA_TX_CLK_P LVDS L30 FMCB_LA_TX_CLK_N LVDS M30 PCIE_REFCLK_SYN_P HCSL AF8 PCIE_REFCLK_SYN_N HCSL AF7 Arria V SoC Development Board Reference Manual Description LVDS output. LVDS output. HCSL output to the PCI Express socket. April 2014 Altera Corporation Chapter 2: Board Components Components and Interfaces 2-23 Components and Interfaces This section describes the development board's communication ports and interface cards relative to the Arria V SoC device. The development board supports the following communication ports: PCI Express 10/100/1000 Ethernet (HPS) 10/100 Ethernet (FPGA) FMC RS-232 UART (HPS) Real-Time clock (HPS) SFP+ I2C interface PCI Express The PCI Express interface on the development board supports auto-negotiating channel width from x1 to x4 as well as the connection speed of Gen1 at 2.5 Gbps/lane for a maximum of 10 Gbps bandwidth. The PCIE_REFCLK_P/N signal is a 100-MHz differential input that is driven to the daughter card through the PCI Express edge connector. This signal connects directly to a Arria V SoC REFCLK input pin pair using DC coupling. The I/O standard is High-Speed Current Steering Logic (HCSL). Figure 2-6 shows the PCI Express reference clock levels. Figure 2-6. PCI Express Reference Clock Levels VMAX = 1.15 V REFCLK - VCROSS MAX = 550 mV VCROSS MIN = 250 mV REFCLK + VMIN = -0.30 V The PCI Express edge connector also has a presence detect feature for the motherboard to determine if a card is installed. A jumper is provided to optionally connect PRSNT1n to any of the three PRSNT2n pins found within the x4 connector definition. This is to address issues on some PC systems that would base the link-width capability on the presence detect pins versus a query operation. Table 2-16 summarizes the PCI Express pin assignments. The signal names and directions are relative to the Arria V SoC. April 2014 Altera Corporation Arria V SoC Development Board Reference Manual 2-24 Chapter 2: Board Components Components and Interfaces Table 2-16. PCI Express Pin Assignments, Schematic Signal Names, and Functions Board Reference (J42) Schematic Signal Name I/O Standard Arria V SoC Device Pin Number Description A11 PCIE_PERSTN LVTTL AK6 Reset B17 PCIE_PRSNT2N_X1 LVTTL AC22 Presence detect DIP switch B31 PCIE_PRSNT2N_X4 LVTTL AD21 Presence detect DIP switch A14 PCIE_REFCLK_SYN_N HCSL AF7 Motherboard reference clock A13 PCIE_REFCLK_SYN_P HCSL AF8 Motherboard reference clock B5 PCIE_SMCLK LVTTL AG20 SMB clock B6 PCIE_SMDAT LVTTL AG23 SMB data B11 PCIE_WAKEN LVTTL AL6 Wake signal A17 PCIE_RX_N0 1.5-V PCML AU2 Receive bus A22 PCIE_RX_N1 1.5-V PCML AR2 Receive bus A26 PCIE_RX_N2 1.5-V PCML AN2 Receive bus A30 PCIE_RX_N3 1.5-V PCML AL2 Receive bus A16 PCIE_RX_P0 1.5-V PCML AU1 Receive bus A21 PCIE_RX_P1 1.5-V PCML AR1 Receive bus A25 PCIE_RX_P2 1.5-V PCML AN1 Receive bus A29 PCIE_RX_P3 1.5-V PCML AL1 Receive bus B15 PCIE_TX_N0 1.5-V PCML AT4 Transmit bus B20 PCIE_TX_N1 1.5-V PCML AP4 Transmit bus B24 PCIE_TX_N2 1.5-V PCML AM4 Transmit bus B28 PCIE_TX_N3 1.5-V PCML AK4 Transmit bus B14 PCIE_TX_P0 1.5-V PCML AT3 Transmit bus B19 PCIE_TX_P1 1.5-V PCML AP3 Transmit bus B23 PCIE_TX_P2 1.5-V PCML AM3 Transmit bus B27 PCIE_TX_P3 1.5-V PCML AK3 Transmit bus Arria V SoC Development Board Reference Manual April 2014 Altera Corporation Chapter 2: Board Components Components and Interfaces 2-25 10/100/1000 Ethernet (HPS) The development board supports an RJ-45 10/100/1000 base-T Ethernet using an external Micrel KSZ9021RN PHY and the HPS EMAC function from the Altera Triple-Speed Ethernet MegaCore MAC function. The PHY-to-MAC interface employs RGMII connection using four data lines at 250 Mbps each for a connection speed of 1 Gbps. The Micrel KSZ9021RN PHY uses 2.5-V or 3.3-V power rails. The PHY interfaces to an RJ-45 model with internal magnetics that can be used for driving copper lines with Ethernet traffic. Figure 2-7 shows the RGMII interface between the HPS (MAC) and Micrel KSZ9021RN PHY. Figure 2-7. RGMII Interface between HPS (MAC) and PHY RGMII Mac Single-Port RGMII Micrel KSZ9021RN RJ-45 Table 2-17 lists the HPS Ethernet PHY interface pin assignments. Table 2-17. Ethernet PHY (HPS) Pin Assignments, Signal Names and Functions (Part 1 of 2) Board Reference (U7) Schematic Signal Name Arria V SoC Pin Number I/O Standard -- -- Clock out 125-MHz LED mode 125-MHz RGMII transmit clock Description 41 CLK125_NDO_LED_MODE 24 ENET_HPS_GTX_CLK D19 3.3-V CMOS 38 ENET_HPS_INTN A18 3.3-V CMOS Management bus interrupt 17 ENET_HPS_LED1_LINK -- 3.3-V CMOS Receive data active LED 15 ENET_HPS_LED2_LINK -- 3.3-V CMOS Transmit data active LED 36 ENET_HPS_MDC L18 3.3-V CMOS Management bus data clock 37 ENET_HPS_MDIO J18 3.3-V CMOS Management bus data 42 ENET_HPS_RESETN -- 3.3-V CMOS Device reset 48 ENET_HPS_RSET -- 3.3-V CMOS Device interrupt 35 ENET_HPS_RX_CLK G21 3.3-V CMOS RGMII receive clock 33 ENET_HPS_RX_DV H19 3.3-V CMOS RGMII receive data valid 32 ENET_HPS_RXD0 E19 3.3-V CMOS RGMII receive data bus 31 ENET_HPS_RXD1 M17 3.3-V CMOS RGMII receive data bus 28 ENET_HPS_RXD2 G20 3.3-V CMOS RGMII receive data bus 27 ENET_HPS_RXD3 G19 3.3-V CMOS RGMII receive data bus 25 ENET_HPS_TX_EN N18 3.3-V CMOS RGMII transmit enable 19 ENET_HPS_TXD0 H18 3.3-V CMOS RGMII transmit data bus 20 ENET_HPS_TXD1 F19 3.3-V CMOS RGMII transmit data bus April 2014 Altera Corporation Arria V SoC Development Board Reference Manual 2-26 Chapter 2: Board Components Components and Interfaces Table 2-17. Ethernet PHY (HPS) Pin Assignments, Signal Names and Functions (Part 2 of 2) Board Reference (U7) Schematic Signal Name Arria V SoC Pin Number I/O Standard Description 21 ENET_HPS_TXD2 K18 3.3-V CMOS RGMII transmit data bus 22 ENET_HPS_TXD3 M18 3.3-V CMOS RGMII transmit data bus 3 MDI_HPS_N0 -- 3.3-V CMOS Media dependent interface 6 MDI_HPS_N1 -- 3.3-V CMOS Media dependent interface 8 MDI_HPS_N2 -- 3.3-V CMOS Media dependent interface 11 MDI_HPS_N3 -- 3.3-V CMOS Media dependent interface 2 MDI_HPS_P0 -- 3.3-V CMOS Media dependent interface 5 MDI_HPS_P1 -- 3.3-V CMOS Media dependent interface 7 MDI_HPS_P2 -- 3.3-V CMOS Media dependent interface 10 MDI_HPS_P3 -- 3.3-V CMOS Media dependent interface The Micrel KSZ9021RN PHY uses a multi-level POR bootstrap encoding scheme to allow a small set of I/O pins (7) to set up a very large number of default settings within the device. The related I/O pins have integrated pull-up or pull-down resistors to configure the device. Table 2-18 lists the level encoding scheme. Table 2-18. Ethernet PHY (HPS) Bootstrap Encoding Scheme Board Reference (U7) Schematic Signal Name Description Strapping Option 17 ENET_HPS_LED1_LINK PHY address bit 0 Pulled low 15 ENET_HPS_LED2_LINK PHY address bit 1 Pulled low 32 ENET_HPS_RXD0 Mode 0 Pulled high 31 ENET_HPS_RXD1 Mode 1 Pulled high 28 ENET_HPS_RXD2 Mode 2 Pulled high 27 ENET_HPS_RXD3 Mode 3 Pulled high 35 ENET_HPS_RX_CLK PHY address bit 2 Pulled high 33 ENET_HPS_RX_DV Clock enable Pulled low 41 CLK125_NDO_LED_MODE Single LED mode Pulled high 10/100 Ethernet (FPGA) The development board supports an RJ-45 10/100 base-T Ethernet using an external Renesas uPD60620 PHY. This PHY supports EtherCAT, Ethernet IRT and DLR features using a third party MAC IP. The PHY-to-MAC interface employs MII connection using four data lines at 25 Mbps each for a connection speed of 100 Mbps. The PHY uses 3.3-V power rails and requires a 25 MHz reference clock to be driven from a dedicated oscillator. The PHY interfaces to a dual RJ-45 model with internal magnetics that can be used for driving copper lines with Ethernet traffic. Arria V SoC Development Board Reference Manual April 2014 Altera Corporation Chapter 2: Board Components Components and Interfaces 2-27 Figure 2-7 shows the MII interface between the FPGA (MAC) and Renesas uPD60620 PHY. Figure 2-8. MII Interface between FPGA (MAC) and PHY RJ-45 Dual-Port RGMII Renesas uPD60620 FPGA MII Mac RJ-45 Table 2-19 lists the Ethernet PHY interface pin assignments. Table 2-19. Ethernet PHY (FPGA) Pin Assignments, Signal Names and Functions (Part 1 of 2) Board Reference (U55) Schematic Signal Name Arria V SoC Pin Number I/O Standard Description 68 ENET1_ACT_LED -- 2.5-V Receive data active LED 69 ENET1_LINK_LED -- 2.5-V Transmit data active LED 18 ENET1_MDI_RX_N -- 2.5-V Media dependent interface 17 ENET1_MDI_RX_P -- 2.5-V Media dependent interface 16 ENET1_MDI_TX_N -- 2.5-V Media dependent interface 15 ENET1_MDI_TX_P -- 2.5-V Media dependent interface 59 ENET1_RX_CLK AE22 2.5-V MII receive clock 53 ENET1_RX_D0 AL23 2.5-V MII receive data bus 54 ENET1_RX_D1 AW22 2.5-V MII receive data bus 55 ENET1_RX_D2 AW21 2.5-V MII receive data bus 56 ENET1_RX_D3 AV21 2.5-V MII receive data bus 57 ENET1_RX_DV AF22 2.5-V MII receive data valid 58 ENET1_RX_ERROR AH23 2.5-V MII receive error 49 ENET1_TX_CLK_FB AN23 2.5-V 25-MHz MII transmit clock 43 ENET1_TX_D0 AU22 2.5-V MII transmit data bus 44 ENET1_TX_D1 AT22 2.5-V MII transmit data bus 45 ENET1_TX_D2 AE23 2.5-V MII transmit data bus 46 ENET1_TX_D3 AD22 2.5-V MII transmit data bus 48 ENET1_TX_EN AP23 2.5-V MII transmit enable 65 ENET2_ACT_LED -- 2.5-V Receive data active LED 67 ENET2_LINK_LED -- 2.5-V Transmit data active LED 4 ENET2_MDI_RX_N -- 2.5-V Media dependent interface 5 ENET2_MDI_RX_P -- 2.5-V Media dependent interface 6 ENET2_MDI_TX_N -- 2.5-V Media dependent interface April 2014 Altera Corporation Arria V SoC Development Board Reference Manual 2-28 Chapter 2: Board Components Components and Interfaces Table 2-19. Ethernet PHY (FPGA) Pin Assignments, Signal Names and Functions (Part 2 of 2) Board Reference (U55) Schematic Signal Name Arria V SoC Pin Number I/O Standard -- 2.5-V Media dependent interface Description 7 ENET2_MDI_TX_P 41 ENET2_RX_CLK AT20 2.5-V MII receive clock 35 ENET2_RX_D0 AW19 2.5-V MII receive data bus 36 ENET2_RX_D1 AL22 2.5-V MII receive data bus 37 ENET2_RX_D2 AH22 2.5-V MII receive data bus 38 ENET2_RX_D3 AU20 2.5-V MII receive data bus 39 ENET2_RX_DV AP20 2.5-V MII receive data valid 40 ENET2_RX_ERROR AN22 2.5-V MII receive error 29 ENET2_TX_CLK_FB AN21 2.5-V 25-MHz MII transmit clock 23 ENET2_TX_D0 AT21 2.5-V MII transmit data bus 24 ENET2_TX_D1 AR21 2.5-V MII transmit data bus 25 ENET2_TX_D2 AK21 2.5-V MII transmit data bus 26 ENET2_TX_D3 AP22 2.5-V MII transmit data bus 28 ENET2_TX_EN AW20 2.5-V MII transmit enable 1 ENET_DUAL_RESETN AV22 2.5-V Device reset 62 ENET_FPGA_MDC AG22 2.5-V Management bus data clock 63 ENET_FPGA_MDIO AK22 2.5-V Management bus data The PHY uses a multi-level POR bootstrap encoding scheme to allow a small set of I/O pins to set up a very large number of default settings within the device. The related I/O pins have integrated pull-up or pull-down resistors to configure the device. To change the configuration, connect an external resistor of maximum 5 k to the pin. Table 2-20 lists the level encoding scheme. Table 2-20. Ethernet PHY (FPGA) Bootstrap Encoding Scheme Board Reference (U55) Arria V SoC Development Board Reference Manual Schematic Signal Name Description Strapping Option 36 ENET2_RX_D1 Auto-negotiation disabled. 100 base-T default. Pulled low 35 ENET2_RX_D0 Full duplex operation Pulled high 41 ENET2_RX_CLK Disable quick auto negotiation Pulled low 58 ENET1_RX_ERROR MII mode operation Pulled low 59 ENET1_RX_CLK AUTOMDI-X enabled Pulled high 39 ENET2_RX_DV Transmit mode for PHY1 Pulled high 53 ENET1_RX_D0 Auto-negotiation disabled. 10 base-T default. Pulled low 53 ENET1_RX_D0 Address for SMI Pulled low 54 ENET1_RX_D1 Address for SMI Pulled low April 2014 Altera Corporation Chapter 2: Board Components Components and Interfaces 2-29 FMC The development board contains two high pin count (HPC) FPGA mezzanine card (FMC) ports that functions with a quadrature amplitude modulation (QAM) digitalto-analog converter (DAC) FMC module or daughter card. This pinout satisfies a QAM DAC that requires 58 LVDS data output pairs, one LVDS input clock pair, and three low-voltage differential signaling (LVDS) control pairs from the Arria V. These pins also have the option to be used as single-ended I/O pins. The VCCIO supply for FMC bank A in the low pin count (LPC) and HPC provide a variable voltage of 1.5 V, 1.8 V, 2.5 V (default), or 3.3 V. The VCCIO supply for FMC bank B in the HPC provides a variable voltage from 1.2 V to 3.3 V, which can be supplied by the FMC module. For device safety concerns, a jumper is available for you to connect this bank to the same VCCIO used for FMC bank A. This allows the VCCIO pins on the FPGA to be tied to a known power. The VCCIO pins also allows you the option to perform a manual check for the module's input voltage before connecting to the FPGA. This is to ensure that the module does not exceed the power supply maximum voltage rating. Table 2-21 lists the FMC port A pin assignments, signal names, and functions. Table 2-21. FMC Port A Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 5) Board Reference (J26) Schematic Signal Name Arria V SoC I/O Standard Pin Number Description D1 FMC_C2M_PG -- 2.5-V CMOS H4 FMC_CLK_M2C_P0 B22 LVDS Clock input 0 H5 FMC_CLK_M2C_N0 C22 LVDS Clock input 0 G2 FMC_CLK_M2C_P1 A22 LVDS Clock input 1 G3 FMC_CLK_M2C_N1 A21 LVDS Clock input 1 C3 FMC_DP_C2M_N0 AE36 PCML Transmit channel A23 FMC_DP_C2M_N1 AA36 PCML Transmit channel A27 FMC_DP_C2M_N2 W36 PCML Transmit channel A31 FMC_DP_C2M_N3 R36 PCML Transmit channel A35 FMC_DP_C2M_N4 N36 PCML Transmit channel A39 FMC_DP_C2M_N5 J36 PCML Transmit channel B37 FMC_DP_C2M_N6 G36 PCML Transmit channel B33 FMC_DP_C2M_N7 C36 PCML Transmit channel C2 FMC_DP_C2M_P0 AE37 PCML Transmit channel A22 FMC_DP_C2M_P1 AA37 PCML Transmit channel A26 FMC_DP_C2M_P2 W37 PCML Transmit channel A30 FMC_DP_C2M_P3 R37 PCML Transmit channel A34 FMC_DP_C2M_P4 N37 PCML Transmit channel A38 FMC_DP_C2M_P5 J37 PCML Transmit channel B36 FMC_DP_C2M_P6 G37 PCML Transmit channel B32 FMC_DP_C2M_P7 C37 PCML Transmit channel C7 FMC_DP_M2C_N0 AF38 PCML Receive channel A3 FMC_DP_M2C_N1 AB38 PCML Receive channel April 2014 Altera Corporation Power good output Arria V SoC Development Board Reference Manual 2-30 Chapter 2: Board Components Components and Interfaces Table 2-21. FMC Port A Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 5) Board Reference (J26) Schematic Signal Name Arria V SoC I/O Standard Pin Number Description A7 FMC_DP_M2C_N2 Y38 PCML Receive channel A11 FMC_DP_M2C_N3 T38 PCML Receive channel A15 FMC_DP_M2C_N4 P38 PCML Receive channel A19 FMC_DP_M2C_N5 K38 PCML Receive channel B17 FMC_DP_M2C_N6 H38 PCML Receive channel B13 FMC_DP_M2C_N7 D38 PCML Receive channel C6 FMC_DP_M2C_P0 AF39 PCML Receive channel A2 FMC_DP_M2C_P1 AB39 PCML Receive channel A6 FMC_DP_M2C_P2 Y39 PCML Receive channel A10 FMC_DP_M2C_P3 T39 PCML Receive channel A14 FMC_DP_M2C_P4 P39 PCML Receive channel A18 FMC_DP_M2C_P5 K39 PCML Receive channel B16 FMC_DP_M2C_P6 H39 PCML Receive channel B12 FMC_DP_M2C_P7 D39 PCML Receive channel C34 FMC_GA0 C23 2.5-V CMOS FMC geographical address 0 D35 FMC_GA1 P25 2.5-V CMOS FMC geographical address 1 D4 FMC_GBTCLK_M2C_P0 AC31 LVDS Transceiver reference clock 0 D5 FMC_GBTCLK_M2C_N0 AC32 LVDS Transceiver reference clock 0 B20 FMC_GBTCLK_M2C_P1 AA31 LVDS Transceiver reference clock 1 B21 FMC_GBTCLK_M2C_N1 AA32 LVDS Transceiver reference clock 1 E18 FMC_GPIO0 B24 2.5-V CMOS FMC general purpose IO bit 0 (part of the partially populated HPS connector signal group) E19 FMC_GPIO1 C24 2.5-V CMOS FMC general purpose IO bit 1 (part of the partially populated HPS connector signal group) K19 FMC_GPIO2 F24 2.5-V CMOS FMC general purpose IO bit 2 (part of the partially populated HPS connector signal group) K20 FMC_GPIO3 G24 2.5-V CMOS FMC general purpose IO bit 3 (part of the partially populated HPS connector signal group) J21 FMC_GPIO4 H24 2.5-V CMOS FMC general purpose IO bit 4 (part of the partially populated HPS connector signal group) J22 FMC_GPIO5 J24 2.5-V CMOS FMC general purpose IO bit 5 (part of the partially populated HPS connector signal group) K22 FMC_GPIO6 B27 2.5-V CMOS FMC general purpose IO bit 6 (part of the partially populated HPS connector signal group) K23 FMC_GPIO7 C27 2.5-V CMOS FMC general purpose IO bit 7 (part of the partially populated HPS connector signal group) D30 FMC_JTAG_TDI -- 2.5-V CMOS JTAG data in D31 FMC_JTAG_TDO -- 2.5-V CMOS JTAG data out D33 FMC_JTAG_TMS -- 2.5-V CMOS JTAG mode select D34 FMC_JTAG_RST -- 2.5-V CMOS JTAG mode reset Arria V SoC Development Board Reference Manual April 2014 Altera Corporation Chapter 2: Board Components Components and Interfaces 2-31 Table 2-21. FMC Port A Pin Assignments, Schematic Signal Names, and Functions (Part 3 of 5) Board Reference (J26) Schematic Signal Name Arria V SoC I/O Standard Pin Number Description G6 FMC_LA_RX_CLK_P H21 LVDS Secondary carrier-bound clock G7 FMC_LA_RX_CLK_N J21 LVDS Secondary carrier-bound clock G10 FMC_LA_RX_N0 T28 2.5-V CMOS FMC data bus C11 FMC_LA_RX_N1 R27 2.5-V CMOS FMC data bus F11 FMC_LA_RX_N2 N27 2.5-V CMOS FMC data bus C15 FMC_LA_RX_N3 N26 2.5-V CMOS FMC data bus G16 FMC_LA_RX_N4 D26 2.5-V CMOS FMC data bus C19 FMC_LA_RX_N5 T27 2.5-V CMOS FMC data bus G19 FMC_LA_RX_N6 G26 2.5-V CMOS FMC data bus D21 FMC_LA_RX_N7 D20 2.5-V CMOS FMC data bus G22 FMC_LA_RX_N8 F22 2.5-V CMOS FMC data bus G25 FMC_LA_RX_N9 P22 2.5-V CMOS FMC data bus G28 FMC_LA_RX_N10 B25 2.5-V CMOS FMC data bus D24 FMC_LA_RX_N11 T25 2.5-V CMOS FMC data bus G31 FMC_LA_RX_N12 P24 2.5-V CMOS FMC data bus G34 FMC_LA_RX_N13 E25 2.5-V CMOS FMC data bus G37 FMC_LA_RX_N14 E24 2.5-V CMOS FMC data bus F20 FMC_LA_RX_N15 G23 2.5-V CMOS FMC data bus G9 FMC_LA_RX_P0 R28 2.5-V CMOS FMC data bus C10 FMC_LA_RX_P1 P27 2.5-V CMOS FMC data bus F10 FMC_LA_RX_P2 M27 2.5-V CMOS FMC data bus C14 FMC_LA_RX_P3 M26 2.5-V CMOS FMC data bus G15 FMC_LA_RX_P4 C26 2.5-V CMOS FMC data bus C18 FMC_LA_RX_P5 R26 2.5-V CMOS FMC data bus G18 FMC_LA_RX_P6 F26 2.5-V CMOS FMC data bus D20 FMC_LA_RX_P7 C20 2.5-V CMOS FMC data bus G21 FMC_LA_RX_P8 E22 2.5-V CMOS FMC data bus G24 FMC_LA_RX_P9 N22 2.5-V CMOS FMC data bus G27 FMC_LA_RX_P10 A25 2.5-V CMOS FMC data bus D23 FMC_LA_RX_P11 T26 2.5-V CMOS FMC data bus G30 FMC_LA_RX_P12 N24 2.5-V CMOS FMC data bus G33 FMC_LA_RX_P13 D25 2.5-V CMOS FMC data bus G36 FMC_LA_RX_P14 D24 2.5-V CMOS FMC data bus F19 FMC_LA_RX_P15 F23 2.5-V CMOS FMC data bus D8 FMC_LA_TX_CLK_P M23 2.5-V CMOS Mezzanine-bound clock D9 FMC_LA_TX_CLK_N N23 2.5-V CMOS Mezzanine-bound clock H8 FMC_LA_TX_N0 J27 2.5-V CMOS FMC data bus H11 FMC_LA_TX_N1 K26 2.5-V CMOS FMC data bus April 2014 Altera Corporation Arria V SoC Development Board Reference Manual 2-32 Chapter 2: Board Components Components and Interfaces Table 2-21. FMC Port A Pin Assignments, Schematic Signal Names, and Functions (Part 4 of 5) Board Reference (J26) Schematic Signal Name Arria V SoC I/O Standard Pin Number Description D12 FMC_LA_TX_N2 F27 2.5-V CMOS FMC data bus H14 FMC_LA_TX_N3 P28 2.5-V CMOS FMC data bus D15 FMC_LA_TX_N4 A27 2.5-V CMOS FMC data bus H17 FMC_LA_TX_N5 N25 2.5-V CMOS FMC data bus D18 FMC_LA_TX_N6 L27 2.5-V CMOS FMC data bus H20 FMC_LA_TX_N7 P21 2.5-V CMOS FMC data bus H23 FMC_LA_TX_N9 T21 2.5-V CMOS FMC data bus H26 FMC_LA_TX_N10 A24 2.5-V CMOS FMC data bus H29 FMC_LA_TX_N12 T22 2.5-V CMOS FMC data bus D27 FMC_LA_TX_N13 L24 2.5-V CMOS FMC data bus H35 FMC_LA_TX_N14 H25 2.5-V CMOS FMC data bus H38 FMC_LA_TX_N15 T24 2.5-V CMOS FMC data bus G13 FMC_LA_TX_N16 T23 2.5-V CMOS FMC data bus H32 FMC_LA_TX_N17 K23 2.5-V CMOS FMC data bus H7 FMC_LA_TX_P0 H27 2.5-V CMOS FMC data bus H10 FMC_LA_TX_P1 J26 2.5-V CMOS FMC data bus D11 FMC_LA_TX_P2 E27 2.5-V CMOS FMC data bus H13 FMC_LA_TX_P3 N28 2.5-V CMOS FMC data bus D14 FMC_LA_TX_P4 A26 2.5-V CMOS FMC data bus H16 FMC_LA_TX_P5 M25 2.5-V CMOS FMC data bus D17 FMC_LA_TX_P6 K27 2.5-V CMOS FMC data bus H19 FMC_LA_TX_P7 N21 2.5-V CMOS FMC data bus H22 FMC_LA_TX_P9 R21 2.5-V CMOS FMC data bus H25 FMC_LA_TX_P10 A23 2.5-V CMOS FMC data bus H28 FMC_LA_TX_P12 R22 2.5-V CMOS FMC data bus D26 FMC_LA_TX_P13 K24 2.5-V CMOS FMC data bus H34 FMC_LA_TX_P14 G25 2.5-V CMOS FMC data bus H37 FMC_LA_TX_P15 R24 2.5-V CMOS FMC data bus G12 FMC_LA_TX_P16 R23 2.5-V CMOS FMC data bus H31 FMC_LA_TX_P17 J23 2.5-V CMOS FMC data bus F1 FMC_M2C_PG -- 2.5-V CMOS Power good input H2 FMC_PRSNT K25 2.5-V CMOS FMC module present C30 FMC_SCL J22 2.5-V CMOS Management serial clock line C31 FMC_SDA D23 2.5-V CMOS Management serial data line D29 JTAG_MUX_TCK AV34 2.5-V CMOS JTAG chain clock C23 LMK_CLK_FMC_N -- 2.5-V CMOS Alternate mezzanine-bound clock (from LMK device) C22 LMK_CLK_FMC_P -- 2.5-V CMOS Alternate mezzanine-bound clock (from LMK device) Arria V SoC Development Board Reference Manual April 2014 Altera Corporation Chapter 2: Board Components Components and Interfaces 2-33 Table 2-21. FMC Port A Pin Assignments, Schematic Signal Names, and Functions (Part 5 of 5) Board Reference (J26) Schematic Signal Name LMK_SYSREF_FMC_N C27 LMK_SYSREF_FMC_P C26 Arria V SoC I/O Standard Pin Number Description -- 2.5-V CMOS Alternate mezzanine-bound SYSREF signal (from LMK device) -- 2.5-V CMOS Alternate mezzanine-bound SYSREF signal (from LMK device) Table 2-22 lists the FMC port B pin assignments, signal names, and functions. Table 2-22. FMC Port B Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 4) Board Reference (J4) Schematic Signal Name D1 FMCB_C2M_PG Arria V SoC I/O Standard Pin Number -- 2.5-V CMOS Description Power good output H4 FMCB_CLK_M2C_P0 C34 LVDS Clock input 0 H5 FMCB_CLK_M2C_N0 D34 LVDS Clock input 0 G2 FMCB_CLK_M2C_P1 G34 LVDS Clock input 1 G3 FMCB_CLK_M2C_N1 H34 LVDS Clock input 1 C3 FMCB_DP_C2M_N0 AU36 PCML Transmit channel A23 FMCB_DP_C2M_N1 AN36 PCML Transmit channel A27 FMCB_DP_C2M_N2 AL36 PCML Transmit channel A31 FMCB_DP_C2M_N3 AG36 PCML Transmit channel C2 FMCB_DP_C2M_P0 AU37 PCML Transmit channel A22 FMCB_DP_C2M_P1 AN37 PCML Transmit channel A26 FMCB_DP_C2M_P2 AL37 PCML Transmit channel A30 FMCB_DP_C2M_P3 AG37 PCML Transmit channel C7 FMCB_DP_M2C_N0 AW36 PCML Receive channel A3 FMCB_DP_M2C_N1 AP38 PCML Receive channel A7 FMCB_DP_M2C_N2 AM38 PCML Receive channel A11 FMCB_DP_M2C_N3 AH38 PCML Receive channel C6 FMCB_DP_M2C_P0 AW37 PCML Receive channel A2 FMCB_DP_M2C_P1 AP39 PCML Receive channel A6 FMCB_DP_M2C_P2 AM39 PCML Receive channel A10 FMCB_DP_M2C_P3 AH39 PCML Receive channel C34 FMCB_GA0 J33 2.5-V CMOS FMC geographical address 0 D35 FMCB_GA1 R30 2.5-V CMOS FMC geographical address 1 D4 FMCB_GBTCLK_M2C_P0 AG32 LVDS Transceiver reference clock 0 D5 FMCB_GBTCLK_M2C_N0 AG33 LVDS Transceiver reference clock 0 B20 FMCB_GBTCLK_M2C_P1 AE31 LVDS Transceiver reference clock 1 B21 FMCB_GBTCLK_M2C_N1 AE32 LVDS Transceiver reference clock 1 E18 FMCB_GPIO0 F32 2.5-V CMOS April 2014 Altera Corporation FMC general purpose IO bit 0 (part of the partially populated HPS connector signal group) Arria V SoC Development Board Reference Manual 2-34 Chapter 2: Board Components Components and Interfaces Table 2-22. FMC Port B Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 4) Board Reference (J4) Schematic Signal Name Arria V SoC I/O Standard Pin Number Description E19 FMCB_GPIO1 G32 2.5-V CMOS FMC general purpose IO bit 1 (part of the partially populated HPS connector signal group) K19 FMCB_GPIO2 U19 2.5-V CMOS FMC general purpose IO bit 2 (part of the partially populated HPS connector signal group) K20 FMCB_GPIO3 U20 2.5-V CMOS FMC general purpose IO bit 3 (part of the partially populated HPS connector signal group) J21 FMCB_GPIO4 P20 2.5-V CMOS FMC general purpose IO bit 4 (part of the partially populated HPS connector signal group) J22 FMCB_GPIO5 R20 2.5-V CMOS FMC general purpose IO bit 5 (part of the partially populated HPS connector signal group) K22 FMCB_GPIO6 L20 2.5-V CMOS FMC general purpose IO bit 6 (part of the partially populated HPS connector signal group) K23 FMCB_GPIO7 M20 2.5-V CMOS FMC general purpose IO bit 7 (part of the partially populated HPS connector signal group) D30 FMCB_JTAG_TDI -- 2.5-V CMOS JTAG data in D31 FMCB_JTAG_TDO -- 2.5-V CMOS JTAG data out D33 FMCB_JTAG_TMS -- 2.5-V CMOS JTAG mode select D34 FMCB_JTAG_RST -- 2.5-V CMOS JTAG mode reset G6 FMCB_LA_RX_CLK_P E34 LVDS Secondary carrier-bound clock G7 FMCB_LA_RX_CLK_N F34 LVDS Secondary carrier-bound clock G31 FMCB_LA_RX_N0 A30 2.5-V CMOS FMC data bus G25 FMCB_LA_RX_N1 B33 2.5-V CMOS FMC data bus G22 FMCB_LA_RX_N2 D31 2.5-V CMOS FMC data bus F11 FMCB_LA_RX_N3 P31 2.5-V CMOS FMC data bus G19 FMCB_LA_RX_N4 N32 2.5-V CMOS FMC data bus D24 FMCB_LA_RX_N5 C30 2.5-V CMOS FMC data bus G16 FMCB_LA_RX_N6 M33 2.5-V CMOS FMC data bus C15 FMCB_LA_RX_N7 N33 2.5-V CMOS FMC data bus C11 FMCB_LA_RX_N8 P30 2.5-V CMOS FMC data bus G34 FMCB_LA_RX_N9 C29 2.5-V CMOS FMC data bus G37 FMCB_LA_RX_N10 A28 2.5-V CMOS FMC data bus D21 FMCB_LA_RX_N11 D29 2.5-V CMOS FMC data bus G10 FMCB_LA_RX_N12 T29 2.5-V CMOS FMC data bus G28 FMCB_LA_RX_N13 A35 2.5-V CMOS FMC data bus F20 FMCB_LA_RX_N14 D28 2.5-V CMOS FMC data bus C19 FMCB_LA_RX_N15 N29 2.5-V CMOS FMC data bus G30 FMCB_LA_RX_P0 B31 2.5-V CMOS FMC data bus G24 FMCB_LA_RX_P1 A33 2.5-V CMOS FMC data bus G21 FMCB_LA_RX_P2 C31 2.5-V CMOS FMC data bus F10 FMCB_LA_RX_P3 N31 2.5-V CMOS FMC data bus Arria V SoC Development Board Reference Manual April 2014 Altera Corporation Chapter 2: Board Components Components and Interfaces 2-35 Table 2-22. FMC Port B Pin Assignments, Schematic Signal Names, and Functions (Part 3 of 4) Board Reference (J4) Schematic Signal Name Arria V SoC I/O Standard Pin Number Description G18 FMCB_LA_RX_P4 M32 2.5-V CMOS FMC data bus D23 FMCB_LA_RX_P5 B30 2.5-V CMOS FMC data bus G15 FMCB_LA_RX_P6 L33 2.5-V CMOS FMC data bus C14 FMCB_LA_RX_P7 N34 2.5-V CMOS FMC data bus C10 FMCB_LA_RX_P8 N30 2.5-V CMOS FMC data bus G33 FMCB_LA_RX_P9 B28 2.5-V CMOS FMC data bus G36 FMCB_LA_RX_P10 A29 2.5-V CMOS FMC data bus D20 FMCB_LA_RX_P11 D30 2.5-V CMOS FMC data bus G9 FMCB_LA_RX_P12 R29 2.5-V CMOS FMC data bus G27 FMCB_LA_RX_P13 B34 2.5-V CMOS FMC data bus F19 FMCB_LA_RX_P14 C28 2.5-V CMOS FMC data bus C18 FMCB_LA_RX_P15 M29 2.5-V CMOS FMC data bus D8 FMCB_LA_TX_CLK_P L30 2.5-V CMOS Mezzanine-bound clock D9 FMCB_LA_TX_CLK_N M30 2.5-V CMOS Mezzanine-bound clock D15 FMCB_LA_TX_N0 A32 2.5-V CMOS FMC data bus H23 FMCB_LA_TX_N1 J31 2.5-V CMOS FMC data bus H38 FMCB_LA_TX_N2 D32 2.5-V CMOS FMC data bus H20 FMCB_LA_TX_N3 K32 2.5-V CMOS FMC data bus H17 FMCB_LA_TX_N4 K34 2.5-V CMOS FMC data bus H32 FMCB_LA_TX_N5 F31 2.5-V CMOS FMC data bus G13 FMCB_LA_TX_N6 M34 2.5-V CMOS FMC data bus H11 FMCB_LA_TX_N7 M31 2.5-V CMOS FMC data bus H29 FMCB_LA_TX_N9 F33 2.5-V CMOS FMC data bus H14 FMCB_LA_TX_N10 K30 2.5-V CMOS FMC data bus H26 FMCB_LA_TX_N12 G30 2.5-V CMOS FMC data bus D12 FMCB_LA_TX_N13 J28 2.5-V CMOS FMC data bus D27 FMCB_LA_TX_N14 G28 2.5-V CMOS FMC data bus D18 FMCB_LA_TX_N15 G29 2.5-V CMOS FMC data bus H8 FMCB_LA_TX_N16 K29 2.5-V CMOS FMC data bus H35 FMCB_LA_TX_N17 D33 2.5-V CMOS FMC data bus D14 FMCB_LA_TX_P0 A31 2.5-V CMOS FMC data bus H22 FMCB_LA_TX_P1 H31 2.5-V CMOS FMC data bus H37 FMCB_LA_TX_P2 C32 2.5-V CMOS FMC data bus H19 FMCB_LA_TX_P3 J32 2.5-V CMOS FMC data bus H16 FMCB_LA_TX_P4 J34 2.5-V CMOS FMC data bus H31 FMCB_LA_TX_P5 E31 2.5-V CMOS FMC data bus G12 FMCB_LA_TX_P6 L34 2.5-V CMOS FMC data bus H10 FMCB_LA_TX_P7 L31 2.5-V CMOS FMC data bus April 2014 Altera Corporation Arria V SoC Development Board Reference Manual 2-36 Chapter 2: Board Components Components and Interfaces Table 2-22. FMC Port B Pin Assignments, Schematic Signal Names, and Functions (Part 4 of 4) Board Reference (J4) Schematic Signal Name Arria V SoC I/O Standard Pin Number Description H28 FMCB_LA_TX_P9 E33 2.5-V CMOS FMC data bus H13 FMCB_LA_TX_P10 J30 2.5-V CMOS FMC data bus H25 FMCB_LA_TX_P12 F30 2.5-V CMOS FMC data bus D11 FMCB_LA_TX_P13 H28 2.5-V CMOS FMC data bus D26 FMCB_LA_TX_P14 F28 2.5-V CMOS FMC data bus D17 FMCB_LA_TX_P15 F29 2.5-V CMOS FMC data bus H7 FMCB_LA_TX_P16 J29 2.5-V CMOS FMC data bus H34 FMCB_LA_TX_P17 C33 2.5-V CMOS FMC data bus F1 FMCB_M2C_PG -- 2.5-V CMOS Power good input H2 FMCB_PRSNT L19 2.5-V CMOS FMC module present C30 FMCB_SCL N19 2.5-V CMOS Management serial clock line C31 FMCB_SDA M19 2.5-V CMOS Management serial data line D29 JTAG_MUX_TCK AV34 2.5-V CMOS JTAG chain clock C23 LMK_CLK_FMCB_N -- 2.5-V CMOS Alternate mezzanine-bound clock (from LMK device) C22 LMK_CLK_FMCB_P -- 2.5-V CMOS Alternate mezzanine-bound clock (from LMK device) -- 2.5-V CMOS Alternate mezzanine-bound SYSREF signal (from LMK device) -- 2.5-V CMOS Alternate mezzanine-bound SYSREF signal (from LMK device) LMK_SYSREF_FMCB_N C27 LMK_SYSREF_FMCB_P C26 RS-232 UART (HPS) The development board supports two UART interfaces that connect to a mini-USB connector (J27) using a FT232RQ-REEL USB-to-UART bridge. The maximum supported rate for this interface is 1 Mbps. Board reference D21-D24 are the UART LEDs that illuminate to indicate TX and RX activity. Table 2-27 lists the RS-232 UART pin assignments, signal names, and functions. The signal names and types are relative to the Arria V SoC in terms of I/O setting and direction. Table 2-23. RS-232 UART Schematic Signal Names and Functions Schematic Signal Name Board Reference Arria V SoC Pin Number I/O Standard Description UART Port A (U25) 2 UARTA_TX M13 3.3-V Transmit data 30 UARTA_RX M12 3.3-V Receive data 18 RESET_HPS_UARTA_N -- 3.3-V Reset 11 POWER_ENA -- 3.3-V Power 2 UARTB_TX N13 3.3-V Transmit data 30 UARTB_RX G13 3.3-V Receive data UART Port B (U36) Arria V SoC Development Board Reference Manual April 2014 Altera Corporation Chapter 2: Board Components Components and Interfaces 2-37 Table 2-23. RS-232 UART Schematic Signal Names and Functions Board Reference Schematic Signal Name Arria V SoC Pin Number I/O Standard 18 RESET_HPS_UARTB_N -- 3.3-V Reset 11 POWER_ENB -- 3.3-V Power Description Real-Time Clock (HPS) The HPS system has a battery-backed real-time clock (RTC) connected through the I2C interface. The RTC is implemented using a DS1339 device from Maxim Semiconductor. The device has a built-in power sense circuit that detects power failures and automatically switches to backup battery supply, maintaining time. The device uses a CR1225 lithium coin battery with a nominal voltage of 3 V. Using typical current capacity, the RTC is expected to have 120,000 backup hours. The battery is mounted inside a holder attached to the board to allow battery replacement or removal. Table 2-24 lists the RTC device pin assignments, signal names, and functions. The signal names and types are relative to the Arria V SoC in terms of I/O setting and direction. Table 2-24. RTC Device Schematic Signal Names and Functions Board Reference (U11) Schematic Signal Name Arria V SoC Pin Number I/O Standard Description 16 I2C_SDA_HPS C13 3.3-V Management serial data 1 I2C_SCL_HPS L13 3.3-V Management serial clock SFP+ The development board include two SFP+ ports that uses two transceiver channels from the FPGA. These ports takes in serial data from the FPGA and transform them into optical signals. Both SFP+ ports are active and include the SFP+ cage assembly. Table 2-25 list the SFP+ ports interface pin assignments, signal names, and functions. Table 2-25. SFP+ Ports Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 2) Board Reference Schematic Signal Name Arria V SoC Pin Number I/O Standard Description SFP+ Port A (J44) 6 SFPA_MOD0_PRSNTn AR9 3.3-V LVTTL Module present indicator 8 SFPA_LOS AV7 3.3-V LVTTL Signal present indicator 2 SFPA_TXFAULT AL9 3.3-V LVTTL Transmitter fault indicator 12 SFPA_RX_N AE2 PCML Receiver data 13 SFPA_RX_P AE1 PCML Receiver data 5 SFPA_MOD1_SCL AT8 3.3-V LVTTL Serial 2-wire clock 4 SFPA_MOD1_SDA AH8 3.3-V LVTTL Serial 2-wire data 3 SFPA_TXDISABLE AP7 3.3-V LVTTL Drive low to disable transmitter 19 SFPA_TX_N AD4 PCML April 2014 Altera Corporation Transmitter data Arria V SoC Development Board Reference Manual 2-38 Chapter 2: Board Components Components and Interfaces Table 2-25. SFP+ Ports Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 2) Board Reference Schematic Signal Name Arria V SoC Pin Number I/O Standard Description 18 SFPA_TX_P AD3 PCML Transmitter data 7 SFPA_RATESEL0 AU6 3.3-V LVTTL Rate select 9 SFPA_RATESEL1 AL8 3.3-V LVTTL Rate select 6 SFPB_MOD0_PRSNTn AP8 3.3-V LVTTL Module present indicator 8 SFPB_LOS AG21 3.3-V LVTTL Signal present indicator 2 SFPB_TXFAULT AK20 3.3-V LVTTL Transmitter fault indicator 12 SFPB_RX_N W2 PCML Receiver data 13 SFPB_RX_P W1 PCML Receiver data 5 SFPB_MOD1_SCL AN8 3.3-V LVTTL Serial 2-wire clock 4 SFPB_MOD1_SDA AJ7 3.3-V LVTTL Serial 2-wire data 3 SFPB_TXDISABLE AT6 3.3-V LVTTL Drive low to disable transmitter 19 SFPB_TX_N Y4 PCML Rate select 18 SFPB_TX_P Y3 PCML Rate select 7 SFPB_RATESEL0 AK8 3.3-V LVTTL Reserved 9 SFPB_RATESEL1 AN7 3.3-V LVTTL Reserved SFP+ Port B (J43) I2C Interface The HPS system has one I2C interface for communicating with the on-board and external components using a data rate of 400 kbps. Table 2-26 lists the I2C interface address map. Table 2-26. I2C interface address map Address Arria V SoC Development Board Reference Manual Device 0x68 Real-time clock 0x50 LCD 0x51 EEPROM 0x5C HPS power monitor 0x5E FPGA power monitor 1 0x62 FPGA power monitor 2 0x55 Si571 programmable oscillator 0x66 Si570 programmable oscillator 0x70 Si5338 quad-programmable clock April 2014 Altera Corporation Chapter 2: Board Components Memory 2-39 Memory This section describes the development board's memory interface support and also their signal names, types, and connectivity relative to the Arria V SoC. The development board has the following memory interfaces: DDR3 SDRAM (FPGA) DDR3 SDRAM (HPS) QSPI flash (HPS) EPCQ flash Synchronous flash Micro SD flash memory I2C EEPROM f For more information about the memory interfaces, refer to the following documents: Timing Analysis section in the External Memory Interface Handbook. DDR, DDR2, and DDR3 SDRAM Design Tutorials section in the External Memory Interface Handbook. DDR3 SDRAM (FPGA) The development board supports two 32Mx16x8 DDR3 SDRAM interface for very high-speed sequential memory access. The 32-bit data bus comprises of two x16 devices with a single address or command bus. This interface connects to the dedicated HMC I/O banks on the bottom edge of the FPGA. The DDR3 device shipped with this board are running at 533 MHz, for a total theoretical bandwidth of over 25.6 Gbps. The speed grade of this DDR3 device is 800 MHz with a CAS latency of 9. Table 2-27 lists the DDR3 SDRAM pin assignments, signal names, and functions. The signal names and types are relative to the Arria V SoC in terms of I/O setting and direction. Table 2-27. DDR3 SDRAM Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 7) Board Reference Schematic Signal Name Arria V SoC Pin Number I/O Standard Description DDR3 x32 (U37) N3 DDR3A_A0 AU29 1.5-V SSTL Class I Address bus P7 DDR3A_A1 AT29 1.5-V SSTL Class I Address bus P3 DDR3A_A2 AV30 1.5-V SSTL Class I Address bus N2 DDR3A_A3 AU30 1.5-V SSTL Class I Address bus P8 DDR3A_A4 AT30 1.5-V SSTL Class I Address bus P2 DDR3A_A5 AR30 1.5-V SSTL Class I Address bus R8 DDR3A_A6 AL30 1.5-V SSTL Class I Address bus R2 DDR3A_A7 AK30 1.5-V SSTL Class I Address bus April 2014 Altera Corporation Arria V SoC Development Board Reference Manual 2-40 Chapter 2: Board Components Memory Table 2-27. DDR3 SDRAM Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 7) Board Reference Schematic Signal Name Arria V SoC Pin Number I/O Standard Description T8 DDR3A_A8 AW31 1.5-V SSTL Class I Address bus R3 DDR3A_A9 AW30 1.5-V SSTL Class I Address bus L7 DDR3A_A10 AV31 1.5-V SSTL Class I Address bus R7 DDR3A_A11 AU31 1.5-V SSTL Class I Address bus N7 DDR3A_A12 AH30 1.5-V SSTL Class I Address bus T3 DDR3A_A13 AG30 1.5-V SSTL Class I Address bus T7 DDR3A_A14 AE29 1.5-V SSTL Class I Address bus M2 DDR3A_BA0 AT31 1.5-V SSTL Class I Bank address bus N8 DDR3A_BA1 AR31 1.5-V SSTL Class I Bank address bus M3 DDR3A_BA2 AP31 1.5-V SSTL Class I Bank address bus K3 DDR3A_CASN AW32 1.5-V SSTL Class I Row address select K9 DDR3A_CKE AP30 1.5-V SSTL Class I Column address select J7 DDR3A_CLK_P AP29 Differential 1.5-V SSTL Class I Differential output clock K7 DDR3A_CLK_N AN29 Differential 1.5-V SSTL Class I Differential output clock L2 DDR3A_CSN AP32 1.5-V SSTL Class I Chip select E7 DDR3A_DM2 AF27 1.5-V SSTL Class I Write mask byte lane D3 DDR3A_DM3 AK25 1.5-V SSTL Class I Write mask byte lane F7 DDR3A_DQ16 AH25 1.5-V SSTL Class I Data bus E3 DDR3A_DQ17 AG25 1.5-V SSTL Class I Data bus F8 DDR3A_DQ18 AE26 1.5-V SSTL Class I Data bus H8 DDR3A_DQ19 AH26 1.5-V SSTL Class I Data bus H7 DDR3A_DQ20 AG26 1.5-V SSTL Class I Data bus F2 DDR3A_DQ21 AD25 1.5-V SSTL Class I Data bus G2 DDR3A_DQ22 AC25 1.5-V SSTL Class I Data bus H3 DDR3A_DQ23 AB25 1.5-V SSTL Class I Data bus C2 DDR3A_DQ24 AV24 1.5-V SSTL Class I Data bus C3 DDR3A_DQ25 AV25 1.5-V SSTL Class I Data bus C8 DDR3A_DQ26 AL26 1.5-V SSTL Class I Data bus A3 DDR3A_DQ27 AW26 1.5-V SSTL Class I Data bus D7 DDR3A_DQ28 AW25 1.5-V SSTL Class I Data bus A2 DDR3A_DQ29 AT25 1.5-V SSTL Class I Data bus A7 DDR3A_DQ30 AN25 1.5-V SSTL Class I Data bus B8 DDR3A_DQ31 AM25 1.5-V SSTL Class I Data bus F3 DDR3A_DQS_P2 AF25 Differential 1.5-V SSTL Class I Data strobe P byte lane 2 G3 DDR3A_DQS_N2 AE25 Differential 1.5-V SSTL Class I Data strobe N byte lane 2 Arria V SoC Development Board Reference Manual April 2014 Altera Corporation Chapter 2: Board Components Memory 2-41 Table 2-27. DDR3 SDRAM Pin Assignments, Schematic Signal Names, and Functions (Part 3 of 7) Board Reference Schematic Signal Name Arria V SoC Pin Number I/O Standard Description C7 DDR3A_DQS_P3 AU26 Differential 1.5-V SSTL Class I Data strobe P byte lane 3 B7 DDR3A_DQS_N3 AT26 Differential 1.5-V SSTL Class I Data strobe N byte lane 3 K1 DDR3A_ODT AM31 1.5-V SSTL Class I On-die termination enable J3 DDR3A_RASN AN31 1.5-V SSTL Class I Row address select T2 DDR3A_RESETN AB29 1.5-V SSTL Class I Reset L3 DDR3A_WEN AW33 1.5-V SSTL Class I Write enable L8 DDR3A_ZQ1 -- 1.5-V SSTL Class I ZQ impedance calibration N3 DDR3A_A0 AU29 1.5-V SSTL Class I Address bus P7 DDR3A_A1 AT29 1.5-V SSTL Class I Address bus P3 DDR3A_A2 AV30 1.5-V SSTL Class I Address bus N2 DDR3A_A3 AU30 1.5-V SSTL Class I Address bus P8 DDR3A_A4 AT30 1.5-V SSTL Class I Address bus DDR3 x16 (U29) P2 DDR3A_A5 AR30 1.5-V SSTL Class I Address bus R8 DDR3A_A6 AL30 1.5-V SSTL Class I Address bus R2 DDR3A_A7 AK30 1.5-V SSTL Class I Address bus T8 DDR3A_A8 AW31 1.5-V SSTL Class I Address bus R3 DDR3A_A9 AW30 1.5-V SSTL Class I Address bus L7 DDR3A_A10 AV31 1.5-V SSTL Class I Address bus R7 DDR3A_A11 AU31 1.5-V SSTL Class I Address bus N7 DDR3A_A12 AH30 1.5-V SSTL Class I Address bus T3 DDR3A_A13 AG30 1.5-V SSTL Class I Address bus T7 DDR3A_A14 AE29 1.5-V SSTL Class I Address bus M2 DDR3A_BA0 AT31 1.5-V SSTL Class I Bank address bus N8 DDR3A_BA1 AR31 1.5-V SSTL Class I Bank address bus M3 DDR3A_BA2 AP31 1.5-V SSTL Class I Bank address bus K3 DDR3A_CASN AW32 1.5-V SSTL Class I Row address select K9 DDR3A_CKE AP30 1.5-V SSTL Class I Column address select J7 DDR3A_CLK_P AP29 1.5-V SSTL Class I Differential output clock K7 DDR3A_CLK_N AN29 1.5-V SSTL Class I Differential output clock L2 DDR3A_CSN AP32 1.5-V SSTL Class I Chip select E7 DDR3A_DM0 AF27 1.5-V SSTL Class I Write mask byte lane D3 DDR3A_DM1 AK25 1.5-V SSTL Class I Write mask byte lane H3 DDR3A_DQ0 AH25 1.5-V SSTL Class I Data bus F8 DDR3A_DQ1 AG25 1.5-V SSTL Class I Data bus G2 DDR3A_DQ2 AE26 1.5-V SSTL Class I Data bus H8 DDR3A_DQ3 AH26 1.5-V SSTL Class I Data bus April 2014 Altera Corporation Arria V SoC Development Board Reference Manual 2-42 Chapter 2: Board Components Memory Table 2-27. DDR3 SDRAM Pin Assignments, Schematic Signal Names, and Functions (Part 4 of 7) Board Reference Schematic Signal Name Arria V SoC Pin Number I/O Standard Description H7 DDR3A_DQ4 AG26 1.5-V SSTL Class I Data bus F7 DDR3A_DQ5 AD25 1.5-V SSTL Class I Data bus E3 DDR3A_DQ6 AC25 1.5-V SSTL Class I Data bus F2 DDR3A_DQ7 AB25 1.5-V SSTL Class I Data bus C2 DDR3A_DQ8 AV24 1.5-V SSTL Class I Data bus A2 DDR3A_DQ9 AV25 1.5-V SSTL Class I Data bus D7 DDR3A_DQ10 AL26 1.5-V SSTL Class I Data bus A7 DDR3A_DQ11 AW26 1.5-V SSTL Class I Data bus C8 DDR3A_DQ12 AW25 1.5-V SSTL Class I Data bus B8 DDR3A_DQ13 AT25 1.5-V SSTL Class I Data bus A3 DDR3A_DQ14 AN25 1.5-V SSTL Class I Data bus C3 DDR3A_DQ15 AM25 1.5-V SSTL Class I Data bus F3 DDR3A_DQS_P0 AF25 Differential 1.5-V SSTL Class I Data strobe P byte lane 0 G3 DDR3A_DQS_N0 AE25 Differential 1.5-V SSTL Class I Data strobe N byte lane 0 C7 DDR3A_DQS_P1 AU26 Differential 1.5-V SSTL Class I Data strobe P byte lane 1 B7 DDR3A_DQS_N1 AT26 Differential 1.5-V SSTL Class I Data strobe N byte lane 1 K1 DDR3A_ODT AM31 1.5-V SSTL Class I On-die termination enable J3 DDR3A_RASN AN31 1.5-V SSTL Class I Row address select T2 DDR3A_RESETN AB29 1.5-V SSTL Class I Reset L3 DDR3A_WEN AW33 1.5-V SSTL Class I Write enable L8 DDR3A_ZQ -- 1.5-V SSTL Class I ZQ impedance calibration N3 DDR3B_A0 AP16 1.5-V SSTL Class I Address bus P7 DDR3B_A1 AN16 1.5-V SSTL Class I Address bus P3 DDR3B_A2 AK16 1.5-V SSTL Class I Address bus N2 DDR3B_A3 AJ16 1.5-V SSTL Class I Address bus P8 DDR3B_A4 AV16 1.5-V SSTL Class I Address bus DDR3 x32 (U49) P2 DDR3B_A5 AU16 1.5-V SSTL Class I Address bus R8 DDR3B_A6 AT16 1.5-V SSTL Class I Address bus R2 DDR3B_A7 AR16 1.5-V SSTL Class I Address bus T8 DDR3B_A8 AP17 1.5-V SSTL Class I Address bus R3 DDR3B_A9 AN17 1.5-V SSTL Class I Address bus L7 DDR3B_A10 AH17 1.5-V SSTL Class I Address bus R7 DDR3B_A11 AG17 1.5-V SSTL Class I Address bus N7 DDR3B_A12 AM18 1.5-V SSTL Class I Address bus Arria V SoC Development Board Reference Manual April 2014 Altera Corporation Chapter 2: Board Components Memory 2-43 Table 2-27. DDR3 SDRAM Pin Assignments, Schematic Signal Names, and Functions (Part 5 of 7) Board Reference Schematic Signal Name Arria V SoC Pin Number I/O Standard Description T3 DDR3B_A13 AL18 1.5-V SSTL Class I Address bus T7 DDR3B_A14 AG18 1.5-V SSTL Class I Address bus M2 DDR3B_BA0 AE18 1.5-V SSTL Class I Bank address bus N8 DDR3B_BA1 AD18 1.5-V SSTL Class I Bank address bus M3 DDR3B_BA2 AC18 1.5-V SSTL Class I Bank address bus K3 DDR3B_CASN AR18 1.5-V SSTL Class I Row address select K9 DDR3B_CKE AM16 1.5-V SSTL Class I Column address select J7 DDR3B_CLK_P AF16 Differential 1.5-V SSTL Class I Differential output clock K7 DDR3B_CLK_N AE17 Differential 1.5-V SSTL Class I Differential output clock L2 DDR3B_CSN AL17 1.5-V SSTL Class I Chip select E7 DDR3B_DM2 AU12 1.5-V SSTL Class I Write mask byte lane D3 DDR3B_DM3 AV10 1.5-V SSTL Class I Write mask byte lane H3 DDR3B_DQ16 AJ13 1.5-V SSTL Class I Data bus F2 DDR3B_DQ17 AH13 1.5-V SSTL Class I Data bus E3 DDR3B_DQ18 AP12 1.5-V SSTL Class I Data bus F8 DDR3B_DQ19 AW11 1.5-V SSTL Class I Data bus F7 DDR3B_DQ20 AW10 1.5-V SSTL Class I Data bus H8 DDR3B_DQ21 AM13 1.5-V SSTL Class I Data bus G2 DDR3B_DQ22 AE13 1.5-V SSTL Class I Data bus H7 DDR3B_DQ23 AE14 1.5-V SSTL Class I Data bus C8 DDR3B_DQ24 AW9 1.5-V SSTL Class I Data bus B8 DDR3B_DQ25 AV9 1.5-V SSTL Class I Data bus A7 DDR3B_DQ26 AP11 1.5-V SSTL Class I Data bus C2 DDR3B_DQ27 AD13 1.5-V SSTL Class I Data bus A2 DDR3B_DQ28 AC13 1.5-V SSTL Class I Data bus D7 DDR3B_DQ29 AL12 1.5-V SSTL Class I Data bus C3 DDR3B_DQ30 AG13 1.5-V SSTL Class I Data bus A3 DDR3B_DQ31 AF13 1.5-V SSTL Class I Data bus F3 DDR3B_DQS_P2 AW12 Differential 1.5-V SSTL Class I Data strobe P byte lane 2 G3 DDR3B_DQS_N2 AV12 Differential 1.5-V SSTL Class I Data strobe N byte lane 2 C7 DDR3B_DQS_P3 AU11 Differential 1.5-V SSTL Class I Data strobe P byte lane 3 B7 DDR3B_DQS_N3 AT11 Differential 1.5-V SSTL Class I Data strobe N byte lane 3 K1 DDR3B_ODT AD19 1.5-V SSTL Class I On-die termination enable J3 DDR3B_RASN AD17 1.5-V SSTL Class I Row address select April 2014 Altera Corporation Arria V SoC Development Board Reference Manual 2-44 Chapter 2: Board Components Memory Table 2-27. DDR3 SDRAM Pin Assignments, Schematic Signal Names, and Functions (Part 6 of 7) Board Reference Schematic Signal Name Arria V SoC Pin Number I/O Standard Description T2 DDR3B_RESETN AN15 1.5-V SSTL Class I Reset L3 DDR3B_WEN AP18 1.5-V SSTL Class I Write enable L8 DDR3B_ZQ1 -- 1.5-V SSTL Class I ZQ impedance calibration N3 DDR3B_A0 AP16 1.5-V SSTL Class I Address bus P7 DDR3B_A1 AN16 1.5-V SSTL Class I Address bus P3 DDR3B_A2 AK16 1.5-V SSTL Class I Address bus N2 DDR3B_A3 AJ16 1.5-V SSTL Class I Address bus P8 DDR3B_A4 AV16 1.5-V SSTL Class I Address bus P2 DDR3B_A5 AU16 1.5-V SSTL Class I Address bus R8 DDR3B_A6 AT16 1.5-V SSTL Class I Address bus R2 DDR3B_A7 AR16 1.5-V SSTL Class I Address bus T8 DDR3B_A8 AP17 1.5-V SSTL Class I Address bus R3 DDR3B_A9 AN17 1.5-V SSTL Class I Address bus L7 DDR3B_A10 AH17 1.5-V SSTL Class I Address bus R7 DDR3B_A11 AG17 1.5-V SSTL Class I Address bus N7 DDR3B_A12 AM18 1.5-V SSTL Class I Address bus T3 DDR3B_A13 AL18 1.5-V SSTL Class I Address bus T7 DDR3B_A14 AG18 1.5-V SSTL Class I Address bus M2 DDR3B_BA0 AE18 1.5-V SSTL Class I Bank address bus N8 DDR3B_BA1 AD18 1.5-V SSTL Class I Bank address bus M3 DDR3B_BA2 AC18 1.5-V SSTL Class I Bank address bus K3 DDR3B_CASN AR18 1.5-V SSTL Class I Row address select K9 DDR3B_CKE AM16 1.5-V SSTL Class I Column address select J7 DDR3B_CLK_P AF16 1.5-V SSTL Class I Differential output clock K7 DDR3B_CLK_N AE17 1.5-V SSTL Class I Differential output clock L2 DDR3B_CSN AL17 1.5-V SSTL Class I Chip select E7 DDR3B_DM0 AD16 1.5-V SSTL Class I Write mask byte lane D3 DDR3B_DM1 AU13 1.5-V SSTL Class I Write mask byte lane H8 DDR3B_DQ0 AU15 1.5-V SSTL Class I Data bus F8 DDR3B_DQ1 AT15 1.5-V SSTL Class I Data bus DDR3 x16 (U43) H3 DDR3B_DQ2 AH15 1.5-V SSTL Class I Data bus H7 DDR3B_DQ3 AW13 1.5-V SSTL Class I Data bus G2 DDR3B_DQ4 AV13 1.5-V SSTL Class I Data bus F2 DDR3B_DQ5 AL15 1.5-V SSTL Class I Data bus F7 DDR3B_DQ6 AW15 1.5-V SSTL Class I Data bus E3 DDR3B_DQ7 AW14 1.5-V SSTL Class I Data bus B8 DDR3B_DQ8 AE15 1.5-V SSTL Class I Data bus Arria V SoC Development Board Reference Manual April 2014 Altera Corporation Chapter 2: Board Components Memory 2-45 Table 2-27. DDR3 SDRAM Pin Assignments, Schematic Signal Names, and Functions (Part 7 of 7) Board Reference Schematic Signal Name Arria V SoC Pin Number I/O Standard Description C8 DDR3B_DQ9 AD15 1.5-V SSTL Class I Data bus A7 DDR3B_DQ10 AH14 1.5-V SSTL Class I Data bus A3 DDR3B_DQ11 AP14 1.5-V SSTL Class I Data bus C3 DDR3B_DQ12 AN14 1.5-V SSTL Class I Data bus D7 DDR3B_DQ13 AL14 1.5-V SSTL Class I Data bus A2 DDR3B_DQ14 AU14 1.5-V SSTL Class I Data bus C2 DDR3B_DQ15 AT14 1.5-V SSTL Class I Data bus F3 DDR3B_DQS_P0 AH16 Differential 1.5-V SSTL Class I Data strobe P byte lane 0 G3 DDR3B_DQS_N0 AG16 Differential 1.5-V SSTL Class I Data strobe N byte lane 0 C7 DDR3B_DQS_P1 AF15 Differential 1.5-V SSTL Class I Data strobe P byte lane 1 B7 DDR3B_DQS_N1 AE16 Differential 1.5-V SSTL Class I Data strobe N byte lane 1 K1 DDR3B_ODT AD19 1.5-V SSTL Class I On-die termination enable J3 DDR3B_RASN AD17 1.5-V SSTL Class I Row address select T2 DDR3B_RESETN AN15 1.5-V SSTL Class I Reset L3 DDR3B_WEN AP18 1.5-V SSTL Class I Write enable L8 DDR3B_ZQ -- 1.5-V SSTL Class I ZQ impedance calibration DDR3 SDRAM (HPS) The development board supports three 32Mx16x8 banks DDR3 SDRAM interface with ECC for very high-speed sequential memory access. The 40-bit data bus comprises of three x16 devices with a single address or command bus. This interface connects to the dedicated HMC for HPS I/O banks on the top edge of the FPGA. The DDR3 device shipped with this board are running at 533 MHz, for a total theoretical bandwidth of over 25.6 Gbps. The speed grade of this DDR3 device is 800 MHz with a CAS latency of 9. Table 2-27 lists the DDR3 SDRAM pin assignments, signal names, and functions. The signal names and types are relative to the Arria V SoC in terms of I/O setting and direction. Table 2-28. DDR3 SDRAM Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 5) Board Reference Schematic Signal Name Arria V SoC Pin Number I/O Standard Description DDR3 x16 (U51) N3 DDR3_HPS_A0 N9 1.5-V SSTL Class I Address bus P7 DDR3_HPS_A1 M9 1.5-V SSTL Class I Address bus P3 DDR3_HPS_A2 N10 1.5-V SSTL Class I Address bus N2 DDR3_HPS_A3 M10 1.5-V SSTL Class I Address bus April 2014 Altera Corporation Arria V SoC Development Board Reference Manual 2-46 Chapter 2: Board Components Memory Table 2-28. DDR3 SDRAM Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 5) Board Reference Schematic Signal Name Arria V SoC Pin Number I/O Standard Description P8 DDR3_HPS_A4 A8 1.5-V SSTL Class I Address bus P2 DDR3_HPS_A5 B7 1.5-V SSTL Class I Address bus R8 DDR3_HPS_A6 B9 1.5-V SSTL Class I Address bus R2 DDR3_HPS_A7 A9 1.5-V SSTL Class I Address bus T8 DDR3_HPS_A8 D9 1.5-V SSTL Class I Address bus R3 DDR3_HPS_A9 C10 1.5-V SSTL Class I Address bus L7 DDR3_HPS_A10 K7 1.5-V SSTL Class I Address bus R7 DDR3_HPS_A11 J7 1.5-V SSTL Class I Address bus N7 DDR3_HPS_A12 F9 1.5-V SSTL Class I Address bus T3 DDR3_HPS_A13 E9 1.5-V SSTL Class I Address bus T7 DDR3_HPS_A14 D11 1.5-V SSTL Class I Address bus M2 DDR3_HPS_BA0 L7 1.5-V SSTL Class I Bank address bus N8 DDR3_HPS_BA1 C9 1.5-V SSTL Class I Bank address bus M3 DDR3_HPS_BA2 D8 1.5-V SSTL Class I Bank address bus K3 DDR3_HPS_CASN G9 1.5-V SSTL Class I Row address select K9 DDR3_HPS_CKE R8 1.5-V SSTL Class I Column address select Differential output clock Differential output clock J7 DDR3_HPS_CLK_P A11 Differential 1.5-V SSTL Class I K7 DDR3_HPS_CLK_N B10 Differential 1.5-V SSTL Class I L2 DDR3_HPS_CSN H9 1.5-V SSTL Class I Chip select E7 DDR3_HPS_DM4 T7 1.5-V SSTL Class I Write mask byte lane E3 DDR3_HPS_DQ32 G1 1.5-V SSTL Class I Data bus G2 DDR3_HPS_DQ33 F1 1.5-V SSTL Class I Data bus F2 DDR3_HPS_DQ34 P6 1.5-V SSTL Class I Data bus F8 DDR3_HPS_DQ35 L1 1.5-V SSTL Class I Data bus F7 DDR3_HPS_DQ36 M2 1.5-V SSTL Class I Data bus H8 DDR3_HPS_DQ37 M1 1.5-V SSTL Class I Data bus H7 DDR3_HPS_DQ38 N1 1.5-V SSTL Class I Data bus H3 DDR3_HPS_DQ39 R6 1.5-V SSTL Class I Data bus F3 DDR3_HPS_DQS_P4 J1 Differential 1.5-V SSTL Class I Data strobe P byte lane 4 G3 DDR3_HPS_DQS_N4 H1 Differential 1.5-V SSTL Class I Data strobe N byte lane 4 K1 DDR3_HPS_ODT H7 1.5-V SSTL Class I On-die termination enable J3 DDR3_HPS_RASN G8 1.5-V SSTL Class I Row address select T2 DDR3_HPS_RESETN E3 1.5-V SSTL Class I Reset L3 DDR3_HPS_WEN J8 1.5-V SSTL Class I Write enable L8 DDR3_HPS_ZQ01 -- 1.5-V SSTL Class I ZQ impedance calibration Arria V SoC Development Board Reference Manual April 2014 Altera Corporation Chapter 2: Board Components Memory 2-47 Table 2-28. DDR3 SDRAM Pin Assignments, Schematic Signal Names, and Functions (Part 3 of 5) Board Reference Schematic Signal Name Arria V SoC Pin Number I/O Standard Description DDR3 x16 (U44) N3 DDR3_HPS_A0 N9 1.5-V SSTL Class I Address bus P7 DDR3_HPS_A1 M9 1.5-V SSTL Class I Address bus P3 DDR3_HPS_A2 N10 1.5-V SSTL Class I Address bus N2 DDR3_HPS_A3 M10 1.5-V SSTL Class I Address bus P8 DDR3_HPS_A4 A8 1.5-V SSTL Class I Address bus P2 DDR3_HPS_A5 B7 1.5-V SSTL Class I Address bus R8 DDR3_HPS_A6 B9 1.5-V SSTL Class I Address bus R2 DDR3_HPS_A7 A9 1.5-V SSTL Class I Address bus T8 DDR3_HPS_A8 D9 1.5-V SSTL Class I Address bus R3 DDR3_HPS_A9 C10 1.5-V SSTL Class I Address bus L7 DDR3_HPS_A10 K7 1.5-V SSTL Class I Address bus R7 DDR3_HPS_A11 J7 1.5-V SSTL Class I Address bus N7 DDR3_HPS_A12 F9 1.5-V SSTL Class I Address bus T3 DDR3_HPS_A13 E9 1.5-V SSTL Class I Address bus T7 DDR3_HPS_A14 D11 1.5-V SSTL Class I Address bus M2 DDR3_HPS_BA0 L7 1.5-V SSTL Class I Bank address bus N8 DDR3_HPS_BA1 C9 1.5-V SSTL Class I Bank address bus M3 DDR3_HPS_BA2 D8 1.5-V SSTL Class I Bank address bus K3 DDR3_HPS_CASN G9 1.5-V SSTL Class I Row address select K9 DDR3_HPS_CKE R8 1.5-V SSTL Class I Column address select J7 DDR3_HPS_CLK_P A11 1.5-V SSTL Class I Differential output clock K7 DDR3_HPS_CLK_N B10 1.5-V SSTL Class I Differential output clock L2 DDR3_HPS_CSN H9 1.5-V SSTL Class I Chip select E7 DDR3_HPS_DM2 D3 1.5-V SSTL Class I Write mask byte lane D3 DDR3_HPS_DM3 D1 1.5-V SSTL Class I Write mask byte lane F2 DDR3_HPS_DQ16 J5 1.5-V SSTL Class I Data bus H3 DDR3_HPS_DQ17 K5 1.5-V SSTL Class I Data bus G2 DDR3_HPS_DQ18 N7 1.5-V SSTL Class I Data bus F8 DDR3_HPS_DQ19 F3 1.5-V SSTL Class I Data bus H7 DDR3_HPS_DQ20 H3 1.5-V SSTL Class I Data bus E3 DDR3_HPS_DQ21 J4 1.5-V SSTL Class I Data bus H8 DDR3_HPS_DQ22 M5 1.5-V SSTL Class I Data bus F7 DDR3_HPS_DQ23 C3 1.5-V SSTL Class I Data bus A3 DDR3_HPS_DQ24 A2 1.5-V SSTL Class I Data bus C3 DDR3_HPS_DQ25 A3 1.5-V SSTL Class I Data bus C8 DDR3_HPS_DQ26 P7 1.5-V SSTL Class I Data bus A7 DDR3_HPS_DQ27 C1 1.5-V SSTL Class I Data bus April 2014 Altera Corporation Arria V SoC Development Board Reference Manual 2-48 Chapter 2: Board Components Memory Table 2-28. DDR3 SDRAM Pin Assignments, Schematic Signal Names, and Functions (Part 4 of 5) Board Reference Schematic Signal Name Arria V SoC Pin Number I/O Standard Description C2 DDR3_HPS_DQ28 G2 1.5-V SSTL Class I Data bus A2 DDR3_HPS_DQ29 F2 1.5-V SSTL Class I Data bus B8 DDR3_HPS_DQ30 M3 1.5-V SSTL Class I Data bus D7 DDR3_HPS_DQ31 E1 1.5-V SSTL Class I Data bus F3 DDR3_HPS_DQS_P2 G4 Differential 1.5-V SSTL Class I Data strobe P byte lane 1 G3 DDR3_HPS_DQS_N2 H4 Differential 1.5-V SSTL Class I Data strobe P byte lane 0 C7 DDR3_HPS_DQS_P3 C2 Differential 1.5-V SSTL Class I Data strobe N byte lane 1 B7 DDR3_HPS_DQS_N3 D2 Differential 1.5-V SSTL Class I Data strobe N byte lane 0 K1 DDR3_HPS_ODT H7 1.5-V SSTL Class I On-die termination enable J3 DDR3_HPS_RASN G8 1.5-V SSTL Class I Row address select T2 DDR3_HPS_RESETN E3 1.5-V SSTL Class I Reset L3 DDR3_HPS_WEN J8 1.5-V SSTL Class I Write enable L8 DDR3_HPS_ZQ2 -- 1.5-V SSTL Class I ZQ impedance calibration N3 DDR3_HPS_A0 N9 1.5-V SSTL Class I Address bus P7 DDR3_HPS_A1 M9 1.5-V SSTL Class I Address bus P3 DDR3_HPS_A2 N10 1.5-V SSTL Class I Address bus N2 DDR3_HPS_A3 M10 1.5-V SSTL Class I Address bus P8 DDR3_HPS_A4 A8 1.5-V SSTL Class I Address bus DDR3 x16 (U38) P2 DDR3_HPS_A5 B7 1.5-V SSTL Class I Address bus R8 DDR3_HPS_A6 B9 1.5-V SSTL Class I Address bus R2 DDR3_HPS_A7 A9 1.5-V SSTL Class I Address bus T8 DDR3_HPS_A8 D9 1.5-V SSTL Class I Address bus R3 DDR3_HPS_A9 C10 1.5-V SSTL Class I Address bus L7 DDR3_HPS_A10 K7 1.5-V SSTL Class I Address bus R7 DDR3_HPS_A11 J7 1.5-V SSTL Class I Address bus N7 DDR3_HPS_A12 F9 1.5-V SSTL Class I Address bus T3 DDR3_HPS_A13 E9 1.5-V SSTL Class I Address bus T7 DDR3_HPS_A14 D11 1.5-V SSTL Class I Address bus M2 DDR3_HPS_BA0 L7 1.5-V SSTL Class I Bank address bus N8 DDR3_HPS_BA1 C9 1.5-V SSTL Class I Bank address bus M3 DDR3_HPS_BA2 D8 1.5-V SSTL Class I Bank address bus K3 DDR3_HPS_CASN G9 1.5-V SSTL Class I Row address select K9 DDR3_HPS_CKE R8 1.5-V SSTL Class I Column address select J7 DDR3_HPS_CLK_P A11 1.5-V SSTL Class I Differential output clock Arria V SoC Development Board Reference Manual April 2014 Altera Corporation Chapter 2: Board Components Memory 2-49 Table 2-28. DDR3 SDRAM Pin Assignments, Schematic Signal Names, and Functions (Part 5 of 5) Board Reference Schematic Signal Name Arria V SoC Pin Number I/O Standard Description K7 DDR3_HPS_CLK_N B10 1.5-V SSTL Class I Differential output clock L2 DDR3_HPS_CSN H9 1.5-V SSTL Class I Chip select E7 DDR3_HPS_DM0 C6 1.5-V SSTL Class I Write mask byte lane D3 DDR3_HPS_DM1 E4 1.5-V SSTL Class I Write mask byte lane F7 DDR3_HPS_DQ0 D7 1.5-V SSTL Class I Data bus F8 DDR3_HPS_DQ1 C7 1.5-V SSTL Class I Data bus F2 DDR3_HPS_DQ2 R10 1.5-V SSTL Class I Data bus E3 DDR3_HPS_DQ3 G7 1.5-V SSTL Class I Data bus H8 DDR3_HPS_DQ4 A6 1.5-V SSTL Class I Data bus H3 DDR3_HPS_DQ5 A7 1.5-V SSTL Class I Data bus G2 DDR3_HPS_DQ6 L6 1.5-V SSTL Class I Data bus H7 DDR3_HPS_DQ7 D6 1.5-V SSTL Class I Data bus C3 DDR3_HPS_DQ8 H6 1.5-V SSTL Class I Data bus A3 DDR3_HPS_DQ9 G6 1.5-V SSTL Class I Data bus A2 DDR3_HPS_DQ10 N8 1.5-V SSTL Class I Data bus D7 DDR3_HPS_DQ11 G5 1.5-V SSTL Class I Data bus A7 DDR3_HPS_DQ12 A4 1.5-V SSTL Class I Data bus B8 DDR3_HPS_DQ13 A5 1.5-V SSTL Class I Data bus C2 DDR3_HPS_DQ14 R9 1.5-V SSTL Class I Data bus C8 DDR3_HPS_DQ15 F4 1.5-V SSTL Class I Data bus F3 DDR3_HPS_DQS_P0 F7 Differential 1.5-V SSTL Class I Data strobe P byte lane 1 G3 DDR3_HPS_DQS_N0 E7 Differential 1.5-V SSTL Class I Data strobe P byte lane 0 C7 DDR3_HPS_DQS_P1 D5 Differential 1.5-V SSTL Class I Data strobe N byte lane 1 B7 DDR3_HPS_DQS_N1 E6 Differential 1.5-V SSTL Class I Data strobe N byte lane 0 K1 DDR3_HPS_ODT H7 1.5-V SSTL Class I On-die termination enable J3 DDR3_HPS_RASN G8 1.5-V SSTL Class I Row address select T2 DDR3_HPS_RESETN E3 1.5-V SSTL Class I Reset L3 DDR3_HPS_WEN J8 1.5-V SSTL Class I Write enable L8 DDR3_HPS_ZQ -- 1.5-V SSTL Class I ZQ impedance calibration April 2014 Altera Corporation Arria V SoC Development Board Reference Manual 2-50 Chapter 2: Board Components Memory QSPI Flash (HPS) The development board supports one 1-Gb serial NOR flash device for non-volatile storage of the HPS boot code, user data, and program. The device connects to the HPS dedicated interface and may contain a secondary boot code. This 4-bit data memory interface can sustain burst read operations at up to 108 MHz for a throughput of 54 MBps. Erase capability is at 4 KB, 64 KB, and 32 MB. Table 2-29 lists the QSPI flash pin assignments, signal names, and functions. The signal names and types are relative to the Arria V SoC in terms of I/O setting and direction. Table 2-29. QSPI Flash Schematic Signal Names and Functions Board Reference (U19) Schematic Signal Name Arria V SoC Pin Number I/O Standard Description 16 QSPI_CLK F15 3.3-V Clock 15 QSPI_IO0 D15 3.3-V Data bus 8 QSPI_IO1 G15 3.3-V Data bus 9 QSPI_IO2 M15 3.3-V Data bus 1 QSPI_IO3 H15 3.3-V Data bus 7 QSPI_SS0 N15 3.3-V Chip enable 3 MAX_QSPI_RSTN -- 3.3-V Reset EPCQ Flash The development board supports one 256-Mb serial/quad-serial NOR flash device for non-volatile storage of the FPGA configuration image. The device connects to the FPGA dedicated interface through the IDTQS3861 device. Table 2-29 lists the EPCQ flash pin assignments, signal names, and functions. The signal names and types are relative to the MAX V CPLD 5M2210 System Controller in terms of I/O setting and direction. Some pins are used in other interfaces as well due to functionality sharing. Table 2-30. EPCQ Flash Schematic Signal Names and Functions Board Reference (U28) Arria V SoC Development Board Reference Manual Schematic Signal Name I/O Standard Description 16 FPGA_DCLK 3.3-V Clock 15 FPGA_AS_DATA0 3.3-V Data bus 8 FPGA_AS_DATA1 3.3-V Data bus 9 FPGA_AS_DATA2 3.3-V Data bus 1 FPGA_AS_DATA3 3.3-V Data bus 7 FPGA_NCS0 3.3-V Chip enable April 2014 Altera Corporation Chapter 2: Board Components Memory 2-51 Synchronous Flash The development board supports a 512-Mb CFI-compatible synchronous flash device for non-volatile storage of FPGA configuration data, board information, and test application data. This device connects to the MAX V CPLD 5M2210 System Controller for FPGA configuration in FPP and PS modes. This 16-bit data memory interface can sustain burst read operations at up to 52 MHz for a throughput of 832 Mbps per device. The write performance is 270 s for a single word buffer while the erase time is 800 ms for a 128 K array block. Table 2-31 lists the flash pin assignments, signal names, and functions. The signal names and types are relative to the MAX V CPLD 5M2210 System Controller in terms of I/O setting and direction. Table 2-31. Flash Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 2) Board Reference (U13) April 2014 Altera Corporation Schematic Signal Name I/O Standard Description F6 FLASH_ADVN 1.8-V Address valid B4 FLASH_CEN0 1.8-V Chip enable E6 FLASH_CLK 1.8-V Clock F8 FLASH_OEN 1.8-V Output enable F7 FLASH_RDYBSYN 1.8-V Ready D4 FLASH_RESETN 1.8-V Reset G8 FLASH_WEN 1.8-V Write enable C6 FLASH_WPN 1.8-V Write protect A1 FSM_A1 1.8-V Address bus B1 FSM_A2 1.8-V Address bus C1 FSM_A3 1.8-V Address bus D1 FSM_A4 1.8-V Address bus D2 FSM_A5 1.8-V Address bus A2 FSM_A6 1.8-V Address bus C2 FSM_A7 1.8-V Address bus A3 FSM_A8 1.8-V Address bus B3 FSM_A9 1.8-V Address bus C3 FSM_A10 1.8-V Address bus D3 FSM_A11 1.8-V Address bus C4 FSM_A12 1.8-V Address bus A5 FSM_A13 1.8-V Address bus B5 FSM_A14 1.8-V Address bus C5 FSM_A15 1.8-V Address bus D7 FSM_A16 1.8-V Address bus D8 FSM_A17 1.8-V Address bus A7 FSM_A18 1.8-V Address bus B7 FSM_A19 1.8-V Address bus C7 FSM_A20 1.8-V Address bus Arria V SoC Development Board Reference Manual 2-52 Chapter 2: Board Components Memory Table 2-31. Flash Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 2) Board Reference (U13) Schematic Signal Name I/O Standard Description C8 FSM_A21 1.8-V Address bus A8 FSM_A22 1.8-V Address bus G1 FSM_A23 1.8-V Address bus H8 FSM_A24 1.8-V Address bus B6 FSM_A25 1.8-V Address bus B8 FSM_A26 1.8-V Address bus F2 FSM_D0 1.8-V Data bus E2 FSM_D1 1.8-V Data bus G3 FSM_D2 1.8-V Data bus E4 FSM_D3 1.8-V Data bus E5 FSM_D4 1.8-V Data bus G5 FSM_D5 1.8-V Data bus G6 FSM_D6 1.8-V Data bus H7 FSM_D7 1.8-V Data bus E1 FSM_D8 1.8-V Data bus E3 FSM_D9 1.8-V Data bus F3 FSM_D10 1.8-V Data bus F4 FSM_D11 1.8-V Data bus F5 FSM_D12 1.8-V Data bus H5 FSM_D13 1.8-V Data bus G7 FSM_D14 1.8-V Data bus E7 FSM_D15 1.8-V Data bus Micro SD Flash Memory The development board supports a micro SD card interface using x4 data lines. The HPS dedicated interface and the USB 2.0 OTG interface are mutually exclusive since both interfaces share some pins. The interface selection is done using the DIP switch. The data and control lines are multiplexed or demultiplexed using on the board's analog switches. The micro SD card interface may contain secondary boot code. This 4-bit data interface can sustain burst read operations at up to 50 MHz for a throughput of 25 MBps. Table 2-32 lists the micro SD flash memory interface pin assignments, signal names, and functions. The signal names and types are relative to the Arria V SoC in terms of I/O setting and direction. Table 2-32. Micro SD Flash Memory Interface Schematic Signal Names and Functions (Part 1 of 2) Board Reference (J5) Schematic Signal Name Arria V SoC Pin Number I/O Standard Description 5 SD_CLK L16 3.3-V Clock 7 SD_DAT0 C17 3.3-V Data bus Arria V SoC Development Board Reference Manual April 2014 Altera Corporation Chapter 2: Board Components Power Supply 2-53 Table 2-32. Micro SD Flash Memory Interface Schematic Signal Names and Functions (Part 2 of 2) Board Reference (J5) Schematic Signal Name Arria V SoC Pin Number I/O Standard Description 8 SD_DAT1 N16 3.3-V Data bus 1 SD_DAT2 J16 3.3-V Data bus 2 SD_CD_DAT3 M16 3.3-V Control or data bus 3 SD_CMD D16 3.3-V Control I2C EEPROM This board includes a 32 Kb EEPROM device. This device has a 2-wire I2C serial interface bus and is organized as four blocks of 4K x 8-bit memory. The main function of the device is for EtherCAT IP usage, but it can be used for other storage purposes as well. Table 2-33 lists the I2C EEPROM pin assignments, signal names, and functions. The signal names and types are relative to the Arria V SoC in terms of I/O setting and direction. Table 2-33. I2C EEPROM Schematic Signal Names and Functions Board Reference (U34) Schematic Signal Name Arria V SoC Pin Number I/O Standard Description 6 I2C_SCL_HPS L13 3.3-V Management serial clock 5 I2C_SDA_HPS C13 3.3-V Management serial data Power Supply You can power up the development board from a laptop-style DC power input or through the DC auxiliary connector. The Arria V SoC is designed in such way that the power rails for the HPS and FPGA are independent, allowing power down for the FPGA side when the HPS side is running. This eliminates power consumption on the FPGA part when not in use. Table 2-34 lists the maximum allowed draws of the power input. Table 2-34. Power Input Maximum Allowed Draws Source Laptop Supply--DC input DC auxiliary connector Voltage (V) Wattage (W) 16.0 300 20.0 200 12.0 200 An on-board multi-channel analog-to-digital converter (ADC) measures the current for several specific board rails. April 2014 Altera Corporation Arria V SoC Development Board Reference Manual 2-54 Chapter 2: Board Components Power Supply Power Distribution System Figure 2-9 shows the power distribution system on the development board. Regulator inefficiencies and sharing are reflected in the currents shown, which are conservative absolute maximum levels. Figure 2-9. Power Distribution System 0.130 A LTC3605 (5 A) Switching Regulator (+/- 2%) 0.003 A LTC3605 (5 A) Switching Regulator (+/- 2%) 0.043 A LTC3605 (5 A) Switching Regulator (+/- 2%) 0.593 A LTC3605 (5 A) Switching Regulator (+/- 2%) 1.15 V, 1.0824 A 1.5V_HPS A5ST HPS VCC 1.5 V, 0.021 A 1.5V_HPS VCCIO HPS, VDD DDR3 3.3V_HPS VCCPD, VCCIO, VDD ENET, EZ-USB, VDD-USB2OTG, VCC-RS232, VCC-CAN, VDD-QSPI Flash, VCC/Q Flash, VCC-SDCARD, VCC-EPCQ 3.3 V, 0.125 A 2.5 V, 2.278 A 0.760 A 0.001 A 2.5V_HPS_FILT VCCPLL, VCCAUX 0.767 A 2.5V_VCCAUX_SHARED HPS VCCAUX_SHARED BEAD BEAD LTC3022 1 A LDO 2.509 A LTC3866 (30 A) Switching Regulator (+/- 2%) 1.15 V, 20.946 A 1.2 V, 0.75 A LTC3605 (5 A) Switching Regulator (+/- 2%) 0.426 A LTC3605 (5 A) Switching Regulator (+/- 2%) DVD_ENET DVDD 19.12 A 1.5V_VCC A5ST FPGA VCC 1.826 A 1.15V_VCCP VCCP BEAD 0.107 A 2.5V_HPS VCCPD, VCCIO, VCCRST-CLK, VCCIO-MAXV, VCCIO-EPM570, AVDD, VDDO-ENET, Clocks 1.5 V, 0.890 A 1.5V_FPGA VCCIO, VDD DDR3 124 W Total DC AUX DC Input 19 V Ideal Diode Multiplexer 12 V, 7.553 A LTC3855 Dual Channel 3.3 V Controller 10.200 A 0.592 A LTM8025 (3 A) Switching Regulator (+/- 2%) 2.5 V, 1.634 A 2.5 V (Default) BEAD 2.301 A 0.867 A 2.5V_FPGA VCCPD, VCCPGM, VCCIO 0.767 A 2.5V_FPGA_AUX VCC_FPLL, VCCA, VCC_AUX 0.301 A VAR_VCCIO VCCIO FMC 2.000 A 1.15V_GXB VCCR_VCCL_GXB 1.15V_VCCT VCCT_GXB 1.5V_VCCD/VCCH VCCD, VCCH 0.860 A 0.370 A 0.140 A LTC3026 (1.5 A) Linear Regulator 0.860 A LTC3026 (1.5 A) Linear Regulator 0.370 A LTC3026 (1.5 A) Linear Regulator 5 V, 0.200 A 0.150 A LTC3509 (Dual 0.7 A) Switching Regulator (+/- 2%) 1.8 V, 0.200 A 0.140 A 12 V, 3.000 A 3.3 V, 8.830 A Arria V SoC Development Board Reference Manual FMC BEAD 5.0V USB, LTCEXT 1V8 VCCINT/IO-MAXV, VCC-CFI Flash, VCCINT-EMP570 12V_EXP PCIe, FMC 3.3V PCIe, ECAT-VDD, FMC April 2014 Altera Corporation Chapter 2: Board Components Power Supply 2-55 Power Measurement There are eleven power supply rails that have on-board current sense capabilities using 16-bit differential ADC devices. Precision sense resistors split the ADC devices and rails from the primary supply plane for the ADC to measure current. Figure 2-10 shows the block diagram for the power measurement circuitry. Figure 2-10. Power Measurement Circuit Embedded USB-Blaster II USB PHY EPM570 Feedback Supply #0-6 To User PC Power Supply Load #0-6 JTAG Chain R SENSE SPI Bus 8 Ch. MAX V CPLD 5M2210 System Controller Arria V SoC 14-pin E 2x16 RW RS Character D(0:7) LCD SCK DSI DSO CSn Table 2-35 lists the targeted rails. The schematic signal name column specifies the name of the rail being measured while the device pin column specifies the devices attached to the rail. Table 2-35. Power Measurement Rails (Part 1 of 2) Channel Schematic Signal Name Voltage (V) Device Pin Description VCCIO 0 2.5V_FPGA 2.5 VCCPD I/O, FPGA internal and peripheral devices VCC 1 1.5V_FPGA 1.5 VCCIO I/O and DDR3 devices 2 1.15V_VCC 1.15 VCC FPGA core power, transceiver, and clock 3 VAR_VCCIO 2.5, 1.8, 1.5, 1.2 VCCIO FMC I/O 4 1.15V_GXB 1.15 VCCR_GXB Receiver power VCCL_GXB Transceiver clock network 5 1.15V_VCCT 1.15 VCCT_GXB Transmitter power 6 1.5V_VCCD/VCCH 1.5 VCCD_FPLL Phase-locked loop (PLL) digital power VCCH_GXB Transmitter output buffer power 7 1.15V_HPS 1.15 VCC_HPS HPS core power 8 1.5V_HPS 1.5 VCCIO_HPS I/O and DDR3 devices April 2014 Altera Corporation Arria V SoC Development Board Reference Manual 2-56 Chapter 2: Board Components Power Supply Table 2-35. Power Measurement Rails (Part 2 of 2) Channel Schematic Signal Name Voltage (V) Device Pin Description VCCPD_HPS 9 2.5V_HPS 2.5 VCCIO_HPS I/O, HPS internal and peripheral devices VCC_AUX 10 3.3V_HPS Arria V SoC Development Board Reference Manual 3.3 VCCPD_HPS VCCIO_HPS I/O and HPS peripheral devices April 2014 Altera Corporation 3. Board Components Reference This chapter lists the component reference and manufacturing information of all the components on the Arria V SoC development board. Table 3-1. Component Reference and Manufacturing Information Board Reference Component Manufacturer Manufacturing Part Number Manufacturer Website U41 Arria V SoC FPGA F1517, 462,000 LEs, lead free Altera Corporation 5ASTFD5K3F40I3 www.altera.com U27 MAX V CPLD 5M2210 System Controller Altera Corporation 5M2210ZF256 www.altera.com U61 High-Speed USB peripheral controller Cypress CY7C68013A www.cypress.com Lumex Inc. SML-LXT0805GW-TR www.lumex.com D9-D16, D20-D24, D33-D36, D38-D43, Green LEDs D39 Red LED Lumex Inc. SML-LXT0805IW-TR www.lumex.com D37 Blue LED Lumex Inc. SML-LX0805USBC-TR www.lumex.com SW2, SW4 Four-position DIP switches C&K Components/ ITT Industries TDA04H0SB1 www.ckcomponents.com SW1, SW3 Eight-Position DIP switch C & K Components TDA08H0SB1 www.ckcomponents.com Panasonic EVQPAC07K www.panasonic.com S1-S9, S12-S14 Push buttons J17 External Mictor 38-pin connector X4 50 MHz 1.8-V oscillator Tyco Electronics 2-767004-2 www.te.com ECS, Inc. ECS-3518-500-B-xx www.ecsxtal.com X5 125.00 MHz LVDS crystal oscillator Epson EG-2121CA 125.0000M-LGPNL3 www.eea.epson.com U35 Programmable quad clock, I2C 0x70, defaults LVDS 156.25 MHz, 25 MHz, 25 MHz, 100 MHz default Silicon Labs Si5338C-A01917-GM www.silabs.com U42 IC - Pre-programmed (quad clock generator), 25, 25, 100, 100 MHZ LVCMOS, 1.8V, 2.5V Silicon Labs Si5335A-B02062-GM www.silabs.com U59 IC - PCIE Gen 1/2 dual output clock generator Silicon Labs SI52112-B3-GM2 www.silabs.com U30 1 to 3 single-ended clock buffer Silicon Labs SL18860DC www.silabs.com X2 Programmable LVDS clock 100M defaults Silicon Labs 570FAB000973DG www.silabs.com X3 Programmable LVDS clock 148.5M defaults Silicon Labs 571FAB000973DG www.silabs.com Samtec TSM-107-07-G-D www.samtec.com Lumex Inc. LCM-S01602DSR/C www.lumex.com J29 April 2014 2x7 pin LCD socket strip 2x16 character LCD, 5x8 dot matrix Altera Corporation Arria V SoC Development Board Reference Manual 3-2 Chapter 3: Board Components Reference Table 3-1. Component Reference and Manufacturing Information Board Reference Manufacturer Manufacturing Part Number Manufacturer Website Marvell Semiconductor 88E1111-B2CAA1C000 www.marvell.com Bel Fuse L829-1J1T-43 www.belfuse.com Wurth Elektronik 7499011121A www.we-online.com PCIE socket x4 Samtec PCIE-064-02-F-D-TH www.samtec.com FMC 0.050 pitch socket array assembly, 400 I/O, 40 x 10 configuration Samtec ASP-134486-01 www.samtec.com SFP+ right-angle, press-fit cage Molex 74754-0101 www.molex.com J443, J44 SFP+ right-angle, 20-pin SMT connector Samtec MECT-110-01-M-DRA1 www.samtec.com U25, U26 USB to serial UART interface Future Technology Devices International Ltd. FT232RQ www.ftdichip.com Real-time clock Maxim DS1339C www.maxim-ic.com 32M x 16 x 8, 1024-MB DDR3 SDRAM Micron MT41K256M16HA125:E www.micron.com U19 256-Mb QSPI flash Micron N25Q00AA13GSF40F www.micron.com U13 512-Mb CFI synchronous flash Numonyx PC28F512P30BF www.numonyx.com U28 256-Mb NOR flash Altera Corporation EPCQ256SI16N www.altera.com U34 32-Kb I2C EEPROM Microchip 24LC32A www.microchip.com Wurth Elektronik 693 071 010 811 www.we-online.com Linear Technology LTC2978 www.linear.com U7, U55 J13 J47, J48 J42 J4, J26 B5 U11 U29, U37, U38, U43, U44, U51 U49 J5 U26, U34 Component Ethernet PHY BASE-T devices MagJack 1000BaseT, 1x1 integrated connector module (ICM) RJ45 connector with integrated transformer Micro SD card socket Octal digital power supply manager with EEPROM Arria V SoC Development Board Reference Manual April 2014 Altera Corporation Chapter 3: Board Components Reference Statement of China-RoHS Compliance 3-3 Statement of China-RoHS Compliance Table 3-2 lists hazardous substances included with the kit. Table 3-2. Table of Hazardous Substances' Name and Concentration Part Name Arria V SoC development board Notes (1), (2) Lead (Pb) Cadmium (Cd) Hexavalent Chromium (Cr6+) Mercury (Hg) Polybrominated biphenyls (PBB) Polybrominated diphenyl Ethers (PBDE) X* 0 0 0 0 0 16 V power supply 0 0 0 0 0 0 Type A-B USB cable 0 0 0 0 0 0 User guide 0 0 0 0 0 0 Notes to Table 3-2: (1) 0 indicates that the concentration of the hazardous substance in all homogeneous materials in the parts is below the relevant threshold of the SJ/T11363-2006 standard. (2) X* indicates that the concentration of the hazardous substance of at least one of all homogeneous materials in the parts is above the relevant threshold of the SJ/T11363-2006 standard, but it is exempted by EU RoHS. CE EMI Conformity Caution This development kit is delivered conforming to relevant standards mandated by Directive 2004/108/EC. Because of the nature of programmable logic devices, it is possible for the user to modify the kit in such a way as to generate electromagnetic interference (EMI) that exceeds the limits established for this equipment. Any EMI caused as the result of modifications to the delivered material is the responsibility of the user. April 2014 Altera Corporation Arria V SoC Development Board Reference Manual 3-4 Arria V SoC Development Board Reference Manual Chapter 3: Board Components Reference CE EMI Conformity Caution April 2014 Altera Corporation Additional Information This chapter provides additional information about the board, document and Altera. Board Revision History The following table lists the versions of all releases of the Arria V SoC development board. Release Date December 2013 Version Description Engineering silicon Initial release. Document Revision History The following table lists the revision history for this document. Date Version April 2014 1.1 December 2013 1.0 Changes Corrected reference manual to include proper F1517 info. Corrected Table 2-8 ON/OFF descriptions. Initial release. How to Contact Altera To locate the most up-to-date information about Altera products, refer to the following table. Contact (1) Technical support Technical training Product literature Contact Method Address Website www.altera.com/support Website www.altera.com/training Email Website custrain@altera.com www.altera.com/literature Nontechnical support (general) Email nacomp@altera.com (software licensing) Email authorization@altera.com Note to Table: (1) You can also contact your local Altera sales office or sales representative. April 2014 Altera Corporation Arria V SoC Development Board Reference Manual Info-2 Additional InformationAdditional Information Typographic Conventions Typographic Conventions The following table shows the typographic conventions this document uses. Visual Cue Meaning Bold Type with Initial Capital Letters Indicate command names, dialog box titles, dialog box options, and other GUI labels. For example, Save As dialog box. For GUI elements, capitalization matches the GUI. bold type Indicates directory names, project names, disk drive names, file names, file name extensions, software utility names, and GUI labels. For example, \qdesigns directory, D: drive, and chiptrip.gdf file. Italic Type with Initial Capital Letters Indicate document titles. For example, Stratix IV Design Guidelines. Indicates variables. For example, n + 1. italic type Variable names are enclosed in angle brackets (< >). For example, <file name> and <project name>.pof file. Initial Capital Letters Indicate keyboard keys and menu names. For example, the Delete key and the Options menu. "Subheading Title" Quotation marks indicate references to sections in a document and titles of Quartus II Help topics. For example, "Typographic Conventions." Indicates signal, port, register, bit, block, and primitive names. For example, data1, tdi, and input. The suffix n denotes an active-low signal. For example, resetn. Courier type Indicates command line commands and anything that must be typed exactly as it appears. For example, c:\qdesigns\tutorial\chiptrip.gdf. Also indicates sections of an actual file, such as a Report File, references to parts of files (for example, the AHDL keyword SUBDESIGN), and logic function names (for example, TRI). r An angled arrow instructs you to press the Enter key. 1., 2., 3., and a., b., c., and so on Numbered steps indicate a list of items when the sequence of the items is important, such as the steps listed in a procedure. Bullets indicate a list of items when the sequence of the items is not important. 1 The hand points to information that requires special attention. h The question mark directs you to a software help system with related information. f The feet direct you to another document or website with related information. m The multimedia icon directs you to a related multimedia presentation. c A caution calls attention to a condition or possible situation that can damage or destroy the product or your work. w A warning calls attention to a condition or possible situation that can cause you injury. The envelope links to the Email Subscription Management Center page of the Altera website, where you can sign up to receive update notifications for Altera documents. The feedback icon allows you to submit feedback to Altera about the document. Methods for collecting feedback vary as appropriate for each document. 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