IRLZ44STRRPBF - Vishay [Siliconix]

Document Number: 91329 www.vishay.com

S11-1055-Rev. C, 30-May-11 1

This document is subject to change without notice.

THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

www.vishay.com/doc?91000

Power MOSFET

IRLZ44S, SiHLZ44S

Vishay Siliconix

FEATURES

•Halogen-free According to IEC 61249-2-21

Definition

• Surface Mount

• Available in Tape and Reel

• Dynamic dV/dt Rating

• Logic-Level Gate Drive

•R

DS(on) Specified at VGS = 4 V and 5 V

• 175 °C Operating Temperature

•Fast Switching

• Compliant to RoHS Directive 2002/95/EC

DESCRIPTION

Third generation Power MOSFETs from Vishay provide the

designer with the best combination of fast switching,

ruggedized device design, low on-resistance and

cost-effectiveness.

The D2PAK (TO-263) is a surface mount power package

capable of accommodating die sizes up to HEX-4. It

provides the highest power capability and the lowest

possible on-resistance in any existing surface mount

package. The D2PAK (TO-263) is suitable for high current

applications because of its low internal connection

resistance and can dissipate up to 2.0 W in a typical surface

mount application.

Note

a. See device orientation.

Notes

a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).

b. VDD = 25 V, starting TJ = 25 °C, L = 179 μH, Rg = 25 , IAS = 51 A (see fig. 12).

c. ISD  51 A, dI/dt  250 A/μs, VDD  VDS, TJ  175 °C.

d. 1.6 mm from case.

e. When mounted on 1" square PCB (FR-4 or G-10 material).

f. Current limited by the package, (die current = 51 A).

PRODUCT SUMMARY

VDS (V) 60

RDS(on) ()V

GS = 5.0 V 0.028

Qg (Max.) (nC) 66

Qgs (nC) 12

Qgd (nC) 43

Configuration Single

N-Channel MOSFET

PAK (TO-263)

ORDERING INFORMATION

Package D2PAK (TO-263) D2PAK (TO-263)

Lead (Pb)-free and Halogen-free SiHLZ44S-GE3 SiHLZ44STRR-GE3a

Lead (Pb)-free IRLZ44SPbF IRLZ44STRRPbFa

SiHLZ44S-E3 SiHLZ44STR-E3a

ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)

PARAMETER SYMBOL LIMIT UNIT

Drain-Source Voltage VDS 60 V

Gate-Source Voltage VGS ± 10

Continuous Drain Currentf

VGS at 5.0 V TC = 25 °C ID

Continuous Drain Current TC = 100 °C 36

Pulsed Drain CurrentaIDM 200

Linear Derating Factor 1.0 W/°C

Linear Derating Factor (PCB Mount)e0.025

Single Pulse Avalanche EnergybEAS 400 mJ

Maximum Power Dissipation TC = 25 °C PD

150 W

Maximum Power Dissipation (PCB Mount)eTA = 25 °C 3.7

Peak Diode Recovery dV/dtcdV/dt 4.5 V/ns

Operating Junction and Storage Temperature Range TJ, Tstg - 55 to + 175 °C

Soldering Recommendations (Peak Temperature)dfor 10 s 300d

* Pb containing terminations are not RoHS compliant, exemptions may apply

www.vishay.com Document Number: 91329

2S11-1055-Rev. C, 30-May-11

This document is subject to change without notice.

THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

www.vishay.com/doc?91000

IRLZ44S, SiHLZ44S

Vishay Siliconix

Note

a. When mounted on 1" square PCB (FR-4 or G-10 material).

Notes

a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).

b. Pulse width  300 μs; duty cycle  2 %.

c. Current limited by the package, (Die Current = 51 A).

THERMAL RESISTANCE RATINGS

PARAMETER SYMBOL TYP. MAX. UNIT

Maximum Junction-to-Ambient RthJA -62

°C/W

Maximum Junction-to-Ambient

(PCB Mount)aRthJA -40

Maximum Junction-to-Case (Drain) RthJC -1.0

SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)

PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT

Static

Drain-Source Breakdown Voltage VDS VGS = 0, ID = 250 μA 60 - - V

VDS Temperature Coefficient VDS/TJ Reference to 25 °C, ID = 1 mA - 0.070 - V/°C

Gate-Source Threshold Voltage VGS(th) VDS = VGS, ID = 250 μA 1.0 - 2.0 V

Gate-Source Leakage IGSS V

GS = ± 10 V - - ± 100 nA

Zero Gate Voltage Drain Current IDSS

VDS = 60 V, VGS = 0 V - - 25 μA

VDS = 48 V, VGS = 0 V, TJ = 150 °C - - 250

Drain-Source On-State Resistance RDS(on) VGS = 5.0 V ID = 31 Ab- - 0.028 

VGS = 4.0 V ID = 25 Ab- - 0.039

Forward Transconductance gfs VDS = 25 V, ID = 31 Ab23 - - S

Dynamic

Input Capacitance Ciss VGS = 0 V,

VDS = 25 V,

f = 1.0 MHz, see fig. 5

- 3300 -

pFOutput Capacitance Coss - 1200 -

Reverse Transfer Capacitance Crss - 200 -

Total Gate Charge Qg

VGS = 5.0 V ID = 51 A, VDS = 48 V,

see fig. 6 and 13b

--66

nC Gate-Source Charge Qgs --12

Gate-Drain Charge Qgd --43

Turn-On Delay Time td(on)

VDD = 30 V, ID = 51 A,

Rg = 4.6 , RD = 0.56 , see fig. 10b

-17-

Rise Time tr - 230 -

Turn-Off Delay Time td(off) -42-

Fall Time tf - 110 -

Internal Drain Inductance LD Between lead,

6 mm (0.25") from

package and center of

die contact

-4.5-

Internal Source Inductance LS-7.5-

Drain-Source Body Diode Characteristics

Continuous Source-Drain Diode Current ISMOSFET symbol

showing the

integral reverse

p - n junction diode

--50

Pulsed Diode Forward CurrentaISM - - 200

Body Diode Voltage VSD TJ = 25 °C, IS = 51 A, VGS = 0 Vb--2.5V

Body Diode Reverse Recovery Time trr TJ = 25 °C, IF = 51 A, dI/dt = 100 A/μsb- 130 180 ns

Body Diode Reverse Recovery Charge Qrr - 0.84 1.3 μC

Forward Turn-On Time ton Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)

Document Number: 91329 www.vishay.com

S11-1055-Rev. C, 30-May-11 3

This document is subject to change without notice.

THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

www.vishay.com/doc?91000

IRLZ44S, SiHLZ44S

Vishay Siliconix

TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)

Fig. 1 - Typical Output Characteristics, TC = 25 °C

Fig. 2 - Typical Output Characteristics, TC = 150 °C

Fig. 3 - Typical Transfer Characteristics

Fig. 4 - Normalized On-Resistance vs. Temperature

www.vishay.com Document Number: 91329

4S11-1055-Rev. C, 30-May-11

This document is subject to change without notice.

THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

www.vishay.com/doc?91000

IRLZ44S, SiHLZ44S

Vishay Siliconix

Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage

Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage

Fig. 7 - Typical Source-Drain Diode Forward Voltage

Fig. 8 - Maximum Safe Operating Area

Document Number: 91329 www.vishay.com

S11-1055-Rev. C, 30-May-11 5

This document is subject to change without notice.

THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

www.vishay.com/doc?91000

IRLZ44S, SiHLZ44S

Vishay Siliconix

Fig. 9 - Maximum Drain Current vs. Case Temperature

Fig. 10a - Switching Time Test Circuit

Fig. 10b - Switching Time Waveforms

Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case

Pulse width ≤ 1 µs

Duty factor ≤ 0.1 %

VGS

D.U.T.

5 V

VDS

VDD

VDS

90 %

10 %

VGS

td(on) trtd(off) tf

www.vishay.com Document Number: 91329

6S11-1055-Rev. C, 30-May-11

This document is subject to change without notice.

THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

www.vishay.com/doc?91000

IRLZ44S, SiHLZ44S

Vishay Siliconix

Fig. 12a - Unclamped Inductive Test Circuit Fig. 12b - Unclamped Inductive Waveforms

Fig. 12c - Maximum Avalanche Energy vs. Drain Current

Fig. 13a - Basic Gate Charge Waveform Fig. 13b - Gate Charge Test Circuit

IAS

0.01 Ω

D.U.T.

VDS

-VDD

5 V

Vary tp to obtain

required IAS

QGS QGD

Charge

5 V

D.U.T.

3 mA

VGS

VDS

IGID

0.3 µF

0.2 µF

50 kΩ

12 V

Current regulator

Current sampling resistors

Same type as D.U.T.

Document Number: 91329 www.vishay.com

S11-1055-Rev. C, 30-May-11 7

This document is subject to change without notice.

THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

www.vishay.com/doc?91000

IRLZ44S, SiHLZ44S

Vishay Siliconix

Fig. 14 - For N-Channel

Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon

Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and

reliability data, see www.vishay.com/ppg?91329.

P.W. Period

dI/dt

Diode recovery

dV/dt

Ripple ≤ 5 %

Body diode forward drop

Re-applied

voltage

Reverse

recovery

current

Body diode forward

current

VGS = 10 Va

ISD

Driver gate drive

D.U.T. lSD waveform

D.U.T. VDS waveform

Inductor current

D = P.W.

Period

Peak Diode Recovery dV/dt Test Circuit

VDD

• dV/dt controlled by Rg

• Driver same type as D.U.T.

• ISD controlled by duty factor “D”

• D.U.T. - device under test

D.U.T. Circuit layout considerations

• Low stray inductance

• Ground plane

• Low leakage inductance

current transformer

Note

a. VGS = 5 V for logic level devices

VDD

AN826

Vishay Siliconix

Document Number: 73397

11-Apr-05

www.vishay.com

RECOMMENDED MINIMUM PADS FOR D2PAK: 3-Lead

0.635

(16.129)

Recommended Minimum Pads

Dimensions in Inches/(mm)

0.420

(10.668)

0.355

(9.017)

0.145

(3.683)

0.135

(3.429)

0.200

(5.080)

0.050

(1.257)

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Revision: 12-Mar-12 1Document Number: 91000

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