1
EXTENDED COMMERCIAL TEMPERATURE RANGE
IDT74ALVC16820
3.3V CMOS 10-BIT FLIP-FLOP WITH DUAL 3-STATE OUTPUTS
AUGUST 1999
1999 Integrated Device Technology, Inc. DSC-4541/1c
IDT74ALVC16820
EXTENDED COMMERCIAL TEMPERATURE RANGE
3.3V CMOS 10-BIT
FLIP-FLOP WITH DUAL
3-STATE OUTPUTS
DESCRIPTION:
This 10-bit flip-flop is built using advanced dual metal CMOS technol-
ogy. The flip-flops of the ALVC16820 are edge-triggered D-type flip-
flops. On the positive transition of the clock (CLK) input, the device
provides true data at the Q outputs.
A buffered output-enable (OE) input can be used to place the ten
outputs in either a normal logic state (high or low logic level) or a high-
impedance state. In the high impedance state, the outputs neither load
nor drive the bus lines significantly. The high-impedance state and
increased drive provide the capability to drive bus lines without the need
for interface or pullup components. OE input does not affect the internal
operation of the flip-flops. Old data can be retained or new data can be
entered while the outputs are in the high-impedance state.
The ALVC16820 has been designed with a ±24mA output driver.
This driver is capable of driving a moderate to heavy load while
maintaining speed performance.
APPLICATIONS:
• SDRAM Modules
• PC Motherboards
• Workstations
FEATURES:
– 0.5 MICRON CMOS Technology
–Typical t
SK(0) (Output Skew) < 250ps
– ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
– 0.635mm pitch SSOP, 0.50mm pitch TSSOP,
and 0.40mm pitch TVSOP packages
– Extended commercial range of – 40°C to + 85°C
–V
CC = 3.3V ± 0.3V, Normal Range
–V
CC = 2.7V to 3.6V, Extended Range
–V
CC = 2.5V ± 0.2V
– CMOS power levels (0.4µW typ. static)
– Rail-to-Rail output swing for increased noise margin
Drive Features for ALVC16820:
– High Output Drivers: ±24mA
– Suitable for heavy loads
FUNCTIONAL BLOCK DIAGRAM
C1
D1
TO 9 OTHER CHANNELS
1OE 1
56
28
31Q2
2OE
CLK
D155
1Q1
2
2
EXTENDED COMMERCIAL TEMPERATURE RANGE
IDT74ALVC16820
3.3V CMOS 10-BIT FLIP-FLOP WITH DUAL 3-STATE OUTPUTS
1998 Integrated Device Technology, Inc. DSC-123456c
PIN CONFIGURATION
SSOP/
TSSOP/ TVSOP
TOP VIEW
NOTE:
1. H = HIGH Voltage Le vel
L = LOW V oltage Le v el
X = Don’t Care
Z = High-Impedance
- = LOW -to-HIGH Transition
Q0 = Output level before the indicated steady-state input conditions were
established
FUNCTION TABLE (each flip-flop)(1)
PIN DESCRIPTION
ABSOLUTE MAXIMUM RATING (1)
Symbol Description Max. Unit
VTERM(2) Terminal Voltage
with Respect to GND – 0.5 to + 4.6 V
VTERM(3) Terminal Voltage
with Respect to GND – 0.5 to
VCC + 0.5 V
TSTG Storage Temperature – 65 to + 150 °C
IOUT DC Output Current – 50 to + 50 mA
IIK Continuous Clamp Current,
VI < 0 or VI > VCC ± 50 mA
IOK Continuous Clamp Current, VO < 0 – 50 mA
ICC
ISS Continuous Current through
each VCC or GND ±100 mA
NEW16link
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other c onditions above t hose indicated in the operational s ections
of this specification is not implied. Exposure to absolute maximum
rating condit i ons for extended periods may aff ec t reliability.
2. VCC terminals.
3. All terminals exc ept V CC.
CAPACITANCE (TA = +25oC, f = 1.0MHz)
Symbol Parameter(1) Conditions Typ. Max. Unit
CIN Input Capacitance VIN = 0V 5 7 pF
COUT Output
Capacitance VOUT = 0V 7 9 pF
CI/O I/O Port
Capacitance VIN = 0V 7 9 pF
NEW16link
NOTE:
1. As appl i cable to the devic e type.
Pin Names Description
Dx Data Inputs
CLK Clock Input
xQx 3–State Outputs
xOE 3–State Output Enable Inputs (Active LOW)
Inputs Outputs
xOE CLK Dx xQx
L↑HH
L
↑
LL
LLX Q
O
HXX Z
1
OE
1Q1
GND
1Q2
VCC
3Q1
3Q2
GND
4Q1
4Q2
5Q1
5Q2
2Q2
6Q1
GND
6Q2
7Q1
7Q2
VCC
8Q1
SO56-1
SO56-2
SO56-3
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
48
49
50
51
52
53
54
55
561 CLK
D1
GND
VCC
GND
GND
10Q1
GND
9Q1
2OE
25
26
27
28
32
31
30
29
GND
9Q2
2Q1
8Q2
VCC
NC
10Q2
NC
NC
D3
D2
D4
NC
NC
NC
D5
D6
NC
NC
D7
D8
NC
NC
D9
D10
NC
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EXTENDED COMMERCIAL TEMPERATURE RANGE
IDT74ALVC16820
3.3V CMOS 10-BIT FLIP-FLOP WITH DUAL 3-STATE OUTPUTS
OUTPUT DRIVE CHARACTERISTICS
NOTE:
1. VIH and VIL must be within the min. or max. range shown in the DC ELE CTRICAL CHARACTE RISTI CS OVER OPE RATING RA NGE table f or the
appropriate VCC range. T A = – 40° C t o + 85° C.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions A pply Unless Otherwise S pecified:
Operating Condition: TA = – 40°C to +85°C
Symbol Param e t e r Test C ondit ions Min. Typ.(1) Max. Unit
VIH Input HIGH Voltage Level VCC = 2.3V to 2.7V 1.7 — — V
VCC = 2.7V to 3.6V 2 — —
VIL Input LOW Voltage Level VCC = 2.3V to 2.7V — — 0.7 V
VCC = 2.7V to 3.6V — — 0.8
IIH Input HIGH Current VCC = 3.6V VI = VCC ——± 5µA
I
IL Input LOW Current VCC = 3.6V VI = GND — — ± 5
IOZH High Impedance Output C urrent VCC = 3.6V VO = VCC ——± 10µA
I
OZL (3-Sta te Output p ins) VO = GN D — — ± 10 µA
VIK Clamp Diode Voltage VCC = 2.3V, IIN = – 18mA — – 0.7 – 1.2 V
VHInput Hysteresis VCC = 3.3V — 100 — mV
ICCL
ICCH
ICCZ
Quiescent Power Supply Current VCC = 3.6V
VIN = GND or VCC —0.140µA
∆
I
CC Quiescent Power Supply
Current Variation One input at V CC − 0.6V,
other inputs at VCC or GND — — 750 µA
NEW16lin
k
NOTE:
1. Typic al v al ues are at VCC = 3.3V, +25°C am bi ent.
Symbol Parameter Test Conditi ons(1) Min. Max. Unit
VOH Output HIGH Voltage VCC = 2.3V to 3.6V IOH = – 0.1mA VCC – 0.2 — V
VCC = 2.3V IOH = – 6mA 2 —
VCC = 2.3V IOH = – 12mA 1.7 —
VCC = 2.7V 2.2 —
VCC = 3.0V 2.4 —
VCC = 3.0V IOH = – 24mA 2 —
VOL Output LOW Voltage VCC = 2.3V to 3.6V IOL = 0.1mA — 0.2 V
VCC = 2.3V IOL = 6mA — 0.4
IOL = 12mA — 0.7
VCC = 2.7V IOL = 12mA — 0.4
VCC = 3.0V IOL = 24mA — 0.55 NEW16link
4
EXTENDED COMMERCIAL TEMPERATURE RANGE
IDT74ALVC16820
3.3V CMOS 10-BIT FLIP-FLOP WITH DUAL 3-STATE OUTPUTS
SWITCHING CHARACTERISTICS(1)
OPERATING CHARACTERISTICS, TA = 25oCVCC = 2.5V ± 0.2V VCC = 3.3V ± 0.3V
Symbol Parameter Test Conditi ons Typical Typical Unit
CPD Power Dissipation Capacitance per flip-flop
Outputs enabled CL = 0pF, f = 10Mhz 60 63 pF
CPD Power Dissipation Capacitance per flip-flop
Outputs disabled 38 46 pF
VCC = 2.5V ± 0.2V VCC = 2.7V VCC = 3.3V ± 0.3V VCC = 3.3V ± 0.15V
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit
tPLH
tPHL Propagation Delay,
CLK to xQx 1 5.9 — 5.5 — 4.5 1 4 ns
tPZH
tPZL Output Enable Time,
xOE to xQx 1 6.4 — 6.1 — 5.7 1 5 ns
tPHZ
tPLZ Output Disable Time,
xOE to xQx 1 5.7 — 5 — 4.5 1.3 4.5 ns
tWPulse Width, CLK HIGH or LOW 3.3 — 3.3 — 3.3 — 3.3 — ns
tSU Set-up Time, HIGH or LOW,
data before CLK↑1.7 — 1.8 — 1.4 — 1.4 — ns
tHHold Time, HIGH or LOW,
data after CLK↑1.1 — 1.1 — 1 — 1 — ns
tSK(O) Output Skew(2) ———————500ps
NOTES:
1. See test circuit s and waveforms. TA = – 40°C to + 85°C.
2. Skew between any two outputs of the same package and switching in the s am e di rection.
5
EXTENDED COMMERCIAL TEMPERATURE RANGE
IDT74ALVC16820
3.3V CMOS 10-BIT FLIP-FLOP WITH DUAL 3-STATE OUTPUTS
Open
VLOAD
GND
VCC
Pulse
Generator D.U.T.
500Ω
500Ω
CL
RT
VIN VOUT
(1, 2 )
ALVC Link
INPUT
VIH
0V
VOH
VOL
tPLH1
tSK (x)
OUTPU T 1
OUTPU T 2
tPHL1
tSK (x)
tPLH2 tPHL2
VT
VT
VOH
VT
VOL
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
ALVC Link
SAME PHAS E
INPUT TRANSITION
OPPOSITE PHASE
INPUT TRANSITION
0V
0V
VOH
VOL
tPLH tPHL
tPHL
tPLH
OUTPUT
VIH
VT
VT
VIH
VT
ALVC Link
DATA
INPUT 0V
0V
0V
0V
tREM
TIMING
INPUT
SYNCHRONOUS
CONTROL
tSU tH
tSU tH
VIH
VT
VIH
VT
VIH
VT
VIH
VT
ALVC Link
ASYNCHRONOUS
CONTROL
LOW-HIGH-LOW
PULSE
HIGH-LOW-HIGH
PULSE
VT
tW
VT
ALVC Link
CONTROL
INPUT tPLZ 0V
OUTPUT
NORMALLY
LOW tPZH
0V
SWITCH
CLOSED
OUTPUT
NORMALLY
HIGH
ENABLE DISABLE
SWITCH
OPEN
tPHZ
0V
VOL + VLZ
VOH
VT
VT
tPZL
VLOAD/2 VLOAD/2
VIH
VT
VOL
VOH - VHZ
ALVC Link
NOTES:
1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For tSK(b) OUTPUT1 and OUTPUT2 are in the sam e bank .
TEST CIRCUITS AND WAVEFORMS
TEST CONDITIONS PROPAGATION DELAY
TEST CIRCUITS FOR ALL OUTPUTS ENABLE AND DISABLE TIMES
SET-UP, HOLD, AND RELEASE TIMES
SWITCH POSITION
OUTPUT SKEW - TSK (x)
Symbol
VCC(1)= 3.3V±0.3V VCC(1)= 2.7V VCC(2)= 2.5V±0.2V Unit
VLOAD 662 x VccV
V
IH 2.7 2.7 Vcc V
VT1.5 1.5 Vcc / 2 V
VLZ 300 300 150 mV
VHZ 300 300 150 mV
CL50 50 30 pF
NEW16link
Test Switch
Open Drain
Disable Low
Enable Low
VLOAD
Disable High
Enable High GND
All Other tests Open NEW16link
DEFINITIONS:
CL= Load capac i tance: includes j ig and probe capaci t ance.
RT = Termination resistanc e: should be equal to ZOUT of the Pul s e
Generator. NOTE:
1. Diagram s hown for input Control Enab l e-LOW and i nput Control
Disable-HIGH.
NOTES:
1. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
2. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns.
PULSE WIDTH
6
EXTENDED COMMERCIAL TEMPERATURE RANGE
IDT74ALVC16820
3.3V CMOS 10-BIT FLIP-FLOP WITH DUAL 3-STATE OUTPUTS
CORPORATE HEADQUARTERS for SALES:
2975 Stender Way 800-345-7015 or 408-727-6116
Santa Clara, CA 95054 fax: 408-492-8674
www.idt.com*
*To search for sales office near you, please click the sales button found on our home page or dial the 800# above and press 2.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
ORDERING INFORMATION
IDT XX ALVC XXX XX
PackageDevice Type
Temp. Range
PV
PA
PF
16
74
Shrink S mall Outline P a c ka ge (S O56-1)
Thin S hr in k Sm al l O utlin e P ac k ag e (S O56-2)
Thin V er y Sm a ll O u tlin e P a ck ag e (S O 5 6- 3)
10-Bit Flip-Flop with Dual 3-State Outputs
–40°C to +85°C
XXX
FamilyBus-Hold
820
No Bus-Hold
Double-Density with Resistors, ±24mA
Blank
