IDT74ALVC16820 3.3V CMOS 10-BIT FLIP-FLOP WITH DUAL 3-STATE OUTPUTS EXTENDED COMMERCIAL TEMPERATURE RANGE 3.3V CMOS 10-BIT FLIP-FLOP WITH DUAL 3-STATE OUTPUTS IDT74ALVC16820 DESCRIPTION: FEATURES: - - - 0.5 MICRON CMOS Technology Typical tSK(0) (Output Skew) < 250ps ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) - 0.635mm pitch SSOP, 0.50mm pitch TSSOP, and 0.40mm pitch TVSOP packages - Extended commercial range of - 40C to + 85C - VCC = 3.3V 0.3V, Normal Range - VCC = 2.7V to 3.6V, Extended Range - VCC = 2.5V 0.2V - CMOS power levels (0.4 W typ. static) - Rail-to-Rail output swing for increased noise margin Drive Features for ALVC16820: - High Output Drivers: 24mA - Suitable for heavy loads This 10-bit flip-flop is built using advanced dual metal CMOS technology. The flip-flops of the ALVC16820 are edge-triggered D-type flipflops. On the positive transition of the clock (CLK) input, the device provides true data at the Q outputs. A buffered output-enable (OE) input can be used to place the ten outputs in either a normal logic state (high or low logic level) or a highimpedance state. In the high impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without the need for interface or pullup components. OE input does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. The ALVC16820 has been designed with a 24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance. APPLICATIONS: * SDRAM Modules * PC Motherboards * Workstations FUNCTIONAL BLOCK DIAGRAM 1 1 OE 2 OE C LK 28 2 56 C1 D1 55 3 1Q 1 1Q 2 D1 TO 9 O TH ER C HA NN ELS EXTENDED COMMERCIAL TEMPERATURE RANGE AUGUST 1999 1 c 1999 Integrated Device Technology, Inc. DSC-4541/1 IDT74ALVC16820 3.3V CMOS 10-BIT FLIP-FLOP WITH DUAL 3-STATE OUTPUTS EXTENDED COMMERCIAL TEMPERATURE RANGE ABSOLUTE MAXIMUM RATING PIN CONFIGURATION Symbol VTERM(2) (1) 1 OE 1 56 CLK 1Q 1 2 55 D1 1Q 2 3 54 NC TSTG GND 4 Description Terminal Voltage with Respect to GND Terminal Voltage with Respect to GND Storage Temperature 53 GND IOUT 5 DC Output Current 2Q 1 52 D2 IIK mA 6 51 NC V CC 7 50 V CC IOK Continuous Clamp Current, VI < 0 or VI > VCC Continuous Clamp Current, VO < 0 50 2Q 2 - 50 mA ICC ISS Continuous Current through each VCC or GND 100 mA 3Q 1 8 49 D3 3Q 2 9 48 NC 4Q 1 10 47 D4 GND 11 46 GND 4Q 2 12 45 NC 5Q 1 13 44 14 6Q 1 15 SO56-1 SO56-2 43 SO56-3 42 D5 5Q 2 6Q 2 16 41 NC 7Q 1 17 40 D7 GND 18 39 GND 7Q 2 19 38 NC 20 37 D8 8Q 2 21 36 NC V CC 22 35 V CC 23 34 D9 9Q 2 24 33 NC GND 25 32 GND 10 Q 1 26 31 D 10 27 30 NC 28 29 NC 8Q 1 9Q 1 10 Q 2 2 OE VTERM(3) Pin Names Unit V - 0.5 to VCC + 0.5 - 65 to + 150 V C - 50 to + 50 mA NEW16link NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VCC terminals. 3. All terminals except VCC. NC D6 CAPACITANCE (TA = +25oC, f = 1.0MHz) Symbol CIN Parameter(1) Input Capacitance Conditions VIN = 0V Typ. 5 Max. 7 Unit pF COUT Output Capacitance I/O Port Capacitance VOUT = 0V 7 9 pF VIN = 0V 7 9 pF CI/O NEW16link NOTE: 1. As applicable to the device type. FUNCTION TABLE (each flip-flop)(1) Inputs SSOP/ TSSOP/ TVSOP TOP VIEW PIN DESCRIPTION Max. - 0.5 to + 4.6 Outputs xOE L CLK Dx H xQx H L L L L L X QO H X X Z NOTE: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care Z = High-Impedance Description Dx Data Inputs - = LOW-to-HIGH Transition CLK Clock Input xQx 3-State Outputs Q0 = Output level before the indicated steady-state input conditions were established xOE 3-State Output Enable Inputs (Active LOW) c 1998 Integrated Device Technology, Inc. 2 DSC-123456 IDT74ALVC16820 3.3V CMOS 10-BIT FLIP-FLOP WITH DUAL 3-STATE OUTPUTS EXTENDED COMMERCIAL TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = - 40C to +85C Symbol VIH Parameter Input HIGH Voltage Level VCC = 2.3V to 2.7V Min. 1.7 Typ.(1) -- Max. -- VCC = 2.7V to 3.6V 2 -- -- VCC = 2.3V to 2.7V -- -- 0.7 Test Conditions Unit V VIL Input LOW Voltage Level -- -- 0.8 IIH Input HIGH Current VCC = 3.6V VI = VCC -- -- 5 IIL Input LOW Current VCC = 3.6V VI = GND -- -- 5 IOZH High Impedance Output Current VCC = 3.6V VO = VCC -- -- 10 A IOZL (3-State Output pins) VO = GND -- -- 10 A VIK Clamp Diode Voltage VCC = 2.3V, IIN = - 18mA -- - 0.7 - 1.2 V VH Input Hysteresis VCC = 3.3V -- 100 -- mV ICCL ICCH ICCZ ICC Quiescent Power Supply Current VCC = 3.6V VIN = GND or VCC -- 0.1 40 A Quiescent Power Supply Current Variation One input at VCC - 0.6V, other inputs at VCC or GND -- -- 750 A VCC = 2.7V to 3.6V V A NEW16link NOTE: 1. Typical values are at VCC = 3.3V, +25C ambient. OUTPUT DRIVE CHARACTERISTICS Symbol VOH VOL Parameter Output HIGH Voltage Output LOW Voltage VCC Test Conditions(1) = 2.3V to 3.6V IOH = - 0.1mA VCC = 2.3V IOH = - 6mA VCC = 2.3V IOH = - 12mA Min. VCC - 0.2 Max. -- 2 -- 1.7 -- VCC = 2.7V 2.2 -- VCC = 3.0V 2.4 -- VCC = 3.0V IOH = - 24mA 2 -- VCC = 2.3V to 3.6V IOL = 0.1mA -- 0.2 VCC = 2.3V IOL = 6mA -- 0.4 IOL = 12mA -- 0.7 VCC = 2.7V IOL = 12mA -- 0.4 VCC = 3.0V IOL = 24mA -- 0.55 Unit V V NEW16link NOTE: 1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range. TA = - 40C to + 85C. 3 IDT74ALVC16820 3.3V CMOS 10-BIT FLIP-FLOP WITH DUAL 3-STATE OUTPUTS EXTENDED COMMERCIAL TEMPERATURE RANGE OPERATING CHARACTERISTICS, TA = 25oC Symbol CPD CPD Parameter Power Dissipation Capacitance per flip-flop Outputs enabled Power Dissipation Capacitance per flip-flop Outputs disabled Test Conditions CL = 0pF, f = 10Mhz VCC = 2.5V 0.2V VCC = 3.3V 0.3V Typical 60 Typical 63 38 46 Unit pF pF SWITCHING CHARACTERISTICS(1) VCC = 2.5V 0.2V VCC = 2.7V VCC = 3.3V 0.3V VCC = 3.3V 0.15V Symbol tPLH tPHL tPZH tPZL tPHZ tPLZ tW Parameter Propagation Delay, CLK to xQx Output Enable Time, xOE to xQx Output Disable Time, xOE to xQx Pulse Width, CLK HIGH or LOW Min. 1 Max. 5.9 Min. -- Max. 5.5 Min. -- Max. 4.5 Min. 1 Max. 4 Unit ns 1 6.4 -- 6.1 -- 5.7 1 5 ns 1 5.7 -- 5 -- 4.5 1.3 4.5 ns 3.3 -- 3.3 -- 3.3 -- 3.3 -- ns tSU Set-up Time, HIGH or LOW, data before CLK Hold Time, HIGH or LOW, data after CLK Output Skew(2) 1.7 -- 1.8 -- 1.4 -- 1.4 -- ns 1.1 -- 1.1 -- 1 -- 1 -- ns -- -- -- -- -- -- -- 500 ps tH tSK(O) NOTES: 1. See test circuits and waveforms. TA = - 40C to + 85C. 2. Skew between any two outputs of the same package and switching in the same direction. 4 IDT74ALVC16820 3.3V CMOS 10-BIT FLIP-FLOP WITH DUAL 3-STATE OUTPUTS EXTENDED COMMERCIAL TEMPERATURE RANGE TEST CIRCUITS AND WAVEFORMS TEST CONDITIONS PROPAGATION DELAY Symbol VLOAD VCC(1)= 3.3V0.3V VCC(1)= 2.7V VCC(2)= 2.5V0.2V 6 6 2 x Vcc Unit V VIH 2.7 2.7 Vcc V SAME PHASE INPUT TRANSITION VT 1.5 1.5 Vcc / 2 V OUTPUT VLZ 300 300 150 mV VHZ 300 300 150 mV CL 50 50 30 tPLH tPHL tPLH tPHL V IH VT 0V V OH VT V OL V IH VT 0V OPPOSITE PHASE INPUT TRANSITION pF NEW16link ALVC Link TEST CIRCUITS FOR ALL OUTPUTS ENABLE AND DISABLE TIMES V LOAD V CC 500 (1, 2) V IN CONTROL INPUT GND tPZL V OUT Pulse Generator D.U.T. OUTPUT SWITCH NORMALLY CLOSED LOW tPZH OUTPUT SWITCH NORMALLY OPEN HIGH 500 RT CL ALVC Link DEFINITIONS: CL= Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. NOTES: 1. Pulse Generator for All Pulses: Rate 10MHz; tF 2.5ns; tR 2.5ns. 2. Pulse Generator for All Pulses: Rate 10MHz; tF 2ns; tR 2ns. Switch VLOAD SYNCHRONOUS CONTROL Open tPHL1 tSK (x) tPHZ VT V OH V OH - V HZ 0V 0V tSU V IH VT 0V V IH VT 0V V IH VT 0V V IH VT 0V tH tREM tSU tH V IH VT 0V PULSE WIDTH V OH OUTPUT 1 V OL + V LZ V OL ALVC Link (x) tPLH1 V LOAD/2 VT ASYNCHRONOUS CONTROL NEW16link INPUT V LOAD/2 TIMING INPUT GND TSK 0V SET-UP, HOLD, AND RELEASE TIMES DATA INPUT Test Open Drain Disable Low Enable Low Disable High Enable High All Other tests tPLZ V IH VT ALVC Link NOTE: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. SWITCH POSITION OUTPUT SKEW - DISABLE ENABLE Open LOW-HIGH-LOW PULSE VT V OL tSK (x) tW V OH VT V OL OUTPUT 2 VT HIGH-LOW-HIGH PULSE VT ALVC Link tPLH2 tPHL2 tSK (x) = tPLH2 - tPLH1 or tPHL2 - tPHL1 ALVC Link NOTES: 1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs. 2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank. 5 IDT74ALVC16820 3.3V CMOS 10-BIT FLIP-FLOP WITH DUAL 3-STATE OUTPUTS EXTENDED COMMERCIAL TEMPERATURE RANGE ORDERING INFORMATION IDT XX X XX Bus-Hold Family ALVC Temp. Range XXX XX Device Type Package PV PA PF Shrink Small Outline Package (SO56-1) Thin Shrink Small Outline Package (SO56-2) Thin Very Small Outline Package (SO56-3) 820 10-Bit Flip-Flop with Dual 3-State Outputs 16 Double-Density with Resistors, 24mA Blank No Bus-Hold 74 CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 -40C to +85C for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com* *To search for sales office near you, please click the sales button found on our home page or dial the 800# above and press 2. The IDT logo is a registered trademark of Integrated Device Technology, Inc. 6