TP3465
TP3465 MICROWIRE(TM) Interface Device (MID)
Literature Number: SNOS569
TL/H/10803
TP3465MICROWIREInterfaceDevice(MID)
July 1999
TP3465MICROWIRETM InterfaceDevice(MID)
GeneralDescription
TheMICROWIRETM InterfaceDeviceMIDgivesageneral
microprocessor(suchasNationalSeries32000Éproces-
sors,Intel80C188,80C86or80286,Motorola6800and
68000familyofprocessors)theabilitytocommunicateeffi-
cientlywithuptoeightperipheraldevicesviatheserialMI-
CROWIREinterface.TheMIDcauseseachoftheperipheral
devicestoappeartothemPasmemorymappedlocations,
byperformingallthedataserializationandtransferproto-
colstoandfromtheperipherals.
Applications
YISDNTerminalAdapters
YDigitalLinecards(ISDNandNonISDN)
YAnalogLinecardsusingNationalCOMBOÉ
YInterfacingtoindustrystandardserialEEPROMs
YInterfacingtoindustrystandardMICROWIREperipheral
devicessuchasAnalogtoDigitalConverters,LCDdriv-
ers,clockgenerators
Features
YMultiplexedandNon-multiplexedmicroprocessorbus
compatible
YNational/IntelandMotorolamicroprocessorbus
compatible
YMicroprocessorClock(CKIN)upto20MHz
YMICROWIREclockspeedsupto5MHz
YDirectlycompatiblewith8-and16-bitMICROWIRE
peripherals
YCommercial temperature range 0C to +70C
YTP3465for8ChipSelectoutput
YMemorymappedperipherals
YProgrammableMICROWIREClocktocommunicatewith
devicesofdifferentspeeds
YOperatesasMICROWIREbusmasterorslave
Y28-pinPLCC Package
YCMOS,LowPower
BlockDiagram
TL/H/10803–1
FIGURE1.MICROWIREInterfaceDeviceMID
COMBOÉ,Series32000ÉandTRI-STATEÉareregisteredtrademarksofNationalSemiconductorCorporation.
MICROWIRETMisatrademarkofNationalSemiconductorCorporation.
C1999 NationalSemiconductorCorporation
ConnectionDiagrams
28-PinPLCC
TL/H/10803–3
TopView
OrderNumberTP3465V
SeeNSPackageNumberV28A
FIGURE2.MICROWIREInterfaceDeviceMIDTP3465Pinouts
PinDescription
Name PinNo. Type Function
28Pkg.
VCC 28 I +5VSupply
GND 14 I 0V
CKIN 17 I MasterClockInputUsedtoDerivetheSKClock
MICROWIREInterface
TheMICROWIREInterfaceconsistsofSK(clockout),SO(dataout),SI(datain)andupto8chipselectoutputlines.
Name PinNo. Type Function
28Pkg.
SK 13 O MICROWIREclockoutput.
SO 15 O/I MICROWIREdataoutput.Canalsobeusedfor
MICROWIREdatainputwhencommunicatingwithspecial
devices.Seeapplicationsection.
SI 16 I MICROWIREdatainput.
CS0-CS3 24-27 I/O Fourinput/outputlines,normallyusedasoutputsforchip
selectstoMICROWIREperipherals
CSCS7 6,9,20, I/O Fourchipselectlinesaccessible
23 whenusingtheMultiplexedbusmode.
2
MultiplexedMicroprocessorBusInterface
TheMULT/INT pinissampledonpower-upand,ifLOW,themicroprocessorbusformatisassumedtobeMultiplexedandthe
pinisconsideredaninputpintoindicateMultiplexedbusformat.Thepinhasaninternalpull-upandthusifpinisleftfloating,it
willbeconsideredasinNon-multiplexedmode.TheinterfaceconsistsofaneightbitmultiplexedAddress/Datamicroprocessor
bus(onlytheA0,A1,A2andA3addresslinesaredecoded),andsixcontrollines(CE,RST,AS/MI,RD/DS,WR/(R/W)andthe
MULT input)whichshouldbetiedLOW.
Name PinNo. Type Function
28Pkg.
AD0-AD7 1,2,3,4, I/O Address/Databus.Transfersaddressesanddata
5,7,8,10 betweenthemicroprocessorandtheMID.
CE 19 I ChipEnable.ALOWonthissignalselectstheMIDfora
Read/Writeoperation.
WR/ 11 I WriteorRead-Writedirection.ThissignalindicatesaWrite
R/W operationorRead/Writedirectionsignal.
RD/DS 12 I ReadorDataStrobe.WithanIntelmPthissignalindicates
aReadoperation(activelowpolaritysignal)orwitha
MotorolamP,aDatastrobe(activehighpolaritysignal).
AS/MI 21 I AddressLatchEnableorAddressStrobe.AHIGHonthis
lineindicatesanaddressontheexternalA/Dbus.When
MULTe1(non-multiplexedbus),thepinindicatesthe
typeofbus,MIe1forNSC/IntelformatandMIe0,for
Motorolaformat.
RST 22 I TheRST isthemasterResetinput,whenLOWforcesthe
deviceintheRESETcondition(sameasPower-on-
Reset).
MULT/ 18 I MultiplexedBusinputorINTerruptoutput.Itisinternally
INT pulledHIGHtoindicateaNon-Multiplexedbusformatand
needstobepulledLOWexternallytoindicatethe
Multiplexedbusformat.
Non-MultiplexedMicroprocessorInterface
TheMULT/INT pinissampledonpower-upand,ifnotLOW,themicroprocessorbusformatisassumedtobeNon-multiplexed.
Thisinterfaceconsistsofafour-bitAddressbus,aneight-bitDatabusandsixcontrollines(CE RST,AS/MI,RD/DS,
WR/(R/WR)andtheINT signalifenabled).
Name PinNo. Type Function
28Pkg.
A0–A3 6,9, I Addressbus.These4pins(accessibleinthe28-pinpackage)
20,23 areusedtoaddressthe16registers.
D0–D7 1,2,3,4, I/O Databusfordatatransferbetweenthemicroprocessorandthe
5,7,8,10 MID.
CE 19 I ChipEnable.ALOWonthissignalselectstheMIDfora
Read/Writeoperation.
WR/ 11 I WriteorRead-Writedirection.ThissignalindicatesaWrite
(R/W) operationorRead/Writedirectionsignal.
RD/DS 12 I ReadorDataStrobe.WithanIntelmPthissignalindicatesa
Readoperation(activelowpolaritysignal)orwithaMotorolamP,
aDataStrobe(activehighpolaritysignal).
AS/MI 21 I AddressLatchEnableorAddressStrobe.AHIGHonthisline
indicatesanaddressontheexternalA/Dbus.WhenMULTe1
(non-multiplexedbus),thepinindicatesthetypeofbus,MIe1
forNSC/IntelformatandMIe0forMotorolaformat.
3
Non-MultiplexedMicroprocessorInterface(Continued)
TheMULT/INT pinissampledonpower-upand,ifnotLOW,themicroprocessorbusformatisassumedtobeNon-multiplexed.
Thisinterfaceconsistsofafour-bitAddressbus,aneight-bitDatabusandsixcontrollines(CE RST,AS/MI,RD/DS,
WR/(R/WR)andtheINT signalifenabled).
Name PinNo. Type Function
28Pkg.
RST 22 I TheRST isthemasterResetinput;whenLOW,itforcesthe
deviceintheRESETcondition(sameasPower-on-Reset).
MULT/ 18 I MultiplexedBusinputorINTerruptoutput.Itisinternallypulled
INT O HIGHtoindicateaNon-multiplexedbusformatandthepincan
beanINT outputpinifenabledbysettingtheIntenbitinthe
CKRregister.INT pullslowtoindicatethecompletionofa
MICROWIREtransferoperation.
FunctionalDescription
TheblockdiagramoftheMICROWIREInterfaceDevice
(MID)isshownin
Figure 1
. It essentially consists of a very
flexiblemicroprocessorbusinterface,aserialMICROWIRE
interfaceandaChipSelect(output)port.Internallyitcon-
tainsaprogrammableclockdividertoderivetheMICRO-
WIREclockspeedfromasystemclock.
MICROPROCESSORINTERFACE
TheMicroprocessorbusinterfacesupportsbothNational/
IntelandMotorolabusformatsintheMultiplexedandNon-
multiplexedbusmodes.
TheMULT/INT pinissampledonpower-upand,ifLOW,the
microprocessorbusformatisassumedtobeMultiplexed
andthepinisconsideredaninputpintoindicateMulti-
plexedbusformat.ThepinisinternallypulledHIGH.Upon
sampling,ifthepinisnotLOW,thebusformatisassumed
tobeNon-multiplexed.
ThemicroprocessorinterfacesupportsmultiplexedAd-
dress/DataFormatsfortheIntel8088/80188andMotorola
6803familiestoworkin8-bitmode.Non-multiplexedbusses
oftheNational32000,Intel80286andMotorola68000,se-
riesprocessorsandsimilararesupportedintheTP346528-
pinpart.FouraddresslinesallowaccesstoallMIDregis-
ters.
TheMIDincorporatesaflexiblebusinterfacelogictosup-
portthedifferentaddressanddatastrobesrequiredbythe
differentbusformats.Thetimingspecificationsareshownin
alatersection.Thefollowingtableshowsmicroprocessor
buscontrolpinfunctions:
MIDPin NSC/IntelBus MotorolaBus
MUXed Non-MUXed MUXed Non-MUXed
AS/MI ALE MIe1ASMIe0
RD/DS RD RD DS DS
WR/(R/W)WRWR (R/W) (R/W)
See
Figure 7
for connection of the AS and DS signals to
MotorolamPs.
MICROWIRECOMMUNICATIONMODES
TheMIDprovidesaMICROWIREporttothemainproces-
sorhavingtwomodesofoperationwiththeMICROWIRE
peripherals;software-controlledchipselectandhard-
ware-generatedchipselectmodes.
Inthefirstscheme,besidesthe2databyteregisters,there
isathirdregisterwhichmapsdirectlywiththeoutputCS
ChipSelectspins, which there eight pins for this function in
theTP346528-pinpackage .Thesoftwareinthemicroproc-
essorthenwritestotheCSregistertoselectanddeselect
individualbits(correspondingtopins).
Inthesecondscheme,theCSpinsareactivatedbyahard-
warestatemachinewhentriggered,byaccessingthedata
registersthroughotheraddresslocations(seesectionon
Registerdescription).Inthiscasethehardwarewillactivate
thechipselectpin,sendtheappropriatenumberofMICRO-
WIREdatabits(8 or 16 )andthendeselectthepin. This
enhancedmodeofcommunicationallowstheMICROWIRE
peripheraldevicestoappearasifI/Omappedinthemicro-
processor’smemoryspace.
CONTROLANDDATAREGISTERS
Thereare6controlregisters(PD,MWM,SKP,SKR,STand
CS),and1setofDataregisters(FirstMICROWIREByte
FMBandSecondMICROWIREByteSMB)fordatacom-
municationtoMICROWIREdevices.Innormalmode,the
ChipselectpinsCS0–C7arecontrolled(viatheCSregister)
bysoftwareanddataistransferredviatheFMBandSMB
registerslocatedataddress01hand00h(seeTableI).
Eightadditionaladdresses(FMBD0–7)accessthesame
dataregister(FMB)butprovideadditionalinformationto
aninternalstatemachinewhichdrivesappropriatechipse-
lectpins(e.g.,FMBD0ataddress02hcontrolsCS0pin,
FMBD1ataddress03hcontrolsCS1pinetc.).Thereis
only1setofDataregisters(FMBandSMB)whichhan-
dletheMICROWIREcommunication.Thislattermethod
ofallocatingspecialaddressestoprovidepin-selectinfor-
mationfacilitatesanenhancedMICROWIREinterfaceto
thehostprocessor.
TableIsummarizestheControlandDataRegistersandthe
addressesatwhichtheyareaccessed.
4
Functional Description (Continued)
TABLE I. Control and Data Registers
Address Register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
00h SMB d7 d6 d5 d4 d3 d2 d1 d0
01h FMB d7 d6 d5 d4 d3 d2 d1 d0
02h FMBD0 d7 d6 d5 d4 d3 d2 d1 d0
03h FMBD1 d7 d6 d5 d4 d3 d2 d1 d0
04h FMBD2 d7 d6 d5 d4 d3 d2 d1 d0
05h FMBD3 d7 d6 d5 d4 d3 d2 d1 d0
06h FMBD4 d7 d6 d5 d4 d3 d2 d1 d0
07h FMBD5 d7 d6 d5 d4 d3 d2 d1 d0
08h FMBD6 d7 d6 d5 d4 d3 d2 d1 d0
09h FMBD7 d7 d6 d5 d4 d3 d2 d1 d0
0Ah CS cs7 cs6 cs5 cs4 cs3 cs2 cs1 cs0
0Bh SKP skp7 skp6 skp5 skp4 skp3 skp2 skp1 skp0
0Ch MWM mwm7 mwm6 mwm5 mwm4 mwm3 mwm2 mwm1 mwm0
0Dh SKR inten soi ms 0 0 div2 div1 div0
0Eh ST uwdone 0 0 0 0 0 0 0
0Fh PD pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0
PDÐPin Definition Register: W Register
RESET condition is FFhex (all pins as Inputs)
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0
pd0–7 bits configure the CS07 pins as inputs or outputs.
For example pd0 e1, sets the CS0 pin as an input; pd0 e
0, sets CS0 pin as an output. Upon chip RESET, the pd0–7
bits are set to 1.
SKPÐMICROWIRE Clock (SK) Polarity: W Register
RESET condition is 00hex (Normal MICROWIRE clock)
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
skp7 skp6 skp5 skp4 skp3 skp2 skp1 skp0
skp 07 bits set the polarity of the SK MICROWIRE clock
when communicating with device connected to each of the
pins CS07. For example skp0 e0, normal MICROWIRE
mode (i.e., SO data output on negative edge of SK clock)
when sending data to device controlled by CS0 pin; skp1 e
1, NSC COMBO II clock format for device controlled by CS1
(i.e., SO data output on the positive edge of SK clock).
MWMÐMICROWIRE Mode Register: W Register
RESET condition is 00hex
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
mwm7 mwm6 mwm5 mwm4 mwm3 mwm2 mwm1 mwm0
mwm07 bits specify whether 8 or 16 clocks are generated
for devices connected to CS07 pins. For example mwm1
e1, 16 clocks will be generated for device controlled by
CS1, (16 data bits will be shifted out and 16 data bits will be
strobed in); mwm0 e0, 8 clocks will be generated for de-
vice controlled by CS0 (8 data bits will be shifted out and
strobed in).
SKRÐMICROWIRE Clock (SK) Rate Register:
W Register
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
inten soi ms 0 0 div2 div1 div0
The 3 bits div02 give the divide-by value for deriving the
SK clock output rate from the CKIN. The maximum CKIN
rate is 20 MHz, and the slowest MICROWIRE peripheral
works at 256 kHz. Table 2 below gives the division ratios
and some examples:
div2 div1 div0 SK Ratio e.g., CKIN e5 MHz e.g., CKIN e20 MHz
000SK
e
CKIN SK e5 MHz
001SK
e
CKIN/2 SK e2.5 MHz
010SK
e
CKIN/4 e1.25 MHz SK e5 MHz
011SK
e
CKIN/8 e625 kHz e2.5 MHz
100SK
e
CKIN/16 e312.5 kHz e1.25 MHz
101SK
e
CKIN/32 e156.25 kHz e625 kHz
110SK
e
CKIN/64 e78.125 kHz e312.5 kHz
111SK
e
CKIN/128 e39.06 kHz e156.25 kHz
TABLE 2. SK Clock Rate Control
5
FunctionalDescription(Continued)
TheuwdonebitintheSTregistercanbeconnectedtothe
INT pinoftheMIDtoalertthehostprocessorwhen
MICROWIREtransmissioniscompletedbysettingtheinten
bitinthisSKRregister.TheINT pinwillonlybefunctionalas
aninterruptintheNon-multiplexedbusmodeinthe28-pin
TP3465device.
ThesoibitconfigurestheSOpintobeoutput(soie0)or
input(soie1).ThisbitfunctionisusedtoperformaRead
operationonadevicesuchasNSCTP3071COMBOIIbe-
causetheTP3071sendsdatabackontheSOpin.When
soie1,theSOpinfunctionsastheSIinputpin,internally,
andfeedsthedataregisters.Seeapplicationsdiagramsand
softwareproceduresformoredetails.
ThemsbitconfigurestheMIDdeviceasaMasterofMI-
CROWIRE(mse0)orSlaveofMICROWIRE(mse1).
MICROWIRESlavemodeisdescribedandillustratedinthe
applicationssection.
CSÐChipSelectPortRegister:R/WRegister
RESETcondition,CSpinsareinputsandtheregistercon-
tainsthestateofthesepins.
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
cs7 cs6 cs5 cs4 cs3 cs2 cs1 cs0
The cs0-7bitscontrolthe8,CSinput/outputportpins.
However, only the cs0-3 control bits areavailableinthe
TP3465devicewhenusedinthenon-multiplexedbusfor-
mat.InthemultiplexedbusformatinTP3465,all8CSpins
areaccessible.
Writingtothisregisterwillaffectthepins(configuredas
outputsinPDregister)directly.Similarly,thestateofthe
pinswhichareconfiguredasinputsinthePDregisterscan
beReadviathesame(CS)register.Whenreadingthepins
designatedasoutputs,thebitswillhavea‘‘1’condition.
Writingtobitscorrespondingtoinputpinswillhavenoeffect
onthepins.
Thestateofanoutputchipselectpinmayalsobecon-
trolledbythechiphardwarestatemachineiftheuserwrites
totheFMBD0–7registers.Thehardwarecanonlybringthe
appropriatepinLOWforthedurationoftheMICROWIRE
transferandwillattempttosetitHIGHattheendofthe
transfer.Iftheuserhas,however,setthispintobeLOWby
writingtothisregister,itwillover-ridetheactionofthehard-
wareandthepinwillremainLOW.Thustheusermustwrite
a‘‘1’inthebitsthatwillbecontrolledbyhardware,andthe
pinsmustbesetasoutputsinthePDregister.
STÐMICROWIREStatusRegister:RRegister
RESETCondition,Read80Hex
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
uwdone 0 0 0 0 0 0 0
Theuwdonebit(readonly)intheSTregistercanbepolled
bythesoftwaretodeterminetheendoftheMICROWIRE
transmission(uwdonee1).uwdonee0duringtransmis-
sion.
FMBÐFirstMICROWIREByte:R/WRegister
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
d7 d6 d5 d4 d3 d2 d1 d0
SMBÐSecondMICROWIREByte:R/WRegister
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
d7 d6 d5 d4 d3 d2 d1 d0
TheSMBandtheFMBdataregistersareusedtocommuni-
catetoanyMICROWIREdevice0–7(connectedtopins
CS0–7)whencontrollingthechipselectlinesviaCSregis-
ter(usingsoftware).TheMICROWIREparametersforthis
modeofoperationaredefinedbytheparametersfordevice
7,i.e.,skp7inSKPregister,andmwm7inMWMregister.
Sowhencommunicatingwithperipheralsrequiringdifferent
formats,theskp7andmwm7bitsmayneedtobere-config-
uredbeforesendingdatatoeachofthesedevices.Example
ofcommunicationto8-bitand16-bitperipheralsarede-
scribedbelow:
Example1:Communicatingwithan8-bitMICROWIREpe-
ripheralatCS1:
Settheskp7bitto0(normalMICROWIREpolarity),andset
themwm7to0for1byteoperation.Setcs1bitto0to
selectthedevice.WritethedataintotheFMBbytelocation
soitwillbeshiftedoutafterthetrailingedgeoftheWrite
strobesignal.AttheendoftheMICROWIREtransmission
setthecs1bitto1tode-selectthedevice.The8-bit
STATUSfromtheperipheralisreadfromtheFMByteloca-
tion.
Example2:Communicatingwitha16-bitMICROWIREpe-
ripheralatCS3:
MICROWIREprotocolspecifiesthattheMostSignificantBit
istransmittedfirst.ThustheHIGHbyteofdatabecomesthe
FirstMICROWIREBytetobesentout.
Settheskp7bitto0(normalMICROWIREpolarity),andset
themwm7to1for2byteoperation.Setcs3bitto0to
selectthedevice.WritetheLOWdatabyteintheSMBreg-
isterandthenwritetheHIGHdatabyteintotheFMBbyte
location.All16databitsareshiftedoutafterthetrailing
edgeoftheWritestrobefortheFMBregister.Attheendof
theMICROWIREtransmissionsetthecs3bitto1tode-
selectthedevice.The16-bitSTATUSfromtheperipheralis
readfromtheFMB(HIGHdatabyte)andtheSMB(LOW
databyte)locations.
FMBD0ÐFirstMICROWIREByteDev0:R/WRegister
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
d7 d6 d5 d4 d3 d2 d1 d0
Thereis
only one set of data registers (FMB and SMB)
whichhandletheMICROWIREdatacommunication.
The
FMBD0 address accesses the data register FMB but also
provides information for the internal state machine to con-
trol the CS0 pin.
The MICROWIRE parameters for device 0
areindicatedbythestateofbitsskp0andmwm0,etc.
6
Functional Description (Continued)
Example 1: Communicating with 8-bit peripheralÐdevice 0:
The mwm0 bit must be set to 0. Write the MICROWIRE
data in to the FMBD0 address. The 8-bit data is then shifted
out after the trailing edge of the write pulse. The Chip Select
(CS0) is automatically activated (LOW) and deactivated
(HIGH) by hardware before and after the data transfer (see
timing diagrams). The 8-bit STATUS from the peripheral is
read from the FMBD0 byte location.
Example 2: Communicating with 16-bit peripheralÐdevice
0:
The mwm0 bit must be set to 1. Write the LOW byte of
MICROWIRE data into the SMB data register and then write
the HIGH byte in to the FMBD0 address. The 16-bit data is
then shifted out after the trailing edge of the write strobe
signal for this FMBD0 address. The Chip Select 0 (CS0) pin
is automatically activated (LOW) and deactivated (HIGH) by
hardware before and after the data transfer (see timing dia-
grams). The 16-bit STATUS from the peripheral is read from
the FMBD0 (HIGH data byte) and the SMB (LOW data byte)
locations.
FMBD1ÐFirst MICROWIRE Byte Dev1: R/W Register
Same function as FMBD0 except this refers to Device 1 and
Chip Select 1 (CS1).
FMBD2ÐFirst MICROWIRE Byte Dev2: R/W Register
Same function as FMBD0 except this refers to Device 2 and
Chip Select 2 (CS2).
FMBD3ÐFirst MICROWIRE Byte Dev3: R/W Register
Same function as FMBD0 except this refers to Device 3 and
Chip Select 3 (CS3).
FMBD4ÐFirst MICROWIRE Byte Dev4: R/W Register
Same function as FMBD0 except this refers to Device 4 and
Chip Select 4 (CS4).
FMBD5ÐFirst MICROWIRE Byte Dev5: R/W Register
Same function as FMBD0 except this refers to Device 5 and
Chip Select 5 (CS5).
FMBD6ÐFirst MICROWIRE Byte Dev6: R/W Register
Same function as FMBD0 except this refers to Device 6 and
Chip Select 6 (CS6).
FMBD7ÐFirst MICROWIRE Byte Dev7: R/W Register
Same function as FMBD0 except this refers to Device 7 and
Chip Select 7 (CS7).
MICROWIRE Master/Slave Modes
MICROWIRE MASTER MODE
The primary application for MID is as a master of MICRO-
WIRE bus (ms bit in CKR register set to 0), and as such it
provides the SK clock out to the peripheral devices. It trans-
mits data on the SO pin and receives data on the SI pin. The
CS07 pins are used as chip select pins for the peripherals
and have a predefined relationship with the SK clock output.
Writing to the FMB pin causes the most significant bit to be
output immediately to the SO pin, and the uwdone bit is
automatically reset to 0. Upon completion of transfer of ei-
ther 8 bits (mwm7 e0) or 16 bits (mwm7 e1), the
uwdone bit is set to 1. The SO pin is then set to the TRI-
STATEÉcondition. Note that when using the FMB and SMB
registers, the communication mode is determined by the pa-
rameters for channel 7 (mwm7 and skp7).
MICROWIRE SLAVE MODE
The MID can be set to work in MICROWIRE Slave mode by
setting the ms bit to 1. The MICROWIRE clock from the
master is connected to the CKIN pin of this MID device. The
SK output is ignored. Normally the SO pin is in TRI-STATE
condition and, while the uwdone bit is 1, any CKIN clock
inputs are ignored. Writing to the FMB register causes the
most significant bit to be output immediately to the SO pin
and the uwdone bit is reset to 0 by hardware. The SK clock
input is then enabled to clock data into SI and out of SO.
After receiving SK clock pulses; either 8 (mwm7 e0) or 16
bits (mwm7 e1), the uwdone bit is set to 1 by hardware.
The SO pin is then set to TRI-STATE condition. Note that
when using the FMB and SMB registers, the communication
mode is determined by the parameters of channel 7 (mwm7
and skp7).
FMBD07 addresses are not used in the slave mode. The
CS register, however, can be used as a general I/O port
control register.
See applications section for an example of the Slave opera-
tion
(Figure 6)
.
MICROWIRE BUS FORMATS
MID supports devices which implement either of the two
MICROWIRE bus formats; a 3-pin format and a 4-pin format.
Figure 3
shows a MID connected to devices supporting
each of these formats.
The standard 4-pin format consists of the CCLK clock pin,
CO and CI as the data out and data in pins, and CS to select
the MICROWIRE peripheral. ISDN transceivers and other
intelligent peripherals also have an INTerrupt signal from
the peripheral to the local microprocessor. NSC MICRO-
WIRE devices with this 4-pin format include ISDN transceiv-
ers, COMBO II, LCD display drivers and EEPROMs.
There are, however, some MICROWIRE peripherals (e.g.,
TP3071 COMBO II, and some EEPROMs) which support a
3-pin bus format because of package pin limitations. The
format consists of the CCLK clock signal, a bi-directional
data signal CO/CI, and a CS chip select signal. The direc-
tion of the data transferred on the CO/CI pin is determined
by a protocol between the Master and the Slave of the MI-
CROWIRE bus. For example, the TP3071 implements a
two-byte protocol. The first byte into the TP3071 indicates a
Read or a Write operation and thus defines the direction of
the next byte to the device.
Software Driver Procedures
This section describes the steps for software driver routines
to communicate with different MICROWIRE devices (8-bit,
16-bit, or more) and those supporting the 3-pin or 4-pin
MICROWIRE bus formats.
INITIALIZATION
1. Write to PD (Pin Definition) register to set the desired chip
select control pins (CS07) as outputs. (All CS pins are
set to inputs on chip RESET.)
2. Write to SKP (SK polarity), to select the polarity of the SK
clock for each of the MICROWIRE devices connected to
CS07 pins.
3. Write to MWM (MICROWIRE Mode) register to select
whether 8- or 16-bit devices are attached to the CS07
pins. Devices needing more than 16-bits may still be con-
figured as 8-bit mode (if multiple of 8) or 16-bit mode (if
multiple of 16 bits).
7
SoftwareDriverProcedures(Continued)
4.WritetoSKRtosetthedivbitstosupportthefastestSK
clockratesupportedbytheperipherals.Setintene1if
theuwdonestatusistosetanINTerrupttothehost
processor(availableonlyintheNon-multiplexedbusim-
plementationofTP3465,28-pinpackage).Themsand
thesoibitaresetto0uponpowerupandindicatethat
theMIDisinMICROWIREMastermode,withSOasan
outputpinasnormal.
SENDINGDATATOPERIPHERALS(NormalMode)
Assumesending16-bitdatatoaMICROWIREbaseddevice
connectedtoanyoneofCS0toCS7.
1.WritetoCS(ChipSelect)registerandresettheappropri-
atebitandthusactivatethecorrespondingCSpin.
2.WriteLOWbytedatatoSMB(SecondMICROWIREByte)
registerandthenHIGHbytedatatoFMB(FirstMICRO-
WIREByte)register.
3.ReadtheST(Status)registerandstayinaloopuntil
uwdonebitisset.
4.WritetoCSregisterandsetthebittodeactivatetheap-
propriatechipselectpin.
SENDINGDATATOPERIPHERALS
(HardwareAssistedChipSelect)
Assumingsending16-bitdatatodev3connectedtoCS3
pin.
1.WriteLOWbytedatatoaddressSMBandthenHIGH
bytedatatoFMBD3.
2.ReadtheSTregisterandstayinaloopuntiluwdonebit
isset.
CommunicatingwithanNSC
TP3071COMBOIITypeDevice
TheNSCTP3071COMBOIIdevicehasamodifiedMICRO-
WIREport.Itsharesasinglepin(calledCO/CI)forincoming
andoutgoingdata.TheMID’sSOpinmaybetiedtothispin,
asshownin
Figure 3
, and the following steps are followed
toReadfromandWritetothisdevice.Assumethatthechip
selectforTP3071isconnectedtoCS1pin.
TP3071WriteOperation:
a.Initializationstates:skp1e1,mwm1e1,andsoie0
b.Datatransferoptions:
i.Setcs1bitto0,writeLOWbytetoSMB,andHIGH
bytetoFMBandthensetcs1bitto1afteruwdonebit
issetto1.
OR
ii.WriteLOWbytetoSMB,andHIGHbytetoFMBD1.
TP3071ReadOperation:
a.Initializationstates:skp1e1,mwm1e0,andsoie0.
b.Datatransferoptions:
i.Setcs1bitto0,writeHIGHbytetoFMB,waituntil
uwdonebitissetto1byhardware.Setsoibitto1.
WritedummyLOWbyte(e.g.,00h)toFMB,waituntil
uwdonebitissetto1byhardware.ReadSTATUS
fromFMBaddress.Setsoito0andcs1to1.
OR
ii.WriteHIGHbytetoFMBD1,waituntiluwdonebitisset
to1byhardware.Setsoibitto1.WriteadummyLOW
byte(e.g.,00h)toFMBD1andwaituntiluwdonebitis
setto1byhardware.ReadSTATUSfromFMBD1ad-
dress.Setsoibitto0.
Applications
Theversatile TP3465MICROWIREInterfaceDevicecanbe
usedinanumberofapplicationsinvolvingMICROWIREpe-
ripheraldevicesthatneedtobecontrolledusingastandard
microprocessorwhichonlyhasaparallelbusstructure.
ISDNTERMINALADAPTER
TheMIDcanbeusedinISDNterminaladapters(see
Figure
4
)interfacingtoISDNcomponentssuchasTP3420SID,as
wellasnon-ISDNcomponentssuchasLCDdisplaydrivers
(e.g.,COP470)andserialEEPROMs(COP494).Inthisap-
plicationtheMIDsignalsSK,SOandSIarebussedtoall
peripheraldevices. The device chipselectscontrol lines
a total of 8inthe28-pinpackage areindividuallyconnected
toeachofthedevices.StatusInterruptfromtheperipherals
suchasSIDareconnecteddirectlytothemainprocessor.
ANALOGORDIGITALLINECARDS
TheMIDcanalsobeusedinanaloganddigital(ISDNand
Non-ISDN)linecardapplications(see
Figure 5
). Up to 8
MICROWIREperipheraldevices(TP3070COMBOII,or
TP3420SIDs,TP3410UIDsorTP3401DASLs)canbecon-
nectedtooneMIDdevice.TheInterruptsfromthetrans-
ceiversmaybewire-ORedandfedintooneinterruptlineof
themainprocessor,inwhichcaseallthedeviceswillneed
tobepolledafteraninterrupt.Theefficientinterfacebe-
tweentheMIDandmicroprocessorallowsthisprocessto
beaccomplishedwithminimumoverhead.
Inagivenapplication,ifanyofthechipselectpinsarenot
usedtoperformchipselectforperipherals,thenitmaybe
usedasageneralpurposeinput/outputpinundersoftware
control.
MIDSUPPORTINGMASTERANDSLAVE
MICROWIREOPERATION
TheMICROWIREserialdatabusisoftenusedasameans
ofinter-processorcommunication.TheMIDmaybeused
eitherastheMasteroftheMICROWIREclockSKorasa
SlavetotheSKclockfedviaCKINpin.
Figure 6
shows an
applicationinwhichtwogeneralmicroprocessorscommuni-
catewitheachotherovertheMICROWIREbus.Atthe
sametimeotherperipheralsarealsoconnectedtotheserial
bus.Externalhandshakingbetweenthetwoprocessorsis
requiredbeforetheMICROWIREBytedatatransferisexe-
cutedbythemasteroftheMICROWIREbus.
8
Applications (Continued)
TL/H/1080315
FIGURE 3. MID, Two Types of Microwire Formats;
3-Pin (e.g., TP3071 COMBO II) and 4-Pin (e.g., TP3420, SID)
TL/H/108034
FIGURE 4. MID, TERMINAL EQUIPMENT Application
²The nomenclature for MICROWIRE signal names is as follows:
MICROWIRE controllerÐSK (clock), SO (data out), SI (data in)
MICROWIRE peripheralÐCCLK (clock), CO (data out), CI (data in).
9
Applications (Continued)
TL/H/108035
FIGURE 5. MID, LINECARD ApplicationÐDigital (ISDN/Non-ISDN) or Analog
10
Applications(Continued)
²ThenomenclatureforMICROWIREsignalnamesisasfollows:
MICROWIREcontrollerÐSK(clock),SO(dataout),SI(datain)
MICROWIREperipheralÐCCLK(clock),CO(dataout),CI(datain).
TL/H/10803–6
FIGURE6.ExampleofMIDinMasterorSlaveMICROWIREOperation
TL/H/10803–16
Note:ForTP3465,theAS(AddressStrobe)andDS(DataStrobe)areactivehighpolaritysignals.Fornon-multiplexedbusses,AS=0.
FIGURE7.MID,ConnectingtoMotorolamPs.
11
Device Electrical Characteristics
Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
VCC to GND 7V
Input Voltage b0.3V to VCC a0.3V
DC Input Current IIg50 mA
Storage Temperature Range b65§Ctoa
150§C
Lead Temperature
(Soldering, 10 Sec.) 300§C
ESD Rating t1500V
Electrical Characteristics
Unless otherwise noted, limits in BOLD characters are electrical testing limits at VCC e5.0V and TAea
25§C. All other limits
are assured by correlation with other production tests and/or product design and characterization for VCC e5.0V g5% and
TAe0§Ctoa
70§C. All signals are referenced to GND.
Symbol Parameter Conditions Limits Units
Min Max
VIL Input Low Voltage All Inputs 0.8 V
VIH Input High Voltage All Inputs 2.0 V
VOL Output Low Voltage CS0 7: IOL e1mA
SK, SO: IOL e4mA 0.4 V
AD(7:0): IOL e2mA
V
OH Output High Voltage CS0 7: IOH e1mA
SK, SO: IOH e4mA 2.4 V
AD(7:0): IOH e2mA
I
IH High Level Input Current All Inputs, b10 mA
GND kVIN kVCC
IIL Low Level Input Current All Inputs a10 mA
IOZ Output Current in High-Z AD(7:0), SO g20 mA
ICC Dynamic Supply Current CKIN eSK e1 MHz 0.7 mA
CKIN eSK e20 MHz 4
12
Timing Characteristics
This section contains timing diagrams for the microprocessor bus interface, MICROWIRE port interface and the Control and
Clock timings relationships.
Timing characteristics are derived from worst-case simulations plus guardbanding. Production testing is limited to device func-
tionality.
NSC/Intel Bus Format
MULTIPLEXED MICROPROCESSOR BUS
TL/H/108037
NON-MULTIPLEXED MICROPROCESSOR BUS
TL/H/108038
Symbol Parameter Conditions Min Max Units
tWASH Width, Address Strobe High 20 ns
tSAAS Setup, Address to Address Strobe 10 ns
tHASA Hold, Address Strobe Low to Address 10 ns
tHASR Hold, Address Strobe to Read Strobe 10 ns
tDRD Delay, Read Low to Data 100 pF Load 70 ns
tHRD Hold, Read High to Data 5 40 ns
tWRL Width, Read Strobe Low 20 ns
tSDW Setup, Data to Write High 30 ns
tHWD Hold, Write High to Data 10 ns
tWWL Width, Write Strobe Low 20 ns
tSAR Setup, Address to Read Low Non-Muxed, MI e110 ns
t
HRA Hold, Read High to Address Non-Muxed, MI e110 ns
t
SAW Setup, Address to Write Low Non-Muxed, MI e110 ns
t
HWA Hold, Write High to Address Non-Muxed, MI e110 ns
13
MotorolaBusFormat
MULTIPLEXEDMICROPROCESSORBUS
TL/H/10803–9
NON-MULTIPLEXEDMICROPROCESSORBUS
TL/H/10803–10
Note:ForTP3465MID,theAS(AddressStrobe)andDS(DataStrobe)areactivehighpolaritysignals.ForNon-multiplexedbussesAS=0.See
Figure7
for
connectiondiagram.
Symbol Parameter Conditions Min Max Units
tWASH Width,AddressStrobeHigh 20 ns
tSAAS Setup,AddresstoAddressStrobe 10 ns
tHASA Hold,AddressStrobeLowtoAddress 10 ns
tHASDS Hold,AddressStrobetoDataStrobe 10 ns
tDDSD Delay,DataStrobe LowtoData(Read) 100pFLoad 70 ns
tHDSD Hold,DataStrobe HightoData 5 40 ns
tWDSL Width,DataStrobe Low 20 ns
tSDDS Setup,DatatoDataStrobe High(Write) 30 ns
tSRWDS Setup,R/WStrobetoDataStrobe 10 ns
tHDSRW Hold,DataStrobetoR/W 10 ns
tSADS Setup,AddresstoDataStrobe Low Non-Muxed,MIe010 ns
t
HDSA Hold,DataStrobe HightoAddress Non-Muxed,MIe010 ns
14
MICROWIRE Timing Diagrams
Symbol Parameter Conditions Min Max Units
fCKIN CKin Frequency 20 MHz
fSK SK Frequency 5 MHz
tSKD SK Clock Duration 200 ns
tSKH SK High Duration 70 ns
tSKL SK Low Duration 70 ns
tRSK Rise Time, SK 100 pF Load 30 ns
tFSK Fall Time, SK 100 pF Load 30 ns
tSISK Setup Time, SI Valid to SK Edge 20 ns
tHSKI Hold Time, SK High to SI Invalid 20 ns
tDSKO Delay, SK Edge to SO Data Valid Output 20 ns
tDSKZ Delay, Last SK to SO TRI-STATE 30 ns
tDWOV Delay, WR to SO Valid FMB or 50 ns
FMBD0 7
MICROWIRE Timing for 1 Byte Transfer
TL/H/1080311
MICROWIRE Timing for 2 Byte Transfers
TL/H/1080312
15
Control Interface Timing Relationships
Symbol Parameter Conditions Min Max Units
tDWCSA Delay, Write Strobe to CS Asserted Auto Mode 2 SK Cycle
tDCSSKA Delay, CS Active to first SK Edge Auto Mode 0.5 SK 0.5 SK ns
b50 ns
tDSKCSA Delay, Last SK Edge to CS Inactive Auto Mode 2.8 7.3 ns
CS Load e10 pF; SK Load e50 pF
tDWCSS Delay, Write Strobe (CS Register) Software 30 ns
to CS Asserted
tDCSN Delay, CS High to INT Low 50 ns
tDRDN Delay, RD Low to INT High ST Register 80 ns
TL/H/1080313
16
TP3465MICROWIREInterfaceDevice(MID)
Physical Dimensions inches (millimeters) (Continued)
Plastic Chip Carrier (V)
Order Number TP3465V
NS Package Number V28A
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