TL/F/9584
54F/74F657 Octal Bidirectional Transceiver
with 8-Bit Parity Generator/Checker and TRI-STATE Outputs
December 1994
54F/74F657 Octal Bidirectional Transceiver
with 8-Bit Parity Generator/Checker
and TRI-STATEÉOutputs
General Description
The ’F657 contains eight non-inverting buffers with
TRI-STATEÉoutputs and an 8-bit parity generator/checker.
It is intended for bus-oriented applications. The buffers have
a guaranteed current sinking capability of 24 mA (20 mA mil)
at the A port and 64 mA (48 mA mil) at the B port.
Features
Y300 Mil 24-pin slimline DIP
YCombines ’F245 and ’F280A functions in one package
YTRI-STATE outputs
YB Outputs sink 64 mA (48 mA mil)
Y12 mA source current, B side
YInput diodes for termination effects
Commercial Military Package Package Description
Number
74F657SPC N24C 24-Lead (0.300×Wide) Molded Dual-In-Line
54F657SDM (Note 2) J24F 24-Lead (0.300×Wide) Ceramic Dual-In-Line
75F657SC (Note 1) M24B 24-Lead (0.300×Wide) Molded Small Outline, JEDEC
54F657FM (Note 2) W24C 24-Lead Cerpack
54F657LM (Note 2) E28A 24-Lead Ceramic Leadless Chip Carrier, Type C
Note 1: Devices also available in 13×reel. Use suffix eSCX.
Note 2: Military grade device with environmental and burn-in processing. Use suffix eDMQB, FMQB and LMQB.
Logic Symbols
IEEE/IEC
TL/F/9584–5
TL/F/9584–1
TRI-STATEÉis a registered trademark of National Semiconductor Corporation.
C1995 National Semiconductor Corporation RRD-B30M75/Printed in U. S. A.
Connection Diagrams
Pin Assignment
for DIP, SOIC
and Flatpak
TL/F/9584–2
Pin Assignment
for LCC
TL/F/9584–3
Unit Loading/Fan Out
54F/74F
Pin Names Description U.L. Input IIH/IIL
HIGH/LOW Output IOH/IOL
A0–A7Data Inputs/ 4.5/0.15 90 mA/b90 mA
TRI-STATE Outputs 150/40 (33.3) b3 mA/24 mA (20 mA)
B0–B7Data Inputs/ 3.5/0.117 70 mA/b70 mA
TRI-STATE Outputs 600/106.6 (80) b12 mA/64 mA (48 mA)
T/R Transmit/Receive Input 2.0/0.067 40 mA/b40 mA
OE Enable Input 2.0/0.067 40 mA/b40 mA
PARITY Parity Input/ 3.5/0.117 70 mA/b70mA
TRI-STATE Output 600/106.6 (80) b12 mA/64 mA (48 mA)
ODD/EVEN ODD/EVEN Parity Input 1.0/0.033 20 mA/b20 mA
ERROR Error Output 600/106.6 (80) b12 mA/64 mA (48 mA)
Functional Description
The Transmit/Receive (T/R) input determines the direction
of the data flow through the bidirectional transceivers.
Transmit (active HIGH) enables data from the A port to the
B port; Receive (active LOW) enables data from the B port
to the A port.
The Output Enable (OE) input disables the parity and
ERROR outputs and both the A and B ports by placing them
in a HIGH-Z condition when the Output Enable input is
HIGH.
When transmitting (T/R HIGH), the parity generator detects
whether an even or odd number of bits on the A port are
HIGH and compares these with the condition of the pari-
ty select (ODD/EVEN). If the Parity Select is HIGH and an
even number of A inputs are HIGH, the Parity output is
HIGH.
In receiving mode (T/R LOW), the parity select and number
of HIGH inputs on port B are compared to the condition of
the Parity input. If an even number of bits on the B port are
HIGH, the parity select is HIGH, and the PARITY input is
HIGH, then ERROR will be HIGH to indicate no error. If an
odd number of bits on the B port are HIGH, the parity select
is HIGH, and the PARITY input is HIGH, the ERROR will be
LOW indicating an error.
2
Function Table
Number of Inputs Input/ Outputs
Inputs That Output
Are High OE T/R ODD/EVEN Parity ERROR Outputs Mode
0, 2, 4, 6, 8 L H H H Z Transmit
L H L L Z Transmit
L L H H H Receive
L L H L L Receive
L L L H L Receive
L L L L H Receive
1, 3, 5, 7 L H H L Z Transmit
L H L H Z Transmit
L L H H L Receive
L L H L H Receive
L L L H H Receive
L L L L L Receive
Immaterial H X X Z Z Z
HeHIGH Voltage Level
LeLOW Voltage Level
XeImmaterial
ZeHigh Impedance
Function Table
Inputs Outputs
OE T/R
L L Bus B Data to Bus A
L H Bus A Data to Bus B
H X High-Z State
HeHIGH Voltage Level
LeLOW Voltage Level
XeImmaterial
3
Functional Block Diagram
TL/F/9584–4
4
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Storage Temperature b65§Ctoa
150§C
Ambient Temperature under Bias b55§Ctoa
125§C
Junction Temperature under Bias b55§Ctoa
175§C
Plastic b55§Ctoa
150§C
VCC Pin Potential to
Ground Pin b0.5V to a7.0V
Input Voltage (Note 2) b0.5V to a7.0V
Input Current (Note 2) b30 mA to a5.0 mA
Voltage Applied to Output
in HIGH State (with VCC e0V)
Standard Output b0.5V to VCC
TRI-STATE Output b0.5V to a5.5V
Current Applied to Output
in LOW State (Max) twice the rated IOL (mA)
Note 1: Absolute maximum ratings are values beyond which the device may
be damaged or have its useful life impaired. Functional operation under
these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature
Military b55§Ctoa
125§C
Commercial 0§Ctoa
70§C
Supply Voltage
Military a4.5V to a5.5V
Commercial a4.5V to a5.5V
DC Electrical Characteristics
Symbol Parameter 54F/74F Units VCC Conditions
Min Typ Max
VIH Input HIGH Voltage 2.0 V Recognized as a HIGH Signal
VIL Input LOW Voltage 0.8 V Recognized as a LOW Signal
VCD Input Clamp Diode Voltage b1.2 V Min IIN eb
18 mA
VOH Output HIGH 54F 10%VCC 2.5 IOH eb
1mA(A
n
)
Voltage 54F 10% VCC 2.4 IOH eb
3mA(A
n
,B
n
, Parity, ERROR)
54F 10% VCC 2.0 IOH eb
12 mA (Bn, Parity, ERROR)
74F 10% VCC 2.5 V Min IOH eb
1mA(A
n
)
74F 10% VCC 2.4 IOH eb
3mA(A
nB
n
, Parity, ERROR)
74F 10% VCC 2.0 IOH eb
15 mA (Bn, Parity, ERROR)
74F 5% VCC 2.7 IOH eb
1mA(A
n
)
74F 5% VCC 2.7 IOH eb
3mA(A
n
,B
n
, Parity, ERROR)
VOL Output LOW 54F 10% VCC 0.5 IOL e20 mA (An)
Voltage 54F 10% VCC 0.55 V Min IOL e48 mA (Bn, Parity, ERROR)
74F 10% VCC 0.5 IOL e24 mA (An)
74F 10% VCC 0.55 IOL e64 mA (BnParity, ERROR)
IIH Input HIGH Current 20 mA Max VIN e2.7V (ODD/EVEN)
40 VIN 2.7V (T/R,OE)
I
BVI Input HIGH Current 100 mAV
CC e0VIN e7.0V (T/R,OE, ODD/EVEN)
Breakdown Test
IBVIT Input HIGH Current 1.0 mA Max VIN e5.5V (Parity, Bn)
Breakdown Test (I/O) 2.0 VIN e5.5V (An)
IIL Input LOW Current b20 mA Max VIN e0.5V (ODD/EVEN)
b40 VIN e0.5V (T/R,OE)
I
OZH Output Leakage Current 50 mA Max VOUT e2.7V (ERROR)
IOZL Output Leakage Current b50 mA Max VOUT e0.5V (ERROR)
IIH aIOZH Output Leakage Current 70 mA Max VI/O e2.7V (Bn, Parity)
90 VI/O e2.7V (An)
IIL aIOZL Output Leakage Current b70 mA Max VI/O e0.5V (Bn, Parity)
b90 VI/O e0.5V (An)
IOS Output Short-Circuit Current b60 b150 mA Max VOUT e0V (An)
b100 b225 VOUT e0V (Bn, Parity, ERROR)
ICEX Output HIGH Leakage 250 mA Max VOUT eVCC (ERROR)
Current 1.0 mA Max VOUT eVCC (Bn, Parity)
2.0 mA Max VOUT eVCC (An)
IZZ Bus Drainage Test 500 mA 0.0V VOUT e5.25V (An,B
n
, Parity, ERROR)
ICCH Power Supply Current 101 125 mA Max VOeHIGH
ICCL Power Supply Current 112 150 mA Max VOeLOW
ICCZ Power Supply Current 109 145 mA Max VOeHIGH Z
5
AC Electrical Characteristics
74F 54F 74F
TAea
25§CTA,V
CC eMil TA,V
CC eCom
Symbol Parameter VCC ea
5.0V CLe50 pF CLe50 pF Units
CLe50 pF
Min Typ Max Min Max Min Max
tPLH Propagation Delay 2.5 4.5 8.0 2.5 9.5 2.5 9.0 ns
tPHL Anto Bn,B
nto An3.0 4..9 7.5 3.0 8.5 3.0 8.0
tPLH Propagation Delay 6.5 10.1 14.0 5.5 18.0 6.0 16.0 ns
tPHL Anto Parity 7.0 10.9 15.0 5.5 20.5 6.0 16.5
tPLH Propagation Delay 4.5 7.8 11.0 4.0 14.0 4.0 13.0 ns
tPHL ODD/EVEN to PARITY 4.5 8.8 12.0 4.5 16.5 4.5 13.5
tPLH Propagation Delay 4.5 7.5 11.0 4.0 14.0 4.0 13.0 ns
tPHL ODD/EVEN to ERROR 4.5 8.2 12.0 4.5 16.5 4.5 13.5
tPLH Propagation Delay 8.0 14.0 20.5 7.5 27.0 7.5 23.0 ns
tPHL Bnto ERROR 8.0 15.0 21.5 7.5 28.5 7.5 23.5
tPLH Propagation Delay 7.0 10.8 15.5 6.0 20.0 6.0 17.0 ns
tPHL PARITY to ERROR 7.5 11.8 16.5 6.5 22.0 7.5 18.5
tPZH Output Enable Time 3.0 5.0 8.0 2.5 11.0 2.5 9.5 ns
tPZL OE to An/Bn4.0 6.5 10.0 3.5 13.5 3.5 11.0
tPHZ Output Disable Time 1.0 4.5 8.0 1.0 9.5 1.0 9.0 ns
tPLZ OE to An/Bn1.0 4.9 7.5 1.0 8.5 1.0 8.0
tPZH Output Enable Time 3.0 5.0 8.0 2.5 11.0 2.5 9.5 ns
tPZL OE to ERROR (Note 1) 4.0 7.7 10.0 3.5 13.5 3.5 11.0
tPHZ Output Disable Time 1.0 4.5 8.0 1.0 9.5 1.0 9.0 ns
tPLZ OE to ERROR 1.0 4.9 7.5 1.0 8.5 1.0 8.0
tPZH Output Enable Time 3.0 5.0 8.0 2.5 11.0 2.5 9.5 ns
tPZL OE to PARITY 4.0 7.7 10.0 3.5 13.5 3.5 11.0
tPHZ Output Disable Time 1.0 4.6 8.0 1.0 9.5 1.0 9.0 ns
tPLZ OE to PARITY 1.0 5.1 7.5 1.0 8.5 1.0 8.0
Note 1: These delay times reflect the TRI-STATE recovery time only and not the signal time through the buffers or the parity check circuity. To assure VALID
information at the ERROR pin, time must be allowed for the signal to propagate through the drivers (B to A), through the parity check circuitry (same as A to
PARITY), and to the ERROR output after the ERROR pin has been enabled (Output Enable times). VALID data at the ERROR pin t(A to PARITY) a(Output
Enable Time).
Ordering Information
The device number is used to form part of a simplified purchasing code where a package type and temperature range are
defined as follows:
74F 657 P C X
Temperature Range Family Special Variations
74F eCommercial X eDevices shipped in 13×reels
54F eMilitary QB eMilitary grade with
environmental and burn-in
Device Type processing shipped in tubes
Package Code Temperature Range
SP eSlim Plastic DIP CeCommercial (0§Ctoa
70§C)
SD eSlim Ceramic DIP MeMilitary (b55§Ctoa
125§C)
FeFlatpak
LeLeadless Ceramic Chip Carrier (LCC)
SeSmall Outline (SOIC)
6
7
Physical Dimensions inches (millimeters)
28-Lead Ceramic Leadless Chip Carrier (L)
NS Package Number E28A
24-Lead (0.300×Wide) Ceramic Dual-In-Line Package (SD)
NS Package Number J24F
8
Physical Dimensions inches (millimeters) (Continued)
24-Lead (0.300×Wide) Molded Small Outline Package, JEDEC (S)
NS Package Number M24B
24-Lead (0.300×Wide) Molded Dual-In-Line Package (SP)
NS Package Number N24C
9
54F/74F657 Octal Bidirectional Transceiver
with 8-Bit Parity Generator/Checker and TRI-STATE Outputs
Physical Dimensions inches (millimeters) (Continued)
24-Lead Ceramic Flatpak (F)
NS Package Number W24C
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SEMICONDUCTOR CORPORATION. As used herein:
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systems which, (a) are intended for surgical implant support device or system whose failure to perform can
into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life
failure to perform, when properly used in accordance support device or system, or to affect its safety or
with instructions for use provided in the labeling, can effectiveness.
be reasonably expected to result in a significant injury
to the user.
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