54F/74F657 Octal Bidirectional Transceiver with 8-Bit Parity Generator/Checker and TRI-STATEE Outputs General Description Features The 'F657 contains eight non-inverting buffers with TRI-STATEE outputs and an 8-bit parity generator/checker. It is intended for bus-oriented applications. The buffers have a guaranteed current sinking capability of 24 mA (20 mA mil) at the A port and 64 mA (48 mA mil) at the B port. Y Y Y Y Y Y Commercial Package Number Military 74F657SPC 54F657SDM (Note 2) 300 Mil 24-pin slimline DIP Combines 'F245 and 'F280A functions in one package TRI-STATE outputs B Outputs sink 64 mA (48 mA mil) 12 mA source current, B side Input diodes for termination effects Package Description N24C 24-Lead (0.300x Wide) Molded Dual-In-Line J24F 24-Lead (0.300x Wide) Ceramic Dual-In-Line M24B 24-Lead (0.300x Wide) Molded Small Outline, JEDEC 54F657FM (Note 2) W24C 24-Lead Cerpack 54F657LM (Note 2) E28A 24-Lead Ceramic Leadless Chip Carrier, Type C 75F657SC (Note 1) Note 1: Devices also available in 13x reel. Use suffix e SCX. Note 2: Military grade device with environmental and burn-in processing. Use suffix e DMQB, FMQB and LMQB. Logic Symbols IEEE/IEC TL/F/9584 - 1 TL/F/9584 - 5 TRI-STATEE is a registered trademark of National Semiconductor Corporation. C1995 National Semiconductor Corporation TL/F/9584 RRD-B30M75/Printed in U. S. A. 54F/74F657 Octal Bidirectional Transceiver with 8-Bit Parity Generator/Checker and TRI-STATE Outputs December 1994 Connection Diagrams Pin Assignment for DIP, SOIC and Flatpak Pin Assignment for LCC TL/F/9584 - 3 TL/F/9584-2 Unit Loading/Fan Out 54F/74F Pin Names Description U.L. HIGH/LOW Input IIH/IIL Output IOH/IOL A0 - A7 Data Inputs/ 4.5/0.15 90 mA/b 90 mA TRI-STATE Outputs 150/40 (33.3) b3 mA/24 mA (20 mA) B 0 - B7 Data Inputs/ 3.5/0.117 70 mA/b70 mA TRI-STATE Outputs 600/106.6 (80) b12 mA/64 mA (48 mA) T/R Transmit/Receive Input 2.0/0.067 40 mA/b40 mA OE Enable Input 2.0/0.067 40 mA/b40 mA PARITY Parity Input/ 3.5/0.117 70 mA/b70mA TRI-STATE Output 600/106.6 (80) b12 mA/64 mA (48 mA) ODD/EVEN ODD/EVEN Parity Input 1.0/0.033 20 mA/b20 mA ERROR Error Output 600/106.6 (80) b12 mA/64 mA (48 mA) Functional Description ty select (ODD/EVEN). If the Parity Select is HIGH and an even number of A inputs are HIGH, the Parity output is HIGH. In receiving mode (T/R LOW), the parity select and number of HIGH inputs on port B are compared to the condition of the Parity input. If an even number of bits on the B port are HIGH, the parity select is HIGH, and the PARITY input is HIGH, then ERROR will be HIGH to indicate no error. If an odd number of bits on the B port are HIGH, the parity select is HIGH, and the PARITY input is HIGH, the ERROR will be LOW indicating an error. The Transmit/Receive (T/R) input determines the direction of the data flow through the bidirectional transceivers. Transmit (active HIGH) enables data from the A port to the B port; Receive (active LOW) enables data from the B port to the A port. The Output Enable (OE) input disables the parity and ERROR outputs and both the A and B ports by placing them in a HIGH-Z condition when the Output Enable input is HIGH. When transmitting (T/R HIGH), the parity generator detects whether an even or odd number of bits on the A port are HIGH and compares these with the condition of the pari- 2 Function Table Number of Inputs That Are High Input/ Output Inputs Outputs OE T/R ODD/EVEN Parity ERROR Outputs Mode 0, 2, 4, 6, 8 L L L L L L H H L L L L H L H H L L H L H L H L Z Z H L L H Transmit Transmit Receive Receive Receive Receive 1, 3, 5, 7 L L L L L L H H L L L L H L H H L L L H H L H L Z Z L H H L Transmit Transmit Receive Receive Receive Receive Immaterial H X X Z Z Z H e HIGH Voltage Level L e LOW Voltage Level X e Immaterial Z e High Impedance Function Table Inputs Outputs OE T/R L L H L H X H e HIGH Voltage Level L e LOW Voltage Level X e Immaterial Bus B Data to Bus A Bus A Data to Bus B High-Z State 3 Functional Block Diagram TL/F/9584 - 4 4 Absolute Maximum Ratings (Note 1) Current Applied to Output in LOW State (Max) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Storage Temperature b 65 C to a 150 C Ambient Temperature under Bias b 55 C to a 125 C b 55 C to a 175 C b 55 C to a 150 C Junction Temperature under Bias Plastic VCC Pin Potential to Ground Pin Note 2: Either voltage limit or current limit is sufficient to protect inputs. Recommended Operating Conditions b 0.5V to a 7.0V Free Air Ambient Temperature Military Commercial b 0.5V to a 7.0V b 30 mA to a 5.0 mA Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Output in HIGH State (with VCC e 0V) Standard Output TRI-STATE Output twice the rated IOL (mA) Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. b 55 C to a 125 C 0 C to a 70 C Supply Voltage Military Commercial b 0.5V to VCC b 0.5V to a 5.5V a 4.5V to a 5.5V a 4.5V to a 5.5V DC Electrical Characteristics Symbol 54F/74F Parameter Min VIH Input HIGH Voltage VIL Input LOW Voltage VCD Input Clamp Diode Voltage VOH Output HIGH Voltage VOL Output LOW Voltage 54F 10%VCC 54F 10% VCC 54F 10% VCC 74F 10% VCC 74F 10% VCC 74F 10% VCC 74F 5% VCC 74F 5% VCC Typ Units Max 2.0 VCC V 0.8 V b 1.2 V Recognized as a HIGH Signal Recognized as a LOW Signal Min IIN e b18 mA V Min IOH IOH IOH IOH IOH IOH IOH IOH e e e e e e e e b 1 mA (An) b 3 mA (An, Bn, Parity, ERROR) b 12 mA (Bn, Parity, ERROR) b 1 mA (An) b 3 mA (An Bn, Parity, ERROR) b 15 mA (Bn, Parity, ERROR) b 1 mA (An) b 3 mA (An, Bn, Parity, ERROR) 0.5 0.55 0.5 0.55 V Min IOL IOL IOL IOL e e e e 20 mA (An) 48 mA (Bn, Parity, ERROR) 24 mA (An) 64 mA (Bn Parity, ERROR) 20 40 mA Max VIN e 2.7V (ODD/EVEN) VIN 2.7V (T/R, OE) 2.5 2.4 2.0 2.5 2.4 2.0 2.7 2.7 54F 10% VCC 54F 10% VCC 74F 10% VCC 74F 10% VCC Conditions IIH Input HIGH Current IBVI Input HIGH Current Breakdown Test 100 mA VCC e 0 IBVIT Input HIGH Current Breakdown Test (I/O) 1.0 2.0 mA Max VIN e 5.5V (Parity, Bn) VIN e 5.5V (An) IIL Input LOW Current b 20 b 40 mA Max VIN e 0.5V (ODD/EVEN) VIN e 0.5V (T/R, OE) IOZH Output Leakage Current 50 mA Max VOUT e 2.7V (ERROR) IOZL Output Leakage Current b 50 mA Max VOUT e 0.5V (ERROR) IIH a IOZH Output Leakage Current 70 90 mA Max VI/O e 2.7V (Bn, Parity) VI/O e 2.7V (An) IIL a IOZL Output Leakage Current b 70 b 90 mA Max VI/O e 0.5V (Bn, Parity) VI/O e 0.5V (An) IOS Output Short-Circuit Current b 150 b 225 mA Max VOUT e 0V (An) VOUT e 0V (Bn, Parity, ERROR) ICEX Output HIGH Leakage Current 250 1.0 2.0 mA mA mA Max Max Max VOUT e VCC (ERROR) VOUT e VCC (Bn, Parity) VOUT e VCC (An) IZZ Bus Drainage Test 500 mA 0.0V VOUT e 5.25V (An, Bn, Parity, ERROR) ICCH Power Supply Current 101 125 mA Max VO e HIGH ICCL Power Supply Current 112 150 mA Max VO e LOW ICCZ Power Supply Current 109 145 mA Max VO e HIGH Z b 60 b 100 5 VIN e 7.0V (T/R, OE, ODD/EVEN) AC Electrical Characteristics Symbol Parameter 74F 54F 74F TA e a 25 C VCC e a 5.0V CL e 50 pF TA, VCC e Mil CL e 50 pF TA, VCC e Com CL e 50 pF Units Min Typ Max Min Max Min Max tPLH tPHL Propagation Delay An to Bn, Bn to An 2.5 3.0 4.5 4..9 8.0 7.5 2.5 3.0 9.5 8.5 2.5 3.0 9.0 8.0 ns tPLH tPHL Propagation Delay An to Parity 6.5 7.0 10.1 10.9 14.0 15.0 5.5 5.5 18.0 20.5 6.0 6.0 16.0 16.5 ns tPLH tPHL Propagation Delay ODD/EVEN to PARITY 4.5 4.5 7.8 8.8 11.0 12.0 4.0 4.5 14.0 16.5 4.0 4.5 13.0 13.5 ns tPLH tPHL Propagation Delay ODD/EVEN to ERROR 4.5 4.5 7.5 8.2 11.0 12.0 4.0 4.5 14.0 16.5 4.0 4.5 13.0 13.5 ns tPLH tPHL Propagation Delay Bn to ERROR 8.0 8.0 14.0 15.0 20.5 21.5 7.5 7.5 27.0 28.5 7.5 7.5 23.0 23.5 ns tPLH tPHL Propagation Delay PARITY to ERROR 7.0 7.5 10.8 11.8 15.5 16.5 6.0 6.5 20.0 22.0 6.0 7.5 17.0 18.5 ns tPZH tPZL Output Enable Time OE to An/Bn 3.0 4.0 5.0 6.5 8.0 10.0 2.5 3.5 11.0 13.5 2.5 3.5 9.5 11.0 ns tPHZ tPLZ Output Disable Time OE to An/Bn 1.0 1.0 4.5 4.9 8.0 7.5 1.0 1.0 9.5 8.5 1.0 1.0 9.0 8.0 ns tPZH tPZL Output Enable Time OE to ERROR (Note 1) 3.0 4.0 5.0 7.7 8.0 10.0 2.5 3.5 11.0 13.5 2.5 3.5 9.5 11.0 ns tPHZ tPLZ Output Disable Time OE to ERROR 1.0 1.0 4.5 4.9 8.0 7.5 1.0 1.0 9.5 8.5 1.0 1.0 9.0 8.0 ns tPZH tPZL Output Enable Time OE to PARITY 3.0 4.0 5.0 7.7 8.0 10.0 2.5 3.5 11.0 13.5 2.5 3.5 9.5 11.0 ns tPHZ tPLZ Output Disable Time OE to PARITY 1.0 1.0 4.6 5.1 8.0 7.5 1.0 1.0 9.5 8.5 1.0 1.0 9.0 8.0 ns Note 1: These delay times reflect the TRI-STATE recovery time only and not the signal time through the buffers or the parity check circuity. To assure VALID information at the ERROR pin, time must be allowed for the signal to propagate through the drivers (B to A), through the parity check circuitry (same as A to PARITY), and to the ERROR output after the ERROR pin has been enabled (Output Enable times). VALID data at the ERROR pin t (A to PARITY) a (Output Enable Time). Ordering Information The device number is used to form part of a simplified purchasing code where a package type and temperature range are defined as follows: 74F 657 P Temperature Range Family 74F e Commercial 54F e Military C X Special Variations X e Devices shipped in 13x reels QB e Military grade with environmental and burn-in processing shipped in tubes Device Type Package Code SP e Slim Plastic DIP SD e Slim Ceramic DIP F e Flatpak L e Leadless Ceramic Chip Carrier (LCC) S e Small Outline (SOIC) Temperature Range C e Commercial (0 C to a 70 C) M e Military (b55 C to a 125 C) 6 7 Physical Dimensions inches (millimeters) 28-Lead Ceramic Leadless Chip Carrier (L) NS Package Number E28A 24-Lead (0.300x Wide) Ceramic Dual-In-Line Package (SD) NS Package Number J24F 8 Physical Dimensions inches (millimeters) (Continued) 24-Lead (0.300x Wide) Molded Small Outline Package, JEDEC (S) NS Package Number M24B 24-Lead (0.300x Wide) Molded Dual-In-Line Package (SP) NS Package Number N24C 9 54F/74F657 Octal Bidirectional Transceiver with 8-Bit Parity Generator/Checker and TRI-STATE Outputs Physical Dimensions inches (millimeters) (Continued) 24-Lead Ceramic Flatpak (F) NS Package Number W24C LIFE SUPPORT POLICY NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. 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