Product Folder Sample & Buy Support & Community Tools & Software Technical Documents TPS53355 SLUSAE5D - AUGUST 2011 - REVISED NOVEMBER 2016 TPS53355 High-Efficiency 30-A Synchronous Buck SWIFTTM Converter With Eco-modeTM 1 Features 2 Applications * * * * * * * * * * 1 * * * * * * * * * * * * * * * * * 96% Maximum Efficiency Conversion Input Voltage Range: 1.5 V to 15 V VDD Input Voltage Range: 4.5 V to 25 V Output Voltage Range: 0.6 V to 5.5 V 5-V LDO Output Supports Single Rail Input Integrated Power MOSFETs with 30-A of Continuous Output Current Auto-Skip Eco-modeTM for Light-Load Efficiency < 10-A Shutdown Current D-CAPTM Mode With Fast Transient Response Selectable Switching Frequency from 250 kHz to 1 MHz With External Resistor Selectable Auto-Skip or PWM-Only Operation Built-in 1% 0.6-V Reference. 0.7-ms, 1.4-ms, 2.8-ms and 5.6-ms Selectable Internal Voltage Servo Soft-Start Integrated Boost Switch Precharged Startup Capability Adjustable Overcurrent Limit with Thermal Compensation Overvoltage, Undervoltage, UVLO and Overtemperature Protection Supports All Ceramic Output Capacitors Open-Drain Power Good Indication Incorporates NexFETTM Power Block Technology 22-Pin QFN Package With PowerPADTM For SWIFTTM Power Products Documentation, see http://www.ti.com/swift Green (RoHS Compatible), is Optional Servers and Storage Workstations and Desktops Telecommunications Infrastructure 3 Description TPS53355 is a D-CAPTM mode, 30-A synchronous switcher with integrated MOSFETs. It is designed for ease of use, low external component count, and space-conscious power systems. This device features 5 m/2.0 m integrated MOSFETs, accurate 1%, 0.6-V reference, and integrated boost switch. A sample of competitive features include: 1.5-V to 15-V wide conversion input voltage range, very low external component count, DCAPTM mode control for super fast transient, autoskip mode operation, internal soft-start control, selectable frequency, and no need for compensation. The conversion input voltage ranges from 1.5 V to 15 V, the supply voltage range is from 4.5 V to 25 V, and the output voltage range is from 0.6 V to 5.5 V. The device is available in 5-mm x 6-mm, 22-pin QFN package and is specified from -40C to 85C. Device Information(1) PART NUMBER TPS53355 PACKAGE BODY SIZE (NOM) LSON-CLIP (22) 6.00 mm x 5.00 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. Typical Application VVDD 21 20 19 18 17 16 15 14 13 TRIP MODE VDD VREG VIN VIN VIN VIN VIN EN PGOOD VBST N/C LL LL LL LL LL LL GND VFB TPS53355 12 VIN 22 RF VIN 1 2 3 4 5 6 7 8 9 10 11 VREG VOUT PGOOD EN Copyright (c) 2016, Texas Instruments Incorporated 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPS53355 SLUSAE5D - AUGUST 2011 - REVISED NOVEMBER 2016 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 4 5 6.1 6.2 6.3 6.4 6.5 6.6 5 5 5 6 6 8 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Infomation ................................................... Electrical Characteristics........................................... Typical Characteristics .............................................. Detailed Description ............................................ 14 7.1 Overview ................................................................. 14 7.2 Functional Block Diagram ....................................... 15 7.3 Feature Description................................................. 15 7.4 Device Functional Modes........................................ 19 8 Application and Implementation ........................ 21 8.1 Application Information............................................ 21 8.2 Typical Applications ................................................ 22 9 Power Supply Recommendations...................... 29 10 Layout................................................................... 29 10.1 Layout Guidelines ................................................. 29 10.2 Layout Example .................................................... 30 11 Device and Documentation Support ................. 31 11.1 11.2 11.3 11.4 11.5 Receiving Notification of Documentation Updates Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 31 31 31 31 31 12 Mechanical, Packaging, and Orderable Information ........................................................... 31 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision C (February 2016) to Revision D Page * Added Feature: Green (RoHS Compatible), is Optional ....................................................................................................... 1 * Added the VQP package to the Thermal Infomation ............................................................................................................. 6 * From: a SC5026-1R0 inductor is used. To: a 744355182 inductor is used. .......................................................................... 8 * Changed Figure 32 and Figure 33 ....................................................................................................................................... 12 * 5-V LDO and VREG Start-Up, Changed the NOTE From: "The 5-V LDO is not controlled" To: "The 5-V LDO is controlled" ............................................................................................................................................................................. 15 * Changed 250 s To ~550 s in Figure 34............................................................................................................................ 16 Changes from Revision B (January 2014) to Revision C Page * Changed the datasheet Title From: "TPS53355 High-Efficiency 30-A Synchronous Buck Converter With EcomodeTM" To: "TPS53355 High-Efficiency 30-A Synchronous Buck SWIFTTM Converter With Eco-modeTM" ........................ 1 * Added Features: "For SWIFTTM Power Products Documentation,..." .................................................................................... 1 Changes from Revision A (September 2012) to Revision B * 2 Page Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1 Submit Documentation Feedback Copyright (c) 2011-2016, Texas Instruments Incorporated Product Folder Links: TPS53355 TPS53355 www.ti.com SLUSAE5D - AUGUST 2011 - REVISED NOVEMBER 2016 Changes from Original (August 2011) to Revision A Page * Changed conversion input voltage from "3 V" to "1.5 V" ....................................................................................................... 1 * Changed VIN input voltage range minimum from "3 V" to "1.5 V" ......................................................................................... 4 * Changed typographical error in THERMAL INFORMATION table......................................................................................... 5 * Changed VIN (main supply) input voltage range minimum from "3 V' to "1.5 V" in Recommended Operating Conditions... 5 * Changed VIN pin power conversion input minimum voltage from "3 V" to "1.5 V" in ELECTRICAL CHARACTERISTICS table ..................................................................................................................................................... 6 * Changed conversion input voltage range from "3 V" to "1.5" in Overview ........................................................................... 14 * Added note to the Functional Block Diagram ....................................................................................................................... 15 * Changed "ripple injection capacitor" to "ripple injection resistor" in Layout Guidelines section ........................................... 29 Submit Documentation Feedback Copyright (c) 2011-2016, Texas Instruments Incorporated Product Folder Links: TPS53355 3 TPS53355 SLUSAE5D - AUGUST 2011 - REVISED NOVEMBER 2016 www.ti.com 5 Pin Configuration and Functions Package With PowerPad 22-Pins (LSON-CLIP) Top View (1) VFB 1 22 RF EN 2 21 TRIP PGOOD 3 20 MODE VBST 4 19 VDD N/C 5 18 VREG LL 6 17 VIN LL 7 16 VIN LL 8 15 VIN LL 9 14 VIN LL 10 13 VIN LL 11 12 VIN GND PowerPad TM N/C = no connection Pin Functions PIN NAME NO I/O/P (1) DESCRIPTION EN 2 I GND -- -- Enable pin. Typical turn-on threshold voltage is 1.2 V. Typical turn-off threshold is 0.95 V. Ground and thermal pad of the device. Use proper number of vias to connect to ground plane. B Output of converted power. Connect this pin to the output Inductor. I Soft-start and Skip/CCM selection. Connect a resistor to select soft-start time using Table 3. The soft-start time is detected and stored into internal register during start-up. 6 7 8 LL 9 10 11 MODE 20 N/C 5 PGOOD 3 O Open drain power good flag. Provides 1-ms start-up delay after VFB falls in specified limits. When VFB goes out of the specified limits PGOOD goes low after a 2-s delay. RF 22 I Switching frequency selection. Connect a resistor to GND or VREG to select switching frequency using Table 1. The switching frequency is detected and stored during the startup. TRIP 21 I No connect. OCL detection threshold setting pin. ITRIP = 10 A at room temperature, 4700 ppm/C current is sourced and set the OCL trip voltage as follows: space VOCL = VTRIP/32 (VTRIP 2.4 V, VOCL 75 mV) VBST 4 P Supply input for high-side FET gate driver (boost terminal). Connect capacitor from this pin to LL node. Internally connected to VREG via bootstrap MOSFET switch. VDD 19 P Controller power supply input. VDD input voltage range is from 4.5 V to 25 V. 1 I Output feedback input. Connect this pin to Vout through a resistor divider. P Conversion power input. VIN input voltage range is from 1.5 V to 15 V. P 5-V low drop out (LDO) output. Supplies the internal analog circuitry and driver circuitry. VFB 12 13 14 VIN 15 16 17 VREG (1) 4 18 I=Input, O=Output, B=Bidirectional, P=Supply Submit Documentation Feedback Copyright (c) 2011-2016, Texas Instruments Incorporated Product Folder Links: TPS53355 TPS53355 www.ti.com SLUSAE5D - AUGUST 2011 - REVISED NOVEMBER 2016 6 Specifications 6.1 Absolute Maximum Ratings (1) Input voltage MIN MAX VIN (main supply) -0.3 25 VDD -0.3 28 VBST -0.3 32 VBST (with respect to LL) -0.3 7 EN, TRIP, VFB, RF, MODE -0.3 7 -2 25 DC LL Output voltage Source/Sink current -7 27 PGOOD, VREG Pulse < 20ns, E=5 J -0.3 7 GND -0.3 0.3 VBST V V 50 mA Operating free-air temperature, TA -40 85 Junction temperature, TJ -40 150 Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds C 300 Storage temperature, Tstg (1) UNIT -55 150 C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 6.2 ESD Ratings VALUE Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 V(ESD) (1) (2) Electrostatic discharge (1) UNIT 2000 Charged-device model (CDM), per JEDEC specification JESD22C101 (2) V 500 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) Input voltage range MIN MAX VIN (main supply) 1.5 15 VDD 4.5 25 VBST 4.5 28 4.5 6.5 -0.1 6.5 VBST (with respect to LL) EN, TRIP, VFB, RF, MODE Output voltage range LL PGOOD, VREG Junction temperature range, TJ -1 22 -0.1 6.5 -40 125 Submit Documentation Feedback Copyright (c) 2011-2016, Texas Instruments Incorporated Product Folder Links: TPS53355 UNIT V V C 5 TPS53355 SLUSAE5D - AUGUST 2011 - REVISED NOVEMBER 2016 www.ti.com 6.4 Thermal Infomation TPS53355 THERMAL METRIC (1) DQP VQP 22 PINS 22 PINS JA Junction-to-ambient thermal resistance 27.2 27.2 JCtop Junction-to-case (top) thermal resistance 17.1 17.1 JB Junction-to-board thermal resistance 5.9 5.9 JT Junction-to-top characterization parameter 0.8 0.8 JB Junction-to-board characterization parameter 5.8 5.8 JCbot Junction-to-case (bottom) thermal resistance 1.2 1.2 (1) UNIT C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. 6.5 Electrical Characteristics Over recommended free-air temperature range, VVDD= 12 V (unless otherwise noted) PARAMETER CONDITIONS MIN TYP MAX UNIT SUPPLY CURRENT VVIN VIN pin power conversion input voltage VVDD Supply input voltage IVIN(leak) VIN pin leakage current VEN = 0 V IVDD VDD supply current TA = 25C, No load, VEN = 5 V, VVFB = 0.630 V IVDDSDN VDD shutdown current TA = 25C, No load, VEN = 0 V 1.5 15 4.5 25.0 V 1 A 590 A 10 A 420 V INTERNAL REFERENCE VOLTAGE VVFB VFB regulation voltage CCM condition (1) 0.600 TA = 25C VVFB VFB regulation voltage 0C TA 85C -40C TA 85C IVFB VFB input current V 0.597 0.600 0.603 0.5952 0.600 0.6048 0.594 0.600 0.606 0.01 0.20 5.00 5.36 VVFB = 0.630 V, TA = 25C V A LDO OUTPUT VVREG LDO output voltage 0 mA IVREG 30 mA IVREG LDO output current (1) Maximum current allowed from LDO VDO Low drop out voltage VVDD = 4.5 V, IVREG = 30 mA 4.77 V 30 mA 230 mV BOOT STRAP SWITCH VFBST Forward voltage VVREG-VBST, IF = 10 mA, TA = 25C IVBSTLK VBST leakage current VVBST = 23 V, VSW = 17 V, TA = 25C 0.1 0.2 V 0.01 1.50 A 260 400 ns DUTY AND FREQUENCY CONTROL tOFF(min) tON(min) Minimum off time TA = 25C Minimum on time VIN = 17 V, VOUT = 0.6 V, RRF = 39 k, TA = 25 C (1) 150 35 RMODE = 39 k 0.7 RMODE = 100 k 1.4 RMODE = 200 k 2.8 RMODE = 470 k 5.6 ns SOFT START Internal soft-start time from VOUT = 0 V to 95% of VOUT tSS ms INTERNAL MOSFETS RDS(on)H High-side MOSFET on-resistance TA = 25C 5.0 m RDS(on)L Low-side MOSFET on-resistance TA = 25C 2.0 m (1) 6 Ensured by design. Not production tested. Submit Documentation Feedback Copyright (c) 2011-2016, Texas Instruments Incorporated Product Folder Links: TPS53355 TPS53355 www.ti.com SLUSAE5D - AUGUST 2011 - REVISED NOVEMBER 2016 Electrical Characteristics (continued) Over recommended free-air temperature range, VVDD= 12 V (unless otherwise noted) PARAMETER CONDITIONS MIN TYP MAX UNIT POWERGOOD VTHPG PG threshold RPG PG transistor on-resistance tPGDEL PG delay PG in from lower 92.5% 95.0% 98.5% PG in from higher 107.5% 110.0% 112.5% 2.5% 5.0% 7.5% 15 30 55 Delay for PG in 0.8 1 1.2 ms Enable 1.8 PG hysteresis LOGIC THRESHOLD AND SETTING CONDITIONS VEN EN Voltage V Disable IEN EN Input current 0.6 VEN = 5 V 1.0 RRF = 0 to GND, TA = 25C fSW Switching frequency (2) 200 250 300 RRF = 187 k to GND, TA = 25C (2) 250 300 350 RRF = 619 k, to GND, TA = 25C (2) 350 400 450 RRF = Open, TA= 25C (2) 450 500 550 RRF = 866 k to VREG, TA = 25C (2) 580 650 720 RRF = 309 k to VREG, TA = 25C (2) 670 750 820 RRF = 124 k to VREG, TA = 25C (2) 770 850 930 880 970 1070 9.4 10.0 10.6 RRF = 0 to VREG, TA = 25C (2) A kHz PROTECTION: CURRENT SENSE ITRIP TRIP source current VTRIP = 1 V, TA = 25C TCITRIP TRIP current temperature coefficient On the basis of 25C VTRIP Current limit threshold setting range VTRIP-GND VOCL Current limit threshold VOCLN Negative current limit threshold VAZCADJ Auto zero cross adjustable range (1) 4700 ppm/C 0.4 2.4 VTRIP = 2.4 V 68.5 75.0 81.5 VTRIP = 0.4 V 7.5 12.5 17.5 VTRIP = 2.4 V -315 -300 -285 VTRIP = 0.4 V -58 -50 -42 3 15 Positive Negative A V mV mV mV -15 -3 115% 120% 125% 65% 70% 75% 0.8 1.0 1.2 ms 1.8 2.6 3.2 ms 4.00 4.20 4.33 PROTECTION: UVP and OVP VOVP OVP trip threshold OVP detect tOVPDEL OVP propagation delay VFB delay with 50-mV overdrive VUVP Output UVP trip threshold UVP detect tUVPDEL Output UVP propagation delay tUVPEN Output UVP enable delay From enable to UVP workable 1 s UVLO VUVVREG VREG UVLO threshold Wake up Hysteresis 0.25 Shutdown temperature (1) 145 V THERMAL SHUTDOWN TSDN (2) Thermal shutdown threshold Hysteresis (1) C 10 Not production tested. Test condition is VIN= 12 V, VOUT= 1.1 V, IOUT = 10 A using application circuit shown in Figure 47. Submit Documentation Feedback Copyright (c) 2011-2016, Texas Instruments Incorporated Product Folder Links: TPS53355 7 TPS53355 SLUSAE5D - AUGUST 2011 - REVISED NOVEMBER 2016 www.ti.com 6.6 Typical Characteristics 700 7 600 6 500 400 300 200 VEN = 5V VVDD = 12 V VVFB = 0.63 V No Load 100 0 -40 -25 -10 5 20 35 50 65 80 Junction Temperature (C) 95 5 4 3 2 0 -40 -25 -10 14 120 OVP/UVP Trip Threshold (%) 140 10 8 6 4 5 20 35 50 65 80 Junction Temperature (C) 95 100 80 60 40 20 2 OVP UVP VVDD = 12 V 0 -40 -25 -10 5 20 35 50 65 80 Junction Temperature (C) 95 0 -40 -25 -10 110 125 Figure 3. TRIP Pin Current vs. Junction Temperature 100 FCCM Skip Mode 10 VIN = 12 V VOUT = 1.1 V fSW = 300 kHz 0.1 1 Output Current (A) 10 100 Switching Frequency (kHz) Switching Frequency (kHz) 95 110 125 1000 Figure 5. Switching Frequency vs. Output Current 8 5 20 35 50 65 80 Junction Temperature (C) Figure 4. OVP/UVP Trip Threshold vs. Junction Temperature 1000 1 0.01 110 125 Figure 2. VDD Shutdown Current vs. Junction Temperature 16 12 VEN = 0 V VVDD = 12 V No Load 1 110 125 Figure 1. VDD Supply Current vs. Junction Temperature TRIP Pin Current (A) VDD Shutdown Current (A) VDD Supply Current (A) For VOUT = 5 V, a 744355182 inductor is used. For 1 VOUT 3.3 V, a PA0513.441 inductor is used. 100 FCCM Skip Mode 10 VIN = 12 V VOUT = 1.1 V fSW = 500 kHz 1 0.01 0.1 1 Output Current (A) 10 100 Figure 6. Switching Frequency vs. Output Current Submit Documentation Feedback Copyright (c) 2011-2016, Texas Instruments Incorporated Product Folder Links: TPS53355 TPS53355 www.ti.com SLUSAE5D - AUGUST 2011 - REVISED NOVEMBER 2016 Typical Characteristics (continued) For VOUT = 5 V, a 744355182 inductor is used. For 1 VOUT 3.3 V, a PA0513.441 inductor is used. 1000 Switching Frequency (kHz) Switching Frequency (kHz) 1000 100 10 VIN = 12 V VOUT = 1.1 V fSW = 750 kHz FCCM Skip Mode 1 0.01 0.1 1 Output Current (A) 10 10 VIN = 12 V VOUT = 1.1 V fSW = 1 MHz FCCM Skip Mode 1 0.01 100 0.1 G001 1 Output Current (A) 10 100 Figure 8. Switching Frequency vs. Output Current Figure 7. Switching Frequency vs. Output Current 1500 1.120 fSET = 300 kHz fSET = 500 kHz fSET = 750 kHz fSET = 1 MHz VIN = 12 V IOUT = 10 A 1200 fSW = 500 kHz VIN = 12 V VOUT = 1.1 V 1.115 1.110 Output Voltage (V) Switching Frequency (kHz) 100 900 600 1.105 1.100 1.095 1.090 300 1.085 0 0 1 2 3 4 Output Voltage (V) 5 1.080 6 Figure 9. Switching Frequency vs. Output Voltage Skip Mode FCCM 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 Output Current (A) Figure 10. Output Voltage vs. Output Current 1.120 100 fSW = 500 kHz VIN = 12 V 1.115 90 80 70 Efficiency (%) Output Voltage (V) 1.110 1.105 1.100 1.095 60 VIN = 12 V VVDD = 5 V VOUT = 1.1 V 50 40 30 Skip Mode, fSW = 500 kHz FCCM, fSW = 500 kHz Skip Mode, fSW = 300 kHz FCCM, fSW = 300 kHz 1.090 FCCM, IOUT = 0 A Skip Mode, IOUT = 0 A FCCM and Skip Mode, IOUT = 20 A 1.085 1.080 4 6 8 10 12 Input Voltage (V) 14 16 20 10 0 0.01 Figure 11. Output Voltage vs. Input Voltage 0.1 1 Output Current (A) 10 Figure 12. Efficiency vs Output Current Submit Documentation Feedback Copyright (c) 2011-2016, Texas Instruments Incorporated Product Folder Links: TPS53355 100 9 TPS53355 SLUSAE5D - AUGUST 2011 - REVISED NOVEMBER 2016 www.ti.com Typical Characteristics (continued) 100 100 95 95 90 90 Efficiency (%) Efficiency (%) For VOUT = 5 V, a 744355182 inductor is used. For 1 VOUT 3.3 V, a PA0513.441 inductor is used. 85 VOUT = 5.0 V VOUT = 3.3 V VOUT = 1.8 V VOUT = 1.5 V VOUT = 1.2 V VOUT = 1.1 V VOUT = 1.0 V 80 75 70 0 5 10 15 20 Output Current (A) FCCM VIN = 12 V VVDD = 5 V fSW = 300 kHz 25 85 VOUT = 5.0 V VOUT = 3.3 V VOUT = 1.8 V VOUT = 1.5 V VOUT = 1.2 V VOUT = 1.1 V VOUT = 1.0 V 80 75 70 30 0 100 95 95 90 90 85 VOUT = 5.0 V VOUT = 3.3 V VOUT = 1.8 V VOUT = 1.5 V VOUT = 1.2 V VOUT = 1.1 V VOUT = 1.0 V 80 75 70 0 5 10 15 20 Output Current (A) FCCM VIN = 12 V VVDD = 5 V fSW = 500 kHz 25 VOUT = 5.0 V VOUT = 3.3 V VOUT = 1.8 V VOUT = 1.5 V VOUT = 1.2 V VOUT = 1.1 V VOUT = 1.0 V 80 75 70 30 0 95 95 90 90 85 75 70 0 2 4 6 8 10 12 14 Output Current (A) FCCM VIN = 5 V VVDD = 5 V fSW = 500 kHz 16 5 10 15 20 Output Current (A) Skip Mode VIN = 12 V VVDD = 5 V fSW = 500 kHz 25 30 18 20 85 80 VOUT = 1.8 V VOUT = 1.5 V VOUT = 1.2 V VOUT = 1.1 V VOUT = 1.0 V 75 70 0 Figure 17. Efficiency vs Output Current 10 30 Figure 16. Efficiency vs Output Current 100 Efficiency (%) Efficiency (%) Figure 15. Efficiency vs Output Current VOUT = 1.8 V VOUT = 1.5 V VOUT = 1.2 V VOUT = 1.1 V VOUT = 1.0 V 25 85 100 80 10 15 20 Output Current (A) Figure 14. Efficiency vs Output Current 100 Efficiency (%) Efficiency (%) Figure 13. Efficiency vs Output Current 5 Skip Mode VIN = 12 V VVDD = 5 V fSW = 300 kHz Submit Documentation Feedback 2 4 6 8 10 12 14 Output Current (A) Skip Mode VIN = 5 V VVDD = 5 V fSW = 500 kHz 16 18 20 Figure 18. Efficiency vs Output Current Copyright (c) 2011-2016, Texas Instruments Incorporated Product Folder Links: TPS53355 TPS53355 www.ti.com SLUSAE5D - AUGUST 2011 - REVISED NOVEMBER 2016 Typical Characteristics (continued) For VOUT = 5 V, a 744355182 inductor is used. For 1 VOUT 3.3 V, a PA0513.441 inductor is used. VIN = 12 V VIN = 12 V IOUT = 20 A EN (5 V/div) EN (5 V/div) IOUT = 0 A VOUT (0.5 V/div) VOUT (0.5 V/div) 0.5 V pre-biased VREG(5 V/div) VREG(5 V/div) PGOOD (5 V/div) PGOOD (5 V/div) Time (1 ms/div) Time (1 ms/div) Figure 20. Pre-Bias Start-Up Waveforms Figure 19. Start-Up Waveforms VIN = 12 V VEN = 5 V IOUT = 20 A EN (5 V/div) VIN (5 V/div) VDD = VIN IOUT = 20 A VOUT (0.5 V/div) VOUT (0.5 V/div) VREG(5 V/div) VREG(5 V/div) PGOOD (5 V/div) PGOOD (5 V/div) Time (20 ms/div) Time (2 ms/div) Figure 21. Shutdown Waveforms Figure 22. UVLO Start-Up Waveforms Skip Mode VIN = 12 V IOUT = 0 A FCCM VIN = 12 V IOUT = 0 A VOUT (20 mV/div) VOUT (20 mV/div) LL (5 V/div) LL (5 V/div) IL (5 A/div) IL (5 A/div) Time (2 ms/div) Time (1 ms/div) Figure 23. 1.1-V Output FCCM Mode Steady-State Operation Figure 24. 1.1-V Output Skip Mode Steady-State Operation Submit Documentation Feedback Copyright (c) 2011-2016, Texas Instruments Incorporated Product Folder Links: TPS53355 11 TPS53355 SLUSAE5D - AUGUST 2011 - REVISED NOVEMBER 2016 www.ti.com Typical Characteristics (continued) For VOUT = 5 V, a 744355182 inductor is used. For 1 VOUT 3.3 V, a PA0513.441 inductor is used. Skip Mode VIN = 12 V VOUT = 1.1 V Skip Mode VIN = 12 V VOUT = 1.1 V VOUT (20 mV/div) VOUT (20 mV/div) LL (5 V/div) LL (5 V/div) IL (5 A/div) IL (5 A/div) Time (200 ms/div) Time (200 ms/div) Figure 25. CCM to DCM Transition Waveforms Figure 26. DCM to CCM Transition Waveforms FCCM VIN = 12 V, VOUT = 1.1 V Skip Mode VIN = 12 V, VOUT = 1.1 V IOUT from 0 A to 10 A, 2.5 A/ms IOUT from 0 A to 10 A, 2.5 A/ms VOUT (20 mV/div) VOUT (20 mV/div) IOUT (5 A/div) IOUT (5 A/div) Time (100 ms/div) Time (100 ms/div) Figure 28. Skip Mode Load Transeint Figure 27. FCCM Load Transient IOUT from 20 A to 25 A VOUT (1 V/div) VOUT (1 V/div) IOUT 2 A then Short Output VIN = 12 V VIN = 12 V LL (10 V/div) LL (10 V/div) IL (10 A/div) IL (10 A/div) IOUT (25 A/div) PGOOD (5 V/div) Time (10 ms/div) Time (10 ms/div) Figure 29. Overcurrent Protection Waveforms 12 Figure 30. Output Short Circuit Protection Waveforms Submit Documentation Feedback Copyright (c) 2011-2016, Texas Instruments Incorporated Product Folder Links: TPS53355 TPS53355 www.ti.com SLUSAE5D - AUGUST 2011 - REVISED NOVEMBER 2016 Typical Characteristics (continued) For VOUT = 5 V, a 744355182 inductor is used. For 1 VOUT 3.3 V, a PA0513.441 inductor is used. 110 EN (5 V/div) Ambient Temperature (qC) 100 VOUT (1 V/div) VIN = 12 V IOUT = 20 A PGOOD (5 V/div) 90 80 70 60 50 Nat Conv 100 LFM 200 LFM 400 LFM 40 30 0 5 10 15 20 Output Current (A) Time (1 s/div) VIN = 12 V 25 VOUT = 1.2 V 30 D001 fSW = 500 kHz Figure 32. Safe Operating Area Figure 31. Over-temperature Protection Waveforms 110 Ambient Temperature (qC) 100 90 80 70 60 50 Nat Conv 100 LFM 200 LFM 400 LFM 40 30 0 5 VIN = 12 V 10 15 20 Output Current (A) VOUT = 5 V 25 30 D002 fSW = 500 kHz Figure 33. Safe Operating Area Submit Documentation Feedback Copyright (c) 2011-2016, Texas Instruments Incorporated Product Folder Links: TPS53355 13 TPS53355 SLUSAE5D - AUGUST 2011 - REVISED NOVEMBER 2016 www.ti.com 7 Detailed Description 7.1 Overview The TPS53355 is a high-efficiency, single channel, synchronous buck converter suitable for low output voltage point-of-load applications in computing and similar digital consumer applications. The device features proprietary D-CAPTM mode control combined with an adaptive on-time architecture. This combination is ideal for building modern low duty ratio, ultra-fast load step response DC-DC converters. The output voltage ranges from 0.6 V to 5.5 V. The conversion input voltage range is from 1.5 V up to 15 V and the VDD bias voltage is from 4.5 V to 25 V. The D-CAPTM mode uses the equivalent series resistance (ESR) of the output capacitor(s) to sense the device current. One advantage of this control scheme is that it does not require an external phase compensation network. This allows a simple design with a low external component count. Eight preset switching frequency values can be chosen using a resistor connected from the RF pin to ground or VREG. Adaptive on-time control tracks the preset switching frequency over a wide input and output voltage range while allowing the switching frequency to increase at the step-up of the load. The TPS53355 has a MODE pin to select between auto-skip mode and forced continuous conduction mode (FCCM) for light load conditions. The MODE pin also sets the selectable soft-start time ranging from 0.7 ms to 5.6 ms as shown in Table 3. 14 Submit Documentation Feedback Copyright (c) 2011-2016, Texas Instruments Incorporated Product Folder Links: TPS53355 TPS53355 www.ti.com SLUSAE5D - AUGUST 2011 - REVISED NOVEMBER 2016 7.2 Functional Block Diagram 0.6 V +10/15% 0.6 V -30% + UV PGOOD + Delay Delay + 0.6 V -5/10% Ramp Compensation Control Logic + OV +20% + VFB VREG 0.6 V SS UVP/OVP Logic RF VBST + + PWM VIN 10 mA GND TRIP tON OneShot + + OCP LL LL XCON + GND ZC Control Logic SS FCCM/ Skip Decode MODE EN * * * * * + 1.2 V/0.95 V GND On/Off time Minimum On/Off Light load OVP/UVP FCCM/Skip VDDOK LL Fault Shutdown TPS53355 LDO + VDD 4.2 V/ 3.95 V Enable THOK VREG EN + 145C/ 135C Copyright (c) 2016, Texas Instruments Incorporated NOTE The thresholds in this block diagram are typical values. Refer to the Electrical Characteristics table for threshold limits. 7.3 Feature Description 7.3.1 5-V LDO and VREG Start-Up TPS53355 provides an internal 5-V LDO function using input from VDD and output to VREG. When the VDD voltage rises above 2 V, the internal LDO is enabled and outputs voltage to the VREG pin. The VREG voltage provides the bias voltage for the internal analog circuitry and also provides the supply voltage for the gate drives. NOTE The 5-V LDO is controlled by the EN pin. The LDO starts-up any time VDD rises to approximately 2 V. Figure 34 Submit Documentation Feedback Copyright (c) 2011-2016, Texas Instruments Incorporated Product Folder Links: TPS53355 15 TPS53355 SLUSAE5D - AUGUST 2011 - REVISED NOVEMBER 2016 www.ti.com Feature Description (continued) 7.3.2 Adaptive On-Time D-CAP Control and Frequency Selection The TPS53355 does not have a dedicated oscillator to determine switching frequency. However, the device operates with pseudo-constant frequency by feed-forwarding the input and output voltages into the on-time oneshot timer. The adaptive on-time control adjusts the on-time to be inversely proportional to the input voltage and proportional to the output voltage (tON VOUT/VIN). This makes the switching frequency fairly constant in steady state conditions over a wide input voltage range. The switching frequency is selectable from eight preset values by a resistor connected between the RF pin and GND or between the RF pin and the VREG pin as shown in Table 1. (Maintaining open resistance sets the switching frequency to 500 kHz.) Table 1. Resistor and Switching Frequency RESISTOR (RRF) CONNECTIONS VALUE (k) CONNECT TO SWITCHING FREQUENCY (fSW) (kHz) 0 GND 250 187 GND 300 619 GND 400 OPEN n/a 500 866 VREG 650 309 VREG 750 124 VREG 850 0 VREG 970 The off-time is modulated by a PWM comparator. The VFB node voltage (the mid-point of resistor divider) is compared to the internal 0.6-V reference voltage added with a ramp signal. When both signals match, the PWM comparator asserts a set signal to terminate the off time (turn off the low-side MOSFET and turn on high-side MOSFET). The set signal is valid if the inductor current level is below the OCP threshold, otherwise the off time is extended until the current level falls below the threshold. Figure 35 and Figure 36 show two on-time control schemes. VFB Above 2 V VDD VREF VREG 0.6 V EN PWM tON VREF tOFF VOUT Soft-start UDG-10208 ~550 s Figure 34. Power Up Sequence 16 Figure 35. On-Time Control Without Ramp Compensation Submit Documentation Feedback Copyright (c) 2011-2016, Texas Instruments Incorporated Product Folder Links: TPS53355 TPS53355 www.ti.com SLUSAE5D - AUGUST 2011 - REVISED NOVEMBER 2016 VFB VREF Compensation Ramp PWM tON tOFF UDG-10209 Figure 36. On-Time Control With Ramp Compensation 7.3.3 Ramp Signal The TPS53355 adds a ramp signal to the 0.6-V reference in order to improve jitter performance. As described in the previous section, the feedback voltage is compared with the reference information to keep the output voltage in regulation. By adding a small ramp signal to the reference, the signal-to-noise ratio at the onset of a new switching cycle is improved. Therefore the operation becomes less jittery and more stable. The ramp signal is controlled to start with -7 mV at the beginning of an on-cycle and becomes 0 mV at the end of an off-cycle in steady state. During skip mode operation, under discontinuous conduction mode (DCM), the switching frequency is lower than the nominal frequency and the off-time is longer than the off-time in CCM. Because of the longer off-time, the ramp signal extends after crossing 0 mV. However, it is clamped at 3 mV to minimize the DC offset. 7.3.4 Adaptive Zero Crossing The TPS53355 has an adaptive zero crossing circuit which performs optimization of the zero inductor current detection at skip mode operation. This function pursues ideal low-side MOSFET turning off timing and compensates inherent offset voltage of the Z-C comparator and delay time of the Z-C detection circuit. It prevents SW-node swing-up caused by too late detection and minimizes diode conduction period caused by too early detection. As a result, better light load efficiency is delivered. 7.3.5 Power-Good The TPS53355 has power-good output that indicates high when switcher output is within the target. The powergood function is activated after soft-start has finished. If the output voltage becomes within +10% and -5% of the target value, internal comparators detect power-good state and the power-good signal becomes high after a 1ms internal delay. If the output voltage goes outside of +15% or -10% of the target value, the power-good signal becomes low after two microsecond (2-s) internal delay. The power-good output is an open drain output and must be pulled up externally. The power-good MOSFET is powered through the VDD pin. VVDD must be >1 V in order to have a valid powergood logic. It is recommended to pull PGOOD up to VREG (or a voltage divided from VREG) so that the powergood logic is still valid even without VDD supply. 7.3.6 Current Sense, Overcurrent and Short Circuit Protection TPS53355 has cycle-by-cycle overcurrent limiting control. The inductor current is monitored during the OFF state and the controller maintains the OFF state during the period in that the inductor current is larger than the overcurrent trip level. In order to provide both good accuracy and cost effective solution, TPS53355 supports temperature compensated MOSFET RDS(on) sensing. The TRIP pin should be connected to GND through the trip voltage setting resistor, RTRIP. The TRIP terminal sources current (ITRIP) which is 10 A typically at room temperature, and the trip level is set to the OCL trip voltage VTRIP as shown in Equation 1. VTRIP (mV ) = RTRIP (kW ) ITRIP (mA ) (1) Submit Documentation Feedback Copyright (c) 2011-2016, Texas Instruments Incorporated Product Folder Links: TPS53355 17 TPS53355 SLUSAE5D - AUGUST 2011 - REVISED NOVEMBER 2016 www.ti.com The inductor current is monitored by the LL pin. The GND pin is used as the positive current sensing node and the LL pin is used as the negative current sense node. The trip current, ITRIP has 4700ppm/C temperature slope to compensate the temperature dependency of the RDS(on). As the comparison is made during the OFF state, VTRIP sets the valley level of the inductor current. Thus, the load current at the overcurrent threshold, IOCP, can be calculated as shown in Equation 2. IOCP = VTRIP (32 RDS(on) ) + IIND(ripple) 2 = VTRIP (32 RDS(on) ) + (VIN - VOUT ) VOUT 1 2 L fSW VIN (2) In an overcurrent or short circuit condition, the current to the load exceeds the current to the output capacitor thus the output voltage tends to decrease. Eventually, it crosses the undervoltage protection threshold and shuts down. After a hiccup delay (16 ms with 0.7 ms sort-start), the controller restarts. If the overcurrent condition remains, the procedure is repeated and the device enters hiccup mode. Hiccup time calculation: tHIC(wait) = (2n + 257) x 4 s where * n = 8, 9, 10, or 11 depending on soft start time selection tHIC(dly) = 7 x (2n + 257) x 4 s (3) (4) Table 2. Hiccup Delay SELECTED SOFT-START TIME (tSS) (ms) n HICCUP WAIT TIME (tHIC(wait)) (ms) HICCUP DELAY TIME (tHIC(dly)) (ms) 0.7 8 2.052 14.364 1.4 9 3.076 21.532 2.8 10 5.124 35.868 5.6 11 9.220 64.540 7.3.7 Overvoltage and Undervoltage Protection TPS53355 monitors a resistor divided feedback voltage to detect over and under voltage. When the feedback voltage becomes lower than 70% of the target voltage, the UVP comparator output goes high and an internal UVP delay counter begins counting. After 1ms, TPS53355 latches OFF both high-side and low-side MOSFETs drivers. The controller restarts after a hiccup delay (16 ms with 0.7 ms soft-start). This function is enabled 1.5-ms after the soft-start is completed. When the feedback voltage becomes higher than 120% of the target voltage, the OVP comparator output goes high and the circuit latches OFF the high-side MOSFET driver and latches ON the low-side MOSFET driver. The output voltage decreases. If the output voltage reaches UV threshold, then both high-side MOSFET and low-side MOSFET driver will be OFF and the device restarts after a hiccup delay. If the OV condition remains, both highside MOSFET and low-side MOSFET driver remains OFF until the OV condition is removed. 7.3.8 UVLO Protection The TPS53355 uses VREG undervoltage lockout protection (UVLO). When the VREG voltage is lower than 3.95 V, the device shuts off. When the VREG voltage is higher than 4.2 V, the device restarts. This is a non-latch protection. 7.3.9 Thermal Shutdown TPS53355 monitors the temperature of itself. If the temperature exceeds the threshold value (typically 145C), TPS53355 is shut off. When the temperature falls about 10C below the threshold value, the device will turn back on. This is a non-latch protection. 18 Submit Documentation Feedback Copyright (c) 2011-2016, Texas Instruments Incorporated Product Folder Links: TPS53355 TPS53355 www.ti.com SLUSAE5D - AUGUST 2011 - REVISED NOVEMBER 2016 7.4 Device Functional Modes 7.4.1 Enable, Soft Start, and Mode Selection When the EN pin voltage rises above the enable threshold voltage (typically 1.2 V), the controller enters its startup sequence. The internal LDO regulator starts immediately and regulates to 5 V at the VREG pin. The controller then uses the first 250 s to calibrate the switching frequency setting resistance attached to the RF pin and stores the switching frequency code in internal registers. During this period, the MODE pin also senses the resistance attached to this pin and determines the soft-start time. Switching is inhibited during this phase. In the second phase, an internal DAC starts ramping up the reference voltage from 0 V to 0.6 V. Depending on the MODE pin setting, the ramping up time varies from 0.7 ms to 5.6 ms. Smooth and constant ramp-up of the output voltage is maintained during start-up regardless of load current. Table 3. Soft-Start and MODE Settings MODE SELECTION Auto Skip Forced CCM (1) (1) ACTION SOFT-START TIME (ms) Pull down to GND Connect to PGOOD RMODE (k) 0.7 39 1.4 100 2.8 200 5.6 475 0.7 39 1.4 100 2.8 200 5.6 475 Device enters FCCM after the PGOOD pin goes high when MODE is connected to PGOOD through the resistor RMODE. After soft-start begins, the MODE pin becomes the input of an internal comparator which determines auto skip or FCCM mode operation. If MODE voltage is higher than 1.3 V, the converter enters into FCCM mode. Otherwise it will be in auto skip mode at light load condition. Typically, when FCCM mode is selected, the MODE pin is connected to PGOOD through the RMODE resistor, so that before PGOOD goes high the converter remains in auto skip mode. 7.4.2 Auto-Skip Eco-modeTM Light Load Operation While the MODE pin is pulled low via RMODE, TPS53355 automatically reduces the switching frequency at light load conditions to maintain high efficiency. Detailed operation is described as follows. As the output current decreases from heavy load condition, the inductor current is also reduced and eventually comes to the point that its rippled valley touches zero level, which is the boundary between continuous conduction and discontinuous conduction modes. The synchronous MOSFET is turned off when this zero inductor current is detected. As the load current further decreases, the converter runs into discontinuous conduction mode (DCM). The on-time is kept almost the same as it was in the continuous conduction mode so that it takes longer time to discharge the output capacitor with smaller load current to the level of the reference voltage. The transition point to the lightload operation IOUT(LL) (i.e., the threshold between continuous and discontinuous conduction mode) can be calculated as shown in Equation 5. IOUT(LL ) = (VIN - VOUT ) VOUT 1 2 L fSW VIN where * SW is the PWM switching frequency (5) Switching frequency versus output current in the light load condition is a function of L, VIN and VOUT, but it decreases almost proportionally to the output current from the IOUT(LL) given in Equation 5. For example, it is 60 kHz at IOUT(LL)/5 if the frequency setting is 300 kHz. Submit Documentation Feedback Copyright (c) 2011-2016, Texas Instruments Incorporated Product Folder Links: TPS53355 19 TPS53355 SLUSAE5D - AUGUST 2011 - REVISED NOVEMBER 2016 www.ti.com 7.4.3 Forced Continuous Conduction Mode When the MODE pin is tied to PGOOD through a resistor, the controller keeps continuous conduction mode (CCM) in light load condition. In this mode, switching frequency is kept almost constant over the entire load range which is suitable for applications that need tight control of the switching frequency at a cost of lower efficiency. 20 Submit Documentation Feedback Copyright (c) 2011-2016, Texas Instruments Incorporated Product Folder Links: TPS53355 TPS53355 www.ti.com SLUSAE5D - AUGUST 2011 - REVISED NOVEMBER 2016 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The TPS53355 is a high-efficiency, single channel, synchronous buck converter suitable for low output voltage point-of-load applications in computing and similar digital consumer applications. The device features proprietary D-CAP mode control combined with an adaptive on-time architecture. This combination is ideal for building modern low duty ratio, ultra-fast load step response DC-DC converters. The output voltage ranges from 0.6 V to 5.5 V. The conversion input voltage range is from 1.5 V up to 15 V and the VDD bias voltage is from 4.5 V to 25 V. The D-CAP mode uses the equivalent series resistance (ESR) of the output capacitor(s) to sense the device current . One advantage of this control scheme is that it does not require an external phase compensation network. This allows a simple design with a low external component count. Eight preset switching frequency values can be chosen using a resistor connected from the RF pin to ground or VREG. Adaptive on-time control tracks the preset switching frequency over a wide input and output voltage range while allowing the switching frequency to increase at the step-up of the load. 8.1.1 Small Signal Model From small-signal loop analysis, a buck converter using D-CAPTM mode can be simplified as shown in Figure 37. TPS53355 Switching Modulator VIN VIN R1 VFB PWM 1 R2 + + Control Logic and Divider LL L VOUT IIND IC IOUT 0.6 V ESR RLOAD Voltage Divider VC COUT Output Capacitor Copyright (c) 2016, Texas Instruments Incorporated Figure 37. Simplified Modulator Model The output voltage is compared with the internal reference voltage (ramp signal is ignored here for simplicity). The PWM comparator determines the timing to turn on the high-side MOSFET. The gain and speed of the comparator can be assumed high enough to keep the voltage at the beginning of each on cycle substantially constant. 1 H (s ) = s ESR COUT (6) For loop stability, the 0-dB frequency, 0, defined below need to be lower than 1/4 of the switching frequency. Submit Documentation Feedback Copyright (c) 2011-2016, Texas Instruments Incorporated Product Folder Links: TPS53355 21 TPS53355 SLUSAE5D - AUGUST 2011 - REVISED NOVEMBER 2016 www.ti.com Application Information (continued) f0 = f 1 SW 2p ESR COUT 4 (7) TM According to the equation above, the loop stability of D-CAP mode modulator is mainly determined by the capacitor's chemistry. For example, specialty polymer capacitors (SP-CAP) have an output capacitance in the order of several 100 F and ESR in range of 10 m. These makes 0 on the order of 100 kHz or less, creating a stable loop. However, ceramic capacitors have an 0 at more than 700 kHz, and need special care when used with this modulator. An application circuit for ceramic capacitor is described in External Component Selection Using All Ceramic Output Capacitors. 8.2 Typical Applications 8.2.1 Typical Application Circuit Diagram with Ceramic Output Capacitors C4 4.7 mF R4 NI R8 147 kW C3 1 mF VVDD 4.5 V to 25 V R6 200 kW 22 21 20 19 18 RF TRIP MODE VDD 17 VREG VIN 16 15 14 13 12 VIN VIN VIN VIN VIN TPS53355 CIN 22 mF VFB EN 1 2 PGOOD EN PGOOD VBST 3 4 N/C LL LL LL LL LL LL 5 6 7 8 9 10 11 R2 10 kW R7 3.01 kW R11 NI R9 2W C5 0.1 mF CIN 22 mF CIN 22 mF VOUT L1 0.44 mH PA0513.441 GND VREG R10 100 kW CIN 22 mF VIN 8 V to 14 V C1 0.1 mF C2 1 nF COUT 4 x 100 mF Ceramic C6 NI R1 14.7 kW Copyright (c) 2016, Texas Instruments Incorporated Figure 38. Typical Application Circuit Diagram with Ceramic Output Capacitors Schematic 22 Submit Documentation Feedback Copyright (c) 2011-2016, Texas Instruments Incorporated Product Folder Links: TPS53355 TPS53355 www.ti.com SLUSAE5D - AUGUST 2011 - REVISED NOVEMBER 2016 Typical Applications (continued) 8.2.1.1 Design Requirements Table 4. Design Parameters PARAMETER TEST CONDITION MIN TYP MAX 12 14 UNIT INPUT CHARACTERISTICS VIN Voltage range IMAX 8 Maximum input current VIN = 8 V, IOUT = 30 A No load input current VIN = 14 V, IOUT = 0 A with auto-skip mode V 6.3 A 1 mA OUTPUT CHARACTERISTICS Output voltage 1.5 Line regulation, 8 V VIN 15 V 0.1% Output voltage regulation Load regulation, VIN = 12 V, 0 A IOUT 30 A with FCCM 0.2% VRIPPLE Output voltage ripple VIN = 12 V, IOUT = 30 A with FCCM ILOAD Output load current IOCP Output overcurrent threshold 34 A tSS Soft-start time 1.4 ms 500 kHz VOUT 20 mVPP 0 30 A SYSTEMS CHARACTERISTICS fSW Switching frequency TA Peak efficiency VIN = 12 V, VOUT = 1.1 V, IOUT = 10 A 91.87% Full load efficiency VIN = 12 V, VOUT = 1.1 V, IOUT = 30 A 89.46% Operating temperature 25 C 8.2.1.2 Detailed Design Procedure 8.2.1.2.1 External Component Selection The external components selection is a simple process when using organic semiconductors or special polymer output capacitors. 1. Select operation mode and soft-start time Select operation mode and soft-start time using Table 3. 2. Select switching frequency Select the switching frequency from 250 kHz to 1 MHz using Table 1. 3. Choose the inductor The inductance value should be determined to give the ripple current of approximately 1/4 to 1/2 of maximum output current. Larger ripple current increases output ripple voltage and improves signal-to-noise ratio and helps ensure stable operation, but increases inductor core loss. Using 1/3 ripple current to maximum output current ratio, the inductance can be determined by Equation 8. L= 1 IIND(ripple ) fSW (V IN(max ) - VOUT ) V OUT VIN(max ) = 3 IOUT(max ) fSW (V IN(max ) - VOUT ) V OUT VIN(max) (8) The inductor requires a low DCR to achieve good efficiency. It also requires enough room above peak inductor current before saturation. The peak inductor current can be estimated in Equation 9. IIND(peak ) = VTRIP 1 + 32 RDS(on ) L fSW (V IN(max ) - VOUT ) V OUT VIN(max ) (9) Submit Documentation Feedback Copyright (c) 2011-2016, Texas Instruments Incorporated Product Folder Links: TPS53355 23 TPS53355 SLUSAE5D - AUGUST 2011 - REVISED NOVEMBER 2016 www.ti.com 4. External component selection with all ceramic output capacitors Refer to External Component Selection Using All Ceramic Output Capacitors to select external components because ceramic output capacitors are used in this design. 5. Choose the overcurrent setting resistor The overcurrent setting resistor, RTRIP, can be determined by Equation 10. ae ae o (VIN - VOUT ) VOUT 1 cc IOCP - c / VIN e 2 L fSW o e RTRIP (kW) = ITRIP (mA) o // 32 RDS(on) (mW ) o where * * ITRIP is the TRIP pin sourcing current (10 A) RDS(on) is the thermally compensated on-time resistance value of the low-side MOSFET (10) Use an RDS(on) value of 1.5 m for an overcurrent level of approximately 30 A. Use an RDS(on) value of 1.7 m for overcurrent level of approximately 10 A. 8.2.1.2.2 External Component Selection Using All Ceramic Output Capacitors When a ceramic output capacitor is used, the stability criteria in Equation 7 cannot be satisfied. The ripple injection approach as shown in Figure 38 is implemented to increase the ripple on the VFB pin and make the system stable. In addition to the selections made using steps 1 through step 6 in External Component Selection, the ripple injection components must be selected. The C2 value can be fixed at 1 nF. The value of C1 can be selected between 10 nF to 200 nF. L COUT t > N ON R7 C1 2 where * N is the coefficient to account for L and COUT variation (11) N is also used to provide enough margin for stability. It is recommended N=2 for VOUT 1.8 V and N=4 for VOUT 3.3 V or when L 250 nH. The higher VOUT needs a higher N value because the effective output capacitance is reduced significantly with higher DC bias. For example, a 6.3-V, 22-F ceramic capacitor may have only 8 F of effective capacitance when biased at 5 V. Because the VFB pin voltage is regulated at the valley, the increased ripple on the VFB pin causes the increase of the VFB DC value. The AC ripple coupled to the VFB pin has two components, one coupled from SW node and the other coupled from the VOUT pin and they can be calculated using Equation 12 and Equation 13 when neglecting the output voltage ripple caused by equivalent series inductance (ESL). V - VOUT D VINJ _ SW = IN R7 C1 fSW (12) VINJ _ OUT = ESR IIND(ripple ) + IIND(ripple ) 8 COUT fSW (13) It is recommended that VINJ_SW to be less than 50 mV. If the calculated VINJ_SW is higher than 50 mV, then other parameters need to be adjusted to reduce it. For example, COUT can be increased to satisfy Equation 11 with a higher R7 value, thereby reducing VINJ_SW. The DC voltage at the VFB pin can be calculated by Equation 14: VINJ _ SW + VINJ _ OUT VVFB = 0.6 + 2 (14) And the resistor divider value can be determined by Equation 15: - VVFB V R2 R1 = OUT VVFB (15) 24 Submit Documentation Feedback Copyright (c) 2011-2016, Texas Instruments Incorporated Product Folder Links: TPS53355 TPS53355 www.ti.com SLUSAE5D - AUGUST 2011 - REVISED NOVEMBER 2016 8.2.1.3 Application Curves TPS5335EVM Enable Start Up TPS5335EVM Enable Shut Down Test condition: 12 Vin, 1.5 V/30 A Auto Skip Mode Test condition: 12 Vin, 1.5 V/30 A Auto Skip Mode CH1: EN CH1: EN CH2: 1.5 Vout CH2: 1.5 Vout CH3: PGOOD CH3: PGOOD Figure 40. Enable Turn-off Figure 39. Enable Turn-on TPS5335EVM Output Transient from DCM to CCM TPS5335EVM Output Transient from CCM to DCM Test condition: 12 Vin, 0 A -15 A Auto Skip Mode Test condition: 12 Vin, 1.5 V/15 A-0 A Auto Skip Mode CH1: 1.5 Vout CH1: 1.5 Vout CH4: Output Current CH4: Output Current Figure 41. Output Transient From DCM to CCM TPS5335EVM Output Transient from 0 A to 15 A Test condition: 12 Vin, 1.5 V/0 A-15 A FCCM Mode Figure 42. Output Transient From CCM to DCM TPS5335EVM 0.75 V Pre-bias Enable Start up Test condition: 12 Vin, 1.5 V/0 A FCCM Mode CH1: EN CH1: 1.5 Vout CH2: 1.5 Vout CH4: output Current CH3: PGOOD Figure 43. Output Transient With FCCM Mode Figure 44. Output 0.75-V Prebias Turn-on Submit Documentation Feedback Copyright (c) 2011-2016, Texas Instruments Incorporated Product Folder Links: TPS53355 25 TPS53355 SLUSAE5D - AUGUST 2011 - REVISED NOVEMBER 2016 TPS53355EVM Over Current Protection www.ti.com Test Condition: 12 Vin OCP Test Condition: 12 Vin, 1.5 V Short Circuit TPS53355EVM Short Circuit Protection Ch1: 1.5 Vout Ch1: 1.5 Vout Ch2: LL Ch2: LL Ch3: PGOOD Ch3: PGOOD Figure 46. Output Short Circuit Protection Figure 45. Output Overcurrent Protection 8.2.2 Typical Application Circuit C4 4.7 mF C3 1 mF R6 200 kW R4 NI VVDD 4.5 V to 25 V R8 147 kW 22 21 20 19 RF TRIP MODE VDD 18 17 VREG VIN 16 15 14 13 12 VIN VIN VIN VIN VIN TPS53355 C IN 22 mF C IN 22 mF C IN 22 mF VIN 8 V to 14 V C IN 22 mF GND VREG L1 0.44 mH PA 0513.441 R10 100 kW VFB EN PGOOD VBST N/C LL LL LL LL LL LL 1 2 3 4 5 6 7 8 9 10 11 R11 NI R9 2W PGOOD EN R2 10 kW VOUT C OUT 330 mF C6 NI C5 0.1 mF C OUT 330 mF R1 15 kW UDG-11002 Figure 47. Typical Application Circuit Diagram 8.2.2.1 Design Requirements Table 5. Design Parameters PARAMETER TEST CONDITION MIN TYP MAX 12 14 UNIT INPUT CHARACTERISTICS VIN IMAX Voltage range 8 Maximum input current VIN = 8 V, IOUT = 30 A No load input current VIN = 14 V, IOUT = 0 A with auto-skip mode 6.3 V A 1 mA OUTPUT CHARACTERISTICS Output voltage 1.5 Line regulation, 8 V VIN 15 V 0.1% Output voltage regulation Load regulation, VIN = 12 V, 0 A IOUT 30 A with FCCM 0.2% VRIPPLE Output voltage ripple VIN = 12 V, IOUT = 30 A with FCCM ILOAD Output load current IOCP Output overcurrent threshold VOUT 26 20 0 34 Submit Documentation Feedback mVPP 30 A A Copyright (c) 2011-2016, Texas Instruments Incorporated Product Folder Links: TPS53355 TPS53355 www.ti.com SLUSAE5D - AUGUST 2011 - REVISED NOVEMBER 2016 Table 5. Design Parameters (continued) PARAMETER tSS TEST CONDITION MIN TYP Soft-start time MAX UNIT 1.4 ms 500 kHz SYSTEMS CHARACTERISTICS fSW Switching frequency TA Peak efficiency VIN = 12 V, VOUT = 1.1 V, IOUT = 10 A 91.87% Full load efficiency VIN = 12 V, VOUT = 1.1 V, IOUT = 30 A 89.46% Operating temperature 25 C 8.2.2.2 Detailed Design Procedure 8.2.2.2.1 External Component Selection Refer to External Component Selection Using All Ceramic Output Capacitors for guidelines for this design with all ceramic output capacitors. The external components selection is a simple process when using organic semiconductors or special polymer output capacitors. 1. Select operation mode and soft-start time Select operation mode and soft-start time using Table 3. 2. Select switching frequency Select the switching frequency from 250 kHz to 1 MHz using Table 1. 3. Choose the inductor The inductance value should be determined to give the ripple current of approximately 1/4 to 1/2 of maximum output current. Larger ripple current increases output ripple voltage and improves signal-to-noise ratio and helps ensure stable operation, but increases inductor core loss. Using 1/3 ripple current to maximum output current ratio, the inductance can be determined by Equation 16. L= 1 IIND(ripple ) fSW (V IN(max ) - VOUT ) V OUT VIN(max ) = 3 IOUT(max ) fSW (V IN(max ) - VOUT ) V OUT VIN(max) (16) The inductor requires a low DCR to achieve good efficiency. It also requires enough room above peak inductor current before saturation. The peak inductor current can be estimated in Equation 9. IIND(peak ) = VTRIP 1 + 32 RDS(on ) L fSW (V IN(max ) - VOUT ) V OUT VIN(max ) (17) 4. Choose the output capacitors When organic semiconductor capacitor(s) or specialty polymer capacitor(s) are used, for loop stability, capacitance and ESR should satisfy Equation 7. For jitter performance, Equation 18 is a good starting point to determine ESR. 10mV (1 - D) 10mV L fSW L fSW V = = ESR = OUT (W ) 0.6 V IIND(ripple ) 0.6 V 60 where * * D is the duty factor. The required output ripple slope is approximately 10 mV per tSW (switching period) in terms of VFB terminal voltage. (18) Submit Documentation Feedback Copyright (c) 2011-2016, Texas Instruments Incorporated Product Folder Links: TPS53355 27 TPS53355 SLUSAE5D - AUGUST 2011 - REVISED NOVEMBER 2016 www.ti.com 5. Determine the value of R1 and R2 The output voltage is programmed by the voltage-divider resistor, R1 and R2 shown in Figure 37. R1 is connected between VFB pin and the output, and R2 is connected between the VFB pin and GND. Recommended R2 value is from 1 k to 20 k. Determine R1 using Equation 19. IIND(ripple ) ESR - 0.6 VOUT 2 R2 R1 = 0.6 (19) 6. Choose the overcurrent setting resistor The overcurrent setting resistor, RTRIP, can be determined by Equation 10. ae ae o (VIN - VOUT ) VOUT 1 cc IOCP - c / VIN e 2 L fSW o e RTRIP (kW) = ITRIP (mA) o // 32 RDS(on) (mW ) o where * * ITRIP is the TRIP pin sourcing current (10 A) RDS(on) is the thermally compensated on-time resistance value of the low-side MOSFET (20) Use an RDS(on) value of 1.5 m for an overcurrent level of approximately 30 A. Use an RDS(on) value of 1.7 m for overcurrent level of approximately 10 A. 8.2.2.3 Application Curves TPS5335EVM Enable Start Up Test condition: 12 Vin, 1.5 V/30 A Auto Skip Mode TPS5335EVM Enable Shut Down Test condition: 12 Vin, 1.5 V/30 A Auto Skip Mode CH1: EN CH1: EN CH2: 1.5 Vout CH2: 1.5 Vout CH3: PGOOD CH3: PGOOD Figure 49. Enable Turn-off Figure 48. Enable Turn-on 28 Submit Documentation Feedback Copyright (c) 2011-2016, Texas Instruments Incorporated Product Folder Links: TPS53355 TPS53355 www.ti.com SLUSAE5D - AUGUST 2011 - REVISED NOVEMBER 2016 9 Power Supply Recommendations The device is designed to operate from an input voltage supply range between 1.5 V and 22 V (4.5-V to 25-V biased). This input supply must be well regulated. Proper bypassing of input supplies and internal regulators is also critical for noise performance, as is PCB layout and grounding scheme. See the recommendations in Layout. 10 Layout 10.1 Layout Guidelines Certain points must be considered before starting a layout work using the TPS53355. * The power components (including input/output capacitors, inductor and TPS53355) should be placed on one side of the PCB (solder side). At least one inner plane should be inserted, connected to ground, in order to shield and isolate the small signal traces from noisy power lines. * All sensitive analog traces and components such as VFB, PGOOD, TRIP, MODE and RF should be placed away from high-voltage switching nodes such as LL, VBST to avoid coupling. Use internal layer(s) as ground plane(s) and shield feedback trace from power traces and components. * Place the VIN decoupling capacitors as close to the VIN and PGND pins as possible to minimize the input AC current loop. * Because the TPS53355 controls output voltage referring to voltage across VOUT capacitor, the top-side resistor of the voltage divider should be connected to the positive node of the VOUT capacitor. The GND of the bottom side resistor should be connected to the GND pad of the device. The trace from these resistors to the VFB pin should be short and thin. * Place the frequency setting resistor (RF), OCP setting resistor (RTRIP) and mode setting resistor (RMODE) as close to the device as possible. Use the common GND via to connect them to GND plane if applicable. * Place the VDD and VREG decoupling capacitors as close to the device as possible. Make sure GND vias are provided for each decoupling capacitor and make the loop as small as possible. * The PCB trace defined as switch node, which connects the LL pins and high-voltage side of the inductor, should be as short and wide as possible. * Connect the ripple injection VOUT signal (VOUT side of the C1 capacitor in Figure 38) from the terminal of ceramic output capacitor. The AC coupling capacitor (C2 in Figure 38) should be placed near the device, and R7 and C1 can be placed near the power stage. * Use separate vias or trace to connect LL node to snubber, boot strap capacitor and ripple injection resistor. Do not combine these connections. Submit Documentation Feedback Copyright (c) 2011-2016, Texas Instruments Incorporated Product Folder Links: TPS53355 29 TPS53355 SLUSAE5D - AUGUST 2011 - REVISED NOVEMBER 2016 www.ti.com 10.2 Layout Example GND shape VOUT shape VIN shape LL shape VDD Bottom side component and trace VREG VBST PGOOD MODE TRIP RF EN VFB GND VOUT Bottom side components and trace Keep VFB trace short and away from noisy signals Bottom side components and trace To GND Plane UDG-11166 Figure 50. Layout Recommendation 30 Submit Documentation Feedback Copyright (c) 2011-2016, Texas Instruments Incorporated Product Folder Links: TPS53355 TPS53355 www.ti.com SLUSAE5D - AUGUST 2011 - REVISED NOVEMBER 2016 11 Device and Documentation Support 11.1 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 11.2 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2ETM Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.3 Trademarks Eco-mode, NexFET, PowerPAD, SWIFT, D-CAP, E2E are trademarks of Texas Instruments. All other trademarks are the property of their respective owners. 11.4 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 11.5 Glossary SLYZ022 -- TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright (c) 2011-2016, Texas Instruments Incorporated Product Folder Links: TPS53355 31 PACKAGE OPTION ADDENDUM www.ti.com 15-Apr-2017 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) HPA01111DQPR ACTIVE LSON-CLIP DQP 22 2500 Pb-Free (RoHS Exempt) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 53355DQP TPS53355DQPR ACTIVE LSON-CLIP DQP 22 2500 Pb-Free (RoHS Exempt) CU NIPDAU | CU SN Level-2-260C-1 YEAR -40 to 85 53355DQP TPS53355DQPT ACTIVE LSON-CLIP DQP 22 250 Pb-Free (RoHS Exempt) CU NIPDAU | CU SN Level-2-260C-1 YEAR -40 to 85 53355DQP (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 6-Jun-2018 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS53355DQPR LSONCLIP DQP 22 2500 330.0 15.4 5.3 6.3 1.8 8.0 12.0 Q1 TPS53355DQPT LSONCLIP DQP 22 250 330.0 15.4 5.3 6.3 1.8 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 6-Jun-2018 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS53355DQPR LSON-CLIP DQP 22 2500 336.6 336.6 41.3 TPS53355DQPT LSON-CLIP DQP 22 250 336.6 336.6 41.3 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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