TPS62140RGTT - Texas Instruments

100

0.0 0.4 0.8 1.2 1.6 2.0

VIN=5V VIN=12V VIN=17V

Output Current (A)

Efficiency (%)

VOUT=3.3V

fsw=1.25MHz

G001

22uF

1.8V / 2A

10uF

2.2 µH

(3 .. 17)V

3.3nF

TPS62141

PVIN

AVIN

SS/TR

DEF

FSW

VOS

AGND

PGND

100k

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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

TPS62140

TPS62140A

TPS62141

TPS62142

TPS62143

SLVSAJ0E –NOVEMBER 2011–REVISED SEPTEMBER 2016

TPS6214x 3-V to 17-V 2-A Step-Down Converter in 3 × 3 QFN Package

1 Features

1• DCS-ControlTM Topology

• Input Voltage Range: 3 V to 17 V

• Up to 2-A Output Current

• Adjustable Output Voltage from 0.9 V to 6 V

• Pin-Selectable Output Voltage (Nominal, +5%)

• Programmable Soft Start and Tracking

• Seamless Power-Save Mode Transition

• Quiescent Current of 17 µA (Typical)

• Selectable Operating Frequency

• Power-Good Output

• 100% Duty-Cycle Mode

• Short-Circuit Protection

• Over Temperature Protection

• Pin to Pin Compatible with TPS62130 and

TPS62150

• Available in a 3-mm × 3-mm, VQFN-16 Package

2 Applications

• Standard 12-V Rail Supplies

• POL Supply From Single or Multiple Li-Ion Battery

• Solid-State Disk Drives

• Embedded Systems

• LDO Replacement

• Mobile PCs, Tablet, Modems, Cameras

• Server, Microserver

• Data Terminal, Point of Sales (ePOS)

3 Description

The TPS6214x family is an easy-to-use synchronous

step-down DC-DC converter optimized for

applications with high power density. A high switching

frequency of typically 2.5 MHz allows the use of small

inductors and provides fast transient response by use

of the DCS-Control™ topology.

With their wide operating input voltage range of 3 V

to 17 V, the devices are ideally suited for systems

powered from either a Li-Ion or other batteries, as

well as from 12-V intermediate power rails. It

supports up to 2 A of continuous output current at

output voltages between 0.9 V and 6 V (with 100%

duty-cycle mode). The output voltage start-up ramp is

controlled by the soft-start pin, which allows operation

as either a standalone power supply or in tracking

configurations. Power sequencing is also possible by

configuring the Enable (EN) and open-drain Power

Good (PG) pins.

In Power Save Mode, the devices draw quiescent

current of about 17 μA from VIN. Power Save Mode,

entered automatically and seamlessly if the load is

small, maintains high efficiency over the entire load

range. In Shutdown Mode, the device is turned off

and current consumption is less than 2 μA.

The device, available in adjustable and fixed output

voltage versions, is packaged in a 16-pin VQFN

package measuring 3 mm × 3 mm (RGT).

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)

TPS6214x VQFN (16) 3.00 mm x 3.00 mm

(1) For all available packages, see the orderable addendum at

the end of the datasheet.

Typical Application Schematic Efficiency vs Output Current

TPS62140

TPS62140A

TPS62141

TPS62142

TPS62143

SLVSAJ0E –NOVEMBER 2011–REVISED SEPTEMBER 2016

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Product Folder Links: TPS62140 TPS62140A TPS62141 TPS62142 TPS62143

Table of Contents

1 Features.................................................................. 1

2 Applications ........................................................... 1

3 Description............................................................. 1

4 Revision History..................................................... 2

5 Device Comparison Table..................................... 4

6 Pin Configuration and Functions......................... 4

7 Specifications......................................................... 5

7.1 Absolute Maximum Ratings ...................................... 5

7.2 ESD Ratings.............................................................. 5

7.3 Recommended Operating Conditions....................... 5

7.4 Thermal Information.................................................. 5

7.5 Electrical Characteristics........................................... 6

7.6 Typical Characteristics.............................................. 7

8 Detailed Description.............................................. 8

8.1 Overview................................................................... 8

8.2 Functional Block Diagrams ....................................... 8

8.3 Feature Description................................................... 9

8.4 Device Functional Modes........................................ 11

9 Application and Implementation ........................ 13

9.1 Application Information............................................ 13

9.2 Typical Application.................................................. 13

9.3 System Examples ................................................... 25

10 Power Supply Recommendations ..................... 28

11 Layout................................................................... 29

11.1 Layout Guidelines ................................................. 29

11.2 Layout Example .................................................... 29

11.3 Thermal Considerations........................................ 30

12 Device and Documentation Support................. 31

12.1 Device Support...................................................... 31

12.2 Documentation Support ........................................ 31

12.3 Related Links ........................................................ 31

12.4 Receiving Notification of Documentation Updates 31

12.5 Community Resources.......................................... 32

12.6 Trademarks........................................................... 32

12.7 Electrostatic Discharge Caution............................ 32

12.8 Glossary................................................................ 32

13 Mechanical, Packaging, and Orderable

Information........................................................... 32

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision D (October 2015) to Revision E Page

• Added "Pin to Pin Compatible with TPS62130 and TPS62150" to Features list .................................................................. 1

• Changed the TJMAX value From: 125°C To: 150°C in the Absolute Maximum Rating ....................................................... 5

• Changed the Thermal Information values ............................................................................................................................. 5

• Changed (TJ= –40°C to 85°C) To: (TJ= –40°C to 125°C) in the Electrical Characteristics conditions ............................... 6

• Added a test condition for IQ at TA = -40°C to +85°C in the Electrical Characteristics ........................................................ 6

• Added Table 1 and Table 2 ................................................................................................................................................. 10

• Added indicators (C1, C3, and C5) for capacitances to Figure 7......................................................................................... 13

• Added Switching Frequency graphs for 1.0-V, 1.8-V, and 5.0-V applications ( Figure 24 through Figure 31).................... 20

• Changed Layout Example.................................................................................................................................................... 29

Changes from Revision C (August 2015) to Revision D Page

• Changed VTH_PG Falling (%VOUT) specification MAX value from "93%" to "94%" in the Electrical Characteristics................ 6

Changes from Revision B (June 2013) to Revision C Page

• Added ESD Rating table, Feature Description section, Device Functional Modes,Application and Implementation

section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and

Mechanical, Packaging, and Orderable Information section.................................................................................................. 1

TPS62140

TPS62140A

TPS62141

TPS62142

TPS62143

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SLVSAJ0E –NOVEMBER 2011–REVISED SEPTEMBER 2016

Product Folder Links: TPS62140 TPS62140A TPS62141 TPS62142 TPS62143

Changes from Revision A (October 2012) to Revision B Page

• Added new device version TPS62140A to the data sheet..................................................................................................... 1

• Added text to Power Good section regarding the TPS62140A function.............................................................................. 10

• Added pin option to the footnote for Pin-Selectable Output (DEF) section.......................................................................... 10

• Added text to Frequency Selection (FSW) section regarding pin control............................................................................. 11

• Added text to Tracking Function section for clarification...................................................................................................... 17

• Added application example with regard to new version TPS62140A................................................................................... 25

Changes from Original (November 2011) to Revision A Page

• Changed the description of the AGND pin, and added Note 3.............................................................................................. 4

• Added values to the Initial output voltage accuracy for TA= –10°C to 85°C ......................................................................... 6

• Added text to the Power-Save Mode Operation section following Equation 1..................................................................... 11

• Changed the Layout Considerations section........................................................................................................................ 29

• Changed Layout Example.................................................................................................................................................... 29

Exposed

Thermal Pad

765

16 15 14 13

PVIN

AVIN

SS/TR

PGND

VOS

AGND

FSW

DEF

TPS62140

TPS62140A

TPS62141

TPS62142

TPS62143

SLVSAJ0E –NOVEMBER 2011–REVISED SEPTEMBER 2016

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Product Folder Links: TPS62140 TPS62140A TPS62141 TPS62142 TPS62143

5 Device Comparison Table

PART NUMBER OUTPUT VOLTAGE Power Good Logic Level (EN=Low)

TPS62140 adjustable High Impedance

TPS62140A adjustable Low

TPS62141 1.8 V High Impedance

TPS62142 3.3 V High Impedance

TPS62143 5.0 V High Impedance

(1) For more information about connecting pins, see the Detailed Description and Application and Implementation sections.

(2) Connect FSW to VOUT or PG in this case.

(3) An internal pull-down resistor keeps the logic level low, if pin is floating.

6 Pin Configuration and Functions

RGT Package

16-Pin VQFN

Top View

Pin Functions

PIN(1) I/O DESCRIPTION

NO. NAME

1,2,3 SW O Switch node, which is connected to the internal MOSFET switches. Connect inductor between SW and

output capacitor.

4 PG O Output power good (High = VOUT ready, Low = VOUT below nominal regulation) ; open drain (requires

pull-up resistor)

5 FB I Voltage feedback of adjustable version. Connect resistive voltage divider to this pin. It is recommended

to connect FB to AGND on fixed output voltage versions for improved thermal performance.

6 AGND Analog Ground. Must be connected directly to the Exposed Thermal Pad and common ground plane.

7 FSW I Switching Frequency Select (Low ≈2.5MHz, High ≈1.25MHz(2) for typical operation)(3)

8 DEF I Output Voltage Scaling (Low = nominal, High = nominal + 5%)(3)

9 SS/TR I Soft-Start / Tracking Pin. An external capacitor connected to this pin sets the internal voltage reference

rise time. It can be used for tracking and sequencing.

10 AVIN I Supply voltage for control circuitry. Connect to same source as PVIN.

11,12 PVIN I Supply voltage for power stage. Connect to same source as AVIN.

13 EN I Enable input (High = enabled, Low = disabled)(3)

14 VOS I Output voltage sense pin and connection for the control loop circuitry.

15,16 PGND Power Ground. Must be connected directly to the Exposed Thermal Pad and common ground plane.

Exposed

Thermal Pad Must be connected to AGND (pin 6), PGND (pin 15,16) and common ground plane. See the Layout

Example. Must be soldered to achieve appropriate power dissipation and mechanical reliability.

TPS62140

TPS62140A

TPS62141

TPS62142

TPS62143

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SLVSAJ0E –NOVEMBER 2011–REVISED SEPTEMBER 2016

Product Folder Links: TPS62140 TPS62140A TPS62141 TPS62142 TPS62143

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are with respect to network ground terminal.

7 Specifications

7.1 Absolute Maximum Ratings(1)

over operating junction temperature range (unless otherwise noted) MIN MAX UNIT

Pin voltage (2)

AVIN, PVIN –0.3 20 V

EN, SS/TR –0.3 VIN+0.3

SW –0.3 VIN+0.3 V

DEF, FSW, FB, PG, VOS –0.3 7 V

Power-good sink current PG 10 mA

Temperature Operating junction temperature, TJ–40 150 °C

Storage temperature, Tstg –65 150

(1) ESD testing is performed according to the respective JESD22 JEDEC standard.

(2) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(3) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.2 ESD Ratings VALUE UNIT

V(ESD) Electrostatic discharge(1)

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all

pins(2) ±2000 V

Charged device model (CDM), per JEDEC specification

JESD22-C101, all pins(3) ±500

7.3 Recommended Operating Conditions

over operating junction temperature range (unless otherwise noted) MIN NOM MAX UNIT

Supply voltage, VIN (at AVIN and PVIN) 3 17 V

Operating junction temperature, TJ–40 125 °C

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

7.4 Thermal Information

THERMAL METRIC(1) TPS6214x UNIT

RGT 16 PINS

RθJA Junction-to-ambient thermal resistance 45 °C/W

RθJC(top) Junction-to-case(top) thermal resistance 53.6 °C/W

RθJB Junction-to-board thermal resistance 17.4 °C/W

ψJT Junction-to-top characterization parameter 1.1 °C/W

ψJB Junction-to-board characterization parameter 17.4 °C/W

RθJC(bot) Junction-to-case(bottom) thermal resistance 4.5 °C/W

TPS62140

TPS62140A

TPS62141

TPS62142

TPS62143

SLVSAJ0E –NOVEMBER 2011–REVISED SEPTEMBER 2016

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Product Folder Links: TPS62140 TPS62140A TPS62141 TPS62142 TPS62143

(1) The device is still functional down to undervoltage lockout (see parameter VUVLO).

(2) Current into AVIN + PVIN pins

(3) This is the static current limit. It can be temporarily higher in applications due to internal propagation delay (see Current Limit and Short

Circuit Protection section).

(4) This is the accuracy provided at the FB pin for the adjustable VOUT version (line and load regulation effects are not included). For the

fixed-voltage versions the (internal) resistive divider is included.

(5) Line and load regulation depend on external component selection and layout (see Figure 22 and Figure 23).

7.5 Electrical Characteristics

over operating junction temperature (TJ= –40°C to 125°C), typical values at VIN=12V and TA=25°C (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

SUPPLY

VIN Input voltage range(1) 3 17 V

IQOperating quiescent current EN = High, IOUT = 0 mA,

device not switching 17 30 µA

TA= -40°C to +85°C 17 25

ISD Shutdown current(2) EN = Low 1.5 25 µA

TA= -40°C to +85°C 1.5 4

VUVLO Undervoltage lockout threshold Falling input voltage (PWM mode operation) 2.6 2.7 2.8 V

Hysteresis 200 mV

TSD Thermal shutdown temperature 160 °C

Thermal shutdown hysteresis 20

CONTROL (EN, DEF, FSW, SS/TR, PG)

VHHigh level input threshold voltage (EN, DEF,

FSW) 0.9 0.65 V

VLLow level input threshold voltage (EN, DEF,

FSW) 0.45 0.3 V

ILKG Input leakage current (EN, DEF, FSW) EN = VIN or GND; DEF, FSW = VOUT or GND 0.01 1 µA

VTH_PG Power-good threshold voltage Rising (%VOUT) 92% 95% 98%

Falling (%VOUT) 87% 90% 94%

VOL_PG Power-good output low voltage IPG= –2 mA 0.07 0.3 V

ILKG_PG Input leakage current (PG) VPG = 1.8 V 1 400 nA

ISS/TR SS/TR pin source current 2.3 2.5 2.7 µA

POWER SWITCH

rDS(on)

High-side MOSFET ON-resistance VIN ≥6 V 90 170 mΩ

VIN = 3 V 120

Low-side MOSFET ON-resistance VIN ≥6 V 40 70 mΩ

VIN = 3 V 50

ILIMF High-side MOSFET forward current limit(3) VIN = 12 V, TA= 25°C 2.45 3 3.5 A

OUTPUT

ILKG_FB Input leakage current (FB) TPS62140, VFB = 0.8 V 1 100 nA

VOUT

Output voltage range (TPS62140) VIN ≥VOUT 0.9 6.0 V

DEF (output voltage programming) DEF = 0 (GND) VOUT

DEF = 1 (VOUT) VOUT + 5%

Initial output voltage accuracy(4)

PWM mode operation, VIN ≥VOUT + 1 V 785.6 800 814.

PWM mode operation, VIN ≥VOUT +1 V,

TA= –10°C to 85°C 788.0 800 812.

Power-save mode operation, COUT=22µF 781.6 800 822.

Load regulation(5) VIN = 12 V, VOUT = 3.3 V, PWM mode operation 0.05 %/A

Line regulation(5) 3 V ≤VIN ≤17 V, VOUT = 3.3 V, IOUT = 1 A, PWM

mode operation 0.02 %/V

0.0

20.0

40.0

60.0

80.0

100.0

120.0

140.0

160.0

180.0

200.0

0.0 3.0 6.0 9.0 12.0 15.0 18.0 20.0

−40°C

−10°C

25°C

85°C

125°C

Input Voltage (V)

RDSon High−Side (mΩ)

G001

0.0

20.0

40.0

60.0

80.0

100.0

0.0 3.0 6.0 9.0 12.0 15.0 18.0 20.0

−40°C

−10°C

25°C

85°C

125°C

Input Voltage (V)

RDSon Low−Side (mΩ)

G001

TPS62140

TPS62140A

TPS62141

TPS62142

TPS62143

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SLVSAJ0E –NOVEMBER 2011–REVISED SEPTEMBER 2016

Product Folder Links: TPS62140 TPS62140A TPS62141 TPS62142 TPS62143

7.6 Typical Characteristics

Figure 1. Quiescent Current Figure 2. Shutdown Current

Figure 3. High-Side Switch Resistance Figure 4. Low-Side Switch Resistance

control logic

Soft

start

Thermal

Shtdwn UVLO PG control

power

control

error

amplifier

gate

drive

HS lim

LS lim

PVINPVINAVINPG

PGNDPGND

AGND

comp

timer tON

DCS - ControlTM

direct control

compensation

comparator

ramp

EN*

SS/TR

DEF*

FSW*

VOS

TPS62140

TPS62140A

TPS62141

TPS62142

TPS62143

SLVSAJ0E –NOVEMBER 2011–REVISED SEPTEMBER 2016

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Product Folder Links: TPS62140 TPS62140A TPS62141 TPS62142 TPS62143

8 Detailed Description

8.1 Overview

The TPS6214x synchronous switched-mode power converters are based on DCS-Control™ (Direct Control with

Seamless Transition into Power-Save Mode), an advanced regulation topology, that combines the advantages of

hysteretic, voltage mode and current mode control including an ac loop directly associated with the output

voltage. This control loop takes information about output voltage changes and feeds it directly to a fast

comparator stage. It sets the switching frequency, which is constant for steady-state operating conditions, and

provides immediate response to dynamic load changes. To get accurate DC load regulation, a voltage feedback

loop is used. The internally compensated regulation network achieves fast and stable operation with small

external components and low-ESR capacitors.

The DCS-Control™ topology supports Pulse Width Modulation (PWM) mode for medium and heavy load

conditions and a Power Save Mode at light loads. During PWM, it operates at its nominal switching frequency in

continuous conduction mode. This frequency is typically about 2.5 MHz or 1.25MHz with a controlled frequency

variation depending on the input voltage. If the load current decreases, the converter enters Power Save Mode to

sustain high efficiency down to very light loads. In Power Save Mode, the switching frequency decreases linearly

with the load current. Because DCS-Control™ supports both operation modes within one single building block,

the transition from PWM to Power Save Mode is seamless without effects on the output voltage.

Fixed output-voltage versions provide the smallest solution size and lowest current consumption, requiring only 3

external components. An internal current limit supports nominal output currents of up to 2 A.

The TPS6214x family offers both excellent DC voltage and superior load transient regulation, combined with very

low output voltage ripple, minimizing interference with RF circuits.

8.2 Functional Block Diagrams

* This pin is connected to a pull down resistor internally (see Feature Description section)

Figure 5. TPS62140 and TPS62140A (Adjustable Output Voltage)

control logic

Soft

start

Thermal

Shtdwn UVLO PG control

power

control

error

amplifier

gate

drive

HS lim

LS lim

PVINPVINAVINPG

PGNDPGND

AGND

comp

timer tON

DCS - ControlTM

direct control

compensation

comparator

ramp

EN*

SS/TR

DEF*

FSW*

VOS

FB*

TPS62140

TPS62140A

TPS62141

TPS62142

TPS62143

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SLVSAJ0E –NOVEMBER 2011–REVISED SEPTEMBER 2016

Product Folder Links: TPS62140 TPS62140A TPS62141 TPS62142 TPS62143

Functional Block Diagrams (continued)

* This pin is connected to a pull down resistor internally (see Feature Description section)

Figure 6. TPS62141/2/3 (Fixed Output Voltage)

space

8.3 Feature Description

8.3.1 Enable / Shutdown (EN)

When Enable (EN) is set High, the device starts operation. Shutdown is forced if EN is pulled Low with a

shutdown current of typically 1.5µA. During shutdown, the internal power MOSFETs as well as the entire control

circuitry are turned off. The internal resistive divider pulls down the output voltage smoothly. The EN signal must

be set externally to High or Low. An internal pull-down resistor of about 400kΩis connected and keeps EN logic

low, if Low is set initially and then the pin gets floating. It is disconnected if the pin is set High

Connecting the EN pin to an appropriate output signal of another power rail provides sequencing of multiple

power rails.

8.3.2 Soft-Start / Tracking (SS/TR)

The internal soft-start circuitry controls the output voltage slope during start-up. This avoids excessive inrush

current and ensures a controlled output-voltage rise time. It also prevents unwanted voltage drops from high-

impedance power sources or batteries. When EN is set to start device operation, the device starts switching after

a delay of about 50 µs, and VOUT rises with a slope controlled by an external capacitor connected to the SS/TR

pin. See Figure 40 and Figure 41 for typical start-up operation.

TPS62140

TPS62140A

TPS62141

TPS62142

TPS62143

SLVSAJ0E –NOVEMBER 2011–REVISED SEPTEMBER 2016

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Product Folder Links: TPS62140 TPS62140A TPS62141 TPS62142 TPS62143

Feature Description (continued)

Using a very small capacitor (or leaving SS/TR pin un-connected) provides fastest startup behavior. There is no

theoretical limit for the longest startup time. The TPS6214x can start into a pre-biased output. During monotonic

pre-biased startup, both the power MOSFETs are not allowed to turn on until the devices internal ramp sets an

output voltage above the pre-bias voltage. As long as the output is below about 0.5 V, a reduced current limit of

typically 1.6 A is set internally. If the device is set to shutdown (EN = GND), undervoltage lockout, or thermal

shutdown, an internal resistor pulls the SS/TR pin down to ensure a proper low level. Returning from those states

causes a new start-up sequence as set by the SS/TR connection.

A voltage supplied to SS/TR can be used for tracking a master voltage. The output voltage follows this voltage in

both directions, up and down (see Application and Implementation).

8.3.3 Power Good (PG)

The TPS6214x has a built-in power-good (PG) function to indicate whether the output voltage has reached its

appropriate level or not. The PG signal can be used for start-up sequencing of multiple rails. The PG pin is an

open-drain output that requires a pullup resistor (to any voltage below 7 V). It can sink 2 mA of current and

maintain its specified logic-low level. With TPS62140 it is high-impedance when the device is turned off due to

EN, UVLO, or thermal shutdown. TPS62140A features PG=Low in this case and can be used to actively

discharge Vout (see Figure 47). VIN must remain present for the PG pin to stay Low. See SLVA644 for

application details. If not used, the PG pin should be connected to GND but may be left floating.

space

Table 1. Power Good Pin Logic Table (TPS62140)

Device State PG Logic Status

High Impedance Low

Enable (EN=High) VFB ≥VTH_PG √

VFB ≤VTH_PG √

Shutdown (EN=Low) √

UVLO 0.7 V < VIN < VUVLO √

Thermal Shutdown TJ> TSD √

Power Supply Removal VIN < 0.7 V √

space

Table 2. Power Good Pin Logic Table (TPS62140A)

Device State PG Logic Status

High Impedance Low

Enable (EN=High) VFB ≥VTH_PG √

VFB ≤VTH_PG √

Shutdown (EN=Low) √

UVLO 0.7 V < VIN < VUVLO √

Thermal Shutdown TJ> TSD √

Power Supply Removal VIN < 0.7 V √

(1) Maximum allowed voltage is 7 V. Therefore, it is recommended to connect it to VOUT or PG, not VIN.

space

8.3.4 Pin-Selectable Output Voltage (DEF)

The output voltage of the TPS6214x devices can be increased by 5% above the nominal voltage by setting the

DEF pin to High (1). When DEF is Low, the device regulates to the nominal output voltage. Increasing the nominal

voltage allows adapting the power supply voltage to the variations of the application hardware. More detailed

information on voltage margining using TPS6214x can be found in SLVA489. A pull down resistor of about 400

kΩis internally connected to the pin, to ensure a proper logic level if the pin is high impedance or floating after

initially set to Low. The resistor is disconnected if the pin is set High.

OUT

ON 400×=

TPS62140

TPS62140A

TPS62141

TPS62142

TPS62143

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8.3.5 Frequency Selection (FSW)

To get high power density with very small solution size, a high switching frequency allows the use of small

external components for the output filter. However switching losses increase with the switching frequency. If

efficiency is the key parameter, more than solution size, the switching frequency can be set to half (1.25 MHz

typ.) by pulling FSW to High. It is mandatory to start with FSW=Low to limit inrush current, which can be done by

connecting to VOUT or PG. Running with lower frequency a higher efficiency, but also a higher output voltage

ripple, is achieved. Pull FSW to Low for high frequency operation (2.5 MHz typ.). To get low ripple and full output

current at the lower switching frequency, it's recommended to use an inductor of at least 2.2uH. The switching

frequency can be changed during operation, if needed. A pull down resistor of about 400kOhm is internally

connected to the pin, acting the same way as at the DEF pin (see above).

8.3.6 Undervoltage Lockout (UVLO)

If the input voltage drops, the undervoltage lockout prevents incorrect operation of the device by switching off

both the power FETs. The undervoltage lockout threshold is set typically to 2.7 V. The device is fully operational

for voltages above the UVLO threshold and turns off if the input voltage trips the threshold. The converter starts

operation again once the input voltage exceeds the threshold by a hysteresis of typically 200 mV.

8.3.7 Thermal Shutdown

The junction temperature (TJ) of the device is monitored by an internal temperature sensor. If TJexceeds 160°C

(typ.), the device goes into thermal shutdown. Both the high-side and low-side power FETs are turned off and PG

goes high-impedance. When TJdecreases below the hysteresis amount, the converter resumes normal

operation, beginning with soft start. To avoid unstable conditions, a hysteresis of typically 20°C is implemented

on the thermal shutdown temperature.

8.4 Device Functional Modes

8.4.1 Pulse-Width Modulation (PWM) Operation

The TPS6214x operates with pulse-width modulation in continuous-conduction mode (CCM) with a nominal

switching frequency of 2.5 MHz or 1.25 MHz, selectable with the FSW pin. The frequency variation in PWM is

controlled and depends on VIN, VOUT and the inductance. The device operates in PWM mode as long the output

current is higher than half the inductor ripple current. To maintain high efficiency at light loads, the device enters

power-save mode at the boundary to discontinuous conduction mode (DCM). This happens if the output current

becomes smaller than half the inductor ripple current.

8.4.2 Power Save Mode Operation

The TPS6214x enters its built-in power-save mode seamlessly if the load current decreases. This secures a high

efficiency in light-load operation. The device remains in power-save mode as long as the inductor current is

discontinuous.

In power-save mode, the switching frequency decreases linearly with the load current, maintaining high

efficiency. The transition into and out of power-save mode happens within the entire regulation scheme and is

seamless in both directions.

TPS6214x includes a fixed-on-time circuit. An estimate for this on-time, in steady-state operation with FSW=Low,

is:

space

(1)

space

For very small output voltages, an absolute minimum on-time of about 80 ns is kept to limit switching losses. The

operating frequency is thereby reduced from its nominal value, which keeps efficiency high. Also the off-time can

reach its minimum value at high duty cycles. The output voltage remains regulated in such case. Using tON, the

typical peak inductor current in Power Save Mode can be approximated by:

space

( ) ns

II OUTIN

LIMFtyppeak 30

)( ×

LIMFtyppeak t

II ×+=

)(

( )

L)on(DSOUT(min)OUT(min)IN RRIVV ++=

OUTIN

peakLPSM t

I×

)(

TPS62140

TPS62140A

TPS62141

TPS62142

TPS62143

SLVSAJ0E –NOVEMBER 2011–REVISED SEPTEMBER 2016

www.ti.com

Product Folder Links: TPS62140 TPS62140A TPS62141 TPS62142 TPS62143

Device Functional Modes (continued)

(2)

When VIN decreases to typically 15% above VOUT, the TPS6214x does not enter power-save mode, regardless

of the load current. The device maintains output regulation in PWM mode.

8.4.3 100% Duty-Cycle Operation

The duty cycle of the buck converter is given by D = Vout/Vin and increases as the input voltage comes close to

the output voltage. In this case, the device starts 100% duty-cycle operation, turning on the high-side switch

100% of the time. The high-side switch stays turned on as long as the output voltage is below the internal

setpoint. This allows the conversion of small input-to-output voltage differences, e.g., for longest operation time

of battery-powered applications. In 100% duty-cycle mode, the low-side FET is switched off.

The minimum input voltage to maintain output voltage regulation, depending on the load current and the output

voltage level, is calculated as:

space

where

• IOUT is the output current.

• RDS(on) is the RDS(on) of the high-side FET.

• RLis the DC resistance of the inductor used. (3)

8.4.4 Current Limit and Short Circuit Protection

The TPS6214x devices are protected against heavy load and short-circuit events. If a short circuit is detected

(VOUT drops below 0.5 V), the current limit is reduced to 1.6 A, typically. If the output voltage rises above 0.5 V,

the device runs in normal operation again. At heavy loads, the current limit determines the maximum output

current. If the current limit is reached, the high-side FET is turned off. Avoiding shoot through current, then the

low-side FET switches on to allow the inductor current to decrease. The low-side current limit is typically 2.4A.

The high-side FET turns on again only if the current in the low-side FET has decreased below the low-side

current-limit threshold.

The output current of the device is limited by the current limit (see Electrical Characteristics). Due to internal

propagation delay, the actual current can exceed the static current limit during that time. The dynamic current

limit is calculated as follows:

space

where

• ILIMF is the static current limit, specified in the Electrical Characteristics

• L is the inductor value

• VLis the voltage across the inductor (VIN – VOUT)

• tPD is the internal propagation delay (4)

space

The current limit can exceed static values, especially if the input voltage is high and very small inductances are

used. The dynamic high-side switch peak current is calculated as follows:

space

(5)

22uF

VOUT / 2A

10uF

2.2µH

(3 .. 17)V

3.3nF

TPS62140

PVIN

AVIN

SS/TR

DEF

FSW

VOS

AGND

PGND

100k

TPS62140

TPS62140A

TPS62141

TPS62142

TPS62143

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SLVSAJ0E –NOVEMBER 2011–REVISED SEPTEMBER 2016

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(1) See Third-Party Products Disclaimer

9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

The TPS62140 is a switched mode step-down converter, able to convert a 3 V to 17 V input voltage into a 0.9 V

to 6 V output voltage, providing up to 2 A. It needs a minimum amount of external components. Apart from the

LC output filter and the input capacitor, only the TPS62140 (TPS62140A) with an adjustable output voltage

needs an additional resistive divider to set the output voltage level.

9.2 Typical Application

space

Figure 7. 3.3V/2A Step-Down Converter

9.2.1 Design Requirements

The following design guideline provides a component selection to operate the device within the recommended

operating conditions. Using the FSW pin, the design can be optimized for highest efficiency or smallest solution

size and lowest output voltage ripple. For highest efficiency set FSW = High and the device operates at the lower

switching frequency. For smallest solution size and lowest output voltage ripple set FSW = Low and the device

operates with higher switching frequency. The typical values for all measurements are VIN = 12 V, VOUT = 3.3 V

and T = 25°C, using the external components of Table 3.

9.2.2 Detailed Design Procedure

The component selection used for measurements is given as follows:

Table 3. List of Components(1)

REFERENCE DESCRIPTION MANUFACTURER

IC 17-V, 2-A step-down converter, QFN TPS62140RGT, Texas Instruments

L1 2.2-µH, 3.1-A, 0.165 in × 0.165 in XFL4020-222MEB, Coilcraft

C1 10-µF, 25-V, ceramic, 1210 Standard

C3 22-µF, 6.3-V, ceramic, 0805 Standard

C5 3300-pF, 25-V, ceramic, 0603

R1 Dependent on Vout

R2 Dependent on Vout

R3 100-kΩ, chip, 0603, 1/16W, 1% Standard

(max)

(max)(max)

OUTL

æ-= 1

0.8V

RR OUT

TPS62140

TPS62140A

TPS62141

TPS62142

TPS62143

SLVSAJ0E –NOVEMBER 2011–REVISED SEPTEMBER 2016

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Product Folder Links: TPS62140 TPS62140A TPS62141 TPS62142 TPS62143

(1) The values in the table are nominal values. The effective capacitance was considered to vary by +20% and -50%.

(2) This LC combination is the standard value and recommended for most applications.

9.2.2.1 Programming the Output Voltage

While the output voltage of the TPS62140 (TPS62140A) is adjustable, the TPS62141/2/3 are programmed to

fixed output voltages. For fixed output versions, the FB pin is pulled down internally and may be left floating. It is

recommended to connect to AGND to improve thermal resistance. The adjustable version can be programmed

for output voltages from 0.9 V to 6 V by using a resistive divider from VOUT to AGND. The voltage at the FB pin

is regulated to 800 mV. The value of the output voltage is set by the selection of the resistive divider from

Equation 6. It is recommended to choose resistor values which allow a current of at least 2 µA, meaning the

value of R2 should not exceed 400 kΩ. Lower resistor values are recommended for highest accuracy and most-

robust design. For applications requiring lowest current consumption, the use of fixed output-voltage versions is

recommended.

spacing

(6)

spacing

In case the FB pin is opened, the device clamps the output voltage at the VOS pin internally to about 7.4 V.

9.2.2.2 External Component Selection

The external components have to fulfill the needs of the application, but also the stability criteria of the devices

control loop. The TPS6214X is optimized to work within a range of external components. The LC output filter's

inductance and capacitance have to be considered in conjunction, creating a double pole, responsible for the

corner frequency of the converter (see Output Filter and Loop Stability section). Table 4 can be used to simplify

the output filter component selection. Checked cells represent combinations that are proven for stability by

simulation and lab test. Further combinations should be checked for each individual application. See SLVA463

for details.

Table 4. Recommended LC Output Filter Combinations(1)

4.7 µF 10 µF 22 µF 47 µF 100 µF 200 µF 400 µF

0.47 µH

1 µH √√√√

2.2 µH √ √(2) √√√

3.3 µH √√√√

4.7 µH

spacing

TPS6214X can be run with an inductor as low as 1 µH or 2.2 µH. FSW should be set Low in this case. However,

for applications running with the low-frequency setting (FSW = High) or with low input voltages, 3.3 µH is

recommended.

9.2.2.2.1 Inductor Selection

The inductor selection is affected by several effects like inductor ripple current, output ripple voltage, PWM-to-

PSM transition point, and efficiency. In addition, the inductor selected must be rated for appropriate saturation

current and DC resistance (DCR). Equation 7 and Equation 8 calculate the maximum inductor current under

static load conditions.

spacing

(7)

spacing

LPSMload II D=

)(

×=D

OUT

OUTL fL

(min)

(max)

TPS62140

TPS62140A

TPS62141

TPS62142

TPS62143

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(1) Lower of IRMS at 40°C rise or ISAT at 30% drop.

(2) See Third-Party Products Disclaimer

where

• IL(max) is the maximum inductor current

•ΔILis the peak-to-peak inductor ripple current

• L(min) is the minimum effective inductor value

• fSW is the actual PWM switching frequency (8)

spacing

Calculating the maximum inductor current using the actual operating conditions gives the minimum required

inductor saturation current. It is recommended to add a margin of about 20%. A larger inductor value is also

useful to get lower ripple current, but increases the transient response time and size as well. The following

inductors have been used with the TPS6214x and are recommended for use:

Table 5. List of Inductors

TYPE INDUCTANCE (µH) CURRENT (A)(1) DIMENSIONS [L x B x

H] (mm) MANUFACTURER(2)

XFL4020-222ME_ 2.2 µH, ±20% 3.5 4 x 4 x 2.1 Coilcraft

XFL4020-332ME_ 3.3 µH, ±20% 2.9 4 x 4 x 2.1 Coilcraft

IHLP1212BZ-11 2.2 µH, ±20% 3.0 3 x 3.6 x 2 Vishay

IHLP1616AB-11 2.2 µH, ±20% 2.75 4.05 x 4.45 x 1.2 Vishay

DEM4518C 1235AS-H-3R3M 3.3 µH, ±20% 2.5 4.5 x 4.7 x 1.9 Toko

spacing

The inductor value also determines the load current at which the power-save mode is entered:

spacing

(9)

spacing

Using Equation 8, this current level can be adjusted by changing the inductor value.

9.2.2.2.2 Capacitor Selection

9.2.2.2.2.1 Output Capacitor

The recommended value for the output capacitor is 22 µF. The architecture of the TPS6214X allows the use of

tiny ceramic output capacitors with low equivalent series resistance (ESR). These capacitors provide low output-

voltage ripple and are recommended. To keep its low resistance up to high frequencies and to get narrow

capacitance variation with temperature, it is recommended to use X7R or X5R dielectric. Using a higher value

can have some advantages, like smaller voltage ripple and a tighter DC output accuracy in power-save mode

(see SLVA463).

Note: In power-save mode, the output voltage ripple depends on the output capacitance, its ESR and the peak

inductor current. Using ceramic capacitors provides small ESR and low ripple.

VFB [V]

VSS/

TR [V]

0.2 0.4 0.6 0.8

0.4

1.2

0.8

TRSSFB VV /

64.0 ×»

[ ]

tC SSSS 251

×=

TPS62140

TPS62140A

TPS62141

TPS62142

TPS62143

SLVSAJ0E –NOVEMBER 2011–REVISED SEPTEMBER 2016

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Product Folder Links: TPS62140 TPS62140A TPS62141 TPS62142 TPS62143

9.2.2.2.2.2 Input Capacitor

For most applications, 10 µF is sufficient and is recommended, though a larger value reduces input-current ripple

further. The input capacitor buffers the input voltage for transient events and also decouples the converter from

the supply. A low-ESR multilayer ceramic capacitor is recommended for best filtering and should be placed

between PVIN and PGND as close as possible to those pins. Even though AVIN and PVIN must be supplied

from the same input source, it is recommended to place a capacitance of 0.1 uF from AVIN to AGND, to avoid

potential noise coupling.

9.2.2.2.2.3 Soft-Start Capacitor

A capacitance connected between the SS/TR pin and AGND allows a user-programmable start-up slope of the

output voltage. A constant-current source provides 2.5 µA to charge the external capacitance. The capacitor

required for a given soft-start ramp time for the output voltage is given by:

spacing

where

• CSS is the capacitance (F) required at the SS/TR pin

• tSS is the desired soft-start ramp time (s). (10)

spacing

NOTE

DC bias effect: High-capacitance ceramic capacitors have a DC bias effect, which has a

strong influence on the final effective capacitance. Therefore, the right capacitor value

must be chosen carefully. Package size and voltage rating in combination with dielectric

material are responsible for differences between the rated capacitor value and the

effective capacitance.

spacing

9.2.2.3 Tracking Function

If a tracking function is desired, the SS/TR pin can be used for this purpose by connecting it to an external

tracking voltage. The output voltage tracks that voltage. If the tracking voltage is between 50 mV and 1.2 V, the

FB pin tracks the SS/TR pin voltage as described in Equation 11 and shown in Figure 8.

spacing

(11)

spacing

Figure 8. Voltage Tracking Relationship

TPS62140

PVIN

AVIN

SS/TR

DEF

FSW

VOS

AGND

PGND

TPS62140

PVIN

AVIN

SS/TR

DEF

FSW

VOS

AGND

PGND

VOUT1

VOUT2

TPS62140

TPS62140A

TPS62141

TPS62142

TPS62143

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Once the SS/TR pin voltage reaches about 1.2V, the internal voltage is clamped to the internal feedback voltage

and device goes to normal regulation. This works for rising and falling tracking voltages with the same behavior,

as long as the input voltage is inside the recommended operating conditions. For decreasing SS/TR pin voltage,

the device doesn't sink current from the output. So, the resulting decrease of the output voltage may be slower

than the SS/TR pin voltage if the load is light. When driving the SS/TR pin with an external voltage, do not

exceed the voltage rating of the SS/TR pin which is VIN+0.3V.

If the input voltage drops into undervoltage lockout or even down to zero, the output voltage goes to zero,

independent of the tracking voltage. Figure 9 shows how to connect devices to get ratiometric and simultaneous

sequencing by using the tracking function.

spacing

Figure 9. Sequence for Ratiometric and Simultaneous Startup

spacing

The resistive divider of R1 and R2 can be used to change the ramp rate of VOUT2 faster, slower, or the same as

VOUT1.

A sequential start-up is achieved by connecting the PG pin of VOUT1 to the EN pin of VOUT2. A ratiometric

start-up sequence happens if both supplies are sharing the same soft-start capacitor. Equation 10 calculates the

soft-start time, though the SS/TR current must be doubled. Details about these and other tracking and

sequencing circuits are found in SLVA470.

Note: If the voltage at the FB pin is below its typical value of 0.8 V, the output voltage accuracy may have a

wider tolerance than specified.

æ+×

252

RRpF

fpole p

pFR

fzero 252

1××

fLC

TPS62140

TPS62140A

TPS62141

TPS62142

TPS62143

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9.2.2.4 Output Filter and Loop Stability

The devices of the TPS6214x family are internally compensated to be stable with L-C filter combinations

corresponding to a corner frequency to be calculated with Equation 12:

spacing

(12)

spacing

Proven nominal values for inductance and ceramic capacitance are given in Table 4 and are recommended for

use. Different values may work, but care must be taken on the loop stability, which is affected. More information

including a detailed L-C stability matrix can be found in SLVA463.

The TPS6214x devices, both fixed and adjustable versions, include an internal 25 pF feed-forward capacitor,

connected between the VOS and FB pins. This capacitor impacts the frequency behavior and sets a pole and

zero in the control loop with the resistors of the feedback divider, per equations Equation 13 and Equation 14:

spacing

(13)

spacing

(14)

spacing

Though the TPS6214x devices are stable without the pole and zero being in a particular location, adjusting their

location to the specific needs of the application can provide better performance in power-save mode and/or

improved transient response. An external feed-forward capacitor can also be added. A more detailed discussion

on the optimization for stability vs transient response can be found in SLVA289 and SLVA466.

0.0

10.0

20.0

30.0

40.0

50.0

60.0

70.0

80.0

90.0

100.0

0.0001 0.001 0.01 0.1 1 10

VIN=5V

VIN=12V VIN=17V

Output Current (A)

Efficiency (%)

VOUT=3.3V

L=2.2uH (XFL4020)

Cout=22uF

G001

0.0

10.0

20.0

30.0

40.0

50.0

60.0

70.0

80.0

90.0

100.0

4 5 6 7 8 9 10 11 12 13 14 15 16 17

IOUT=1mAIOUT=10mAIOUT=100mAIOUT=1A

Input Voltage (V)

Efficiency (%)

VOUT=3.3V

L=2.2uH (XFL4020)

Cout=22uF

G001

0.0

10.0

20.0

30.0

40.0

50.0

60.0

70.0

80.0

90.0

100.0

0.0001 0.001 0.01 0.1 1 10

VIN=12V

VIN=17V

Output Current (A)

Efficiency (%)

VOUT=5.0V

L=2.2uH (XFL4020)

Cout=22uF

G001

0.0

10.0

20.0

30.0

40.0

50.0

60.0

70.0

80.0

90.0

100.0

7 8 9 10 11 12 13 14 15 16 17

IOUT=1mA

IOUT=10mA

IOUT=100mA

IOUT=1A

Input Voltage (V)

Efficiency (%)

VOUT=5.0V

L=2.2uH (XFL4020)

Cout=22uF

G001

0.0

10.0

20.0

30.0

40.0

50.0

60.0

70.0

80.0

90.0

100.0

0.0001 0.001 0.01 0.1 1 10

VIN=12V VIN=17V

Output Current (A)

Efficiency (%)

VOUT=5.0V

L=2.2uH (XFL4020)

Cout=22uF

G001

0.0

10.0

20.0

30.0

40.0

50.0

60.0

70.0

80.0

90.0

100.0

7 8 9 10 11 12 13 14 15 16 17

IOUT=1mA

IOUT=10mA

IOUT=100mA

IOUT=1A

Input Voltage (V)

Efficiency (%)

VOUT=5.0V

L=2.2uH (XFL4020)

Cout=22uF

G001

TPS62140

TPS62140A

TPS62141

TPS62142

TPS62143

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9.2.3 Application Curves

VIN = 12 V, VOUT = 3.3 V, TA= 25°C, (unless otherwise noted)

VOUT = 5 V

Figure 10. Efficiency With 1.25 MHz

VOUT = 5 V

Figure 11. Efficiency With 1.25 MHz

VOUT = 5 V

Figure 12. Efficiency With 2.5 MHz

VOUT = 5 V

Figure 13. Efficiency With 2.5 MHz

VOUT = 3.3 V

Figure 14. Efficiency With 1.25 MHz

VOUT = 3.3 V

Figure 15. Efficiency With 1.25 MHz

0.0

10.0

20.0

30.0

40.0

50.0

60.0

70.0

80.0

90.0

100.0

0.0001 0.001 0.01 0.1 1 10

VIN=5V

VIN=12V VIN=17V

Output Current (A)

Efficiency (%)

VOUT=0.9V

L=2.2uH (XFL4020)

Cout=22uF

G001

0.0

10.0

20.0

30.0

40.0

50.0

60.0

70.0

80.0

90.0

100.0

3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

IOUT=1mA

IOUT=10mA

IOUT=100mA

IOUT=1A

Input Voltage (V)

Efficiency (%)

VOUT=0.9V

L=2.2uH (XFL4020)

Cout=22uF

G001

0.0

10.0

20.0

30.0

40.0

50.0

60.0

70.0

80.0

90.0

100.0

0.0001 0.001 0.01 0.1 1 10

VIN=5V

VIN=12V VIN=17V

Output Current (A)

Efficiency (%)

VOUT=1.8V

L=2.2uH (XFL4020)

Cout=22uF

G001

0.0

10.0

20.0

30.0

40.0

50.0

60.0

70.0

80.0

90.0

100.0

3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

IOUT=1mA

IOUT=10mA

IOUT=100mA

IOUT=1A

Input Voltage (V)

Efficiency (%)

VOUT=1.8V

L=2.2uH (XFL4020)

Cout=22uF

G001

0.0

10.0

20.0

30.0

40.0

50.0

60.0

70.0

80.0

90.0

100.0

0.0001 0.001 0.01 0.1 1 10

VIN=5V

VIN=12V VIN=17V

Output Current (A)

Efficiency (%)

VOUT=3.3V

L=2.2uH (XFL4020)

Cout=22uF

G001

0.0

10.0

20.0

30.0

40.0

50.0

60.0

70.0

80.0

90.0

100.0

4 5 6 7 8 9 10 11 12 13 14 15 16 17

IOUT=1mA

IOUT=10mA

IOUT=100mA

IOUT=1A

Input Voltage (V)

Efficiency (%)

VOUT=3.3V

L=2.2uH (XFL4020)

Cout=22uF

G001

TPS62140

TPS62140A

TPS62141

TPS62142

TPS62143

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VOUT = 3.3 V

Figure 16. Efficiency With 2.5 MHz,

VOUT = 3.3 V

Figure 17. Efficiency With 2.5 MHz

VOUT = 1.8 V

Figure 18. Efficiency With 1.25 MHz

VOUT = 1.8 V

Figure 19. Efficiency With 1.25 MHz

VOUT = 0.9 V

Figure 20. Efficiency With 1.25 MHz

VOUT = 0.9 V

Figure 21. Efficiency With 1.25 MHz

0.5

1.5

2.5

3.5

4 6 8 10 12 14 16 18

IOUT=0.5A IOUT=1A

IOUT=2A

Input Voltage (V)

Switching Frequency (MHz)

G000

0.5

1.5

2.5

3.5

0 0.5 1 1.5 2

Output Current (A)

Switching Frequency (MHz)

G000

0.5

1.5

2.5

3.5

6 8 10 12 14 16 18

IOUT=0.5A IOUT=1A

IOUT=2A

Input Voltage (V)

Switching Frequency (MHz)

G000

0.5

1.5

2.5

3.5

0 0.5 1 1.5 2

Output Current (A)

Switching Frequency (MHz)

G000

3.20

3.25

3.30

3.35

3.40

0.0001 0.001 0.01 0.1 1 10

VIN=5V

VIN=12V

VIN=17V

Output Current (A)

Output Voltage (V)

VOUT=3.3V

L=2.2uH (XFL4020)

Cout=22uF

G001

3.20

3.25

3.30

3.35

3.40

4 7 10 13 16

IOUT=1mA IOUT=10mA

IOUT=100mAIOUT=1A

Input Voltage (V)

Output Voltage (V)

VOUT=3.3V

L=2.2uH (XFL4020)

Cout=22uF

G001

TPS62140

TPS62140A

TPS62141

TPS62142

TPS62143

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Figure 22. Output Voltage Accuracy (Load Regulation) Figure 23. Output Voltage Accuracy (Line Regulation)

FSW = Low VOUT = 5 V

Figure 24. Switching Frequency vs Input Voltage

FSW = Low VOUT = 5 V

Figure 25. Switching Frequency vs Output Current

FSW = Low VOUT = 3.3 V

Figure 26. Switching Frequency vs Input Voltage

FSW = Low VOUT = 3.3 V

Figure 27. Switching Frequency vs Output Current

0.01

0.02

0.03

0.04

0.05

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

VIN=5V

VIN=12V

VIN=17V

Output Current (A)

Output Voltage Ripple (V)

VOUT=3.3V,

L=2.2uH (XFL4020)

Cout=22uF

G000

0.5

1.5

2.5

3.5

4 5 6 7 8 9 10 11 12 13 14 15 16 17

−40°C 25°C

85°C

Input Voltage (V)

Output Current (A)

VOUT=3.3V

L=2.2uH (XFL4020)

Cout=22uF

G000

0.5

1.5

2.5

3 5 7 9 11 13 15 17

IOUT=1A

IOUT=2A

IOUT=0.5A

Input Voltage (V)

Switching Frequency (MHz)

G000

0.5

1.5

2.5

0 0.5 1 1.5 2

Output Current (A)

Switching Frequency (MHz)

G000

0.5

1.5

2.5

3.5

3 5 7 9 11 13 15 17

IOUT=0.5A IOUT=1A

IOUT=2A

Input Voltage (V)

Switching Frequency (MHz)

G000

0.5

1.5

2.5

3.5

0 0.5 1 1.5 2

Output Current (A)

Switching Frequency (MHz)

G000

TPS62140

TPS62140A

TPS62141

TPS62142

TPS62143

SLVSAJ0E –NOVEMBER 2011–REVISED SEPTEMBER 2016

www.ti.com

Product Folder Links: TPS62140 TPS62140A TPS62141 TPS62142 TPS62143

FSW = Low VOUT = 1.8 V

Figure 28. Switching Frequency vs Input Voltage

FSW = Low VOUT = 1.8 V

Figure 29. Switching Frequency vs Output Current

FSW = Low VOUT = 1 V

Figure 30. Switching Frequency vs Input Voltage

FSW = Low VOUT = 1 V

Figure 31. Switching Frequency vs Output Current

Figure 32. Output Voltage Ripple Figure 33. Maximum Output Current

100

10 100 1k 10k 100k 1M

VIN=5V

VIN=12V

VIN=17V

Frequency (Hz)

PSRR (dB)

VOUT=3.3V, IOUT=1A

L=2.2uH (XFL4020)

Cin=10uF, Cout=22uF

G000

100

10 100 1k 10k 100k 1M

VIN=5V

VIN=12V

VIN=17V

Frequency (Hz)

PSRR (dB)

VOUT=3.3V, IOUT=0.1A

L=2.2uH (XFL4020)

Cin=10uF, Cout=22uF

G000

TPS62140

TPS62140A

TPS62141

TPS62142

TPS62143

www.ti.com

SLVSAJ0E –NOVEMBER 2011–REVISED SEPTEMBER 2016

Product Folder Links: TPS62140 TPS62140A TPS62141 TPS62142 TPS62143

IOUT = 1A fSW = 2.5 MHz

Figure 34. Power-Supply Rejection Ratio

IOUT = 0.1A fSW = 2.5 MHz

Figure 35. Power-Supply Rejection Ratio

VIN = 12 V VOUT = 3.3 V With 50 mV/div

Figure 36. PWM-PSM-Transition

IOUT= 0.5 to 2 to

0.5 A VIN = 12 V VOUT = 3.3 V

Figure 37. Load Transient Response

Figure 38. Line Transient Response of Figure 37, Rising

Edge Figure 39. Line Transient Response of Figure 37, Falling

Edge

105

115

125

0 0.5 1 1.5 2 2.5

Output Current (A)

Free−Air Temperature (°C)

TPS62140 EVM

L=2.2uH (XFL4020)

VIN=12V, VOUT=3.3V

G000

105

115

125

0 2 4 6 8 10 12

Output Power (W)

Free−Air Temperature (°C)

TPS62140 EVM

L=2.2uH (XFL4020)

VIN=12V, VOUT=3.3V

G000

TPS62140

TPS62140A

TPS62141

TPS62142

TPS62143

SLVSAJ0E –NOVEMBER 2011–REVISED SEPTEMBER 2016

www.ti.com

Product Folder Links: TPS62140 TPS62140A TPS62141 TPS62142 TPS62143

VIN = 12 V VOUT = 3.3 V

Figure 40. Start-Up Into 100 mA

VIN = 12 V VOUT = 3.3 V

Figure 41. Start-Up into 2 A

IOUT = 1 A

Figure 42. Typical Operation in PWM Mode

IOUT = 10 A

Figure 43. Typical Operation in Power-Save Mode

fSW = 2.5 MHz

Figure 44. Maximum Ambient Temperature

fSW = 2.5 MHz

Figure 45. Maximum Ambient Temperature

22uF

Vout / 2A

10uF

1 / 2.2 µH

(3 .. 17)V

3.3nF

PVIN

AVIN

SS/TR

DEF

FSW

VOS

AGND

PGND

TPS62140A

TRSSFB RAV /

.. ××= m52640

22uF

10uF

2.2 µH(4 .. 17) V

0.15R187k

ADIM

PVIN

AVIN

SS/TR

DEF

FSW

VOS

AGND

PGND

TPS62140

TPS62140A

TPS62141

TPS62142

TPS62143

www.ti.com

SLVSAJ0E –NOVEMBER 2011–REVISED SEPTEMBER 2016

Product Folder Links: TPS62140 TPS62140A TPS62141 TPS62142 TPS62143

9.3 System Examples

9.3.1 LED Power Supply

The TPS62140 can be used as a power supply for power LEDs. The FB pin can be easily set down to lower

values than nominal by using the SS/TR pin. With that, the voltage drop on the sense resistor is low to avoid

excessive power loss. Because this pin provides 2.5 µA, the feedback pin voltage can be adjusted by an external

resistor per Equation 15. This drop, proportional to the LED current, is used to regulate the output voltage (anode

voltage) to a proper level to drive the LED. Both analog and PWM dimming are supported with the TPS62140.

Figure 46 shows an application circuit, tested with analog dimming:

spacing

Figure 46. Single Power LED Supply

The resistor at SS/TR sets the FB voltage to a level of about 300 mV and is calculated from Equation 15.

spacing

(15)

spacing

The device now supplies a constant current, set by the resistor at the FB pin, by regulating the output voltage

accordingly. The minimum input voltage must be rated according to the forward voltage needed by the LED

used. More information is available in the application note SLVA451.

9.3.2 Active Output Discharge

The TPS62140A pulls the PG pin Low, when the device is shut down by EN, UVLO or thermal shutdown.

Connecting PG to Vout through a resistor can be used to discharge Vout in those cases (see Figure 47). The

discharge rate can be adjusted by R3, which is also used to pull up the PG pin in normal operation. For reliability,

keep the maximum current into the PG pin less than 10mA.

Figure 47. Discharge Vout through PG Pin With TPS62140A

22uF

5V / 2A

10uF

2.2 µH

(5 .. 17)V

3.3nF

TPS62143

PVIN

AVIN

SS/TR

DEF

FSW

VOS

AGND

PGND

100k

TPS62140

PVIN

AVIN

SS/TR

DEF

FSW

VOS

AGND

PGND

2.2µH

(3 .. 13.7)V

10uF

383k

1.21M

22uF

-3.3V

10uF

3.3nF

maxINOUTIN VVV £+

TPS62140

TPS62140A

TPS62141

TPS62142

TPS62143

SLVSAJ0E –NOVEMBER 2011–REVISED SEPTEMBER 2016

www.ti.com

Product Folder Links: TPS62140 TPS62140A TPS62141 TPS62142 TPS62143

System Examples (continued)

9.3.3 Inverting Power Supply

The TPS6214x can be used as inverting power supply by rearranging external circuitry as shown in Figure 48.

As the former GND node now represents a voltage level below system ground, the voltage difference between

VIN and VOUT has to be limited for operation to the maximum supply voltage of 17V (see Equation 16).

spacing

(16)

spacing

Figure 48. –3.3V Inverting Power Supply

spacing

The transfer function of the inverting power supply configuration differs from the buck mode transfer function,

incorporating a Right Half Plane Zero additionally. The loop stability has to be adapted and an output

capacitance of at least 22µF is recommended. A detailed design example is given in SLVA469.

spacing

9.3.4 Various Output Voltages

The following example circuits show how to use the various devices and configure the external circuitry to furnish

different output voltages at 2A.

spacing

Figure 49. 5-V/2-A Power Supply

spacing

22uF

1.8V / 2A

10uF

2.2 µH

(3 .. 17)V

3.3nF

TPS62141

PVIN

AVIN

SS/TR

DEF

FSW

VOS

AGND

PGND

100k

22uF

2.5V / 2A

10uF

2.2 µH

(3 .. 17)V

3.3nF

TPS62140

390k

180k

PVIN

AVIN

SS/TR

DEF

FSW

VOS

AGND

PGND

100k

22uF

3.3V / 2A

10uF

2.2 µH

(3.3 .. 17)V

3.3nF

TPS62142

PVIN

AVIN

SS/TR

DEF

FSW

VOS

AGND

PGND

100k

TPS62140

TPS62140A

TPS62141

TPS62142

TPS62143

www.ti.com

SLVSAJ0E –NOVEMBER 2011–REVISED SEPTEMBER 2016

Product Folder Links: TPS62140 TPS62140A TPS62141 TPS62142 TPS62143

System Examples (continued)

spacing

Figure 50. 3.3-V/2-A Power Supply

spacing

Figure 51. 2.5-V/2-A Power Supply

spacing

Figure 52. 1.8-V/2-A Power Supply

spacing

22uF

1V / 2A

10uF

2.2 µH

3.3nF

TPS62140

51k

200k

PVIN

AVIN

SS/TR

DEF

FSW

VOS

AGND

PGND

100k

22uF

1.2V / 2A

10uF

2.2 µH

(3 .. 17)V

3.3nF

TPS62140

75k

150k

PVIN

AVIN

SS/TR

DEF

FSW

VOS

AGND

PGND

100k

22uF

1.5V / 2A

10uF

2.2 µH

(3 .. 17)V

3.3nF

TPS62140

130k

150k

PVIN

AVIN

SS/TR

DEF

FSW

VOS

AGND

PGND

100k

TPS62140

TPS62140A

TPS62141

TPS62142

TPS62143

SLVSAJ0E –NOVEMBER 2011–REVISED SEPTEMBER 2016

www.ti.com

Product Folder Links: TPS62140 TPS62140A TPS62141 TPS62142 TPS62143

System Examples (continued)

Figure 53. 1.5-V/2-A Power Supply

spacing

Figure 54. 1.2-V/2-A Power Supply

spacing

Figure 55. 1-V/2-A Power Supply

10 Power Supply Recommendations

The TPS6214X are designed to operate from a 3-V to 17-V input voltage supply. The input power supply's output

current needs to be rated according to the output voltage and the output current of the power rail application.

VIN

GND

AGND

VOUT

AVIN

PVIN

PGND

PGND AGND

VOS

SS/TR

FSW

DEF

C1 C3

TPS62140

TPS62140A

TPS62141

TPS62142

TPS62143

www.ti.com

SLVSAJ0E –NOVEMBER 2011–REVISED SEPTEMBER 2016

Product Folder Links: TPS62140 TPS62140A TPS62141 TPS62142 TPS62143

11 Layout

11.1 Layout Guidelines

A proper layout is critical for the operation of a switched-mode power supply, even more at high switching

frequencies. Therefore, the PCB layout of the TPS6214x demands careful attention to ensure operation and to

get the performance specified. A poor layout can lead to issues like poor regulation (both line and load), stability

and accuracy weaknesses, increased EMI radiation, and noise sensitivity.

See Figure 56 for the recommended layout of the TPS6214x, which is designed for common external ground

connections. Therefore both AGND and PGND pins are directly connected to the Exposed Thermal Pad. On the

PCB, the direct common ground connection of AGND and PGND to the Exposed Thermal Pad and the system

ground (ground plane) is mandatory. Also connect the VOS pin in the shortest way to VOUT at the output

capacitor. To avoid noise coupling into the VOS line, this connection should be separated from the VOUT power

line/plane as shown in Layout Example.

Provide low inductive and resistive paths for loops with high di/dt. Therefore, paths conducting the switched load

current should be as short and wide as possible. Provide low capacitive paths (with respect to all other nodes) for

wires with high dv/dt. Therefore, the input and output capacitance should be placed as close as possible to the

IC pins and parallel wiring over long distances as well as narrow traces should be avoided. Loops which conduct

an alternating current should outline an area as small as possible, as this area is proportional to the energy

radiated.

Sensitive nodes like FB and VOS need to be connected with short wires and not nearby high dv/dt signals (that

is, SW). As they carry information about the output voltage, they should be connected as close as possible to the

actual output voltage (at the output capacitor). The capacitor on the SS/TR pin and on AVIN as well as the FB

resistors, R1 and R2, should be kept close to the IC and connect directly to those pins and the system ground

plane.

The Exposed Thermal Pad must be soldered to the circuit board for mechanical reliability and to achieve

appropriate power dissipation.

The recommended layout is implemented on the EVM and shown in its Users Guide, SLVU437. Additionally, the

EVM Gerber data are available for download here, SLVC394.

11.2 Layout Example

space

Figure 56. Layout Recommendation

TPS62140

TPS62140A

TPS62141

TPS62142

TPS62143

SLVSAJ0E –NOVEMBER 2011–REVISED SEPTEMBER 2016

www.ti.com

Product Folder Links: TPS62140 TPS62140A TPS62141 TPS62142 TPS62143

11.3 Thermal Considerations

Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires

special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added

heat sinks and convection surfaces, and the presence of other heat-generating components affect the power-

dissipation limits of a given component.

Three basic approaches for enhancing thermal performance are listed below:

• Improving the power dissipation capability of the PCB design

• Improving the thermal coupling of the component to the PCB by soldering the exposed thermal pad

• Introducing airflow in the system

For more details on how to use the thermal parameters, see the application notes: Thermal Characteristics

Application Note (SZZA017), and (SPRA953).

The TPS6214X is designed for a maximum operating junction temperature (TJ) of 125°C. Therefore, the

maximum output power is limited by the power losses that can be dissipated over the actual thermal resistance,

given by the package and the surrounding PCB structures. Since the thermal resistance of the package is fixed,

increasing the size of the surrounding copper area and improving the thermal connection to the IC can reduce

the thermal resistance. To get improved thermal behavior, it is recommended to use top layer metal to connect

the device with wide and thick metal lines. Internal ground layers can connect to vias directly under the IC for

improved thermal performance.

If short-circuit or overload conditions are present, the device is protected by limiting internal power dissipation.

Experimental data, taken from the TPS62140 EVM, shows the maximum ambient temperature (without additional

cooling like airflow or heat sink), that can be allowed to limit the junction temperature to at most 125°C (see

Figure 44).

TPS62140

TPS62140A

TPS62141

TPS62142

TPS62143

www.ti.com

SLVSAJ0E –NOVEMBER 2011–REVISED SEPTEMBER 2016

Product Folder Links: TPS62140 TPS62140A TPS62141 TPS62142 TPS62143

12 Device and Documentation Support

12.1 Device Support

12.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT

CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES

OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER

ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

12.2 Documentation Support

12.2.1 Related Documentation

For related documentation see the following:

• Users Guide, SLVU437

• EVM Gerber Data, SLVC394

• Thermal Characteristics Application Note, SZZA017 and SPRA953

12.3 Related Links

The table below lists quick access links. Categories include technical documents, support and community

resources, tools and software, and quick access to sample or buy.

Table 6. Related Links

PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL

DOCUMENTS TOOLS &

SOFTWARE SUPPORT &

COMMUNITY

TPS62140 Click here Click here Click here Click here Click here

TPS62140A Click here Click here Click here Click here Click here

TPS62141 Click here Click here Click here Click here Click here

TPS62142 Click here Click here Click here Click here Click here

TPS62143 Click here Click here Click here Click here Click here

12.4 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper

right corner, click on Alert me to register and receive a weekly digest of any product information that has

changed. For change details, review the revision history included in any revised document.

TPS62140

TPS62140A

TPS62141

TPS62142

TPS62143

SLVSAJ0E –NOVEMBER 2011–REVISED SEPTEMBER 2016

www.ti.com

Product Folder Links: TPS62140 TPS62140A TPS62141 TPS62142 TPS62143

12.5 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

12.6 Trademarks

DCS-Control, E2E are trademarks of Texas Instruments.

All other trademarks are the property of their respective owners.

12.7 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

12.8 Glossary

SLYZ022 —TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

PACKAGE OPTION ADDENDUM

www.ti.com 11-Aug-2017

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

TPS62140ARGTR ACTIVE VQFN RGT 16 3000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PA7I

TPS62140ARGTT ACTIVE VQFN RGT 16 250 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PA7I

TPS62140RGTR ACTIVE VQFN RGT 16 3000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 QTZ

TPS62140RGTT ACTIVE VQFN RGT 16 250 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 QTZ

TPS62141RGTR ACTIVE VQFN RGT 16 3000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 QWA

TPS62141RGTT ACTIVE VQFN RGT 16 250 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 QWA

TPS62142RGTR ACTIVE VQFN RGT 16 3000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 QWB

TPS62142RGTT ACTIVE VQFN RGT 16 250 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 QWB

TPS62143RGTR ACTIVE VQFN RGT 16 3000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 QWC

TPS62143RGTT ACTIVE VQFN RGT 16 250 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 QWC

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

PACKAGE OPTION ADDENDUM

www.ti.com 11-Aug-2017

Addendum-Page 2

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

TPS62140ARGTR VQFN RGT 16 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2

TPS62140ARGTT VQFN RGT 16 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2

TPS62140RGTR VQFN RGT 16 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2

TPS62140RGTT VQFN RGT 16 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2

TPS62141RGTR VQFN RGT 16 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2

TPS62141RGTT VQFN RGT 16 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2

TPS62142RGTR VQFN RGT 16 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2

TPS62142RGTT VQFN RGT 16 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2

TPS62143RGTR VQFN RGT 16 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2

TPS62143RGTT VQFN RGT 16 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2

PACKAGE MATERIALS INFORMATION

www.ti.com 11-Aug-2017

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

TPS62140ARGTR VQFN RGT 16 3000 552.0 367.0 36.0

TPS62140ARGTT VQFN RGT 16 250 552.0 185.0 36.0

TPS62140RGTR VQFN RGT 16 3000 367.0 367.0 35.0

TPS62140RGTT VQFN RGT 16 250 210.0 185.0 35.0

TPS62141RGTR VQFN RGT 16 3000 367.0 367.0 35.0

TPS62141RGTT VQFN RGT 16 250 210.0 185.0 35.0

TPS62142RGTR VQFN RGT 16 3000 367.0 367.0 35.0

TPS62142RGTT VQFN RGT 16 250 210.0 185.0 35.0

TPS62143RGTR VQFN RGT 16 3000 367.0 367.0 35.0

TPS62143RGTT VQFN RGT 16 250 210.0 185.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 11-Aug-2017

Pack Materials-Page 2

www.ti.com

PACKAGE OUTLINE

16X 0.30

0.18

1.68 0.07

16X 0.5

0.3

1 MAX

(0.2) TYP

0.05

0.00

12X 0.5

1.5

A3.1

2.9 B

3.1

2.9

VQFN - 1 mm max heightRGT0016C

PLASTIC QUAD FLATPACK - NO LEAD

4222419/B 11/2016

PIN 1 INDEX AREA

0.08

SEATING PLANE

16 13

(OPTIONAL)

PIN 1 ID 0.1 C A B

0.05

EXPOSED

THERMAL PAD

SYMM

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

SCALE 3.600

www.ti.com

EXAMPLE BOARD LAYOUT

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

16X (0.24)

16X (0.6)

( 0.2) TYP

VIA

12X (0.5)

(2.8)

(0.58)

TYP

( 1.68)

(R0.05)

ALL PAD CORNERS (0.58) TYP

VQFN - 1 mm max heightRGT0016C

PLASTIC QUAD FLATPACK - NO LEAD

4222419/B 11/2016

SYMM

LAND PATTERN EXAMPLE

SCALE:20X

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

DEFINED

METAL

SOLDER MASK

OPENING

SOLDER MASK DETAILS

NON SOLDER MASK

DEFINED

(PREFERRED)

www.ti.com

EXAMPLE STENCIL DESIGN

16X (0.6)

16X (0.24)

12X (0.5)

(2.8)

( 1.55)

(R0.05) TYP

VQFN - 1 mm max heightRGT0016C

PLASTIC QUAD FLATPACK - NO LEAD

4222419/B 11/2016

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

SYMM

ALL AROUND

METAL

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 17:

85% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:25X

SYMM

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